motg.c revision 1.12.2.5
1 /* $NetBSD: motg.c,v 1.12.2.5 2014/12/02 09:00:33 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include "opt_motg.h" 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.12.2.5 2014/12/02 09:00:33 skrll Exp $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/kmem.h> 51 #include <sys/device.h> 52 #include <sys/select.h> 53 #include <sys/extent.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/bus.h> 57 #include <sys/cpu.h> 58 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #ifdef MOTG_ALLWINNER 68 #include <arch/arm/allwinner/awin_otgreg.h> 69 #else 70 #include <dev/usb/motgreg.h> 71 #endif 72 73 #include <dev/usb/motgvar.h> 74 #include <dev/usb/usbroothub_subr.h> 75 76 #define MOTG_DEBUG 77 #ifdef MOTG_DEBUG 78 #define DPRINTF(x) if (motgdebug) printf x 79 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 80 #define MD_ROOT 0x0002 81 #define MD_CTRL 0x0004 82 #define MD_BULK 0x0008 83 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 84 int motgdebug = 0; 85 #else 86 #define DPRINTF(x) 87 #define DPRINTFN(n,x) 88 #endif 89 90 /* various timeouts, for various speeds */ 91 /* control NAK timeouts */ 92 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 93 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 94 95 /* intr/iso polling intervals */ 96 #define POLL_TO 100 /* 100 frames, about 0.1s */ 97 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 98 99 /* bulk NAK timeouts */ 100 #define NAK_TO_BULK 0 /* disabled */ 101 #define NAK_TO_BULK_HIGH 0 102 103 static void motg_hub_change(struct motg_softc *); 104 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 105 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 106 static void motg_root_ctrl_abort(usbd_xfer_handle); 107 static void motg_root_ctrl_close(usbd_pipe_handle); 108 static void motg_root_ctrl_done(usbd_xfer_handle); 109 110 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 111 static usbd_status motg_root_intr_start(usbd_xfer_handle); 112 static void motg_root_intr_abort(usbd_xfer_handle); 113 static void motg_root_intr_close(usbd_pipe_handle); 114 static void motg_root_intr_done(usbd_xfer_handle); 115 116 static usbd_status motg_open(usbd_pipe_handle); 117 static void motg_poll(struct usbd_bus *); 118 static void motg_softintr(void *); 119 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 120 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 121 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 122 static void motg_noop(usbd_pipe_handle pipe); 123 static usbd_status motg_portreset(struct motg_softc*); 124 125 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 126 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 127 static void motg_device_ctrl_abort(usbd_xfer_handle); 128 static void motg_device_ctrl_close(usbd_pipe_handle); 129 static void motg_device_ctrl_done(usbd_xfer_handle); 130 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 131 static void motg_device_ctrl_read(usbd_xfer_handle); 132 static void motg_device_ctrl_intr_rx(struct motg_softc *); 133 static void motg_device_ctrl_intr_tx(struct motg_softc *); 134 135 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 136 static usbd_status motg_device_data_start(usbd_xfer_handle); 137 static usbd_status motg_device_data_start1(struct motg_softc *, 138 struct motg_hw_ep *); 139 static void motg_device_data_abort(usbd_xfer_handle); 140 static void motg_device_data_close(usbd_pipe_handle); 141 static void motg_device_data_done(usbd_xfer_handle); 142 static void motg_device_intr_rx(struct motg_softc *, int); 143 static void motg_device_intr_tx(struct motg_softc *, int); 144 static void motg_device_data_read(usbd_xfer_handle); 145 static void motg_device_data_write(usbd_xfer_handle); 146 147 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 148 static void motg_device_clear_toggle(usbd_pipe_handle); 149 static void motg_device_xfer_abort(usbd_xfer_handle); 150 151 #define MOTG_INTR_ENDPT 1 152 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 153 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 154 #define UWRITE1(sc, r, x) \ 155 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 156 } while (/*CONSTCOND*/0) 157 #define UWRITE2(sc, r, x) \ 158 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 159 } while (/*CONSTCOND*/0) 160 #define UWRITE4(sc, r, x) \ 161 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 162 } while (/*CONSTCOND*/0) 163 164 static __inline uint32_t 165 UREAD1(struct motg_softc *sc, bus_size_t r) 166 { 167 168 UBARR(sc); 169 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 170 } 171 static __inline uint32_t 172 UREAD2(struct motg_softc *sc, bus_size_t r) 173 { 174 175 UBARR(sc); 176 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 177 } 178 179 #if 0 180 static __inline uint32_t 181 UREAD4(struct motg_softc *sc, bus_size_t r) 182 { 183 184 UBARR(sc); 185 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 186 } 187 #endif 188 189 static void 190 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 191 { 192 uint8_t val; 193 194 val = UREAD1(sc, MUSB2_REG_POWER); 195 if (on) 196 val |= MUSB2_MASK_SOFTC; 197 else 198 val &= ~MUSB2_MASK_SOFTC; 199 200 UWRITE1(sc, MUSB2_REG_POWER, val); 201 } 202 203 const struct usbd_bus_methods motg_bus_methods = { 204 .ubm_open = motg_open, 205 .ubm_softint = motg_softintr, 206 .ubm_dopoll = motg_poll, 207 .ubm_allocx = motg_allocx, 208 .ubm_freex = motg_freex, 209 .ubm_getlock = motg_get_lock, 210 .ubm_newdev = NULL, 211 }; 212 213 const struct usbd_pipe_methods motg_root_ctrl_methods = { 214 .upm_transfer = motg_root_ctrl_transfer, 215 .upm_start = motg_root_ctrl_start, 216 .upm_abort = motg_root_ctrl_abort, 217 .upm_close = motg_root_ctrl_close, 218 .upm_cleartoggle = motg_noop, 219 .upm_done = motg_root_ctrl_done, 220 }; 221 222 const struct usbd_pipe_methods motg_root_intr_methods = { 223 .upm_transfer = motg_root_intr_transfer, 224 .upm_start = motg_root_intr_start, 225 .upm_abort = motg_root_intr_abort, 226 .upm_close = motg_root_intr_close, 227 .upm_cleartoggle = motg_noop, 228 .upm_done = motg_root_intr_done, 229 }; 230 231 const struct usbd_pipe_methods motg_device_ctrl_methods = { 232 .upm_transfer = motg_device_ctrl_transfer, 233 .upm_start = motg_device_ctrl_start, 234 .upm_abort = motg_device_ctrl_abort, 235 .upm_close = motg_device_ctrl_close, 236 .upm_cleartoggle = motg_noop, 237 .upm_done = motg_device_ctrl_done, 238 }; 239 240 const struct usbd_pipe_methods motg_device_data_methods = { 241 .upm_transfer = motg_device_data_transfer, 242 .upm_start = motg_device_data_start, 243 .upm_abort = motg_device_data_abort, 244 .upm_close = motg_device_data_close, 245 .upm_cleartoggle = motg_device_clear_toggle, 246 .upm_done = motg_device_data_done, 247 }; 248 249 usbd_status 250 motg_init(struct motg_softc *sc) 251 { 252 uint32_t nrx, ntx, val; 253 int dynfifo; 254 int offset, i; 255 256 if (sc->sc_mode == MOTG_MODE_DEVICE) 257 return USBD_NORMAL_COMPLETION; /* not supported */ 258 259 /* disable all interrupts */ 260 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 261 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 262 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 263 /* disable pullup */ 264 265 musbotg_pull_common(sc, 0); 266 267 #ifdef MUSB2_REG_RXDBDIS 268 /* disable double packet buffering XXX what's this ? */ 269 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 270 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 271 #endif 272 273 /* enable HighSpeed and ISO Update flags */ 274 275 UWRITE1(sc, MUSB2_REG_POWER, 276 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 277 278 if (sc->sc_mode == MOTG_MODE_DEVICE) { 279 /* clear Session bit, if set */ 280 val = UREAD1(sc, MUSB2_REG_DEVCTL); 281 val &= ~MUSB2_MASK_SESS; 282 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 283 } else { 284 /* Enter session for Host mode */ 285 val = UREAD1(sc, MUSB2_REG_DEVCTL); 286 val |= MUSB2_MASK_SESS; 287 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 288 } 289 delay(1000); 290 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 291 292 /* disable testmode */ 293 294 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 295 296 #ifdef MUSB2_REG_MISC 297 /* set default value */ 298 299 UWRITE1(sc, MUSB2_REG_MISC, 0); 300 #endif 301 302 /* select endpoint index 0 */ 303 304 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 305 306 if (sc->sc_ep_max == 0) { 307 /* read out number of endpoints */ 308 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 309 310 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 311 312 /* these numbers exclude the control endpoint */ 313 314 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 315 316 sc->sc_ep_max = MAX(nrx, ntx); 317 } else { 318 nrx = ntx = sc->sc_ep_max; 319 } 320 if (sc->sc_ep_max == 0) { 321 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 322 return USBD_INVAL; 323 } 324 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 325 /* read out configuration data */ 326 val = UREAD1(sc, MUSB2_REG_CONFDATA); 327 328 DPRINTF(("Config Data: 0x%02x\n", val)); 329 330 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 331 332 if (dynfifo) { 333 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 334 "assuming 16Kbytes of FIFO RAM\n"); 335 } 336 337 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 338 339 /* initialise endpoint profiles */ 340 sc->sc_in_ep[0].ep_fifo_size = 64; 341 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 342 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 343 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 344 offset = 64; 345 346 for (i = 1; i <= sc->sc_ep_max; i++) { 347 int fiforx_size, fifotx_size, fifo_size; 348 349 /* select endpoint */ 350 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 351 352 if (sc->sc_ep_fifosize) { 353 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 354 } else { 355 val = UREAD1(sc, MUSB2_REG_FSIZE); 356 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 357 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 358 } 359 360 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 361 i, fifotx_size, fiforx_size, dynfifo)); 362 363 if (dynfifo) { 364 if (sc->sc_ep_fifosize) { 365 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 366 } else { 367 if (i < 3) { 368 fifo_size = 12; /* 4K */ 369 } else if (i < 10) { 370 fifo_size = 10; /* 1K */ 371 } else { 372 fifo_size = 7; /* 128 bytes */ 373 } 374 } 375 if (fiforx_size && (i <= nrx)) { 376 fiforx_size = fifo_size; 377 if (fifo_size > 7) { 378 #if 0 379 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 380 MUSB2_VAL_FIFOSZ(fifo_size) | 381 MUSB2_MASK_FIFODB); 382 #else 383 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 384 MUSB2_VAL_FIFOSZ(fifo_size)); 385 #endif 386 } else { 387 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 388 MUSB2_VAL_FIFOSZ(fifo_size)); 389 } 390 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 391 offset >> 3); 392 offset += (1 << fiforx_size); 393 } 394 if (fifotx_size && (i <= ntx)) { 395 fifotx_size = fifo_size; 396 if (fifo_size > 7) { 397 #if 0 398 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 399 MUSB2_VAL_FIFOSZ(fifo_size) | 400 MUSB2_MASK_FIFODB); 401 #else 402 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size)); 404 #endif 405 } else { 406 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size)); 408 } 409 410 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 411 offset >> 3); 412 413 offset += (1 << fifotx_size); 414 } 415 } 416 if (fiforx_size && (i <= nrx)) { 417 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 418 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 419 } 420 if (fifotx_size && (i <= ntx)) { 421 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 422 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 423 } 424 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 425 } 426 427 428 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 429 430 /* turn on default interrupts */ 431 432 if (sc->sc_mode == MOTG_MODE_HOST) { 433 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 434 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 435 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 436 } else 437 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 438 439 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 440 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 441 442 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 443 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 444 445 /* Set up the bus struct. */ 446 sc->sc_bus.methods = &motg_bus_methods; 447 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 448 sc->sc_bus.usbrev = USBREV_2_0; 449 sc->sc_bus.hci_private = sc; 450 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 451 "Mentor Graphics"); 452 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 453 return USBD_NORMAL_COMPLETION; 454 } 455 456 static int 457 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 458 { 459 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 460 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 461 struct motg_hw_ep *ep; 462 int i, size; 463 464 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 465 sc->sc_in_ep : sc->sc_out_ep; 466 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 467 468 for (i = sc->sc_ep_max; i >= 1; i--) { 469 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 470 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 471 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 472 if (ep[i].ep_fifo_size >= size) { 473 /* found a suitable endpoint */ 474 otgpipe->hw_ep = &ep[i]; 475 mutex_enter(&sc->sc_lock); 476 if (otgpipe->hw_ep->refcount > 0) { 477 /* no luck, try next */ 478 mutex_exit(&sc->sc_lock); 479 otgpipe->hw_ep = NULL; 480 } else { 481 otgpipe->hw_ep->refcount++; 482 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 483 otgpipe, ep_pipe_list); 484 mutex_exit(&sc->sc_lock); 485 return 0; 486 } 487 } 488 } 489 return -1; 490 } 491 492 /* Open a new pipe. */ 493 usbd_status 494 motg_open(usbd_pipe_handle pipe) 495 { 496 struct motg_softc *sc = pipe->device->bus->hci_private; 497 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 498 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 499 500 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 501 pipe, pipe->device->address, 502 ed->bEndpointAddress, sc->sc_root_addr)); 503 504 if (sc->sc_dying) 505 return USBD_IOERROR; 506 507 /* toggle state needed for bulk endpoints */ 508 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 509 510 if (pipe->device->address == sc->sc_root_addr) { 511 switch (ed->bEndpointAddress) { 512 case USB_CONTROL_ENDPOINT: 513 pipe->methods = &motg_root_ctrl_methods; 514 break; 515 case UE_DIR_IN | MOTG_INTR_ENDPT: 516 pipe->methods = &motg_root_intr_methods; 517 break; 518 default: 519 return (USBD_INVAL); 520 } 521 } else { 522 switch (ed->bmAttributes & UE_XFERTYPE) { 523 case UE_CONTROL: 524 pipe->methods = &motg_device_ctrl_methods; 525 /* always use sc_in_ep[0] for in and out */ 526 otgpipe->hw_ep = &sc->sc_in_ep[0]; 527 mutex_enter(&sc->sc_lock); 528 otgpipe->hw_ep->refcount++; 529 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 530 otgpipe, ep_pipe_list); 531 mutex_exit(&sc->sc_lock); 532 break; 533 case UE_BULK: 534 case UE_INTERRUPT: 535 DPRINTFN(MD_BULK, 536 ("new %s %s pipe wMaxPacketSize %d\n", 537 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 538 "bulk" : "interrupt", 539 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 540 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 541 if (motg_select_ep(sc, pipe) != 0) 542 goto bad; 543 KASSERT(otgpipe->hw_ep != NULL); 544 pipe->methods = &motg_device_data_methods; 545 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 546 break; 547 default: 548 goto bad; 549 #ifdef notyet 550 case UE_ISOCHRONOUS: 551 ... 552 break; 553 #endif /* notyet */ 554 } 555 } 556 return (USBD_NORMAL_COMPLETION); 557 558 bad: 559 return (USBD_NOMEM); 560 } 561 562 void 563 motg_softintr(void *v) 564 { 565 struct usbd_bus *bus = v; 566 struct motg_softc *sc = bus->hci_private; 567 uint16_t rx_status, tx_status; 568 uint8_t ctrl_status; 569 uint32_t val; 570 int i; 571 572 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 573 574 DPRINTFN(MD_ROOT | MD_CTRL, 575 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 576 577 mutex_spin_enter(&sc->sc_intr_lock); 578 rx_status = sc->sc_intr_rx_ep; 579 sc->sc_intr_rx_ep = 0; 580 tx_status = sc->sc_intr_tx_ep; 581 sc->sc_intr_tx_ep = 0; 582 ctrl_status = sc->sc_intr_ctrl; 583 sc->sc_intr_ctrl = 0; 584 mutex_spin_exit(&sc->sc_intr_lock); 585 586 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 587 588 if (ctrl_status & (MUSB2_MASK_IRESET | 589 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 590 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 591 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 592 ctrl_status)); 593 594 if (ctrl_status & MUSB2_MASK_IRESET) { 595 sc->sc_isreset = 1; 596 sc->sc_port_suspended = 0; 597 sc->sc_port_suspended_change = 1; 598 sc->sc_connected_changed = 1; 599 sc->sc_port_enabled = 1; 600 601 val = UREAD1(sc, MUSB2_REG_POWER); 602 if (val & MUSB2_MASK_HSMODE) 603 sc->sc_high_speed = 1; 604 else 605 sc->sc_high_speed = 0; 606 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 607 sc->sc_high_speed)); 608 609 /* turn off interrupts */ 610 val = MUSB2_MASK_IRESET; 611 val &= ~MUSB2_MASK_IRESUME; 612 val |= MUSB2_MASK_ISUSP; 613 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 614 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 615 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 616 } 617 if (ctrl_status & MUSB2_MASK_IRESUME) { 618 if (sc->sc_port_suspended) { 619 sc->sc_port_suspended = 0; 620 sc->sc_port_suspended_change = 1; 621 val = UREAD1(sc, MUSB2_REG_INTUSBE); 622 /* disable resume interrupt */ 623 val &= ~MUSB2_MASK_IRESUME; 624 /* enable suspend interrupt */ 625 val |= MUSB2_MASK_ISUSP; 626 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 627 } 628 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 629 if (!sc->sc_port_suspended) { 630 sc->sc_port_suspended = 1; 631 sc->sc_port_suspended_change = 1; 632 633 val = UREAD1(sc, MUSB2_REG_INTUSBE); 634 /* disable suspend interrupt */ 635 val &= ~MUSB2_MASK_ISUSP; 636 /* enable resume interrupt */ 637 val |= MUSB2_MASK_IRESUME; 638 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 639 } 640 } 641 if (ctrl_status & MUSB2_MASK_ICONN) { 642 sc->sc_connected = 1; 643 sc->sc_connected_changed = 1; 644 sc->sc_isreset = 1; 645 sc->sc_port_enabled = 1; 646 } else if (ctrl_status & MUSB2_MASK_IDISC) { 647 sc->sc_connected = 0; 648 sc->sc_connected_changed = 1; 649 sc->sc_isreset = 0; 650 sc->sc_port_enabled = 0; 651 } 652 653 /* complete root HUB interrupt endpoint */ 654 655 motg_hub_change(sc); 656 } 657 /* 658 * read in interrupt status and mix with the status we 659 * got from the wrapper 660 */ 661 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 662 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 663 664 if (rx_status & 0x01) 665 panic("ctrl_rx %08x", rx_status); 666 if (tx_status & 0x01) 667 motg_device_ctrl_intr_tx(sc); 668 for (i = 1; i <= sc->sc_ep_max; i++) { 669 if (rx_status & (0x01 << i)) 670 motg_device_intr_rx(sc, i); 671 if (tx_status & (0x01 << i)) 672 motg_device_intr_tx(sc, i); 673 } 674 return; 675 } 676 677 void 678 motg_poll(struct usbd_bus *bus) 679 { 680 struct motg_softc *sc = bus->hci_private; 681 682 sc->sc_intr_poll(sc->sc_intr_poll_arg); 683 mutex_enter(&sc->sc_lock); 684 motg_softintr(bus); 685 mutex_exit(&sc->sc_lock); 686 } 687 688 int 689 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 690 uint8_t ctrl) 691 { 692 KASSERT(mutex_owned(&sc->sc_intr_lock)); 693 sc->sc_intr_tx_ep = tx_ep; 694 sc->sc_intr_rx_ep = rx_ep; 695 sc->sc_intr_ctrl = ctrl; 696 697 if (!sc->sc_bus.use_polling) { 698 usb_schedsoftintr(&sc->sc_bus); 699 } 700 return 1; 701 } 702 703 int 704 motg_intr_vbus(struct motg_softc *sc, int vbus) 705 { 706 uint8_t val; 707 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 708 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 709 /* try to re-enter session for Host mode */ 710 val = UREAD1(sc, MUSB2_REG_DEVCTL); 711 val |= MUSB2_MASK_SESS; 712 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 713 } 714 return 1; 715 } 716 717 usbd_xfer_handle 718 motg_allocx(struct usbd_bus *bus) 719 { 720 struct motg_softc *sc = bus->hci_private; 721 usbd_xfer_handle xfer; 722 723 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 724 if (xfer != NULL) { 725 memset(xfer, 0, sizeof(struct motg_xfer)); 726 UXFER(xfer)->sc = sc; 727 #ifdef DIAGNOSTIC 728 // XXX UXFER(xfer)->iinfo.isdone = 1; 729 xfer->busy_free = XFER_BUSY; 730 #endif 731 } 732 return (xfer); 733 } 734 735 void 736 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 737 { 738 struct motg_softc *sc = bus->hci_private; 739 740 #ifdef DIAGNOSTIC 741 if (xfer->busy_free != XFER_BUSY) { 742 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 743 xfer->busy_free); 744 } 745 xfer->busy_free = XFER_FREE; 746 #endif 747 pool_cache_put(sc->sc_xferpool, xfer); 748 } 749 750 static void 751 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 752 { 753 struct motg_softc *sc = bus->hci_private; 754 755 *lock = &sc->sc_lock; 756 } 757 758 /* 759 * Data structures and routines to emulate the root hub. 760 */ 761 usb_device_descriptor_t motg_devd = { 762 USB_DEVICE_DESCRIPTOR_SIZE, 763 UDESC_DEVICE, /* type */ 764 {0x00, 0x01}, /* USB version */ 765 UDCLASS_HUB, /* class */ 766 UDSUBCLASS_HUB, /* subclass */ 767 UDPROTO_FSHUB, /* protocol */ 768 64, /* max packet */ 769 {0},{0},{0x00,0x01}, /* device id */ 770 1,2,0, /* string indicies */ 771 1 /* # of configurations */ 772 }; 773 774 const usb_config_descriptor_t motg_confd = { 775 USB_CONFIG_DESCRIPTOR_SIZE, 776 UDESC_CONFIG, 777 {USB_CONFIG_DESCRIPTOR_SIZE + 778 USB_INTERFACE_DESCRIPTOR_SIZE + 779 USB_ENDPOINT_DESCRIPTOR_SIZE}, 780 1, 781 1, 782 0, 783 UC_ATTR_MBO | UC_SELF_POWERED, 784 0 /* max power */ 785 }; 786 787 const usb_interface_descriptor_t motg_ifcd = { 788 USB_INTERFACE_DESCRIPTOR_SIZE, 789 UDESC_INTERFACE, 790 0, 791 0, 792 1, 793 UICLASS_HUB, 794 UISUBCLASS_HUB, 795 UIPROTO_FSHUB, 796 0 797 }; 798 799 const usb_endpoint_descriptor_t motg_endpd = { 800 USB_ENDPOINT_DESCRIPTOR_SIZE, 801 UDESC_ENDPOINT, 802 UE_DIR_IN | MOTG_INTR_ENDPT, 803 UE_INTERRUPT, 804 {8}, 805 255 806 }; 807 808 const usb_hub_descriptor_t motg_hubd = { 809 USB_HUB_DESCRIPTOR_SIZE, 810 UDESC_HUB, 811 1, 812 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 813 50, /* power on to power good */ 814 0, 815 { 0x00 }, /* port is removable */ 816 { 0 }, 817 }; 818 819 /* 820 * Simulate a hardware hub by handling all the necessary requests. 821 */ 822 usbd_status 823 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 824 { 825 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 826 usbd_status err; 827 828 /* Insert last in queue. */ 829 mutex_enter(&sc->sc_lock); 830 err = usb_insert_transfer(xfer); 831 mutex_exit(&sc->sc_lock); 832 if (err) 833 return (err); 834 835 /* 836 * Pipe isn't running (otherwise err would be USBD_INPROG), 837 * so start it first. 838 */ 839 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 840 } 841 842 usbd_status 843 motg_root_ctrl_start(usbd_xfer_handle xfer) 844 { 845 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 846 usb_device_request_t *req; 847 void *buf = NULL; 848 int len, value, index, status, change, l, totlen = 0; 849 usb_port_status_t ps; 850 usbd_status err; 851 uint32_t val; 852 853 if (sc->sc_dying) 854 return (USBD_IOERROR); 855 856 #ifdef DIAGNOSTIC 857 if (!(xfer->rqflags & URQ_REQUEST)) 858 panic("motg_root_ctrl_start: not a request"); 859 #endif 860 req = &xfer->request; 861 862 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 863 req->bmRequestType, req->bRequest)); 864 865 len = UGETW(req->wLength); 866 value = UGETW(req->wValue); 867 index = UGETW(req->wIndex); 868 869 if (len != 0) 870 buf = xfer->buf; 871 872 #define C(x,y) ((x) | ((y) << 8)) 873 switch(C(req->bRequest, req->bmRequestType)) { 874 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 875 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 876 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 877 /* 878 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 879 * for the integrated root hub. 880 */ 881 break; 882 case C(UR_GET_CONFIG, UT_READ_DEVICE): 883 if (len > 0) { 884 *(uint8_t *)buf = sc->sc_root_conf; 885 totlen = 1; 886 } 887 break; 888 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 889 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 890 if (len == 0) 891 break; 892 switch(value >> 8) { 893 case UDESC_DEVICE: 894 if ((value & 0xff) != 0) { 895 err = USBD_IOERROR; 896 goto ret; 897 } 898 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 899 USETW(motg_devd.idVendor, sc->sc_id_vendor); 900 memcpy(buf, &motg_devd, l); 901 break; 902 case UDESC_CONFIG: 903 if ((value & 0xff) != 0) { 904 err = USBD_IOERROR; 905 goto ret; 906 } 907 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 908 memcpy(buf, &motg_confd, l); 909 buf = (char *)buf + l; 910 len -= l; 911 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 912 totlen += l; 913 memcpy(buf, &motg_ifcd, l); 914 buf = (char *)buf + l; 915 len -= l; 916 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 917 totlen += l; 918 memcpy(buf, &motg_endpd, l); 919 break; 920 case UDESC_STRING: 921 #define sd ((usb_string_descriptor_t *)buf) 922 switch (value & 0xff) { 923 case 0: /* Language table */ 924 totlen = usb_makelangtbl(sd, len); 925 break; 926 case 1: /* Vendor */ 927 totlen = usb_makestrdesc(sd, len, 928 sc->sc_vendor); 929 break; 930 case 2: /* Product */ 931 totlen = usb_makestrdesc(sd, len, 932 "MOTG root hub"); 933 break; 934 } 935 #undef sd 936 break; 937 default: 938 err = USBD_IOERROR; 939 goto ret; 940 } 941 break; 942 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 943 if (len > 0) { 944 *(uint8_t *)buf = 0; 945 totlen = 1; 946 } 947 break; 948 case C(UR_GET_STATUS, UT_READ_DEVICE): 949 if (len > 1) { 950 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 951 totlen = 2; 952 } 953 break; 954 case C(UR_GET_STATUS, UT_READ_INTERFACE): 955 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 956 if (len > 1) { 957 USETW(((usb_status_t *)buf)->wStatus, 0); 958 totlen = 2; 959 } 960 break; 961 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 962 if (value >= USB_MAX_DEVICES) { 963 err = USBD_IOERROR; 964 goto ret; 965 } 966 sc->sc_root_addr = value; 967 break; 968 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 969 if (value != 0 && value != 1) { 970 err = USBD_IOERROR; 971 goto ret; 972 } 973 sc->sc_root_conf = value; 974 break; 975 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 976 break; 977 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 978 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 979 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 980 err = USBD_IOERROR; 981 goto ret; 982 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 983 break; 984 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 985 break; 986 /* Hub requests */ 987 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 988 break; 989 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 990 DPRINTFN(MD_ROOT, 991 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 992 "port=%d feature=%d\n", 993 index, value)); 994 if (index != 1) { 995 err = USBD_IOERROR; 996 goto ret; 997 } 998 switch(value) { 999 case UHF_PORT_ENABLE: 1000 sc->sc_port_enabled = 0; 1001 break; 1002 case UHF_PORT_SUSPEND: 1003 if (sc->sc_port_suspended != 0) { 1004 val = UREAD1(sc, MUSB2_REG_POWER); 1005 val &= ~MUSB2_MASK_SUSPMODE; 1006 val |= MUSB2_MASK_RESUME; 1007 UWRITE1(sc, MUSB2_REG_POWER, val); 1008 /* wait 20 milliseconds */ 1009 usb_delay_ms(&sc->sc_bus, 20); 1010 val = UREAD1(sc, MUSB2_REG_POWER); 1011 val &= ~MUSB2_MASK_RESUME; 1012 UWRITE1(sc, MUSB2_REG_POWER, val); 1013 sc->sc_port_suspended = 0; 1014 sc->sc_port_suspended_change = 1; 1015 } 1016 break; 1017 case UHF_PORT_RESET: 1018 break; 1019 case UHF_C_PORT_CONNECTION: 1020 break; 1021 case UHF_C_PORT_ENABLE: 1022 break; 1023 case UHF_C_PORT_OVER_CURRENT: 1024 break; 1025 case UHF_C_PORT_RESET: 1026 sc->sc_isreset = 0; 1027 err = USBD_NORMAL_COMPLETION; 1028 goto ret; 1029 case UHF_PORT_POWER: 1030 /* XXX todo */ 1031 break; 1032 case UHF_PORT_CONNECTION: 1033 case UHF_PORT_OVER_CURRENT: 1034 case UHF_PORT_LOW_SPEED: 1035 case UHF_C_PORT_SUSPEND: 1036 default: 1037 err = USBD_IOERROR; 1038 goto ret; 1039 } 1040 break; 1041 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1042 err = USBD_IOERROR; 1043 goto ret; 1044 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1045 if (len == 0) 1046 break; 1047 if ((value & 0xff) != 0) { 1048 err = USBD_IOERROR; 1049 goto ret; 1050 } 1051 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1052 totlen = l; 1053 memcpy(buf, &motg_hubd, l); 1054 break; 1055 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1056 if (len != 4) { 1057 err = USBD_IOERROR; 1058 goto ret; 1059 } 1060 memset(buf, 0, len); 1061 totlen = len; 1062 break; 1063 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1064 if (index != 1) { 1065 err = USBD_IOERROR; 1066 goto ret; 1067 } 1068 if (len != 4) { 1069 err = USBD_IOERROR; 1070 goto ret; 1071 } 1072 status = change = 0; 1073 if (sc->sc_connected) 1074 status |= UPS_CURRENT_CONNECT_STATUS; 1075 if (sc->sc_connected_changed) { 1076 change |= UPS_C_CONNECT_STATUS; 1077 sc->sc_connected_changed = 0; 1078 } 1079 if (sc->sc_port_enabled) 1080 status |= UPS_PORT_ENABLED; 1081 if (sc->sc_port_enabled_changed) { 1082 change |= UPS_C_PORT_ENABLED; 1083 sc->sc_port_enabled_changed = 0; 1084 } 1085 if (sc->sc_port_suspended) 1086 status |= UPS_SUSPEND; 1087 if (sc->sc_high_speed) 1088 status |= UPS_HIGH_SPEED; 1089 status |= UPS_PORT_POWER; /* XXX */ 1090 if (sc->sc_isreset) 1091 change |= UPS_C_PORT_RESET; 1092 USETW(ps.wPortStatus, status); 1093 USETW(ps.wPortChange, change); 1094 l = min(len, sizeof ps); 1095 memcpy(buf, &ps, l); 1096 totlen = l; 1097 break; 1098 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1099 err = USBD_IOERROR; 1100 goto ret; 1101 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1102 break; 1103 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1104 if (index != 1) { 1105 err = USBD_IOERROR; 1106 goto ret; 1107 } 1108 switch(value) { 1109 case UHF_PORT_ENABLE: 1110 sc->sc_port_enabled = 1; 1111 break; 1112 case UHF_PORT_SUSPEND: 1113 if (sc->sc_port_suspended == 0) { 1114 val = UREAD1(sc, MUSB2_REG_POWER); 1115 val |= MUSB2_MASK_SUSPMODE; 1116 UWRITE1(sc, MUSB2_REG_POWER, val); 1117 /* wait 20 milliseconds */ 1118 usb_delay_ms(&sc->sc_bus, 20); 1119 sc->sc_port_suspended = 1; 1120 sc->sc_port_suspended_change = 1; 1121 } 1122 break; 1123 case UHF_PORT_RESET: 1124 err = motg_portreset(sc); 1125 goto ret; 1126 case UHF_PORT_POWER: 1127 /* XXX todo */ 1128 err = USBD_NORMAL_COMPLETION; 1129 goto ret; 1130 case UHF_C_PORT_CONNECTION: 1131 case UHF_C_PORT_ENABLE: 1132 case UHF_C_PORT_OVER_CURRENT: 1133 case UHF_PORT_CONNECTION: 1134 case UHF_PORT_OVER_CURRENT: 1135 case UHF_PORT_LOW_SPEED: 1136 case UHF_C_PORT_SUSPEND: 1137 case UHF_C_PORT_RESET: 1138 default: 1139 err = USBD_IOERROR; 1140 goto ret; 1141 } 1142 break; 1143 default: 1144 err = USBD_IOERROR; 1145 goto ret; 1146 } 1147 xfer->actlen = totlen; 1148 err = USBD_NORMAL_COMPLETION; 1149 ret: 1150 xfer->status = err; 1151 mutex_enter(&sc->sc_lock); 1152 usb_transfer_complete(xfer); 1153 mutex_exit(&sc->sc_lock); 1154 return (USBD_IN_PROGRESS); 1155 } 1156 1157 /* Abort a root control request. */ 1158 void 1159 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1160 { 1161 /* Nothing to do, all transfers are synchronous. */ 1162 } 1163 1164 /* Close the root pipe. */ 1165 void 1166 motg_root_ctrl_close(usbd_pipe_handle pipe) 1167 { 1168 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1169 } 1170 1171 void 1172 motg_root_ctrl_done(usbd_xfer_handle xfer) 1173 { 1174 } 1175 1176 /* Abort a root interrupt request. */ 1177 void 1178 motg_root_intr_abort(usbd_xfer_handle xfer) 1179 { 1180 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1181 1182 KASSERT(mutex_owned(&sc->sc_lock)); 1183 KASSERT(xfer->pipe->intrxfer == xfer); 1184 1185 sc->sc_intr_xfer = NULL; 1186 1187 #ifdef DIAGNOSTIC 1188 // XXX UXFER(xfer)->iinfo.isdone = 1; 1189 #endif 1190 xfer->status = USBD_CANCELLED; 1191 usb_transfer_complete(xfer); 1192 } 1193 1194 usbd_status 1195 motg_root_intr_transfer(usbd_xfer_handle xfer) 1196 { 1197 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1198 usbd_status err; 1199 1200 /* Insert last in queue. */ 1201 mutex_enter(&sc->sc_lock); 1202 err = usb_insert_transfer(xfer); 1203 mutex_exit(&sc->sc_lock); 1204 if (err) 1205 return (err); 1206 1207 /* 1208 * Pipe isn't running (otherwise err would be USBD_INPROG), 1209 * start first 1210 */ 1211 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1212 } 1213 1214 /* Start a transfer on the root interrupt pipe */ 1215 usbd_status 1216 motg_root_intr_start(usbd_xfer_handle xfer) 1217 { 1218 usbd_pipe_handle pipe = xfer->pipe; 1219 struct motg_softc *sc = pipe->device->bus->hci_private; 1220 1221 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1222 xfer, xfer->length, xfer->flags)); 1223 1224 if (sc->sc_dying) 1225 return (USBD_IOERROR); 1226 1227 sc->sc_intr_xfer = xfer; 1228 return (USBD_IN_PROGRESS); 1229 } 1230 1231 /* Close the root interrupt pipe. */ 1232 void 1233 motg_root_intr_close(usbd_pipe_handle pipe) 1234 { 1235 struct motg_softc *sc = pipe->device->bus->hci_private; 1236 1237 KASSERT(mutex_owned(&sc->sc_lock)); 1238 1239 sc->sc_intr_xfer = NULL; 1240 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1241 } 1242 1243 void 1244 motg_root_intr_done(usbd_xfer_handle xfer) 1245 { 1246 } 1247 1248 void 1249 motg_noop(usbd_pipe_handle pipe) 1250 { 1251 } 1252 1253 static usbd_status 1254 motg_portreset(struct motg_softc *sc) 1255 { 1256 uint32_t val; 1257 1258 val = UREAD1(sc, MUSB2_REG_POWER); 1259 val |= MUSB2_MASK_RESET; 1260 UWRITE1(sc, MUSB2_REG_POWER, val); 1261 /* Wait for 20 msec */ 1262 usb_delay_ms(&sc->sc_bus, 20); 1263 1264 val = UREAD1(sc, MUSB2_REG_POWER); 1265 val &= ~MUSB2_MASK_RESET; 1266 UWRITE1(sc, MUSB2_REG_POWER, val); 1267 1268 /* determine line speed */ 1269 val = UREAD1(sc, MUSB2_REG_POWER); 1270 if (val & MUSB2_MASK_HSMODE) 1271 sc->sc_high_speed = 1; 1272 else 1273 sc->sc_high_speed = 0; 1274 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1275 sc->sc_high_speed)); 1276 1277 sc->sc_isreset = 1; 1278 sc->sc_port_enabled = 1; 1279 return (USBD_NORMAL_COMPLETION); 1280 } 1281 1282 /* 1283 * This routine is executed when an interrupt on the root hub is detected 1284 */ 1285 static void 1286 motg_hub_change(struct motg_softc *sc) 1287 { 1288 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1289 usbd_pipe_handle pipe; 1290 u_char *p; 1291 1292 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1293 1294 if (xfer == NULL) 1295 return; /* the interrupt pipe is not open */ 1296 1297 pipe = xfer->pipe; 1298 if (pipe->device == NULL || pipe->device->bus == NULL) 1299 return; /* device has detached */ 1300 1301 p = xfer->buf; 1302 p[0] = 1<<1; 1303 xfer->actlen = 1; 1304 xfer->status = USBD_NORMAL_COMPLETION; 1305 usb_transfer_complete(xfer); 1306 } 1307 1308 static uint8_t 1309 motg_speed(uint8_t speed) 1310 { 1311 switch(speed) { 1312 case USB_SPEED_LOW: 1313 return MUSB2_MASK_TI_SPEED_LO; 1314 case USB_SPEED_FULL: 1315 return MUSB2_MASK_TI_SPEED_FS; 1316 case USB_SPEED_HIGH: 1317 return MUSB2_MASK_TI_SPEED_HS; 1318 default: 1319 panic("motg: unknown speed %d", speed); 1320 /* NOTREACHED */ 1321 } 1322 } 1323 1324 static uint8_t 1325 motg_type(uint8_t type) 1326 { 1327 switch(type) { 1328 case UE_CONTROL: 1329 return MUSB2_MASK_TI_PROTO_CTRL; 1330 case UE_ISOCHRONOUS: 1331 return MUSB2_MASK_TI_PROTO_ISOC; 1332 case UE_BULK: 1333 return MUSB2_MASK_TI_PROTO_BULK; 1334 case UE_INTERRUPT: 1335 return MUSB2_MASK_TI_PROTO_INTR; 1336 default: 1337 panic("motg: unknown type %d", type); 1338 /* NOTREACHED */ 1339 } 1340 } 1341 1342 static void 1343 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1344 { 1345 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1346 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1347 usbd_device_handle dev = otgpipe->pipe.device; 1348 int epnumber = otgpipe->hw_ep->ep_number; 1349 1350 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1351 if (dev->myhsport) { 1352 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1353 dev->myhsport->parent->address); 1354 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1355 dev->myhsport->portno); 1356 } else { 1357 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1358 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1359 } 1360 UWRITE1(sc, MUSB2_REG_TXTI, 1361 motg_speed(dev->speed) | 1362 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1363 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1364 ); 1365 if (epnumber == 0) { 1366 if (sc->sc_high_speed) { 1367 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1368 NAK_TO_CTRL_HIGH); 1369 } else { 1370 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1371 } 1372 } else { 1373 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1374 == UE_BULK) { 1375 if (sc->sc_high_speed) { 1376 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1377 NAK_TO_BULK_HIGH); 1378 } else { 1379 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1380 } 1381 } else { 1382 if (sc->sc_high_speed) { 1383 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1384 } else { 1385 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1386 } 1387 } 1388 } 1389 } 1390 1391 static void 1392 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1393 { 1394 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1395 usbd_device_handle dev = xfer->pipe->device; 1396 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1397 int epnumber = otgpipe->hw_ep->ep_number; 1398 1399 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1400 if (dev->myhsport) { 1401 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1402 dev->myhsport->parent->address); 1403 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1404 dev->myhsport->portno); 1405 } else { 1406 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1407 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1408 } 1409 UWRITE1(sc, MUSB2_REG_RXTI, 1410 motg_speed(dev->speed) | 1411 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1412 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1413 ); 1414 if (epnumber == 0) { 1415 if (sc->sc_high_speed) { 1416 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1417 NAK_TO_CTRL_HIGH); 1418 } else { 1419 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1420 } 1421 } else { 1422 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1423 == UE_BULK) { 1424 if (sc->sc_high_speed) { 1425 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1426 NAK_TO_BULK_HIGH); 1427 } else { 1428 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1429 } 1430 } else { 1431 if (sc->sc_high_speed) { 1432 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1433 } else { 1434 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1435 } 1436 } 1437 } 1438 } 1439 1440 static usbd_status 1441 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1442 { 1443 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1444 usbd_status err; 1445 1446 /* Insert last in queue. */ 1447 mutex_enter(&sc->sc_lock); 1448 err = usb_insert_transfer(xfer); 1449 xfer->status = USBD_NOT_STARTED; 1450 mutex_exit(&sc->sc_lock); 1451 if (err) 1452 return (err); 1453 1454 /* 1455 * Pipe isn't running (otherwise err would be USBD_INPROG), 1456 * so start it first. 1457 */ 1458 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1459 } 1460 1461 static usbd_status 1462 motg_device_ctrl_start(usbd_xfer_handle xfer) 1463 { 1464 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1465 usbd_status err; 1466 mutex_enter(&sc->sc_lock); 1467 err = motg_device_ctrl_start1(sc); 1468 mutex_exit(&sc->sc_lock); 1469 if (err != USBD_IN_PROGRESS) 1470 return err; 1471 if (sc->sc_bus.use_polling) 1472 motg_waitintr(sc, xfer); 1473 return USBD_IN_PROGRESS; 1474 } 1475 1476 static usbd_status 1477 motg_device_ctrl_start1(struct motg_softc *sc) 1478 { 1479 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1480 usbd_xfer_handle xfer = NULL; 1481 struct motg_pipe *otgpipe; 1482 usbd_status err = 0; 1483 1484 KASSERT(mutex_owned(&sc->sc_lock)); 1485 if (sc->sc_dying) 1486 return (USBD_IOERROR); 1487 1488 if (!sc->sc_connected) 1489 return (USBD_IOERROR); 1490 1491 if (ep->xfer != NULL) { 1492 err = USBD_IN_PROGRESS; 1493 goto end; 1494 } 1495 /* locate the first pipe with work to do */ 1496 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1497 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1498 DPRINTFN(MD_CTRL, 1499 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1500 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1501 1502 if (xfer != NULL) { 1503 /* move this pipe to the end of the list */ 1504 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1505 motg_pipe, ep_pipe_list); 1506 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1507 otgpipe, ep_pipe_list); 1508 break; 1509 } 1510 } 1511 if (xfer == NULL) { 1512 err = USBD_NOT_STARTED; 1513 goto end; 1514 } 1515 xfer->status = USBD_IN_PROGRESS; 1516 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1517 KASSERT(otgpipe->hw_ep == ep); 1518 #ifdef DIAGNOSTIC 1519 if (!(xfer->rqflags & URQ_REQUEST)) 1520 panic("motg_device_ctrl_transfer: not a request"); 1521 #endif 1522 // KASSERT(xfer->actlen == 0); 1523 xfer->actlen = 0; 1524 1525 ep->xfer = xfer; 1526 ep->datalen = xfer->length; 1527 if (ep->datalen > 0) 1528 ep->data = xfer->buf; 1529 else 1530 ep->data = NULL; 1531 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1532 (ep->datalen % 64) == 0) 1533 ep->need_short_xfer = 1; 1534 else 1535 ep->need_short_xfer = 0; 1536 /* now we need send this request */ 1537 DPRINTFN(MD_CTRL, 1538 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1539 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1540 xfer->pipe->device->address)); 1541 KASSERT(ep->phase == IDLE); 1542 ep->phase = SETUP; 1543 /* select endpoint 0 */ 1544 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1545 /* fifo should be empty at this point */ 1546 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1547 /* send data */ 1548 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1549 KASSERT(sizeof(xfer->request) == 8); 1550 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1551 (void *)&xfer->request, sizeof(xfer->request)); 1552 1553 motg_setup_endpoint_tx(xfer); 1554 /* start transaction */ 1555 UWRITE1(sc, MUSB2_REG_TXCSRL, 1556 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1557 1558 end: 1559 if (err) 1560 return (err); 1561 1562 return (USBD_IN_PROGRESS); 1563 } 1564 1565 static void 1566 motg_device_ctrl_read(usbd_xfer_handle xfer) 1567 { 1568 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1569 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1570 /* assume endpoint already selected */ 1571 motg_setup_endpoint_rx(xfer); 1572 /* start transaction */ 1573 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1574 otgpipe->hw_ep->phase = DATA_IN; 1575 } 1576 1577 static void 1578 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1579 { 1580 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1581 usbd_xfer_handle xfer = ep->xfer; 1582 uint8_t csr; 1583 int datalen, max_datalen; 1584 char *data; 1585 bool got_short; 1586 usbd_status new_status = USBD_IN_PROGRESS; 1587 1588 KASSERT(mutex_owned(&sc->sc_lock)); 1589 1590 #ifdef DIAGNOSTIC 1591 if (ep->phase != DATA_IN && 1592 ep->phase != STATUS_IN) 1593 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1594 #endif 1595 /* select endpoint 0 */ 1596 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1597 1598 /* read out FIFO status */ 1599 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1600 DPRINTFN(MD_CTRL, 1601 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1602 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1603 1604 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1605 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1606 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1607 1608 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1609 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1610 new_status = USBD_TIMEOUT; /* XXX */ 1611 goto complete; 1612 } 1613 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1614 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1615 new_status = USBD_STALLED; 1616 else 1617 new_status = USBD_IOERROR; 1618 /* clear status */ 1619 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1620 goto complete; 1621 } 1622 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1623 return; /* no data yet */ 1624 1625 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1626 goto complete; 1627 1628 if (ep->phase == STATUS_IN) { 1629 new_status = USBD_NORMAL_COMPLETION; 1630 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1631 goto complete; 1632 } 1633 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1634 DPRINTFN(MD_CTRL, 1635 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1636 ep->phase, datalen)); 1637 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1638 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1639 ep->datalen); 1640 if (datalen > max_datalen) { 1641 new_status = USBD_IOERROR; 1642 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1643 goto complete; 1644 } 1645 got_short = (datalen < max_datalen); 1646 if (datalen > 0) { 1647 KASSERT(ep->phase == DATA_IN); 1648 data = ep->data; 1649 ep->data += datalen; 1650 ep->datalen -= datalen; 1651 xfer->actlen += datalen; 1652 if (((vaddr_t)data & 0x3) == 0 && 1653 (datalen >> 2) > 0) { 1654 DPRINTFN(MD_CTRL, 1655 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1656 data, datalen)); 1657 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1658 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1659 data += (datalen & ~0x3); 1660 datalen -= (datalen & ~0x3); 1661 } 1662 DPRINTFN(MD_CTRL, 1663 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1664 data, datalen)); 1665 if (datalen) { 1666 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1667 MUSB2_REG_EPFIFO(0), data, datalen); 1668 } 1669 } 1670 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1671 KASSERT(ep->phase == DATA_IN); 1672 if (got_short || (ep->datalen == 0)) { 1673 if (ep->need_short_xfer == 0) { 1674 ep->phase = STATUS_OUT; 1675 UWRITE1(sc, MUSB2_REG_TXCSRH, 1676 UREAD1(sc, MUSB2_REG_TXCSRH) | 1677 MUSB2_MASK_CSR0H_PING_DIS); 1678 motg_setup_endpoint_tx(xfer); 1679 UWRITE1(sc, MUSB2_REG_TXCSRL, 1680 MUSB2_MASK_CSR0L_STATUSPKT | 1681 MUSB2_MASK_CSR0L_TXPKTRDY); 1682 return; 1683 } 1684 ep->need_short_xfer = 0; 1685 } 1686 motg_device_ctrl_read(xfer); 1687 return; 1688 complete: 1689 ep->phase = IDLE; 1690 ep->xfer = NULL; 1691 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1692 KASSERT(new_status != USBD_IN_PROGRESS); 1693 xfer->status = new_status; 1694 usb_transfer_complete(xfer); 1695 } 1696 motg_device_ctrl_start1(sc); 1697 } 1698 1699 static void 1700 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1701 { 1702 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1703 usbd_xfer_handle xfer = ep->xfer; 1704 uint8_t csr; 1705 int datalen; 1706 char *data; 1707 usbd_status new_status = USBD_IN_PROGRESS; 1708 1709 KASSERT(mutex_owned(&sc->sc_lock)); 1710 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1711 motg_device_ctrl_intr_rx(sc); 1712 return; 1713 } 1714 1715 #ifdef DIAGNOSTIC 1716 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1717 ep->phase != STATUS_OUT) 1718 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1719 #endif 1720 /* select endpoint 0 */ 1721 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1722 1723 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1724 DPRINTFN(MD_CTRL, 1725 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1726 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1727 1728 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1729 /* command not accepted */ 1730 new_status = USBD_STALLED; 1731 /* clear status */ 1732 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1733 goto complete; 1734 } 1735 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1736 new_status = USBD_TIMEOUT; /* XXX */ 1737 /* flush fifo */ 1738 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1739 UWRITE1(sc, MUSB2_REG_TXCSRH, 1740 UREAD1(sc, MUSB2_REG_TXCSRH) | 1741 MUSB2_MASK_CSR0H_FFLUSH); 1742 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1743 } 1744 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1745 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1746 goto complete; 1747 } 1748 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1749 new_status = USBD_IOERROR; 1750 /* clear status */ 1751 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1752 goto complete; 1753 } 1754 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1755 /* data still not sent */ 1756 return; 1757 } 1758 if (xfer == NULL) 1759 goto complete; 1760 if (ep->phase == STATUS_OUT) { 1761 /* 1762 * we have sent status and got no error; 1763 * declare transfer complete 1764 */ 1765 DPRINTFN(MD_CTRL, 1766 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1767 xfer, xfer->status)); 1768 new_status = USBD_NORMAL_COMPLETION; 1769 goto complete; 1770 } 1771 if (ep->datalen == 0) { 1772 if (ep->need_short_xfer) { 1773 ep->need_short_xfer = 0; 1774 /* one more data phase */ 1775 if (xfer->request.bmRequestType & UT_READ) { 1776 DPRINTFN(MD_CTRL, 1777 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1778 motg_device_ctrl_read(xfer); 1779 return; 1780 } /* else fall back to DATA_OUT */ 1781 } else { 1782 DPRINTFN(MD_CTRL, 1783 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1784 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1785 ep->phase = STATUS_IN; 1786 UWRITE1(sc, MUSB2_REG_RXCSRH, 1787 UREAD1(sc, MUSB2_REG_RXCSRH) | 1788 MUSB2_MASK_CSR0H_PING_DIS); 1789 motg_setup_endpoint_rx(xfer); 1790 UWRITE1(sc, MUSB2_REG_TXCSRL, 1791 MUSB2_MASK_CSR0L_STATUSPKT | 1792 MUSB2_MASK_CSR0L_REQPKT); 1793 return; 1794 } 1795 } 1796 if (xfer->request.bmRequestType & UT_READ) { 1797 motg_device_ctrl_read(xfer); 1798 return; 1799 } 1800 /* setup a dataout phase */ 1801 datalen = min(ep->datalen, 1802 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1803 ep->phase = DATA_OUT; 1804 DPRINTFN(MD_CTRL, 1805 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1806 UREAD1(sc, MUSB2_REG_TXCSRH))); 1807 if (datalen) { 1808 data = ep->data; 1809 ep->data += datalen; 1810 ep->datalen -= datalen; 1811 xfer->actlen += datalen; 1812 if (((vaddr_t)data & 0x3) == 0 && 1813 (datalen >> 2) > 0) { 1814 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1815 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1816 data += (datalen & ~0x3); 1817 datalen -= (datalen & ~0x3); 1818 } 1819 if (datalen) { 1820 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1821 MUSB2_REG_EPFIFO(0), data, datalen); 1822 } 1823 } 1824 /* send data */ 1825 motg_setup_endpoint_tx(xfer); 1826 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1827 return; 1828 1829 complete: 1830 ep->phase = IDLE; 1831 ep->xfer = NULL; 1832 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1833 KASSERT(new_status != USBD_IN_PROGRESS); 1834 xfer->status = new_status; 1835 usb_transfer_complete(xfer); 1836 } 1837 motg_device_ctrl_start1(sc); 1838 } 1839 1840 /* Abort a device control request. */ 1841 void 1842 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1843 { 1844 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1845 motg_device_xfer_abort(xfer); 1846 } 1847 1848 /* Close a device control pipe */ 1849 void 1850 motg_device_ctrl_close(usbd_pipe_handle pipe) 1851 { 1852 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 1853 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1854 struct motg_pipe *otgpipeiter; 1855 1856 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1857 KASSERT(mutex_owned(&sc->sc_lock)); 1858 KASSERT(otgpipe->hw_ep->xfer == NULL || 1859 otgpipe->hw_ep->xfer->pipe != pipe); 1860 1861 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1862 if (otgpipeiter == otgpipe) { 1863 /* remove from list */ 1864 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1865 motg_pipe, ep_pipe_list); 1866 otgpipe->hw_ep->refcount--; 1867 /* we're done */ 1868 return; 1869 } 1870 } 1871 panic("motg_device_ctrl_close: not found"); 1872 } 1873 1874 void 1875 motg_device_ctrl_done(usbd_xfer_handle xfer) 1876 { 1877 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 1878 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1879 KASSERT(otgpipe->hw_ep->xfer != xfer); 1880 } 1881 1882 static usbd_status 1883 motg_device_data_transfer(usbd_xfer_handle xfer) 1884 { 1885 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1886 usbd_status err; 1887 1888 /* Insert last in queue. */ 1889 mutex_enter(&sc->sc_lock); 1890 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1891 xfer, xfer->status)); 1892 err = usb_insert_transfer(xfer); 1893 xfer->status = USBD_NOT_STARTED; 1894 mutex_exit(&sc->sc_lock); 1895 if (err) 1896 return (err); 1897 1898 /* 1899 * Pipe isn't running (otherwise err would be USBD_INPROG), 1900 * so start it first. 1901 */ 1902 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1903 } 1904 1905 static usbd_status 1906 motg_device_data_start(usbd_xfer_handle xfer) 1907 { 1908 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1909 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1910 usbd_status err; 1911 mutex_enter(&sc->sc_lock); 1912 DPRINTF(("motg_device_data_start(%p) status %d\n", 1913 xfer, xfer->status)); 1914 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1915 mutex_exit(&sc->sc_lock); 1916 if (err != USBD_IN_PROGRESS) 1917 return err; 1918 if (sc->sc_bus.use_polling) 1919 motg_waitintr(sc, xfer); 1920 return USBD_IN_PROGRESS; 1921 } 1922 1923 static usbd_status 1924 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1925 { 1926 usbd_xfer_handle xfer = NULL; 1927 struct motg_pipe *otgpipe; 1928 usbd_status err = 0; 1929 uint32_t val __diagused; 1930 1931 KASSERT(mutex_owned(&sc->sc_lock)); 1932 if (sc->sc_dying) 1933 return (USBD_IOERROR); 1934 1935 if (!sc->sc_connected) 1936 return (USBD_IOERROR); 1937 1938 if (ep->xfer != NULL) { 1939 err = USBD_IN_PROGRESS; 1940 goto end; 1941 } 1942 /* locate the first pipe with work to do */ 1943 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1944 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1945 DPRINTFN(MD_BULK, 1946 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1947 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1948 if (xfer != NULL) { 1949 /* move this pipe to the end of the list */ 1950 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1951 motg_pipe, ep_pipe_list); 1952 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1953 otgpipe, ep_pipe_list); 1954 break; 1955 } 1956 } 1957 if (xfer == NULL) { 1958 err = USBD_NOT_STARTED; 1959 goto end; 1960 } 1961 xfer->status = USBD_IN_PROGRESS; 1962 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1963 KASSERT(otgpipe->hw_ep == ep); 1964 #ifdef DIAGNOSTIC 1965 if (xfer->rqflags & URQ_REQUEST) 1966 panic("motg_device_data_transfer: a request"); 1967 #endif 1968 // KASSERT(xfer->actlen == 0); 1969 xfer->actlen = 0; 1970 1971 ep->xfer = xfer; 1972 ep->datalen = xfer->length; 1973 KASSERT(ep->datalen > 0); 1974 ep->data = xfer->buf; 1975 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1976 (ep->datalen % 64) == 0) 1977 ep->need_short_xfer = 1; 1978 else 1979 ep->need_short_xfer = 0; 1980 /* now we need send this request */ 1981 DPRINTFN(MD_BULK, 1982 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 1983 xfer, 1984 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 1985 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1986 xfer->pipe->device->address)); 1987 KASSERT(ep->phase == IDLE); 1988 /* select endpoint */ 1989 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1990 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 1991 == UE_DIR_IN) { 1992 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1993 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1994 motg_device_data_read(xfer); 1995 } else { 1996 ep->phase = DATA_OUT; 1997 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1998 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1999 motg_device_data_write(xfer); 2000 } 2001 end: 2002 if (err) 2003 return (err); 2004 2005 return (USBD_IN_PROGRESS); 2006 } 2007 2008 static void 2009 motg_device_data_read(usbd_xfer_handle xfer) 2010 { 2011 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2012 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2013 uint32_t val; 2014 2015 KASSERT(mutex_owned(&sc->sc_lock)); 2016 /* assume endpoint already selected */ 2017 motg_setup_endpoint_rx(xfer); 2018 /* Max packet size */ 2019 UWRITE2(sc, MUSB2_REG_RXMAXP, 2020 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2021 /* Data Toggle */ 2022 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2023 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2024 if (otgpipe->nexttoggle) 2025 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2026 else 2027 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2028 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2029 2030 DPRINTFN(MD_BULK, 2031 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2032 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2033 /* start transaction */ 2034 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2035 otgpipe->hw_ep->phase = DATA_IN; 2036 } 2037 2038 static void 2039 motg_device_data_write(usbd_xfer_handle xfer) 2040 { 2041 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2042 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2043 struct motg_hw_ep *ep = otgpipe->hw_ep; 2044 int datalen; 2045 char *data; 2046 uint32_t val; 2047 2048 KASSERT(xfer!=NULL); 2049 KASSERT(mutex_owned(&sc->sc_lock)); 2050 2051 datalen = min(ep->datalen, 2052 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2053 ep->phase = DATA_OUT; 2054 DPRINTFN(MD_BULK, 2055 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2056 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2057 2058 /* assume endpoint already selected */ 2059 /* write data to fifo */ 2060 data = ep->data; 2061 ep->data += datalen; 2062 ep->datalen -= datalen; 2063 xfer->actlen += datalen; 2064 if (((vaddr_t)data & 0x3) == 0 && 2065 (datalen >> 2) > 0) { 2066 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2067 MUSB2_REG_EPFIFO(ep->ep_number), 2068 (void *)data, datalen >> 2); 2069 data += (datalen & ~0x3); 2070 datalen -= (datalen & ~0x3); 2071 } 2072 if (datalen) { 2073 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2074 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2075 } 2076 2077 motg_setup_endpoint_tx(xfer); 2078 /* Max packet size */ 2079 UWRITE2(sc, MUSB2_REG_TXMAXP, 2080 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2081 /* Data Toggle */ 2082 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2083 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2084 if (otgpipe->nexttoggle) 2085 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2086 else 2087 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2088 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2089 2090 /* start transaction */ 2091 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2092 } 2093 2094 static void 2095 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2096 { 2097 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2098 usbd_xfer_handle xfer = ep->xfer; 2099 uint8_t csr; 2100 int datalen, max_datalen; 2101 char *data; 2102 bool got_short; 2103 usbd_status new_status = USBD_IN_PROGRESS; 2104 2105 KASSERT(mutex_owned(&sc->sc_lock)); 2106 KASSERT(ep->ep_number == epnumber); 2107 2108 DPRINTFN(MD_BULK, 2109 ("motg_device_intr_rx on ep %d\n", epnumber)); 2110 /* select endpoint */ 2111 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2112 2113 /* read out FIFO status */ 2114 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2115 DPRINTFN(MD_BULK, 2116 ("motg_device_intr_rx phase %d csr 0x%x\n", 2117 ep->phase, csr)); 2118 2119 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2120 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2121 return; 2122 2123 #ifdef DIAGNOSTIC 2124 if (ep->phase != DATA_IN) 2125 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2126 #endif 2127 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2128 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2129 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2130 2131 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2132 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2133 new_status = USBD_TIMEOUT; /* XXX */ 2134 goto complete; 2135 } 2136 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2137 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2138 new_status = USBD_STALLED; 2139 else 2140 new_status = USBD_IOERROR; 2141 /* clear status */ 2142 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2143 goto complete; 2144 } 2145 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2146 2147 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2148 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2149 goto complete; 2150 } 2151 2152 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2153 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2154 2155 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2156 DPRINTFN(MD_BULK, 2157 ("motg_device_intr_rx phase %d datalen %d\n", 2158 ep->phase, datalen)); 2159 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2160 max_datalen = min( 2161 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2162 ep->datalen); 2163 if (datalen > max_datalen) { 2164 new_status = USBD_IOERROR; 2165 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2166 goto complete; 2167 } 2168 got_short = (datalen < max_datalen); 2169 if (datalen > 0) { 2170 KASSERT(ep->phase == DATA_IN); 2171 data = ep->data; 2172 ep->data += datalen; 2173 ep->datalen -= datalen; 2174 xfer->actlen += datalen; 2175 if (((vaddr_t)data & 0x3) == 0 && 2176 (datalen >> 2) > 0) { 2177 DPRINTFN(MD_BULK, 2178 ("motg_device_intr_rx r4 data %p len %d\n", 2179 data, datalen)); 2180 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2181 MUSB2_REG_EPFIFO(ep->ep_number), 2182 (void *)data, datalen >> 2); 2183 data += (datalen & ~0x3); 2184 datalen -= (datalen & ~0x3); 2185 } 2186 DPRINTFN(MD_BULK, 2187 ("motg_device_intr_rx r1 data %p len %d\n", 2188 data, datalen)); 2189 if (datalen) { 2190 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2191 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2192 } 2193 } 2194 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2195 KASSERT(ep->phase == DATA_IN); 2196 if (got_short || (ep->datalen == 0)) { 2197 if (ep->need_short_xfer == 0) { 2198 new_status = USBD_NORMAL_COMPLETION; 2199 goto complete; 2200 } 2201 ep->need_short_xfer = 0; 2202 } 2203 motg_device_data_read(xfer); 2204 return; 2205 complete: 2206 DPRINTFN(MD_BULK, 2207 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2208 (xfer != NULL) ? xfer->status : 0)); 2209 ep->phase = IDLE; 2210 ep->xfer = NULL; 2211 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2212 KASSERT(new_status != USBD_IN_PROGRESS); 2213 xfer->status = new_status; 2214 usb_transfer_complete(xfer); 2215 } 2216 motg_device_data_start1(sc, ep); 2217 } 2218 2219 static void 2220 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2221 { 2222 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2223 usbd_xfer_handle xfer = ep->xfer; 2224 uint8_t csr; 2225 struct motg_pipe *otgpipe; 2226 usbd_status new_status = USBD_IN_PROGRESS; 2227 2228 KASSERT(mutex_owned(&sc->sc_lock)); 2229 KASSERT(ep->ep_number == epnumber); 2230 2231 DPRINTFN(MD_BULK, 2232 ("motg_device_intr_tx on ep %d\n", epnumber)); 2233 /* select endpoint */ 2234 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2235 2236 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2237 DPRINTFN(MD_BULK, 2238 ("motg_device_intr_tx phase %d csr 0x%x\n", 2239 ep->phase, csr)); 2240 2241 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2242 /* command not accepted */ 2243 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2244 new_status = USBD_STALLED; 2245 else 2246 new_status = USBD_IOERROR; 2247 /* clear status */ 2248 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2249 goto complete; 2250 } 2251 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2252 new_status = USBD_TIMEOUT; /* XXX */ 2253 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2254 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2255 /* flush fifo */ 2256 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2257 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2258 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2259 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2260 delay(1000); 2261 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2262 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2263 epnumber, csr)); 2264 } 2265 goto complete; 2266 } 2267 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2268 /* data still not sent */ 2269 return; 2270 } 2271 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2272 goto complete; 2273 #ifdef DIAGNOSTIC 2274 if (ep->phase != DATA_OUT) 2275 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2276 #endif 2277 2278 otgpipe = (struct motg_pipe *)xfer->pipe; 2279 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2280 2281 if (ep->datalen == 0) { 2282 if (ep->need_short_xfer) { 2283 ep->need_short_xfer = 0; 2284 /* one more data phase */ 2285 } else { 2286 new_status = USBD_NORMAL_COMPLETION; 2287 goto complete; 2288 } 2289 } 2290 motg_device_data_write(xfer); 2291 return; 2292 2293 complete: 2294 DPRINTFN(MD_BULK, 2295 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2296 (xfer != NULL) ? xfer->status : 0)); 2297 #ifdef DIAGNOSTIC 2298 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2299 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2300 #endif 2301 ep->phase = IDLE; 2302 ep->xfer = NULL; 2303 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2304 KASSERT(new_status != USBD_IN_PROGRESS); 2305 xfer->status = new_status; 2306 usb_transfer_complete(xfer); 2307 } 2308 motg_device_data_start1(sc, ep); 2309 } 2310 2311 /* Abort a device control request. */ 2312 void 2313 motg_device_data_abort(usbd_xfer_handle xfer) 2314 { 2315 #ifdef DIAGNOSTIC 2316 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2317 #endif 2318 KASSERT(mutex_owned(&sc->sc_lock)); 2319 2320 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2321 motg_device_xfer_abort(xfer); 2322 } 2323 2324 /* Close a device control pipe */ 2325 void 2326 motg_device_data_close(usbd_pipe_handle pipe) 2327 { 2328 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 2329 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2330 struct motg_pipe *otgpipeiter; 2331 2332 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2333 KASSERT(mutex_owned(&sc->sc_lock)); 2334 KASSERT(otgpipe->hw_ep->xfer == NULL || 2335 otgpipe->hw_ep->xfer->pipe != pipe); 2336 2337 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2338 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2339 if (otgpipeiter == otgpipe) { 2340 /* remove from list */ 2341 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2342 motg_pipe, ep_pipe_list); 2343 otgpipe->hw_ep->refcount--; 2344 /* we're done */ 2345 return; 2346 } 2347 } 2348 panic("motg_device_data_close: not found"); 2349 } 2350 2351 void 2352 motg_device_data_done(usbd_xfer_handle xfer) 2353 { 2354 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 2355 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2356 KASSERT(otgpipe->hw_ep->xfer != xfer); 2357 } 2358 2359 /* 2360 * Wait here until controller claims to have an interrupt. 2361 * Then call motg_intr and return. Use timeout to avoid waiting 2362 * too long. 2363 * Only used during boot when interrupts are not enabled yet. 2364 */ 2365 void 2366 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2367 { 2368 int timo = xfer->timeout; 2369 2370 mutex_enter(&sc->sc_lock); 2371 2372 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2373 2374 for (; timo >= 0; timo--) { 2375 mutex_exit(&sc->sc_lock); 2376 usb_delay_ms(&sc->sc_bus, 1); 2377 mutex_spin_enter(&sc->sc_intr_lock); 2378 motg_poll(&sc->sc_bus); 2379 mutex_spin_exit(&sc->sc_intr_lock); 2380 mutex_enter(&sc->sc_lock); 2381 if (xfer->status != USBD_IN_PROGRESS) 2382 goto done; 2383 } 2384 2385 /* Timeout */ 2386 DPRINTF(("motg_waitintr: timeout\n")); 2387 panic("motg_waitintr: timeout"); 2388 /* XXX handle timeout ! */ 2389 2390 done: 2391 mutex_exit(&sc->sc_lock); 2392 } 2393 2394 void 2395 motg_device_clear_toggle(usbd_pipe_handle pipe) 2396 { 2397 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2398 otgpipe->nexttoggle = 0; 2399 } 2400 2401 /* Abort a device control request. */ 2402 static void 2403 motg_device_xfer_abort(usbd_xfer_handle xfer) 2404 { 2405 int wake; 2406 uint8_t csr; 2407 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2408 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2409 KASSERT(mutex_owned(&sc->sc_lock)); 2410 2411 DPRINTF(("motg_device_xfer_abort:\n")); 2412 if (xfer->hcflags & UXFER_ABORTING) { 2413 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2414 xfer->hcflags |= UXFER_ABORTWAIT; 2415 while (xfer->hcflags & UXFER_ABORTING) 2416 cv_wait(&xfer->hccv, &sc->sc_lock); 2417 return; 2418 } 2419 xfer->hcflags |= UXFER_ABORTING; 2420 if (otgpipe->hw_ep->xfer == xfer) { 2421 KASSERT(xfer->status == USBD_IN_PROGRESS); 2422 otgpipe->hw_ep->xfer = NULL; 2423 if (otgpipe->hw_ep->ep_number > 0) { 2424 /* select endpoint */ 2425 UWRITE1(sc, MUSB2_REG_EPINDEX, 2426 otgpipe->hw_ep->ep_number); 2427 if (otgpipe->hw_ep->phase == DATA_OUT) { 2428 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2429 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2430 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2431 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2432 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2433 } 2434 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2435 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2436 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2437 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2438 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2439 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2440 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2441 } 2442 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2443 } 2444 otgpipe->hw_ep->phase = IDLE; 2445 } 2446 } 2447 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2448 wake = xfer->hcflags & UXFER_ABORTWAIT; 2449 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2450 usb_transfer_complete(xfer); 2451 if (wake) 2452 cv_broadcast(&xfer->hccv); 2453 } 2454
Indexes created Mon Oct 13 08:09:50 GMT 2025