motg.c revision 1.14
1 /* $NetBSD: motg.c,v 1.14 2016/04/23 10:15:32 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.14 2016/04/23 10:15:32 skrll Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_motg.h" 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/bus.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usbhist.h> 70 71 #ifdef MOTG_ALLWINNER 72 #include <arch/arm/allwinner/awin_otgreg.h> 73 #else 74 #include <dev/usb/motgreg.h> 75 #endif 76 77 #include <dev/usb/motgvar.h> 78 #include <dev/usb/usbroothub.h> 79 80 #ifdef USB_DEBUG 81 #ifndef MOTG_DEBUG 82 #define motgdebug 0 83 #else 84 int motgdebug = 0; 85 86 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 87 { 88 int err; 89 const struct sysctlnode *rnode; 90 const struct sysctlnode *cnode; 91 92 err = sysctl_createv(clog, 0, NULL, &rnode, 93 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 94 SYSCTL_DESCR("motg global controls"), 95 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 96 97 if (err) 98 goto fail; 99 100 /* control debugging printfs */ 101 err = sysctl_createv(clog, 0, &rnode, &cnode, 102 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 103 "debug", SYSCTL_DESCR("Enable debugging output"), 104 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 105 if (err) 106 goto fail; 107 108 return; 109 fail: 110 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 111 } 112 113 #endif /* MOTG_DEBUG */ 114 #endif /* USB_DEBUG */ 115 116 #define MD_ROOT 0x0002 117 #define MD_CTRL 0x0004 118 #define MD_BULK 0x0008 119 120 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 121 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 122 #define MOTGHIST_FUNC() USBHIST_FUNC() 123 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 124 125 126 /* various timeouts, for various speeds */ 127 /* control NAK timeouts */ 128 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 129 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 130 131 /* intr/iso polling intervals */ 132 #define POLL_TO 100 /* 100 frames, about 0.1s */ 133 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 134 135 /* bulk NAK timeouts */ 136 #define NAK_TO_BULK 0 /* disabled */ 137 #define NAK_TO_BULK_HIGH 0 138 139 static void motg_hub_change(struct motg_softc *); 140 141 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 142 static usbd_status motg_root_intr_start(struct usbd_xfer *); 143 static void motg_root_intr_abort(struct usbd_xfer *); 144 static void motg_root_intr_close(struct usbd_pipe *); 145 static void motg_root_intr_done(struct usbd_xfer *); 146 147 static usbd_status motg_open(struct usbd_pipe *); 148 static void motg_poll(struct usbd_bus *); 149 static void motg_softintr(void *); 150 static struct usbd_xfer * 151 motg_allocx(struct usbd_bus *, unsigned int); 152 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 153 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 154 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 155 void *, int); 156 157 static void motg_noop(struct usbd_pipe *pipe); 158 static usbd_status motg_portreset(struct motg_softc*); 159 160 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 161 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 162 static void motg_device_ctrl_abort(struct usbd_xfer *); 163 static void motg_device_ctrl_close(struct usbd_pipe *); 164 static void motg_device_ctrl_done(struct usbd_xfer *); 165 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 166 static void motg_device_ctrl_read(struct usbd_xfer *); 167 static void motg_device_ctrl_intr_rx(struct motg_softc *); 168 static void motg_device_ctrl_intr_tx(struct motg_softc *); 169 170 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 171 static usbd_status motg_device_data_start(struct usbd_xfer *); 172 static usbd_status motg_device_data_start1(struct motg_softc *, 173 struct motg_hw_ep *); 174 static void motg_device_data_abort(struct usbd_xfer *); 175 static void motg_device_data_close(struct usbd_pipe *); 176 static void motg_device_data_done(struct usbd_xfer *); 177 static void motg_device_intr_rx(struct motg_softc *, int); 178 static void motg_device_intr_tx(struct motg_softc *, int); 179 static void motg_device_data_read(struct usbd_xfer *); 180 static void motg_device_data_write(struct usbd_xfer *); 181 182 static void motg_waitintr(struct motg_softc *, struct usbd_xfer *); 183 static void motg_device_clear_toggle(struct usbd_pipe *); 184 static void motg_device_xfer_abort(struct usbd_xfer *); 185 186 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 187 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 188 #define UWRITE1(sc, r, x) \ 189 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 190 } while (/*CONSTCOND*/0) 191 #define UWRITE2(sc, r, x) \ 192 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 193 } while (/*CONSTCOND*/0) 194 #define UWRITE4(sc, r, x) \ 195 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 196 } while (/*CONSTCOND*/0) 197 198 static __inline uint32_t 199 UREAD1(struct motg_softc *sc, bus_size_t r) 200 { 201 202 UBARR(sc); 203 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 204 } 205 static __inline uint32_t 206 UREAD2(struct motg_softc *sc, bus_size_t r) 207 { 208 209 UBARR(sc); 210 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 211 } 212 213 #if 0 214 static __inline uint32_t 215 UREAD4(struct motg_softc *sc, bus_size_t r) 216 { 217 218 UBARR(sc); 219 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 220 } 221 #endif 222 223 static void 224 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 225 { 226 uint8_t val; 227 228 val = UREAD1(sc, MUSB2_REG_POWER); 229 if (on) 230 val |= MUSB2_MASK_SOFTC; 231 else 232 val &= ~MUSB2_MASK_SOFTC; 233 234 UWRITE1(sc, MUSB2_REG_POWER, val); 235 } 236 237 const struct usbd_bus_methods motg_bus_methods = { 238 .ubm_open = motg_open, 239 .ubm_softint = motg_softintr, 240 .ubm_dopoll = motg_poll, 241 .ubm_allocx = motg_allocx, 242 .ubm_freex = motg_freex, 243 .ubm_getlock = motg_get_lock, 244 .ubm_rhctrl = motg_roothub_ctrl, 245 }; 246 247 const struct usbd_pipe_methods motg_root_intr_methods = { 248 .upm_transfer = motg_root_intr_transfer, 249 .upm_start = motg_root_intr_start, 250 .upm_abort = motg_root_intr_abort, 251 .upm_close = motg_root_intr_close, 252 .upm_cleartoggle = motg_noop, 253 .upm_done = motg_root_intr_done, 254 }; 255 256 const struct usbd_pipe_methods motg_device_ctrl_methods = { 257 .upm_transfer = motg_device_ctrl_transfer, 258 .upm_start = motg_device_ctrl_start, 259 .upm_abort = motg_device_ctrl_abort, 260 .upm_close = motg_device_ctrl_close, 261 .upm_cleartoggle = motg_noop, 262 .upm_done = motg_device_ctrl_done, 263 }; 264 265 const struct usbd_pipe_methods motg_device_data_methods = { 266 .upm_transfer = motg_device_data_transfer, 267 .upm_start = motg_device_data_start, 268 .upm_abort = motg_device_data_abort, 269 .upm_close = motg_device_data_close, 270 .upm_cleartoggle = motg_device_clear_toggle, 271 .upm_done = motg_device_data_done, 272 }; 273 274 int 275 motg_init(struct motg_softc *sc) 276 { 277 uint32_t nrx, ntx, val; 278 int dynfifo; 279 int offset, i; 280 281 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 282 283 if (sc->sc_mode == MOTG_MODE_DEVICE) 284 return ENOTSUP; /* not supported */ 285 286 /* disable all interrupts */ 287 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 288 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 289 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 290 /* disable pullup */ 291 292 musbotg_pull_common(sc, 0); 293 294 #ifdef MUSB2_REG_RXDBDIS 295 /* disable double packet buffering XXX what's this ? */ 296 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 297 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 298 #endif 299 300 /* enable HighSpeed and ISO Update flags */ 301 302 UWRITE1(sc, MUSB2_REG_POWER, 303 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 304 305 if (sc->sc_mode == MOTG_MODE_DEVICE) { 306 /* clear Session bit, if set */ 307 val = UREAD1(sc, MUSB2_REG_DEVCTL); 308 val &= ~MUSB2_MASK_SESS; 309 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 310 } else { 311 /* Enter session for Host mode */ 312 val = UREAD1(sc, MUSB2_REG_DEVCTL); 313 val |= MUSB2_MASK_SESS; 314 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 315 } 316 delay(1000); 317 DPRINTF("DEVCTL 0x%x", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 318 319 /* disable testmode */ 320 321 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 322 323 #ifdef MUSB2_REG_MISC 324 /* set default value */ 325 326 UWRITE1(sc, MUSB2_REG_MISC, 0); 327 #endif 328 329 /* select endpoint index 0 */ 330 331 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 332 333 if (sc->sc_ep_max == 0) { 334 /* read out number of endpoints */ 335 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 336 337 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 338 339 /* these numbers exclude the control endpoint */ 340 341 DPRINTFN(1,"RX/TX endpoints: %u/%u", nrx, ntx, 0, 0); 342 343 sc->sc_ep_max = MAX(nrx, ntx); 344 } else { 345 nrx = ntx = sc->sc_ep_max; 346 } 347 if (sc->sc_ep_max == 0) { 348 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 349 return -1; 350 } 351 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 352 /* read out configuration data */ 353 val = UREAD1(sc, MUSB2_REG_CONFDATA); 354 355 DPRINTF("Config Data: 0x%02x", val, 0, 0, 0); 356 357 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 358 359 if (dynfifo) { 360 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 361 "assuming 16Kbytes of FIFO RAM\n"); 362 } 363 364 DPRINTF("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 365 366 /* initialise endpoint profiles */ 367 sc->sc_in_ep[0].ep_fifo_size = 64; 368 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 369 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 370 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 371 offset = 64; 372 373 for (i = 1; i <= sc->sc_ep_max; i++) { 374 int fiforx_size, fifotx_size, fifo_size; 375 376 /* select endpoint */ 377 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 378 379 if (sc->sc_ep_fifosize) { 380 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 381 } else { 382 val = UREAD1(sc, MUSB2_REG_FSIZE); 383 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 384 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 385 } 386 387 DPRINTF("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d", 388 i, fifotx_size, fiforx_size, dynfifo); 389 390 if (dynfifo) { 391 if (sc->sc_ep_fifosize) { 392 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 393 } else { 394 if (i < 3) { 395 fifo_size = 12; /* 4K */ 396 } else if (i < 10) { 397 fifo_size = 10; /* 1K */ 398 } else { 399 fifo_size = 7; /* 128 bytes */ 400 } 401 } 402 if (fiforx_size && (i <= nrx)) { 403 fiforx_size = fifo_size; 404 if (fifo_size > 7) { 405 #if 0 406 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size) | 408 MUSB2_MASK_FIFODB); 409 #else 410 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 411 MUSB2_VAL_FIFOSZ(fifo_size)); 412 #endif 413 } else { 414 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 415 MUSB2_VAL_FIFOSZ(fifo_size)); 416 } 417 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 418 offset >> 3); 419 offset += (1 << fiforx_size); 420 } 421 if (fifotx_size && (i <= ntx)) { 422 fifotx_size = fifo_size; 423 if (fifo_size > 7) { 424 #if 0 425 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 426 MUSB2_VAL_FIFOSZ(fifo_size) | 427 MUSB2_MASK_FIFODB); 428 #else 429 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 430 MUSB2_VAL_FIFOSZ(fifo_size)); 431 #endif 432 } else { 433 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 434 MUSB2_VAL_FIFOSZ(fifo_size)); 435 } 436 437 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 438 offset >> 3); 439 440 offset += (1 << fifotx_size); 441 } 442 } 443 if (fiforx_size && (i <= nrx)) { 444 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 445 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 446 } 447 if (fifotx_size && (i <= ntx)) { 448 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 449 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 450 } 451 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 452 } 453 454 455 DPRINTF("Dynamic FIFO size = %d bytes", offset, 0, 0, 0); 456 457 /* turn on default interrupts */ 458 459 if (sc->sc_mode == MOTG_MODE_HOST) { 460 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 461 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 462 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 463 } else 464 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 465 466 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 467 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 468 469 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 470 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 471 472 /* Set up the bus struct. */ 473 sc->sc_bus.ub_methods = &motg_bus_methods; 474 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 475 sc->sc_bus.ub_revision = USBREV_2_0; 476 sc->sc_bus.ub_usedma = false; 477 sc->sc_bus.ub_hcpriv = sc; 478 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 479 "Mentor Graphics"); 480 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 481 return 0; 482 } 483 484 static int 485 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 486 { 487 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 488 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 489 struct motg_hw_ep *ep; 490 int i, size; 491 492 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 493 494 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 495 sc->sc_in_ep : sc->sc_out_ep; 496 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 497 498 for (i = sc->sc_ep_max; i >= 1; i--) { 499 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 500 "in_ep[%d].ep_fifo_size %d size %d ref %d" : 501 "out_ep[%d].ep_fifo_size %d size %d ref %d", i, 502 ep[i].ep_fifo_size, size, ep[i].refcount); 503 if (ep[i].ep_fifo_size >= size) { 504 /* found a suitable endpoint */ 505 otgpipe->hw_ep = &ep[i]; 506 mutex_enter(&sc->sc_lock); 507 if (otgpipe->hw_ep->refcount > 0) { 508 /* no luck, try next */ 509 mutex_exit(&sc->sc_lock); 510 otgpipe->hw_ep = NULL; 511 } else { 512 otgpipe->hw_ep->refcount++; 513 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 514 otgpipe, ep_pipe_list); 515 mutex_exit(&sc->sc_lock); 516 return 0; 517 } 518 } 519 } 520 return -1; 521 } 522 523 /* Open a new pipe. */ 524 usbd_status 525 motg_open(struct usbd_pipe *pipe) 526 { 527 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 528 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 529 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 530 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 531 532 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 533 534 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, 535 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 536 537 if (sc->sc_dying) 538 return USBD_IOERROR; 539 540 /* toggle state needed for bulk endpoints */ 541 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 542 543 if (pipe->up_dev->ud_addr == rhaddr) { 544 switch (ed->bEndpointAddress) { 545 case USB_CONTROL_ENDPOINT: 546 pipe->up_methods = &roothub_ctrl_methods; 547 break; 548 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 549 pipe->up_methods = &motg_root_intr_methods; 550 break; 551 default: 552 return USBD_INVAL; 553 } 554 } else { 555 switch (ed->bmAttributes & UE_XFERTYPE) { 556 case UE_CONTROL: 557 pipe->up_methods = &motg_device_ctrl_methods; 558 /* always use sc_in_ep[0] for in and out */ 559 otgpipe->hw_ep = &sc->sc_in_ep[0]; 560 mutex_enter(&sc->sc_lock); 561 otgpipe->hw_ep->refcount++; 562 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 563 otgpipe, ep_pipe_list); 564 mutex_exit(&sc->sc_lock); 565 break; 566 case UE_BULK: 567 case UE_INTERRUPT: 568 DPRINTFN(MD_BULK, 569 "type %d dir %d pipe wMaxPacketSize %d", 570 UE_GET_XFERTYPE(ed->bmAttributes), 571 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 572 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 573 if (motg_select_ep(sc, pipe) != 0) 574 goto bad; 575 KASSERT(otgpipe->hw_ep != NULL); 576 pipe->up_methods = &motg_device_data_methods; 577 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 578 break; 579 default: 580 goto bad; 581 #ifdef notyet 582 case UE_ISOCHRONOUS: 583 ... 584 break; 585 #endif /* notyet */ 586 } 587 } 588 return USBD_NORMAL_COMPLETION; 589 590 bad: 591 return USBD_NOMEM; 592 } 593 594 void 595 motg_softintr(void *v) 596 { 597 struct usbd_bus *bus = v; 598 struct motg_softc *sc = MOTG_BUS2SC(bus); 599 uint16_t rx_status, tx_status; 600 uint8_t ctrl_status; 601 uint32_t val; 602 int i; 603 604 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 605 606 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 607 608 DPRINTFN(MD_ROOT | MD_CTRL, "sc %p", sc, 0 ,0 ,0); 609 610 mutex_spin_enter(&sc->sc_intr_lock); 611 rx_status = sc->sc_intr_rx_ep; 612 sc->sc_intr_rx_ep = 0; 613 tx_status = sc->sc_intr_tx_ep; 614 sc->sc_intr_tx_ep = 0; 615 ctrl_status = sc->sc_intr_ctrl; 616 sc->sc_intr_ctrl = 0; 617 mutex_spin_exit(&sc->sc_intr_lock); 618 619 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 620 621 if (ctrl_status & (MUSB2_MASK_IRESET | 622 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 623 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 624 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%x", ctrl_status, 0, 0, 0); 625 626 if (ctrl_status & MUSB2_MASK_IRESET) { 627 sc->sc_isreset = 1; 628 sc->sc_port_suspended = 0; 629 sc->sc_port_suspended_change = 1; 630 sc->sc_connected_changed = 1; 631 sc->sc_port_enabled = 1; 632 633 val = UREAD1(sc, MUSB2_REG_POWER); 634 if (val & MUSB2_MASK_HSMODE) 635 sc->sc_high_speed = 1; 636 else 637 sc->sc_high_speed = 0; 638 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 639 0, 0, 0); 640 641 /* turn off interrupts */ 642 val = MUSB2_MASK_IRESET; 643 val &= ~MUSB2_MASK_IRESUME; 644 val |= MUSB2_MASK_ISUSP; 645 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 646 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 647 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 648 } 649 if (ctrl_status & MUSB2_MASK_IRESUME) { 650 if (sc->sc_port_suspended) { 651 sc->sc_port_suspended = 0; 652 sc->sc_port_suspended_change = 1; 653 val = UREAD1(sc, MUSB2_REG_INTUSBE); 654 /* disable resume interrupt */ 655 val &= ~MUSB2_MASK_IRESUME; 656 /* enable suspend interrupt */ 657 val |= MUSB2_MASK_ISUSP; 658 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 659 } 660 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 661 if (!sc->sc_port_suspended) { 662 sc->sc_port_suspended = 1; 663 sc->sc_port_suspended_change = 1; 664 665 val = UREAD1(sc, MUSB2_REG_INTUSBE); 666 /* disable suspend interrupt */ 667 val &= ~MUSB2_MASK_ISUSP; 668 /* enable resume interrupt */ 669 val |= MUSB2_MASK_IRESUME; 670 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 671 } 672 } 673 if (ctrl_status & MUSB2_MASK_ICONN) { 674 sc->sc_connected = 1; 675 sc->sc_connected_changed = 1; 676 sc->sc_isreset = 1; 677 sc->sc_port_enabled = 1; 678 } else if (ctrl_status & MUSB2_MASK_IDISC) { 679 sc->sc_connected = 0; 680 sc->sc_connected_changed = 1; 681 sc->sc_isreset = 0; 682 sc->sc_port_enabled = 0; 683 } 684 685 /* complete root HUB interrupt endpoint */ 686 687 motg_hub_change(sc); 688 } 689 /* 690 * read in interrupt status and mix with the status we 691 * got from the wrapper 692 */ 693 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 694 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 695 696 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 697 if (tx_status & 0x01) 698 motg_device_ctrl_intr_tx(sc); 699 for (i = 1; i <= sc->sc_ep_max; i++) { 700 if (rx_status & (0x01 << i)) 701 motg_device_intr_rx(sc, i); 702 if (tx_status & (0x01 << i)) 703 motg_device_intr_tx(sc, i); 704 } 705 return; 706 } 707 708 void 709 motg_poll(struct usbd_bus *bus) 710 { 711 struct motg_softc *sc = MOTG_BUS2SC(bus); 712 713 sc->sc_intr_poll(sc->sc_intr_poll_arg); 714 mutex_enter(&sc->sc_lock); 715 motg_softintr(bus); 716 mutex_exit(&sc->sc_lock); 717 } 718 719 int 720 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 721 uint8_t ctrl) 722 { 723 KASSERT(mutex_owned(&sc->sc_intr_lock)); 724 sc->sc_intr_tx_ep = tx_ep; 725 sc->sc_intr_rx_ep = rx_ep; 726 sc->sc_intr_ctrl = ctrl; 727 728 if (!sc->sc_bus.ub_usepolling) { 729 usb_schedsoftintr(&sc->sc_bus); 730 } 731 return 1; 732 } 733 734 int 735 motg_intr_vbus(struct motg_softc *sc, int vbus) 736 { 737 uint8_t val; 738 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 739 740 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 741 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 742 /* try to re-enter session for Host mode */ 743 val = UREAD1(sc, MUSB2_REG_DEVCTL); 744 val |= MUSB2_MASK_SESS; 745 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 746 } 747 return 1; 748 } 749 750 struct usbd_xfer * 751 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 752 { 753 struct motg_softc *sc = MOTG_BUS2SC(bus); 754 struct usbd_xfer *xfer; 755 756 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 757 if (xfer != NULL) { 758 memset(xfer, 0, sizeof(struct motg_xfer)); 759 #ifdef DIAGNOSTIC 760 xfer->ux_state = XFER_BUSY; 761 #endif 762 } 763 return xfer; 764 } 765 766 void 767 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 768 { 769 struct motg_softc *sc = MOTG_BUS2SC(bus); 770 771 #ifdef DIAGNOSTIC 772 if (xfer->ux_state != XFER_BUSY) { 773 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 774 xfer->ux_state); 775 } 776 xfer->ux_state = XFER_FREE; 777 #endif 778 pool_cache_put(sc->sc_xferpool, xfer); 779 } 780 781 static void 782 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 783 { 784 struct motg_softc *sc = MOTG_BUS2SC(bus); 785 786 *lock = &sc->sc_lock; 787 } 788 789 /* 790 * Routines to emulate the root hub. 791 */ 792 Static int 793 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 794 void *buf, int buflen) 795 { 796 struct motg_softc *sc = MOTG_BUS2SC(bus); 797 int status, change, totlen = 0; 798 uint16_t len, value, index; 799 usb_port_status_t ps; 800 usbd_status err; 801 uint32_t val; 802 803 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 804 805 if (sc->sc_dying) 806 return -1; 807 808 DPRINTFN(MD_ROOT, "type=0x%02x request=%02x", req->bmRequestType, 809 req->bRequest, 0, 0); 810 811 len = UGETW(req->wLength); 812 value = UGETW(req->wValue); 813 index = UGETW(req->wIndex); 814 815 #define C(x,y) ((x) | ((y) << 8)) 816 switch (C(req->bRequest, req->bmRequestType)) { 817 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 818 DPRINTFN(MD_ROOT, "wValue=0x%04x", value, 0, 0, 0); 819 switch (value) { 820 case C(0, UDESC_DEVICE): { 821 usb_device_descriptor_t devd; 822 823 totlen = min(buflen, sizeof(devd)); 824 memcpy(&devd, buf, totlen); 825 USETW(devd.idVendor, sc->sc_id_vendor); 826 memcpy(buf, &devd, totlen); 827 break; 828 } 829 case C(1, UDESC_STRING): 830 #define sd ((usb_string_descriptor_t *)buf) 831 /* Vendor */ 832 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 833 break; 834 case C(2, UDESC_STRING): 835 /* Product */ 836 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 837 break; 838 #undef sd 839 default: 840 /* default from usbroothub */ 841 return buflen; 842 } 843 break; 844 /* Hub requests */ 845 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 846 break; 847 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 848 DPRINTFN(MD_ROOT, 849 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 850 0, 0); 851 if (index != 1) { 852 return -1; 853 } 854 switch (value) { 855 case UHF_PORT_ENABLE: 856 sc->sc_port_enabled = 0; 857 break; 858 case UHF_PORT_SUSPEND: 859 if (sc->sc_port_suspended != 0) { 860 val = UREAD1(sc, MUSB2_REG_POWER); 861 val &= ~MUSB2_MASK_SUSPMODE; 862 val |= MUSB2_MASK_RESUME; 863 UWRITE1(sc, MUSB2_REG_POWER, val); 864 /* wait 20 milliseconds */ 865 usb_delay_ms(&sc->sc_bus, 20); 866 val = UREAD1(sc, MUSB2_REG_POWER); 867 val &= ~MUSB2_MASK_RESUME; 868 UWRITE1(sc, MUSB2_REG_POWER, val); 869 sc->sc_port_suspended = 0; 870 sc->sc_port_suspended_change = 1; 871 } 872 break; 873 case UHF_PORT_RESET: 874 break; 875 case UHF_C_PORT_CONNECTION: 876 break; 877 case UHF_C_PORT_ENABLE: 878 break; 879 case UHF_C_PORT_OVER_CURRENT: 880 break; 881 case UHF_C_PORT_RESET: 882 sc->sc_isreset = 0; 883 break; 884 case UHF_PORT_POWER: 885 /* XXX todo */ 886 break; 887 case UHF_PORT_CONNECTION: 888 case UHF_PORT_OVER_CURRENT: 889 case UHF_PORT_LOW_SPEED: 890 case UHF_C_PORT_SUSPEND: 891 default: 892 return -1; 893 } 894 break; 895 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 896 return -1; 897 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 898 if (len == 0) 899 break; 900 if ((value & 0xff) != 0) { 901 return -1; 902 } 903 totlen = buflen; 904 break; 905 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 906 if (len != 4) { 907 return -1; 908 } 909 memset(buf, 0, len); 910 totlen = len; 911 break; 912 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 913 if (index != 1) { 914 return -1; 915 } 916 if (len != 4) { 917 return -1; 918 } 919 status = change = 0; 920 if (sc->sc_connected) 921 status |= UPS_CURRENT_CONNECT_STATUS; 922 if (sc->sc_connected_changed) { 923 change |= UPS_C_CONNECT_STATUS; 924 sc->sc_connected_changed = 0; 925 } 926 if (sc->sc_port_enabled) 927 status |= UPS_PORT_ENABLED; 928 if (sc->sc_port_enabled_changed) { 929 change |= UPS_C_PORT_ENABLED; 930 sc->sc_port_enabled_changed = 0; 931 } 932 if (sc->sc_port_suspended) 933 status |= UPS_SUSPEND; 934 if (sc->sc_high_speed) 935 status |= UPS_HIGH_SPEED; 936 status |= UPS_PORT_POWER; /* XXX */ 937 if (sc->sc_isreset) 938 change |= UPS_C_PORT_RESET; 939 USETW(ps.wPortStatus, status); 940 USETW(ps.wPortChange, change); 941 totlen = min(len, sizeof(ps)); 942 memcpy(buf, &ps, totlen); 943 break; 944 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 945 return -1; 946 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 947 break; 948 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 949 if (index != 1) { 950 return -1; 951 } 952 switch(value) { 953 case UHF_PORT_ENABLE: 954 sc->sc_port_enabled = 1; 955 break; 956 case UHF_PORT_SUSPEND: 957 if (sc->sc_port_suspended == 0) { 958 val = UREAD1(sc, MUSB2_REG_POWER); 959 val |= MUSB2_MASK_SUSPMODE; 960 UWRITE1(sc, MUSB2_REG_POWER, val); 961 /* wait 20 milliseconds */ 962 usb_delay_ms(&sc->sc_bus, 20); 963 sc->sc_port_suspended = 1; 964 sc->sc_port_suspended_change = 1; 965 } 966 break; 967 case UHF_PORT_RESET: 968 err = motg_portreset(sc); 969 if (err != USBD_NORMAL_COMPLETION) 970 return -1; 971 return 0; 972 case UHF_PORT_POWER: 973 /* XXX todo */ 974 return 0; 975 case UHF_C_PORT_CONNECTION: 976 case UHF_C_PORT_ENABLE: 977 case UHF_C_PORT_OVER_CURRENT: 978 case UHF_PORT_CONNECTION: 979 case UHF_PORT_OVER_CURRENT: 980 case UHF_PORT_LOW_SPEED: 981 case UHF_C_PORT_SUSPEND: 982 case UHF_C_PORT_RESET: 983 default: 984 return -1; 985 } 986 break; 987 default: 988 /* default from usbroothub */ 989 return buflen; 990 } 991 992 return totlen; 993 } 994 995 /* Abort a root interrupt request. */ 996 void 997 motg_root_intr_abort(struct usbd_xfer *xfer) 998 { 999 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1000 1001 KASSERT(mutex_owned(&sc->sc_lock)); 1002 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 1003 1004 sc->sc_intr_xfer = NULL; 1005 1006 xfer->ux_status = USBD_CANCELLED; 1007 usb_transfer_complete(xfer); 1008 } 1009 1010 usbd_status 1011 motg_root_intr_transfer(struct usbd_xfer *xfer) 1012 { 1013 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1014 usbd_status err; 1015 1016 /* Insert last in queue. */ 1017 mutex_enter(&sc->sc_lock); 1018 err = usb_insert_transfer(xfer); 1019 mutex_exit(&sc->sc_lock); 1020 if (err) 1021 return err; 1022 1023 /* 1024 * Pipe isn't running (otherwise err would be USBD_INPROG), 1025 * start first 1026 */ 1027 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1028 } 1029 1030 /* Start a transfer on the root interrupt pipe */ 1031 usbd_status 1032 motg_root_intr_start(struct usbd_xfer *xfer) 1033 { 1034 struct usbd_pipe *pipe = xfer->ux_pipe; 1035 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1036 1037 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1038 1039 DPRINTFN(MD_ROOT, "xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 1040 xfer->ux_flags, 0); 1041 1042 if (sc->sc_dying) 1043 return USBD_IOERROR; 1044 1045 sc->sc_intr_xfer = xfer; 1046 return USBD_IN_PROGRESS; 1047 } 1048 1049 /* Close the root interrupt pipe. */ 1050 void 1051 motg_root_intr_close(struct usbd_pipe *pipe) 1052 { 1053 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1054 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1055 1056 KASSERT(mutex_owned(&sc->sc_lock)); 1057 1058 sc->sc_intr_xfer = NULL; 1059 } 1060 1061 void 1062 motg_root_intr_done(struct usbd_xfer *xfer) 1063 { 1064 } 1065 1066 void 1067 motg_noop(struct usbd_pipe *pipe) 1068 { 1069 } 1070 1071 static usbd_status 1072 motg_portreset(struct motg_softc *sc) 1073 { 1074 uint32_t val; 1075 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1076 1077 val = UREAD1(sc, MUSB2_REG_POWER); 1078 val |= MUSB2_MASK_RESET; 1079 UWRITE1(sc, MUSB2_REG_POWER, val); 1080 /* Wait for 20 msec */ 1081 usb_delay_ms(&sc->sc_bus, 20); 1082 1083 val = UREAD1(sc, MUSB2_REG_POWER); 1084 val &= ~MUSB2_MASK_RESET; 1085 UWRITE1(sc, MUSB2_REG_POWER, val); 1086 1087 /* determine line speed */ 1088 val = UREAD1(sc, MUSB2_REG_POWER); 1089 if (val & MUSB2_MASK_HSMODE) 1090 sc->sc_high_speed = 1; 1091 else 1092 sc->sc_high_speed = 0; 1093 DPRINTFN(MD_ROOT | MD_CTRL, "speed %d", sc->sc_high_speed, 0, 0, 0); 1094 1095 sc->sc_isreset = 1; 1096 sc->sc_port_enabled = 1; 1097 return USBD_NORMAL_COMPLETION; 1098 } 1099 1100 /* 1101 * This routine is executed when an interrupt on the root hub is detected 1102 */ 1103 static void 1104 motg_hub_change(struct motg_softc *sc) 1105 { 1106 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1107 struct usbd_pipe *pipe; 1108 u_char *p; 1109 1110 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1111 1112 if (xfer == NULL) 1113 return; /* the interrupt pipe is not open */ 1114 1115 pipe = xfer->ux_pipe; 1116 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1117 return; /* device has detached */ 1118 1119 p = xfer->ux_buf; 1120 p[0] = 1<<1; 1121 xfer->ux_actlen = 1; 1122 xfer->ux_status = USBD_NORMAL_COMPLETION; 1123 usb_transfer_complete(xfer); 1124 } 1125 1126 static uint8_t 1127 motg_speed(uint8_t speed) 1128 { 1129 switch(speed) { 1130 case USB_SPEED_LOW: 1131 return MUSB2_MASK_TI_SPEED_LO; 1132 case USB_SPEED_FULL: 1133 return MUSB2_MASK_TI_SPEED_FS; 1134 case USB_SPEED_HIGH: 1135 return MUSB2_MASK_TI_SPEED_HS; 1136 default: 1137 panic("motg: unknown speed %d", speed); 1138 /* NOTREACHED */ 1139 } 1140 } 1141 1142 static uint8_t 1143 motg_type(uint8_t type) 1144 { 1145 switch(type) { 1146 case UE_CONTROL: 1147 return MUSB2_MASK_TI_PROTO_CTRL; 1148 case UE_ISOCHRONOUS: 1149 return MUSB2_MASK_TI_PROTO_ISOC; 1150 case UE_BULK: 1151 return MUSB2_MASK_TI_PROTO_BULK; 1152 case UE_INTERRUPT: 1153 return MUSB2_MASK_TI_PROTO_INTR; 1154 default: 1155 panic("motg: unknown type %d", type); 1156 /* NOTREACHED */ 1157 } 1158 } 1159 1160 static void 1161 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1162 { 1163 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1164 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1165 struct usbd_device *dev = otgpipe->pipe.up_dev; 1166 int epnumber = otgpipe->hw_ep->ep_number; 1167 1168 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1169 if (dev->ud_myhsport) { 1170 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1171 dev->ud_myhsport->up_parent->ud_addr); 1172 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1173 dev->ud_myhsport->up_portno); 1174 } else { 1175 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1176 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1177 } 1178 UWRITE1(sc, MUSB2_REG_TXTI, 1179 motg_speed(dev->ud_speed) | 1180 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1181 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1182 ); 1183 if (epnumber == 0) { 1184 if (sc->sc_high_speed) { 1185 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1186 NAK_TO_CTRL_HIGH); 1187 } else { 1188 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1189 } 1190 } else { 1191 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1192 == UE_BULK) { 1193 if (sc->sc_high_speed) { 1194 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1195 NAK_TO_BULK_HIGH); 1196 } else { 1197 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1198 } 1199 } else { 1200 if (sc->sc_high_speed) { 1201 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1202 } else { 1203 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1204 } 1205 } 1206 } 1207 } 1208 1209 static void 1210 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1211 { 1212 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1213 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1214 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1215 int epnumber = otgpipe->hw_ep->ep_number; 1216 1217 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1218 if (dev->ud_myhsport) { 1219 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1220 dev->ud_myhsport->up_parent->ud_addr); 1221 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1222 dev->ud_myhsport->up_portno); 1223 } else { 1224 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1225 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1226 } 1227 UWRITE1(sc, MUSB2_REG_RXTI, 1228 motg_speed(dev->ud_speed) | 1229 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1230 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1231 ); 1232 if (epnumber == 0) { 1233 if (sc->sc_high_speed) { 1234 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1235 NAK_TO_CTRL_HIGH); 1236 } else { 1237 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1238 } 1239 } else { 1240 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1241 == UE_BULK) { 1242 if (sc->sc_high_speed) { 1243 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1244 NAK_TO_BULK_HIGH); 1245 } else { 1246 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1247 } 1248 } else { 1249 if (sc->sc_high_speed) { 1250 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1251 } else { 1252 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1253 } 1254 } 1255 } 1256 } 1257 1258 static usbd_status 1259 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1260 { 1261 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1262 usbd_status err; 1263 1264 /* Insert last in queue. */ 1265 mutex_enter(&sc->sc_lock); 1266 err = usb_insert_transfer(xfer); 1267 xfer->ux_status = USBD_NOT_STARTED; 1268 mutex_exit(&sc->sc_lock); 1269 if (err) 1270 return err; 1271 1272 /* 1273 * Pipe isn't running (otherwise err would be USBD_INPROG), 1274 * so start it first. 1275 */ 1276 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1277 } 1278 1279 static usbd_status 1280 motg_device_ctrl_start(struct usbd_xfer *xfer) 1281 { 1282 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1283 usbd_status err; 1284 mutex_enter(&sc->sc_lock); 1285 err = motg_device_ctrl_start1(sc); 1286 mutex_exit(&sc->sc_lock); 1287 if (err != USBD_IN_PROGRESS) 1288 return err; 1289 if (sc->sc_bus.ub_usepolling) 1290 motg_waitintr(sc, xfer); 1291 return USBD_IN_PROGRESS; 1292 } 1293 1294 static usbd_status 1295 motg_device_ctrl_start1(struct motg_softc *sc) 1296 { 1297 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1298 struct usbd_xfer *xfer = NULL; 1299 struct motg_pipe *otgpipe; 1300 usbd_status err = 0; 1301 1302 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1303 1304 KASSERT(mutex_owned(&sc->sc_lock)); 1305 if (sc->sc_dying) 1306 return USBD_IOERROR; 1307 1308 if (!sc->sc_connected) 1309 return USBD_IOERROR; 1310 1311 if (ep->xfer != NULL) { 1312 err = USBD_IN_PROGRESS; 1313 goto end; 1314 } 1315 /* locate the first pipe with work to do */ 1316 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1317 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1318 DPRINTFN(MD_CTRL, "pipe %p xfer %p status %d", 1319 otgpipe, xfer, (xfer != NULL) ? xfer->ux_status : 0, 0); 1320 1321 if (xfer != NULL) { 1322 /* move this pipe to the end of the list */ 1323 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1324 motg_pipe, ep_pipe_list); 1325 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1326 otgpipe, ep_pipe_list); 1327 break; 1328 } 1329 } 1330 if (xfer == NULL) { 1331 err = USBD_NOT_STARTED; 1332 goto end; 1333 } 1334 xfer->ux_status = USBD_IN_PROGRESS; 1335 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1336 KASSERT(otgpipe->hw_ep == ep); 1337 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1338 // KASSERT(xfer->ux_actlen == 0); 1339 xfer->ux_actlen = 0; 1340 1341 ep->xfer = xfer; 1342 ep->datalen = xfer->ux_length; 1343 if (ep->datalen > 0) 1344 ep->data = xfer->ux_buf; 1345 else 1346 ep->data = NULL; 1347 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1348 (ep->datalen % 64) == 0) 1349 ep->need_short_xfer = 1; 1350 else 1351 ep->need_short_xfer = 0; 1352 /* now we need send this request */ 1353 DPRINTFN(MD_CTRL, 1354 "xfer %p send data %p len %d short %d", 1355 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1356 DPRINTFN(MD_CTRL, 1357 "xfer %p ... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1358 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1359 KASSERT(ep->phase == IDLE); 1360 ep->phase = SETUP; 1361 /* select endpoint 0 */ 1362 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1363 /* fifo should be empty at this point */ 1364 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1365 /* send data */ 1366 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1367 KASSERT(sizeof(xfer->ux_request) == 8); 1368 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1369 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1370 1371 motg_setup_endpoint_tx(xfer); 1372 /* start transaction */ 1373 UWRITE1(sc, MUSB2_REG_TXCSRL, 1374 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1375 1376 end: 1377 if (err) 1378 return err; 1379 1380 return USBD_IN_PROGRESS; 1381 } 1382 1383 static void 1384 motg_device_ctrl_read(struct usbd_xfer *xfer) 1385 { 1386 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1387 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1388 /* assume endpoint already selected */ 1389 motg_setup_endpoint_rx(xfer); 1390 /* start transaction */ 1391 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1392 otgpipe->hw_ep->phase = DATA_IN; 1393 } 1394 1395 static void 1396 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1397 { 1398 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1399 struct usbd_xfer *xfer = ep->xfer; 1400 uint8_t csr; 1401 int datalen, max_datalen; 1402 char *data; 1403 bool got_short; 1404 usbd_status new_status = USBD_IN_PROGRESS; 1405 1406 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1407 1408 KASSERT(mutex_owned(&sc->sc_lock)); 1409 1410 KASSERT(ep->phase == DATA_IN || ep->phase != STATUS_IN); 1411 /* select endpoint 0 */ 1412 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1413 1414 /* read out FIFO status */ 1415 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1416 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1417 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1418 1419 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1420 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1421 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1422 1423 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1424 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1425 new_status = USBD_TIMEOUT; /* XXX */ 1426 goto complete; 1427 } 1428 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1429 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1430 new_status = USBD_STALLED; 1431 else 1432 new_status = USBD_IOERROR; 1433 /* clear status */ 1434 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1435 goto complete; 1436 } 1437 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1438 return; /* no data yet */ 1439 1440 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1441 goto complete; 1442 1443 if (ep->phase == STATUS_IN) { 1444 new_status = USBD_NORMAL_COMPLETION; 1445 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1446 goto complete; 1447 } 1448 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1449 DPRINTFN(MD_CTRL, "phase %d datalen %d", ep->phase, datalen, 0, 0); 1450 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1451 max_datalen = min(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1452 ep->datalen); 1453 if (datalen > max_datalen) { 1454 new_status = USBD_IOERROR; 1455 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1456 goto complete; 1457 } 1458 got_short = (datalen < max_datalen); 1459 if (datalen > 0) { 1460 KASSERT(ep->phase == DATA_IN); 1461 data = ep->data; 1462 ep->data += datalen; 1463 ep->datalen -= datalen; 1464 xfer->ux_actlen += datalen; 1465 if (((vaddr_t)data & 0x3) == 0 && 1466 (datalen >> 2) > 0) { 1467 DPRINTFN(MD_CTRL, "r4 data %p len %d", data, datalen, 1468 0, 0); 1469 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1470 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1471 data += (datalen & ~0x3); 1472 datalen -= (datalen & ~0x3); 1473 } 1474 DPRINTFN(MD_CTRL, "r1 data %p len %d", data, datalen, 0, 0); 1475 if (datalen) { 1476 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1477 MUSB2_REG_EPFIFO(0), data, datalen); 1478 } 1479 } 1480 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1481 KASSERT(ep->phase == DATA_IN); 1482 if (got_short || (ep->datalen == 0)) { 1483 if (ep->need_short_xfer == 0) { 1484 ep->phase = STATUS_OUT; 1485 UWRITE1(sc, MUSB2_REG_TXCSRH, 1486 UREAD1(sc, MUSB2_REG_TXCSRH) | 1487 MUSB2_MASK_CSR0H_PING_DIS); 1488 motg_setup_endpoint_tx(xfer); 1489 UWRITE1(sc, MUSB2_REG_TXCSRL, 1490 MUSB2_MASK_CSR0L_STATUSPKT | 1491 MUSB2_MASK_CSR0L_TXPKTRDY); 1492 return; 1493 } 1494 ep->need_short_xfer = 0; 1495 } 1496 motg_device_ctrl_read(xfer); 1497 return; 1498 complete: 1499 ep->phase = IDLE; 1500 ep->xfer = NULL; 1501 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1502 KASSERT(new_status != USBD_IN_PROGRESS); 1503 xfer->ux_status = new_status; 1504 usb_transfer_complete(xfer); 1505 } 1506 motg_device_ctrl_start1(sc); 1507 } 1508 1509 static void 1510 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1511 { 1512 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1513 struct usbd_xfer *xfer = ep->xfer; 1514 uint8_t csr; 1515 int datalen; 1516 char *data; 1517 usbd_status new_status = USBD_IN_PROGRESS; 1518 1519 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1520 1521 KASSERT(mutex_owned(&sc->sc_lock)); 1522 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1523 motg_device_ctrl_intr_rx(sc); 1524 return; 1525 } 1526 1527 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1528 ep->phase == STATUS_OUT); 1529 1530 /* select endpoint 0 */ 1531 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1532 1533 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1534 DPRINTFN(MD_CTRL, "phase %d csr 0x%x xfer %p status %d", 1535 ep->phase, csr, xfer, (xfer != NULL) ? xfer->ux_status : 0); 1536 1537 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1538 /* command not accepted */ 1539 new_status = USBD_STALLED; 1540 /* clear status */ 1541 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1542 goto complete; 1543 } 1544 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1545 new_status = USBD_TIMEOUT; /* XXX */ 1546 /* flush fifo */ 1547 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1548 UWRITE1(sc, MUSB2_REG_TXCSRH, 1549 UREAD1(sc, MUSB2_REG_TXCSRH) | 1550 MUSB2_MASK_CSR0H_FFLUSH); 1551 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1552 } 1553 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1554 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1555 goto complete; 1556 } 1557 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1558 new_status = USBD_IOERROR; 1559 /* clear status */ 1560 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1561 goto complete; 1562 } 1563 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1564 /* data still not sent */ 1565 return; 1566 } 1567 if (xfer == NULL) 1568 goto complete; 1569 if (ep->phase == STATUS_OUT) { 1570 /* 1571 * we have sent status and got no error; 1572 * declare transfer complete 1573 */ 1574 DPRINTFN(MD_CTRL, "xfer %p status %d complete", xfer, 1575 xfer->ux_status, 0, 0); 1576 new_status = USBD_NORMAL_COMPLETION; 1577 goto complete; 1578 } 1579 if (ep->datalen == 0) { 1580 if (ep->need_short_xfer) { 1581 ep->need_short_xfer = 0; 1582 /* one more data phase */ 1583 if (xfer->ux_request.bmRequestType & UT_READ) { 1584 DPRINTFN(MD_CTRL, "xfer %p to DATA_IN", xfer, 1585 0, 0, 0); 1586 motg_device_ctrl_read(xfer); 1587 return; 1588 } /* else fall back to DATA_OUT */ 1589 } else { 1590 DPRINTFN(MD_CTRL, "xfer %p to STATUS_IN, csrh 0x%x", 1591 xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1592 ep->phase = STATUS_IN; 1593 UWRITE1(sc, MUSB2_REG_RXCSRH, 1594 UREAD1(sc, MUSB2_REG_RXCSRH) | 1595 MUSB2_MASK_CSR0H_PING_DIS); 1596 motg_setup_endpoint_rx(xfer); 1597 UWRITE1(sc, MUSB2_REG_TXCSRL, 1598 MUSB2_MASK_CSR0L_STATUSPKT | 1599 MUSB2_MASK_CSR0L_REQPKT); 1600 return; 1601 } 1602 } 1603 if (xfer->ux_request.bmRequestType & UT_READ) { 1604 motg_device_ctrl_read(xfer); 1605 return; 1606 } 1607 /* setup a dataout phase */ 1608 datalen = min(ep->datalen, 1609 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1610 ep->phase = DATA_OUT; 1611 DPRINTFN(MD_CTRL, "xfer %p to DATA_OUT, csrh 0x%x", xfer, 1612 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1613 if (datalen) { 1614 data = ep->data; 1615 ep->data += datalen; 1616 ep->datalen -= datalen; 1617 xfer->ux_actlen += datalen; 1618 if (((vaddr_t)data & 0x3) == 0 && 1619 (datalen >> 2) > 0) { 1620 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1621 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1622 data += (datalen & ~0x3); 1623 datalen -= (datalen & ~0x3); 1624 } 1625 if (datalen) { 1626 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1627 MUSB2_REG_EPFIFO(0), data, datalen); 1628 } 1629 } 1630 /* send data */ 1631 motg_setup_endpoint_tx(xfer); 1632 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1633 return; 1634 1635 complete: 1636 ep->phase = IDLE; 1637 ep->xfer = NULL; 1638 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1639 KASSERT(new_status != USBD_IN_PROGRESS); 1640 xfer->ux_status = new_status; 1641 usb_transfer_complete(xfer); 1642 } 1643 motg_device_ctrl_start1(sc); 1644 } 1645 1646 /* Abort a device control request. */ 1647 void 1648 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1649 { 1650 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1651 1652 motg_device_xfer_abort(xfer); 1653 } 1654 1655 /* Close a device control pipe */ 1656 void 1657 motg_device_ctrl_close(struct usbd_pipe *pipe) 1658 { 1659 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1660 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1661 struct motg_pipe *otgpipeiter; 1662 1663 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1664 1665 KASSERT(mutex_owned(&sc->sc_lock)); 1666 KASSERT(otgpipe->hw_ep->xfer == NULL || 1667 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1668 1669 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1670 if (otgpipeiter == otgpipe) { 1671 /* remove from list */ 1672 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1673 motg_pipe, ep_pipe_list); 1674 otgpipe->hw_ep->refcount--; 1675 /* we're done */ 1676 return; 1677 } 1678 } 1679 panic("motg_device_ctrl_close: not found"); 1680 } 1681 1682 void 1683 motg_device_ctrl_done(struct usbd_xfer *xfer) 1684 { 1685 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1686 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1687 1688 KASSERT(otgpipe->hw_ep->xfer != xfer); 1689 } 1690 1691 static usbd_status 1692 motg_device_data_transfer(struct usbd_xfer *xfer) 1693 { 1694 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1695 usbd_status err; 1696 1697 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1698 1699 /* Insert last in queue. */ 1700 mutex_enter(&sc->sc_lock); 1701 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1702 err = usb_insert_transfer(xfer); 1703 xfer->ux_status = USBD_NOT_STARTED; 1704 mutex_exit(&sc->sc_lock); 1705 if (err) 1706 return err; 1707 1708 /* 1709 * Pipe isn't running (otherwise err would be USBD_INPROG), 1710 * so start it first. 1711 */ 1712 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1713 } 1714 1715 static usbd_status 1716 motg_device_data_start(struct usbd_xfer *xfer) 1717 { 1718 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1719 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1720 usbd_status err; 1721 1722 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1723 1724 mutex_enter(&sc->sc_lock); 1725 DPRINTF("xfer %p status %d", xfer, xfer->ux_status, 0, 0); 1726 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1727 mutex_exit(&sc->sc_lock); 1728 if (err != USBD_IN_PROGRESS) 1729 return err; 1730 if (sc->sc_bus.ub_usepolling) 1731 motg_waitintr(sc, xfer); 1732 return USBD_IN_PROGRESS; 1733 } 1734 1735 static usbd_status 1736 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1737 { 1738 struct usbd_xfer *xfer = NULL; 1739 struct motg_pipe *otgpipe; 1740 usbd_status err = 0; 1741 uint32_t val __diagused; 1742 1743 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1744 1745 KASSERT(mutex_owned(&sc->sc_lock)); 1746 if (sc->sc_dying) 1747 return USBD_IOERROR; 1748 1749 if (!sc->sc_connected) 1750 return USBD_IOERROR; 1751 1752 if (ep->xfer != NULL) { 1753 err = USBD_IN_PROGRESS; 1754 goto end; 1755 } 1756 /* locate the first pipe with work to do */ 1757 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1758 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1759 DPRINTFN(MD_BULK, "pipe %p xfer %p status %d", otgpipe, xfer, 1760 (xfer != NULL) ? xfer->ux_status : 0, 0); 1761 if (xfer != NULL) { 1762 /* move this pipe to the end of the list */ 1763 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1764 motg_pipe, ep_pipe_list); 1765 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1766 otgpipe, ep_pipe_list); 1767 break; 1768 } 1769 } 1770 if (xfer == NULL) { 1771 err = USBD_NOT_STARTED; 1772 goto end; 1773 } 1774 xfer->ux_status = USBD_IN_PROGRESS; 1775 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1776 KASSERT(otgpipe->hw_ep == ep); 1777 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1778 // KASSERT(xfer->ux_actlen == 0); 1779 xfer->ux_actlen = 0; 1780 1781 ep->xfer = xfer; 1782 ep->datalen = xfer->ux_length; 1783 KASSERT(ep->datalen > 0); 1784 ep->data = xfer->ux_buf; 1785 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1786 (ep->datalen % 64) == 0) 1787 ep->need_short_xfer = 1; 1788 else 1789 ep->need_short_xfer = 0; 1790 /* now we need send this request */ 1791 DPRINTFN(MD_BULK, 1792 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1793 "xfer %p in data %p len %d short %d" : 1794 "xfer %p out data %p len %d short %d", 1795 xfer, ep->data, ep->datalen, ep->need_short_xfer); 1796 DPRINTFN(MD_BULK, "... speed %d to %d", xfer->ux_pipe->up_dev->ud_speed, 1797 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1798 KASSERT(ep->phase == IDLE); 1799 /* select endpoint */ 1800 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1801 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1802 == UE_DIR_IN) { 1803 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1804 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1805 motg_device_data_read(xfer); 1806 } else { 1807 ep->phase = DATA_OUT; 1808 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1809 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1810 motg_device_data_write(xfer); 1811 } 1812 end: 1813 if (err) 1814 return err; 1815 1816 return USBD_IN_PROGRESS; 1817 } 1818 1819 static void 1820 motg_device_data_read(struct usbd_xfer *xfer) 1821 { 1822 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1823 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1824 uint32_t val; 1825 1826 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1827 1828 KASSERT(mutex_owned(&sc->sc_lock)); 1829 /* assume endpoint already selected */ 1830 motg_setup_endpoint_rx(xfer); 1831 /* Max packet size */ 1832 UWRITE2(sc, MUSB2_REG_RXMAXP, 1833 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1834 /* Data Toggle */ 1835 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1836 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1837 if (otgpipe->nexttoggle) 1838 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1839 else 1840 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1841 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1842 1843 DPRINTFN(MD_BULK, "%p to DATA_IN on ep %d, csrh 0x%x", 1844 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1845 /* start transaction */ 1846 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1847 otgpipe->hw_ep->phase = DATA_IN; 1848 } 1849 1850 static void 1851 motg_device_data_write(struct usbd_xfer *xfer) 1852 { 1853 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1854 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1855 struct motg_hw_ep *ep = otgpipe->hw_ep; 1856 int datalen; 1857 char *data; 1858 uint32_t val; 1859 1860 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1861 1862 KASSERT(xfer!=NULL); 1863 KASSERT(mutex_owned(&sc->sc_lock)); 1864 1865 datalen = min(ep->datalen, 1866 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1867 ep->phase = DATA_OUT; 1868 DPRINTFN(MD_BULK, "%p to DATA_OUT on ep %d, len %d csrh 0x%x", 1869 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH)); 1870 1871 /* assume endpoint already selected */ 1872 /* write data to fifo */ 1873 data = ep->data; 1874 ep->data += datalen; 1875 ep->datalen -= datalen; 1876 xfer->ux_actlen += datalen; 1877 if (((vaddr_t)data & 0x3) == 0 && 1878 (datalen >> 2) > 0) { 1879 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1880 MUSB2_REG_EPFIFO(ep->ep_number), 1881 (void *)data, datalen >> 2); 1882 data += (datalen & ~0x3); 1883 datalen -= (datalen & ~0x3); 1884 } 1885 if (datalen) { 1886 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1887 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1888 } 1889 1890 motg_setup_endpoint_tx(xfer); 1891 /* Max packet size */ 1892 UWRITE2(sc, MUSB2_REG_TXMAXP, 1893 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1894 /* Data Toggle */ 1895 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1896 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1897 if (otgpipe->nexttoggle) 1898 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1899 else 1900 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1901 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1902 1903 /* start transaction */ 1904 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1905 } 1906 1907 static void 1908 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1909 { 1910 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1911 struct usbd_xfer *xfer = ep->xfer; 1912 uint8_t csr; 1913 int datalen, max_datalen; 1914 char *data; 1915 bool got_short; 1916 usbd_status new_status = USBD_IN_PROGRESS; 1917 1918 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1919 1920 KASSERT(mutex_owned(&sc->sc_lock)); 1921 KASSERT(ep->ep_number == epnumber); 1922 1923 DPRINTFN(MD_BULK, "on ep %d", epnumber, 0, 0, 0); 1924 /* select endpoint */ 1925 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1926 1927 /* read out FIFO status */ 1928 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1929 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr ,0 ,0); 1930 1931 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1932 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1933 return; 1934 1935 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1936 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1937 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1938 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1939 1940 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1941 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1942 new_status = USBD_TIMEOUT; /* XXX */ 1943 goto complete; 1944 } 1945 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1946 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1947 new_status = USBD_STALLED; 1948 else 1949 new_status = USBD_IOERROR; 1950 /* clear status */ 1951 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1952 goto complete; 1953 } 1954 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1955 1956 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1957 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1958 goto complete; 1959 } 1960 1961 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1962 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1963 1964 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1965 DPRINTFN(MD_BULK, "phase %d datalen %d", ep->phase, datalen ,0 ,0); 1966 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1967 max_datalen = min( 1968 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1969 ep->datalen); 1970 if (datalen > max_datalen) { 1971 new_status = USBD_IOERROR; 1972 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1973 goto complete; 1974 } 1975 got_short = (datalen < max_datalen); 1976 if (datalen > 0) { 1977 KASSERT(ep->phase == DATA_IN); 1978 data = ep->data; 1979 ep->data += datalen; 1980 ep->datalen -= datalen; 1981 xfer->ux_actlen += datalen; 1982 if (((vaddr_t)data & 0x3) == 0 && 1983 (datalen >> 2) > 0) { 1984 DPRINTFN(MD_BULK, "r4 data %p len %d", data, datalen, 1985 0, 0); 1986 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1987 MUSB2_REG_EPFIFO(ep->ep_number), 1988 (void *)data, datalen >> 2); 1989 data += (datalen & ~0x3); 1990 datalen -= (datalen & ~0x3); 1991 } 1992 DPRINTFN(MD_BULK, "r1 data %p len %d", data, datalen ,0 ,0); 1993 if (datalen) { 1994 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1995 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1996 } 1997 } 1998 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1999 KASSERT(ep->phase == DATA_IN); 2000 if (got_short || (ep->datalen == 0)) { 2001 if (ep->need_short_xfer == 0) { 2002 new_status = USBD_NORMAL_COMPLETION; 2003 goto complete; 2004 } 2005 ep->need_short_xfer = 0; 2006 } 2007 motg_device_data_read(xfer); 2008 return; 2009 complete: 2010 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2011 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2012 ep->phase = IDLE; 2013 ep->xfer = NULL; 2014 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2015 KASSERT(new_status != USBD_IN_PROGRESS); 2016 xfer->ux_status = new_status; 2017 usb_transfer_complete(xfer); 2018 } 2019 motg_device_data_start1(sc, ep); 2020 } 2021 2022 static void 2023 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2024 { 2025 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2026 struct usbd_xfer *xfer = ep->xfer; 2027 uint8_t csr; 2028 struct motg_pipe *otgpipe; 2029 usbd_status new_status = USBD_IN_PROGRESS; 2030 2031 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2032 2033 KASSERT(mutex_owned(&sc->sc_lock)); 2034 KASSERT(ep->ep_number == epnumber); 2035 2036 DPRINTFN(MD_BULK, " on ep %d", epnumber, 0, 0, 0); 2037 /* select endpoint */ 2038 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2039 2040 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2041 DPRINTFN(MD_BULK, "phase %d csr 0x%x", ep->phase, csr, 0, 0); 2042 2043 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2044 /* command not accepted */ 2045 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2046 new_status = USBD_STALLED; 2047 else 2048 new_status = USBD_IOERROR; 2049 /* clear status */ 2050 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2051 goto complete; 2052 } 2053 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2054 new_status = USBD_TIMEOUT; /* XXX */ 2055 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2056 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2057 /* flush fifo */ 2058 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2059 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2060 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2061 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2062 delay(1000); 2063 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2064 DPRINTFN(MD_BULK, "TX fifo flush ep %d CSR 0x%x", 2065 epnumber, csr, 0, 0); 2066 } 2067 goto complete; 2068 } 2069 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2070 /* data still not sent */ 2071 return; 2072 } 2073 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2074 goto complete; 2075 KASSERT(ep->phase == DATA_OUT); 2076 2077 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2078 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2079 2080 if (ep->datalen == 0) { 2081 if (ep->need_short_xfer) { 2082 ep->need_short_xfer = 0; 2083 /* one more data phase */ 2084 } else { 2085 new_status = USBD_NORMAL_COMPLETION; 2086 goto complete; 2087 } 2088 } 2089 motg_device_data_write(xfer); 2090 return; 2091 2092 complete: 2093 DPRINTFN(MD_BULK, "xfer %p complete, status %d", xfer, 2094 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2095 #ifdef DIAGNOSTIC 2096 if (xfer && xfer->ux_status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2097 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2098 #endif 2099 ep->phase = IDLE; 2100 ep->xfer = NULL; 2101 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2102 KASSERT(new_status != USBD_IN_PROGRESS); 2103 xfer->ux_status = new_status; 2104 usb_transfer_complete(xfer); 2105 } 2106 motg_device_data_start1(sc, ep); 2107 } 2108 2109 /* Abort a device control request. */ 2110 void 2111 motg_device_data_abort(struct usbd_xfer *xfer) 2112 { 2113 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2114 KASSERT(mutex_owned(&sc->sc_lock)); 2115 2116 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2117 2118 motg_device_xfer_abort(xfer); 2119 } 2120 2121 /* Close a device control pipe */ 2122 void 2123 motg_device_data_close(struct usbd_pipe *pipe) 2124 { 2125 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2126 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2127 struct motg_pipe *otgpipeiter; 2128 2129 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 KASSERT(otgpipe->hw_ep->xfer == NULL || 2133 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2134 2135 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2136 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2137 if (otgpipeiter == otgpipe) { 2138 /* remove from list */ 2139 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2140 motg_pipe, ep_pipe_list); 2141 otgpipe->hw_ep->refcount--; 2142 /* we're done */ 2143 return; 2144 } 2145 } 2146 panic("motg_device_data_close: not found"); 2147 } 2148 2149 void 2150 motg_device_data_done(struct usbd_xfer *xfer) 2151 { 2152 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2153 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2154 2155 KASSERT(otgpipe->hw_ep->xfer != xfer); 2156 } 2157 2158 /* 2159 * Wait here until controller claims to have an interrupt. 2160 * Then call motg_intr and return. Use timeout to avoid waiting 2161 * too long. 2162 * Only used during boot when interrupts are not enabled yet. 2163 */ 2164 void 2165 motg_waitintr(struct motg_softc *sc, struct usbd_xfer *xfer) 2166 { 2167 int timo = xfer->ux_timeout; 2168 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2169 2170 mutex_enter(&sc->sc_lock); 2171 2172 DPRINTF("timeout = %dms", timo, 0, 0, 0); 2173 2174 for (; timo >= 0; timo--) { 2175 mutex_exit(&sc->sc_lock); 2176 usb_delay_ms(&sc->sc_bus, 1); 2177 mutex_spin_enter(&sc->sc_intr_lock); 2178 motg_poll(&sc->sc_bus); 2179 mutex_spin_exit(&sc->sc_intr_lock); 2180 mutex_enter(&sc->sc_lock); 2181 if (xfer->ux_status != USBD_IN_PROGRESS) 2182 goto done; 2183 } 2184 2185 /* Timeout */ 2186 DPRINTF("timeout", 0, 0, 0, 0); 2187 panic("motg_waitintr: timeout"); 2188 /* XXX handle timeout ! */ 2189 2190 done: 2191 mutex_exit(&sc->sc_lock); 2192 } 2193 2194 void 2195 motg_device_clear_toggle(struct usbd_pipe *pipe) 2196 { 2197 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2198 otgpipe->nexttoggle = 0; 2199 } 2200 2201 /* Abort a device control request. */ 2202 static void 2203 motg_device_xfer_abort(struct usbd_xfer *xfer) 2204 { 2205 int wake; 2206 uint8_t csr; 2207 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2208 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2209 KASSERT(mutex_owned(&sc->sc_lock)); 2210 2211 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2212 2213 if (xfer->ux_hcflags & UXFER_ABORTING) { 2214 DPRINTF("already aborting", 0, 0, 0, 0); 2215 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2216 while (xfer->ux_hcflags & UXFER_ABORTING) 2217 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2218 return; 2219 } 2220 xfer->ux_hcflags |= UXFER_ABORTING; 2221 if (otgpipe->hw_ep->xfer == xfer) { 2222 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2223 otgpipe->hw_ep->xfer = NULL; 2224 if (otgpipe->hw_ep->ep_number > 0) { 2225 /* select endpoint */ 2226 UWRITE1(sc, MUSB2_REG_EPINDEX, 2227 otgpipe->hw_ep->ep_number); 2228 if (otgpipe->hw_ep->phase == DATA_OUT) { 2229 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2230 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2231 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2232 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2233 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2234 } 2235 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2236 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2237 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2238 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2239 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2240 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2241 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2242 } 2243 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2244 } 2245 otgpipe->hw_ep->phase = IDLE; 2246 } 2247 } 2248 xfer->ux_status = USBD_CANCELLED; /* make software ignore it */ 2249 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2250 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2251 usb_transfer_complete(xfer); 2252 if (wake) 2253 cv_broadcast(&xfer->ux_hccv); 2254 } 2255
Indexes created Thu Sep 25 16:09:42 GMT 2025