motg.c revision 1.19
1 /* $NetBSD: motg.c,v 1.19 2017/11/17 08:22:02 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.19 2017/11/17 08:22:02 skrll Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_motg.h" 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/bus.h> 53 #include <sys/cpu.h> 54 #include <sys/device.h> 55 #include <sys/kernel.h> 56 #include <sys/kmem.h> 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 #include <sys/sysctl.h> 61 #include <sys/systm.h> 62 63 #include <machine/endian.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 #include <dev/usb/usbdivar.h> 68 #include <dev/usb/usb_mem.h> 69 #include <dev/usb/usbhist.h> 70 71 #ifdef MOTG_ALLWINNER 72 #include <arch/arm/allwinner/awin_otgreg.h> 73 #else 74 #include <dev/usb/motgreg.h> 75 #endif 76 77 #include <dev/usb/motgvar.h> 78 #include <dev/usb/usbroothub.h> 79 80 #ifdef USB_DEBUG 81 #ifndef MOTG_DEBUG 82 #define motgdebug 0 83 #else 84 int motgdebug = 0; 85 86 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 87 { 88 int err; 89 const struct sysctlnode *rnode; 90 const struct sysctlnode *cnode; 91 92 err = sysctl_createv(clog, 0, NULL, &rnode, 93 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 94 SYSCTL_DESCR("motg global controls"), 95 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 96 97 if (err) 98 goto fail; 99 100 /* control debugging printfs */ 101 err = sysctl_createv(clog, 0, &rnode, &cnode, 102 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 103 "debug", SYSCTL_DESCR("Enable debugging output"), 104 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 105 if (err) 106 goto fail; 107 108 return; 109 fail: 110 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 111 } 112 113 #endif /* MOTG_DEBUG */ 114 #endif /* USB_DEBUG */ 115 116 #define MD_ROOT 0x0002 117 #define MD_CTRL 0x0004 118 #define MD_BULK 0x0008 119 120 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 121 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 122 #define MOTGHIST_FUNC() USBHIST_FUNC() 123 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 124 125 126 /* various timeouts, for various speeds */ 127 /* control NAK timeouts */ 128 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 129 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 130 131 /* intr/iso polling intervals */ 132 #define POLL_TO 100 /* 100 frames, about 0.1s */ 133 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 134 135 /* bulk NAK timeouts */ 136 #define NAK_TO_BULK 0 /* disabled */ 137 #define NAK_TO_BULK_HIGH 0 138 139 static void motg_hub_change(struct motg_softc *); 140 141 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 142 static usbd_status motg_root_intr_start(struct usbd_xfer *); 143 static void motg_root_intr_abort(struct usbd_xfer *); 144 static void motg_root_intr_close(struct usbd_pipe *); 145 static void motg_root_intr_done(struct usbd_xfer *); 146 147 static usbd_status motg_open(struct usbd_pipe *); 148 static void motg_poll(struct usbd_bus *); 149 static void motg_softintr(void *); 150 static struct usbd_xfer * 151 motg_allocx(struct usbd_bus *, unsigned int); 152 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 153 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 154 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 155 void *, int); 156 157 static void motg_noop(struct usbd_pipe *pipe); 158 static usbd_status motg_portreset(struct motg_softc*); 159 160 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 161 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 162 static void motg_device_ctrl_abort(struct usbd_xfer *); 163 static void motg_device_ctrl_close(struct usbd_pipe *); 164 static void motg_device_ctrl_done(struct usbd_xfer *); 165 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 166 static void motg_device_ctrl_read(struct usbd_xfer *); 167 static void motg_device_ctrl_intr_rx(struct motg_softc *); 168 static void motg_device_ctrl_intr_tx(struct motg_softc *); 169 170 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 171 static usbd_status motg_device_data_start(struct usbd_xfer *); 172 static usbd_status motg_device_data_start1(struct motg_softc *, 173 struct motg_hw_ep *); 174 static void motg_device_data_abort(struct usbd_xfer *); 175 static void motg_device_data_close(struct usbd_pipe *); 176 static void motg_device_data_done(struct usbd_xfer *); 177 static void motg_device_intr_rx(struct motg_softc *, int); 178 static void motg_device_intr_tx(struct motg_softc *, int); 179 static void motg_device_data_read(struct usbd_xfer *); 180 static void motg_device_data_write(struct usbd_xfer *); 181 182 static void motg_device_clear_toggle(struct usbd_pipe *); 183 static void motg_device_xfer_abort(struct usbd_xfer *); 184 185 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 186 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 187 #define UWRITE1(sc, r, x) \ 188 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 189 } while (/*CONSTCOND*/0) 190 #define UWRITE2(sc, r, x) \ 191 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 192 } while (/*CONSTCOND*/0) 193 #define UWRITE4(sc, r, x) \ 194 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 195 } while (/*CONSTCOND*/0) 196 197 static __inline uint32_t 198 UREAD1(struct motg_softc *sc, bus_size_t r) 199 { 200 201 UBARR(sc); 202 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 203 } 204 static __inline uint32_t 205 UREAD2(struct motg_softc *sc, bus_size_t r) 206 { 207 208 UBARR(sc); 209 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 210 } 211 212 #if 0 213 static __inline uint32_t 214 UREAD4(struct motg_softc *sc, bus_size_t r) 215 { 216 217 UBARR(sc); 218 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 219 } 220 #endif 221 222 static void 223 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 224 { 225 uint8_t val; 226 227 val = UREAD1(sc, MUSB2_REG_POWER); 228 if (on) 229 val |= MUSB2_MASK_SOFTC; 230 else 231 val &= ~MUSB2_MASK_SOFTC; 232 233 UWRITE1(sc, MUSB2_REG_POWER, val); 234 } 235 236 const struct usbd_bus_methods motg_bus_methods = { 237 .ubm_open = motg_open, 238 .ubm_softint = motg_softintr, 239 .ubm_dopoll = motg_poll, 240 .ubm_allocx = motg_allocx, 241 .ubm_freex = motg_freex, 242 .ubm_getlock = motg_get_lock, 243 .ubm_rhctrl = motg_roothub_ctrl, 244 }; 245 246 const struct usbd_pipe_methods motg_root_intr_methods = { 247 .upm_transfer = motg_root_intr_transfer, 248 .upm_start = motg_root_intr_start, 249 .upm_abort = motg_root_intr_abort, 250 .upm_close = motg_root_intr_close, 251 .upm_cleartoggle = motg_noop, 252 .upm_done = motg_root_intr_done, 253 }; 254 255 const struct usbd_pipe_methods motg_device_ctrl_methods = { 256 .upm_transfer = motg_device_ctrl_transfer, 257 .upm_start = motg_device_ctrl_start, 258 .upm_abort = motg_device_ctrl_abort, 259 .upm_close = motg_device_ctrl_close, 260 .upm_cleartoggle = motg_noop, 261 .upm_done = motg_device_ctrl_done, 262 }; 263 264 const struct usbd_pipe_methods motg_device_data_methods = { 265 .upm_transfer = motg_device_data_transfer, 266 .upm_start = motg_device_data_start, 267 .upm_abort = motg_device_data_abort, 268 .upm_close = motg_device_data_close, 269 .upm_cleartoggle = motg_device_clear_toggle, 270 .upm_done = motg_device_data_done, 271 }; 272 273 int 274 motg_init(struct motg_softc *sc) 275 { 276 uint32_t nrx, ntx, val; 277 int dynfifo; 278 int offset, i; 279 280 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 281 282 if (sc->sc_mode == MOTG_MODE_DEVICE) 283 return ENOTSUP; /* not supported */ 284 285 /* disable all interrupts */ 286 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 287 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 288 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 289 /* disable pullup */ 290 291 musbotg_pull_common(sc, 0); 292 293 #ifdef MUSB2_REG_RXDBDIS 294 /* disable double packet buffering XXX what's this ? */ 295 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 296 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 297 #endif 298 299 /* enable HighSpeed and ISO Update flags */ 300 301 UWRITE1(sc, MUSB2_REG_POWER, 302 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 303 304 if (sc->sc_mode == MOTG_MODE_DEVICE) { 305 /* clear Session bit, if set */ 306 val = UREAD1(sc, MUSB2_REG_DEVCTL); 307 val &= ~MUSB2_MASK_SESS; 308 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 309 } else { 310 /* Enter session for Host mode */ 311 val = UREAD1(sc, MUSB2_REG_DEVCTL); 312 val |= MUSB2_MASK_SESS; 313 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 314 } 315 delay(1000); 316 DPRINTF("DEVCTL 0x%jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 317 318 /* disable testmode */ 319 320 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 321 322 #ifdef MUSB2_REG_MISC 323 /* set default value */ 324 325 UWRITE1(sc, MUSB2_REG_MISC, 0); 326 #endif 327 328 /* select endpoint index 0 */ 329 330 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 331 332 if (sc->sc_ep_max == 0) { 333 /* read out number of endpoints */ 334 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 335 336 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 337 338 /* these numbers exclude the control endpoint */ 339 340 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 341 342 sc->sc_ep_max = MAX(nrx, ntx); 343 } else { 344 nrx = ntx = sc->sc_ep_max; 345 } 346 if (sc->sc_ep_max == 0) { 347 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 348 return -1; 349 } 350 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 351 /* read out configuration data */ 352 val = UREAD1(sc, MUSB2_REG_CONFDATA); 353 354 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 355 356 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 357 358 if (dynfifo) { 359 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 360 "assuming 16Kbytes of FIFO RAM\n"); 361 } 362 363 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 364 365 /* initialise endpoint profiles */ 366 sc->sc_in_ep[0].ep_fifo_size = 64; 367 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 368 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 369 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 370 offset = 64; 371 372 for (i = 1; i <= sc->sc_ep_max; i++) { 373 int fiforx_size, fifotx_size, fifo_size; 374 375 /* select endpoint */ 376 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 377 378 if (sc->sc_ep_fifosize) { 379 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 380 } else { 381 val = UREAD1(sc, MUSB2_REG_FSIZE); 382 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 383 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 384 } 385 386 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 387 i, fifotx_size, fiforx_size, dynfifo); 388 389 if (dynfifo) { 390 if (sc->sc_ep_fifosize) { 391 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 392 } else { 393 if (i < 3) { 394 fifo_size = 12; /* 4K */ 395 } else if (i < 10) { 396 fifo_size = 10; /* 1K */ 397 } else { 398 fifo_size = 7; /* 128 bytes */ 399 } 400 } 401 if (fiforx_size && (i <= nrx)) { 402 fiforx_size = fifo_size; 403 if (fifo_size > 7) { 404 #if 0 405 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 406 MUSB2_VAL_FIFOSZ(fifo_size) | 407 MUSB2_MASK_FIFODB); 408 #else 409 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 410 MUSB2_VAL_FIFOSZ(fifo_size)); 411 #endif 412 } else { 413 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 414 MUSB2_VAL_FIFOSZ(fifo_size)); 415 } 416 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 417 offset >> 3); 418 offset += (1 << fiforx_size); 419 } 420 if (fifotx_size && (i <= ntx)) { 421 fifotx_size = fifo_size; 422 if (fifo_size > 7) { 423 #if 0 424 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 425 MUSB2_VAL_FIFOSZ(fifo_size) | 426 MUSB2_MASK_FIFODB); 427 #else 428 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 429 MUSB2_VAL_FIFOSZ(fifo_size)); 430 #endif 431 } else { 432 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 433 MUSB2_VAL_FIFOSZ(fifo_size)); 434 } 435 436 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 437 offset >> 3); 438 439 offset += (1 << fifotx_size); 440 } 441 } 442 if (fiforx_size && (i <= nrx)) { 443 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 444 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 445 } 446 if (fifotx_size && (i <= ntx)) { 447 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 448 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 449 } 450 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 451 } 452 453 454 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 455 456 /* turn on default interrupts */ 457 458 if (sc->sc_mode == MOTG_MODE_HOST) { 459 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 460 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 461 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 462 } else 463 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 464 465 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 466 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 467 468 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 469 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 470 471 /* Set up the bus struct. */ 472 sc->sc_bus.ub_methods = &motg_bus_methods; 473 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 474 sc->sc_bus.ub_revision = USBREV_2_0; 475 sc->sc_bus.ub_usedma = false; 476 sc->sc_bus.ub_hcpriv = sc; 477 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 478 "Mentor Graphics"); 479 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 480 return 0; 481 } 482 483 static int 484 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 485 { 486 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 487 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 488 struct motg_hw_ep *ep; 489 int i, size; 490 491 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 492 493 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 494 sc->sc_in_ep : sc->sc_out_ep; 495 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 496 497 for (i = sc->sc_ep_max; i >= 1; i--) { 498 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 499 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 500 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 501 ep[i].ep_fifo_size, size, ep[i].refcount); 502 if (ep[i].ep_fifo_size >= size) { 503 /* found a suitable endpoint */ 504 otgpipe->hw_ep = &ep[i]; 505 mutex_enter(&sc->sc_lock); 506 if (otgpipe->hw_ep->refcount > 0) { 507 /* no luck, try next */ 508 mutex_exit(&sc->sc_lock); 509 otgpipe->hw_ep = NULL; 510 } else { 511 otgpipe->hw_ep->refcount++; 512 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 513 otgpipe, ep_pipe_list); 514 mutex_exit(&sc->sc_lock); 515 return 0; 516 } 517 } 518 } 519 return -1; 520 } 521 522 /* Open a new pipe. */ 523 usbd_status 524 motg_open(struct usbd_pipe *pipe) 525 { 526 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 527 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 528 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 529 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 530 531 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 532 533 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 534 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 535 536 if (sc->sc_dying) 537 return USBD_IOERROR; 538 539 /* toggle state needed for bulk endpoints */ 540 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 541 542 if (pipe->up_dev->ud_addr == rhaddr) { 543 switch (ed->bEndpointAddress) { 544 case USB_CONTROL_ENDPOINT: 545 pipe->up_methods = &roothub_ctrl_methods; 546 break; 547 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 548 pipe->up_methods = &motg_root_intr_methods; 549 break; 550 default: 551 return USBD_INVAL; 552 } 553 } else { 554 switch (ed->bmAttributes & UE_XFERTYPE) { 555 case UE_CONTROL: 556 pipe->up_methods = &motg_device_ctrl_methods; 557 /* always use sc_in_ep[0] for in and out */ 558 otgpipe->hw_ep = &sc->sc_in_ep[0]; 559 mutex_enter(&sc->sc_lock); 560 otgpipe->hw_ep->refcount++; 561 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 562 otgpipe, ep_pipe_list); 563 mutex_exit(&sc->sc_lock); 564 break; 565 case UE_BULK: 566 case UE_INTERRUPT: 567 DPRINTFN(MD_BULK, 568 "type %jd dir %jd pipe wMaxPacketSize %jd", 569 UE_GET_XFERTYPE(ed->bmAttributes), 570 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 571 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 572 if (motg_select_ep(sc, pipe) != 0) 573 goto bad; 574 KASSERT(otgpipe->hw_ep != NULL); 575 pipe->up_methods = &motg_device_data_methods; 576 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 577 break; 578 default: 579 goto bad; 580 #ifdef notyet 581 case UE_ISOCHRONOUS: 582 ... 583 break; 584 #endif /* notyet */ 585 } 586 } 587 return USBD_NORMAL_COMPLETION; 588 589 bad: 590 return USBD_NOMEM; 591 } 592 593 void 594 motg_softintr(void *v) 595 { 596 struct usbd_bus *bus = v; 597 struct motg_softc *sc = MOTG_BUS2SC(bus); 598 uint16_t rx_status, tx_status; 599 uint8_t ctrl_status; 600 uint32_t val; 601 int i; 602 603 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 604 605 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 606 607 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 608 609 mutex_spin_enter(&sc->sc_intr_lock); 610 rx_status = sc->sc_intr_rx_ep; 611 sc->sc_intr_rx_ep = 0; 612 tx_status = sc->sc_intr_tx_ep; 613 sc->sc_intr_tx_ep = 0; 614 ctrl_status = sc->sc_intr_ctrl; 615 sc->sc_intr_ctrl = 0; 616 mutex_spin_exit(&sc->sc_intr_lock); 617 618 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 619 620 if (ctrl_status & (MUSB2_MASK_IRESET | 621 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 622 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 623 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%jx", ctrl_status, 0, 0, 0); 624 625 if (ctrl_status & MUSB2_MASK_IRESET) { 626 sc->sc_isreset = 1; 627 sc->sc_port_suspended = 0; 628 sc->sc_port_suspended_change = 1; 629 sc->sc_connected_changed = 1; 630 sc->sc_port_enabled = 1; 631 632 val = UREAD1(sc, MUSB2_REG_POWER); 633 if (val & MUSB2_MASK_HSMODE) 634 sc->sc_high_speed = 1; 635 else 636 sc->sc_high_speed = 0; 637 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 638 0, 0, 0); 639 640 /* turn off interrupts */ 641 val = MUSB2_MASK_IRESET; 642 val &= ~MUSB2_MASK_IRESUME; 643 val |= MUSB2_MASK_ISUSP; 644 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 645 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 646 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 647 } 648 if (ctrl_status & MUSB2_MASK_IRESUME) { 649 if (sc->sc_port_suspended) { 650 sc->sc_port_suspended = 0; 651 sc->sc_port_suspended_change = 1; 652 val = UREAD1(sc, MUSB2_REG_INTUSBE); 653 /* disable resume interrupt */ 654 val &= ~MUSB2_MASK_IRESUME; 655 /* enable suspend interrupt */ 656 val |= MUSB2_MASK_ISUSP; 657 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 658 } 659 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 660 if (!sc->sc_port_suspended) { 661 sc->sc_port_suspended = 1; 662 sc->sc_port_suspended_change = 1; 663 664 val = UREAD1(sc, MUSB2_REG_INTUSBE); 665 /* disable suspend interrupt */ 666 val &= ~MUSB2_MASK_ISUSP; 667 /* enable resume interrupt */ 668 val |= MUSB2_MASK_IRESUME; 669 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 670 } 671 } 672 if (ctrl_status & MUSB2_MASK_ICONN) { 673 sc->sc_connected = 1; 674 sc->sc_connected_changed = 1; 675 sc->sc_isreset = 1; 676 sc->sc_port_enabled = 1; 677 } else if (ctrl_status & MUSB2_MASK_IDISC) { 678 sc->sc_connected = 0; 679 sc->sc_connected_changed = 1; 680 sc->sc_isreset = 0; 681 sc->sc_port_enabled = 0; 682 } 683 684 /* complete root HUB interrupt endpoint */ 685 686 motg_hub_change(sc); 687 } 688 /* 689 * read in interrupt status and mix with the status we 690 * got from the wrapper 691 */ 692 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 693 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 694 695 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 696 if (tx_status & 0x01) 697 motg_device_ctrl_intr_tx(sc); 698 for (i = 1; i <= sc->sc_ep_max; i++) { 699 if (rx_status & (0x01 << i)) 700 motg_device_intr_rx(sc, i); 701 if (tx_status & (0x01 << i)) 702 motg_device_intr_tx(sc, i); 703 } 704 return; 705 } 706 707 void 708 motg_poll(struct usbd_bus *bus) 709 { 710 struct motg_softc *sc = MOTG_BUS2SC(bus); 711 712 sc->sc_intr_poll(sc->sc_intr_poll_arg); 713 mutex_enter(&sc->sc_lock); 714 motg_softintr(bus); 715 mutex_exit(&sc->sc_lock); 716 } 717 718 int 719 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 720 uint8_t ctrl) 721 { 722 KASSERT(mutex_owned(&sc->sc_intr_lock)); 723 sc->sc_intr_tx_ep = tx_ep; 724 sc->sc_intr_rx_ep = rx_ep; 725 sc->sc_intr_ctrl = ctrl; 726 727 if (!sc->sc_bus.ub_usepolling) { 728 usb_schedsoftintr(&sc->sc_bus); 729 } 730 return 1; 731 } 732 733 int 734 motg_intr_vbus(struct motg_softc *sc, int vbus) 735 { 736 uint8_t val; 737 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 738 739 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 740 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 741 /* try to re-enter session for Host mode */ 742 val = UREAD1(sc, MUSB2_REG_DEVCTL); 743 val |= MUSB2_MASK_SESS; 744 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 745 } 746 return 1; 747 } 748 749 struct usbd_xfer * 750 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 751 { 752 struct motg_softc *sc = MOTG_BUS2SC(bus); 753 struct usbd_xfer *xfer; 754 755 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 756 if (xfer != NULL) { 757 memset(xfer, 0, sizeof(struct motg_xfer)); 758 #ifdef DIAGNOSTIC 759 xfer->ux_state = XFER_BUSY; 760 #endif 761 } 762 return xfer; 763 } 764 765 void 766 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 767 { 768 struct motg_softc *sc = MOTG_BUS2SC(bus); 769 770 #ifdef DIAGNOSTIC 771 if (xfer->ux_state != XFER_BUSY) { 772 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 773 xfer->ux_state); 774 } 775 xfer->ux_state = XFER_FREE; 776 #endif 777 pool_cache_put(sc->sc_xferpool, xfer); 778 } 779 780 static void 781 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 782 { 783 struct motg_softc *sc = MOTG_BUS2SC(bus); 784 785 *lock = &sc->sc_lock; 786 } 787 788 /* 789 * Routines to emulate the root hub. 790 */ 791 Static int 792 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 793 void *buf, int buflen) 794 { 795 struct motg_softc *sc = MOTG_BUS2SC(bus); 796 int status, change, totlen = 0; 797 uint16_t len, value, index; 798 usb_port_status_t ps; 799 usbd_status err; 800 uint32_t val; 801 802 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 803 804 if (sc->sc_dying) 805 return -1; 806 807 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 808 req->bRequest, 0, 0); 809 810 len = UGETW(req->wLength); 811 value = UGETW(req->wValue); 812 index = UGETW(req->wIndex); 813 814 #define C(x,y) ((x) | ((y) << 8)) 815 switch (C(req->bRequest, req->bmRequestType)) { 816 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 817 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 818 switch (value) { 819 case C(0, UDESC_DEVICE): { 820 usb_device_descriptor_t devd; 821 822 totlen = min(buflen, sizeof(devd)); 823 memcpy(&devd, buf, totlen); 824 USETW(devd.idVendor, sc->sc_id_vendor); 825 memcpy(buf, &devd, totlen); 826 break; 827 } 828 case C(1, UDESC_STRING): 829 #define sd ((usb_string_descriptor_t *)buf) 830 /* Vendor */ 831 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 832 break; 833 case C(2, UDESC_STRING): 834 /* Product */ 835 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 836 break; 837 #undef sd 838 default: 839 /* default from usbroothub */ 840 return buflen; 841 } 842 break; 843 /* Hub requests */ 844 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 845 break; 846 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 847 DPRINTFN(MD_ROOT, 848 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 849 0, 0); 850 if (index != 1) { 851 return -1; 852 } 853 switch (value) { 854 case UHF_PORT_ENABLE: 855 sc->sc_port_enabled = 0; 856 break; 857 case UHF_PORT_SUSPEND: 858 if (sc->sc_port_suspended != 0) { 859 val = UREAD1(sc, MUSB2_REG_POWER); 860 val &= ~MUSB2_MASK_SUSPMODE; 861 val |= MUSB2_MASK_RESUME; 862 UWRITE1(sc, MUSB2_REG_POWER, val); 863 /* wait 20 milliseconds */ 864 usb_delay_ms(&sc->sc_bus, 20); 865 val = UREAD1(sc, MUSB2_REG_POWER); 866 val &= ~MUSB2_MASK_RESUME; 867 UWRITE1(sc, MUSB2_REG_POWER, val); 868 sc->sc_port_suspended = 0; 869 sc->sc_port_suspended_change = 1; 870 } 871 break; 872 case UHF_PORT_RESET: 873 break; 874 case UHF_C_PORT_CONNECTION: 875 break; 876 case UHF_C_PORT_ENABLE: 877 break; 878 case UHF_C_PORT_OVER_CURRENT: 879 break; 880 case UHF_C_PORT_RESET: 881 sc->sc_isreset = 0; 882 break; 883 case UHF_PORT_POWER: 884 /* XXX todo */ 885 break; 886 case UHF_PORT_CONNECTION: 887 case UHF_PORT_OVER_CURRENT: 888 case UHF_PORT_LOW_SPEED: 889 case UHF_C_PORT_SUSPEND: 890 default: 891 return -1; 892 } 893 break; 894 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 895 return -1; 896 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 897 if (len == 0) 898 break; 899 if ((value & 0xff) != 0) { 900 return -1; 901 } 902 totlen = buflen; 903 break; 904 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 905 if (len != 4) { 906 return -1; 907 } 908 memset(buf, 0, len); 909 totlen = len; 910 break; 911 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 912 if (index != 1) { 913 return -1; 914 } 915 if (len != 4) { 916 return -1; 917 } 918 status = change = 0; 919 if (sc->sc_connected) 920 status |= UPS_CURRENT_CONNECT_STATUS; 921 if (sc->sc_connected_changed) { 922 change |= UPS_C_CONNECT_STATUS; 923 sc->sc_connected_changed = 0; 924 } 925 if (sc->sc_port_enabled) 926 status |= UPS_PORT_ENABLED; 927 if (sc->sc_port_enabled_changed) { 928 change |= UPS_C_PORT_ENABLED; 929 sc->sc_port_enabled_changed = 0; 930 } 931 if (sc->sc_port_suspended) 932 status |= UPS_SUSPEND; 933 if (sc->sc_high_speed) 934 status |= UPS_HIGH_SPEED; 935 status |= UPS_PORT_POWER; /* XXX */ 936 if (sc->sc_isreset) 937 change |= UPS_C_PORT_RESET; 938 USETW(ps.wPortStatus, status); 939 USETW(ps.wPortChange, change); 940 totlen = min(len, sizeof(ps)); 941 memcpy(buf, &ps, totlen); 942 break; 943 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 944 return -1; 945 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 946 break; 947 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 948 if (index != 1) { 949 return -1; 950 } 951 switch(value) { 952 case UHF_PORT_ENABLE: 953 sc->sc_port_enabled = 1; 954 break; 955 case UHF_PORT_SUSPEND: 956 if (sc->sc_port_suspended == 0) { 957 val = UREAD1(sc, MUSB2_REG_POWER); 958 val |= MUSB2_MASK_SUSPMODE; 959 UWRITE1(sc, MUSB2_REG_POWER, val); 960 /* wait 20 milliseconds */ 961 usb_delay_ms(&sc->sc_bus, 20); 962 sc->sc_port_suspended = 1; 963 sc->sc_port_suspended_change = 1; 964 } 965 break; 966 case UHF_PORT_RESET: 967 err = motg_portreset(sc); 968 if (err != USBD_NORMAL_COMPLETION) 969 return -1; 970 return 0; 971 case UHF_PORT_POWER: 972 /* XXX todo */ 973 return 0; 974 case UHF_C_PORT_CONNECTION: 975 case UHF_C_PORT_ENABLE: 976 case UHF_C_PORT_OVER_CURRENT: 977 case UHF_PORT_CONNECTION: 978 case UHF_PORT_OVER_CURRENT: 979 case UHF_PORT_LOW_SPEED: 980 case UHF_C_PORT_SUSPEND: 981 case UHF_C_PORT_RESET: 982 default: 983 return -1; 984 } 985 break; 986 default: 987 /* default from usbroothub */ 988 return buflen; 989 } 990 991 return totlen; 992 } 993 994 /* Abort a root interrupt request. */ 995 void 996 motg_root_intr_abort(struct usbd_xfer *xfer) 997 { 998 struct motg_softc *sc = MOTG_XFER2SC(xfer); 999 1000 KASSERT(mutex_owned(&sc->sc_lock)); 1001 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 1002 1003 sc->sc_intr_xfer = NULL; 1004 1005 xfer->ux_status = USBD_CANCELLED; 1006 usb_transfer_complete(xfer); 1007 } 1008 1009 usbd_status 1010 motg_root_intr_transfer(struct usbd_xfer *xfer) 1011 { 1012 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1013 usbd_status err; 1014 1015 /* Insert last in queue. */ 1016 mutex_enter(&sc->sc_lock); 1017 err = usb_insert_transfer(xfer); 1018 mutex_exit(&sc->sc_lock); 1019 if (err) 1020 return err; 1021 1022 /* 1023 * Pipe isn't running (otherwise err would be USBD_INPROG), 1024 * start first 1025 */ 1026 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1027 } 1028 1029 /* Start a transfer on the root interrupt pipe */ 1030 usbd_status 1031 motg_root_intr_start(struct usbd_xfer *xfer) 1032 { 1033 struct usbd_pipe *pipe = xfer->ux_pipe; 1034 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1035 1036 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1037 1038 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1039 xfer->ux_length, xfer->ux_flags, 0); 1040 1041 if (sc->sc_dying) 1042 return USBD_IOERROR; 1043 1044 sc->sc_intr_xfer = xfer; 1045 return USBD_IN_PROGRESS; 1046 } 1047 1048 /* Close the root interrupt pipe. */ 1049 void 1050 motg_root_intr_close(struct usbd_pipe *pipe) 1051 { 1052 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1053 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1054 1055 KASSERT(mutex_owned(&sc->sc_lock)); 1056 1057 sc->sc_intr_xfer = NULL; 1058 } 1059 1060 void 1061 motg_root_intr_done(struct usbd_xfer *xfer) 1062 { 1063 } 1064 1065 void 1066 motg_noop(struct usbd_pipe *pipe) 1067 { 1068 } 1069 1070 static usbd_status 1071 motg_portreset(struct motg_softc *sc) 1072 { 1073 uint32_t val; 1074 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1075 1076 val = UREAD1(sc, MUSB2_REG_POWER); 1077 val |= MUSB2_MASK_RESET; 1078 UWRITE1(sc, MUSB2_REG_POWER, val); 1079 /* Wait for 20 msec */ 1080 usb_delay_ms(&sc->sc_bus, 20); 1081 1082 val = UREAD1(sc, MUSB2_REG_POWER); 1083 val &= ~MUSB2_MASK_RESET; 1084 UWRITE1(sc, MUSB2_REG_POWER, val); 1085 1086 /* determine line speed */ 1087 val = UREAD1(sc, MUSB2_REG_POWER); 1088 if (val & MUSB2_MASK_HSMODE) 1089 sc->sc_high_speed = 1; 1090 else 1091 sc->sc_high_speed = 0; 1092 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1093 1094 sc->sc_isreset = 1; 1095 sc->sc_port_enabled = 1; 1096 return USBD_NORMAL_COMPLETION; 1097 } 1098 1099 /* 1100 * This routine is executed when an interrupt on the root hub is detected 1101 */ 1102 static void 1103 motg_hub_change(struct motg_softc *sc) 1104 { 1105 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1106 struct usbd_pipe *pipe; 1107 u_char *p; 1108 1109 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1110 1111 if (xfer == NULL) 1112 return; /* the interrupt pipe is not open */ 1113 1114 pipe = xfer->ux_pipe; 1115 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1116 return; /* device has detached */ 1117 1118 p = xfer->ux_buf; 1119 p[0] = 1<<1; 1120 xfer->ux_actlen = 1; 1121 xfer->ux_status = USBD_NORMAL_COMPLETION; 1122 usb_transfer_complete(xfer); 1123 } 1124 1125 static uint8_t 1126 motg_speed(uint8_t speed) 1127 { 1128 switch(speed) { 1129 case USB_SPEED_LOW: 1130 return MUSB2_MASK_TI_SPEED_LO; 1131 case USB_SPEED_FULL: 1132 return MUSB2_MASK_TI_SPEED_FS; 1133 case USB_SPEED_HIGH: 1134 return MUSB2_MASK_TI_SPEED_HS; 1135 default: 1136 panic("motg: unknown speed %d", speed); 1137 /* NOTREACHED */ 1138 } 1139 } 1140 1141 static uint8_t 1142 motg_type(uint8_t type) 1143 { 1144 switch(type) { 1145 case UE_CONTROL: 1146 return MUSB2_MASK_TI_PROTO_CTRL; 1147 case UE_ISOCHRONOUS: 1148 return MUSB2_MASK_TI_PROTO_ISOC; 1149 case UE_BULK: 1150 return MUSB2_MASK_TI_PROTO_BULK; 1151 case UE_INTERRUPT: 1152 return MUSB2_MASK_TI_PROTO_INTR; 1153 default: 1154 panic("motg: unknown type %d", type); 1155 /* NOTREACHED */ 1156 } 1157 } 1158 1159 static void 1160 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1161 { 1162 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1163 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1164 struct usbd_device *dev = otgpipe->pipe.up_dev; 1165 int epnumber = otgpipe->hw_ep->ep_number; 1166 1167 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1168 if (dev->ud_myhsport) { 1169 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1170 dev->ud_myhsport->up_parent->ud_addr); 1171 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1172 dev->ud_myhsport->up_portno); 1173 } else { 1174 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1175 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1176 } 1177 UWRITE1(sc, MUSB2_REG_TXTI, 1178 motg_speed(dev->ud_speed) | 1179 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1180 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1181 ); 1182 if (epnumber == 0) { 1183 if (sc->sc_high_speed) { 1184 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1185 NAK_TO_CTRL_HIGH); 1186 } else { 1187 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1188 } 1189 } else { 1190 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1191 == UE_BULK) { 1192 if (sc->sc_high_speed) { 1193 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1194 NAK_TO_BULK_HIGH); 1195 } else { 1196 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1197 } 1198 } else { 1199 if (sc->sc_high_speed) { 1200 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1201 } else { 1202 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1203 } 1204 } 1205 } 1206 } 1207 1208 static void 1209 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1210 { 1211 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1212 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1213 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1214 int epnumber = otgpipe->hw_ep->ep_number; 1215 1216 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1217 if (dev->ud_myhsport) { 1218 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1219 dev->ud_myhsport->up_parent->ud_addr); 1220 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1221 dev->ud_myhsport->up_portno); 1222 } else { 1223 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1224 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1225 } 1226 UWRITE1(sc, MUSB2_REG_RXTI, 1227 motg_speed(dev->ud_speed) | 1228 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1229 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1230 ); 1231 if (epnumber == 0) { 1232 if (sc->sc_high_speed) { 1233 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1234 NAK_TO_CTRL_HIGH); 1235 } else { 1236 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1237 } 1238 } else { 1239 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1240 == UE_BULK) { 1241 if (sc->sc_high_speed) { 1242 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1243 NAK_TO_BULK_HIGH); 1244 } else { 1245 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1246 } 1247 } else { 1248 if (sc->sc_high_speed) { 1249 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1250 } else { 1251 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1252 } 1253 } 1254 } 1255 } 1256 1257 static usbd_status 1258 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1259 { 1260 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1261 usbd_status err; 1262 1263 /* Insert last in queue. */ 1264 mutex_enter(&sc->sc_lock); 1265 err = usb_insert_transfer(xfer); 1266 xfer->ux_status = USBD_NOT_STARTED; 1267 mutex_exit(&sc->sc_lock); 1268 if (err) 1269 return err; 1270 1271 /* 1272 * Pipe isn't running (otherwise err would be USBD_INPROG), 1273 * so start it first. 1274 */ 1275 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1276 } 1277 1278 static usbd_status 1279 motg_device_ctrl_start(struct usbd_xfer *xfer) 1280 { 1281 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1282 usbd_status err; 1283 mutex_enter(&sc->sc_lock); 1284 err = motg_device_ctrl_start1(sc); 1285 mutex_exit(&sc->sc_lock); 1286 if (err != USBD_IN_PROGRESS) 1287 return err; 1288 return USBD_IN_PROGRESS; 1289 } 1290 1291 static usbd_status 1292 motg_device_ctrl_start1(struct motg_softc *sc) 1293 { 1294 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1295 struct usbd_xfer *xfer = NULL; 1296 struct motg_pipe *otgpipe; 1297 usbd_status err = 0; 1298 1299 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1300 1301 KASSERT(mutex_owned(&sc->sc_lock)); 1302 if (sc->sc_dying) 1303 return USBD_IOERROR; 1304 1305 if (!sc->sc_connected) 1306 return USBD_IOERROR; 1307 1308 if (ep->xfer != NULL) { 1309 err = USBD_IN_PROGRESS; 1310 goto end; 1311 } 1312 /* locate the first pipe with work to do */ 1313 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1314 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1315 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1316 (uintptr_t)otgpipe, (uintptr_t)xfer, 1317 (xfer != NULL) ? xfer->ux_status : 0, 0); 1318 1319 if (xfer != NULL) { 1320 /* move this pipe to the end of the list */ 1321 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1322 motg_pipe, ep_pipe_list); 1323 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1324 otgpipe, ep_pipe_list); 1325 break; 1326 } 1327 } 1328 if (xfer == NULL) { 1329 err = USBD_NOT_STARTED; 1330 goto end; 1331 } 1332 xfer->ux_status = USBD_IN_PROGRESS; 1333 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1334 KASSERT(otgpipe->hw_ep == ep); 1335 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1336 // KASSERT(xfer->ux_actlen == 0); 1337 xfer->ux_actlen = 0; 1338 1339 ep->xfer = xfer; 1340 ep->datalen = xfer->ux_length; 1341 if (ep->datalen > 0) 1342 ep->data = xfer->ux_buf; 1343 else 1344 ep->data = NULL; 1345 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1346 (ep->datalen % 64) == 0) 1347 ep->need_short_xfer = 1; 1348 else 1349 ep->need_short_xfer = 0; 1350 /* now we need send this request */ 1351 DPRINTFN(MD_CTRL, 1352 "xfer %#jx send data %#jx len %jd short %jd", 1353 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1354 ep->need_short_xfer); 1355 DPRINTFN(MD_CTRL, 1356 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1357 xfer->ux_pipe->up_dev->ud_speed, 1358 xfer->ux_pipe->up_dev->ud_addr, 0); 1359 KASSERT(ep->phase == IDLE); 1360 ep->phase = SETUP; 1361 /* select endpoint 0 */ 1362 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1363 /* fifo should be empty at this point */ 1364 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1365 /* send data */ 1366 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1367 KASSERT(sizeof(xfer->ux_request) == 8); 1368 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1369 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1370 1371 motg_setup_endpoint_tx(xfer); 1372 /* start transaction */ 1373 UWRITE1(sc, MUSB2_REG_TXCSRL, 1374 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1375 1376 end: 1377 if (err) 1378 return err; 1379 1380 return USBD_IN_PROGRESS; 1381 } 1382 1383 static void 1384 motg_device_ctrl_read(struct usbd_xfer *xfer) 1385 { 1386 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1387 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1388 /* assume endpoint already selected */ 1389 motg_setup_endpoint_rx(xfer); 1390 /* start transaction */ 1391 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1392 otgpipe->hw_ep->phase = DATA_IN; 1393 } 1394 1395 static void 1396 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1397 { 1398 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1399 struct usbd_xfer *xfer = ep->xfer; 1400 uint8_t csr; 1401 int datalen, max_datalen; 1402 char *data; 1403 bool got_short; 1404 usbd_status new_status = USBD_IN_PROGRESS; 1405 1406 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1407 1408 KASSERT(mutex_owned(&sc->sc_lock)); 1409 1410 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1411 /* select endpoint 0 */ 1412 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1413 1414 /* read out FIFO status */ 1415 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1416 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1417 ep->phase, csr, (uintptr_t)xfer, 1418 (xfer != NULL) ? xfer->ux_status : 0); 1419 1420 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1421 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1422 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1423 1424 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1425 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1426 new_status = USBD_TIMEOUT; /* XXX */ 1427 goto complete; 1428 } 1429 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1430 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1431 new_status = USBD_STALLED; 1432 else 1433 new_status = USBD_IOERROR; 1434 /* clear status */ 1435 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1436 goto complete; 1437 } 1438 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1439 return; /* no data yet */ 1440 1441 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1442 goto complete; 1443 1444 if (ep->phase == STATUS_IN) { 1445 new_status = USBD_NORMAL_COMPLETION; 1446 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1447 goto complete; 1448 } 1449 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1450 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1451 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1452 max_datalen = min(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1453 ep->datalen); 1454 if (datalen > max_datalen) { 1455 new_status = USBD_IOERROR; 1456 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1457 goto complete; 1458 } 1459 got_short = (datalen < max_datalen); 1460 if (datalen > 0) { 1461 KASSERT(ep->phase == DATA_IN); 1462 data = ep->data; 1463 ep->data += datalen; 1464 ep->datalen -= datalen; 1465 xfer->ux_actlen += datalen; 1466 if (((vaddr_t)data & 0x3) == 0 && 1467 (datalen >> 2) > 0) { 1468 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1469 (uintptr_t)data, datalen, 0, 0); 1470 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1471 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1472 data += (datalen & ~0x3); 1473 datalen -= (datalen & ~0x3); 1474 } 1475 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1476 datalen, 0, 0); 1477 if (datalen) { 1478 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1479 MUSB2_REG_EPFIFO(0), data, datalen); 1480 } 1481 } 1482 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1483 KASSERT(ep->phase == DATA_IN); 1484 if (got_short || (ep->datalen == 0)) { 1485 if (ep->need_short_xfer == 0) { 1486 ep->phase = STATUS_OUT; 1487 UWRITE1(sc, MUSB2_REG_TXCSRH, 1488 UREAD1(sc, MUSB2_REG_TXCSRH) | 1489 MUSB2_MASK_CSR0H_PING_DIS); 1490 motg_setup_endpoint_tx(xfer); 1491 UWRITE1(sc, MUSB2_REG_TXCSRL, 1492 MUSB2_MASK_CSR0L_STATUSPKT | 1493 MUSB2_MASK_CSR0L_TXPKTRDY); 1494 return; 1495 } 1496 ep->need_short_xfer = 0; 1497 } 1498 motg_device_ctrl_read(xfer); 1499 return; 1500 complete: 1501 ep->phase = IDLE; 1502 ep->xfer = NULL; 1503 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1504 KASSERT(new_status != USBD_IN_PROGRESS); 1505 xfer->ux_status = new_status; 1506 usb_transfer_complete(xfer); 1507 } 1508 motg_device_ctrl_start1(sc); 1509 } 1510 1511 static void 1512 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1513 { 1514 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1515 struct usbd_xfer *xfer = ep->xfer; 1516 uint8_t csr; 1517 int datalen; 1518 char *data; 1519 usbd_status new_status = USBD_IN_PROGRESS; 1520 1521 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1522 1523 KASSERT(mutex_owned(&sc->sc_lock)); 1524 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1525 motg_device_ctrl_intr_rx(sc); 1526 return; 1527 } 1528 1529 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1530 ep->phase == STATUS_OUT); 1531 1532 /* select endpoint 0 */ 1533 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1534 1535 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1536 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1537 ep->phase, csr, (uintptr_t)xfer, 1538 (xfer != NULL) ? xfer->ux_status : 0); 1539 1540 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1541 /* command not accepted */ 1542 new_status = USBD_STALLED; 1543 /* clear status */ 1544 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1545 goto complete; 1546 } 1547 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1548 new_status = USBD_TIMEOUT; /* XXX */ 1549 /* flush fifo */ 1550 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1551 UWRITE1(sc, MUSB2_REG_TXCSRH, 1552 UREAD1(sc, MUSB2_REG_TXCSRH) | 1553 MUSB2_MASK_CSR0H_FFLUSH); 1554 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1555 } 1556 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1557 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1558 goto complete; 1559 } 1560 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1561 new_status = USBD_IOERROR; 1562 /* clear status */ 1563 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1564 goto complete; 1565 } 1566 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1567 /* data still not sent */ 1568 return; 1569 } 1570 if (xfer == NULL) 1571 goto complete; 1572 if (ep->phase == STATUS_OUT) { 1573 /* 1574 * we have sent status and got no error; 1575 * declare transfer complete 1576 */ 1577 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1578 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1579 new_status = USBD_NORMAL_COMPLETION; 1580 goto complete; 1581 } 1582 if (ep->datalen == 0) { 1583 if (ep->need_short_xfer) { 1584 ep->need_short_xfer = 0; 1585 /* one more data phase */ 1586 if (xfer->ux_request.bmRequestType & UT_READ) { 1587 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1588 (uintptr_t)xfer, 0, 0, 0); 1589 motg_device_ctrl_read(xfer); 1590 return; 1591 } /* else fall back to DATA_OUT */ 1592 } else { 1593 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh 0x%jx", 1594 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1595 0, 0); 1596 ep->phase = STATUS_IN; 1597 UWRITE1(sc, MUSB2_REG_RXCSRH, 1598 UREAD1(sc, MUSB2_REG_RXCSRH) | 1599 MUSB2_MASK_CSR0H_PING_DIS); 1600 motg_setup_endpoint_rx(xfer); 1601 UWRITE1(sc, MUSB2_REG_TXCSRL, 1602 MUSB2_MASK_CSR0L_STATUSPKT | 1603 MUSB2_MASK_CSR0L_REQPKT); 1604 return; 1605 } 1606 } 1607 if (xfer->ux_request.bmRequestType & UT_READ) { 1608 motg_device_ctrl_read(xfer); 1609 return; 1610 } 1611 /* setup a dataout phase */ 1612 datalen = min(ep->datalen, 1613 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1614 ep->phase = DATA_OUT; 1615 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh 0x%jx", (uintptr_t)xfer, 1616 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1617 if (datalen) { 1618 data = ep->data; 1619 ep->data += datalen; 1620 ep->datalen -= datalen; 1621 xfer->ux_actlen += datalen; 1622 if (((vaddr_t)data & 0x3) == 0 && 1623 (datalen >> 2) > 0) { 1624 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1625 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1626 data += (datalen & ~0x3); 1627 datalen -= (datalen & ~0x3); 1628 } 1629 if (datalen) { 1630 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1631 MUSB2_REG_EPFIFO(0), data, datalen); 1632 } 1633 } 1634 /* send data */ 1635 motg_setup_endpoint_tx(xfer); 1636 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1637 return; 1638 1639 complete: 1640 ep->phase = IDLE; 1641 ep->xfer = NULL; 1642 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1643 KASSERT(new_status != USBD_IN_PROGRESS); 1644 xfer->ux_status = new_status; 1645 usb_transfer_complete(xfer); 1646 } 1647 motg_device_ctrl_start1(sc); 1648 } 1649 1650 /* Abort a device control request. */ 1651 void 1652 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1653 { 1654 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1655 1656 motg_device_xfer_abort(xfer); 1657 } 1658 1659 /* Close a device control pipe */ 1660 void 1661 motg_device_ctrl_close(struct usbd_pipe *pipe) 1662 { 1663 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1664 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1665 struct motg_pipe *otgpipeiter; 1666 1667 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1668 1669 KASSERT(mutex_owned(&sc->sc_lock)); 1670 KASSERT(otgpipe->hw_ep->xfer == NULL || 1671 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1672 1673 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1674 if (otgpipeiter == otgpipe) { 1675 /* remove from list */ 1676 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1677 motg_pipe, ep_pipe_list); 1678 otgpipe->hw_ep->refcount--; 1679 /* we're done */ 1680 return; 1681 } 1682 } 1683 panic("motg_device_ctrl_close: not found"); 1684 } 1685 1686 void 1687 motg_device_ctrl_done(struct usbd_xfer *xfer) 1688 { 1689 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1690 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1691 1692 KASSERT(otgpipe->hw_ep->xfer != xfer); 1693 } 1694 1695 static usbd_status 1696 motg_device_data_transfer(struct usbd_xfer *xfer) 1697 { 1698 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1699 usbd_status err; 1700 1701 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1702 1703 /* Insert last in queue. */ 1704 mutex_enter(&sc->sc_lock); 1705 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1706 err = usb_insert_transfer(xfer); 1707 xfer->ux_status = USBD_NOT_STARTED; 1708 mutex_exit(&sc->sc_lock); 1709 if (err) 1710 return err; 1711 1712 /* 1713 * Pipe isn't running (otherwise err would be USBD_INPROG), 1714 * so start it first. 1715 */ 1716 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1717 } 1718 1719 static usbd_status 1720 motg_device_data_start(struct usbd_xfer *xfer) 1721 { 1722 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1723 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1724 usbd_status err; 1725 1726 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1727 1728 mutex_enter(&sc->sc_lock); 1729 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1730 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1731 mutex_exit(&sc->sc_lock); 1732 if (err != USBD_IN_PROGRESS) 1733 return err; 1734 return USBD_IN_PROGRESS; 1735 } 1736 1737 static usbd_status 1738 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1739 { 1740 struct usbd_xfer *xfer = NULL; 1741 struct motg_pipe *otgpipe; 1742 usbd_status err = 0; 1743 uint32_t val __diagused; 1744 1745 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1746 1747 KASSERT(mutex_owned(&sc->sc_lock)); 1748 if (sc->sc_dying) 1749 return USBD_IOERROR; 1750 1751 if (!sc->sc_connected) 1752 return USBD_IOERROR; 1753 1754 if (ep->xfer != NULL) { 1755 err = USBD_IN_PROGRESS; 1756 goto end; 1757 } 1758 /* locate the first pipe with work to do */ 1759 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1760 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1761 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1762 (uintptr_t)otgpipe, (uintptr_t)xfer, 1763 (xfer != NULL) ? xfer->ux_status : 0, 0); 1764 if (xfer != NULL) { 1765 /* move this pipe to the end of the list */ 1766 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1767 motg_pipe, ep_pipe_list); 1768 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1769 otgpipe, ep_pipe_list); 1770 break; 1771 } 1772 } 1773 if (xfer == NULL) { 1774 err = USBD_NOT_STARTED; 1775 goto end; 1776 } 1777 xfer->ux_status = USBD_IN_PROGRESS; 1778 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1779 KASSERT(otgpipe->hw_ep == ep); 1780 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1781 // KASSERT(xfer->ux_actlen == 0); 1782 xfer->ux_actlen = 0; 1783 1784 ep->xfer = xfer; 1785 ep->datalen = xfer->ux_length; 1786 KASSERT(ep->datalen > 0); 1787 ep->data = xfer->ux_buf; 1788 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1789 (ep->datalen % 64) == 0) 1790 ep->need_short_xfer = 1; 1791 else 1792 ep->need_short_xfer = 0; 1793 /* now we need send this request */ 1794 DPRINTFN(MD_BULK, 1795 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1796 "xfer %#jx in data %#jx len %jd short %jd" : 1797 "xfer %#jx out data %#jx len %jd short %jd", 1798 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1799 ep->need_short_xfer); 1800 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1801 xfer->ux_pipe->up_dev->ud_speed, 1802 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1803 KASSERT(ep->phase == IDLE); 1804 /* select endpoint */ 1805 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1806 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1807 == UE_DIR_IN) { 1808 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1809 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1810 motg_device_data_read(xfer); 1811 } else { 1812 ep->phase = DATA_OUT; 1813 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1814 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1815 motg_device_data_write(xfer); 1816 } 1817 end: 1818 if (err) 1819 return err; 1820 1821 return USBD_IN_PROGRESS; 1822 } 1823 1824 static void 1825 motg_device_data_read(struct usbd_xfer *xfer) 1826 { 1827 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1828 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1829 uint32_t val; 1830 1831 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1832 1833 KASSERT(mutex_owned(&sc->sc_lock)); 1834 /* assume endpoint already selected */ 1835 motg_setup_endpoint_rx(xfer); 1836 /* Max packet size */ 1837 UWRITE2(sc, MUSB2_REG_RXMAXP, 1838 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1839 /* Data Toggle */ 1840 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1841 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1842 if (otgpipe->nexttoggle) 1843 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1844 else 1845 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1846 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1847 1848 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh 0x%jx", 1849 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1850 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1851 /* start transaction */ 1852 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1853 otgpipe->hw_ep->phase = DATA_IN; 1854 } 1855 1856 static void 1857 motg_device_data_write(struct usbd_xfer *xfer) 1858 { 1859 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1860 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1861 struct motg_hw_ep *ep = otgpipe->hw_ep; 1862 int datalen; 1863 char *data; 1864 uint32_t val; 1865 1866 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1867 1868 KASSERT(xfer!=NULL); 1869 KASSERT(mutex_owned(&sc->sc_lock)); 1870 1871 datalen = min(ep->datalen, 1872 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1873 ep->phase = DATA_OUT; 1874 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh 0x%jx", 1875 (uintptr_t)xfer, ep->ep_number, datalen, 1876 UREAD1(sc, MUSB2_REG_TXCSRH)); 1877 1878 /* assume endpoint already selected */ 1879 /* write data to fifo */ 1880 data = ep->data; 1881 ep->data += datalen; 1882 ep->datalen -= datalen; 1883 xfer->ux_actlen += datalen; 1884 if (((vaddr_t)data & 0x3) == 0 && 1885 (datalen >> 2) > 0) { 1886 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1887 MUSB2_REG_EPFIFO(ep->ep_number), 1888 (void *)data, datalen >> 2); 1889 data += (datalen & ~0x3); 1890 datalen -= (datalen & ~0x3); 1891 } 1892 if (datalen) { 1893 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1894 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1895 } 1896 1897 motg_setup_endpoint_tx(xfer); 1898 /* Max packet size */ 1899 UWRITE2(sc, MUSB2_REG_TXMAXP, 1900 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1901 /* Data Toggle */ 1902 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1903 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1904 if (otgpipe->nexttoggle) 1905 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1906 else 1907 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1908 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1909 1910 /* start transaction */ 1911 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1912 } 1913 1914 static void 1915 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1916 { 1917 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1918 struct usbd_xfer *xfer = ep->xfer; 1919 uint8_t csr; 1920 int datalen, max_datalen; 1921 char *data; 1922 bool got_short; 1923 usbd_status new_status = USBD_IN_PROGRESS; 1924 1925 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1926 1927 KASSERT(mutex_owned(&sc->sc_lock)); 1928 KASSERT(ep->ep_number == epnumber); 1929 1930 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1931 /* select endpoint */ 1932 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1933 1934 /* read out FIFO status */ 1935 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1936 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr ,0 ,0); 1937 1938 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1939 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1940 return; 1941 1942 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1943 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1944 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1945 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1946 1947 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1948 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1949 new_status = USBD_TIMEOUT; /* XXX */ 1950 goto complete; 1951 } 1952 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1953 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1954 new_status = USBD_STALLED; 1955 else 1956 new_status = USBD_IOERROR; 1957 /* clear status */ 1958 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1959 goto complete; 1960 } 1961 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1962 1963 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1964 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1965 goto complete; 1966 } 1967 1968 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1969 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1970 1971 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1972 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 1973 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1974 max_datalen = min( 1975 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1976 ep->datalen); 1977 if (datalen > max_datalen) { 1978 new_status = USBD_IOERROR; 1979 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1980 goto complete; 1981 } 1982 got_short = (datalen < max_datalen); 1983 if (datalen > 0) { 1984 KASSERT(ep->phase == DATA_IN); 1985 data = ep->data; 1986 ep->data += datalen; 1987 ep->datalen -= datalen; 1988 xfer->ux_actlen += datalen; 1989 if (((vaddr_t)data & 0x3) == 0 && 1990 (datalen >> 2) > 0) { 1991 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 1992 (uintptr_t)data, datalen, 0, 0); 1993 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1994 MUSB2_REG_EPFIFO(ep->ep_number), 1995 (void *)data, datalen >> 2); 1996 data += (datalen & ~0x3); 1997 datalen -= (datalen & ~0x3); 1998 } 1999 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 2000 datalen ,0 ,0); 2001 if (datalen) { 2002 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2003 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2004 } 2005 } 2006 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2007 KASSERT(ep->phase == DATA_IN); 2008 if (got_short || (ep->datalen == 0)) { 2009 if (ep->need_short_xfer == 0) { 2010 new_status = USBD_NORMAL_COMPLETION; 2011 goto complete; 2012 } 2013 ep->need_short_xfer = 0; 2014 } 2015 motg_device_data_read(xfer); 2016 return; 2017 complete: 2018 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2019 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2020 ep->phase = IDLE; 2021 ep->xfer = NULL; 2022 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2023 KASSERT(new_status != USBD_IN_PROGRESS); 2024 xfer->ux_status = new_status; 2025 usb_transfer_complete(xfer); 2026 } 2027 motg_device_data_start1(sc, ep); 2028 } 2029 2030 static void 2031 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2032 { 2033 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2034 struct usbd_xfer *xfer = ep->xfer; 2035 uint8_t csr; 2036 struct motg_pipe *otgpipe; 2037 usbd_status new_status = USBD_IN_PROGRESS; 2038 2039 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2040 2041 KASSERT(mutex_owned(&sc->sc_lock)); 2042 KASSERT(ep->ep_number == epnumber); 2043 2044 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2045 /* select endpoint */ 2046 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2047 2048 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2049 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr, 0, 0); 2050 2051 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2052 /* command not accepted */ 2053 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2054 new_status = USBD_STALLED; 2055 else 2056 new_status = USBD_IOERROR; 2057 /* clear status */ 2058 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2059 goto complete; 2060 } 2061 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2062 new_status = USBD_TIMEOUT; /* XXX */ 2063 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2064 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2065 /* flush fifo */ 2066 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2067 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2068 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2069 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2070 delay(1000); 2071 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2072 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR 0x%jx", 2073 epnumber, csr, 0, 0); 2074 } 2075 goto complete; 2076 } 2077 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2078 /* data still not sent */ 2079 return; 2080 } 2081 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2082 goto complete; 2083 KASSERT(ep->phase == DATA_OUT); 2084 2085 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2086 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2087 2088 if (ep->datalen == 0) { 2089 if (ep->need_short_xfer) { 2090 ep->need_short_xfer = 0; 2091 /* one more data phase */ 2092 } else { 2093 new_status = USBD_NORMAL_COMPLETION; 2094 goto complete; 2095 } 2096 } 2097 motg_device_data_write(xfer); 2098 return; 2099 2100 complete: 2101 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2102 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2103 #ifdef DIAGNOSTIC 2104 if (xfer && xfer->ux_status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2105 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2106 #endif 2107 ep->phase = IDLE; 2108 ep->xfer = NULL; 2109 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2110 KASSERT(new_status != USBD_IN_PROGRESS); 2111 xfer->ux_status = new_status; 2112 usb_transfer_complete(xfer); 2113 } 2114 motg_device_data_start1(sc, ep); 2115 } 2116 2117 /* Abort a device control request. */ 2118 void 2119 motg_device_data_abort(struct usbd_xfer *xfer) 2120 { 2121 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2122 KASSERT(mutex_owned(&sc->sc_lock)); 2123 2124 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2125 2126 motg_device_xfer_abort(xfer); 2127 } 2128 2129 /* Close a device control pipe */ 2130 void 2131 motg_device_data_close(struct usbd_pipe *pipe) 2132 { 2133 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2134 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2135 struct motg_pipe *otgpipeiter; 2136 2137 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2138 2139 KASSERT(mutex_owned(&sc->sc_lock)); 2140 KASSERT(otgpipe->hw_ep->xfer == NULL || 2141 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2142 2143 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2144 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2145 if (otgpipeiter == otgpipe) { 2146 /* remove from list */ 2147 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2148 motg_pipe, ep_pipe_list); 2149 otgpipe->hw_ep->refcount--; 2150 /* we're done */ 2151 return; 2152 } 2153 } 2154 panic("motg_device_data_close: not found"); 2155 } 2156 2157 void 2158 motg_device_data_done(struct usbd_xfer *xfer) 2159 { 2160 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2161 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2162 2163 KASSERT(otgpipe->hw_ep->xfer != xfer); 2164 } 2165 2166 void 2167 motg_device_clear_toggle(struct usbd_pipe *pipe) 2168 { 2169 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2170 otgpipe->nexttoggle = 0; 2171 } 2172 2173 /* Abort a device control request. */ 2174 static void 2175 motg_device_xfer_abort(struct usbd_xfer *xfer) 2176 { 2177 int wake; 2178 uint8_t csr; 2179 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2180 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2181 KASSERT(mutex_owned(&sc->sc_lock)); 2182 2183 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2184 2185 if (xfer->ux_hcflags & UXFER_ABORTING) { 2186 DPRINTF("already aborting", 0, 0, 0, 0); 2187 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2188 while (xfer->ux_hcflags & UXFER_ABORTING) 2189 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2190 return; 2191 } 2192 xfer->ux_hcflags |= UXFER_ABORTING; 2193 if (otgpipe->hw_ep->xfer == xfer) { 2194 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2195 otgpipe->hw_ep->xfer = NULL; 2196 if (otgpipe->hw_ep->ep_number > 0) { 2197 /* select endpoint */ 2198 UWRITE1(sc, MUSB2_REG_EPINDEX, 2199 otgpipe->hw_ep->ep_number); 2200 if (otgpipe->hw_ep->phase == DATA_OUT) { 2201 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2202 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2203 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2204 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2205 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2206 } 2207 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2208 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2209 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2210 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2211 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2212 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2213 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2214 } 2215 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2216 } 2217 otgpipe->hw_ep->phase = IDLE; 2218 } 2219 } 2220 xfer->ux_status = USBD_CANCELLED; /* make software ignore it */ 2221 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2222 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2223 usb_transfer_complete(xfer); 2224 if (wake) 2225 cv_broadcast(&xfer->ux_hccv); 2226 } 2227
Indexes created Wed Sep 24 05:09:52 GMT 2025