motg.c revision 1.2
1 /* $NetBSD: motg.c,v 1.2 2014/07/17 19:58:18 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.2 2014/07/17 19:58:18 bouyer Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/device.h> 50 #include <sys/select.h> 51 #include <sys/extent.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/motgreg.h> 66 #include <dev/usb/motgvar.h> 67 #include <dev/usb/usbroothub_subr.h> 68 69 #define MOTG_DEBUG 70 #ifdef MOTG_DEBUG 71 #define DPRINTF(x) if (motgdebug) printf x 72 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 73 #define MD_ROOT 0x0002 74 #define MD_CTRL 0x0004 75 #define MD_BULK 0x0008 76 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 77 int motgdebug = 0; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 /* various timeouts, for various speeds */ 84 /* control NAK timeouts */ 85 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 86 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 87 88 /* intr/iso polling intervals */ 89 #define POLL_TO 100 /* 100 frames, about 0.1s */ 90 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 91 92 /* bulk NAK timeouts */ 93 #define NAK_TO_BULK 255 /* 255 frames, about 0.25s */ 94 #define NAK_TO_BULK_HIGH 13 /* 8k microframes, about 1s */ 95 96 static void motg_hub_change(struct motg_softc *); 97 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 98 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 99 static void motg_root_ctrl_abort(usbd_xfer_handle); 100 static void motg_root_ctrl_close(usbd_pipe_handle); 101 static void motg_root_ctrl_done(usbd_xfer_handle); 102 103 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 104 static usbd_status motg_root_intr_start(usbd_xfer_handle); 105 static void motg_root_intr_abort(usbd_xfer_handle); 106 static void motg_root_intr_close(usbd_pipe_handle); 107 static void motg_root_intr_done(usbd_xfer_handle); 108 109 static usbd_status motg_open(usbd_pipe_handle); 110 static void motg_poll(struct usbd_bus *); 111 static void motg_softintr(void *); 112 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 113 static void motg_freem(struct usbd_bus *, usb_dma_t *); 114 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 115 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 116 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 117 static void motg_noop(usbd_pipe_handle pipe); 118 static usbd_status motg_portreset(struct motg_softc*); 119 120 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 121 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 122 static void motg_device_ctrl_abort(usbd_xfer_handle); 123 static void motg_device_ctrl_close(usbd_pipe_handle); 124 static void motg_device_ctrl_done(usbd_xfer_handle); 125 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 126 static void motg_device_ctrl_read(usbd_xfer_handle); 127 static void motg_device_ctrl_intr_rx(struct motg_softc *); 128 static void motg_device_ctrl_intr_tx(struct motg_softc *); 129 130 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 131 static usbd_status motg_device_data_start(usbd_xfer_handle); 132 static usbd_status motg_device_data_start1(struct motg_softc *, 133 struct motg_hw_ep *); 134 static void motg_device_data_abort(usbd_xfer_handle); 135 static void motg_device_data_close(usbd_pipe_handle); 136 static void motg_device_data_done(usbd_xfer_handle); 137 static void motg_device_intr_rx(struct motg_softc *, int); 138 static void motg_device_intr_tx(struct motg_softc *, int); 139 static void motg_device_data_read(usbd_xfer_handle); 140 static void motg_device_data_write(usbd_xfer_handle); 141 142 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 143 static void motg_device_clear_toggle(usbd_pipe_handle pipe); 144 145 #define MOTG_INTR_ENDPT 1 146 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 147 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 148 #define UWRITE1(sc, r, x) \ 149 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 150 } while (/*CONSTCOND*/0) 151 #define UWRITE2(sc, r, x) \ 152 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 153 } while (/*CONSTCOND*/0) 154 #define UWRITE4(sc, r, x) \ 155 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 156 } while (/*CONSTCOND*/0) 157 158 static __inline uint32_t 159 UREAD1(struct motg_softc *sc, bus_size_t r) 160 { 161 162 UBARR(sc); 163 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 164 } 165 static __inline uint32_t 166 UREAD2(struct motg_softc *sc, bus_size_t r) 167 { 168 169 UBARR(sc); 170 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 171 } 172 static __inline uint32_t 173 UREAD4(struct motg_softc *sc, bus_size_t r) 174 { 175 176 UBARR(sc); 177 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 178 } 179 180 static void 181 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 182 { 183 uint8_t val; 184 185 val = UREAD1(sc, MUSB2_REG_POWER); 186 if (on) 187 val |= MUSB2_MASK_SOFTC; 188 else 189 val &= ~MUSB2_MASK_SOFTC; 190 191 UWRITE1(sc, MUSB2_REG_POWER, val); 192 } 193 194 const struct usbd_bus_methods motg_bus_methods = { 195 .open_pipe = motg_open, 196 .soft_intr = motg_softintr, 197 .do_poll = motg_poll, 198 .allocm = motg_allocm, 199 .freem = motg_freem, 200 .allocx = motg_allocx, 201 .freex = motg_freex, 202 .get_lock = motg_get_lock, 203 .new_device = NULL, 204 }; 205 206 const struct usbd_pipe_methods motg_root_ctrl_methods = { 207 .transfer = motg_root_ctrl_transfer, 208 .start = motg_root_ctrl_start, 209 .abort = motg_root_ctrl_abort, 210 .close = motg_root_ctrl_close, 211 .cleartoggle = motg_noop, 212 .done = motg_root_ctrl_done, 213 }; 214 215 const struct usbd_pipe_methods motg_root_intr_methods = { 216 .transfer = motg_root_intr_transfer, 217 .start = motg_root_intr_start, 218 .abort = motg_root_intr_abort, 219 .close = motg_root_intr_close, 220 .cleartoggle = motg_noop, 221 .done = motg_root_intr_done, 222 }; 223 224 const struct usbd_pipe_methods motg_device_ctrl_methods = { 225 .transfer = motg_device_ctrl_transfer, 226 .start = motg_device_ctrl_start, 227 .abort = motg_device_ctrl_abort, 228 .close = motg_device_ctrl_close, 229 .cleartoggle = motg_noop, 230 .done = motg_device_ctrl_done, 231 }; 232 233 const struct usbd_pipe_methods motg_device_data_methods = { 234 .transfer = motg_device_data_transfer, 235 .start = motg_device_data_start, 236 .abort = motg_device_data_abort, 237 .close = motg_device_data_close, 238 .cleartoggle = motg_device_clear_toggle, 239 .done = motg_device_data_done, 240 }; 241 242 usbd_status 243 motg_init(struct motg_softc *sc) 244 { 245 uint32_t nrx, ntx, val; 246 int dynfifo; 247 int offset, i; 248 249 if (sc->sc_mode == MOTG_MODE_DEVICE) 250 return USBD_NORMAL_COMPLETION; /* not supported */ 251 252 /* disable all interrupts */ 253 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 254 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 255 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 256 /* disable pullup */ 257 258 musbotg_pull_common(sc, 0); 259 260 /* disable double packet buffering XXX what's this ? */ 261 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 262 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 263 264 /* enable HighSpeed and ISO Update flags */ 265 266 UWRITE1(sc, MUSB2_REG_POWER, 267 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 268 269 if (sc->sc_mode == MOTG_MODE_DEVICE) { 270 /* clear Session bit, if set */ 271 val = UREAD1(sc, MUSB2_REG_DEVCTL); 272 val &= ~MUSB2_MASK_SESS; 273 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 274 } else { 275 /* Enter session for Host mode */ 276 val = UREAD1(sc, MUSB2_REG_DEVCTL); 277 val |= MUSB2_MASK_SESS; 278 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 279 } 280 delay(1000); 281 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 282 283 /* disable testmode */ 284 285 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 286 287 /* set default value */ 288 289 UWRITE1(sc, MUSB2_REG_MISC, 0); 290 291 /* select endpoint index 0 */ 292 293 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 294 295 /* read out number of endpoints */ 296 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 297 298 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 299 300 /* these numbers exclude the control endpoint */ 301 302 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 303 304 sc->sc_ep_max = MAX(nrx, ntx); 305 if (sc->sc_ep_max == 0) { 306 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 307 return USBD_INVAL; 308 } 309 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 310 /* read out configuration data */ 311 val = UREAD1(sc, MUSB2_REG_CONFDATA); 312 313 DPRINTF(("Config Data: 0x%02x\n", val)); 314 315 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 316 317 if (dynfifo) { 318 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 319 "assuming 16Kbytes of FIFO RAM\n"); 320 } 321 322 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 323 324 /* initialise endpoint profiles */ 325 sc->sc_in_ep[0].ep_fifo_size = 64; 326 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 327 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 328 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 329 offset = 64; 330 331 for (i = 1; i <= sc->sc_ep_max; i++) { 332 int fiforx_size, fifotx_size, fifo_size; 333 334 /* select endpoint */ 335 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 336 337 val = UREAD1(sc, MUSB2_REG_FSIZE); 338 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 339 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 340 341 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 342 i, fifotx_size, fiforx_size, dynfifo)); 343 344 if (dynfifo) { 345 if (i < 3) { 346 fifo_size = 12; /* 4K */ 347 } else if (i < 10) { 348 fifo_size = 10; /* 1K */ 349 } else { 350 fifo_size = 7; /* 128 bytes */ 351 } 352 if (fiforx_size && (i <= nrx)) { 353 fiforx_size = fifo_size; 354 if (fifo_size > 7) { 355 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 356 MUSB2_VAL_FIFOSZ(fifo_size) | 357 MUSB2_MASK_FIFODB); 358 } else { 359 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 360 MUSB2_VAL_FIFOSZ(fifo_size) | 361 MUSB2_MASK_FIFODB); 362 } 363 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 364 offset >> 3); 365 offset += (1 << fiforx_size); 366 } 367 if (fifotx_size && (i <= ntx)) { 368 fifotx_size = fifo_size; 369 if (fifo_size > 7) { 370 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 371 MUSB2_VAL_FIFOSZ(fifo_size) | 372 MUSB2_MASK_FIFODB); 373 } else { 374 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 375 MUSB2_VAL_FIFOSZ(fifo_size)); 376 } 377 378 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 379 offset >> 3); 380 381 offset += (1 << fifotx_size); 382 } 383 } 384 if (fiforx_size && (i <= nrx)) { 385 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 386 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 387 } 388 if (fifotx_size && (i <= ntx)) { 389 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 390 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 391 } 392 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 393 } 394 395 396 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 397 398 /* turn on default interrupts */ 399 400 if (sc->sc_mode == MOTG_MODE_HOST) { 401 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 402 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 403 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 404 } else 405 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 406 407 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 408 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 409 410 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 411 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 412 413 /* Set up the bus struct. */ 414 sc->sc_bus.methods = &motg_bus_methods; 415 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 416 sc->sc_bus.usbrev = USBREV_2_0; 417 sc->sc_bus.hci_private = sc; 418 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 419 "Mentor Graphics"); 420 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 421 return USBD_NORMAL_COMPLETION; 422 } 423 424 static int 425 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 426 { 427 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 428 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 429 struct motg_hw_ep *ep; 430 int i, size; 431 432 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 433 sc->sc_in_ep : sc->sc_out_ep; 434 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 435 436 for (i = sc->sc_ep_max; i >= 1; i--) { 437 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 438 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 439 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 440 if (ep[i].ep_fifo_size >= size) { 441 /* found a suitable endpoint */ 442 otgpipe->hw_ep = &ep[i]; 443 mutex_enter(&sc->sc_lock); 444 if (otgpipe->hw_ep->refcount > 0) { 445 /* no luck, try next */ 446 mutex_exit(&sc->sc_lock); 447 otgpipe->hw_ep = NULL; 448 } else { 449 otgpipe->hw_ep->refcount++; 450 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 451 otgpipe, ep_pipe_list); 452 mutex_exit(&sc->sc_lock); 453 return 0; 454 } 455 } 456 } 457 return -1; 458 } 459 460 /* Open a new pipe. */ 461 usbd_status 462 motg_open(usbd_pipe_handle pipe) 463 { 464 struct motg_softc *sc = pipe->device->bus->hci_private; 465 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 466 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 467 468 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 469 pipe, pipe->device->address, 470 ed->bEndpointAddress, sc->sc_root_addr)); 471 472 if (sc->sc_dying) 473 return USBD_IOERROR; 474 475 /* toggle state needed for bulk endpoints */ 476 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 477 478 if (pipe->device->address == sc->sc_root_addr) { 479 switch (ed->bEndpointAddress) { 480 case USB_CONTROL_ENDPOINT: 481 pipe->methods = &motg_root_ctrl_methods; 482 break; 483 case UE_DIR_IN | MOTG_INTR_ENDPT: 484 pipe->methods = &motg_root_intr_methods; 485 break; 486 default: 487 return (USBD_INVAL); 488 } 489 } else { 490 switch (ed->bmAttributes & UE_XFERTYPE) { 491 case UE_CONTROL: 492 pipe->methods = &motg_device_ctrl_methods; 493 /* always use sc_in_ep[0] for in and out */ 494 otgpipe->hw_ep = &sc->sc_in_ep[0]; 495 mutex_enter(&sc->sc_lock); 496 otgpipe->hw_ep->refcount++; 497 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 498 otgpipe, ep_pipe_list); 499 mutex_exit(&sc->sc_lock); 500 break; 501 case UE_BULK: 502 case UE_INTERRUPT: 503 DPRINTFN(MD_BULK, 504 ("new %s %s pipe wMaxPacketSize %d\n", 505 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 506 "bulk" : "interrupt", 507 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 508 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 509 if (motg_select_ep(sc, pipe) != 0) 510 goto bad; 511 KASSERT(otgpipe->hw_ep != NULL); 512 pipe->methods = &motg_device_data_methods; 513 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 514 break; 515 default: 516 goto bad; 517 #ifdef notyet 518 case UE_ISOCHRONOUS: 519 ... 520 break; 521 #endif /* notyet */ 522 } 523 } 524 return (USBD_NORMAL_COMPLETION); 525 526 bad: 527 return (USBD_NOMEM); 528 } 529 530 void 531 motg_softintr(void *v) 532 { 533 struct usbd_bus *bus = v; 534 struct motg_softc *sc = bus->hci_private; 535 uint16_t rx_status, tx_status; 536 uint8_t ctrl_status; 537 uint32_t val; 538 int i; 539 540 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 541 542 DPRINTFN(MD_ROOT | MD_CTRL, 543 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 544 545 mutex_spin_enter(&sc->sc_intr_lock); 546 rx_status = sc->sc_intr_rx_ep; 547 sc->sc_intr_rx_ep = 0; 548 tx_status = sc->sc_intr_tx_ep; 549 sc->sc_intr_tx_ep = 0; 550 ctrl_status = sc->sc_intr_ctrl; 551 sc->sc_intr_ctrl = 0; 552 mutex_spin_exit(&sc->sc_intr_lock); 553 554 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 555 556 if (ctrl_status & (MUSB2_MASK_IRESET | 557 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 558 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 559 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 560 ctrl_status)); 561 562 if (ctrl_status & MUSB2_MASK_IRESET) { 563 sc->sc_isreset = 1; 564 sc->sc_port_suspended = 0; 565 sc->sc_port_suspended_change = 1; 566 sc->sc_connected_changed = 1; 567 sc->sc_port_enabled = 1; 568 569 val = UREAD1(sc, MUSB2_REG_POWER); 570 if (val & MUSB2_MASK_HSMODE) 571 sc->sc_high_speed = 1; 572 else 573 sc->sc_high_speed = 0; 574 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 575 sc->sc_high_speed)); 576 577 /* turn off interrupts */ 578 val = MUSB2_MASK_IRESET; 579 val &= ~MUSB2_MASK_IRESUME; 580 val |= MUSB2_MASK_ISUSP; 581 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 582 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 583 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 584 } 585 if (ctrl_status & MUSB2_MASK_IRESUME) { 586 if (sc->sc_port_suspended) { 587 sc->sc_port_suspended = 0; 588 sc->sc_port_suspended_change = 1; 589 val = UREAD1(sc, MUSB2_REG_INTUSBE); 590 /* disable resume interrupt */ 591 val &= ~MUSB2_MASK_IRESUME; 592 /* enable suspend interrupt */ 593 val |= MUSB2_MASK_ISUSP; 594 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 595 } 596 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 597 if (!sc->sc_port_suspended) { 598 sc->sc_port_suspended = 1; 599 sc->sc_port_suspended_change = 1; 600 601 val = UREAD1(sc, MUSB2_REG_INTUSBE); 602 /* disable suspend interrupt */ 603 val &= ~MUSB2_MASK_ISUSP; 604 /* enable resume interrupt */ 605 val |= MUSB2_MASK_IRESUME; 606 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 607 } 608 } 609 if (ctrl_status & MUSB2_MASK_ICONN) { 610 sc->sc_connected = 1; 611 sc->sc_connected_changed = 1; 612 sc->sc_isreset = 1; 613 sc->sc_port_enabled = 1; 614 } else if (ctrl_status & MUSB2_MASK_IDISC) { 615 sc->sc_connected = 0; 616 sc->sc_connected_changed = 1; 617 sc->sc_isreset = 0; 618 sc->sc_port_enabled = 0; 619 } 620 621 /* complete root HUB interrupt endpoint */ 622 623 motg_hub_change(sc); 624 } 625 /* 626 * read in interrupt status and mix with the status we 627 * got from the wrapper 628 */ 629 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 630 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 631 632 if (rx_status & 0x01) 633 panic("ctrl_rx"); 634 if (tx_status & 0x01) 635 motg_device_ctrl_intr_tx(sc); 636 for (i = 1; i <= sc->sc_ep_max; i++) { 637 if (rx_status & (0x01 << i)) 638 motg_device_intr_rx(sc, i); 639 if (tx_status & (0x01 << i)) 640 motg_device_intr_tx(sc, i); 641 } 642 643 return; 644 } 645 646 void 647 motg_poll(struct usbd_bus *bus) 648 { 649 struct motg_softc *sc = bus->hci_private; 650 651 sc->sc_intr_poll(sc->sc_intr_poll_arg); 652 mutex_enter(&sc->sc_lock); 653 motg_softintr(bus); 654 mutex_exit(&sc->sc_lock); 655 } 656 657 int 658 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 659 uint8_t ctrl) 660 { 661 KASSERT(mutex_owned(&sc->sc_intr_lock)); 662 sc->sc_intr_tx_ep = tx_ep; 663 sc->sc_intr_rx_ep = rx_ep; 664 sc->sc_intr_ctrl = ctrl; 665 666 if (!sc->sc_bus.use_polling) { 667 sc->sc_bus.no_intrs++; 668 usb_schedsoftintr(&sc->sc_bus); 669 } 670 return 1; 671 } 672 673 int 674 motg_intr_vbus(struct motg_softc *sc, int vbus) 675 { 676 uint8_t val; 677 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 678 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 679 /* try to re-enter session for Host mode */ 680 val = UREAD1(sc, MUSB2_REG_DEVCTL); 681 val |= MUSB2_MASK_SESS; 682 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 683 } 684 return 1; 685 } 686 687 usbd_status 688 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 689 { 690 struct motg_softc *sc = bus->hci_private; 691 usbd_status status; 692 693 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 694 if (status == USBD_NOMEM) 695 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 696 return status; 697 } 698 699 void 700 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 701 { 702 if (dma->block->flags & USB_DMA_RESERVE) { 703 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 704 dma); 705 return; 706 } 707 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 708 } 709 710 usbd_xfer_handle 711 motg_allocx(struct usbd_bus *bus) 712 { 713 struct motg_softc *sc = bus->hci_private; 714 usbd_xfer_handle xfer; 715 716 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 717 if (xfer != NULL) { 718 memset(xfer, 0, sizeof(struct motg_xfer)); 719 UXFER(xfer)->sc = sc; 720 #ifdef DIAGNOSTIC 721 // XXX UXFER(xfer)->iinfo.isdone = 1; 722 xfer->busy_free = XFER_BUSY; 723 #endif 724 } 725 return (xfer); 726 } 727 728 void 729 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 730 { 731 struct motg_softc *sc = bus->hci_private; 732 733 #ifdef DIAGNOSTIC 734 if (xfer->busy_free != XFER_BUSY) { 735 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 736 xfer->busy_free); 737 } 738 xfer->busy_free = XFER_FREE; 739 #endif 740 pool_cache_put(sc->sc_xferpool, xfer); 741 } 742 743 static void 744 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 745 { 746 struct motg_softc *sc = bus->hci_private; 747 748 *lock = &sc->sc_lock; 749 } 750 751 /* 752 * Data structures and routines to emulate the root hub. 753 */ 754 usb_device_descriptor_t motg_devd = { 755 USB_DEVICE_DESCRIPTOR_SIZE, 756 UDESC_DEVICE, /* type */ 757 {0x00, 0x01}, /* USB version */ 758 UDCLASS_HUB, /* class */ 759 UDSUBCLASS_HUB, /* subclass */ 760 UDPROTO_FSHUB, /* protocol */ 761 64, /* max packet */ 762 {0},{0},{0x00,0x01}, /* device id */ 763 1,2,0, /* string indicies */ 764 1 /* # of configurations */ 765 }; 766 767 const usb_config_descriptor_t motg_confd = { 768 USB_CONFIG_DESCRIPTOR_SIZE, 769 UDESC_CONFIG, 770 {USB_CONFIG_DESCRIPTOR_SIZE + 771 USB_INTERFACE_DESCRIPTOR_SIZE + 772 USB_ENDPOINT_DESCRIPTOR_SIZE}, 773 1, 774 1, 775 0, 776 UC_ATTR_MBO | UC_SELF_POWERED, 777 0 /* max power */ 778 }; 779 780 const usb_interface_descriptor_t motg_ifcd = { 781 USB_INTERFACE_DESCRIPTOR_SIZE, 782 UDESC_INTERFACE, 783 0, 784 0, 785 1, 786 UICLASS_HUB, 787 UISUBCLASS_HUB, 788 UIPROTO_FSHUB, 789 0 790 }; 791 792 const usb_endpoint_descriptor_t motg_endpd = { 793 USB_ENDPOINT_DESCRIPTOR_SIZE, 794 UDESC_ENDPOINT, 795 UE_DIR_IN | MOTG_INTR_ENDPT, 796 UE_INTERRUPT, 797 {8}, 798 255 799 }; 800 801 const usb_hub_descriptor_t motg_hubd = { 802 USB_HUB_DESCRIPTOR_SIZE, 803 UDESC_HUB, 804 1, 805 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 806 50, /* power on to power good */ 807 0, 808 { 0x00 }, /* port is removable */ 809 { 0 }, 810 }; 811 812 /* 813 * Simulate a hardware hub by handling all the necessary requests. 814 */ 815 usbd_status 816 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 817 { 818 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 819 usbd_status err; 820 821 /* Insert last in queue. */ 822 mutex_enter(&sc->sc_lock); 823 err = usb_insert_transfer(xfer); 824 mutex_exit(&sc->sc_lock); 825 if (err) 826 return (err); 827 828 /* 829 * Pipe isn't running (otherwise err would be USBD_INPROG), 830 * so start it first. 831 */ 832 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 833 } 834 835 usbd_status 836 motg_root_ctrl_start(usbd_xfer_handle xfer) 837 { 838 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 839 usb_device_request_t *req; 840 void *buf = NULL; 841 int len, value, index, status, change, l, totlen = 0; 842 usb_port_status_t ps; 843 usbd_status err; 844 uint32_t val; 845 846 if (sc->sc_dying) 847 return (USBD_IOERROR); 848 849 #ifdef DIAGNOSTIC 850 if (!(xfer->rqflags & URQ_REQUEST)) 851 panic("motg_root_ctrl_start: not a request"); 852 #endif 853 req = &xfer->request; 854 855 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 856 req->bmRequestType, req->bRequest)); 857 858 len = UGETW(req->wLength); 859 value = UGETW(req->wValue); 860 index = UGETW(req->wIndex); 861 862 if (len != 0) 863 buf = KERNADDR(&xfer->dmabuf, 0); 864 865 #define C(x,y) ((x) | ((y) << 8)) 866 switch(C(req->bRequest, req->bmRequestType)) { 867 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 868 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 869 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 870 /* 871 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 872 * for the integrated root hub. 873 */ 874 break; 875 case C(UR_GET_CONFIG, UT_READ_DEVICE): 876 if (len > 0) { 877 *(u_int8_t *)buf = sc->sc_root_conf; 878 totlen = 1; 879 } 880 break; 881 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 882 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 883 if (len == 0) 884 break; 885 switch(value >> 8) { 886 case UDESC_DEVICE: 887 if ((value & 0xff) != 0) { 888 err = USBD_IOERROR; 889 goto ret; 890 } 891 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 892 USETW(motg_devd.idVendor, sc->sc_id_vendor); 893 memcpy(buf, &motg_devd, l); 894 break; 895 case UDESC_CONFIG: 896 if ((value & 0xff) != 0) { 897 err = USBD_IOERROR; 898 goto ret; 899 } 900 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 901 memcpy(buf, &motg_confd, l); 902 buf = (char *)buf + l; 903 len -= l; 904 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 905 totlen += l; 906 memcpy(buf, &motg_ifcd, l); 907 buf = (char *)buf + l; 908 len -= l; 909 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 910 totlen += l; 911 memcpy(buf, &motg_endpd, l); 912 break; 913 case UDESC_STRING: 914 #define sd ((usb_string_descriptor_t *)buf) 915 switch (value & 0xff) { 916 case 0: /* Language table */ 917 totlen = usb_makelangtbl(sd, len); 918 break; 919 case 1: /* Vendor */ 920 totlen = usb_makestrdesc(sd, len, 921 sc->sc_vendor); 922 break; 923 case 2: /* Product */ 924 totlen = usb_makestrdesc(sd, len, 925 "MOTG root hub"); 926 break; 927 } 928 #undef sd 929 break; 930 default: 931 err = USBD_IOERROR; 932 goto ret; 933 } 934 break; 935 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 936 if (len > 0) { 937 *(u_int8_t *)buf = 0; 938 totlen = 1; 939 } 940 break; 941 case C(UR_GET_STATUS, UT_READ_DEVICE): 942 if (len > 1) { 943 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 944 totlen = 2; 945 } 946 break; 947 case C(UR_GET_STATUS, UT_READ_INTERFACE): 948 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 949 if (len > 1) { 950 USETW(((usb_status_t *)buf)->wStatus, 0); 951 totlen = 2; 952 } 953 break; 954 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 955 if (value >= USB_MAX_DEVICES) { 956 err = USBD_IOERROR; 957 goto ret; 958 } 959 sc->sc_root_addr = value; 960 break; 961 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 962 if (value != 0 && value != 1) { 963 err = USBD_IOERROR; 964 goto ret; 965 } 966 sc->sc_root_conf = value; 967 break; 968 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 969 break; 970 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 971 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 972 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 973 err = USBD_IOERROR; 974 goto ret; 975 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 976 break; 977 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 978 break; 979 /* Hub requests */ 980 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 981 break; 982 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 983 DPRINTFN(MD_ROOT, 984 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 985 "port=%d feature=%d\n", 986 index, value)); 987 if (index != 1) { 988 err = USBD_IOERROR; 989 goto ret; 990 } 991 switch(value) { 992 case UHF_PORT_ENABLE: 993 sc->sc_port_enabled = 0; 994 break; 995 case UHF_PORT_SUSPEND: 996 if (sc->sc_port_suspended != 0) { 997 val = UREAD1(sc, MUSB2_REG_POWER); 998 val &= ~MUSB2_MASK_SUSPMODE; 999 val |= MUSB2_MASK_RESUME; 1000 UWRITE1(sc, MUSB2_REG_POWER, val); 1001 /* wait 20 milliseconds */ 1002 usb_delay_ms(&sc->sc_bus, 20); 1003 val = UREAD1(sc, MUSB2_REG_POWER); 1004 val &= ~MUSB2_MASK_RESUME; 1005 UWRITE1(sc, MUSB2_REG_POWER, val); 1006 sc->sc_port_suspended = 0; 1007 sc->sc_port_suspended_change = 1; 1008 } 1009 break; 1010 case UHF_PORT_RESET: 1011 break; 1012 case UHF_C_PORT_CONNECTION: 1013 break; 1014 case UHF_C_PORT_ENABLE: 1015 break; 1016 case UHF_C_PORT_OVER_CURRENT: 1017 break; 1018 case UHF_C_PORT_RESET: 1019 sc->sc_isreset = 0; 1020 err = USBD_NORMAL_COMPLETION; 1021 goto ret; 1022 case UHF_PORT_POWER: 1023 /* XXX todo */ 1024 break; 1025 case UHF_PORT_CONNECTION: 1026 case UHF_PORT_OVER_CURRENT: 1027 case UHF_PORT_LOW_SPEED: 1028 case UHF_C_PORT_SUSPEND: 1029 default: 1030 err = USBD_IOERROR; 1031 goto ret; 1032 } 1033 break; 1034 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1035 err = USBD_IOERROR; 1036 goto ret; 1037 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1038 if (len == 0) 1039 break; 1040 if ((value & 0xff) != 0) { 1041 err = USBD_IOERROR; 1042 goto ret; 1043 } 1044 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1045 totlen = l; 1046 memcpy(buf, &motg_hubd, l); 1047 break; 1048 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1049 if (len != 4) { 1050 err = USBD_IOERROR; 1051 goto ret; 1052 } 1053 memset(buf, 0, len); 1054 totlen = len; 1055 break; 1056 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1057 if (index != 1) { 1058 err = USBD_IOERROR; 1059 goto ret; 1060 } 1061 if (len != 4) { 1062 err = USBD_IOERROR; 1063 goto ret; 1064 } 1065 status = change = 0; 1066 if (sc->sc_connected) 1067 status |= UPS_CURRENT_CONNECT_STATUS; 1068 if (sc->sc_connected_changed) { 1069 change |= UPS_C_CONNECT_STATUS; 1070 sc->sc_connected_changed = 0; 1071 } 1072 if (sc->sc_port_enabled) 1073 status |= UPS_PORT_ENABLED; 1074 if (sc->sc_port_enabled_changed) { 1075 change |= UPS_C_PORT_ENABLED; 1076 sc->sc_port_enabled_changed = 0; 1077 } 1078 #if 0 /*XXX*/ 1079 if (x & MOTG_PORTSC_OCI) 1080 status |= UPS_OVERCURRENT_INDICATOR; 1081 if (x & MOTG_PORTSC_OCIC) 1082 change |= UPS_C_OVERCURRENT_INDICATOR; 1083 #endif 1084 if (sc->sc_port_suspended) 1085 status |= UPS_SUSPEND; 1086 if (sc->sc_high_speed) 1087 status |= UPS_HIGH_SPEED; 1088 status |= UPS_PORT_POWER; /* XXX */ 1089 if (sc->sc_isreset) 1090 change |= UPS_C_PORT_RESET; 1091 USETW(ps.wPortStatus, status); 1092 USETW(ps.wPortChange, change); 1093 l = min(len, sizeof ps); 1094 memcpy(buf, &ps, l); 1095 totlen = l; 1096 break; 1097 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1098 err = USBD_IOERROR; 1099 goto ret; 1100 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1101 break; 1102 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1103 if (index != 1) { 1104 err = USBD_IOERROR; 1105 goto ret; 1106 } 1107 switch(value) { 1108 case UHF_PORT_ENABLE: 1109 sc->sc_port_enabled = 1; 1110 break; 1111 case UHF_PORT_SUSPEND: 1112 if (sc->sc_port_suspended == 0) { 1113 val = UREAD1(sc, MUSB2_REG_POWER); 1114 val |= MUSB2_MASK_SUSPMODE; 1115 UWRITE1(sc, MUSB2_REG_POWER, val); 1116 /* wait 20 milliseconds */ 1117 usb_delay_ms(&sc->sc_bus, 20); 1118 sc->sc_port_suspended = 1; 1119 sc->sc_port_suspended_change = 1; 1120 } 1121 break; 1122 case UHF_PORT_RESET: 1123 err = motg_portreset(sc); 1124 goto ret; 1125 case UHF_PORT_POWER: 1126 /* XXX todo */ 1127 err = USBD_NORMAL_COMPLETION; 1128 goto ret; 1129 case UHF_C_PORT_CONNECTION: 1130 case UHF_C_PORT_ENABLE: 1131 case UHF_C_PORT_OVER_CURRENT: 1132 case UHF_PORT_CONNECTION: 1133 case UHF_PORT_OVER_CURRENT: 1134 case UHF_PORT_LOW_SPEED: 1135 case UHF_C_PORT_SUSPEND: 1136 case UHF_C_PORT_RESET: 1137 default: 1138 err = USBD_IOERROR; 1139 goto ret; 1140 } 1141 break; 1142 default: 1143 err = USBD_IOERROR; 1144 goto ret; 1145 } 1146 xfer->actlen = totlen; 1147 err = USBD_NORMAL_COMPLETION; 1148 ret: 1149 xfer->status = err; 1150 mutex_enter(&sc->sc_lock); 1151 usb_transfer_complete(xfer); 1152 mutex_exit(&sc->sc_lock); 1153 return (USBD_IN_PROGRESS); 1154 } 1155 1156 /* Abort a root control request. */ 1157 void 1158 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1159 { 1160 /* Nothing to do, all transfers are synchronous. */ 1161 } 1162 1163 /* Close the root pipe. */ 1164 void 1165 motg_root_ctrl_close(usbd_pipe_handle pipe) 1166 { 1167 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1168 } 1169 1170 void 1171 motg_root_ctrl_done(usbd_xfer_handle xfer) 1172 { 1173 } 1174 1175 /* Abort a root interrupt request. */ 1176 void 1177 motg_root_intr_abort(usbd_xfer_handle xfer) 1178 { 1179 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1180 1181 KASSERT(mutex_owned(&sc->sc_lock)); 1182 1183 sc->sc_intr_xfer = NULL; 1184 1185 if (xfer->pipe->intrxfer == xfer) { 1186 DPRINTFN(MD_ROOT, ("motg_root_intr_abort: remove\n")); 1187 xfer->pipe->intrxfer = 0; 1188 } 1189 xfer->status = USBD_CANCELLED; 1190 #ifdef DIAGNOSTIC 1191 // XXX UXFER(xfer)->iinfo.isdone = 1; 1192 #endif 1193 usb_transfer_complete(xfer); 1194 } 1195 1196 usbd_status 1197 motg_root_intr_transfer(usbd_xfer_handle xfer) 1198 { 1199 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1200 usbd_status err; 1201 1202 /* Insert last in queue. */ 1203 mutex_enter(&sc->sc_lock); 1204 err = usb_insert_transfer(xfer); 1205 mutex_exit(&sc->sc_lock); 1206 if (err) 1207 return (err); 1208 1209 /* 1210 * Pipe isn't running (otherwise err would be USBD_INPROG), 1211 * start first 1212 */ 1213 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1214 } 1215 1216 /* Start a transfer on the root interrupt pipe */ 1217 usbd_status 1218 motg_root_intr_start(usbd_xfer_handle xfer) 1219 { 1220 usbd_pipe_handle pipe = xfer->pipe; 1221 struct motg_softc *sc = pipe->device->bus->hci_private; 1222 1223 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1224 xfer, xfer->length, xfer->flags)); 1225 1226 if (sc->sc_dying) 1227 return (USBD_IOERROR); 1228 1229 sc->sc_intr_xfer = xfer; 1230 return (USBD_IN_PROGRESS); 1231 } 1232 1233 /* Close the root interrupt pipe. */ 1234 void 1235 motg_root_intr_close(usbd_pipe_handle pipe) 1236 { 1237 struct motg_softc *sc = pipe->device->bus->hci_private; 1238 1239 KASSERT(mutex_owned(&sc->sc_lock)); 1240 1241 sc->sc_intr_xfer = NULL; 1242 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1243 } 1244 1245 void 1246 motg_root_intr_done(usbd_xfer_handle xfer) 1247 { 1248 } 1249 1250 void 1251 motg_noop(usbd_pipe_handle pipe) 1252 { 1253 } 1254 1255 static usbd_status 1256 motg_portreset(struct motg_softc *sc) 1257 { 1258 uint32_t val; 1259 1260 val = UREAD1(sc, MUSB2_REG_POWER); 1261 val |= MUSB2_MASK_RESET; 1262 UWRITE1(sc, MUSB2_REG_POWER, val); 1263 /* Wait for 20 msec */ 1264 usb_delay_ms(&sc->sc_bus, 20); 1265 1266 val = UREAD1(sc, MUSB2_REG_POWER); 1267 val &= ~MUSB2_MASK_RESET; 1268 UWRITE1(sc, MUSB2_REG_POWER, val); 1269 1270 /* determine line speed */ 1271 val = UREAD1(sc, MUSB2_REG_POWER); 1272 if (val & MUSB2_MASK_HSMODE) 1273 sc->sc_high_speed = 1; 1274 else 1275 sc->sc_high_speed = 0; 1276 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1277 sc->sc_high_speed)); 1278 1279 sc->sc_isreset = 1; 1280 sc->sc_port_enabled = 1; 1281 return (USBD_NORMAL_COMPLETION); 1282 } 1283 1284 /* 1285 * This routine is executed when an interrupt on the root hub is detected 1286 */ 1287 static void 1288 motg_hub_change(struct motg_softc *sc) 1289 { 1290 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1291 usbd_pipe_handle pipe; 1292 u_char *p; 1293 1294 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1295 1296 if (xfer == NULL) 1297 return; /* the interrupt pipe is not open */ 1298 1299 pipe = xfer->pipe; 1300 if (pipe->device == NULL || pipe->device->bus == NULL) 1301 return; /* device has detached */ 1302 1303 p = KERNADDR(&xfer->dmabuf, 0); 1304 p[0] = 1<<1; 1305 xfer->actlen = 1; 1306 xfer->status = USBD_NORMAL_COMPLETION; 1307 usb_transfer_complete(xfer); 1308 } 1309 1310 static uint8_t 1311 motg_speed(u_int8_t speed) 1312 { 1313 switch(speed) { 1314 case USB_SPEED_LOW: 1315 return MUSB2_MASK_TI_SPEED_LO; 1316 case USB_SPEED_FULL: 1317 return MUSB2_MASK_TI_SPEED_FS; 1318 case USB_SPEED_HIGH: 1319 return MUSB2_MASK_TI_SPEED_HS; 1320 default: 1321 panic("motg: unknown speed %d", speed); 1322 /* NOTREACHED */ 1323 } 1324 } 1325 1326 static uint8_t 1327 motg_type(u_int8_t type) 1328 { 1329 switch(type) { 1330 case UE_CONTROL: 1331 return MUSB2_MASK_TI_PROTO_CTRL; 1332 case UE_ISOCHRONOUS: 1333 return MUSB2_MASK_TI_PROTO_ISOC; 1334 case UE_BULK: 1335 return MUSB2_MASK_TI_PROTO_BULK; 1336 case UE_INTERRUPT: 1337 return MUSB2_MASK_TI_PROTO_INTR; 1338 default: 1339 panic("motg: unknown type %d", type); 1340 /* NOTREACHED */ 1341 } 1342 } 1343 1344 static void 1345 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1346 { 1347 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1348 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1349 usbd_device_handle dev = otgpipe->pipe.device; 1350 int epnumber = otgpipe->hw_ep->ep_number; 1351 1352 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1353 if (dev->myhsport) { 1354 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1355 dev->myhsport->parent->address); 1356 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1357 dev->myhsport->portno); 1358 } else { 1359 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1360 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1361 } 1362 UWRITE1(sc, MUSB2_REG_TXTI, 1363 motg_speed(dev->speed) | 1364 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1365 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1366 ); 1367 if (epnumber == 0) { 1368 if (sc->sc_high_speed) { 1369 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1370 NAK_TO_CTRL_HIGH); 1371 } else { 1372 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1373 } 1374 } else { 1375 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1376 == UE_BULK) { 1377 if (sc->sc_high_speed) { 1378 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1379 NAK_TO_BULK_HIGH); 1380 } else { 1381 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1382 } 1383 } else { 1384 if (sc->sc_high_speed) { 1385 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1386 } else { 1387 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1388 } 1389 } 1390 } 1391 } 1392 1393 static void 1394 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1395 { 1396 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1397 usbd_device_handle dev = xfer->pipe->device; 1398 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1399 int epnumber = otgpipe->hw_ep->ep_number; 1400 1401 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1402 if (dev->myhsport) { 1403 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1404 dev->myhsport->parent->address); 1405 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1406 dev->myhsport->portno); 1407 } else { 1408 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1409 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1410 } 1411 UWRITE1(sc, MUSB2_REG_RXTI, 1412 motg_speed(dev->speed) | 1413 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1414 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1415 ); 1416 if (epnumber == 0) { 1417 if (sc->sc_high_speed) { 1418 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1419 NAK_TO_CTRL_HIGH); 1420 } else { 1421 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1422 } 1423 } else { 1424 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1425 == UE_BULK) { 1426 if (sc->sc_high_speed) { 1427 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1428 NAK_TO_BULK_HIGH); 1429 } else { 1430 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1431 } 1432 } else { 1433 if (sc->sc_high_speed) { 1434 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1435 } else { 1436 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1437 } 1438 } 1439 } 1440 } 1441 1442 static usbd_status 1443 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1444 { 1445 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1446 usbd_status err; 1447 1448 /* Insert last in queue. */ 1449 mutex_enter(&sc->sc_lock); 1450 err = usb_insert_transfer(xfer); 1451 mutex_exit(&sc->sc_lock); 1452 if (err) 1453 return (err); 1454 1455 /* 1456 * Pipe isn't running (otherwise err would be USBD_INPROG), 1457 * so start it first. 1458 */ 1459 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1460 } 1461 1462 static usbd_status 1463 motg_device_ctrl_start(usbd_xfer_handle xfer) 1464 { 1465 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1466 usbd_status err; 1467 mutex_enter(&sc->sc_lock); 1468 err = motg_device_ctrl_start1(sc); 1469 mutex_exit(&sc->sc_lock); 1470 if (err != USBD_IN_PROGRESS) 1471 return err; 1472 if (sc->sc_bus.use_polling) 1473 motg_waitintr(sc, xfer); 1474 return USBD_IN_PROGRESS; 1475 } 1476 1477 static usbd_status 1478 motg_device_ctrl_start1(struct motg_softc *sc) 1479 { 1480 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1481 usbd_xfer_handle xfer; 1482 struct motg_pipe *otgpipe; 1483 usbd_status err = 0; 1484 1485 KASSERT(mutex_owned(&sc->sc_lock)); 1486 if (sc->sc_dying) 1487 return (USBD_IOERROR); 1488 1489 if (!sc->sc_connected) 1490 return (USBD_IOERROR); 1491 1492 if (ep->xfer != NULL) { 1493 err = USBD_IN_PROGRESS; 1494 goto end; 1495 } 1496 /* locate the first pipe with work to do */ 1497 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1498 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1499 if (xfer != NULL) { 1500 /* move this pipe to the end of the list */ 1501 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1502 motg_pipe, ep_pipe_list); 1503 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1504 otgpipe, ep_pipe_list); 1505 break; 1506 } 1507 } 1508 if (xfer == NULL) { 1509 err = USBD_NOT_STARTED; 1510 goto end; 1511 } 1512 KASSERT(xfer != NULL); 1513 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1514 KASSERT(otgpipe->hw_ep == ep); 1515 #ifdef DIAGNOSTIC 1516 if (!(xfer->rqflags & URQ_REQUEST)) 1517 panic("motg_device_ctrl_transfer: not a request"); 1518 #endif 1519 // KASSERT(xfer->actlen == 0); 1520 xfer->actlen = 0; 1521 1522 ep->xfer = xfer; 1523 ep->datalen = xfer->length; 1524 if (ep->datalen > 0) 1525 ep->data = KERNADDR(&xfer->dmabuf, 0); 1526 else 1527 ep->data = NULL; 1528 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1529 (ep->datalen % 64) == 0) 1530 ep->need_short_xfer = 1; 1531 else 1532 ep->need_short_xfer = 0; 1533 /* now we need send this request */ 1534 DPRINTFN(MD_CTRL, 1535 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1536 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1537 xfer->pipe->device->address)); 1538 KASSERT(ep->phase == IDLE); 1539 ep->phase = SETUP; 1540 /* select endpoint 0 */ 1541 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1542 /* fifo should be empty at this point */ 1543 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1544 /* send data */ 1545 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1546 KASSERT(sizeof(xfer->request) == 8); 1547 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1548 (void *)&xfer->request, sizeof(xfer->request)); 1549 1550 motg_setup_endpoint_tx(xfer); 1551 /* start transaction */ 1552 UWRITE1(sc, MUSB2_REG_TXCSRL, 1553 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1554 1555 end: 1556 if (err) 1557 return (err); 1558 1559 return (USBD_IN_PROGRESS); 1560 } 1561 1562 static void 1563 motg_device_ctrl_read(usbd_xfer_handle xfer) 1564 { 1565 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1566 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1567 /* assume endpoint already selected */ 1568 motg_setup_endpoint_rx(xfer); 1569 /* start transaction */ 1570 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1571 otgpipe->hw_ep->phase = DATA_IN; 1572 } 1573 1574 static void 1575 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1576 { 1577 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1578 usbd_xfer_handle xfer = ep->xfer; 1579 uint8_t csr; 1580 int datalen, max_datalen; 1581 char *data; 1582 bool got_short; 1583 1584 KASSERT(mutex_owned(&sc->sc_lock)); 1585 1586 #ifdef DIAGNOSTIC 1587 if (ep->phase != DATA_IN && 1588 ep->phase != STATUS_IN) 1589 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1590 #endif 1591 /* select endpoint 0 */ 1592 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1593 1594 /* read out FIFO status */ 1595 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1596 DPRINTFN(MD_CTRL, 1597 ("motg_device_ctrl_intr_rx phase %d csr 0x%x\n", 1598 ep->phase, csr)); 1599 1600 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1601 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1602 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1603 1604 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1605 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1606 if (xfer) 1607 xfer->status = USBD_TIMEOUT; /* XXX */ 1608 goto complete; 1609 } 1610 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1611 if (xfer) { 1612 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1613 xfer->status = USBD_STALLED; 1614 else 1615 xfer->status = USBD_IOERROR; 1616 } 1617 /* clear status */ 1618 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1619 goto complete; 1620 } 1621 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1622 return; /* no data yet */ 1623 1624 if (xfer == NULL) 1625 goto complete; 1626 1627 if (ep->phase == STATUS_IN) { 1628 xfer->status = USBD_NORMAL_COMPLETION; 1629 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1630 goto complete; 1631 } 1632 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1633 DPRINTFN(MD_CTRL, 1634 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1635 ep->phase, datalen)); 1636 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1637 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1638 ep->datalen); 1639 if (datalen > max_datalen) { 1640 xfer->status = USBD_IOERROR; 1641 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1642 goto complete; 1643 } 1644 got_short = (datalen < max_datalen); 1645 if (datalen > 0) { 1646 KASSERT(ep->phase == DATA_IN); 1647 data = ep->data; 1648 ep->data += datalen; 1649 ep->datalen -= datalen; 1650 xfer->actlen += datalen; 1651 if (((vaddr_t)data & 0x3) == 0 && 1652 (datalen >> 2) > 0) { 1653 DPRINTFN(MD_CTRL, 1654 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1655 data, datalen)); 1656 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1657 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1658 data += (datalen & ~0x3); 1659 datalen -= (datalen & ~0x3); 1660 } 1661 DPRINTFN(MD_CTRL, 1662 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1663 data, datalen)); 1664 if (datalen) { 1665 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1666 MUSB2_REG_EPFIFO(0), data, datalen); 1667 } 1668 } 1669 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1670 KASSERT(ep->phase == DATA_IN); 1671 if (got_short || (ep->datalen == 0)) { 1672 if (ep->need_short_xfer == 0) { 1673 ep->phase = STATUS_OUT; 1674 UWRITE1(sc, MUSB2_REG_TXCSRH, 1675 UREAD1(sc, MUSB2_REG_TXCSRH) | 1676 MUSB2_MASK_CSR0H_PING_DIS); 1677 motg_setup_endpoint_tx(xfer); 1678 UWRITE1(sc, MUSB2_REG_TXCSRL, 1679 MUSB2_MASK_CSR0L_STATUSPKT | 1680 MUSB2_MASK_CSR0L_TXPKTRDY); 1681 return; 1682 } 1683 ep->need_short_xfer = 0; 1684 } 1685 motg_device_ctrl_read(xfer); 1686 return; 1687 complete: 1688 ep->phase = IDLE; 1689 ep->xfer = NULL; 1690 if (xfer) 1691 usb_transfer_complete(xfer); 1692 motg_device_ctrl_start1(sc); 1693 } 1694 1695 static void 1696 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1697 { 1698 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1699 usbd_xfer_handle xfer = ep->xfer; 1700 uint8_t csr; 1701 int datalen; 1702 char *data; 1703 1704 KASSERT(mutex_owned(&sc->sc_lock)); 1705 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1706 motg_device_ctrl_intr_rx(sc); 1707 return; 1708 } 1709 1710 #ifdef DIAGNOSTIC 1711 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1712 ep->phase != STATUS_OUT) 1713 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1714 #endif 1715 /* select endpoint 0 */ 1716 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1717 1718 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1719 DPRINTFN(MD_CTRL, 1720 ("motg_device_ctrl_intr_tx phase %d csr 0x%x\n", 1721 ep->phase, csr)); 1722 1723 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1724 /* command not accepted */ 1725 if (xfer) 1726 xfer->status = USBD_STALLED; 1727 /* clear status */ 1728 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1729 goto complete; 1730 } 1731 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1732 if (xfer) 1733 xfer->status = USBD_TIMEOUT; /* XXX */ 1734 /* flush fifo */ 1735 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1736 UWRITE1(sc, MUSB2_REG_TXCSRH, 1737 UREAD1(sc, MUSB2_REG_TXCSRH) | 1738 MUSB2_MASK_CSR0H_FFLUSH); 1739 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1740 } 1741 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1742 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1743 goto complete; 1744 } 1745 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1746 if (xfer) 1747 xfer->status = USBD_IOERROR; 1748 /* clear status */ 1749 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1750 goto complete; 1751 } 1752 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1753 /* data still not sent */ 1754 return; 1755 } 1756 if (xfer == NULL) 1757 goto complete; 1758 if (ep->phase == STATUS_OUT) { 1759 /* 1760 * we have sent status and got no error; 1761 * declare transfer complete 1762 */ 1763 DPRINTFN(MD_CTRL, 1764 ("motg_device_ctrl_intr_tx %p complete\n", xfer)); 1765 xfer->status = USBD_NORMAL_COMPLETION; 1766 goto complete; 1767 } 1768 if (ep->datalen == 0) { 1769 if (ep->need_short_xfer) { 1770 ep->need_short_xfer = 0; 1771 /* one more data phase */ 1772 if (xfer->request.bmRequestType & UT_READ) { 1773 DPRINTFN(MD_CTRL, 1774 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1775 motg_device_ctrl_read(xfer); 1776 return; 1777 } /* else fall back to DATA_OUT */ 1778 } else { 1779 DPRINTFN(MD_CTRL, 1780 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1781 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1782 ep->phase = STATUS_IN; 1783 UWRITE1(sc, MUSB2_REG_RXCSRH, 1784 UREAD1(sc, MUSB2_REG_RXCSRH) | 1785 MUSB2_MASK_CSR0H_PING_DIS); 1786 motg_setup_endpoint_rx(xfer); 1787 UWRITE1(sc, MUSB2_REG_TXCSRL, 1788 MUSB2_MASK_CSR0L_STATUSPKT | 1789 MUSB2_MASK_CSR0L_REQPKT); 1790 return; 1791 } 1792 } 1793 if (xfer->request.bmRequestType & UT_READ) { 1794 motg_device_ctrl_read(xfer); 1795 return; 1796 } 1797 /* setup a dataout phase */ 1798 datalen = min(ep->datalen, 1799 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1800 ep->phase = DATA_OUT; 1801 DPRINTFN(MD_CTRL, 1802 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1803 UREAD1(sc, MUSB2_REG_TXCSRH))); 1804 if (datalen) { 1805 data = ep->data; 1806 ep->data += datalen; 1807 ep->datalen -= datalen; 1808 xfer->actlen += datalen; 1809 if (((vaddr_t)data & 0x3) == 0 && 1810 (datalen >> 2) > 0) { 1811 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1812 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1813 data += (datalen & ~0x3); 1814 datalen -= (datalen & ~0x3); 1815 } 1816 if (datalen) { 1817 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1818 MUSB2_REG_EPFIFO(0), data, datalen); 1819 } 1820 } 1821 /* send data */ 1822 motg_setup_endpoint_tx(xfer); 1823 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1824 return; 1825 1826 complete: 1827 ep->phase = IDLE; 1828 ep->xfer = NULL; 1829 if (xfer) 1830 usb_transfer_complete(xfer); 1831 motg_device_ctrl_start1(sc); 1832 } 1833 1834 /* Abort a device control request. */ 1835 void 1836 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1837 { 1838 #ifdef DIAGNOSTIC 1839 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1840 #endif 1841 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1842 KASSERT(mutex_owned(&sc->sc_lock)); 1843 1844 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1845 if (otgpipe->hw_ep->xfer == xfer) 1846 otgpipe->hw_ep->xfer = NULL; 1847 xfer->status = USBD_CANCELLED; 1848 usb_transfer_complete(xfer); 1849 } 1850 1851 /* Close a device control pipe */ 1852 void 1853 motg_device_ctrl_close(usbd_pipe_handle pipe) 1854 { 1855 struct motg_softc *sc = pipe->device->bus->hci_private; 1856 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1857 struct motg_pipe *otgpipeiter; 1858 1859 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1860 KASSERT(mutex_owned(&sc->sc_lock)); 1861 KASSERT(otgpipe->hw_ep->xfer == NULL || 1862 otgpipe->hw_ep->xfer->pipe != pipe); 1863 1864 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1865 if (otgpipeiter == otgpipe) { 1866 /* remove from list */ 1867 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1868 motg_pipe, ep_pipe_list); 1869 otgpipe->hw_ep->refcount--; 1870 /* we're done */ 1871 return; 1872 } 1873 } 1874 panic("motg_device_ctrl_close: not found"); 1875 } 1876 1877 void 1878 motg_device_ctrl_done(usbd_xfer_handle xfer) 1879 { 1880 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1881 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1882 KASSERT(otgpipe->hw_ep->xfer != xfer); 1883 } 1884 1885 static usbd_status 1886 motg_device_data_transfer(usbd_xfer_handle xfer) 1887 { 1888 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1889 usbd_status err; 1890 1891 /* Insert last in queue. */ 1892 mutex_enter(&sc->sc_lock); 1893 err = usb_insert_transfer(xfer); 1894 mutex_exit(&sc->sc_lock); 1895 if (err) 1896 return (err); 1897 1898 /* 1899 * Pipe isn't running (otherwise err would be USBD_INPROG), 1900 * so start it first. 1901 */ 1902 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1903 } 1904 1905 static usbd_status 1906 motg_device_data_start(usbd_xfer_handle xfer) 1907 { 1908 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1909 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1910 usbd_status err; 1911 mutex_enter(&sc->sc_lock); 1912 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1913 mutex_exit(&sc->sc_lock); 1914 if (err != USBD_IN_PROGRESS) 1915 return err; 1916 if (sc->sc_bus.use_polling) 1917 motg_waitintr(sc, xfer); 1918 return USBD_IN_PROGRESS; 1919 } 1920 1921 static usbd_status 1922 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1923 { 1924 usbd_xfer_handle xfer; 1925 struct motg_pipe *otgpipe; 1926 usbd_status err = 0; 1927 uint32_t val; 1928 1929 KASSERT(mutex_owned(&sc->sc_lock)); 1930 if (sc->sc_dying) 1931 return (USBD_IOERROR); 1932 1933 if (!sc->sc_connected) 1934 return (USBD_IOERROR); 1935 1936 if (ep->xfer != NULL) { 1937 err = USBD_IN_PROGRESS; 1938 goto end; 1939 } 1940 /* locate the first pipe with work to do */ 1941 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1942 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1943 if (xfer != NULL) { 1944 /* move this pipe to the end of the list */ 1945 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1946 motg_pipe, ep_pipe_list); 1947 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1948 otgpipe, ep_pipe_list); 1949 break; 1950 } 1951 } 1952 if (xfer == NULL) { 1953 err = USBD_NOT_STARTED; 1954 goto end; 1955 } 1956 KASSERT(xfer != NULL); 1957 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1958 KASSERT(otgpipe->hw_ep == ep); 1959 #ifdef DIAGNOSTIC 1960 if (xfer->rqflags & URQ_REQUEST) 1961 panic("motg_device_data_transfer: a request"); 1962 #endif 1963 // KASSERT(xfer->actlen == 0); 1964 xfer->actlen = 0; 1965 1966 ep->xfer = xfer; 1967 ep->datalen = xfer->length; 1968 KASSERT(ep->datalen > 0); 1969 ep->data = KERNADDR(&xfer->dmabuf, 0); 1970 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1971 (ep->datalen % 64) == 0) 1972 ep->need_short_xfer = 1; 1973 else 1974 ep->need_short_xfer = 0; 1975 /* now we need send this request */ 1976 DPRINTFN(MD_BULK, 1977 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 1978 xfer, 1979 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 1980 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1981 xfer->pipe->device->address)); 1982 KASSERT(ep->phase == IDLE); 1983 /* select endpoint */ 1984 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1985 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 1986 == UE_DIR_IN) { 1987 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1988 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1989 motg_device_data_read(xfer); 1990 } else { 1991 ep->phase = DATA_OUT; 1992 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1993 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1994 motg_device_data_write(xfer); 1995 } 1996 end: 1997 if (err) 1998 return (err); 1999 2000 return (USBD_IN_PROGRESS); 2001 } 2002 2003 static void 2004 motg_device_data_read(usbd_xfer_handle xfer) 2005 { 2006 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2007 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2008 uint32_t val; 2009 2010 KASSERT(mutex_owned(&sc->sc_lock)); 2011 /* assume endpoint already selected */ 2012 motg_setup_endpoint_rx(xfer); 2013 /* Max packet size */ 2014 UWRITE2(sc, MUSB2_REG_RXMAXP, 2015 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2016 /* Data Toggle */ 2017 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2018 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2019 if (otgpipe->nexttoggle) 2020 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2021 else 2022 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2023 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2024 2025 DPRINTFN(MD_BULK, 2026 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2027 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2028 /* start transaction */ 2029 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2030 otgpipe->hw_ep->phase = DATA_IN; 2031 } 2032 2033 static void 2034 motg_device_data_write(usbd_xfer_handle xfer) 2035 { 2036 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2037 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2038 struct motg_hw_ep *ep = otgpipe->hw_ep; 2039 int datalen; 2040 char *data; 2041 uint32_t val; 2042 2043 KASSERT(xfer!=NULL); 2044 KASSERT(mutex_owned(&sc->sc_lock)); 2045 2046 datalen = min(ep->datalen, 2047 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2048 ep->phase = DATA_OUT; 2049 DPRINTFN(MD_BULK, 2050 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2051 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2052 2053 /* assume endpoint already selected */ 2054 /* write data to fifo */ 2055 data = ep->data; 2056 ep->data += datalen; 2057 ep->datalen -= datalen; 2058 xfer->actlen += datalen; 2059 if (((vaddr_t)data & 0x3) == 0 && 2060 (datalen >> 2) > 0) { 2061 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2062 MUSB2_REG_EPFIFO(ep->ep_number), 2063 (void *)data, datalen >> 2); 2064 data += (datalen & ~0x3); 2065 datalen -= (datalen & ~0x3); 2066 } 2067 if (datalen) { 2068 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2069 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2070 } 2071 2072 motg_setup_endpoint_tx(xfer); 2073 /* Max packet size */ 2074 UWRITE2(sc, MUSB2_REG_TXMAXP, 2075 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2076 /* Data Toggle */ 2077 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2078 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2079 if (otgpipe->nexttoggle) 2080 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2081 else 2082 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2083 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2084 2085 /* start transaction */ 2086 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2087 } 2088 2089 static void 2090 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2091 { 2092 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2093 usbd_xfer_handle xfer = ep->xfer; 2094 uint8_t csr; 2095 int datalen, max_datalen; 2096 char *data; 2097 bool got_short; 2098 2099 KASSERT(mutex_owned(&sc->sc_lock)); 2100 KASSERT(ep->ep_number == epnumber); 2101 2102 DPRINTFN(MD_BULK, 2103 ("motg_device_intr_rx on ep %d\n", epnumber)); 2104 /* select endpoint */ 2105 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2106 2107 /* read out FIFO status */ 2108 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2109 DPRINTFN(MD_BULK, 2110 ("motg_device_intr_rx phase %d csr 0x%x\n", 2111 ep->phase, csr)); 2112 2113 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2114 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2115 return; 2116 2117 #ifdef DIAGNOSTIC 2118 if (ep->phase != DATA_IN) 2119 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2120 #endif 2121 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2122 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2123 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2124 2125 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2126 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2127 if (xfer) 2128 xfer->status = USBD_TIMEOUT; /* XXX */ 2129 goto complete; 2130 } 2131 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2132 if (xfer) { 2133 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2134 xfer->status = USBD_STALLED; 2135 else 2136 xfer->status = USBD_IOERROR; 2137 } 2138 /* clear status */ 2139 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2140 goto complete; 2141 } 2142 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2143 2144 if (xfer == NULL) { 2145 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2146 goto complete; 2147 } 2148 2149 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2150 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2151 2152 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2153 DPRINTFN(MD_BULK, 2154 ("motg_device_intr_rx phase %d datalen %d\n", 2155 ep->phase, datalen)); 2156 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2157 max_datalen = min( 2158 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2159 ep->datalen); 2160 if (datalen > max_datalen) { 2161 xfer->status = USBD_IOERROR; 2162 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2163 goto complete; 2164 } 2165 got_short = (datalen < max_datalen); 2166 if (datalen > 0) { 2167 KASSERT(ep->phase == DATA_IN); 2168 data = ep->data; 2169 ep->data += datalen; 2170 ep->datalen -= datalen; 2171 xfer->actlen += datalen; 2172 if (((vaddr_t)data & 0x3) == 0 && 2173 (datalen >> 2) > 0) { 2174 DPRINTFN(MD_BULK, 2175 ("motg_device_intr_rx r4 data %p len %d\n", 2176 data, datalen)); 2177 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2178 MUSB2_REG_EPFIFO(ep->ep_number), 2179 (void *)data, datalen >> 2); 2180 data += (datalen & ~0x3); 2181 datalen -= (datalen & ~0x3); 2182 } 2183 DPRINTFN(MD_BULK, 2184 ("motg_device_intr_rx r1 data %p len %d\n", 2185 data, datalen)); 2186 if (datalen) { 2187 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2188 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2189 } 2190 } 2191 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2192 KASSERT(ep->phase == DATA_IN); 2193 if (got_short || (ep->datalen == 0)) { 2194 if (ep->need_short_xfer == 0) { 2195 xfer->status = USBD_NORMAL_COMPLETION; 2196 goto complete; 2197 } 2198 ep->need_short_xfer = 0; 2199 } 2200 motg_device_data_read(xfer); 2201 return; 2202 complete: 2203 DPRINTFN(MD_BULK, 2204 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2205 (xfer != NULL) ? xfer->status : 0)); 2206 ep->phase = IDLE; 2207 ep->xfer = NULL; 2208 if (xfer) 2209 usb_transfer_complete(xfer); 2210 motg_device_data_start1(sc, ep); 2211 } 2212 2213 static void 2214 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2215 { 2216 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2217 usbd_xfer_handle xfer = ep->xfer; 2218 uint8_t csr; 2219 struct motg_pipe *otgpipe; 2220 2221 KASSERT(mutex_owned(&sc->sc_lock)); 2222 KASSERT(ep->ep_number == epnumber); 2223 2224 DPRINTFN(MD_BULK, 2225 ("motg_device_intr_tx on ep %d\n", epnumber)); 2226 /* select endpoint */ 2227 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2228 2229 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2230 DPRINTFN(MD_BULK, 2231 ("motg_device_intr_tx phase %d csr 0x%x\n", 2232 ep->phase, csr)); 2233 2234 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2235 /* command not accepted */ 2236 if (xfer) { 2237 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2238 xfer->status = USBD_STALLED; 2239 else 2240 xfer->status = USBD_IOERROR; 2241 } 2242 /* clear status */ 2243 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2244 goto complete; 2245 } 2246 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2247 if (xfer) 2248 xfer->status = USBD_TIMEOUT; /* XXX */ 2249 /* flush fifo */ 2250 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2251 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2252 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2253 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2254 } 2255 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 2256 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2257 goto complete; 2258 } 2259 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2260 /* data still not sent */ 2261 return; 2262 } 2263 if (xfer == NULL) 2264 goto complete; 2265 #ifdef DIAGNOSTIC 2266 if (ep->phase != DATA_OUT) 2267 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2268 #endif 2269 2270 otgpipe = (struct motg_pipe *)xfer->pipe; 2271 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2272 2273 if (ep->datalen == 0) { 2274 if (ep->need_short_xfer) { 2275 ep->need_short_xfer = 0; 2276 /* one more data phase */ 2277 } else { 2278 xfer->status = USBD_NORMAL_COMPLETION; 2279 goto complete; 2280 } 2281 } 2282 motg_device_data_write(xfer); 2283 return; 2284 2285 complete: 2286 DPRINTFN(MD_BULK, 2287 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2288 (xfer != NULL) ? xfer->status : 0)); 2289 #ifdef DIAGNOSTIC 2290 if (xfer && ep->phase != DATA_OUT) 2291 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2292 #endif 2293 ep->phase = IDLE; 2294 ep->xfer = NULL; 2295 if (xfer) 2296 usb_transfer_complete(xfer); 2297 motg_device_data_start1(sc, ep); 2298 } 2299 2300 /* Abort a device control request. */ 2301 void 2302 motg_device_data_abort(usbd_xfer_handle xfer) 2303 { 2304 #ifdef DIAGNOSTIC 2305 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2306 #endif 2307 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2308 uint8_t csr; 2309 2310 KASSERT(mutex_owned(&sc->sc_lock)); 2311 2312 DPRINTFN(MD_BULK, 2313 ("motg_device_data_abort:\n")); 2314 if (otgpipe->hw_ep->xfer == xfer) { 2315 otgpipe->hw_ep->xfer = NULL; 2316 /* select endpoint */ 2317 UWRITE1(sc, MUSB2_REG_EPINDEX, otgpipe->hw_ep->ep_number); 2318 if (otgpipe->hw_ep->phase == DATA_OUT) { 2319 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2320 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2321 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2322 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2323 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2324 } 2325 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2326 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2327 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2328 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2329 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2330 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2331 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2332 } 2333 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2334 } 2335 otgpipe->hw_ep->phase = IDLE; 2336 } 2337 2338 xfer->status = USBD_CANCELLED; 2339 usb_transfer_complete(xfer); 2340 } 2341 2342 /* Close a device control pipe */ 2343 void 2344 motg_device_data_close(usbd_pipe_handle pipe) 2345 { 2346 struct motg_softc *sc = pipe->device->bus->hci_private; 2347 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2348 struct motg_pipe *otgpipeiter; 2349 2350 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2351 KASSERT(mutex_owned(&sc->sc_lock)); 2352 KASSERT(otgpipe->hw_ep->xfer == NULL || 2353 otgpipe->hw_ep->xfer->pipe != pipe); 2354 2355 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2356 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2357 if (otgpipeiter == otgpipe) { 2358 /* remove from list */ 2359 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2360 motg_pipe, ep_pipe_list); 2361 otgpipe->hw_ep->refcount--; 2362 /* we're done */ 2363 return; 2364 } 2365 } 2366 panic("motg_device_data_close: not found"); 2367 } 2368 2369 void 2370 motg_device_data_done(usbd_xfer_handle xfer) 2371 { 2372 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2373 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2374 KASSERT(otgpipe->hw_ep->xfer != xfer); 2375 } 2376 2377 /* 2378 * Wait here until controller claims to have an interrupt. 2379 * Then call motg_intr and return. Use timeout to avoid waiting 2380 * too long. 2381 * Only used during boot when interrupts are not enabled yet. 2382 */ 2383 void 2384 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2385 { 2386 int timo = xfer->timeout; 2387 2388 mutex_enter(&sc->sc_lock); 2389 2390 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2391 2392 xfer->status = USBD_IN_PROGRESS; 2393 for (; timo >= 0; timo--) { 2394 mutex_exit(&sc->sc_lock); 2395 usb_delay_ms(&sc->sc_bus, 1); 2396 mutex_spin_enter(&sc->sc_intr_lock); 2397 motg_poll(&sc->sc_bus); 2398 mutex_spin_exit(&sc->sc_intr_lock); 2399 mutex_enter(&sc->sc_lock); 2400 if (xfer->status != USBD_IN_PROGRESS) 2401 goto done; 2402 } 2403 2404 /* Timeout */ 2405 DPRINTF(("motg_waitintr: timeout\n")); 2406 panic("motg_waitintr: timeout"); 2407 /* XXX handle timeout ! */ 2408 2409 done: 2410 mutex_exit(&sc->sc_lock); 2411 } 2412 2413 void 2414 motg_device_clear_toggle(usbd_pipe_handle pipe) 2415 { 2416 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2417 otgpipe->nexttoggle = 0; 2418 } 2419
Indexes created Fri Sep 26 20:09:58 GMT 2025