motg.c revision 1.20
1 /* $NetBSD: motg.c,v 1.20 2018/04/08 13:36:37 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.20 2018/04/08 13:36:37 jmcneill Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_usb.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usbhist.h> 69 70 #include <dev/usb/motgreg.h> 71 #include <dev/usb/motgvar.h> 72 #include <dev/usb/usbroothub.h> 73 74 #ifdef USB_DEBUG 75 #ifndef MOTG_DEBUG 76 #define motgdebug 0 77 #else 78 int motgdebug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 88 SYSCTL_DESCR("motg global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 107 #endif /* MOTG_DEBUG */ 108 #endif /* USB_DEBUG */ 109 110 #define MD_ROOT 0x0002 111 #define MD_CTRL 0x0004 112 #define MD_BULK 0x0008 113 114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 116 #define MOTGHIST_FUNC() USBHIST_FUNC() 117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 118 119 120 /* various timeouts, for various speeds */ 121 /* control NAK timeouts */ 122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 124 125 /* intr/iso polling intervals */ 126 #define POLL_TO 100 /* 100 frames, about 0.1s */ 127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 128 129 /* bulk NAK timeouts */ 130 #define NAK_TO_BULK 0 /* disabled */ 131 #define NAK_TO_BULK_HIGH 0 132 133 static void motg_hub_change(struct motg_softc *); 134 135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 136 static usbd_status motg_root_intr_start(struct usbd_xfer *); 137 static void motg_root_intr_abort(struct usbd_xfer *); 138 static void motg_root_intr_close(struct usbd_pipe *); 139 static void motg_root_intr_done(struct usbd_xfer *); 140 141 static usbd_status motg_open(struct usbd_pipe *); 142 static void motg_poll(struct usbd_bus *); 143 static void motg_softintr(void *); 144 static struct usbd_xfer * 145 motg_allocx(struct usbd_bus *, unsigned int); 146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 147 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 148 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 149 void *, int); 150 151 static void motg_noop(struct usbd_pipe *pipe); 152 static usbd_status motg_portreset(struct motg_softc*); 153 154 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 155 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 156 static void motg_device_ctrl_abort(struct usbd_xfer *); 157 static void motg_device_ctrl_close(struct usbd_pipe *); 158 static void motg_device_ctrl_done(struct usbd_xfer *); 159 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 160 static void motg_device_ctrl_read(struct usbd_xfer *); 161 static void motg_device_ctrl_intr_rx(struct motg_softc *); 162 static void motg_device_ctrl_intr_tx(struct motg_softc *); 163 164 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 165 static usbd_status motg_device_data_start(struct usbd_xfer *); 166 static usbd_status motg_device_data_start1(struct motg_softc *, 167 struct motg_hw_ep *); 168 static void motg_device_data_abort(struct usbd_xfer *); 169 static void motg_device_data_close(struct usbd_pipe *); 170 static void motg_device_data_done(struct usbd_xfer *); 171 static void motg_device_intr_rx(struct motg_softc *, int); 172 static void motg_device_intr_tx(struct motg_softc *, int); 173 static void motg_device_data_read(struct usbd_xfer *); 174 static void motg_device_data_write(struct usbd_xfer *); 175 176 static void motg_device_clear_toggle(struct usbd_pipe *); 177 static void motg_device_xfer_abort(struct usbd_xfer *); 178 179 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 180 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 181 #define UWRITE1(sc, r, x) \ 182 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 183 } while (/*CONSTCOND*/0) 184 #define UWRITE2(sc, r, x) \ 185 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 186 } while (/*CONSTCOND*/0) 187 #define UWRITE4(sc, r, x) \ 188 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 189 } while (/*CONSTCOND*/0) 190 191 static __inline uint32_t 192 UREAD1(struct motg_softc *sc, bus_size_t r) 193 { 194 195 UBARR(sc); 196 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 197 } 198 static __inline uint32_t 199 UREAD2(struct motg_softc *sc, bus_size_t r) 200 { 201 202 UBARR(sc); 203 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 204 } 205 206 #if 0 207 static __inline uint32_t 208 UREAD4(struct motg_softc *sc, bus_size_t r) 209 { 210 211 UBARR(sc); 212 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 213 } 214 #endif 215 216 static void 217 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 218 { 219 uint8_t val; 220 221 val = UREAD1(sc, MUSB2_REG_POWER); 222 if (on) 223 val |= MUSB2_MASK_SOFTC; 224 else 225 val &= ~MUSB2_MASK_SOFTC; 226 227 UWRITE1(sc, MUSB2_REG_POWER, val); 228 } 229 230 const struct usbd_bus_methods motg_bus_methods = { 231 .ubm_open = motg_open, 232 .ubm_softint = motg_softintr, 233 .ubm_dopoll = motg_poll, 234 .ubm_allocx = motg_allocx, 235 .ubm_freex = motg_freex, 236 .ubm_getlock = motg_get_lock, 237 .ubm_rhctrl = motg_roothub_ctrl, 238 }; 239 240 const struct usbd_pipe_methods motg_root_intr_methods = { 241 .upm_transfer = motg_root_intr_transfer, 242 .upm_start = motg_root_intr_start, 243 .upm_abort = motg_root_intr_abort, 244 .upm_close = motg_root_intr_close, 245 .upm_cleartoggle = motg_noop, 246 .upm_done = motg_root_intr_done, 247 }; 248 249 const struct usbd_pipe_methods motg_device_ctrl_methods = { 250 .upm_transfer = motg_device_ctrl_transfer, 251 .upm_start = motg_device_ctrl_start, 252 .upm_abort = motg_device_ctrl_abort, 253 .upm_close = motg_device_ctrl_close, 254 .upm_cleartoggle = motg_noop, 255 .upm_done = motg_device_ctrl_done, 256 }; 257 258 const struct usbd_pipe_methods motg_device_data_methods = { 259 .upm_transfer = motg_device_data_transfer, 260 .upm_start = motg_device_data_start, 261 .upm_abort = motg_device_data_abort, 262 .upm_close = motg_device_data_close, 263 .upm_cleartoggle = motg_device_clear_toggle, 264 .upm_done = motg_device_data_done, 265 }; 266 267 int 268 motg_init(struct motg_softc *sc) 269 { 270 uint32_t nrx, ntx, val; 271 int dynfifo; 272 int offset, i; 273 274 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 275 276 if (sc->sc_mode == MOTG_MODE_DEVICE) 277 return ENOTSUP; /* not supported */ 278 279 /* disable all interrupts */ 280 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 281 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 282 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 283 /* disable pullup */ 284 285 musbotg_pull_common(sc, 0); 286 287 #ifdef MUSB2_REG_RXDBDIS 288 /* disable double packet buffering XXX what's this ? */ 289 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 290 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 291 #endif 292 293 /* enable HighSpeed and ISO Update flags */ 294 295 UWRITE1(sc, MUSB2_REG_POWER, 296 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 297 298 if (sc->sc_mode == MOTG_MODE_DEVICE) { 299 /* clear Session bit, if set */ 300 val = UREAD1(sc, MUSB2_REG_DEVCTL); 301 val &= ~MUSB2_MASK_SESS; 302 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 303 } else { 304 /* Enter session for Host mode */ 305 val = UREAD1(sc, MUSB2_REG_DEVCTL); 306 val |= MUSB2_MASK_SESS; 307 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 308 } 309 delay(1000); 310 DPRINTF("DEVCTL 0x%jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 311 312 /* disable testmode */ 313 314 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 315 316 #ifdef MUSB2_REG_MISC 317 /* set default value */ 318 319 UWRITE1(sc, MUSB2_REG_MISC, 0); 320 #endif 321 322 /* select endpoint index 0 */ 323 324 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 325 326 if (sc->sc_ep_max == 0) { 327 /* read out number of endpoints */ 328 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 329 330 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 331 332 /* these numbers exclude the control endpoint */ 333 334 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 335 336 sc->sc_ep_max = MAX(nrx, ntx); 337 } else { 338 nrx = ntx = sc->sc_ep_max; 339 } 340 if (sc->sc_ep_max == 0) { 341 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 342 return -1; 343 } 344 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 345 /* read out configuration data */ 346 val = UREAD1(sc, MUSB2_REG_CONFDATA); 347 348 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 349 350 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 351 352 if (dynfifo) { 353 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 354 "assuming 16Kbytes of FIFO RAM\n"); 355 } 356 357 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 358 359 /* initialise endpoint profiles */ 360 sc->sc_in_ep[0].ep_fifo_size = 64; 361 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 362 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 363 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 364 offset = 64; 365 366 for (i = 1; i <= sc->sc_ep_max; i++) { 367 int fiforx_size, fifotx_size, fifo_size; 368 369 /* select endpoint */ 370 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 371 372 if (sc->sc_ep_fifosize) { 373 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 374 } else { 375 val = UREAD1(sc, MUSB2_REG_FSIZE); 376 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 377 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 378 } 379 380 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 381 i, fifotx_size, fiforx_size, dynfifo); 382 383 if (dynfifo) { 384 if (sc->sc_ep_fifosize) { 385 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 386 } else { 387 if (i < 3) { 388 fifo_size = 12; /* 4K */ 389 } else if (i < 10) { 390 fifo_size = 10; /* 1K */ 391 } else { 392 fifo_size = 7; /* 128 bytes */ 393 } 394 } 395 if (fiforx_size && (i <= nrx)) { 396 fiforx_size = fifo_size; 397 if (fifo_size > 7) { 398 #if 0 399 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 400 MUSB2_VAL_FIFOSZ(fifo_size) | 401 MUSB2_MASK_FIFODB); 402 #else 403 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 404 MUSB2_VAL_FIFOSZ(fifo_size)); 405 #endif 406 } else { 407 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 408 MUSB2_VAL_FIFOSZ(fifo_size)); 409 } 410 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 411 offset >> 3); 412 offset += (1 << fiforx_size); 413 } 414 if (fifotx_size && (i <= ntx)) { 415 fifotx_size = fifo_size; 416 if (fifo_size > 7) { 417 #if 0 418 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 419 MUSB2_VAL_FIFOSZ(fifo_size) | 420 MUSB2_MASK_FIFODB); 421 #else 422 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 423 MUSB2_VAL_FIFOSZ(fifo_size)); 424 #endif 425 } else { 426 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 427 MUSB2_VAL_FIFOSZ(fifo_size)); 428 } 429 430 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 431 offset >> 3); 432 433 offset += (1 << fifotx_size); 434 } 435 } 436 if (fiforx_size && (i <= nrx)) { 437 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 438 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 439 } 440 if (fifotx_size && (i <= ntx)) { 441 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 442 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 443 } 444 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 445 } 446 447 448 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 449 450 /* turn on default interrupts */ 451 452 if (sc->sc_mode == MOTG_MODE_HOST) { 453 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 454 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 455 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 456 } else 457 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 458 459 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 460 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 461 462 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 463 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 464 465 /* Set up the bus struct. */ 466 sc->sc_bus.ub_methods = &motg_bus_methods; 467 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 468 sc->sc_bus.ub_revision = USBREV_2_0; 469 sc->sc_bus.ub_usedma = false; 470 sc->sc_bus.ub_hcpriv = sc; 471 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 472 "Mentor Graphics"); 473 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 474 return 0; 475 } 476 477 static int 478 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 479 { 480 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 481 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 482 struct motg_hw_ep *ep; 483 int i, size; 484 485 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 486 487 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 488 sc->sc_in_ep : sc->sc_out_ep; 489 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 490 491 for (i = sc->sc_ep_max; i >= 1; i--) { 492 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 493 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 494 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 495 ep[i].ep_fifo_size, size, ep[i].refcount); 496 if (ep[i].ep_fifo_size >= size) { 497 /* found a suitable endpoint */ 498 otgpipe->hw_ep = &ep[i]; 499 mutex_enter(&sc->sc_lock); 500 if (otgpipe->hw_ep->refcount > 0) { 501 /* no luck, try next */ 502 mutex_exit(&sc->sc_lock); 503 otgpipe->hw_ep = NULL; 504 } else { 505 otgpipe->hw_ep->refcount++; 506 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 507 otgpipe, ep_pipe_list); 508 mutex_exit(&sc->sc_lock); 509 return 0; 510 } 511 } 512 } 513 return -1; 514 } 515 516 /* Open a new pipe. */ 517 usbd_status 518 motg_open(struct usbd_pipe *pipe) 519 { 520 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 521 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 522 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 523 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 524 525 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 526 527 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 528 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 529 530 if (sc->sc_dying) 531 return USBD_IOERROR; 532 533 /* toggle state needed for bulk endpoints */ 534 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 535 536 if (pipe->up_dev->ud_addr == rhaddr) { 537 switch (ed->bEndpointAddress) { 538 case USB_CONTROL_ENDPOINT: 539 pipe->up_methods = &roothub_ctrl_methods; 540 break; 541 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 542 pipe->up_methods = &motg_root_intr_methods; 543 break; 544 default: 545 return USBD_INVAL; 546 } 547 } else { 548 switch (ed->bmAttributes & UE_XFERTYPE) { 549 case UE_CONTROL: 550 pipe->up_methods = &motg_device_ctrl_methods; 551 /* always use sc_in_ep[0] for in and out */ 552 otgpipe->hw_ep = &sc->sc_in_ep[0]; 553 mutex_enter(&sc->sc_lock); 554 otgpipe->hw_ep->refcount++; 555 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 556 otgpipe, ep_pipe_list); 557 mutex_exit(&sc->sc_lock); 558 break; 559 case UE_BULK: 560 case UE_INTERRUPT: 561 DPRINTFN(MD_BULK, 562 "type %jd dir %jd pipe wMaxPacketSize %jd", 563 UE_GET_XFERTYPE(ed->bmAttributes), 564 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 565 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 566 if (motg_select_ep(sc, pipe) != 0) 567 goto bad; 568 KASSERT(otgpipe->hw_ep != NULL); 569 pipe->up_methods = &motg_device_data_methods; 570 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 571 break; 572 default: 573 goto bad; 574 #ifdef notyet 575 case UE_ISOCHRONOUS: 576 ... 577 break; 578 #endif /* notyet */ 579 } 580 } 581 return USBD_NORMAL_COMPLETION; 582 583 bad: 584 return USBD_NOMEM; 585 } 586 587 void 588 motg_softintr(void *v) 589 { 590 struct usbd_bus *bus = v; 591 struct motg_softc *sc = MOTG_BUS2SC(bus); 592 uint16_t rx_status, tx_status; 593 uint8_t ctrl_status; 594 uint32_t val; 595 int i; 596 597 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 598 599 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 600 601 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 602 603 mutex_spin_enter(&sc->sc_intr_lock); 604 rx_status = sc->sc_intr_rx_ep; 605 sc->sc_intr_rx_ep = 0; 606 tx_status = sc->sc_intr_tx_ep; 607 sc->sc_intr_tx_ep = 0; 608 ctrl_status = sc->sc_intr_ctrl; 609 sc->sc_intr_ctrl = 0; 610 mutex_spin_exit(&sc->sc_intr_lock); 611 612 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 613 614 if (ctrl_status & (MUSB2_MASK_IRESET | 615 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 616 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 617 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%jx", ctrl_status, 0, 0, 0); 618 619 if (ctrl_status & MUSB2_MASK_IRESET) { 620 sc->sc_isreset = 1; 621 sc->sc_port_suspended = 0; 622 sc->sc_port_suspended_change = 1; 623 sc->sc_connected_changed = 1; 624 sc->sc_port_enabled = 1; 625 626 val = UREAD1(sc, MUSB2_REG_POWER); 627 if (val & MUSB2_MASK_HSMODE) 628 sc->sc_high_speed = 1; 629 else 630 sc->sc_high_speed = 0; 631 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 632 0, 0, 0); 633 634 /* turn off interrupts */ 635 val = MUSB2_MASK_IRESET; 636 val &= ~MUSB2_MASK_IRESUME; 637 val |= MUSB2_MASK_ISUSP; 638 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 639 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 640 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 641 } 642 if (ctrl_status & MUSB2_MASK_IRESUME) { 643 if (sc->sc_port_suspended) { 644 sc->sc_port_suspended = 0; 645 sc->sc_port_suspended_change = 1; 646 val = UREAD1(sc, MUSB2_REG_INTUSBE); 647 /* disable resume interrupt */ 648 val &= ~MUSB2_MASK_IRESUME; 649 /* enable suspend interrupt */ 650 val |= MUSB2_MASK_ISUSP; 651 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 652 } 653 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 654 if (!sc->sc_port_suspended) { 655 sc->sc_port_suspended = 1; 656 sc->sc_port_suspended_change = 1; 657 658 val = UREAD1(sc, MUSB2_REG_INTUSBE); 659 /* disable suspend interrupt */ 660 val &= ~MUSB2_MASK_ISUSP; 661 /* enable resume interrupt */ 662 val |= MUSB2_MASK_IRESUME; 663 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 664 } 665 } 666 if (ctrl_status & MUSB2_MASK_ICONN) { 667 sc->sc_connected = 1; 668 sc->sc_connected_changed = 1; 669 sc->sc_isreset = 1; 670 sc->sc_port_enabled = 1; 671 } else if (ctrl_status & MUSB2_MASK_IDISC) { 672 sc->sc_connected = 0; 673 sc->sc_connected_changed = 1; 674 sc->sc_isreset = 0; 675 sc->sc_port_enabled = 0; 676 } 677 678 /* complete root HUB interrupt endpoint */ 679 680 motg_hub_change(sc); 681 } 682 /* 683 * read in interrupt status and mix with the status we 684 * got from the wrapper 685 */ 686 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 687 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 688 689 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 690 if (tx_status & 0x01) 691 motg_device_ctrl_intr_tx(sc); 692 for (i = 1; i <= sc->sc_ep_max; i++) { 693 if (rx_status & (0x01 << i)) 694 motg_device_intr_rx(sc, i); 695 if (tx_status & (0x01 << i)) 696 motg_device_intr_tx(sc, i); 697 } 698 return; 699 } 700 701 void 702 motg_poll(struct usbd_bus *bus) 703 { 704 struct motg_softc *sc = MOTG_BUS2SC(bus); 705 706 sc->sc_intr_poll(sc->sc_intr_poll_arg); 707 mutex_enter(&sc->sc_lock); 708 motg_softintr(bus); 709 mutex_exit(&sc->sc_lock); 710 } 711 712 int 713 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 714 uint8_t ctrl) 715 { 716 KASSERT(mutex_owned(&sc->sc_intr_lock)); 717 sc->sc_intr_tx_ep = tx_ep; 718 sc->sc_intr_rx_ep = rx_ep; 719 sc->sc_intr_ctrl = ctrl; 720 721 if (!sc->sc_bus.ub_usepolling) { 722 usb_schedsoftintr(&sc->sc_bus); 723 } 724 return 1; 725 } 726 727 int 728 motg_intr_vbus(struct motg_softc *sc, int vbus) 729 { 730 uint8_t val; 731 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 732 733 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 734 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 735 /* try to re-enter session for Host mode */ 736 val = UREAD1(sc, MUSB2_REG_DEVCTL); 737 val |= MUSB2_MASK_SESS; 738 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 739 } 740 return 1; 741 } 742 743 struct usbd_xfer * 744 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 745 { 746 struct motg_softc *sc = MOTG_BUS2SC(bus); 747 struct usbd_xfer *xfer; 748 749 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 750 if (xfer != NULL) { 751 memset(xfer, 0, sizeof(struct motg_xfer)); 752 #ifdef DIAGNOSTIC 753 xfer->ux_state = XFER_BUSY; 754 #endif 755 } 756 return xfer; 757 } 758 759 void 760 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 761 { 762 struct motg_softc *sc = MOTG_BUS2SC(bus); 763 764 #ifdef DIAGNOSTIC 765 if (xfer->ux_state != XFER_BUSY) { 766 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 767 xfer->ux_state); 768 } 769 xfer->ux_state = XFER_FREE; 770 #endif 771 pool_cache_put(sc->sc_xferpool, xfer); 772 } 773 774 static void 775 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 776 { 777 struct motg_softc *sc = MOTG_BUS2SC(bus); 778 779 *lock = &sc->sc_lock; 780 } 781 782 /* 783 * Routines to emulate the root hub. 784 */ 785 Static int 786 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 787 void *buf, int buflen) 788 { 789 struct motg_softc *sc = MOTG_BUS2SC(bus); 790 int status, change, totlen = 0; 791 uint16_t len, value, index; 792 usb_port_status_t ps; 793 usbd_status err; 794 uint32_t val; 795 796 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 797 798 if (sc->sc_dying) 799 return -1; 800 801 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 802 req->bRequest, 0, 0); 803 804 len = UGETW(req->wLength); 805 value = UGETW(req->wValue); 806 index = UGETW(req->wIndex); 807 808 #define C(x,y) ((x) | ((y) << 8)) 809 switch (C(req->bRequest, req->bmRequestType)) { 810 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 811 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 812 switch (value) { 813 case C(0, UDESC_DEVICE): { 814 usb_device_descriptor_t devd; 815 816 totlen = min(buflen, sizeof(devd)); 817 memcpy(&devd, buf, totlen); 818 USETW(devd.idVendor, sc->sc_id_vendor); 819 memcpy(buf, &devd, totlen); 820 break; 821 } 822 case C(1, UDESC_STRING): 823 #define sd ((usb_string_descriptor_t *)buf) 824 /* Vendor */ 825 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 826 break; 827 case C(2, UDESC_STRING): 828 /* Product */ 829 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 830 break; 831 #undef sd 832 default: 833 /* default from usbroothub */ 834 return buflen; 835 } 836 break; 837 /* Hub requests */ 838 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 839 break; 840 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 841 DPRINTFN(MD_ROOT, 842 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 843 0, 0); 844 if (index != 1) { 845 return -1; 846 } 847 switch (value) { 848 case UHF_PORT_ENABLE: 849 sc->sc_port_enabled = 0; 850 break; 851 case UHF_PORT_SUSPEND: 852 if (sc->sc_port_suspended != 0) { 853 val = UREAD1(sc, MUSB2_REG_POWER); 854 val &= ~MUSB2_MASK_SUSPMODE; 855 val |= MUSB2_MASK_RESUME; 856 UWRITE1(sc, MUSB2_REG_POWER, val); 857 /* wait 20 milliseconds */ 858 usb_delay_ms(&sc->sc_bus, 20); 859 val = UREAD1(sc, MUSB2_REG_POWER); 860 val &= ~MUSB2_MASK_RESUME; 861 UWRITE1(sc, MUSB2_REG_POWER, val); 862 sc->sc_port_suspended = 0; 863 sc->sc_port_suspended_change = 1; 864 } 865 break; 866 case UHF_PORT_RESET: 867 break; 868 case UHF_C_PORT_CONNECTION: 869 break; 870 case UHF_C_PORT_ENABLE: 871 break; 872 case UHF_C_PORT_OVER_CURRENT: 873 break; 874 case UHF_C_PORT_RESET: 875 sc->sc_isreset = 0; 876 break; 877 case UHF_PORT_POWER: 878 /* XXX todo */ 879 break; 880 case UHF_PORT_CONNECTION: 881 case UHF_PORT_OVER_CURRENT: 882 case UHF_PORT_LOW_SPEED: 883 case UHF_C_PORT_SUSPEND: 884 default: 885 return -1; 886 } 887 break; 888 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 889 return -1; 890 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 891 if (len == 0) 892 break; 893 if ((value & 0xff) != 0) { 894 return -1; 895 } 896 totlen = buflen; 897 break; 898 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 899 if (len != 4) { 900 return -1; 901 } 902 memset(buf, 0, len); 903 totlen = len; 904 break; 905 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 906 if (index != 1) { 907 return -1; 908 } 909 if (len != 4) { 910 return -1; 911 } 912 status = change = 0; 913 if (sc->sc_connected) 914 status |= UPS_CURRENT_CONNECT_STATUS; 915 if (sc->sc_connected_changed) { 916 change |= UPS_C_CONNECT_STATUS; 917 sc->sc_connected_changed = 0; 918 } 919 if (sc->sc_port_enabled) 920 status |= UPS_PORT_ENABLED; 921 if (sc->sc_port_enabled_changed) { 922 change |= UPS_C_PORT_ENABLED; 923 sc->sc_port_enabled_changed = 0; 924 } 925 if (sc->sc_port_suspended) 926 status |= UPS_SUSPEND; 927 if (sc->sc_high_speed) 928 status |= UPS_HIGH_SPEED; 929 status |= UPS_PORT_POWER; /* XXX */ 930 if (sc->sc_isreset) 931 change |= UPS_C_PORT_RESET; 932 USETW(ps.wPortStatus, status); 933 USETW(ps.wPortChange, change); 934 totlen = min(len, sizeof(ps)); 935 memcpy(buf, &ps, totlen); 936 break; 937 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 938 return -1; 939 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 940 break; 941 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 942 if (index != 1) { 943 return -1; 944 } 945 switch(value) { 946 case UHF_PORT_ENABLE: 947 sc->sc_port_enabled = 1; 948 break; 949 case UHF_PORT_SUSPEND: 950 if (sc->sc_port_suspended == 0) { 951 val = UREAD1(sc, MUSB2_REG_POWER); 952 val |= MUSB2_MASK_SUSPMODE; 953 UWRITE1(sc, MUSB2_REG_POWER, val); 954 /* wait 20 milliseconds */ 955 usb_delay_ms(&sc->sc_bus, 20); 956 sc->sc_port_suspended = 1; 957 sc->sc_port_suspended_change = 1; 958 } 959 break; 960 case UHF_PORT_RESET: 961 err = motg_portreset(sc); 962 if (err != USBD_NORMAL_COMPLETION) 963 return -1; 964 return 0; 965 case UHF_PORT_POWER: 966 /* XXX todo */ 967 return 0; 968 case UHF_C_PORT_CONNECTION: 969 case UHF_C_PORT_ENABLE: 970 case UHF_C_PORT_OVER_CURRENT: 971 case UHF_PORT_CONNECTION: 972 case UHF_PORT_OVER_CURRENT: 973 case UHF_PORT_LOW_SPEED: 974 case UHF_C_PORT_SUSPEND: 975 case UHF_C_PORT_RESET: 976 default: 977 return -1; 978 } 979 break; 980 default: 981 /* default from usbroothub */ 982 return buflen; 983 } 984 985 return totlen; 986 } 987 988 /* Abort a root interrupt request. */ 989 void 990 motg_root_intr_abort(struct usbd_xfer *xfer) 991 { 992 struct motg_softc *sc = MOTG_XFER2SC(xfer); 993 994 KASSERT(mutex_owned(&sc->sc_lock)); 995 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 996 997 sc->sc_intr_xfer = NULL; 998 999 xfer->ux_status = USBD_CANCELLED; 1000 usb_transfer_complete(xfer); 1001 } 1002 1003 usbd_status 1004 motg_root_intr_transfer(struct usbd_xfer *xfer) 1005 { 1006 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1007 usbd_status err; 1008 1009 /* Insert last in queue. */ 1010 mutex_enter(&sc->sc_lock); 1011 err = usb_insert_transfer(xfer); 1012 mutex_exit(&sc->sc_lock); 1013 if (err) 1014 return err; 1015 1016 /* 1017 * Pipe isn't running (otherwise err would be USBD_INPROG), 1018 * start first 1019 */ 1020 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1021 } 1022 1023 /* Start a transfer on the root interrupt pipe */ 1024 usbd_status 1025 motg_root_intr_start(struct usbd_xfer *xfer) 1026 { 1027 struct usbd_pipe *pipe = xfer->ux_pipe; 1028 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1029 1030 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1031 1032 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1033 xfer->ux_length, xfer->ux_flags, 0); 1034 1035 if (sc->sc_dying) 1036 return USBD_IOERROR; 1037 1038 sc->sc_intr_xfer = xfer; 1039 return USBD_IN_PROGRESS; 1040 } 1041 1042 /* Close the root interrupt pipe. */ 1043 void 1044 motg_root_intr_close(struct usbd_pipe *pipe) 1045 { 1046 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1047 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1048 1049 KASSERT(mutex_owned(&sc->sc_lock)); 1050 1051 sc->sc_intr_xfer = NULL; 1052 } 1053 1054 void 1055 motg_root_intr_done(struct usbd_xfer *xfer) 1056 { 1057 } 1058 1059 void 1060 motg_noop(struct usbd_pipe *pipe) 1061 { 1062 } 1063 1064 static usbd_status 1065 motg_portreset(struct motg_softc *sc) 1066 { 1067 uint32_t val; 1068 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1069 1070 val = UREAD1(sc, MUSB2_REG_POWER); 1071 val |= MUSB2_MASK_RESET; 1072 UWRITE1(sc, MUSB2_REG_POWER, val); 1073 /* Wait for 20 msec */ 1074 usb_delay_ms(&sc->sc_bus, 20); 1075 1076 val = UREAD1(sc, MUSB2_REG_POWER); 1077 val &= ~MUSB2_MASK_RESET; 1078 UWRITE1(sc, MUSB2_REG_POWER, val); 1079 1080 /* determine line speed */ 1081 val = UREAD1(sc, MUSB2_REG_POWER); 1082 if (val & MUSB2_MASK_HSMODE) 1083 sc->sc_high_speed = 1; 1084 else 1085 sc->sc_high_speed = 0; 1086 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1087 1088 sc->sc_isreset = 1; 1089 sc->sc_port_enabled = 1; 1090 return USBD_NORMAL_COMPLETION; 1091 } 1092 1093 /* 1094 * This routine is executed when an interrupt on the root hub is detected 1095 */ 1096 static void 1097 motg_hub_change(struct motg_softc *sc) 1098 { 1099 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1100 struct usbd_pipe *pipe; 1101 u_char *p; 1102 1103 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1104 1105 if (xfer == NULL) 1106 return; /* the interrupt pipe is not open */ 1107 1108 pipe = xfer->ux_pipe; 1109 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1110 return; /* device has detached */ 1111 1112 p = xfer->ux_buf; 1113 p[0] = 1<<1; 1114 xfer->ux_actlen = 1; 1115 xfer->ux_status = USBD_NORMAL_COMPLETION; 1116 usb_transfer_complete(xfer); 1117 } 1118 1119 static uint8_t 1120 motg_speed(uint8_t speed) 1121 { 1122 switch(speed) { 1123 case USB_SPEED_LOW: 1124 return MUSB2_MASK_TI_SPEED_LO; 1125 case USB_SPEED_FULL: 1126 return MUSB2_MASK_TI_SPEED_FS; 1127 case USB_SPEED_HIGH: 1128 return MUSB2_MASK_TI_SPEED_HS; 1129 default: 1130 panic("motg: unknown speed %d", speed); 1131 /* NOTREACHED */ 1132 } 1133 } 1134 1135 static uint8_t 1136 motg_type(uint8_t type) 1137 { 1138 switch(type) { 1139 case UE_CONTROL: 1140 return MUSB2_MASK_TI_PROTO_CTRL; 1141 case UE_ISOCHRONOUS: 1142 return MUSB2_MASK_TI_PROTO_ISOC; 1143 case UE_BULK: 1144 return MUSB2_MASK_TI_PROTO_BULK; 1145 case UE_INTERRUPT: 1146 return MUSB2_MASK_TI_PROTO_INTR; 1147 default: 1148 panic("motg: unknown type %d", type); 1149 /* NOTREACHED */ 1150 } 1151 } 1152 1153 static void 1154 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1155 { 1156 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1157 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1158 struct usbd_device *dev = otgpipe->pipe.up_dev; 1159 int epnumber = otgpipe->hw_ep->ep_number; 1160 1161 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1162 if (dev->ud_myhsport) { 1163 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1164 dev->ud_myhsport->up_parent->ud_addr); 1165 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1166 dev->ud_myhsport->up_portno); 1167 } else { 1168 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1169 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1170 } 1171 UWRITE1(sc, MUSB2_REG_TXTI, 1172 motg_speed(dev->ud_speed) | 1173 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1174 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1175 ); 1176 if (epnumber == 0) { 1177 if (sc->sc_high_speed) { 1178 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1179 NAK_TO_CTRL_HIGH); 1180 } else { 1181 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1182 } 1183 } else { 1184 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1185 == UE_BULK) { 1186 if (sc->sc_high_speed) { 1187 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1188 NAK_TO_BULK_HIGH); 1189 } else { 1190 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1191 } 1192 } else { 1193 if (sc->sc_high_speed) { 1194 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1195 } else { 1196 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1197 } 1198 } 1199 } 1200 } 1201 1202 static void 1203 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1204 { 1205 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1206 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1207 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1208 int epnumber = otgpipe->hw_ep->ep_number; 1209 1210 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1211 if (dev->ud_myhsport) { 1212 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1213 dev->ud_myhsport->up_parent->ud_addr); 1214 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1215 dev->ud_myhsport->up_portno); 1216 } else { 1217 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1218 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1219 } 1220 UWRITE1(sc, MUSB2_REG_RXTI, 1221 motg_speed(dev->ud_speed) | 1222 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1223 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1224 ); 1225 if (epnumber == 0) { 1226 if (sc->sc_high_speed) { 1227 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1228 NAK_TO_CTRL_HIGH); 1229 } else { 1230 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1231 } 1232 } else { 1233 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1234 == UE_BULK) { 1235 if (sc->sc_high_speed) { 1236 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1237 NAK_TO_BULK_HIGH); 1238 } else { 1239 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1240 } 1241 } else { 1242 if (sc->sc_high_speed) { 1243 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1244 } else { 1245 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1246 } 1247 } 1248 } 1249 } 1250 1251 static usbd_status 1252 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1253 { 1254 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1255 usbd_status err; 1256 1257 /* Insert last in queue. */ 1258 mutex_enter(&sc->sc_lock); 1259 err = usb_insert_transfer(xfer); 1260 xfer->ux_status = USBD_NOT_STARTED; 1261 mutex_exit(&sc->sc_lock); 1262 if (err) 1263 return err; 1264 1265 /* 1266 * Pipe isn't running (otherwise err would be USBD_INPROG), 1267 * so start it first. 1268 */ 1269 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1270 } 1271 1272 static usbd_status 1273 motg_device_ctrl_start(struct usbd_xfer *xfer) 1274 { 1275 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1276 usbd_status err; 1277 mutex_enter(&sc->sc_lock); 1278 err = motg_device_ctrl_start1(sc); 1279 mutex_exit(&sc->sc_lock); 1280 if (err != USBD_IN_PROGRESS) 1281 return err; 1282 return USBD_IN_PROGRESS; 1283 } 1284 1285 static usbd_status 1286 motg_device_ctrl_start1(struct motg_softc *sc) 1287 { 1288 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1289 struct usbd_xfer *xfer = NULL; 1290 struct motg_pipe *otgpipe; 1291 usbd_status err = 0; 1292 1293 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1294 1295 KASSERT(mutex_owned(&sc->sc_lock)); 1296 if (sc->sc_dying) 1297 return USBD_IOERROR; 1298 1299 if (!sc->sc_connected) 1300 return USBD_IOERROR; 1301 1302 if (ep->xfer != NULL) { 1303 err = USBD_IN_PROGRESS; 1304 goto end; 1305 } 1306 /* locate the first pipe with work to do */ 1307 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1308 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1309 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1310 (uintptr_t)otgpipe, (uintptr_t)xfer, 1311 (xfer != NULL) ? xfer->ux_status : 0, 0); 1312 1313 if (xfer != NULL) { 1314 /* move this pipe to the end of the list */ 1315 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1316 motg_pipe, ep_pipe_list); 1317 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1318 otgpipe, ep_pipe_list); 1319 break; 1320 } 1321 } 1322 if (xfer == NULL) { 1323 err = USBD_NOT_STARTED; 1324 goto end; 1325 } 1326 xfer->ux_status = USBD_IN_PROGRESS; 1327 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1328 KASSERT(otgpipe->hw_ep == ep); 1329 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1330 // KASSERT(xfer->ux_actlen == 0); 1331 xfer->ux_actlen = 0; 1332 1333 ep->xfer = xfer; 1334 ep->datalen = xfer->ux_length; 1335 if (ep->datalen > 0) 1336 ep->data = xfer->ux_buf; 1337 else 1338 ep->data = NULL; 1339 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1340 (ep->datalen % 64) == 0) 1341 ep->need_short_xfer = 1; 1342 else 1343 ep->need_short_xfer = 0; 1344 /* now we need send this request */ 1345 DPRINTFN(MD_CTRL, 1346 "xfer %#jx send data %#jx len %jd short %jd", 1347 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1348 ep->need_short_xfer); 1349 DPRINTFN(MD_CTRL, 1350 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1351 xfer->ux_pipe->up_dev->ud_speed, 1352 xfer->ux_pipe->up_dev->ud_addr, 0); 1353 KASSERT(ep->phase == IDLE); 1354 ep->phase = SETUP; 1355 /* select endpoint 0 */ 1356 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1357 /* fifo should be empty at this point */ 1358 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1359 /* send data */ 1360 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1361 KASSERT(sizeof(xfer->ux_request) == 8); 1362 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1363 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1364 1365 motg_setup_endpoint_tx(xfer); 1366 /* start transaction */ 1367 UWRITE1(sc, MUSB2_REG_TXCSRL, 1368 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1369 1370 end: 1371 if (err) 1372 return err; 1373 1374 return USBD_IN_PROGRESS; 1375 } 1376 1377 static void 1378 motg_device_ctrl_read(struct usbd_xfer *xfer) 1379 { 1380 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1381 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1382 /* assume endpoint already selected */ 1383 motg_setup_endpoint_rx(xfer); 1384 /* start transaction */ 1385 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1386 otgpipe->hw_ep->phase = DATA_IN; 1387 } 1388 1389 static void 1390 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1391 { 1392 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1393 struct usbd_xfer *xfer = ep->xfer; 1394 uint8_t csr; 1395 int datalen, max_datalen; 1396 char *data; 1397 bool got_short; 1398 usbd_status new_status = USBD_IN_PROGRESS; 1399 1400 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1401 1402 KASSERT(mutex_owned(&sc->sc_lock)); 1403 1404 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1405 /* select endpoint 0 */ 1406 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1407 1408 /* read out FIFO status */ 1409 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1410 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1411 ep->phase, csr, (uintptr_t)xfer, 1412 (xfer != NULL) ? xfer->ux_status : 0); 1413 1414 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1415 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1416 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1417 1418 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1419 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1420 new_status = USBD_TIMEOUT; /* XXX */ 1421 goto complete; 1422 } 1423 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1424 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1425 new_status = USBD_STALLED; 1426 else 1427 new_status = USBD_IOERROR; 1428 /* clear status */ 1429 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1430 goto complete; 1431 } 1432 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1433 return; /* no data yet */ 1434 1435 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1436 goto complete; 1437 1438 if (ep->phase == STATUS_IN) { 1439 new_status = USBD_NORMAL_COMPLETION; 1440 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1441 goto complete; 1442 } 1443 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1444 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1445 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1446 max_datalen = min(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1447 ep->datalen); 1448 if (datalen > max_datalen) { 1449 new_status = USBD_IOERROR; 1450 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1451 goto complete; 1452 } 1453 got_short = (datalen < max_datalen); 1454 if (datalen > 0) { 1455 KASSERT(ep->phase == DATA_IN); 1456 data = ep->data; 1457 ep->data += datalen; 1458 ep->datalen -= datalen; 1459 xfer->ux_actlen += datalen; 1460 if (((vaddr_t)data & 0x3) == 0 && 1461 (datalen >> 2) > 0) { 1462 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1463 (uintptr_t)data, datalen, 0, 0); 1464 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1465 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1466 data += (datalen & ~0x3); 1467 datalen -= (datalen & ~0x3); 1468 } 1469 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1470 datalen, 0, 0); 1471 if (datalen) { 1472 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1473 MUSB2_REG_EPFIFO(0), data, datalen); 1474 } 1475 } 1476 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1477 KASSERT(ep->phase == DATA_IN); 1478 if (got_short || (ep->datalen == 0)) { 1479 if (ep->need_short_xfer == 0) { 1480 ep->phase = STATUS_OUT; 1481 UWRITE1(sc, MUSB2_REG_TXCSRH, 1482 UREAD1(sc, MUSB2_REG_TXCSRH) | 1483 MUSB2_MASK_CSR0H_PING_DIS); 1484 motg_setup_endpoint_tx(xfer); 1485 UWRITE1(sc, MUSB2_REG_TXCSRL, 1486 MUSB2_MASK_CSR0L_STATUSPKT | 1487 MUSB2_MASK_CSR0L_TXPKTRDY); 1488 return; 1489 } 1490 ep->need_short_xfer = 0; 1491 } 1492 motg_device_ctrl_read(xfer); 1493 return; 1494 complete: 1495 ep->phase = IDLE; 1496 ep->xfer = NULL; 1497 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1498 KASSERT(new_status != USBD_IN_PROGRESS); 1499 xfer->ux_status = new_status; 1500 usb_transfer_complete(xfer); 1501 } 1502 motg_device_ctrl_start1(sc); 1503 } 1504 1505 static void 1506 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1507 { 1508 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1509 struct usbd_xfer *xfer = ep->xfer; 1510 uint8_t csr; 1511 int datalen; 1512 char *data; 1513 usbd_status new_status = USBD_IN_PROGRESS; 1514 1515 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1516 1517 KASSERT(mutex_owned(&sc->sc_lock)); 1518 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1519 motg_device_ctrl_intr_rx(sc); 1520 return; 1521 } 1522 1523 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1524 ep->phase == STATUS_OUT); 1525 1526 /* select endpoint 0 */ 1527 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1528 1529 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1530 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1531 ep->phase, csr, (uintptr_t)xfer, 1532 (xfer != NULL) ? xfer->ux_status : 0); 1533 1534 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1535 /* command not accepted */ 1536 new_status = USBD_STALLED; 1537 /* clear status */ 1538 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1539 goto complete; 1540 } 1541 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1542 new_status = USBD_TIMEOUT; /* XXX */ 1543 /* flush fifo */ 1544 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1545 UWRITE1(sc, MUSB2_REG_TXCSRH, 1546 UREAD1(sc, MUSB2_REG_TXCSRH) | 1547 MUSB2_MASK_CSR0H_FFLUSH); 1548 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1549 } 1550 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1551 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1552 goto complete; 1553 } 1554 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1555 new_status = USBD_IOERROR; 1556 /* clear status */ 1557 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1558 goto complete; 1559 } 1560 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1561 /* data still not sent */ 1562 return; 1563 } 1564 if (xfer == NULL) 1565 goto complete; 1566 if (ep->phase == STATUS_OUT) { 1567 /* 1568 * we have sent status and got no error; 1569 * declare transfer complete 1570 */ 1571 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1572 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1573 new_status = USBD_NORMAL_COMPLETION; 1574 goto complete; 1575 } 1576 if (ep->datalen == 0) { 1577 if (ep->need_short_xfer) { 1578 ep->need_short_xfer = 0; 1579 /* one more data phase */ 1580 if (xfer->ux_request.bmRequestType & UT_READ) { 1581 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1582 (uintptr_t)xfer, 0, 0, 0); 1583 motg_device_ctrl_read(xfer); 1584 return; 1585 } /* else fall back to DATA_OUT */ 1586 } else { 1587 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh 0x%jx", 1588 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1589 0, 0); 1590 ep->phase = STATUS_IN; 1591 UWRITE1(sc, MUSB2_REG_RXCSRH, 1592 UREAD1(sc, MUSB2_REG_RXCSRH) | 1593 MUSB2_MASK_CSR0H_PING_DIS); 1594 motg_setup_endpoint_rx(xfer); 1595 UWRITE1(sc, MUSB2_REG_TXCSRL, 1596 MUSB2_MASK_CSR0L_STATUSPKT | 1597 MUSB2_MASK_CSR0L_REQPKT); 1598 return; 1599 } 1600 } 1601 if (xfer->ux_request.bmRequestType & UT_READ) { 1602 motg_device_ctrl_read(xfer); 1603 return; 1604 } 1605 /* setup a dataout phase */ 1606 datalen = min(ep->datalen, 1607 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1608 ep->phase = DATA_OUT; 1609 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh 0x%jx", (uintptr_t)xfer, 1610 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1611 if (datalen) { 1612 data = ep->data; 1613 ep->data += datalen; 1614 ep->datalen -= datalen; 1615 xfer->ux_actlen += datalen; 1616 if (((vaddr_t)data & 0x3) == 0 && 1617 (datalen >> 2) > 0) { 1618 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1619 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1620 data += (datalen & ~0x3); 1621 datalen -= (datalen & ~0x3); 1622 } 1623 if (datalen) { 1624 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1625 MUSB2_REG_EPFIFO(0), data, datalen); 1626 } 1627 } 1628 /* send data */ 1629 motg_setup_endpoint_tx(xfer); 1630 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1631 return; 1632 1633 complete: 1634 ep->phase = IDLE; 1635 ep->xfer = NULL; 1636 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1637 KASSERT(new_status != USBD_IN_PROGRESS); 1638 xfer->ux_status = new_status; 1639 usb_transfer_complete(xfer); 1640 } 1641 motg_device_ctrl_start1(sc); 1642 } 1643 1644 /* Abort a device control request. */ 1645 void 1646 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1647 { 1648 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1649 1650 motg_device_xfer_abort(xfer); 1651 } 1652 1653 /* Close a device control pipe */ 1654 void 1655 motg_device_ctrl_close(struct usbd_pipe *pipe) 1656 { 1657 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1658 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1659 struct motg_pipe *otgpipeiter; 1660 1661 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1662 1663 KASSERT(mutex_owned(&sc->sc_lock)); 1664 KASSERT(otgpipe->hw_ep->xfer == NULL || 1665 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1666 1667 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1668 if (otgpipeiter == otgpipe) { 1669 /* remove from list */ 1670 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1671 motg_pipe, ep_pipe_list); 1672 otgpipe->hw_ep->refcount--; 1673 /* we're done */ 1674 return; 1675 } 1676 } 1677 panic("motg_device_ctrl_close: not found"); 1678 } 1679 1680 void 1681 motg_device_ctrl_done(struct usbd_xfer *xfer) 1682 { 1683 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1684 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1685 1686 KASSERT(otgpipe->hw_ep->xfer != xfer); 1687 } 1688 1689 static usbd_status 1690 motg_device_data_transfer(struct usbd_xfer *xfer) 1691 { 1692 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1693 usbd_status err; 1694 1695 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1696 1697 /* Insert last in queue. */ 1698 mutex_enter(&sc->sc_lock); 1699 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1700 err = usb_insert_transfer(xfer); 1701 xfer->ux_status = USBD_NOT_STARTED; 1702 mutex_exit(&sc->sc_lock); 1703 if (err) 1704 return err; 1705 1706 /* 1707 * Pipe isn't running (otherwise err would be USBD_INPROG), 1708 * so start it first. 1709 */ 1710 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1711 } 1712 1713 static usbd_status 1714 motg_device_data_start(struct usbd_xfer *xfer) 1715 { 1716 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1717 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1718 usbd_status err; 1719 1720 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1721 1722 mutex_enter(&sc->sc_lock); 1723 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1724 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1725 mutex_exit(&sc->sc_lock); 1726 if (err != USBD_IN_PROGRESS) 1727 return err; 1728 return USBD_IN_PROGRESS; 1729 } 1730 1731 static usbd_status 1732 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1733 { 1734 struct usbd_xfer *xfer = NULL; 1735 struct motg_pipe *otgpipe; 1736 usbd_status err = 0; 1737 uint32_t val __diagused; 1738 1739 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1740 1741 KASSERT(mutex_owned(&sc->sc_lock)); 1742 if (sc->sc_dying) 1743 return USBD_IOERROR; 1744 1745 if (!sc->sc_connected) 1746 return USBD_IOERROR; 1747 1748 if (ep->xfer != NULL) { 1749 err = USBD_IN_PROGRESS; 1750 goto end; 1751 } 1752 /* locate the first pipe with work to do */ 1753 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1754 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1755 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1756 (uintptr_t)otgpipe, (uintptr_t)xfer, 1757 (xfer != NULL) ? xfer->ux_status : 0, 0); 1758 if (xfer != NULL) { 1759 /* move this pipe to the end of the list */ 1760 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1761 motg_pipe, ep_pipe_list); 1762 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1763 otgpipe, ep_pipe_list); 1764 break; 1765 } 1766 } 1767 if (xfer == NULL) { 1768 err = USBD_NOT_STARTED; 1769 goto end; 1770 } 1771 xfer->ux_status = USBD_IN_PROGRESS; 1772 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1773 KASSERT(otgpipe->hw_ep == ep); 1774 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1775 // KASSERT(xfer->ux_actlen == 0); 1776 xfer->ux_actlen = 0; 1777 1778 ep->xfer = xfer; 1779 ep->datalen = xfer->ux_length; 1780 KASSERT(ep->datalen > 0); 1781 ep->data = xfer->ux_buf; 1782 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1783 (ep->datalen % 64) == 0) 1784 ep->need_short_xfer = 1; 1785 else 1786 ep->need_short_xfer = 0; 1787 /* now we need send this request */ 1788 DPRINTFN(MD_BULK, 1789 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1790 "xfer %#jx in data %#jx len %jd short %jd" : 1791 "xfer %#jx out data %#jx len %jd short %jd", 1792 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1793 ep->need_short_xfer); 1794 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1795 xfer->ux_pipe->up_dev->ud_speed, 1796 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1797 KASSERT(ep->phase == IDLE); 1798 /* select endpoint */ 1799 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1800 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1801 == UE_DIR_IN) { 1802 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1803 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1804 motg_device_data_read(xfer); 1805 } else { 1806 ep->phase = DATA_OUT; 1807 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1808 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1809 motg_device_data_write(xfer); 1810 } 1811 end: 1812 if (err) 1813 return err; 1814 1815 return USBD_IN_PROGRESS; 1816 } 1817 1818 static void 1819 motg_device_data_read(struct usbd_xfer *xfer) 1820 { 1821 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1822 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1823 uint32_t val; 1824 1825 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1826 1827 KASSERT(mutex_owned(&sc->sc_lock)); 1828 /* assume endpoint already selected */ 1829 motg_setup_endpoint_rx(xfer); 1830 /* Max packet size */ 1831 UWRITE2(sc, MUSB2_REG_RXMAXP, 1832 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1833 /* Data Toggle */ 1834 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1835 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1836 if (otgpipe->nexttoggle) 1837 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1838 else 1839 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1840 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1841 1842 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh 0x%jx", 1843 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1844 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1845 /* start transaction */ 1846 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1847 otgpipe->hw_ep->phase = DATA_IN; 1848 } 1849 1850 static void 1851 motg_device_data_write(struct usbd_xfer *xfer) 1852 { 1853 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1854 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1855 struct motg_hw_ep *ep = otgpipe->hw_ep; 1856 int datalen; 1857 char *data; 1858 uint32_t val; 1859 1860 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1861 1862 KASSERT(xfer!=NULL); 1863 KASSERT(mutex_owned(&sc->sc_lock)); 1864 1865 datalen = min(ep->datalen, 1866 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1867 ep->phase = DATA_OUT; 1868 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh 0x%jx", 1869 (uintptr_t)xfer, ep->ep_number, datalen, 1870 UREAD1(sc, MUSB2_REG_TXCSRH)); 1871 1872 /* assume endpoint already selected */ 1873 /* write data to fifo */ 1874 data = ep->data; 1875 ep->data += datalen; 1876 ep->datalen -= datalen; 1877 xfer->ux_actlen += datalen; 1878 if (((vaddr_t)data & 0x3) == 0 && 1879 (datalen >> 2) > 0) { 1880 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1881 MUSB2_REG_EPFIFO(ep->ep_number), 1882 (void *)data, datalen >> 2); 1883 data += (datalen & ~0x3); 1884 datalen -= (datalen & ~0x3); 1885 } 1886 if (datalen) { 1887 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1888 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1889 } 1890 1891 motg_setup_endpoint_tx(xfer); 1892 /* Max packet size */ 1893 UWRITE2(sc, MUSB2_REG_TXMAXP, 1894 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1895 /* Data Toggle */ 1896 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1897 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1898 if (otgpipe->nexttoggle) 1899 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1900 else 1901 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1902 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1903 1904 /* start transaction */ 1905 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1906 } 1907 1908 static void 1909 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1910 { 1911 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1912 struct usbd_xfer *xfer = ep->xfer; 1913 uint8_t csr; 1914 int datalen, max_datalen; 1915 char *data; 1916 bool got_short; 1917 usbd_status new_status = USBD_IN_PROGRESS; 1918 1919 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1920 1921 KASSERT(mutex_owned(&sc->sc_lock)); 1922 KASSERT(ep->ep_number == epnumber); 1923 1924 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1925 /* select endpoint */ 1926 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1927 1928 /* read out FIFO status */ 1929 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1930 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr ,0 ,0); 1931 1932 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1933 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1934 return; 1935 1936 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1937 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1938 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1939 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1940 1941 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1942 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1943 new_status = USBD_TIMEOUT; /* XXX */ 1944 goto complete; 1945 } 1946 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1947 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1948 new_status = USBD_STALLED; 1949 else 1950 new_status = USBD_IOERROR; 1951 /* clear status */ 1952 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1953 goto complete; 1954 } 1955 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1956 1957 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1958 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1959 goto complete; 1960 } 1961 1962 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1963 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1964 1965 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1966 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 1967 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1968 max_datalen = min( 1969 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1970 ep->datalen); 1971 if (datalen > max_datalen) { 1972 new_status = USBD_IOERROR; 1973 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1974 goto complete; 1975 } 1976 got_short = (datalen < max_datalen); 1977 if (datalen > 0) { 1978 KASSERT(ep->phase == DATA_IN); 1979 data = ep->data; 1980 ep->data += datalen; 1981 ep->datalen -= datalen; 1982 xfer->ux_actlen += datalen; 1983 if (((vaddr_t)data & 0x3) == 0 && 1984 (datalen >> 2) > 0) { 1985 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 1986 (uintptr_t)data, datalen, 0, 0); 1987 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1988 MUSB2_REG_EPFIFO(ep->ep_number), 1989 (void *)data, datalen >> 2); 1990 data += (datalen & ~0x3); 1991 datalen -= (datalen & ~0x3); 1992 } 1993 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 1994 datalen ,0 ,0); 1995 if (datalen) { 1996 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1997 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1998 } 1999 } 2000 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2001 KASSERT(ep->phase == DATA_IN); 2002 if (got_short || (ep->datalen == 0)) { 2003 if (ep->need_short_xfer == 0) { 2004 new_status = USBD_NORMAL_COMPLETION; 2005 goto complete; 2006 } 2007 ep->need_short_xfer = 0; 2008 } 2009 motg_device_data_read(xfer); 2010 return; 2011 complete: 2012 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2013 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2014 ep->phase = IDLE; 2015 ep->xfer = NULL; 2016 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2017 KASSERT(new_status != USBD_IN_PROGRESS); 2018 xfer->ux_status = new_status; 2019 usb_transfer_complete(xfer); 2020 } 2021 motg_device_data_start1(sc, ep); 2022 } 2023 2024 static void 2025 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2026 { 2027 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2028 struct usbd_xfer *xfer = ep->xfer; 2029 uint8_t csr; 2030 struct motg_pipe *otgpipe; 2031 usbd_status new_status = USBD_IN_PROGRESS; 2032 2033 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2034 2035 KASSERT(mutex_owned(&sc->sc_lock)); 2036 KASSERT(ep->ep_number == epnumber); 2037 2038 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2039 /* select endpoint */ 2040 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2041 2042 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2043 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr, 0, 0); 2044 2045 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2046 /* command not accepted */ 2047 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2048 new_status = USBD_STALLED; 2049 else 2050 new_status = USBD_IOERROR; 2051 /* clear status */ 2052 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2053 goto complete; 2054 } 2055 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2056 new_status = USBD_TIMEOUT; /* XXX */ 2057 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2058 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2059 /* flush fifo */ 2060 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2061 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2062 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2063 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2064 delay(1000); 2065 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2066 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR 0x%jx", 2067 epnumber, csr, 0, 0); 2068 } 2069 goto complete; 2070 } 2071 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2072 /* data still not sent */ 2073 return; 2074 } 2075 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2076 goto complete; 2077 KASSERT(ep->phase == DATA_OUT); 2078 2079 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2080 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2081 2082 if (ep->datalen == 0) { 2083 if (ep->need_short_xfer) { 2084 ep->need_short_xfer = 0; 2085 /* one more data phase */ 2086 } else { 2087 new_status = USBD_NORMAL_COMPLETION; 2088 goto complete; 2089 } 2090 } 2091 motg_device_data_write(xfer); 2092 return; 2093 2094 complete: 2095 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2096 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2097 #ifdef DIAGNOSTIC 2098 if (xfer && xfer->ux_status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2099 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2100 #endif 2101 ep->phase = IDLE; 2102 ep->xfer = NULL; 2103 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2104 KASSERT(new_status != USBD_IN_PROGRESS); 2105 xfer->ux_status = new_status; 2106 usb_transfer_complete(xfer); 2107 } 2108 motg_device_data_start1(sc, ep); 2109 } 2110 2111 /* Abort a device control request. */ 2112 void 2113 motg_device_data_abort(struct usbd_xfer *xfer) 2114 { 2115 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2116 KASSERT(mutex_owned(&sc->sc_lock)); 2117 2118 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2119 2120 motg_device_xfer_abort(xfer); 2121 } 2122 2123 /* Close a device control pipe */ 2124 void 2125 motg_device_data_close(struct usbd_pipe *pipe) 2126 { 2127 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2128 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2129 struct motg_pipe *otgpipeiter; 2130 2131 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2132 2133 KASSERT(mutex_owned(&sc->sc_lock)); 2134 KASSERT(otgpipe->hw_ep->xfer == NULL || 2135 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2136 2137 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2138 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2139 if (otgpipeiter == otgpipe) { 2140 /* remove from list */ 2141 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2142 motg_pipe, ep_pipe_list); 2143 otgpipe->hw_ep->refcount--; 2144 /* we're done */ 2145 return; 2146 } 2147 } 2148 panic("motg_device_data_close: not found"); 2149 } 2150 2151 void 2152 motg_device_data_done(struct usbd_xfer *xfer) 2153 { 2154 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2155 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2156 2157 KASSERT(otgpipe->hw_ep->xfer != xfer); 2158 } 2159 2160 void 2161 motg_device_clear_toggle(struct usbd_pipe *pipe) 2162 { 2163 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2164 otgpipe->nexttoggle = 0; 2165 } 2166 2167 /* Abort a device control request. */ 2168 static void 2169 motg_device_xfer_abort(struct usbd_xfer *xfer) 2170 { 2171 int wake; 2172 uint8_t csr; 2173 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2174 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2175 KASSERT(mutex_owned(&sc->sc_lock)); 2176 2177 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2178 2179 if (xfer->ux_hcflags & UXFER_ABORTING) { 2180 DPRINTF("already aborting", 0, 0, 0, 0); 2181 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2182 while (xfer->ux_hcflags & UXFER_ABORTING) 2183 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2184 return; 2185 } 2186 xfer->ux_hcflags |= UXFER_ABORTING; 2187 if (otgpipe->hw_ep->xfer == xfer) { 2188 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2189 otgpipe->hw_ep->xfer = NULL; 2190 if (otgpipe->hw_ep->ep_number > 0) { 2191 /* select endpoint */ 2192 UWRITE1(sc, MUSB2_REG_EPINDEX, 2193 otgpipe->hw_ep->ep_number); 2194 if (otgpipe->hw_ep->phase == DATA_OUT) { 2195 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2196 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2197 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2198 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2199 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2200 } 2201 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2202 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2203 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2204 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2205 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2206 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2207 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2208 } 2209 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2210 } 2211 otgpipe->hw_ep->phase = IDLE; 2212 } 2213 } 2214 xfer->ux_status = USBD_CANCELLED; /* make software ignore it */ 2215 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2216 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2217 usb_transfer_complete(xfer); 2218 if (wake) 2219 cv_broadcast(&xfer->ux_hccv); 2220 } 2221
Indexes created Sun Oct 19 02:09:48 GMT 2025