motg.c revision 1.24
1 /* $NetBSD: motg.c,v 1.24 2019/01/22 06:39:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.24 2019/01/22 06:39:24 skrll Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_usb.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usbhist.h> 69 70 #include <dev/usb/motgreg.h> 71 #include <dev/usb/motgvar.h> 72 #include <dev/usb/usbroothub.h> 73 74 #ifdef USB_DEBUG 75 #ifndef MOTG_DEBUG 76 #define motgdebug 0 77 #else 78 int motgdebug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 88 SYSCTL_DESCR("motg global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 107 #endif /* MOTG_DEBUG */ 108 #endif /* USB_DEBUG */ 109 110 #define MD_ROOT 0x0002 111 #define MD_CTRL 0x0004 112 #define MD_BULK 0x0008 113 114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 116 #define MOTGHIST_FUNC() USBHIST_FUNC() 117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 118 119 120 /* various timeouts, for various speeds */ 121 /* control NAK timeouts */ 122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 124 125 /* intr/iso polling intervals */ 126 #define POLL_TO 100 /* 100 frames, about 0.1s */ 127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 128 129 /* bulk NAK timeouts */ 130 #define NAK_TO_BULK 0 /* disabled */ 131 #define NAK_TO_BULK_HIGH 0 132 133 static void motg_hub_change(struct motg_softc *); 134 135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 136 static usbd_status motg_root_intr_start(struct usbd_xfer *); 137 static void motg_root_intr_abort(struct usbd_xfer *); 138 static void motg_root_intr_close(struct usbd_pipe *); 139 static void motg_root_intr_done(struct usbd_xfer *); 140 141 static usbd_status motg_open(struct usbd_pipe *); 142 static void motg_poll(struct usbd_bus *); 143 static void motg_softintr(void *); 144 static struct usbd_xfer * 145 motg_allocx(struct usbd_bus *, unsigned int); 146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 147 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 148 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 149 void *, int); 150 151 static void motg_noop(struct usbd_pipe *pipe); 152 static usbd_status motg_portreset(struct motg_softc*); 153 154 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 155 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 156 static void motg_device_ctrl_abort(struct usbd_xfer *); 157 static void motg_device_ctrl_close(struct usbd_pipe *); 158 static void motg_device_ctrl_done(struct usbd_xfer *); 159 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 160 static void motg_device_ctrl_read(struct usbd_xfer *); 161 static void motg_device_ctrl_intr_rx(struct motg_softc *); 162 static void motg_device_ctrl_intr_tx(struct motg_softc *); 163 164 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 165 static usbd_status motg_device_data_start(struct usbd_xfer *); 166 static usbd_status motg_device_data_start1(struct motg_softc *, 167 struct motg_hw_ep *); 168 static void motg_device_data_abort(struct usbd_xfer *); 169 static void motg_device_data_close(struct usbd_pipe *); 170 static void motg_device_data_done(struct usbd_xfer *); 171 static void motg_device_intr_rx(struct motg_softc *, int); 172 static void motg_device_intr_tx(struct motg_softc *, int); 173 static void motg_device_data_read(struct usbd_xfer *); 174 static void motg_device_data_write(struct usbd_xfer *); 175 176 static void motg_device_clear_toggle(struct usbd_pipe *); 177 static void motg_device_xfer_abort(struct usbd_xfer *); 178 179 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 180 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 181 #define UWRITE1(sc, r, x) \ 182 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 183 } while (/*CONSTCOND*/0) 184 #define UWRITE2(sc, r, x) \ 185 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 186 } while (/*CONSTCOND*/0) 187 #define UWRITE4(sc, r, x) \ 188 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 189 } while (/*CONSTCOND*/0) 190 191 static __inline uint32_t 192 UREAD1(struct motg_softc *sc, bus_size_t r) 193 { 194 195 UBARR(sc); 196 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 197 } 198 static __inline uint32_t 199 UREAD2(struct motg_softc *sc, bus_size_t r) 200 { 201 202 UBARR(sc); 203 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 204 } 205 206 #if 0 207 static __inline uint32_t 208 UREAD4(struct motg_softc *sc, bus_size_t r) 209 { 210 211 UBARR(sc); 212 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 213 } 214 #endif 215 216 static void 217 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 218 { 219 uint8_t val; 220 221 val = UREAD1(sc, MUSB2_REG_POWER); 222 if (on) 223 val |= MUSB2_MASK_SOFTC; 224 else 225 val &= ~MUSB2_MASK_SOFTC; 226 227 UWRITE1(sc, MUSB2_REG_POWER, val); 228 } 229 230 const struct usbd_bus_methods motg_bus_methods = { 231 .ubm_open = motg_open, 232 .ubm_softint = motg_softintr, 233 .ubm_dopoll = motg_poll, 234 .ubm_allocx = motg_allocx, 235 .ubm_freex = motg_freex, 236 .ubm_getlock = motg_get_lock, 237 .ubm_rhctrl = motg_roothub_ctrl, 238 }; 239 240 const struct usbd_pipe_methods motg_root_intr_methods = { 241 .upm_transfer = motg_root_intr_transfer, 242 .upm_start = motg_root_intr_start, 243 .upm_abort = motg_root_intr_abort, 244 .upm_close = motg_root_intr_close, 245 .upm_cleartoggle = motg_noop, 246 .upm_done = motg_root_intr_done, 247 }; 248 249 const struct usbd_pipe_methods motg_device_ctrl_methods = { 250 .upm_transfer = motg_device_ctrl_transfer, 251 .upm_start = motg_device_ctrl_start, 252 .upm_abort = motg_device_ctrl_abort, 253 .upm_close = motg_device_ctrl_close, 254 .upm_cleartoggle = motg_noop, 255 .upm_done = motg_device_ctrl_done, 256 }; 257 258 const struct usbd_pipe_methods motg_device_data_methods = { 259 .upm_transfer = motg_device_data_transfer, 260 .upm_start = motg_device_data_start, 261 .upm_abort = motg_device_data_abort, 262 .upm_close = motg_device_data_close, 263 .upm_cleartoggle = motg_device_clear_toggle, 264 .upm_done = motg_device_data_done, 265 }; 266 267 int 268 motg_init(struct motg_softc *sc) 269 { 270 uint32_t nrx, ntx, val; 271 int dynfifo; 272 int offset, i; 273 274 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 275 276 if (sc->sc_mode == MOTG_MODE_DEVICE) 277 return ENOTSUP; /* not supported */ 278 279 /* disable all interrupts */ 280 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 281 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 282 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 283 /* disable pullup */ 284 285 musbotg_pull_common(sc, 0); 286 287 #ifdef MUSB2_REG_RXDBDIS 288 /* disable double packet buffering XXX what's this ? */ 289 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 290 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 291 #endif 292 293 /* enable HighSpeed and ISO Update flags */ 294 295 UWRITE1(sc, MUSB2_REG_POWER, 296 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 297 298 if (sc->sc_mode == MOTG_MODE_DEVICE) { 299 /* clear Session bit, if set */ 300 val = UREAD1(sc, MUSB2_REG_DEVCTL); 301 val &= ~MUSB2_MASK_SESS; 302 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 303 } else { 304 /* Enter session for Host mode */ 305 val = UREAD1(sc, MUSB2_REG_DEVCTL); 306 val |= MUSB2_MASK_SESS; 307 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 308 } 309 delay(1000); 310 DPRINTF("DEVCTL 0x%jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 311 312 /* disable testmode */ 313 314 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 315 316 #ifdef MUSB2_REG_MISC 317 /* set default value */ 318 319 UWRITE1(sc, MUSB2_REG_MISC, 0); 320 #endif 321 322 /* select endpoint index 0 */ 323 324 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 325 326 if (sc->sc_ep_max == 0) { 327 /* read out number of endpoints */ 328 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 329 330 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 331 332 /* these numbers exclude the control endpoint */ 333 334 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 335 336 sc->sc_ep_max = MAX(nrx, ntx); 337 } else { 338 nrx = ntx = sc->sc_ep_max; 339 } 340 if (sc->sc_ep_max == 0) { 341 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 342 return -1; 343 } 344 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 345 /* read out configuration data */ 346 val = UREAD1(sc, MUSB2_REG_CONFDATA); 347 348 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 349 350 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 351 352 if (dynfifo) { 353 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 354 "assuming 16Kbytes of FIFO RAM\n"); 355 } 356 357 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 358 359 /* initialise endpoint profiles */ 360 sc->sc_in_ep[0].ep_fifo_size = 64; 361 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 362 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 363 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 364 offset = 64; 365 366 for (i = 1; i <= sc->sc_ep_max; i++) { 367 int fiforx_size, fifotx_size, fifo_size; 368 369 /* select endpoint */ 370 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 371 372 if (sc->sc_ep_fifosize) { 373 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 374 } else { 375 val = UREAD1(sc, MUSB2_REG_FSIZE); 376 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 377 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 378 } 379 380 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 381 i, fifotx_size, fiforx_size, dynfifo); 382 383 if (dynfifo) { 384 if (sc->sc_ep_fifosize) { 385 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 386 } else { 387 if (i < 3) { 388 fifo_size = 12; /* 4K */ 389 } else if (i < 10) { 390 fifo_size = 10; /* 1K */ 391 } else { 392 fifo_size = 7; /* 128 bytes */ 393 } 394 } 395 if (fiforx_size && (i <= nrx)) { 396 fiforx_size = fifo_size; 397 if (fifo_size > 7) { 398 #if 0 399 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 400 MUSB2_VAL_FIFOSZ(fifo_size) | 401 MUSB2_MASK_FIFODB); 402 #else 403 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 404 MUSB2_VAL_FIFOSZ(fifo_size)); 405 #endif 406 } else { 407 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 408 MUSB2_VAL_FIFOSZ(fifo_size)); 409 } 410 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 411 offset >> 3); 412 offset += (1 << fiforx_size); 413 } 414 if (fifotx_size && (i <= ntx)) { 415 fifotx_size = fifo_size; 416 if (fifo_size > 7) { 417 #if 0 418 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 419 MUSB2_VAL_FIFOSZ(fifo_size) | 420 MUSB2_MASK_FIFODB); 421 #else 422 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 423 MUSB2_VAL_FIFOSZ(fifo_size)); 424 #endif 425 } else { 426 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 427 MUSB2_VAL_FIFOSZ(fifo_size)); 428 } 429 430 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 431 offset >> 3); 432 433 offset += (1 << fifotx_size); 434 } 435 } 436 if (fiforx_size && (i <= nrx)) { 437 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 438 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 439 } 440 if (fifotx_size && (i <= ntx)) { 441 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 442 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 443 } 444 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 445 } 446 447 448 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 449 450 /* turn on default interrupts */ 451 452 if (sc->sc_mode == MOTG_MODE_HOST) { 453 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 454 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 455 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 456 } else 457 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 458 459 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 460 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 461 462 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 463 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 464 465 /* Set up the bus struct. */ 466 sc->sc_bus.ub_methods = &motg_bus_methods; 467 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 468 sc->sc_bus.ub_revision = USBREV_2_0; 469 sc->sc_bus.ub_usedma = false; 470 sc->sc_bus.ub_hcpriv = sc; 471 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 472 return 0; 473 } 474 475 static int 476 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 477 { 478 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 479 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 480 struct motg_hw_ep *ep; 481 int i, size; 482 483 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 484 485 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 486 sc->sc_in_ep : sc->sc_out_ep; 487 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 488 489 for (i = sc->sc_ep_max; i >= 1; i--) { 490 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 491 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 492 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 493 ep[i].ep_fifo_size, size, ep[i].refcount); 494 if (ep[i].ep_fifo_size >= size) { 495 /* found a suitable endpoint */ 496 otgpipe->hw_ep = &ep[i]; 497 mutex_enter(&sc->sc_lock); 498 if (otgpipe->hw_ep->refcount > 0) { 499 /* no luck, try next */ 500 mutex_exit(&sc->sc_lock); 501 otgpipe->hw_ep = NULL; 502 } else { 503 otgpipe->hw_ep->refcount++; 504 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 505 otgpipe, ep_pipe_list); 506 mutex_exit(&sc->sc_lock); 507 return 0; 508 } 509 } 510 } 511 return -1; 512 } 513 514 /* Open a new pipe. */ 515 usbd_status 516 motg_open(struct usbd_pipe *pipe) 517 { 518 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 519 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 520 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 521 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 522 523 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 524 525 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 526 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 527 528 if (sc->sc_dying) 529 return USBD_IOERROR; 530 531 /* toggle state needed for bulk endpoints */ 532 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 533 534 if (pipe->up_dev->ud_addr == rhaddr) { 535 switch (ed->bEndpointAddress) { 536 case USB_CONTROL_ENDPOINT: 537 pipe->up_methods = &roothub_ctrl_methods; 538 break; 539 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 540 pipe->up_methods = &motg_root_intr_methods; 541 break; 542 default: 543 return USBD_INVAL; 544 } 545 } else { 546 switch (ed->bmAttributes & UE_XFERTYPE) { 547 case UE_CONTROL: 548 pipe->up_methods = &motg_device_ctrl_methods; 549 /* always use sc_in_ep[0] for in and out */ 550 otgpipe->hw_ep = &sc->sc_in_ep[0]; 551 mutex_enter(&sc->sc_lock); 552 otgpipe->hw_ep->refcount++; 553 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 554 otgpipe, ep_pipe_list); 555 mutex_exit(&sc->sc_lock); 556 break; 557 case UE_BULK: 558 case UE_INTERRUPT: 559 DPRINTFN(MD_BULK, 560 "type %jd dir %jd pipe wMaxPacketSize %jd", 561 UE_GET_XFERTYPE(ed->bmAttributes), 562 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 563 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 564 if (motg_select_ep(sc, pipe) != 0) 565 goto bad; 566 KASSERT(otgpipe->hw_ep != NULL); 567 pipe->up_methods = &motg_device_data_methods; 568 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 569 break; 570 default: 571 goto bad; 572 #ifdef notyet 573 case UE_ISOCHRONOUS: 574 ... 575 break; 576 #endif /* notyet */ 577 } 578 } 579 return USBD_NORMAL_COMPLETION; 580 581 bad: 582 return USBD_NOMEM; 583 } 584 585 void 586 motg_softintr(void *v) 587 { 588 struct usbd_bus *bus = v; 589 struct motg_softc *sc = MOTG_BUS2SC(bus); 590 uint16_t rx_status, tx_status; 591 uint8_t ctrl_status; 592 uint32_t val; 593 int i; 594 595 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 596 597 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 598 599 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 600 601 mutex_spin_enter(&sc->sc_intr_lock); 602 rx_status = sc->sc_intr_rx_ep; 603 sc->sc_intr_rx_ep = 0; 604 tx_status = sc->sc_intr_tx_ep; 605 sc->sc_intr_tx_ep = 0; 606 ctrl_status = sc->sc_intr_ctrl; 607 sc->sc_intr_ctrl = 0; 608 mutex_spin_exit(&sc->sc_intr_lock); 609 610 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 611 612 if (ctrl_status & (MUSB2_MASK_IRESET | 613 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 614 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 615 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%jx", ctrl_status, 0, 0, 0); 616 617 if (ctrl_status & MUSB2_MASK_IRESET) { 618 sc->sc_isreset = 1; 619 sc->sc_port_suspended = 0; 620 sc->sc_port_suspended_change = 1; 621 sc->sc_connected_changed = 1; 622 sc->sc_port_enabled = 1; 623 624 val = UREAD1(sc, MUSB2_REG_POWER); 625 if (val & MUSB2_MASK_HSMODE) 626 sc->sc_high_speed = 1; 627 else 628 sc->sc_high_speed = 0; 629 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 630 0, 0, 0); 631 632 /* turn off interrupts */ 633 val = MUSB2_MASK_IRESET; 634 val &= ~MUSB2_MASK_IRESUME; 635 val |= MUSB2_MASK_ISUSP; 636 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 637 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 638 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 639 } 640 if (ctrl_status & MUSB2_MASK_IRESUME) { 641 if (sc->sc_port_suspended) { 642 sc->sc_port_suspended = 0; 643 sc->sc_port_suspended_change = 1; 644 val = UREAD1(sc, MUSB2_REG_INTUSBE); 645 /* disable resume interrupt */ 646 val &= ~MUSB2_MASK_IRESUME; 647 /* enable suspend interrupt */ 648 val |= MUSB2_MASK_ISUSP; 649 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 650 } 651 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 652 if (!sc->sc_port_suspended) { 653 sc->sc_port_suspended = 1; 654 sc->sc_port_suspended_change = 1; 655 656 val = UREAD1(sc, MUSB2_REG_INTUSBE); 657 /* disable suspend interrupt */ 658 val &= ~MUSB2_MASK_ISUSP; 659 /* enable resume interrupt */ 660 val |= MUSB2_MASK_IRESUME; 661 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 662 } 663 } 664 if (ctrl_status & MUSB2_MASK_ICONN) { 665 sc->sc_connected = 1; 666 sc->sc_connected_changed = 1; 667 sc->sc_isreset = 1; 668 sc->sc_port_enabled = 1; 669 } else if (ctrl_status & MUSB2_MASK_IDISC) { 670 sc->sc_connected = 0; 671 sc->sc_connected_changed = 1; 672 sc->sc_isreset = 0; 673 sc->sc_port_enabled = 0; 674 } 675 676 /* complete root HUB interrupt endpoint */ 677 678 motg_hub_change(sc); 679 } 680 /* 681 * read in interrupt status and mix with the status we 682 * got from the wrapper 683 */ 684 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 685 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 686 687 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 688 if (tx_status & 0x01) 689 motg_device_ctrl_intr_tx(sc); 690 for (i = 1; i <= sc->sc_ep_max; i++) { 691 if (rx_status & (0x01 << i)) 692 motg_device_intr_rx(sc, i); 693 if (tx_status & (0x01 << i)) 694 motg_device_intr_tx(sc, i); 695 } 696 return; 697 } 698 699 void 700 motg_poll(struct usbd_bus *bus) 701 { 702 struct motg_softc *sc = MOTG_BUS2SC(bus); 703 704 sc->sc_intr_poll(sc->sc_intr_poll_arg); 705 mutex_enter(&sc->sc_lock); 706 motg_softintr(bus); 707 mutex_exit(&sc->sc_lock); 708 } 709 710 int 711 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 712 uint8_t ctrl) 713 { 714 KASSERT(mutex_owned(&sc->sc_intr_lock)); 715 sc->sc_intr_tx_ep = tx_ep; 716 sc->sc_intr_rx_ep = rx_ep; 717 sc->sc_intr_ctrl = ctrl; 718 719 if (!sc->sc_bus.ub_usepolling) { 720 usb_schedsoftintr(&sc->sc_bus); 721 } 722 return 1; 723 } 724 725 int 726 motg_intr_vbus(struct motg_softc *sc, int vbus) 727 { 728 uint8_t val; 729 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 730 731 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 732 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 733 /* try to re-enter session for Host mode */ 734 val = UREAD1(sc, MUSB2_REG_DEVCTL); 735 val |= MUSB2_MASK_SESS; 736 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 737 } 738 return 1; 739 } 740 741 struct usbd_xfer * 742 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 743 { 744 struct motg_softc *sc = MOTG_BUS2SC(bus); 745 struct usbd_xfer *xfer; 746 747 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 748 if (xfer != NULL) { 749 memset(xfer, 0, sizeof(struct motg_xfer)); 750 #ifdef DIAGNOSTIC 751 xfer->ux_state = XFER_BUSY; 752 #endif 753 } 754 return xfer; 755 } 756 757 void 758 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 759 { 760 struct motg_softc *sc = MOTG_BUS2SC(bus); 761 762 #ifdef DIAGNOSTIC 763 if (xfer->ux_state != XFER_BUSY) { 764 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 765 xfer->ux_state); 766 } 767 xfer->ux_state = XFER_FREE; 768 #endif 769 pool_cache_put(sc->sc_xferpool, xfer); 770 } 771 772 static void 773 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 774 { 775 struct motg_softc *sc = MOTG_BUS2SC(bus); 776 777 *lock = &sc->sc_lock; 778 } 779 780 /* 781 * Routines to emulate the root hub. 782 */ 783 Static int 784 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 785 void *buf, int buflen) 786 { 787 struct motg_softc *sc = MOTG_BUS2SC(bus); 788 int status, change, totlen = 0; 789 uint16_t len, value, index; 790 usb_port_status_t ps; 791 usbd_status err; 792 uint32_t val; 793 794 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 795 796 if (sc->sc_dying) 797 return -1; 798 799 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 800 req->bRequest, 0, 0); 801 802 len = UGETW(req->wLength); 803 value = UGETW(req->wValue); 804 index = UGETW(req->wIndex); 805 806 #define C(x,y) ((x) | ((y) << 8)) 807 switch (C(req->bRequest, req->bmRequestType)) { 808 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 809 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 810 switch (value) { 811 #define sd ((usb_string_descriptor_t *)buf) 812 case C(2, UDESC_STRING): 813 /* Product */ 814 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 815 break; 816 #undef sd 817 default: 818 /* default from usbroothub */ 819 return buflen; 820 } 821 break; 822 /* Hub requests */ 823 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 824 break; 825 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 826 DPRINTFN(MD_ROOT, 827 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 828 0, 0); 829 if (index != 1) { 830 return -1; 831 } 832 switch (value) { 833 case UHF_PORT_ENABLE: 834 sc->sc_port_enabled = 0; 835 break; 836 case UHF_PORT_SUSPEND: 837 if (sc->sc_port_suspended != 0) { 838 val = UREAD1(sc, MUSB2_REG_POWER); 839 val &= ~MUSB2_MASK_SUSPMODE; 840 val |= MUSB2_MASK_RESUME; 841 UWRITE1(sc, MUSB2_REG_POWER, val); 842 /* wait 20 milliseconds */ 843 usb_delay_ms(&sc->sc_bus, 20); 844 val = UREAD1(sc, MUSB2_REG_POWER); 845 val &= ~MUSB2_MASK_RESUME; 846 UWRITE1(sc, MUSB2_REG_POWER, val); 847 sc->sc_port_suspended = 0; 848 sc->sc_port_suspended_change = 1; 849 } 850 break; 851 case UHF_PORT_RESET: 852 break; 853 case UHF_C_PORT_CONNECTION: 854 break; 855 case UHF_C_PORT_ENABLE: 856 break; 857 case UHF_C_PORT_OVER_CURRENT: 858 break; 859 case UHF_C_PORT_RESET: 860 sc->sc_isreset = 0; 861 break; 862 case UHF_PORT_POWER: 863 /* XXX todo */ 864 break; 865 case UHF_PORT_CONNECTION: 866 case UHF_PORT_OVER_CURRENT: 867 case UHF_PORT_LOW_SPEED: 868 case UHF_C_PORT_SUSPEND: 869 default: 870 return -1; 871 } 872 break; 873 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 874 return -1; 875 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 876 if (len == 0) 877 break; 878 if ((value & 0xff) != 0) { 879 return -1; 880 } 881 totlen = buflen; 882 break; 883 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 884 if (len != 4) { 885 return -1; 886 } 887 memset(buf, 0, len); 888 totlen = len; 889 break; 890 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 891 if (index != 1) { 892 return -1; 893 } 894 if (len != 4) { 895 return -1; 896 } 897 status = change = 0; 898 if (sc->sc_connected) 899 status |= UPS_CURRENT_CONNECT_STATUS; 900 if (sc->sc_connected_changed) { 901 change |= UPS_C_CONNECT_STATUS; 902 sc->sc_connected_changed = 0; 903 } 904 if (sc->sc_port_enabled) 905 status |= UPS_PORT_ENABLED; 906 if (sc->sc_port_enabled_changed) { 907 change |= UPS_C_PORT_ENABLED; 908 sc->sc_port_enabled_changed = 0; 909 } 910 if (sc->sc_port_suspended) 911 status |= UPS_SUSPEND; 912 if (sc->sc_high_speed) 913 status |= UPS_HIGH_SPEED; 914 status |= UPS_PORT_POWER; /* XXX */ 915 if (sc->sc_isreset) 916 change |= UPS_C_PORT_RESET; 917 USETW(ps.wPortStatus, status); 918 USETW(ps.wPortChange, change); 919 totlen = uimin(len, sizeof(ps)); 920 memcpy(buf, &ps, totlen); 921 break; 922 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 923 return -1; 924 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 925 break; 926 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 927 if (index != 1) { 928 return -1; 929 } 930 switch(value) { 931 case UHF_PORT_ENABLE: 932 sc->sc_port_enabled = 1; 933 break; 934 case UHF_PORT_SUSPEND: 935 if (sc->sc_port_suspended == 0) { 936 val = UREAD1(sc, MUSB2_REG_POWER); 937 val |= MUSB2_MASK_SUSPMODE; 938 UWRITE1(sc, MUSB2_REG_POWER, val); 939 /* wait 20 milliseconds */ 940 usb_delay_ms(&sc->sc_bus, 20); 941 sc->sc_port_suspended = 1; 942 sc->sc_port_suspended_change = 1; 943 } 944 break; 945 case UHF_PORT_RESET: 946 err = motg_portreset(sc); 947 if (err != USBD_NORMAL_COMPLETION) 948 return -1; 949 return 0; 950 case UHF_PORT_POWER: 951 /* XXX todo */ 952 return 0; 953 case UHF_C_PORT_CONNECTION: 954 case UHF_C_PORT_ENABLE: 955 case UHF_C_PORT_OVER_CURRENT: 956 case UHF_PORT_CONNECTION: 957 case UHF_PORT_OVER_CURRENT: 958 case UHF_PORT_LOW_SPEED: 959 case UHF_C_PORT_SUSPEND: 960 case UHF_C_PORT_RESET: 961 default: 962 return -1; 963 } 964 break; 965 default: 966 /* default from usbroothub */ 967 return buflen; 968 } 969 970 return totlen; 971 } 972 973 /* Abort a root interrupt request. */ 974 void 975 motg_root_intr_abort(struct usbd_xfer *xfer) 976 { 977 struct motg_softc *sc = MOTG_XFER2SC(xfer); 978 979 KASSERT(mutex_owned(&sc->sc_lock)); 980 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 981 982 sc->sc_intr_xfer = NULL; 983 984 xfer->ux_status = USBD_CANCELLED; 985 usb_transfer_complete(xfer); 986 } 987 988 usbd_status 989 motg_root_intr_transfer(struct usbd_xfer *xfer) 990 { 991 struct motg_softc *sc = MOTG_XFER2SC(xfer); 992 usbd_status err; 993 994 /* Insert last in queue. */ 995 mutex_enter(&sc->sc_lock); 996 err = usb_insert_transfer(xfer); 997 mutex_exit(&sc->sc_lock); 998 if (err) 999 return err; 1000 1001 /* 1002 * Pipe isn't running (otherwise err would be USBD_INPROG), 1003 * start first 1004 */ 1005 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1006 } 1007 1008 /* Start a transfer on the root interrupt pipe */ 1009 usbd_status 1010 motg_root_intr_start(struct usbd_xfer *xfer) 1011 { 1012 struct usbd_pipe *pipe = xfer->ux_pipe; 1013 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1014 1015 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1016 1017 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1018 xfer->ux_length, xfer->ux_flags, 0); 1019 1020 if (sc->sc_dying) 1021 return USBD_IOERROR; 1022 1023 sc->sc_intr_xfer = xfer; 1024 return USBD_IN_PROGRESS; 1025 } 1026 1027 /* Close the root interrupt pipe. */ 1028 void 1029 motg_root_intr_close(struct usbd_pipe *pipe) 1030 { 1031 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1032 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1033 1034 KASSERT(mutex_owned(&sc->sc_lock)); 1035 1036 sc->sc_intr_xfer = NULL; 1037 } 1038 1039 void 1040 motg_root_intr_done(struct usbd_xfer *xfer) 1041 { 1042 } 1043 1044 void 1045 motg_noop(struct usbd_pipe *pipe) 1046 { 1047 } 1048 1049 static usbd_status 1050 motg_portreset(struct motg_softc *sc) 1051 { 1052 uint32_t val; 1053 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1054 1055 val = UREAD1(sc, MUSB2_REG_POWER); 1056 val |= MUSB2_MASK_RESET; 1057 UWRITE1(sc, MUSB2_REG_POWER, val); 1058 /* Wait for 20 msec */ 1059 usb_delay_ms(&sc->sc_bus, 20); 1060 1061 val = UREAD1(sc, MUSB2_REG_POWER); 1062 val &= ~MUSB2_MASK_RESET; 1063 UWRITE1(sc, MUSB2_REG_POWER, val); 1064 1065 /* determine line speed */ 1066 val = UREAD1(sc, MUSB2_REG_POWER); 1067 if (val & MUSB2_MASK_HSMODE) 1068 sc->sc_high_speed = 1; 1069 else 1070 sc->sc_high_speed = 0; 1071 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1072 1073 sc->sc_isreset = 1; 1074 sc->sc_port_enabled = 1; 1075 return USBD_NORMAL_COMPLETION; 1076 } 1077 1078 /* 1079 * This routine is executed when an interrupt on the root hub is detected 1080 */ 1081 static void 1082 motg_hub_change(struct motg_softc *sc) 1083 { 1084 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1085 struct usbd_pipe *pipe; 1086 u_char *p; 1087 1088 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1089 1090 if (xfer == NULL) 1091 return; /* the interrupt pipe is not open */ 1092 1093 pipe = xfer->ux_pipe; 1094 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1095 return; /* device has detached */ 1096 1097 p = xfer->ux_buf; 1098 p[0] = 1<<1; 1099 xfer->ux_actlen = 1; 1100 xfer->ux_status = USBD_NORMAL_COMPLETION; 1101 usb_transfer_complete(xfer); 1102 } 1103 1104 static uint8_t 1105 motg_speed(uint8_t speed) 1106 { 1107 switch(speed) { 1108 case USB_SPEED_LOW: 1109 return MUSB2_MASK_TI_SPEED_LO; 1110 case USB_SPEED_FULL: 1111 return MUSB2_MASK_TI_SPEED_FS; 1112 case USB_SPEED_HIGH: 1113 return MUSB2_MASK_TI_SPEED_HS; 1114 default: 1115 panic("motg: unknown speed %d", speed); 1116 /* NOTREACHED */ 1117 } 1118 } 1119 1120 static uint8_t 1121 motg_type(uint8_t type) 1122 { 1123 switch(type) { 1124 case UE_CONTROL: 1125 return MUSB2_MASK_TI_PROTO_CTRL; 1126 case UE_ISOCHRONOUS: 1127 return MUSB2_MASK_TI_PROTO_ISOC; 1128 case UE_BULK: 1129 return MUSB2_MASK_TI_PROTO_BULK; 1130 case UE_INTERRUPT: 1131 return MUSB2_MASK_TI_PROTO_INTR; 1132 default: 1133 panic("motg: unknown type %d", type); 1134 /* NOTREACHED */ 1135 } 1136 } 1137 1138 static void 1139 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1140 { 1141 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1142 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1143 struct usbd_device *dev = otgpipe->pipe.up_dev; 1144 int epnumber = otgpipe->hw_ep->ep_number; 1145 1146 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1147 if (dev->ud_myhsport) { 1148 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1149 dev->ud_myhsport->up_parent->ud_addr); 1150 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1151 dev->ud_myhsport->up_portno); 1152 } else { 1153 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1154 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1155 } 1156 UWRITE1(sc, MUSB2_REG_TXTI, 1157 motg_speed(dev->ud_speed) | 1158 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1159 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1160 ); 1161 if (epnumber == 0) { 1162 if (sc->sc_high_speed) { 1163 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1164 NAK_TO_CTRL_HIGH); 1165 } else { 1166 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1167 } 1168 } else { 1169 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1170 == UE_BULK) { 1171 if (sc->sc_high_speed) { 1172 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1173 NAK_TO_BULK_HIGH); 1174 } else { 1175 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1176 } 1177 } else { 1178 if (sc->sc_high_speed) { 1179 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1180 } else { 1181 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1182 } 1183 } 1184 } 1185 } 1186 1187 static void 1188 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1189 { 1190 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1191 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1192 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1193 int epnumber = otgpipe->hw_ep->ep_number; 1194 1195 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1196 if (dev->ud_myhsport) { 1197 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1198 dev->ud_myhsport->up_parent->ud_addr); 1199 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1200 dev->ud_myhsport->up_portno); 1201 } else { 1202 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1203 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1204 } 1205 UWRITE1(sc, MUSB2_REG_RXTI, 1206 motg_speed(dev->ud_speed) | 1207 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1208 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1209 ); 1210 if (epnumber == 0) { 1211 if (sc->sc_high_speed) { 1212 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1213 NAK_TO_CTRL_HIGH); 1214 } else { 1215 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1216 } 1217 } else { 1218 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1219 == UE_BULK) { 1220 if (sc->sc_high_speed) { 1221 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1222 NAK_TO_BULK_HIGH); 1223 } else { 1224 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1225 } 1226 } else { 1227 if (sc->sc_high_speed) { 1228 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1229 } else { 1230 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1231 } 1232 } 1233 } 1234 } 1235 1236 static usbd_status 1237 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1238 { 1239 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1240 usbd_status err; 1241 1242 /* Insert last in queue. */ 1243 mutex_enter(&sc->sc_lock); 1244 err = usb_insert_transfer(xfer); 1245 xfer->ux_status = USBD_NOT_STARTED; 1246 mutex_exit(&sc->sc_lock); 1247 if (err) 1248 return err; 1249 1250 /* 1251 * Pipe isn't running (otherwise err would be USBD_INPROG), 1252 * so start it first. 1253 */ 1254 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1255 } 1256 1257 static usbd_status 1258 motg_device_ctrl_start(struct usbd_xfer *xfer) 1259 { 1260 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1261 usbd_status err; 1262 mutex_enter(&sc->sc_lock); 1263 err = motg_device_ctrl_start1(sc); 1264 mutex_exit(&sc->sc_lock); 1265 if (err != USBD_IN_PROGRESS) 1266 return err; 1267 return USBD_IN_PROGRESS; 1268 } 1269 1270 static usbd_status 1271 motg_device_ctrl_start1(struct motg_softc *sc) 1272 { 1273 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1274 struct usbd_xfer *xfer = NULL; 1275 struct motg_pipe *otgpipe; 1276 usbd_status err = 0; 1277 1278 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1279 1280 KASSERT(mutex_owned(&sc->sc_lock)); 1281 if (sc->sc_dying) 1282 return USBD_IOERROR; 1283 1284 if (!sc->sc_connected) 1285 return USBD_IOERROR; 1286 1287 if (ep->xfer != NULL) { 1288 err = USBD_IN_PROGRESS; 1289 goto end; 1290 } 1291 /* locate the first pipe with work to do */ 1292 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1293 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1294 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1295 (uintptr_t)otgpipe, (uintptr_t)xfer, 1296 (xfer != NULL) ? xfer->ux_status : 0, 0); 1297 1298 if (xfer != NULL) { 1299 /* move this pipe to the end of the list */ 1300 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1301 motg_pipe, ep_pipe_list); 1302 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1303 otgpipe, ep_pipe_list); 1304 break; 1305 } 1306 } 1307 if (xfer == NULL) { 1308 err = USBD_NOT_STARTED; 1309 goto end; 1310 } 1311 xfer->ux_status = USBD_IN_PROGRESS; 1312 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1313 KASSERT(otgpipe->hw_ep == ep); 1314 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1315 // KASSERT(xfer->ux_actlen == 0); 1316 xfer->ux_actlen = 0; 1317 1318 ep->xfer = xfer; 1319 ep->datalen = xfer->ux_length; 1320 if (ep->datalen > 0) 1321 ep->data = xfer->ux_buf; 1322 else 1323 ep->data = NULL; 1324 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1325 (ep->datalen % 64) == 0) 1326 ep->need_short_xfer = 1; 1327 else 1328 ep->need_short_xfer = 0; 1329 /* now we need send this request */ 1330 DPRINTFN(MD_CTRL, 1331 "xfer %#jx send data %#jx len %jd short %jd", 1332 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1333 ep->need_short_xfer); 1334 DPRINTFN(MD_CTRL, 1335 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1336 xfer->ux_pipe->up_dev->ud_speed, 1337 xfer->ux_pipe->up_dev->ud_addr, 0); 1338 KASSERT(ep->phase == IDLE); 1339 ep->phase = SETUP; 1340 /* select endpoint 0 */ 1341 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1342 /* fifo should be empty at this point */ 1343 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1344 /* send data */ 1345 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1346 KASSERT(sizeof(xfer->ux_request) == 8); 1347 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1348 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1349 1350 motg_setup_endpoint_tx(xfer); 1351 /* start transaction */ 1352 UWRITE1(sc, MUSB2_REG_TXCSRL, 1353 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1354 1355 end: 1356 if (err) 1357 return err; 1358 1359 return USBD_IN_PROGRESS; 1360 } 1361 1362 static void 1363 motg_device_ctrl_read(struct usbd_xfer *xfer) 1364 { 1365 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1366 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1367 /* assume endpoint already selected */ 1368 motg_setup_endpoint_rx(xfer); 1369 /* start transaction */ 1370 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1371 otgpipe->hw_ep->phase = DATA_IN; 1372 } 1373 1374 static void 1375 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1376 { 1377 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1378 struct usbd_xfer *xfer = ep->xfer; 1379 uint8_t csr; 1380 int datalen, max_datalen; 1381 char *data; 1382 bool got_short; 1383 usbd_status new_status = USBD_IN_PROGRESS; 1384 1385 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1386 1387 KASSERT(mutex_owned(&sc->sc_lock)); 1388 1389 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1390 /* select endpoint 0 */ 1391 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1392 1393 /* read out FIFO status */ 1394 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1395 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1396 ep->phase, csr, (uintptr_t)xfer, 1397 (xfer != NULL) ? xfer->ux_status : 0); 1398 1399 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1400 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1401 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1402 1403 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1404 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1405 new_status = USBD_TIMEOUT; /* XXX */ 1406 goto complete; 1407 } 1408 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1409 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1410 new_status = USBD_STALLED; 1411 else 1412 new_status = USBD_IOERROR; 1413 /* clear status */ 1414 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1415 goto complete; 1416 } 1417 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1418 return; /* no data yet */ 1419 1420 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1421 goto complete; 1422 1423 if (ep->phase == STATUS_IN) { 1424 new_status = USBD_NORMAL_COMPLETION; 1425 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1426 goto complete; 1427 } 1428 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1429 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1430 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1431 max_datalen = uimin(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1432 ep->datalen); 1433 if (datalen > max_datalen) { 1434 new_status = USBD_IOERROR; 1435 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1436 goto complete; 1437 } 1438 got_short = (datalen < max_datalen); 1439 if (datalen > 0) { 1440 KASSERT(ep->phase == DATA_IN); 1441 data = ep->data; 1442 ep->data += datalen; 1443 ep->datalen -= datalen; 1444 xfer->ux_actlen += datalen; 1445 if (((vaddr_t)data & 0x3) == 0 && 1446 (datalen >> 2) > 0) { 1447 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1448 (uintptr_t)data, datalen, 0, 0); 1449 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1450 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1451 data += (datalen & ~0x3); 1452 datalen -= (datalen & ~0x3); 1453 } 1454 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1455 datalen, 0, 0); 1456 if (datalen) { 1457 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1458 MUSB2_REG_EPFIFO(0), data, datalen); 1459 } 1460 } 1461 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1462 KASSERT(ep->phase == DATA_IN); 1463 if (got_short || (ep->datalen == 0)) { 1464 if (ep->need_short_xfer == 0) { 1465 ep->phase = STATUS_OUT; 1466 UWRITE1(sc, MUSB2_REG_TXCSRH, 1467 UREAD1(sc, MUSB2_REG_TXCSRH) | 1468 MUSB2_MASK_CSR0H_PING_DIS); 1469 motg_setup_endpoint_tx(xfer); 1470 UWRITE1(sc, MUSB2_REG_TXCSRL, 1471 MUSB2_MASK_CSR0L_STATUSPKT | 1472 MUSB2_MASK_CSR0L_TXPKTRDY); 1473 return; 1474 } 1475 ep->need_short_xfer = 0; 1476 } 1477 motg_device_ctrl_read(xfer); 1478 return; 1479 complete: 1480 ep->phase = IDLE; 1481 ep->xfer = NULL; 1482 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1483 KASSERT(new_status != USBD_IN_PROGRESS); 1484 xfer->ux_status = new_status; 1485 usb_transfer_complete(xfer); 1486 } 1487 motg_device_ctrl_start1(sc); 1488 } 1489 1490 static void 1491 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1492 { 1493 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1494 struct usbd_xfer *xfer = ep->xfer; 1495 uint8_t csr; 1496 int datalen; 1497 char *data; 1498 usbd_status new_status = USBD_IN_PROGRESS; 1499 1500 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1501 1502 KASSERT(mutex_owned(&sc->sc_lock)); 1503 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1504 motg_device_ctrl_intr_rx(sc); 1505 return; 1506 } 1507 1508 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1509 ep->phase == STATUS_OUT); 1510 1511 /* select endpoint 0 */ 1512 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1513 1514 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1515 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1516 ep->phase, csr, (uintptr_t)xfer, 1517 (xfer != NULL) ? xfer->ux_status : 0); 1518 1519 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1520 /* command not accepted */ 1521 new_status = USBD_STALLED; 1522 /* clear status */ 1523 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1524 goto complete; 1525 } 1526 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1527 new_status = USBD_TIMEOUT; /* XXX */ 1528 /* flush fifo */ 1529 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1530 UWRITE1(sc, MUSB2_REG_TXCSRH, 1531 UREAD1(sc, MUSB2_REG_TXCSRH) | 1532 MUSB2_MASK_CSR0H_FFLUSH); 1533 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1534 } 1535 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1536 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1537 goto complete; 1538 } 1539 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1540 new_status = USBD_IOERROR; 1541 /* clear status */ 1542 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1543 goto complete; 1544 } 1545 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1546 /* data still not sent */ 1547 return; 1548 } 1549 if (xfer == NULL) 1550 goto complete; 1551 if (ep->phase == STATUS_OUT) { 1552 /* 1553 * we have sent status and got no error; 1554 * declare transfer complete 1555 */ 1556 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1557 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1558 new_status = USBD_NORMAL_COMPLETION; 1559 goto complete; 1560 } 1561 if (ep->datalen == 0) { 1562 if (ep->need_short_xfer) { 1563 ep->need_short_xfer = 0; 1564 /* one more data phase */ 1565 if (xfer->ux_request.bmRequestType & UT_READ) { 1566 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1567 (uintptr_t)xfer, 0, 0, 0); 1568 motg_device_ctrl_read(xfer); 1569 return; 1570 } /* else fall back to DATA_OUT */ 1571 } else { 1572 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh 0x%jx", 1573 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1574 0, 0); 1575 ep->phase = STATUS_IN; 1576 UWRITE1(sc, MUSB2_REG_RXCSRH, 1577 UREAD1(sc, MUSB2_REG_RXCSRH) | 1578 MUSB2_MASK_CSR0H_PING_DIS); 1579 motg_setup_endpoint_rx(xfer); 1580 UWRITE1(sc, MUSB2_REG_TXCSRL, 1581 MUSB2_MASK_CSR0L_STATUSPKT | 1582 MUSB2_MASK_CSR0L_REQPKT); 1583 return; 1584 } 1585 } 1586 if (xfer->ux_request.bmRequestType & UT_READ) { 1587 motg_device_ctrl_read(xfer); 1588 return; 1589 } 1590 /* setup a dataout phase */ 1591 datalen = uimin(ep->datalen, 1592 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1593 ep->phase = DATA_OUT; 1594 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh 0x%jx", (uintptr_t)xfer, 1595 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1596 if (datalen) { 1597 data = ep->data; 1598 ep->data += datalen; 1599 ep->datalen -= datalen; 1600 xfer->ux_actlen += datalen; 1601 if (((vaddr_t)data & 0x3) == 0 && 1602 (datalen >> 2) > 0) { 1603 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1604 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1605 data += (datalen & ~0x3); 1606 datalen -= (datalen & ~0x3); 1607 } 1608 if (datalen) { 1609 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1610 MUSB2_REG_EPFIFO(0), data, datalen); 1611 } 1612 } 1613 /* send data */ 1614 motg_setup_endpoint_tx(xfer); 1615 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1616 return; 1617 1618 complete: 1619 ep->phase = IDLE; 1620 ep->xfer = NULL; 1621 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1622 KASSERT(new_status != USBD_IN_PROGRESS); 1623 xfer->ux_status = new_status; 1624 usb_transfer_complete(xfer); 1625 } 1626 motg_device_ctrl_start1(sc); 1627 } 1628 1629 /* Abort a device control request. */ 1630 void 1631 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1632 { 1633 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1634 1635 motg_device_xfer_abort(xfer); 1636 } 1637 1638 /* Close a device control pipe */ 1639 void 1640 motg_device_ctrl_close(struct usbd_pipe *pipe) 1641 { 1642 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1643 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1644 struct motg_pipe *otgpipeiter; 1645 1646 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1647 1648 KASSERT(mutex_owned(&sc->sc_lock)); 1649 KASSERT(otgpipe->hw_ep->xfer == NULL || 1650 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1651 1652 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1653 if (otgpipeiter == otgpipe) { 1654 /* remove from list */ 1655 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1656 motg_pipe, ep_pipe_list); 1657 otgpipe->hw_ep->refcount--; 1658 /* we're done */ 1659 return; 1660 } 1661 } 1662 panic("motg_device_ctrl_close: not found"); 1663 } 1664 1665 void 1666 motg_device_ctrl_done(struct usbd_xfer *xfer) 1667 { 1668 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1669 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1670 1671 KASSERT(otgpipe->hw_ep->xfer != xfer); 1672 } 1673 1674 static usbd_status 1675 motg_device_data_transfer(struct usbd_xfer *xfer) 1676 { 1677 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1678 usbd_status err; 1679 1680 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1681 1682 /* Insert last in queue. */ 1683 mutex_enter(&sc->sc_lock); 1684 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1685 err = usb_insert_transfer(xfer); 1686 xfer->ux_status = USBD_NOT_STARTED; 1687 mutex_exit(&sc->sc_lock); 1688 if (err) 1689 return err; 1690 1691 /* 1692 * Pipe isn't running (otherwise err would be USBD_INPROG), 1693 * so start it first. 1694 */ 1695 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1696 } 1697 1698 static usbd_status 1699 motg_device_data_start(struct usbd_xfer *xfer) 1700 { 1701 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1702 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1703 usbd_status err; 1704 1705 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1706 1707 mutex_enter(&sc->sc_lock); 1708 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1709 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1710 mutex_exit(&sc->sc_lock); 1711 if (err != USBD_IN_PROGRESS) 1712 return err; 1713 return USBD_IN_PROGRESS; 1714 } 1715 1716 static usbd_status 1717 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1718 { 1719 struct usbd_xfer *xfer = NULL; 1720 struct motg_pipe *otgpipe; 1721 usbd_status err = 0; 1722 uint32_t val __diagused; 1723 1724 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1725 1726 KASSERT(mutex_owned(&sc->sc_lock)); 1727 if (sc->sc_dying) 1728 return USBD_IOERROR; 1729 1730 if (!sc->sc_connected) 1731 return USBD_IOERROR; 1732 1733 if (ep->xfer != NULL) { 1734 err = USBD_IN_PROGRESS; 1735 goto end; 1736 } 1737 /* locate the first pipe with work to do */ 1738 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1739 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1740 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1741 (uintptr_t)otgpipe, (uintptr_t)xfer, 1742 (xfer != NULL) ? xfer->ux_status : 0, 0); 1743 if (xfer != NULL) { 1744 /* move this pipe to the end of the list */ 1745 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1746 motg_pipe, ep_pipe_list); 1747 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1748 otgpipe, ep_pipe_list); 1749 break; 1750 } 1751 } 1752 if (xfer == NULL) { 1753 err = USBD_NOT_STARTED; 1754 goto end; 1755 } 1756 xfer->ux_status = USBD_IN_PROGRESS; 1757 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1758 KASSERT(otgpipe->hw_ep == ep); 1759 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1760 // KASSERT(xfer->ux_actlen == 0); 1761 xfer->ux_actlen = 0; 1762 1763 ep->xfer = xfer; 1764 ep->datalen = xfer->ux_length; 1765 KASSERT(ep->datalen > 0); 1766 ep->data = xfer->ux_buf; 1767 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1768 (ep->datalen % 64) == 0) 1769 ep->need_short_xfer = 1; 1770 else 1771 ep->need_short_xfer = 0; 1772 /* now we need send this request */ 1773 DPRINTFN(MD_BULK, 1774 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1775 "xfer %#jx in data %#jx len %jd short %jd" : 1776 "xfer %#jx out data %#jx len %jd short %jd", 1777 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1778 ep->need_short_xfer); 1779 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1780 xfer->ux_pipe->up_dev->ud_speed, 1781 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1782 KASSERT(ep->phase == IDLE); 1783 /* select endpoint */ 1784 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1785 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1786 == UE_DIR_IN) { 1787 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1788 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1789 motg_device_data_read(xfer); 1790 } else { 1791 ep->phase = DATA_OUT; 1792 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1793 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1794 motg_device_data_write(xfer); 1795 } 1796 end: 1797 if (err) 1798 return err; 1799 1800 return USBD_IN_PROGRESS; 1801 } 1802 1803 static void 1804 motg_device_data_read(struct usbd_xfer *xfer) 1805 { 1806 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1807 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1808 uint32_t val; 1809 1810 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1811 1812 KASSERT(mutex_owned(&sc->sc_lock)); 1813 /* assume endpoint already selected */ 1814 motg_setup_endpoint_rx(xfer); 1815 /* Max packet size */ 1816 UWRITE2(sc, MUSB2_REG_RXMAXP, 1817 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1818 /* Data Toggle */ 1819 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1820 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1821 if (otgpipe->nexttoggle) 1822 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1823 else 1824 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1825 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1826 1827 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh 0x%jx", 1828 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1829 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1830 /* start transaction */ 1831 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1832 otgpipe->hw_ep->phase = DATA_IN; 1833 } 1834 1835 static void 1836 motg_device_data_write(struct usbd_xfer *xfer) 1837 { 1838 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1839 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1840 struct motg_hw_ep *ep = otgpipe->hw_ep; 1841 int datalen; 1842 char *data; 1843 uint32_t val; 1844 1845 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1846 1847 KASSERT(xfer!=NULL); 1848 KASSERT(mutex_owned(&sc->sc_lock)); 1849 1850 datalen = uimin(ep->datalen, 1851 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1852 ep->phase = DATA_OUT; 1853 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh 0x%jx", 1854 (uintptr_t)xfer, ep->ep_number, datalen, 1855 UREAD1(sc, MUSB2_REG_TXCSRH)); 1856 1857 /* assume endpoint already selected */ 1858 /* write data to fifo */ 1859 data = ep->data; 1860 ep->data += datalen; 1861 ep->datalen -= datalen; 1862 xfer->ux_actlen += datalen; 1863 if (((vaddr_t)data & 0x3) == 0 && 1864 (datalen >> 2) > 0) { 1865 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1866 MUSB2_REG_EPFIFO(ep->ep_number), 1867 (void *)data, datalen >> 2); 1868 data += (datalen & ~0x3); 1869 datalen -= (datalen & ~0x3); 1870 } 1871 if (datalen) { 1872 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1873 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1874 } 1875 1876 motg_setup_endpoint_tx(xfer); 1877 /* Max packet size */ 1878 UWRITE2(sc, MUSB2_REG_TXMAXP, 1879 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1880 /* Data Toggle */ 1881 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1882 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1883 if (otgpipe->nexttoggle) 1884 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1885 else 1886 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1887 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1888 1889 /* start transaction */ 1890 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1891 } 1892 1893 static void 1894 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1895 { 1896 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1897 struct usbd_xfer *xfer = ep->xfer; 1898 uint8_t csr; 1899 int datalen, max_datalen; 1900 char *data; 1901 bool got_short; 1902 usbd_status new_status = USBD_IN_PROGRESS; 1903 1904 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1905 1906 KASSERT(mutex_owned(&sc->sc_lock)); 1907 KASSERT(ep->ep_number == epnumber); 1908 1909 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1910 /* select endpoint */ 1911 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1912 1913 /* read out FIFO status */ 1914 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1915 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr ,0 ,0); 1916 1917 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1918 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1919 return; 1920 1921 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1922 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1923 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1924 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1925 1926 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1927 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1928 new_status = USBD_TIMEOUT; /* XXX */ 1929 goto complete; 1930 } 1931 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1932 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1933 new_status = USBD_STALLED; 1934 else 1935 new_status = USBD_IOERROR; 1936 /* clear status */ 1937 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1938 goto complete; 1939 } 1940 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1941 1942 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1943 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1944 goto complete; 1945 } 1946 1947 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1948 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1949 1950 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1951 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 1952 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1953 max_datalen = uimin( 1954 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1955 ep->datalen); 1956 if (datalen > max_datalen) { 1957 new_status = USBD_IOERROR; 1958 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1959 goto complete; 1960 } 1961 got_short = (datalen < max_datalen); 1962 if (datalen > 0) { 1963 KASSERT(ep->phase == DATA_IN); 1964 data = ep->data; 1965 ep->data += datalen; 1966 ep->datalen -= datalen; 1967 xfer->ux_actlen += datalen; 1968 if (((vaddr_t)data & 0x3) == 0 && 1969 (datalen >> 2) > 0) { 1970 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 1971 (uintptr_t)data, datalen, 0, 0); 1972 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1973 MUSB2_REG_EPFIFO(ep->ep_number), 1974 (void *)data, datalen >> 2); 1975 data += (datalen & ~0x3); 1976 datalen -= (datalen & ~0x3); 1977 } 1978 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 1979 datalen ,0 ,0); 1980 if (datalen) { 1981 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1982 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1983 } 1984 } 1985 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1986 KASSERT(ep->phase == DATA_IN); 1987 if (got_short || (ep->datalen == 0)) { 1988 if (ep->need_short_xfer == 0) { 1989 new_status = USBD_NORMAL_COMPLETION; 1990 goto complete; 1991 } 1992 ep->need_short_xfer = 0; 1993 } 1994 motg_device_data_read(xfer); 1995 return; 1996 complete: 1997 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 1998 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 1999 ep->phase = IDLE; 2000 ep->xfer = NULL; 2001 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2002 KASSERT(new_status != USBD_IN_PROGRESS); 2003 xfer->ux_status = new_status; 2004 usb_transfer_complete(xfer); 2005 } 2006 motg_device_data_start1(sc, ep); 2007 } 2008 2009 static void 2010 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2011 { 2012 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2013 struct usbd_xfer *xfer = ep->xfer; 2014 uint8_t csr; 2015 struct motg_pipe *otgpipe; 2016 usbd_status new_status = USBD_IN_PROGRESS; 2017 2018 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2019 2020 KASSERT(mutex_owned(&sc->sc_lock)); 2021 KASSERT(ep->ep_number == epnumber); 2022 2023 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2024 /* select endpoint */ 2025 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2026 2027 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2028 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr, 0, 0); 2029 2030 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2031 /* command not accepted */ 2032 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2033 new_status = USBD_STALLED; 2034 else 2035 new_status = USBD_IOERROR; 2036 /* clear status */ 2037 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2038 goto complete; 2039 } 2040 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2041 new_status = USBD_TIMEOUT; /* XXX */ 2042 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2043 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2044 /* flush fifo */ 2045 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2046 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2047 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2048 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2049 delay(1000); 2050 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2051 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR 0x%jx", 2052 epnumber, csr, 0, 0); 2053 } 2054 goto complete; 2055 } 2056 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2057 /* data still not sent */ 2058 return; 2059 } 2060 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2061 goto complete; 2062 KASSERT(ep->phase == DATA_OUT); 2063 2064 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2065 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2066 2067 if (ep->datalen == 0) { 2068 if (ep->need_short_xfer) { 2069 ep->need_short_xfer = 0; 2070 /* one more data phase */ 2071 } else { 2072 new_status = USBD_NORMAL_COMPLETION; 2073 goto complete; 2074 } 2075 } 2076 motg_device_data_write(xfer); 2077 return; 2078 2079 complete: 2080 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2081 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2082 KASSERTMSG(xfer && xfer->ux_status == USBD_IN_PROGRESS && 2083 ep->phase == DATA_OUT, "xfer %p status %d phase %d", 2084 xfer, xfer->ux_status, ep->phase); 2085 ep->phase = IDLE; 2086 ep->xfer = NULL; 2087 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2088 KASSERT(new_status != USBD_IN_PROGRESS); 2089 xfer->ux_status = new_status; 2090 usb_transfer_complete(xfer); 2091 } 2092 motg_device_data_start1(sc, ep); 2093 } 2094 2095 /* Abort a device control request. */ 2096 void 2097 motg_device_data_abort(struct usbd_xfer *xfer) 2098 { 2099 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2100 KASSERT(mutex_owned(&sc->sc_lock)); 2101 2102 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2103 2104 motg_device_xfer_abort(xfer); 2105 } 2106 2107 /* Close a device control pipe */ 2108 void 2109 motg_device_data_close(struct usbd_pipe *pipe) 2110 { 2111 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2112 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2113 struct motg_pipe *otgpipeiter; 2114 2115 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2116 2117 KASSERT(mutex_owned(&sc->sc_lock)); 2118 KASSERT(otgpipe->hw_ep->xfer == NULL || 2119 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2120 2121 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2122 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2123 if (otgpipeiter == otgpipe) { 2124 /* remove from list */ 2125 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2126 motg_pipe, ep_pipe_list); 2127 otgpipe->hw_ep->refcount--; 2128 /* we're done */ 2129 return; 2130 } 2131 } 2132 panic("motg_device_data_close: not found"); 2133 } 2134 2135 void 2136 motg_device_data_done(struct usbd_xfer *xfer) 2137 { 2138 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2139 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2140 2141 KASSERT(otgpipe->hw_ep->xfer != xfer); 2142 } 2143 2144 void 2145 motg_device_clear_toggle(struct usbd_pipe *pipe) 2146 { 2147 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2148 otgpipe->nexttoggle = 0; 2149 } 2150 2151 /* Abort a device control request. */ 2152 static void 2153 motg_device_xfer_abort(struct usbd_xfer *xfer) 2154 { 2155 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2156 uint8_t csr; 2157 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2158 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2159 2160 KASSERT(mutex_owned(&sc->sc_lock)); 2161 ASSERT_SLEEPABLE(); 2162 2163 /* 2164 * We are synchronously aborting. Try to stop the 2165 * callout and task, but if we can't, wait for them to 2166 * complete. 2167 */ 2168 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2169 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 2170 USB_TASKQ_HC, &sc->sc_lock); 2171 2172 /* 2173 * The xfer cannot have been cancelled already. It is the 2174 * responsibility of the caller of usbd_abort_pipe not to try 2175 * to abort a pipe multiple times, whether concurrently or 2176 * sequentially. 2177 */ 2178 KASSERT(xfer->ux_status != USBD_CANCELLED); 2179 2180 /* If anyone else beat us, we're done. */ 2181 if (xfer->ux_status != USBD_IN_PROGRESS) 2182 return; 2183 2184 /* We beat everyone else. Claim the status. */ 2185 xfer->ux_status = USBD_CANCELLED; 2186 2187 /* 2188 * If we're dying, skip the hardware action and just notify the 2189 * software that we're done. 2190 */ 2191 if (sc->sc_dying) { 2192 goto dying; 2193 } 2194 2195 if (otgpipe->hw_ep->xfer == xfer) { 2196 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2197 otgpipe->hw_ep->xfer = NULL; 2198 if (otgpipe->hw_ep->ep_number > 0) { 2199 /* select endpoint */ 2200 UWRITE1(sc, MUSB2_REG_EPINDEX, 2201 otgpipe->hw_ep->ep_number); 2202 if (otgpipe->hw_ep->phase == DATA_OUT) { 2203 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2204 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2205 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2206 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2207 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2208 } 2209 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2210 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2211 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2212 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2213 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2214 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2215 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2216 } 2217 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2218 } 2219 otgpipe->hw_ep->phase = IDLE; 2220 } 2221 } 2222 dying: 2223 usb_transfer_complete(xfer); 2224 KASSERT(mutex_owned(&sc->sc_lock)); 2225 } 2226
Indexes created Wed Sep 24 05:09:52 GMT 2025