motg.c revision 1.25
1 /* $NetBSD: motg.c,v 1.25 2019/02/17 04:17:52 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.25 2019/02/17 04:17:52 rin Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_usb.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usbhist.h> 69 70 #include <dev/usb/motgreg.h> 71 #include <dev/usb/motgvar.h> 72 #include <dev/usb/usbroothub.h> 73 74 #ifdef USB_DEBUG 75 #ifndef MOTG_DEBUG 76 #define motgdebug 0 77 #else 78 int motgdebug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 88 SYSCTL_DESCR("motg global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 107 #endif /* MOTG_DEBUG */ 108 #endif /* USB_DEBUG */ 109 110 #define MD_ROOT 0x0002 111 #define MD_CTRL 0x0004 112 #define MD_BULK 0x0008 113 114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 116 #define MOTGHIST_FUNC() USBHIST_FUNC() 117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 118 119 120 /* various timeouts, for various speeds */ 121 /* control NAK timeouts */ 122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 124 125 /* intr/iso polling intervals */ 126 #define POLL_TO 100 /* 100 frames, about 0.1s */ 127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 128 129 /* bulk NAK timeouts */ 130 #define NAK_TO_BULK 0 /* disabled */ 131 #define NAK_TO_BULK_HIGH 0 132 133 static void motg_hub_change(struct motg_softc *); 134 135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 136 static usbd_status motg_root_intr_start(struct usbd_xfer *); 137 static void motg_root_intr_abort(struct usbd_xfer *); 138 static void motg_root_intr_close(struct usbd_pipe *); 139 static void motg_root_intr_done(struct usbd_xfer *); 140 141 static usbd_status motg_open(struct usbd_pipe *); 142 static void motg_poll(struct usbd_bus *); 143 static void motg_softintr(void *); 144 static struct usbd_xfer * 145 motg_allocx(struct usbd_bus *, unsigned int); 146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 147 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 148 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 149 void *, int); 150 151 static void motg_noop(struct usbd_pipe *pipe); 152 static usbd_status motg_portreset(struct motg_softc*); 153 154 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 155 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 156 static void motg_device_ctrl_abort(struct usbd_xfer *); 157 static void motg_device_ctrl_close(struct usbd_pipe *); 158 static void motg_device_ctrl_done(struct usbd_xfer *); 159 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 160 static void motg_device_ctrl_read(struct usbd_xfer *); 161 static void motg_device_ctrl_intr_rx(struct motg_softc *); 162 static void motg_device_ctrl_intr_tx(struct motg_softc *); 163 164 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 165 static usbd_status motg_device_data_start(struct usbd_xfer *); 166 static usbd_status motg_device_data_start1(struct motg_softc *, 167 struct motg_hw_ep *); 168 static void motg_device_data_abort(struct usbd_xfer *); 169 static void motg_device_data_close(struct usbd_pipe *); 170 static void motg_device_data_done(struct usbd_xfer *); 171 static void motg_device_intr_rx(struct motg_softc *, int); 172 static void motg_device_intr_tx(struct motg_softc *, int); 173 static void motg_device_data_read(struct usbd_xfer *); 174 static void motg_device_data_write(struct usbd_xfer *); 175 176 static void motg_device_clear_toggle(struct usbd_pipe *); 177 static void motg_device_xfer_abort(struct usbd_xfer *); 178 179 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 180 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 181 #define UWRITE1(sc, r, x) \ 182 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 183 } while (/*CONSTCOND*/0) 184 #define UWRITE2(sc, r, x) \ 185 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 186 } while (/*CONSTCOND*/0) 187 #define UWRITE4(sc, r, x) \ 188 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 189 } while (/*CONSTCOND*/0) 190 191 static __inline uint32_t 192 UREAD1(struct motg_softc *sc, bus_size_t r) 193 { 194 195 UBARR(sc); 196 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 197 } 198 static __inline uint32_t 199 UREAD2(struct motg_softc *sc, bus_size_t r) 200 { 201 202 UBARR(sc); 203 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 204 } 205 206 #if 0 207 static __inline uint32_t 208 UREAD4(struct motg_softc *sc, bus_size_t r) 209 { 210 211 UBARR(sc); 212 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 213 } 214 #endif 215 216 static void 217 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 218 { 219 uint8_t val; 220 221 val = UREAD1(sc, MUSB2_REG_POWER); 222 if (on) 223 val |= MUSB2_MASK_SOFTC; 224 else 225 val &= ~MUSB2_MASK_SOFTC; 226 227 UWRITE1(sc, MUSB2_REG_POWER, val); 228 } 229 230 const struct usbd_bus_methods motg_bus_methods = { 231 .ubm_open = motg_open, 232 .ubm_softint = motg_softintr, 233 .ubm_dopoll = motg_poll, 234 .ubm_allocx = motg_allocx, 235 .ubm_freex = motg_freex, 236 .ubm_getlock = motg_get_lock, 237 .ubm_rhctrl = motg_roothub_ctrl, 238 }; 239 240 const struct usbd_pipe_methods motg_root_intr_methods = { 241 .upm_transfer = motg_root_intr_transfer, 242 .upm_start = motg_root_intr_start, 243 .upm_abort = motg_root_intr_abort, 244 .upm_close = motg_root_intr_close, 245 .upm_cleartoggle = motg_noop, 246 .upm_done = motg_root_intr_done, 247 }; 248 249 const struct usbd_pipe_methods motg_device_ctrl_methods = { 250 .upm_transfer = motg_device_ctrl_transfer, 251 .upm_start = motg_device_ctrl_start, 252 .upm_abort = motg_device_ctrl_abort, 253 .upm_close = motg_device_ctrl_close, 254 .upm_cleartoggle = motg_noop, 255 .upm_done = motg_device_ctrl_done, 256 }; 257 258 const struct usbd_pipe_methods motg_device_data_methods = { 259 .upm_transfer = motg_device_data_transfer, 260 .upm_start = motg_device_data_start, 261 .upm_abort = motg_device_data_abort, 262 .upm_close = motg_device_data_close, 263 .upm_cleartoggle = motg_device_clear_toggle, 264 .upm_done = motg_device_data_done, 265 }; 266 267 int 268 motg_init(struct motg_softc *sc) 269 { 270 uint32_t nrx, ntx, val; 271 int dynfifo; 272 int offset, i; 273 274 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 275 276 if (sc->sc_mode == MOTG_MODE_DEVICE) 277 return ENOTSUP; /* not supported */ 278 279 /* disable all interrupts */ 280 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 281 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 282 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 283 /* disable pullup */ 284 285 musbotg_pull_common(sc, 0); 286 287 #ifdef MUSB2_REG_RXDBDIS 288 /* disable double packet buffering XXX what's this ? */ 289 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 290 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 291 #endif 292 293 /* enable HighSpeed and ISO Update flags */ 294 295 UWRITE1(sc, MUSB2_REG_POWER, 296 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 297 298 if (sc->sc_mode == MOTG_MODE_DEVICE) { 299 /* clear Session bit, if set */ 300 val = UREAD1(sc, MUSB2_REG_DEVCTL); 301 val &= ~MUSB2_MASK_SESS; 302 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 303 } else { 304 /* Enter session for Host mode */ 305 val = UREAD1(sc, MUSB2_REG_DEVCTL); 306 val |= MUSB2_MASK_SESS; 307 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 308 } 309 delay(1000); 310 DPRINTF("DEVCTL 0x%jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 311 312 /* disable testmode */ 313 314 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 315 316 #ifdef MUSB2_REG_MISC 317 /* set default value */ 318 319 UWRITE1(sc, MUSB2_REG_MISC, 0); 320 #endif 321 322 /* select endpoint index 0 */ 323 324 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 325 326 if (sc->sc_ep_max == 0) { 327 /* read out number of endpoints */ 328 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 329 330 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 331 332 /* these numbers exclude the control endpoint */ 333 334 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 335 336 sc->sc_ep_max = MAX(nrx, ntx); 337 } else { 338 nrx = ntx = sc->sc_ep_max; 339 } 340 if (sc->sc_ep_max == 0) { 341 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 342 return -1; 343 } 344 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 345 /* read out configuration data */ 346 val = UREAD1(sc, MUSB2_REG_CONFDATA); 347 348 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 349 350 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 351 352 if (dynfifo) { 353 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 354 "assuming 16Kbytes of FIFO RAM\n"); 355 } 356 357 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 358 359 /* initialise endpoint profiles */ 360 sc->sc_in_ep[0].ep_fifo_size = 64; 361 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 362 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 363 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 364 offset = 64; 365 366 for (i = 1; i <= sc->sc_ep_max; i++) { 367 int fiforx_size, fifotx_size, fifo_size; 368 369 /* select endpoint */ 370 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 371 372 if (sc->sc_ep_fifosize) { 373 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 374 } else { 375 val = UREAD1(sc, MUSB2_REG_FSIZE); 376 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 377 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 378 } 379 380 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 381 i, fifotx_size, fiforx_size, dynfifo); 382 383 if (dynfifo) { 384 if (sc->sc_ep_fifosize) { 385 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 386 } else { 387 if (i < 3) { 388 fifo_size = 12; /* 4K */ 389 } else if (i < 10) { 390 fifo_size = 10; /* 1K */ 391 } else { 392 fifo_size = 7; /* 128 bytes */ 393 } 394 } 395 if (fiforx_size && (i <= nrx)) { 396 fiforx_size = fifo_size; 397 if (fifo_size > 7) { 398 #if 0 399 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 400 MUSB2_VAL_FIFOSZ(fifo_size) | 401 MUSB2_MASK_FIFODB); 402 #else 403 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 404 MUSB2_VAL_FIFOSZ(fifo_size)); 405 #endif 406 } else { 407 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 408 MUSB2_VAL_FIFOSZ(fifo_size)); 409 } 410 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 411 offset >> 3); 412 offset += (1 << fiforx_size); 413 } 414 if (fifotx_size && (i <= ntx)) { 415 fifotx_size = fifo_size; 416 if (fifo_size > 7) { 417 #if 0 418 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 419 MUSB2_VAL_FIFOSZ(fifo_size) | 420 MUSB2_MASK_FIFODB); 421 #else 422 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 423 MUSB2_VAL_FIFOSZ(fifo_size)); 424 #endif 425 } else { 426 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 427 MUSB2_VAL_FIFOSZ(fifo_size)); 428 } 429 430 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 431 offset >> 3); 432 433 offset += (1 << fifotx_size); 434 } 435 } 436 if (fiforx_size && (i <= nrx)) { 437 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 438 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 439 } 440 if (fifotx_size && (i <= ntx)) { 441 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 442 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 443 } 444 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 445 } 446 447 448 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 449 450 /* turn on default interrupts */ 451 452 if (sc->sc_mode == MOTG_MODE_HOST) { 453 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 454 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 455 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 456 } else 457 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 458 459 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 460 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 461 462 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 463 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 464 465 /* Set up the bus struct. */ 466 sc->sc_bus.ub_methods = &motg_bus_methods; 467 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 468 sc->sc_bus.ub_revision = USBREV_2_0; 469 sc->sc_bus.ub_usedma = false; 470 sc->sc_bus.ub_hcpriv = sc; 471 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 472 return 0; 473 } 474 475 static int 476 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 477 { 478 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 479 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 480 struct motg_hw_ep *ep; 481 int i, size; 482 483 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 484 485 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 486 sc->sc_in_ep : sc->sc_out_ep; 487 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 488 489 for (i = sc->sc_ep_max; i >= 1; i--) { 490 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 491 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 492 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 493 ep[i].ep_fifo_size, size, ep[i].refcount); 494 if (ep[i].ep_fifo_size >= size) { 495 /* found a suitable endpoint */ 496 otgpipe->hw_ep = &ep[i]; 497 mutex_enter(&sc->sc_lock); 498 if (otgpipe->hw_ep->refcount > 0) { 499 /* no luck, try next */ 500 mutex_exit(&sc->sc_lock); 501 otgpipe->hw_ep = NULL; 502 } else { 503 otgpipe->hw_ep->refcount++; 504 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 505 otgpipe, ep_pipe_list); 506 mutex_exit(&sc->sc_lock); 507 return 0; 508 } 509 } 510 } 511 return -1; 512 } 513 514 /* Open a new pipe. */ 515 usbd_status 516 motg_open(struct usbd_pipe *pipe) 517 { 518 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 519 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 520 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 521 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 522 523 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 524 525 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 526 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 527 528 if (sc->sc_dying) 529 return USBD_IOERROR; 530 531 /* toggle state needed for bulk endpoints */ 532 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 533 534 if (pipe->up_dev->ud_addr == rhaddr) { 535 switch (ed->bEndpointAddress) { 536 case USB_CONTROL_ENDPOINT: 537 pipe->up_methods = &roothub_ctrl_methods; 538 break; 539 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 540 pipe->up_methods = &motg_root_intr_methods; 541 break; 542 default: 543 return USBD_INVAL; 544 } 545 } else { 546 switch (ed->bmAttributes & UE_XFERTYPE) { 547 case UE_CONTROL: 548 pipe->up_methods = &motg_device_ctrl_methods; 549 /* always use sc_in_ep[0] for in and out */ 550 otgpipe->hw_ep = &sc->sc_in_ep[0]; 551 mutex_enter(&sc->sc_lock); 552 otgpipe->hw_ep->refcount++; 553 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 554 otgpipe, ep_pipe_list); 555 mutex_exit(&sc->sc_lock); 556 break; 557 case UE_BULK: 558 case UE_INTERRUPT: 559 DPRINTFN(MD_BULK, 560 "type %jd dir %jd pipe wMaxPacketSize %jd", 561 UE_GET_XFERTYPE(ed->bmAttributes), 562 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 563 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 564 if (motg_select_ep(sc, pipe) != 0) 565 goto bad; 566 KASSERT(otgpipe->hw_ep != NULL); 567 pipe->up_methods = &motg_device_data_methods; 568 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 569 break; 570 default: 571 goto bad; 572 #ifdef notyet 573 case UE_ISOCHRONOUS: 574 ... 575 break; 576 #endif /* notyet */ 577 } 578 } 579 return USBD_NORMAL_COMPLETION; 580 581 bad: 582 return USBD_NOMEM; 583 } 584 585 void 586 motg_softintr(void *v) 587 { 588 struct usbd_bus *bus = v; 589 struct motg_softc *sc = MOTG_BUS2SC(bus); 590 uint16_t rx_status, tx_status; 591 uint8_t ctrl_status; 592 uint32_t val; 593 int i; 594 595 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 596 597 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 598 599 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 600 601 mutex_spin_enter(&sc->sc_intr_lock); 602 rx_status = sc->sc_intr_rx_ep; 603 sc->sc_intr_rx_ep = 0; 604 tx_status = sc->sc_intr_tx_ep; 605 sc->sc_intr_tx_ep = 0; 606 ctrl_status = sc->sc_intr_ctrl; 607 sc->sc_intr_ctrl = 0; 608 mutex_spin_exit(&sc->sc_intr_lock); 609 610 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 611 612 if (ctrl_status & (MUSB2_MASK_IRESET | 613 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 614 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 615 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%jx", ctrl_status, 0, 0, 0); 616 617 if (ctrl_status & MUSB2_MASK_IRESET) { 618 sc->sc_isreset = 1; 619 sc->sc_port_suspended = 0; 620 sc->sc_port_suspended_change = 1; 621 sc->sc_connected_changed = 1; 622 sc->sc_port_enabled = 1; 623 624 val = UREAD1(sc, MUSB2_REG_POWER); 625 if (val & MUSB2_MASK_HSMODE) 626 sc->sc_high_speed = 1; 627 else 628 sc->sc_high_speed = 0; 629 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 630 0, 0, 0); 631 632 /* turn off interrupts */ 633 val = MUSB2_MASK_IRESET; 634 val &= ~MUSB2_MASK_IRESUME; 635 val |= MUSB2_MASK_ISUSP; 636 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 637 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 638 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 639 } 640 if (ctrl_status & MUSB2_MASK_IRESUME) { 641 if (sc->sc_port_suspended) { 642 sc->sc_port_suspended = 0; 643 sc->sc_port_suspended_change = 1; 644 val = UREAD1(sc, MUSB2_REG_INTUSBE); 645 /* disable resume interrupt */ 646 val &= ~MUSB2_MASK_IRESUME; 647 /* enable suspend interrupt */ 648 val |= MUSB2_MASK_ISUSP; 649 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 650 } 651 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 652 if (!sc->sc_port_suspended) { 653 sc->sc_port_suspended = 1; 654 sc->sc_port_suspended_change = 1; 655 656 val = UREAD1(sc, MUSB2_REG_INTUSBE); 657 /* disable suspend interrupt */ 658 val &= ~MUSB2_MASK_ISUSP; 659 /* enable resume interrupt */ 660 val |= MUSB2_MASK_IRESUME; 661 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 662 } 663 } 664 if (ctrl_status & MUSB2_MASK_ICONN) { 665 sc->sc_connected = 1; 666 sc->sc_connected_changed = 1; 667 sc->sc_isreset = 1; 668 sc->sc_port_enabled = 1; 669 } else if (ctrl_status & MUSB2_MASK_IDISC) { 670 sc->sc_connected = 0; 671 sc->sc_connected_changed = 1; 672 sc->sc_isreset = 0; 673 sc->sc_port_enabled = 0; 674 } 675 676 /* complete root HUB interrupt endpoint */ 677 678 motg_hub_change(sc); 679 } 680 /* 681 * read in interrupt status and mix with the status we 682 * got from the wrapper 683 */ 684 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 685 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 686 687 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 688 if (tx_status & 0x01) 689 motg_device_ctrl_intr_tx(sc); 690 for (i = 1; i <= sc->sc_ep_max; i++) { 691 if (rx_status & (0x01 << i)) 692 motg_device_intr_rx(sc, i); 693 if (tx_status & (0x01 << i)) 694 motg_device_intr_tx(sc, i); 695 } 696 return; 697 } 698 699 void 700 motg_poll(struct usbd_bus *bus) 701 { 702 struct motg_softc *sc = MOTG_BUS2SC(bus); 703 704 sc->sc_intr_poll(sc->sc_intr_poll_arg); 705 mutex_enter(&sc->sc_lock); 706 motg_softintr(bus); 707 mutex_exit(&sc->sc_lock); 708 } 709 710 int 711 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 712 uint8_t ctrl) 713 { 714 KASSERT(mutex_owned(&sc->sc_intr_lock)); 715 sc->sc_intr_tx_ep = tx_ep; 716 sc->sc_intr_rx_ep = rx_ep; 717 sc->sc_intr_ctrl = ctrl; 718 719 if (!sc->sc_bus.ub_usepolling) { 720 usb_schedsoftintr(&sc->sc_bus); 721 } 722 return 1; 723 } 724 725 int 726 motg_intr_vbus(struct motg_softc *sc, int vbus) 727 { 728 uint8_t val; 729 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 730 731 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 732 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 733 /* try to re-enter session for Host mode */ 734 val = UREAD1(sc, MUSB2_REG_DEVCTL); 735 val |= MUSB2_MASK_SESS; 736 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 737 } 738 return 1; 739 } 740 741 struct usbd_xfer * 742 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 743 { 744 struct motg_softc *sc = MOTG_BUS2SC(bus); 745 struct usbd_xfer *xfer; 746 747 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 748 if (xfer != NULL) { 749 memset(xfer, 0, sizeof(struct motg_xfer)); 750 #ifdef DIAGNOSTIC 751 xfer->ux_state = XFER_BUSY; 752 #endif 753 } 754 return xfer; 755 } 756 757 void 758 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 759 { 760 struct motg_softc *sc = MOTG_BUS2SC(bus); 761 762 #ifdef DIAGNOSTIC 763 if (xfer->ux_state != XFER_BUSY && 764 xfer->ux_status != USBD_NOT_STARTED) { 765 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 766 xfer->ux_state); 767 } 768 xfer->ux_state = XFER_FREE; 769 #endif 770 pool_cache_put(sc->sc_xferpool, xfer); 771 } 772 773 static void 774 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 775 { 776 struct motg_softc *sc = MOTG_BUS2SC(bus); 777 778 *lock = &sc->sc_lock; 779 } 780 781 /* 782 * Routines to emulate the root hub. 783 */ 784 Static int 785 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 786 void *buf, int buflen) 787 { 788 struct motg_softc *sc = MOTG_BUS2SC(bus); 789 int status, change, totlen = 0; 790 uint16_t len, value, index; 791 usb_port_status_t ps; 792 usbd_status err; 793 uint32_t val; 794 795 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 796 797 if (sc->sc_dying) 798 return -1; 799 800 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 801 req->bRequest, 0, 0); 802 803 len = UGETW(req->wLength); 804 value = UGETW(req->wValue); 805 index = UGETW(req->wIndex); 806 807 #define C(x,y) ((x) | ((y) << 8)) 808 switch (C(req->bRequest, req->bmRequestType)) { 809 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 810 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 811 switch (value) { 812 #define sd ((usb_string_descriptor_t *)buf) 813 case C(2, UDESC_STRING): 814 /* Product */ 815 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 816 break; 817 #undef sd 818 default: 819 /* default from usbroothub */ 820 return buflen; 821 } 822 break; 823 /* Hub requests */ 824 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 825 break; 826 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 827 DPRINTFN(MD_ROOT, 828 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 829 0, 0); 830 if (index != 1) { 831 return -1; 832 } 833 switch (value) { 834 case UHF_PORT_ENABLE: 835 sc->sc_port_enabled = 0; 836 break; 837 case UHF_PORT_SUSPEND: 838 if (sc->sc_port_suspended != 0) { 839 val = UREAD1(sc, MUSB2_REG_POWER); 840 val &= ~MUSB2_MASK_SUSPMODE; 841 val |= MUSB2_MASK_RESUME; 842 UWRITE1(sc, MUSB2_REG_POWER, val); 843 /* wait 20 milliseconds */ 844 usb_delay_ms(&sc->sc_bus, 20); 845 val = UREAD1(sc, MUSB2_REG_POWER); 846 val &= ~MUSB2_MASK_RESUME; 847 UWRITE1(sc, MUSB2_REG_POWER, val); 848 sc->sc_port_suspended = 0; 849 sc->sc_port_suspended_change = 1; 850 } 851 break; 852 case UHF_PORT_RESET: 853 break; 854 case UHF_C_PORT_CONNECTION: 855 break; 856 case UHF_C_PORT_ENABLE: 857 break; 858 case UHF_C_PORT_OVER_CURRENT: 859 break; 860 case UHF_C_PORT_RESET: 861 sc->sc_isreset = 0; 862 break; 863 case UHF_PORT_POWER: 864 /* XXX todo */ 865 break; 866 case UHF_PORT_CONNECTION: 867 case UHF_PORT_OVER_CURRENT: 868 case UHF_PORT_LOW_SPEED: 869 case UHF_C_PORT_SUSPEND: 870 default: 871 return -1; 872 } 873 break; 874 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 875 return -1; 876 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 877 if (len == 0) 878 break; 879 if ((value & 0xff) != 0) { 880 return -1; 881 } 882 totlen = buflen; 883 break; 884 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 885 if (len != 4) { 886 return -1; 887 } 888 memset(buf, 0, len); 889 totlen = len; 890 break; 891 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 892 if (index != 1) { 893 return -1; 894 } 895 if (len != 4) { 896 return -1; 897 } 898 status = change = 0; 899 if (sc->sc_connected) 900 status |= UPS_CURRENT_CONNECT_STATUS; 901 if (sc->sc_connected_changed) { 902 change |= UPS_C_CONNECT_STATUS; 903 sc->sc_connected_changed = 0; 904 } 905 if (sc->sc_port_enabled) 906 status |= UPS_PORT_ENABLED; 907 if (sc->sc_port_enabled_changed) { 908 change |= UPS_C_PORT_ENABLED; 909 sc->sc_port_enabled_changed = 0; 910 } 911 if (sc->sc_port_suspended) 912 status |= UPS_SUSPEND; 913 if (sc->sc_high_speed) 914 status |= UPS_HIGH_SPEED; 915 status |= UPS_PORT_POWER; /* XXX */ 916 if (sc->sc_isreset) 917 change |= UPS_C_PORT_RESET; 918 USETW(ps.wPortStatus, status); 919 USETW(ps.wPortChange, change); 920 totlen = uimin(len, sizeof(ps)); 921 memcpy(buf, &ps, totlen); 922 break; 923 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 924 return -1; 925 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 926 break; 927 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 928 if (index != 1) { 929 return -1; 930 } 931 switch(value) { 932 case UHF_PORT_ENABLE: 933 sc->sc_port_enabled = 1; 934 break; 935 case UHF_PORT_SUSPEND: 936 if (sc->sc_port_suspended == 0) { 937 val = UREAD1(sc, MUSB2_REG_POWER); 938 val |= MUSB2_MASK_SUSPMODE; 939 UWRITE1(sc, MUSB2_REG_POWER, val); 940 /* wait 20 milliseconds */ 941 usb_delay_ms(&sc->sc_bus, 20); 942 sc->sc_port_suspended = 1; 943 sc->sc_port_suspended_change = 1; 944 } 945 break; 946 case UHF_PORT_RESET: 947 err = motg_portreset(sc); 948 if (err != USBD_NORMAL_COMPLETION) 949 return -1; 950 return 0; 951 case UHF_PORT_POWER: 952 /* XXX todo */ 953 return 0; 954 case UHF_C_PORT_CONNECTION: 955 case UHF_C_PORT_ENABLE: 956 case UHF_C_PORT_OVER_CURRENT: 957 case UHF_PORT_CONNECTION: 958 case UHF_PORT_OVER_CURRENT: 959 case UHF_PORT_LOW_SPEED: 960 case UHF_C_PORT_SUSPEND: 961 case UHF_C_PORT_RESET: 962 default: 963 return -1; 964 } 965 break; 966 default: 967 /* default from usbroothub */ 968 return buflen; 969 } 970 971 return totlen; 972 } 973 974 /* Abort a root interrupt request. */ 975 void 976 motg_root_intr_abort(struct usbd_xfer *xfer) 977 { 978 struct motg_softc *sc = MOTG_XFER2SC(xfer); 979 980 KASSERT(mutex_owned(&sc->sc_lock)); 981 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 982 983 sc->sc_intr_xfer = NULL; 984 985 xfer->ux_status = USBD_CANCELLED; 986 usb_transfer_complete(xfer); 987 } 988 989 usbd_status 990 motg_root_intr_transfer(struct usbd_xfer *xfer) 991 { 992 struct motg_softc *sc = MOTG_XFER2SC(xfer); 993 usbd_status err; 994 995 /* Insert last in queue. */ 996 mutex_enter(&sc->sc_lock); 997 err = usb_insert_transfer(xfer); 998 mutex_exit(&sc->sc_lock); 999 if (err) 1000 return err; 1001 1002 /* 1003 * Pipe isn't running (otherwise err would be USBD_INPROG), 1004 * start first 1005 */ 1006 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1007 } 1008 1009 /* Start a transfer on the root interrupt pipe */ 1010 usbd_status 1011 motg_root_intr_start(struct usbd_xfer *xfer) 1012 { 1013 struct usbd_pipe *pipe = xfer->ux_pipe; 1014 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1015 1016 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1017 1018 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1019 xfer->ux_length, xfer->ux_flags, 0); 1020 1021 if (sc->sc_dying) 1022 return USBD_IOERROR; 1023 1024 sc->sc_intr_xfer = xfer; 1025 return USBD_IN_PROGRESS; 1026 } 1027 1028 /* Close the root interrupt pipe. */ 1029 void 1030 motg_root_intr_close(struct usbd_pipe *pipe) 1031 { 1032 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1033 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1034 1035 KASSERT(mutex_owned(&sc->sc_lock)); 1036 1037 sc->sc_intr_xfer = NULL; 1038 } 1039 1040 void 1041 motg_root_intr_done(struct usbd_xfer *xfer) 1042 { 1043 } 1044 1045 void 1046 motg_noop(struct usbd_pipe *pipe) 1047 { 1048 } 1049 1050 static usbd_status 1051 motg_portreset(struct motg_softc *sc) 1052 { 1053 uint32_t val; 1054 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1055 1056 val = UREAD1(sc, MUSB2_REG_POWER); 1057 val |= MUSB2_MASK_RESET; 1058 UWRITE1(sc, MUSB2_REG_POWER, val); 1059 /* Wait for 20 msec */ 1060 usb_delay_ms(&sc->sc_bus, 20); 1061 1062 val = UREAD1(sc, MUSB2_REG_POWER); 1063 val &= ~MUSB2_MASK_RESET; 1064 UWRITE1(sc, MUSB2_REG_POWER, val); 1065 1066 /* determine line speed */ 1067 val = UREAD1(sc, MUSB2_REG_POWER); 1068 if (val & MUSB2_MASK_HSMODE) 1069 sc->sc_high_speed = 1; 1070 else 1071 sc->sc_high_speed = 0; 1072 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1073 1074 sc->sc_isreset = 1; 1075 sc->sc_port_enabled = 1; 1076 return USBD_NORMAL_COMPLETION; 1077 } 1078 1079 /* 1080 * This routine is executed when an interrupt on the root hub is detected 1081 */ 1082 static void 1083 motg_hub_change(struct motg_softc *sc) 1084 { 1085 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1086 struct usbd_pipe *pipe; 1087 u_char *p; 1088 1089 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1090 1091 if (xfer == NULL) 1092 return; /* the interrupt pipe is not open */ 1093 1094 pipe = xfer->ux_pipe; 1095 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1096 return; /* device has detached */ 1097 1098 p = xfer->ux_buf; 1099 p[0] = 1<<1; 1100 xfer->ux_actlen = 1; 1101 xfer->ux_status = USBD_NORMAL_COMPLETION; 1102 usb_transfer_complete(xfer); 1103 } 1104 1105 static uint8_t 1106 motg_speed(uint8_t speed) 1107 { 1108 switch(speed) { 1109 case USB_SPEED_LOW: 1110 return MUSB2_MASK_TI_SPEED_LO; 1111 case USB_SPEED_FULL: 1112 return MUSB2_MASK_TI_SPEED_FS; 1113 case USB_SPEED_HIGH: 1114 return MUSB2_MASK_TI_SPEED_HS; 1115 default: 1116 panic("motg: unknown speed %d", speed); 1117 /* NOTREACHED */ 1118 } 1119 } 1120 1121 static uint8_t 1122 motg_type(uint8_t type) 1123 { 1124 switch(type) { 1125 case UE_CONTROL: 1126 return MUSB2_MASK_TI_PROTO_CTRL; 1127 case UE_ISOCHRONOUS: 1128 return MUSB2_MASK_TI_PROTO_ISOC; 1129 case UE_BULK: 1130 return MUSB2_MASK_TI_PROTO_BULK; 1131 case UE_INTERRUPT: 1132 return MUSB2_MASK_TI_PROTO_INTR; 1133 default: 1134 panic("motg: unknown type %d", type); 1135 /* NOTREACHED */ 1136 } 1137 } 1138 1139 static void 1140 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1141 { 1142 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1143 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1144 struct usbd_device *dev = otgpipe->pipe.up_dev; 1145 int epnumber = otgpipe->hw_ep->ep_number; 1146 1147 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1148 if (dev->ud_myhsport) { 1149 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1150 dev->ud_myhsport->up_parent->ud_addr); 1151 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1152 dev->ud_myhsport->up_portno); 1153 } else { 1154 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1155 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1156 } 1157 UWRITE1(sc, MUSB2_REG_TXTI, 1158 motg_speed(dev->ud_speed) | 1159 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1160 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1161 ); 1162 if (epnumber == 0) { 1163 if (sc->sc_high_speed) { 1164 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1165 NAK_TO_CTRL_HIGH); 1166 } else { 1167 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1168 } 1169 } else { 1170 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1171 == UE_BULK) { 1172 if (sc->sc_high_speed) { 1173 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1174 NAK_TO_BULK_HIGH); 1175 } else { 1176 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1177 } 1178 } else { 1179 if (sc->sc_high_speed) { 1180 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1181 } else { 1182 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1183 } 1184 } 1185 } 1186 } 1187 1188 static void 1189 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1190 { 1191 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1192 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1193 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1194 int epnumber = otgpipe->hw_ep->ep_number; 1195 1196 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1197 if (dev->ud_myhsport) { 1198 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1199 dev->ud_myhsport->up_parent->ud_addr); 1200 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1201 dev->ud_myhsport->up_portno); 1202 } else { 1203 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1204 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1205 } 1206 UWRITE1(sc, MUSB2_REG_RXTI, 1207 motg_speed(dev->ud_speed) | 1208 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1209 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1210 ); 1211 if (epnumber == 0) { 1212 if (sc->sc_high_speed) { 1213 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1214 NAK_TO_CTRL_HIGH); 1215 } else { 1216 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1217 } 1218 } else { 1219 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1220 == UE_BULK) { 1221 if (sc->sc_high_speed) { 1222 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1223 NAK_TO_BULK_HIGH); 1224 } else { 1225 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1226 } 1227 } else { 1228 if (sc->sc_high_speed) { 1229 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1230 } else { 1231 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1232 } 1233 } 1234 } 1235 } 1236 1237 static usbd_status 1238 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1239 { 1240 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1241 usbd_status err; 1242 1243 /* Insert last in queue. */ 1244 mutex_enter(&sc->sc_lock); 1245 err = usb_insert_transfer(xfer); 1246 xfer->ux_status = USBD_NOT_STARTED; 1247 mutex_exit(&sc->sc_lock); 1248 if (err) 1249 return err; 1250 1251 /* 1252 * Pipe isn't running (otherwise err would be USBD_INPROG), 1253 * so start it first. 1254 */ 1255 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1256 } 1257 1258 static usbd_status 1259 motg_device_ctrl_start(struct usbd_xfer *xfer) 1260 { 1261 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1262 usbd_status err; 1263 mutex_enter(&sc->sc_lock); 1264 err = motg_device_ctrl_start1(sc); 1265 mutex_exit(&sc->sc_lock); 1266 if (err != USBD_IN_PROGRESS) 1267 return err; 1268 return USBD_IN_PROGRESS; 1269 } 1270 1271 static usbd_status 1272 motg_device_ctrl_start1(struct motg_softc *sc) 1273 { 1274 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1275 struct usbd_xfer *xfer = NULL; 1276 struct motg_pipe *otgpipe; 1277 usbd_status err = 0; 1278 1279 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1280 1281 KASSERT(mutex_owned(&sc->sc_lock)); 1282 if (sc->sc_dying) 1283 return USBD_IOERROR; 1284 1285 if (!sc->sc_connected) 1286 return USBD_IOERROR; 1287 1288 if (ep->xfer != NULL) { 1289 err = USBD_IN_PROGRESS; 1290 goto end; 1291 } 1292 /* locate the first pipe with work to do */ 1293 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1294 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1295 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1296 (uintptr_t)otgpipe, (uintptr_t)xfer, 1297 (xfer != NULL) ? xfer->ux_status : 0, 0); 1298 1299 if (xfer != NULL) { 1300 /* move this pipe to the end of the list */ 1301 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1302 motg_pipe, ep_pipe_list); 1303 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1304 otgpipe, ep_pipe_list); 1305 break; 1306 } 1307 } 1308 if (xfer == NULL) { 1309 err = USBD_NOT_STARTED; 1310 goto end; 1311 } 1312 xfer->ux_status = USBD_IN_PROGRESS; 1313 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1314 KASSERT(otgpipe->hw_ep == ep); 1315 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1316 // KASSERT(xfer->ux_actlen == 0); 1317 xfer->ux_actlen = 0; 1318 1319 ep->xfer = xfer; 1320 ep->datalen = xfer->ux_length; 1321 if (ep->datalen > 0) 1322 ep->data = xfer->ux_buf; 1323 else 1324 ep->data = NULL; 1325 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1326 (ep->datalen % 64) == 0) 1327 ep->need_short_xfer = 1; 1328 else 1329 ep->need_short_xfer = 0; 1330 /* now we need send this request */ 1331 DPRINTFN(MD_CTRL, 1332 "xfer %#jx send data %#jx len %jd short %jd", 1333 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1334 ep->need_short_xfer); 1335 DPRINTFN(MD_CTRL, 1336 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1337 xfer->ux_pipe->up_dev->ud_speed, 1338 xfer->ux_pipe->up_dev->ud_addr, 0); 1339 KASSERT(ep->phase == IDLE); 1340 ep->phase = SETUP; 1341 /* select endpoint 0 */ 1342 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1343 /* fifo should be empty at this point */ 1344 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1345 /* send data */ 1346 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1347 KASSERT(sizeof(xfer->ux_request) == 8); 1348 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1349 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1350 1351 motg_setup_endpoint_tx(xfer); 1352 /* start transaction */ 1353 UWRITE1(sc, MUSB2_REG_TXCSRL, 1354 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1355 1356 end: 1357 if (err) 1358 return err; 1359 1360 return USBD_IN_PROGRESS; 1361 } 1362 1363 static void 1364 motg_device_ctrl_read(struct usbd_xfer *xfer) 1365 { 1366 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1367 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1368 /* assume endpoint already selected */ 1369 motg_setup_endpoint_rx(xfer); 1370 /* start transaction */ 1371 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1372 otgpipe->hw_ep->phase = DATA_IN; 1373 } 1374 1375 static void 1376 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1377 { 1378 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1379 struct usbd_xfer *xfer = ep->xfer; 1380 uint8_t csr; 1381 int datalen, max_datalen; 1382 char *data; 1383 bool got_short; 1384 usbd_status new_status = USBD_IN_PROGRESS; 1385 1386 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1387 1388 KASSERT(mutex_owned(&sc->sc_lock)); 1389 1390 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1391 /* select endpoint 0 */ 1392 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1393 1394 /* read out FIFO status */ 1395 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1396 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1397 ep->phase, csr, (uintptr_t)xfer, 1398 (xfer != NULL) ? xfer->ux_status : 0); 1399 1400 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1401 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1402 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1403 1404 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1405 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1406 new_status = USBD_TIMEOUT; /* XXX */ 1407 goto complete; 1408 } 1409 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1410 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1411 new_status = USBD_STALLED; 1412 else 1413 new_status = USBD_IOERROR; 1414 /* clear status */ 1415 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1416 goto complete; 1417 } 1418 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1419 return; /* no data yet */ 1420 1421 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1422 goto complete; 1423 1424 if (ep->phase == STATUS_IN) { 1425 new_status = USBD_NORMAL_COMPLETION; 1426 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1427 goto complete; 1428 } 1429 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1430 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1431 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1432 max_datalen = uimin(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1433 ep->datalen); 1434 if (datalen > max_datalen) { 1435 new_status = USBD_IOERROR; 1436 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1437 goto complete; 1438 } 1439 got_short = (datalen < max_datalen); 1440 if (datalen > 0) { 1441 KASSERT(ep->phase == DATA_IN); 1442 data = ep->data; 1443 ep->data += datalen; 1444 ep->datalen -= datalen; 1445 xfer->ux_actlen += datalen; 1446 if (((vaddr_t)data & 0x3) == 0 && 1447 (datalen >> 2) > 0) { 1448 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1449 (uintptr_t)data, datalen, 0, 0); 1450 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1451 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1452 data += (datalen & ~0x3); 1453 datalen -= (datalen & ~0x3); 1454 } 1455 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1456 datalen, 0, 0); 1457 if (datalen) { 1458 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1459 MUSB2_REG_EPFIFO(0), data, datalen); 1460 } 1461 } 1462 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1463 KASSERT(ep->phase == DATA_IN); 1464 if (got_short || (ep->datalen == 0)) { 1465 if (ep->need_short_xfer == 0) { 1466 ep->phase = STATUS_OUT; 1467 UWRITE1(sc, MUSB2_REG_TXCSRH, 1468 UREAD1(sc, MUSB2_REG_TXCSRH) | 1469 MUSB2_MASK_CSR0H_PING_DIS); 1470 motg_setup_endpoint_tx(xfer); 1471 UWRITE1(sc, MUSB2_REG_TXCSRL, 1472 MUSB2_MASK_CSR0L_STATUSPKT | 1473 MUSB2_MASK_CSR0L_TXPKTRDY); 1474 return; 1475 } 1476 ep->need_short_xfer = 0; 1477 } 1478 motg_device_ctrl_read(xfer); 1479 return; 1480 complete: 1481 ep->phase = IDLE; 1482 ep->xfer = NULL; 1483 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1484 KASSERT(new_status != USBD_IN_PROGRESS); 1485 xfer->ux_status = new_status; 1486 usb_transfer_complete(xfer); 1487 } 1488 motg_device_ctrl_start1(sc); 1489 } 1490 1491 static void 1492 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1493 { 1494 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1495 struct usbd_xfer *xfer = ep->xfer; 1496 uint8_t csr; 1497 int datalen; 1498 char *data; 1499 usbd_status new_status = USBD_IN_PROGRESS; 1500 1501 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1502 1503 KASSERT(mutex_owned(&sc->sc_lock)); 1504 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1505 motg_device_ctrl_intr_rx(sc); 1506 return; 1507 } 1508 1509 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1510 ep->phase == STATUS_OUT); 1511 1512 /* select endpoint 0 */ 1513 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1514 1515 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1516 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1517 ep->phase, csr, (uintptr_t)xfer, 1518 (xfer != NULL) ? xfer->ux_status : 0); 1519 1520 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1521 /* command not accepted */ 1522 new_status = USBD_STALLED; 1523 /* clear status */ 1524 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1525 goto complete; 1526 } 1527 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1528 new_status = USBD_TIMEOUT; /* XXX */ 1529 /* flush fifo */ 1530 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1531 UWRITE1(sc, MUSB2_REG_TXCSRH, 1532 UREAD1(sc, MUSB2_REG_TXCSRH) | 1533 MUSB2_MASK_CSR0H_FFLUSH); 1534 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1535 } 1536 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1537 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1538 goto complete; 1539 } 1540 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1541 new_status = USBD_IOERROR; 1542 /* clear status */ 1543 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1544 goto complete; 1545 } 1546 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1547 /* data still not sent */ 1548 return; 1549 } 1550 if (xfer == NULL) 1551 goto complete; 1552 if (ep->phase == STATUS_OUT) { 1553 /* 1554 * we have sent status and got no error; 1555 * declare transfer complete 1556 */ 1557 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1558 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1559 new_status = USBD_NORMAL_COMPLETION; 1560 goto complete; 1561 } 1562 if (ep->datalen == 0) { 1563 if (ep->need_short_xfer) { 1564 ep->need_short_xfer = 0; 1565 /* one more data phase */ 1566 if (xfer->ux_request.bmRequestType & UT_READ) { 1567 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1568 (uintptr_t)xfer, 0, 0, 0); 1569 motg_device_ctrl_read(xfer); 1570 return; 1571 } /* else fall back to DATA_OUT */ 1572 } else { 1573 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh 0x%jx", 1574 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1575 0, 0); 1576 ep->phase = STATUS_IN; 1577 UWRITE1(sc, MUSB2_REG_RXCSRH, 1578 UREAD1(sc, MUSB2_REG_RXCSRH) | 1579 MUSB2_MASK_CSR0H_PING_DIS); 1580 motg_setup_endpoint_rx(xfer); 1581 UWRITE1(sc, MUSB2_REG_TXCSRL, 1582 MUSB2_MASK_CSR0L_STATUSPKT | 1583 MUSB2_MASK_CSR0L_REQPKT); 1584 return; 1585 } 1586 } 1587 if (xfer->ux_request.bmRequestType & UT_READ) { 1588 motg_device_ctrl_read(xfer); 1589 return; 1590 } 1591 /* setup a dataout phase */ 1592 datalen = uimin(ep->datalen, 1593 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1594 ep->phase = DATA_OUT; 1595 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh 0x%jx", (uintptr_t)xfer, 1596 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1597 if (datalen) { 1598 data = ep->data; 1599 ep->data += datalen; 1600 ep->datalen -= datalen; 1601 xfer->ux_actlen += datalen; 1602 if (((vaddr_t)data & 0x3) == 0 && 1603 (datalen >> 2) > 0) { 1604 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1605 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1606 data += (datalen & ~0x3); 1607 datalen -= (datalen & ~0x3); 1608 } 1609 if (datalen) { 1610 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1611 MUSB2_REG_EPFIFO(0), data, datalen); 1612 } 1613 } 1614 /* send data */ 1615 motg_setup_endpoint_tx(xfer); 1616 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1617 return; 1618 1619 complete: 1620 ep->phase = IDLE; 1621 ep->xfer = NULL; 1622 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1623 KASSERT(new_status != USBD_IN_PROGRESS); 1624 xfer->ux_status = new_status; 1625 usb_transfer_complete(xfer); 1626 } 1627 motg_device_ctrl_start1(sc); 1628 } 1629 1630 /* Abort a device control request. */ 1631 void 1632 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1633 { 1634 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1635 1636 motg_device_xfer_abort(xfer); 1637 } 1638 1639 /* Close a device control pipe */ 1640 void 1641 motg_device_ctrl_close(struct usbd_pipe *pipe) 1642 { 1643 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1644 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1645 struct motg_pipe *otgpipeiter; 1646 1647 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1648 1649 KASSERT(mutex_owned(&sc->sc_lock)); 1650 KASSERT(otgpipe->hw_ep->xfer == NULL || 1651 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1652 1653 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1654 if (otgpipeiter == otgpipe) { 1655 /* remove from list */ 1656 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1657 motg_pipe, ep_pipe_list); 1658 otgpipe->hw_ep->refcount--; 1659 /* we're done */ 1660 return; 1661 } 1662 } 1663 panic("motg_device_ctrl_close: not found"); 1664 } 1665 1666 void 1667 motg_device_ctrl_done(struct usbd_xfer *xfer) 1668 { 1669 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1670 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1671 1672 KASSERT(otgpipe->hw_ep->xfer != xfer); 1673 } 1674 1675 static usbd_status 1676 motg_device_data_transfer(struct usbd_xfer *xfer) 1677 { 1678 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1679 usbd_status err; 1680 1681 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1682 1683 /* Insert last in queue. */ 1684 mutex_enter(&sc->sc_lock); 1685 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1686 err = usb_insert_transfer(xfer); 1687 xfer->ux_status = USBD_NOT_STARTED; 1688 mutex_exit(&sc->sc_lock); 1689 if (err) 1690 return err; 1691 1692 /* 1693 * Pipe isn't running (otherwise err would be USBD_INPROG), 1694 * so start it first. 1695 */ 1696 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1697 } 1698 1699 static usbd_status 1700 motg_device_data_start(struct usbd_xfer *xfer) 1701 { 1702 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1703 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1704 usbd_status err; 1705 1706 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1707 1708 mutex_enter(&sc->sc_lock); 1709 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1710 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1711 mutex_exit(&sc->sc_lock); 1712 if (err != USBD_IN_PROGRESS) 1713 return err; 1714 return USBD_IN_PROGRESS; 1715 } 1716 1717 static usbd_status 1718 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1719 { 1720 struct usbd_xfer *xfer = NULL; 1721 struct motg_pipe *otgpipe; 1722 usbd_status err = 0; 1723 uint32_t val __diagused; 1724 1725 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1726 1727 KASSERT(mutex_owned(&sc->sc_lock)); 1728 if (sc->sc_dying) 1729 return USBD_IOERROR; 1730 1731 if (!sc->sc_connected) 1732 return USBD_IOERROR; 1733 1734 if (ep->xfer != NULL) { 1735 err = USBD_IN_PROGRESS; 1736 goto end; 1737 } 1738 /* locate the first pipe with work to do */ 1739 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1740 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1741 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1742 (uintptr_t)otgpipe, (uintptr_t)xfer, 1743 (xfer != NULL) ? xfer->ux_status : 0, 0); 1744 if (xfer != NULL) { 1745 /* move this pipe to the end of the list */ 1746 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1747 motg_pipe, ep_pipe_list); 1748 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1749 otgpipe, ep_pipe_list); 1750 break; 1751 } 1752 } 1753 if (xfer == NULL) { 1754 err = USBD_NOT_STARTED; 1755 goto end; 1756 } 1757 xfer->ux_status = USBD_IN_PROGRESS; 1758 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1759 KASSERT(otgpipe->hw_ep == ep); 1760 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1761 // KASSERT(xfer->ux_actlen == 0); 1762 xfer->ux_actlen = 0; 1763 1764 ep->xfer = xfer; 1765 ep->datalen = xfer->ux_length; 1766 KASSERT(ep->datalen > 0); 1767 ep->data = xfer->ux_buf; 1768 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1769 (ep->datalen % 64) == 0) 1770 ep->need_short_xfer = 1; 1771 else 1772 ep->need_short_xfer = 0; 1773 /* now we need send this request */ 1774 DPRINTFN(MD_BULK, 1775 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1776 "xfer %#jx in data %#jx len %jd short %jd" : 1777 "xfer %#jx out data %#jx len %jd short %jd", 1778 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1779 ep->need_short_xfer); 1780 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1781 xfer->ux_pipe->up_dev->ud_speed, 1782 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1783 KASSERT(ep->phase == IDLE); 1784 /* select endpoint */ 1785 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1786 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1787 == UE_DIR_IN) { 1788 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1789 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1790 motg_device_data_read(xfer); 1791 } else { 1792 ep->phase = DATA_OUT; 1793 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1794 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1795 motg_device_data_write(xfer); 1796 } 1797 end: 1798 if (err) 1799 return err; 1800 1801 return USBD_IN_PROGRESS; 1802 } 1803 1804 static void 1805 motg_device_data_read(struct usbd_xfer *xfer) 1806 { 1807 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1808 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1809 uint32_t val; 1810 1811 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1812 1813 KASSERT(mutex_owned(&sc->sc_lock)); 1814 /* assume endpoint already selected */ 1815 motg_setup_endpoint_rx(xfer); 1816 /* Max packet size */ 1817 UWRITE2(sc, MUSB2_REG_RXMAXP, 1818 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1819 /* Data Toggle */ 1820 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1821 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1822 if (otgpipe->nexttoggle) 1823 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1824 else 1825 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1826 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1827 1828 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh 0x%jx", 1829 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1830 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1831 /* start transaction */ 1832 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1833 otgpipe->hw_ep->phase = DATA_IN; 1834 } 1835 1836 static void 1837 motg_device_data_write(struct usbd_xfer *xfer) 1838 { 1839 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1840 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1841 struct motg_hw_ep *ep = otgpipe->hw_ep; 1842 int datalen; 1843 char *data; 1844 uint32_t val; 1845 1846 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1847 1848 KASSERT(xfer!=NULL); 1849 KASSERT(mutex_owned(&sc->sc_lock)); 1850 1851 datalen = uimin(ep->datalen, 1852 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1853 ep->phase = DATA_OUT; 1854 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh 0x%jx", 1855 (uintptr_t)xfer, ep->ep_number, datalen, 1856 UREAD1(sc, MUSB2_REG_TXCSRH)); 1857 1858 /* assume endpoint already selected */ 1859 /* write data to fifo */ 1860 data = ep->data; 1861 ep->data += datalen; 1862 ep->datalen -= datalen; 1863 xfer->ux_actlen += datalen; 1864 if (((vaddr_t)data & 0x3) == 0 && 1865 (datalen >> 2) > 0) { 1866 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1867 MUSB2_REG_EPFIFO(ep->ep_number), 1868 (void *)data, datalen >> 2); 1869 data += (datalen & ~0x3); 1870 datalen -= (datalen & ~0x3); 1871 } 1872 if (datalen) { 1873 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1874 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1875 } 1876 1877 motg_setup_endpoint_tx(xfer); 1878 /* Max packet size */ 1879 UWRITE2(sc, MUSB2_REG_TXMAXP, 1880 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1881 /* Data Toggle */ 1882 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1883 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1884 if (otgpipe->nexttoggle) 1885 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1886 else 1887 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1888 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1889 1890 /* start transaction */ 1891 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1892 } 1893 1894 static void 1895 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1896 { 1897 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1898 struct usbd_xfer *xfer = ep->xfer; 1899 uint8_t csr; 1900 int datalen, max_datalen; 1901 char *data; 1902 bool got_short; 1903 usbd_status new_status = USBD_IN_PROGRESS; 1904 1905 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1906 1907 KASSERT(mutex_owned(&sc->sc_lock)); 1908 KASSERT(ep->ep_number == epnumber); 1909 1910 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1911 /* select endpoint */ 1912 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1913 1914 /* read out FIFO status */ 1915 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1916 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr ,0 ,0); 1917 1918 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1919 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1920 return; 1921 1922 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1923 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1924 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1925 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1926 1927 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1928 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1929 new_status = USBD_TIMEOUT; /* XXX */ 1930 goto complete; 1931 } 1932 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1933 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1934 new_status = USBD_STALLED; 1935 else 1936 new_status = USBD_IOERROR; 1937 /* clear status */ 1938 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1939 goto complete; 1940 } 1941 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1942 1943 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 1944 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1945 goto complete; 1946 } 1947 1948 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1949 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 1950 1951 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1952 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 1953 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 1954 max_datalen = uimin( 1955 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 1956 ep->datalen); 1957 if (datalen > max_datalen) { 1958 new_status = USBD_IOERROR; 1959 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1960 goto complete; 1961 } 1962 got_short = (datalen < max_datalen); 1963 if (datalen > 0) { 1964 KASSERT(ep->phase == DATA_IN); 1965 data = ep->data; 1966 ep->data += datalen; 1967 ep->datalen -= datalen; 1968 xfer->ux_actlen += datalen; 1969 if (((vaddr_t)data & 0x3) == 0 && 1970 (datalen >> 2) > 0) { 1971 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 1972 (uintptr_t)data, datalen, 0, 0); 1973 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1974 MUSB2_REG_EPFIFO(ep->ep_number), 1975 (void *)data, datalen >> 2); 1976 data += (datalen & ~0x3); 1977 datalen -= (datalen & ~0x3); 1978 } 1979 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 1980 datalen ,0 ,0); 1981 if (datalen) { 1982 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1983 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1984 } 1985 } 1986 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1987 KASSERT(ep->phase == DATA_IN); 1988 if (got_short || (ep->datalen == 0)) { 1989 if (ep->need_short_xfer == 0) { 1990 new_status = USBD_NORMAL_COMPLETION; 1991 goto complete; 1992 } 1993 ep->need_short_xfer = 0; 1994 } 1995 motg_device_data_read(xfer); 1996 return; 1997 complete: 1998 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 1999 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2000 ep->phase = IDLE; 2001 ep->xfer = NULL; 2002 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2003 KASSERT(new_status != USBD_IN_PROGRESS); 2004 xfer->ux_status = new_status; 2005 usb_transfer_complete(xfer); 2006 } 2007 motg_device_data_start1(sc, ep); 2008 } 2009 2010 static void 2011 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2012 { 2013 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2014 struct usbd_xfer *xfer = ep->xfer; 2015 uint8_t csr; 2016 struct motg_pipe *otgpipe; 2017 usbd_status new_status = USBD_IN_PROGRESS; 2018 2019 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2020 2021 KASSERT(mutex_owned(&sc->sc_lock)); 2022 KASSERT(ep->ep_number == epnumber); 2023 2024 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2025 /* select endpoint */ 2026 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2027 2028 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2029 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr, 0, 0); 2030 2031 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2032 /* command not accepted */ 2033 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2034 new_status = USBD_STALLED; 2035 else 2036 new_status = USBD_IOERROR; 2037 /* clear status */ 2038 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2039 goto complete; 2040 } 2041 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2042 new_status = USBD_TIMEOUT; /* XXX */ 2043 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2044 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2045 /* flush fifo */ 2046 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2047 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2048 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2049 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2050 delay(1000); 2051 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2052 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR 0x%jx", 2053 epnumber, csr, 0, 0); 2054 } 2055 goto complete; 2056 } 2057 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2058 /* data still not sent */ 2059 return; 2060 } 2061 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2062 goto complete; 2063 KASSERT(ep->phase == DATA_OUT); 2064 2065 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2066 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2067 2068 if (ep->datalen == 0) { 2069 if (ep->need_short_xfer) { 2070 ep->need_short_xfer = 0; 2071 /* one more data phase */ 2072 } else { 2073 new_status = USBD_NORMAL_COMPLETION; 2074 goto complete; 2075 } 2076 } 2077 motg_device_data_write(xfer); 2078 return; 2079 2080 complete: 2081 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2082 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2083 KASSERTMSG(xfer && xfer->ux_status == USBD_IN_PROGRESS && 2084 ep->phase == DATA_OUT, "xfer %p status %d phase %d", 2085 xfer, xfer->ux_status, ep->phase); 2086 ep->phase = IDLE; 2087 ep->xfer = NULL; 2088 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2089 KASSERT(new_status != USBD_IN_PROGRESS); 2090 xfer->ux_status = new_status; 2091 usb_transfer_complete(xfer); 2092 } 2093 motg_device_data_start1(sc, ep); 2094 } 2095 2096 /* Abort a device control request. */ 2097 void 2098 motg_device_data_abort(struct usbd_xfer *xfer) 2099 { 2100 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2101 KASSERT(mutex_owned(&sc->sc_lock)); 2102 2103 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2104 2105 motg_device_xfer_abort(xfer); 2106 } 2107 2108 /* Close a device control pipe */ 2109 void 2110 motg_device_data_close(struct usbd_pipe *pipe) 2111 { 2112 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2113 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2114 struct motg_pipe *otgpipeiter; 2115 2116 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2117 2118 KASSERT(mutex_owned(&sc->sc_lock)); 2119 KASSERT(otgpipe->hw_ep->xfer == NULL || 2120 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2121 2122 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2123 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2124 if (otgpipeiter == otgpipe) { 2125 /* remove from list */ 2126 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2127 motg_pipe, ep_pipe_list); 2128 otgpipe->hw_ep->refcount--; 2129 /* we're done */ 2130 return; 2131 } 2132 } 2133 panic("motg_device_data_close: not found"); 2134 } 2135 2136 void 2137 motg_device_data_done(struct usbd_xfer *xfer) 2138 { 2139 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2140 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2141 2142 KASSERT(otgpipe->hw_ep->xfer != xfer); 2143 } 2144 2145 void 2146 motg_device_clear_toggle(struct usbd_pipe *pipe) 2147 { 2148 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2149 otgpipe->nexttoggle = 0; 2150 } 2151 2152 /* Abort a device control request. */ 2153 static void 2154 motg_device_xfer_abort(struct usbd_xfer *xfer) 2155 { 2156 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2157 uint8_t csr; 2158 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2159 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2160 2161 KASSERT(mutex_owned(&sc->sc_lock)); 2162 ASSERT_SLEEPABLE(); 2163 2164 /* 2165 * We are synchronously aborting. Try to stop the 2166 * callout and task, but if we can't, wait for them to 2167 * complete. 2168 */ 2169 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2170 usb_rem_task_wait(xfer->ux_pipe->up_dev, &xfer->ux_aborttask, 2171 USB_TASKQ_HC, &sc->sc_lock); 2172 2173 /* 2174 * The xfer cannot have been cancelled already. It is the 2175 * responsibility of the caller of usbd_abort_pipe not to try 2176 * to abort a pipe multiple times, whether concurrently or 2177 * sequentially. 2178 */ 2179 KASSERT(xfer->ux_status != USBD_CANCELLED); 2180 2181 /* If anyone else beat us, we're done. */ 2182 if (xfer->ux_status != USBD_IN_PROGRESS) 2183 return; 2184 2185 /* We beat everyone else. Claim the status. */ 2186 xfer->ux_status = USBD_CANCELLED; 2187 2188 /* 2189 * If we're dying, skip the hardware action and just notify the 2190 * software that we're done. 2191 */ 2192 if (sc->sc_dying) { 2193 goto dying; 2194 } 2195 2196 if (otgpipe->hw_ep->xfer == xfer) { 2197 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2198 otgpipe->hw_ep->xfer = NULL; 2199 if (otgpipe->hw_ep->ep_number > 0) { 2200 /* select endpoint */ 2201 UWRITE1(sc, MUSB2_REG_EPINDEX, 2202 otgpipe->hw_ep->ep_number); 2203 if (otgpipe->hw_ep->phase == DATA_OUT) { 2204 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2205 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2206 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2207 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2208 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2209 } 2210 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2211 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2212 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2213 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2214 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2215 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2216 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2217 } 2218 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2219 } 2220 otgpipe->hw_ep->phase = IDLE; 2221 } 2222 } 2223 dying: 2224 usb_transfer_complete(xfer); 2225 KASSERT(mutex_owned(&sc->sc_lock)); 2226 } 2227
Indexes created Fri Sep 26 08:10:20 GMT 2025