motg.c revision 1.3
1 /* $NetBSD: motg.c,v 1.3 2014/07/19 22:08:54 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.3 2014/07/19 22:08:54 bouyer Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/device.h> 50 #include <sys/select.h> 51 #include <sys/extent.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/motgreg.h> 66 #include <dev/usb/motgvar.h> 67 #include <dev/usb/usbroothub_subr.h> 68 69 #define MOTG_DEBUG 70 #ifdef MOTG_DEBUG 71 #define DPRINTF(x) if (motgdebug) printf x 72 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 73 #define MD_ROOT 0x0002 74 #define MD_CTRL 0x0004 75 #define MD_BULK 0x0008 76 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 77 int motgdebug = 0; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 /* various timeouts, for various speeds */ 84 /* control NAK timeouts */ 85 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 86 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 87 88 /* intr/iso polling intervals */ 89 #define POLL_TO 100 /* 100 frames, about 0.1s */ 90 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 91 92 /* bulk NAK timeouts */ 93 #define NAK_TO_BULK 0 /* disabled */ 94 #define NAK_TO_BULK_HIGH 0 95 96 static void motg_hub_change(struct motg_softc *); 97 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 98 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 99 static void motg_root_ctrl_abort(usbd_xfer_handle); 100 static void motg_root_ctrl_close(usbd_pipe_handle); 101 static void motg_root_ctrl_done(usbd_xfer_handle); 102 103 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 104 static usbd_status motg_root_intr_start(usbd_xfer_handle); 105 static void motg_root_intr_abort(usbd_xfer_handle); 106 static void motg_root_intr_close(usbd_pipe_handle); 107 static void motg_root_intr_done(usbd_xfer_handle); 108 109 static usbd_status motg_open(usbd_pipe_handle); 110 static void motg_poll(struct usbd_bus *); 111 static void motg_softintr(void *); 112 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 113 static void motg_freem(struct usbd_bus *, usb_dma_t *); 114 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 115 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 116 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 117 static void motg_noop(usbd_pipe_handle pipe); 118 static usbd_status motg_portreset(struct motg_softc*); 119 120 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 121 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 122 static void motg_device_ctrl_abort(usbd_xfer_handle); 123 static void motg_device_ctrl_close(usbd_pipe_handle); 124 static void motg_device_ctrl_done(usbd_xfer_handle); 125 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 126 static void motg_device_ctrl_read(usbd_xfer_handle); 127 static void motg_device_ctrl_intr_rx(struct motg_softc *); 128 static void motg_device_ctrl_intr_tx(struct motg_softc *); 129 130 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 131 static usbd_status motg_device_data_start(usbd_xfer_handle); 132 static usbd_status motg_device_data_start1(struct motg_softc *, 133 struct motg_hw_ep *); 134 static void motg_device_data_abort(usbd_xfer_handle); 135 static void motg_device_data_close(usbd_pipe_handle); 136 static void motg_device_data_done(usbd_xfer_handle); 137 static void motg_device_intr_rx(struct motg_softc *, int); 138 static void motg_device_intr_tx(struct motg_softc *, int); 139 static void motg_device_data_read(usbd_xfer_handle); 140 static void motg_device_data_write(usbd_xfer_handle); 141 142 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 143 static void motg_device_clear_toggle(usbd_pipe_handle); 144 static void motg_device_xfer_abort(usbd_xfer_handle); 145 146 #define MOTG_INTR_ENDPT 1 147 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 148 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 149 #define UWRITE1(sc, r, x) \ 150 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 151 } while (/*CONSTCOND*/0) 152 #define UWRITE2(sc, r, x) \ 153 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 154 } while (/*CONSTCOND*/0) 155 #define UWRITE4(sc, r, x) \ 156 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 157 } while (/*CONSTCOND*/0) 158 159 static __inline uint32_t 160 UREAD1(struct motg_softc *sc, bus_size_t r) 161 { 162 163 UBARR(sc); 164 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 165 } 166 static __inline uint32_t 167 UREAD2(struct motg_softc *sc, bus_size_t r) 168 { 169 170 UBARR(sc); 171 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 172 } 173 static __inline uint32_t 174 UREAD4(struct motg_softc *sc, bus_size_t r) 175 { 176 177 UBARR(sc); 178 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 179 } 180 181 static void 182 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 183 { 184 uint8_t val; 185 186 val = UREAD1(sc, MUSB2_REG_POWER); 187 if (on) 188 val |= MUSB2_MASK_SOFTC; 189 else 190 val &= ~MUSB2_MASK_SOFTC; 191 192 UWRITE1(sc, MUSB2_REG_POWER, val); 193 } 194 195 const struct usbd_bus_methods motg_bus_methods = { 196 .open_pipe = motg_open, 197 .soft_intr = motg_softintr, 198 .do_poll = motg_poll, 199 .allocm = motg_allocm, 200 .freem = motg_freem, 201 .allocx = motg_allocx, 202 .freex = motg_freex, 203 .get_lock = motg_get_lock, 204 .new_device = NULL, 205 }; 206 207 const struct usbd_pipe_methods motg_root_ctrl_methods = { 208 .transfer = motg_root_ctrl_transfer, 209 .start = motg_root_ctrl_start, 210 .abort = motg_root_ctrl_abort, 211 .close = motg_root_ctrl_close, 212 .cleartoggle = motg_noop, 213 .done = motg_root_ctrl_done, 214 }; 215 216 const struct usbd_pipe_methods motg_root_intr_methods = { 217 .transfer = motg_root_intr_transfer, 218 .start = motg_root_intr_start, 219 .abort = motg_root_intr_abort, 220 .close = motg_root_intr_close, 221 .cleartoggle = motg_noop, 222 .done = motg_root_intr_done, 223 }; 224 225 const struct usbd_pipe_methods motg_device_ctrl_methods = { 226 .transfer = motg_device_ctrl_transfer, 227 .start = motg_device_ctrl_start, 228 .abort = motg_device_ctrl_abort, 229 .close = motg_device_ctrl_close, 230 .cleartoggle = motg_noop, 231 .done = motg_device_ctrl_done, 232 }; 233 234 const struct usbd_pipe_methods motg_device_data_methods = { 235 .transfer = motg_device_data_transfer, 236 .start = motg_device_data_start, 237 .abort = motg_device_data_abort, 238 .close = motg_device_data_close, 239 .cleartoggle = motg_device_clear_toggle, 240 .done = motg_device_data_done, 241 }; 242 243 usbd_status 244 motg_init(struct motg_softc *sc) 245 { 246 uint32_t nrx, ntx, val; 247 int dynfifo; 248 int offset, i; 249 250 if (sc->sc_mode == MOTG_MODE_DEVICE) 251 return USBD_NORMAL_COMPLETION; /* not supported */ 252 253 /* disable all interrupts */ 254 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 255 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 256 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 257 /* disable pullup */ 258 259 musbotg_pull_common(sc, 0); 260 261 /* disable double packet buffering XXX what's this ? */ 262 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 263 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 264 265 /* enable HighSpeed and ISO Update flags */ 266 267 UWRITE1(sc, MUSB2_REG_POWER, 268 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 269 270 if (sc->sc_mode == MOTG_MODE_DEVICE) { 271 /* clear Session bit, if set */ 272 val = UREAD1(sc, MUSB2_REG_DEVCTL); 273 val &= ~MUSB2_MASK_SESS; 274 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 275 } else { 276 /* Enter session for Host mode */ 277 val = UREAD1(sc, MUSB2_REG_DEVCTL); 278 val |= MUSB2_MASK_SESS; 279 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 280 } 281 delay(1000); 282 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 283 284 /* disable testmode */ 285 286 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 287 288 /* set default value */ 289 290 UWRITE1(sc, MUSB2_REG_MISC, 0); 291 292 /* select endpoint index 0 */ 293 294 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 295 296 /* read out number of endpoints */ 297 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 298 299 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 300 301 /* these numbers exclude the control endpoint */ 302 303 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 304 305 sc->sc_ep_max = MAX(nrx, ntx); 306 if (sc->sc_ep_max == 0) { 307 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 308 return USBD_INVAL; 309 } 310 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 311 /* read out configuration data */ 312 val = UREAD1(sc, MUSB2_REG_CONFDATA); 313 314 DPRINTF(("Config Data: 0x%02x\n", val)); 315 316 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 317 318 if (dynfifo) { 319 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 320 "assuming 16Kbytes of FIFO RAM\n"); 321 } 322 323 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 324 325 /* initialise endpoint profiles */ 326 sc->sc_in_ep[0].ep_fifo_size = 64; 327 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 328 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 329 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 330 offset = 64; 331 332 for (i = 1; i <= sc->sc_ep_max; i++) { 333 int fiforx_size, fifotx_size, fifo_size; 334 335 /* select endpoint */ 336 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 337 338 val = UREAD1(sc, MUSB2_REG_FSIZE); 339 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 340 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 341 342 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 343 i, fifotx_size, fiforx_size, dynfifo)); 344 345 if (dynfifo) { 346 if (i < 3) { 347 fifo_size = 12; /* 4K */ 348 } else if (i < 10) { 349 fifo_size = 10; /* 1K */ 350 } else { 351 fifo_size = 7; /* 128 bytes */ 352 } 353 if (fiforx_size && (i <= nrx)) { 354 fiforx_size = fifo_size; 355 if (fifo_size > 7) { 356 #if 0 357 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 358 MUSB2_VAL_FIFOSZ(fifo_size) | 359 MUSB2_MASK_FIFODB); 360 #else 361 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 362 MUSB2_VAL_FIFOSZ(fifo_size)); 363 #endif 364 } else { 365 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 366 MUSB2_VAL_FIFOSZ(fifo_size)); 367 } 368 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 369 offset >> 3); 370 offset += (1 << fiforx_size); 371 } 372 if (fifotx_size && (i <= ntx)) { 373 fifotx_size = fifo_size; 374 if (fifo_size > 7) { 375 #if 0 376 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 377 MUSB2_VAL_FIFOSZ(fifo_size) | 378 MUSB2_MASK_FIFODB); 379 #else 380 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 381 MUSB2_VAL_FIFOSZ(fifo_size)); 382 #endif 383 } else { 384 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 385 MUSB2_VAL_FIFOSZ(fifo_size)); 386 } 387 388 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 389 offset >> 3); 390 391 offset += (1 << fifotx_size); 392 } 393 } 394 if (fiforx_size && (i <= nrx)) { 395 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 396 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 397 } 398 if (fifotx_size && (i <= ntx)) { 399 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 400 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 401 } 402 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 403 } 404 405 406 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 407 408 /* turn on default interrupts */ 409 410 if (sc->sc_mode == MOTG_MODE_HOST) { 411 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 412 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 413 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 414 } else 415 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 418 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 421 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 422 423 /* Set up the bus struct. */ 424 sc->sc_bus.methods = &motg_bus_methods; 425 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 426 sc->sc_bus.usbrev = USBREV_2_0; 427 sc->sc_bus.hci_private = sc; 428 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 429 "Mentor Graphics"); 430 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 431 return USBD_NORMAL_COMPLETION; 432 } 433 434 static int 435 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 436 { 437 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 438 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 439 struct motg_hw_ep *ep; 440 int i, size; 441 442 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 443 sc->sc_in_ep : sc->sc_out_ep; 444 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 445 446 for (i = sc->sc_ep_max; i >= 1; i--) { 447 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 448 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 449 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 450 if (ep[i].ep_fifo_size >= size) { 451 /* found a suitable endpoint */ 452 otgpipe->hw_ep = &ep[i]; 453 mutex_enter(&sc->sc_lock); 454 if (otgpipe->hw_ep->refcount > 0) { 455 /* no luck, try next */ 456 mutex_exit(&sc->sc_lock); 457 otgpipe->hw_ep = NULL; 458 } else { 459 otgpipe->hw_ep->refcount++; 460 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 461 otgpipe, ep_pipe_list); 462 mutex_exit(&sc->sc_lock); 463 return 0; 464 } 465 } 466 } 467 return -1; 468 } 469 470 /* Open a new pipe. */ 471 usbd_status 472 motg_open(usbd_pipe_handle pipe) 473 { 474 struct motg_softc *sc = pipe->device->bus->hci_private; 475 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 476 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 477 478 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 479 pipe, pipe->device->address, 480 ed->bEndpointAddress, sc->sc_root_addr)); 481 482 if (sc->sc_dying) 483 return USBD_IOERROR; 484 485 /* toggle state needed for bulk endpoints */ 486 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 487 488 if (pipe->device->address == sc->sc_root_addr) { 489 switch (ed->bEndpointAddress) { 490 case USB_CONTROL_ENDPOINT: 491 pipe->methods = &motg_root_ctrl_methods; 492 break; 493 case UE_DIR_IN | MOTG_INTR_ENDPT: 494 pipe->methods = &motg_root_intr_methods; 495 break; 496 default: 497 return (USBD_INVAL); 498 } 499 } else { 500 switch (ed->bmAttributes & UE_XFERTYPE) { 501 case UE_CONTROL: 502 pipe->methods = &motg_device_ctrl_methods; 503 /* always use sc_in_ep[0] for in and out */ 504 otgpipe->hw_ep = &sc->sc_in_ep[0]; 505 mutex_enter(&sc->sc_lock); 506 otgpipe->hw_ep->refcount++; 507 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 508 otgpipe, ep_pipe_list); 509 mutex_exit(&sc->sc_lock); 510 break; 511 case UE_BULK: 512 case UE_INTERRUPT: 513 DPRINTFN(MD_BULK, 514 ("new %s %s pipe wMaxPacketSize %d\n", 515 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 516 "bulk" : "interrupt", 517 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 518 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 519 if (motg_select_ep(sc, pipe) != 0) 520 goto bad; 521 KASSERT(otgpipe->hw_ep != NULL); 522 pipe->methods = &motg_device_data_methods; 523 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 524 break; 525 default: 526 goto bad; 527 #ifdef notyet 528 case UE_ISOCHRONOUS: 529 ... 530 break; 531 #endif /* notyet */ 532 } 533 } 534 return (USBD_NORMAL_COMPLETION); 535 536 bad: 537 return (USBD_NOMEM); 538 } 539 540 void 541 motg_softintr(void *v) 542 { 543 struct usbd_bus *bus = v; 544 struct motg_softc *sc = bus->hci_private; 545 uint16_t rx_status, tx_status; 546 uint8_t ctrl_status; 547 uint32_t val; 548 int i; 549 550 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 551 552 DPRINTFN(MD_ROOT | MD_CTRL, 553 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 554 555 mutex_spin_enter(&sc->sc_intr_lock); 556 rx_status = sc->sc_intr_rx_ep; 557 sc->sc_intr_rx_ep = 0; 558 tx_status = sc->sc_intr_tx_ep; 559 sc->sc_intr_tx_ep = 0; 560 ctrl_status = sc->sc_intr_ctrl; 561 sc->sc_intr_ctrl = 0; 562 mutex_spin_exit(&sc->sc_intr_lock); 563 564 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 565 566 if (ctrl_status & (MUSB2_MASK_IRESET | 567 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 568 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 569 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 570 ctrl_status)); 571 572 if (ctrl_status & MUSB2_MASK_IRESET) { 573 sc->sc_isreset = 1; 574 sc->sc_port_suspended = 0; 575 sc->sc_port_suspended_change = 1; 576 sc->sc_connected_changed = 1; 577 sc->sc_port_enabled = 1; 578 579 val = UREAD1(sc, MUSB2_REG_POWER); 580 if (val & MUSB2_MASK_HSMODE) 581 sc->sc_high_speed = 1; 582 else 583 sc->sc_high_speed = 0; 584 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 585 sc->sc_high_speed)); 586 587 /* turn off interrupts */ 588 val = MUSB2_MASK_IRESET; 589 val &= ~MUSB2_MASK_IRESUME; 590 val |= MUSB2_MASK_ISUSP; 591 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 592 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 593 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 594 } 595 if (ctrl_status & MUSB2_MASK_IRESUME) { 596 if (sc->sc_port_suspended) { 597 sc->sc_port_suspended = 0; 598 sc->sc_port_suspended_change = 1; 599 val = UREAD1(sc, MUSB2_REG_INTUSBE); 600 /* disable resume interrupt */ 601 val &= ~MUSB2_MASK_IRESUME; 602 /* enable suspend interrupt */ 603 val |= MUSB2_MASK_ISUSP; 604 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 605 } 606 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 607 if (!sc->sc_port_suspended) { 608 sc->sc_port_suspended = 1; 609 sc->sc_port_suspended_change = 1; 610 611 val = UREAD1(sc, MUSB2_REG_INTUSBE); 612 /* disable suspend interrupt */ 613 val &= ~MUSB2_MASK_ISUSP; 614 /* enable resume interrupt */ 615 val |= MUSB2_MASK_IRESUME; 616 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 617 } 618 } 619 if (ctrl_status & MUSB2_MASK_ICONN) { 620 sc->sc_connected = 1; 621 sc->sc_connected_changed = 1; 622 sc->sc_isreset = 1; 623 sc->sc_port_enabled = 1; 624 } else if (ctrl_status & MUSB2_MASK_IDISC) { 625 sc->sc_connected = 0; 626 sc->sc_connected_changed = 1; 627 sc->sc_isreset = 0; 628 sc->sc_port_enabled = 0; 629 } 630 631 /* complete root HUB interrupt endpoint */ 632 633 motg_hub_change(sc); 634 } 635 /* 636 * read in interrupt status and mix with the status we 637 * got from the wrapper 638 */ 639 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 640 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 641 642 if (rx_status & 0x01) 643 panic("ctrl_rx"); 644 if (tx_status & 0x01) 645 motg_device_ctrl_intr_tx(sc); 646 for (i = 1; i <= sc->sc_ep_max; i++) { 647 if (rx_status & (0x01 << i)) 648 motg_device_intr_rx(sc, i); 649 if (tx_status & (0x01 << i)) 650 motg_device_intr_tx(sc, i); 651 } 652 return; 653 } 654 655 void 656 motg_poll(struct usbd_bus *bus) 657 { 658 struct motg_softc *sc = bus->hci_private; 659 660 sc->sc_intr_poll(sc->sc_intr_poll_arg); 661 mutex_enter(&sc->sc_lock); 662 motg_softintr(bus); 663 mutex_exit(&sc->sc_lock); 664 } 665 666 int 667 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 668 uint8_t ctrl) 669 { 670 KASSERT(mutex_owned(&sc->sc_intr_lock)); 671 sc->sc_intr_tx_ep = tx_ep; 672 sc->sc_intr_rx_ep = rx_ep; 673 sc->sc_intr_ctrl = ctrl; 674 675 if (!sc->sc_bus.use_polling) { 676 sc->sc_bus.no_intrs++; 677 usb_schedsoftintr(&sc->sc_bus); 678 } 679 return 1; 680 } 681 682 int 683 motg_intr_vbus(struct motg_softc *sc, int vbus) 684 { 685 uint8_t val; 686 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 687 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 688 /* try to re-enter session for Host mode */ 689 val = UREAD1(sc, MUSB2_REG_DEVCTL); 690 val |= MUSB2_MASK_SESS; 691 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 692 } 693 return 1; 694 } 695 696 usbd_status 697 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 698 { 699 struct motg_softc *sc = bus->hci_private; 700 usbd_status status; 701 702 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 703 if (status == USBD_NOMEM) 704 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 705 return status; 706 } 707 708 void 709 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 710 { 711 if (dma->block->flags & USB_DMA_RESERVE) { 712 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 713 dma); 714 return; 715 } 716 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 717 } 718 719 usbd_xfer_handle 720 motg_allocx(struct usbd_bus *bus) 721 { 722 struct motg_softc *sc = bus->hci_private; 723 usbd_xfer_handle xfer; 724 725 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 726 if (xfer != NULL) { 727 memset(xfer, 0, sizeof(struct motg_xfer)); 728 UXFER(xfer)->sc = sc; 729 #ifdef DIAGNOSTIC 730 // XXX UXFER(xfer)->iinfo.isdone = 1; 731 xfer->busy_free = XFER_BUSY; 732 #endif 733 } 734 return (xfer); 735 } 736 737 void 738 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 739 { 740 struct motg_softc *sc = bus->hci_private; 741 742 #ifdef DIAGNOSTIC 743 if (xfer->busy_free != XFER_BUSY) { 744 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 745 xfer->busy_free); 746 } 747 xfer->busy_free = XFER_FREE; 748 #endif 749 pool_cache_put(sc->sc_xferpool, xfer); 750 } 751 752 static void 753 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 754 { 755 struct motg_softc *sc = bus->hci_private; 756 757 *lock = &sc->sc_lock; 758 } 759 760 /* 761 * Data structures and routines to emulate the root hub. 762 */ 763 usb_device_descriptor_t motg_devd = { 764 USB_DEVICE_DESCRIPTOR_SIZE, 765 UDESC_DEVICE, /* type */ 766 {0x00, 0x01}, /* USB version */ 767 UDCLASS_HUB, /* class */ 768 UDSUBCLASS_HUB, /* subclass */ 769 UDPROTO_FSHUB, /* protocol */ 770 64, /* max packet */ 771 {0},{0},{0x00,0x01}, /* device id */ 772 1,2,0, /* string indicies */ 773 1 /* # of configurations */ 774 }; 775 776 const usb_config_descriptor_t motg_confd = { 777 USB_CONFIG_DESCRIPTOR_SIZE, 778 UDESC_CONFIG, 779 {USB_CONFIG_DESCRIPTOR_SIZE + 780 USB_INTERFACE_DESCRIPTOR_SIZE + 781 USB_ENDPOINT_DESCRIPTOR_SIZE}, 782 1, 783 1, 784 0, 785 UC_ATTR_MBO | UC_SELF_POWERED, 786 0 /* max power */ 787 }; 788 789 const usb_interface_descriptor_t motg_ifcd = { 790 USB_INTERFACE_DESCRIPTOR_SIZE, 791 UDESC_INTERFACE, 792 0, 793 0, 794 1, 795 UICLASS_HUB, 796 UISUBCLASS_HUB, 797 UIPROTO_FSHUB, 798 0 799 }; 800 801 const usb_endpoint_descriptor_t motg_endpd = { 802 USB_ENDPOINT_DESCRIPTOR_SIZE, 803 UDESC_ENDPOINT, 804 UE_DIR_IN | MOTG_INTR_ENDPT, 805 UE_INTERRUPT, 806 {8}, 807 255 808 }; 809 810 const usb_hub_descriptor_t motg_hubd = { 811 USB_HUB_DESCRIPTOR_SIZE, 812 UDESC_HUB, 813 1, 814 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 815 50, /* power on to power good */ 816 0, 817 { 0x00 }, /* port is removable */ 818 { 0 }, 819 }; 820 821 /* 822 * Simulate a hardware hub by handling all the necessary requests. 823 */ 824 usbd_status 825 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 826 { 827 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 828 usbd_status err; 829 830 /* Insert last in queue. */ 831 mutex_enter(&sc->sc_lock); 832 err = usb_insert_transfer(xfer); 833 mutex_exit(&sc->sc_lock); 834 if (err) 835 return (err); 836 837 /* 838 * Pipe isn't running (otherwise err would be USBD_INPROG), 839 * so start it first. 840 */ 841 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 842 } 843 844 usbd_status 845 motg_root_ctrl_start(usbd_xfer_handle xfer) 846 { 847 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 848 usb_device_request_t *req; 849 void *buf = NULL; 850 int len, value, index, status, change, l, totlen = 0; 851 usb_port_status_t ps; 852 usbd_status err; 853 uint32_t val; 854 855 if (sc->sc_dying) 856 return (USBD_IOERROR); 857 858 #ifdef DIAGNOSTIC 859 if (!(xfer->rqflags & URQ_REQUEST)) 860 panic("motg_root_ctrl_start: not a request"); 861 #endif 862 req = &xfer->request; 863 864 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 865 req->bmRequestType, req->bRequest)); 866 867 len = UGETW(req->wLength); 868 value = UGETW(req->wValue); 869 index = UGETW(req->wIndex); 870 871 if (len != 0) 872 buf = KERNADDR(&xfer->dmabuf, 0); 873 874 #define C(x,y) ((x) | ((y) << 8)) 875 switch(C(req->bRequest, req->bmRequestType)) { 876 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 877 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 878 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 879 /* 880 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 881 * for the integrated root hub. 882 */ 883 break; 884 case C(UR_GET_CONFIG, UT_READ_DEVICE): 885 if (len > 0) { 886 *(u_int8_t *)buf = sc->sc_root_conf; 887 totlen = 1; 888 } 889 break; 890 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 891 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 892 if (len == 0) 893 break; 894 switch(value >> 8) { 895 case UDESC_DEVICE: 896 if ((value & 0xff) != 0) { 897 err = USBD_IOERROR; 898 goto ret; 899 } 900 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 901 USETW(motg_devd.idVendor, sc->sc_id_vendor); 902 memcpy(buf, &motg_devd, l); 903 break; 904 case UDESC_CONFIG: 905 if ((value & 0xff) != 0) { 906 err = USBD_IOERROR; 907 goto ret; 908 } 909 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 910 memcpy(buf, &motg_confd, l); 911 buf = (char *)buf + l; 912 len -= l; 913 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 914 totlen += l; 915 memcpy(buf, &motg_ifcd, l); 916 buf = (char *)buf + l; 917 len -= l; 918 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 919 totlen += l; 920 memcpy(buf, &motg_endpd, l); 921 break; 922 case UDESC_STRING: 923 #define sd ((usb_string_descriptor_t *)buf) 924 switch (value & 0xff) { 925 case 0: /* Language table */ 926 totlen = usb_makelangtbl(sd, len); 927 break; 928 case 1: /* Vendor */ 929 totlen = usb_makestrdesc(sd, len, 930 sc->sc_vendor); 931 break; 932 case 2: /* Product */ 933 totlen = usb_makestrdesc(sd, len, 934 "MOTG root hub"); 935 break; 936 } 937 #undef sd 938 break; 939 default: 940 err = USBD_IOERROR; 941 goto ret; 942 } 943 break; 944 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 945 if (len > 0) { 946 *(u_int8_t *)buf = 0; 947 totlen = 1; 948 } 949 break; 950 case C(UR_GET_STATUS, UT_READ_DEVICE): 951 if (len > 1) { 952 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 953 totlen = 2; 954 } 955 break; 956 case C(UR_GET_STATUS, UT_READ_INTERFACE): 957 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 958 if (len > 1) { 959 USETW(((usb_status_t *)buf)->wStatus, 0); 960 totlen = 2; 961 } 962 break; 963 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 964 if (value >= USB_MAX_DEVICES) { 965 err = USBD_IOERROR; 966 goto ret; 967 } 968 sc->sc_root_addr = value; 969 break; 970 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 971 if (value != 0 && value != 1) { 972 err = USBD_IOERROR; 973 goto ret; 974 } 975 sc->sc_root_conf = value; 976 break; 977 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 978 break; 979 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 980 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 981 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 982 err = USBD_IOERROR; 983 goto ret; 984 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 985 break; 986 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 987 break; 988 /* Hub requests */ 989 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 990 break; 991 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 992 DPRINTFN(MD_ROOT, 993 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 994 "port=%d feature=%d\n", 995 index, value)); 996 if (index != 1) { 997 err = USBD_IOERROR; 998 goto ret; 999 } 1000 switch(value) { 1001 case UHF_PORT_ENABLE: 1002 sc->sc_port_enabled = 0; 1003 break; 1004 case UHF_PORT_SUSPEND: 1005 if (sc->sc_port_suspended != 0) { 1006 val = UREAD1(sc, MUSB2_REG_POWER); 1007 val &= ~MUSB2_MASK_SUSPMODE; 1008 val |= MUSB2_MASK_RESUME; 1009 UWRITE1(sc, MUSB2_REG_POWER, val); 1010 /* wait 20 milliseconds */ 1011 usb_delay_ms(&sc->sc_bus, 20); 1012 val = UREAD1(sc, MUSB2_REG_POWER); 1013 val &= ~MUSB2_MASK_RESUME; 1014 UWRITE1(sc, MUSB2_REG_POWER, val); 1015 sc->sc_port_suspended = 0; 1016 sc->sc_port_suspended_change = 1; 1017 } 1018 break; 1019 case UHF_PORT_RESET: 1020 break; 1021 case UHF_C_PORT_CONNECTION: 1022 break; 1023 case UHF_C_PORT_ENABLE: 1024 break; 1025 case UHF_C_PORT_OVER_CURRENT: 1026 break; 1027 case UHF_C_PORT_RESET: 1028 sc->sc_isreset = 0; 1029 err = USBD_NORMAL_COMPLETION; 1030 goto ret; 1031 case UHF_PORT_POWER: 1032 /* XXX todo */ 1033 break; 1034 case UHF_PORT_CONNECTION: 1035 case UHF_PORT_OVER_CURRENT: 1036 case UHF_PORT_LOW_SPEED: 1037 case UHF_C_PORT_SUSPEND: 1038 default: 1039 err = USBD_IOERROR; 1040 goto ret; 1041 } 1042 break; 1043 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1044 err = USBD_IOERROR; 1045 goto ret; 1046 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1047 if (len == 0) 1048 break; 1049 if ((value & 0xff) != 0) { 1050 err = USBD_IOERROR; 1051 goto ret; 1052 } 1053 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1054 totlen = l; 1055 memcpy(buf, &motg_hubd, l); 1056 break; 1057 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1058 if (len != 4) { 1059 err = USBD_IOERROR; 1060 goto ret; 1061 } 1062 memset(buf, 0, len); 1063 totlen = len; 1064 break; 1065 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1066 if (index != 1) { 1067 err = USBD_IOERROR; 1068 goto ret; 1069 } 1070 if (len != 4) { 1071 err = USBD_IOERROR; 1072 goto ret; 1073 } 1074 status = change = 0; 1075 if (sc->sc_connected) 1076 status |= UPS_CURRENT_CONNECT_STATUS; 1077 if (sc->sc_connected_changed) { 1078 change |= UPS_C_CONNECT_STATUS; 1079 sc->sc_connected_changed = 0; 1080 } 1081 if (sc->sc_port_enabled) 1082 status |= UPS_PORT_ENABLED; 1083 if (sc->sc_port_enabled_changed) { 1084 change |= UPS_C_PORT_ENABLED; 1085 sc->sc_port_enabled_changed = 0; 1086 } 1087 if (sc->sc_port_suspended) 1088 status |= UPS_SUSPEND; 1089 if (sc->sc_high_speed) 1090 status |= UPS_HIGH_SPEED; 1091 status |= UPS_PORT_POWER; /* XXX */ 1092 if (sc->sc_isreset) 1093 change |= UPS_C_PORT_RESET; 1094 USETW(ps.wPortStatus, status); 1095 USETW(ps.wPortChange, change); 1096 l = min(len, sizeof ps); 1097 memcpy(buf, &ps, l); 1098 totlen = l; 1099 break; 1100 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1101 err = USBD_IOERROR; 1102 goto ret; 1103 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1104 break; 1105 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1106 if (index != 1) { 1107 err = USBD_IOERROR; 1108 goto ret; 1109 } 1110 switch(value) { 1111 case UHF_PORT_ENABLE: 1112 sc->sc_port_enabled = 1; 1113 break; 1114 case UHF_PORT_SUSPEND: 1115 if (sc->sc_port_suspended == 0) { 1116 val = UREAD1(sc, MUSB2_REG_POWER); 1117 val |= MUSB2_MASK_SUSPMODE; 1118 UWRITE1(sc, MUSB2_REG_POWER, val); 1119 /* wait 20 milliseconds */ 1120 usb_delay_ms(&sc->sc_bus, 20); 1121 sc->sc_port_suspended = 1; 1122 sc->sc_port_suspended_change = 1; 1123 } 1124 break; 1125 case UHF_PORT_RESET: 1126 err = motg_portreset(sc); 1127 goto ret; 1128 case UHF_PORT_POWER: 1129 /* XXX todo */ 1130 err = USBD_NORMAL_COMPLETION; 1131 goto ret; 1132 case UHF_C_PORT_CONNECTION: 1133 case UHF_C_PORT_ENABLE: 1134 case UHF_C_PORT_OVER_CURRENT: 1135 case UHF_PORT_CONNECTION: 1136 case UHF_PORT_OVER_CURRENT: 1137 case UHF_PORT_LOW_SPEED: 1138 case UHF_C_PORT_SUSPEND: 1139 case UHF_C_PORT_RESET: 1140 default: 1141 err = USBD_IOERROR; 1142 goto ret; 1143 } 1144 break; 1145 default: 1146 err = USBD_IOERROR; 1147 goto ret; 1148 } 1149 xfer->actlen = totlen; 1150 err = USBD_NORMAL_COMPLETION; 1151 ret: 1152 xfer->status = err; 1153 mutex_enter(&sc->sc_lock); 1154 usb_transfer_complete(xfer); 1155 mutex_exit(&sc->sc_lock); 1156 return (USBD_IN_PROGRESS); 1157 } 1158 1159 /* Abort a root control request. */ 1160 void 1161 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1162 { 1163 /* Nothing to do, all transfers are synchronous. */ 1164 } 1165 1166 /* Close the root pipe. */ 1167 void 1168 motg_root_ctrl_close(usbd_pipe_handle pipe) 1169 { 1170 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1171 } 1172 1173 void 1174 motg_root_ctrl_done(usbd_xfer_handle xfer) 1175 { 1176 } 1177 1178 /* Abort a root interrupt request. */ 1179 void 1180 motg_root_intr_abort(usbd_xfer_handle xfer) 1181 { 1182 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1183 1184 KASSERT(mutex_owned(&sc->sc_lock)); 1185 1186 sc->sc_intr_xfer = NULL; 1187 1188 if (xfer->pipe->intrxfer == xfer) { 1189 DPRINTFN(MD_ROOT, ("motg_root_intr_abort: remove\n")); 1190 xfer->pipe->intrxfer = 0; 1191 } 1192 xfer->status = USBD_CANCELLED; 1193 #ifdef DIAGNOSTIC 1194 // XXX UXFER(xfer)->iinfo.isdone = 1; 1195 #endif 1196 usb_transfer_complete(xfer); 1197 } 1198 1199 usbd_status 1200 motg_root_intr_transfer(usbd_xfer_handle xfer) 1201 { 1202 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1203 usbd_status err; 1204 1205 /* Insert last in queue. */ 1206 mutex_enter(&sc->sc_lock); 1207 err = usb_insert_transfer(xfer); 1208 mutex_exit(&sc->sc_lock); 1209 if (err) 1210 return (err); 1211 1212 /* 1213 * Pipe isn't running (otherwise err would be USBD_INPROG), 1214 * start first 1215 */ 1216 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1217 } 1218 1219 /* Start a transfer on the root interrupt pipe */ 1220 usbd_status 1221 motg_root_intr_start(usbd_xfer_handle xfer) 1222 { 1223 usbd_pipe_handle pipe = xfer->pipe; 1224 struct motg_softc *sc = pipe->device->bus->hci_private; 1225 1226 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1227 xfer, xfer->length, xfer->flags)); 1228 1229 if (sc->sc_dying) 1230 return (USBD_IOERROR); 1231 1232 sc->sc_intr_xfer = xfer; 1233 return (USBD_IN_PROGRESS); 1234 } 1235 1236 /* Close the root interrupt pipe. */ 1237 void 1238 motg_root_intr_close(usbd_pipe_handle pipe) 1239 { 1240 struct motg_softc *sc = pipe->device->bus->hci_private; 1241 1242 KASSERT(mutex_owned(&sc->sc_lock)); 1243 1244 sc->sc_intr_xfer = NULL; 1245 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1246 } 1247 1248 void 1249 motg_root_intr_done(usbd_xfer_handle xfer) 1250 { 1251 } 1252 1253 void 1254 motg_noop(usbd_pipe_handle pipe) 1255 { 1256 } 1257 1258 static usbd_status 1259 motg_portreset(struct motg_softc *sc) 1260 { 1261 uint32_t val; 1262 1263 val = UREAD1(sc, MUSB2_REG_POWER); 1264 val |= MUSB2_MASK_RESET; 1265 UWRITE1(sc, MUSB2_REG_POWER, val); 1266 /* Wait for 20 msec */ 1267 usb_delay_ms(&sc->sc_bus, 20); 1268 1269 val = UREAD1(sc, MUSB2_REG_POWER); 1270 val &= ~MUSB2_MASK_RESET; 1271 UWRITE1(sc, MUSB2_REG_POWER, val); 1272 1273 /* determine line speed */ 1274 val = UREAD1(sc, MUSB2_REG_POWER); 1275 if (val & MUSB2_MASK_HSMODE) 1276 sc->sc_high_speed = 1; 1277 else 1278 sc->sc_high_speed = 0; 1279 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1280 sc->sc_high_speed)); 1281 1282 sc->sc_isreset = 1; 1283 sc->sc_port_enabled = 1; 1284 return (USBD_NORMAL_COMPLETION); 1285 } 1286 1287 /* 1288 * This routine is executed when an interrupt on the root hub is detected 1289 */ 1290 static void 1291 motg_hub_change(struct motg_softc *sc) 1292 { 1293 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1294 usbd_pipe_handle pipe; 1295 u_char *p; 1296 1297 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1298 1299 if (xfer == NULL) 1300 return; /* the interrupt pipe is not open */ 1301 1302 pipe = xfer->pipe; 1303 if (pipe->device == NULL || pipe->device->bus == NULL) 1304 return; /* device has detached */ 1305 1306 p = KERNADDR(&xfer->dmabuf, 0); 1307 p[0] = 1<<1; 1308 xfer->actlen = 1; 1309 xfer->status = USBD_NORMAL_COMPLETION; 1310 usb_transfer_complete(xfer); 1311 } 1312 1313 static uint8_t 1314 motg_speed(u_int8_t speed) 1315 { 1316 switch(speed) { 1317 case USB_SPEED_LOW: 1318 return MUSB2_MASK_TI_SPEED_LO; 1319 case USB_SPEED_FULL: 1320 return MUSB2_MASK_TI_SPEED_FS; 1321 case USB_SPEED_HIGH: 1322 return MUSB2_MASK_TI_SPEED_HS; 1323 default: 1324 panic("motg: unknown speed %d", speed); 1325 /* NOTREACHED */ 1326 } 1327 } 1328 1329 static uint8_t 1330 motg_type(u_int8_t type) 1331 { 1332 switch(type) { 1333 case UE_CONTROL: 1334 return MUSB2_MASK_TI_PROTO_CTRL; 1335 case UE_ISOCHRONOUS: 1336 return MUSB2_MASK_TI_PROTO_ISOC; 1337 case UE_BULK: 1338 return MUSB2_MASK_TI_PROTO_BULK; 1339 case UE_INTERRUPT: 1340 return MUSB2_MASK_TI_PROTO_INTR; 1341 default: 1342 panic("motg: unknown type %d", type); 1343 /* NOTREACHED */ 1344 } 1345 } 1346 1347 static void 1348 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1349 { 1350 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1351 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1352 usbd_device_handle dev = otgpipe->pipe.device; 1353 int epnumber = otgpipe->hw_ep->ep_number; 1354 1355 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1356 if (dev->myhsport) { 1357 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1358 dev->myhsport->parent->address); 1359 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1360 dev->myhsport->portno); 1361 } else { 1362 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1363 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1364 } 1365 UWRITE1(sc, MUSB2_REG_TXTI, 1366 motg_speed(dev->speed) | 1367 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1368 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1369 ); 1370 if (epnumber == 0) { 1371 if (sc->sc_high_speed) { 1372 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1373 NAK_TO_CTRL_HIGH); 1374 } else { 1375 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1376 } 1377 } else { 1378 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1379 == UE_BULK) { 1380 if (sc->sc_high_speed) { 1381 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1382 NAK_TO_BULK_HIGH); 1383 } else { 1384 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1385 } 1386 } else { 1387 if (sc->sc_high_speed) { 1388 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1389 } else { 1390 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1391 } 1392 } 1393 } 1394 } 1395 1396 static void 1397 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1398 { 1399 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1400 usbd_device_handle dev = xfer->pipe->device; 1401 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1402 int epnumber = otgpipe->hw_ep->ep_number; 1403 1404 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1405 if (dev->myhsport) { 1406 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1407 dev->myhsport->parent->address); 1408 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1409 dev->myhsport->portno); 1410 } else { 1411 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1412 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1413 } 1414 UWRITE1(sc, MUSB2_REG_RXTI, 1415 motg_speed(dev->speed) | 1416 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1417 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1418 ); 1419 if (epnumber == 0) { 1420 if (sc->sc_high_speed) { 1421 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1422 NAK_TO_CTRL_HIGH); 1423 } else { 1424 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1425 } 1426 } else { 1427 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1428 == UE_BULK) { 1429 if (sc->sc_high_speed) { 1430 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1431 NAK_TO_BULK_HIGH); 1432 } else { 1433 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1434 } 1435 } else { 1436 if (sc->sc_high_speed) { 1437 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1438 } else { 1439 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1440 } 1441 } 1442 } 1443 } 1444 1445 static usbd_status 1446 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1447 { 1448 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1449 usbd_status err; 1450 1451 /* Insert last in queue. */ 1452 mutex_enter(&sc->sc_lock); 1453 err = usb_insert_transfer(xfer); 1454 xfer->status = USBD_NOT_STARTED; 1455 mutex_exit(&sc->sc_lock); 1456 if (err) 1457 return (err); 1458 1459 /* 1460 * Pipe isn't running (otherwise err would be USBD_INPROG), 1461 * so start it first. 1462 */ 1463 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1464 } 1465 1466 static usbd_status 1467 motg_device_ctrl_start(usbd_xfer_handle xfer) 1468 { 1469 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1470 usbd_status err; 1471 mutex_enter(&sc->sc_lock); 1472 err = motg_device_ctrl_start1(sc); 1473 mutex_exit(&sc->sc_lock); 1474 if (err != USBD_IN_PROGRESS) 1475 return err; 1476 if (sc->sc_bus.use_polling) 1477 motg_waitintr(sc, xfer); 1478 return USBD_IN_PROGRESS; 1479 } 1480 1481 static usbd_status 1482 motg_device_ctrl_start1(struct motg_softc *sc) 1483 { 1484 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1485 usbd_xfer_handle xfer = NULL; 1486 struct motg_pipe *otgpipe; 1487 usbd_status err = 0; 1488 1489 KASSERT(mutex_owned(&sc->sc_lock)); 1490 if (sc->sc_dying) 1491 return (USBD_IOERROR); 1492 1493 if (!sc->sc_connected) 1494 return (USBD_IOERROR); 1495 1496 if (ep->xfer != NULL) { 1497 err = USBD_IN_PROGRESS; 1498 goto end; 1499 } 1500 /* locate the first pipe with work to do */ 1501 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1502 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1503 DPRINTFN(MD_CTRL, 1504 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1505 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1506 1507 if (xfer != NULL) { 1508 /* move this pipe to the end of the list */ 1509 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1510 motg_pipe, ep_pipe_list); 1511 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1512 otgpipe, ep_pipe_list); 1513 break; 1514 } 1515 } 1516 if (xfer == NULL) { 1517 err = USBD_NOT_STARTED; 1518 goto end; 1519 } 1520 xfer->status = USBD_IN_PROGRESS; 1521 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1522 KASSERT(otgpipe->hw_ep == ep); 1523 #ifdef DIAGNOSTIC 1524 if (!(xfer->rqflags & URQ_REQUEST)) 1525 panic("motg_device_ctrl_transfer: not a request"); 1526 #endif 1527 // KASSERT(xfer->actlen == 0); 1528 xfer->actlen = 0; 1529 1530 ep->xfer = xfer; 1531 ep->datalen = xfer->length; 1532 if (ep->datalen > 0) 1533 ep->data = KERNADDR(&xfer->dmabuf, 0); 1534 else 1535 ep->data = NULL; 1536 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1537 (ep->datalen % 64) == 0) 1538 ep->need_short_xfer = 1; 1539 else 1540 ep->need_short_xfer = 0; 1541 /* now we need send this request */ 1542 DPRINTFN(MD_CTRL, 1543 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1544 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1545 xfer->pipe->device->address)); 1546 KASSERT(ep->phase == IDLE); 1547 ep->phase = SETUP; 1548 /* select endpoint 0 */ 1549 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1550 /* fifo should be empty at this point */ 1551 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1552 /* send data */ 1553 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1554 KASSERT(sizeof(xfer->request) == 8); 1555 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1556 (void *)&xfer->request, sizeof(xfer->request)); 1557 1558 motg_setup_endpoint_tx(xfer); 1559 /* start transaction */ 1560 UWRITE1(sc, MUSB2_REG_TXCSRL, 1561 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1562 1563 end: 1564 if (err) 1565 return (err); 1566 1567 return (USBD_IN_PROGRESS); 1568 } 1569 1570 static void 1571 motg_device_ctrl_read(usbd_xfer_handle xfer) 1572 { 1573 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1574 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1575 /* assume endpoint already selected */ 1576 motg_setup_endpoint_rx(xfer); 1577 /* start transaction */ 1578 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1579 otgpipe->hw_ep->phase = DATA_IN; 1580 } 1581 1582 static void 1583 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1584 { 1585 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1586 usbd_xfer_handle xfer = ep->xfer; 1587 uint8_t csr; 1588 int datalen, max_datalen; 1589 char *data; 1590 bool got_short; 1591 usbd_status new_status = USBD_IN_PROGRESS; 1592 1593 KASSERT(mutex_owned(&sc->sc_lock)); 1594 1595 #ifdef DIAGNOSTIC 1596 if (ep->phase != DATA_IN && 1597 ep->phase != STATUS_IN) 1598 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1599 #endif 1600 /* select endpoint 0 */ 1601 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1602 1603 /* read out FIFO status */ 1604 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1605 DPRINTFN(MD_CTRL, 1606 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1607 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1608 1609 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1610 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1611 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1612 1613 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1614 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1615 new_status = USBD_TIMEOUT; /* XXX */ 1616 goto complete; 1617 } 1618 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1619 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1620 new_status = USBD_STALLED; 1621 else 1622 new_status = USBD_IOERROR; 1623 /* clear status */ 1624 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1625 goto complete; 1626 } 1627 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1628 return; /* no data yet */ 1629 1630 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1631 goto complete; 1632 1633 if (ep->phase == STATUS_IN) { 1634 new_status = USBD_NORMAL_COMPLETION; 1635 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1636 goto complete; 1637 } 1638 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1639 DPRINTFN(MD_CTRL, 1640 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1641 ep->phase, datalen)); 1642 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1643 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1644 ep->datalen); 1645 if (datalen > max_datalen) { 1646 new_status = USBD_IOERROR; 1647 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1648 goto complete; 1649 } 1650 got_short = (datalen < max_datalen); 1651 if (datalen > 0) { 1652 KASSERT(ep->phase == DATA_IN); 1653 data = ep->data; 1654 ep->data += datalen; 1655 ep->datalen -= datalen; 1656 xfer->actlen += datalen; 1657 if (((vaddr_t)data & 0x3) == 0 && 1658 (datalen >> 2) > 0) { 1659 DPRINTFN(MD_CTRL, 1660 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1661 data, datalen)); 1662 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1663 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1664 data += (datalen & ~0x3); 1665 datalen -= (datalen & ~0x3); 1666 } 1667 DPRINTFN(MD_CTRL, 1668 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1669 data, datalen)); 1670 if (datalen) { 1671 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1672 MUSB2_REG_EPFIFO(0), data, datalen); 1673 } 1674 } 1675 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1676 KASSERT(ep->phase == DATA_IN); 1677 if (got_short || (ep->datalen == 0)) { 1678 if (ep->need_short_xfer == 0) { 1679 ep->phase = STATUS_OUT; 1680 UWRITE1(sc, MUSB2_REG_TXCSRH, 1681 UREAD1(sc, MUSB2_REG_TXCSRH) | 1682 MUSB2_MASK_CSR0H_PING_DIS); 1683 motg_setup_endpoint_tx(xfer); 1684 UWRITE1(sc, MUSB2_REG_TXCSRL, 1685 MUSB2_MASK_CSR0L_STATUSPKT | 1686 MUSB2_MASK_CSR0L_TXPKTRDY); 1687 return; 1688 } 1689 ep->need_short_xfer = 0; 1690 } 1691 motg_device_ctrl_read(xfer); 1692 return; 1693 complete: 1694 ep->phase = IDLE; 1695 ep->xfer = NULL; 1696 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1697 KASSERT(new_status != USBD_IN_PROGRESS); 1698 xfer->status = new_status; 1699 usb_transfer_complete(xfer); 1700 } 1701 motg_device_ctrl_start1(sc); 1702 } 1703 1704 static void 1705 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1706 { 1707 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1708 usbd_xfer_handle xfer = ep->xfer; 1709 uint8_t csr; 1710 int datalen; 1711 char *data; 1712 usbd_status new_status = USBD_IN_PROGRESS; 1713 1714 KASSERT(mutex_owned(&sc->sc_lock)); 1715 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1716 motg_device_ctrl_intr_rx(sc); 1717 return; 1718 } 1719 1720 #ifdef DIAGNOSTIC 1721 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1722 ep->phase != STATUS_OUT) 1723 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1724 #endif 1725 /* select endpoint 0 */ 1726 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1727 1728 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1729 DPRINTFN(MD_CTRL, 1730 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1731 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1732 1733 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1734 /* command not accepted */ 1735 new_status = USBD_STALLED; 1736 /* clear status */ 1737 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1738 goto complete; 1739 } 1740 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1741 new_status = USBD_TIMEOUT; /* XXX */ 1742 /* flush fifo */ 1743 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1744 UWRITE1(sc, MUSB2_REG_TXCSRH, 1745 UREAD1(sc, MUSB2_REG_TXCSRH) | 1746 MUSB2_MASK_CSR0H_FFLUSH); 1747 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1748 } 1749 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1750 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1751 goto complete; 1752 } 1753 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1754 new_status = USBD_IOERROR; 1755 /* clear status */ 1756 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1757 goto complete; 1758 } 1759 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1760 /* data still not sent */ 1761 return; 1762 } 1763 if (xfer == NULL) 1764 goto complete; 1765 if (ep->phase == STATUS_OUT) { 1766 /* 1767 * we have sent status and got no error; 1768 * declare transfer complete 1769 */ 1770 DPRINTFN(MD_CTRL, 1771 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1772 xfer, xfer->status)); 1773 new_status = USBD_NORMAL_COMPLETION; 1774 goto complete; 1775 } 1776 if (ep->datalen == 0) { 1777 if (ep->need_short_xfer) { 1778 ep->need_short_xfer = 0; 1779 /* one more data phase */ 1780 if (xfer->request.bmRequestType & UT_READ) { 1781 DPRINTFN(MD_CTRL, 1782 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1783 motg_device_ctrl_read(xfer); 1784 return; 1785 } /* else fall back to DATA_OUT */ 1786 } else { 1787 DPRINTFN(MD_CTRL, 1788 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1789 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1790 ep->phase = STATUS_IN; 1791 UWRITE1(sc, MUSB2_REG_RXCSRH, 1792 UREAD1(sc, MUSB2_REG_RXCSRH) | 1793 MUSB2_MASK_CSR0H_PING_DIS); 1794 motg_setup_endpoint_rx(xfer); 1795 UWRITE1(sc, MUSB2_REG_TXCSRL, 1796 MUSB2_MASK_CSR0L_STATUSPKT | 1797 MUSB2_MASK_CSR0L_REQPKT); 1798 return; 1799 } 1800 } 1801 if (xfer->request.bmRequestType & UT_READ) { 1802 motg_device_ctrl_read(xfer); 1803 return; 1804 } 1805 /* setup a dataout phase */ 1806 datalen = min(ep->datalen, 1807 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1808 ep->phase = DATA_OUT; 1809 DPRINTFN(MD_CTRL, 1810 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1811 UREAD1(sc, MUSB2_REG_TXCSRH))); 1812 if (datalen) { 1813 data = ep->data; 1814 ep->data += datalen; 1815 ep->datalen -= datalen; 1816 xfer->actlen += datalen; 1817 if (((vaddr_t)data & 0x3) == 0 && 1818 (datalen >> 2) > 0) { 1819 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1820 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1821 data += (datalen & ~0x3); 1822 datalen -= (datalen & ~0x3); 1823 } 1824 if (datalen) { 1825 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1826 MUSB2_REG_EPFIFO(0), data, datalen); 1827 } 1828 } 1829 /* send data */ 1830 motg_setup_endpoint_tx(xfer); 1831 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1832 return; 1833 1834 complete: 1835 ep->phase = IDLE; 1836 ep->xfer = NULL; 1837 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1838 KASSERT(new_status != USBD_IN_PROGRESS); 1839 xfer->status = new_status; 1840 usb_transfer_complete(xfer); 1841 } 1842 motg_device_ctrl_start1(sc); 1843 } 1844 1845 /* Abort a device control request. */ 1846 void 1847 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1848 { 1849 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1850 motg_device_xfer_abort(xfer); 1851 } 1852 1853 /* Close a device control pipe */ 1854 void 1855 motg_device_ctrl_close(usbd_pipe_handle pipe) 1856 { 1857 struct motg_softc *sc = pipe->device->bus->hci_private; 1858 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1859 struct motg_pipe *otgpipeiter; 1860 1861 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1862 KASSERT(mutex_owned(&sc->sc_lock)); 1863 KASSERT(otgpipe->hw_ep->xfer == NULL || 1864 otgpipe->hw_ep->xfer->pipe != pipe); 1865 1866 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1867 if (otgpipeiter == otgpipe) { 1868 /* remove from list */ 1869 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1870 motg_pipe, ep_pipe_list); 1871 otgpipe->hw_ep->refcount--; 1872 /* we're done */ 1873 return; 1874 } 1875 } 1876 panic("motg_device_ctrl_close: not found"); 1877 } 1878 1879 void 1880 motg_device_ctrl_done(usbd_xfer_handle xfer) 1881 { 1882 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1883 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1884 KASSERT(otgpipe->hw_ep->xfer != xfer); 1885 } 1886 1887 static usbd_status 1888 motg_device_data_transfer(usbd_xfer_handle xfer) 1889 { 1890 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1891 usbd_status err; 1892 1893 /* Insert last in queue. */ 1894 mutex_enter(&sc->sc_lock); 1895 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1896 xfer, xfer->status)); 1897 err = usb_insert_transfer(xfer); 1898 xfer->status = USBD_NOT_STARTED; 1899 mutex_exit(&sc->sc_lock); 1900 if (err) 1901 return (err); 1902 1903 /* 1904 * Pipe isn't running (otherwise err would be USBD_INPROG), 1905 * so start it first. 1906 */ 1907 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1908 } 1909 1910 static usbd_status 1911 motg_device_data_start(usbd_xfer_handle xfer) 1912 { 1913 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1914 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1915 usbd_status err; 1916 mutex_enter(&sc->sc_lock); 1917 DPRINTF(("motg_device_data_start(%p) status %d\n", 1918 xfer, xfer->status)); 1919 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1920 mutex_exit(&sc->sc_lock); 1921 if (err != USBD_IN_PROGRESS) 1922 return err; 1923 if (sc->sc_bus.use_polling) 1924 motg_waitintr(sc, xfer); 1925 return USBD_IN_PROGRESS; 1926 } 1927 1928 static usbd_status 1929 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1930 { 1931 usbd_xfer_handle xfer = NULL; 1932 struct motg_pipe *otgpipe; 1933 usbd_status err = 0; 1934 uint32_t val; 1935 1936 KASSERT(mutex_owned(&sc->sc_lock)); 1937 if (sc->sc_dying) 1938 return (USBD_IOERROR); 1939 1940 if (!sc->sc_connected) 1941 return (USBD_IOERROR); 1942 1943 if (ep->xfer != NULL) { 1944 err = USBD_IN_PROGRESS; 1945 goto end; 1946 } 1947 /* locate the first pipe with work to do */ 1948 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1949 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1950 DPRINTFN(MD_BULK, 1951 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1952 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1953 if (xfer != NULL) { 1954 /* move this pipe to the end of the list */ 1955 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1956 motg_pipe, ep_pipe_list); 1957 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1958 otgpipe, ep_pipe_list); 1959 break; 1960 } 1961 } 1962 if (xfer == NULL) { 1963 err = USBD_NOT_STARTED; 1964 goto end; 1965 } 1966 xfer->status = USBD_IN_PROGRESS; 1967 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1968 KASSERT(otgpipe->hw_ep == ep); 1969 #ifdef DIAGNOSTIC 1970 if (xfer->rqflags & URQ_REQUEST) 1971 panic("motg_device_data_transfer: a request"); 1972 #endif 1973 // KASSERT(xfer->actlen == 0); 1974 xfer->actlen = 0; 1975 1976 ep->xfer = xfer; 1977 ep->datalen = xfer->length; 1978 KASSERT(ep->datalen > 0); 1979 ep->data = KERNADDR(&xfer->dmabuf, 0); 1980 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1981 (ep->datalen % 64) == 0) 1982 ep->need_short_xfer = 1; 1983 else 1984 ep->need_short_xfer = 0; 1985 /* now we need send this request */ 1986 DPRINTFN(MD_BULK, 1987 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 1988 xfer, 1989 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 1990 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1991 xfer->pipe->device->address)); 1992 KASSERT(ep->phase == IDLE); 1993 /* select endpoint */ 1994 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1995 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 1996 == UE_DIR_IN) { 1997 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1998 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1999 motg_device_data_read(xfer); 2000 } else { 2001 ep->phase = DATA_OUT; 2002 val = UREAD1(sc, MUSB2_REG_TXCSRL); 2003 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 2004 motg_device_data_write(xfer); 2005 } 2006 end: 2007 if (err) 2008 return (err); 2009 2010 return (USBD_IN_PROGRESS); 2011 } 2012 2013 static void 2014 motg_device_data_read(usbd_xfer_handle xfer) 2015 { 2016 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2017 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2018 uint32_t val; 2019 2020 KASSERT(mutex_owned(&sc->sc_lock)); 2021 /* assume endpoint already selected */ 2022 motg_setup_endpoint_rx(xfer); 2023 /* Max packet size */ 2024 UWRITE2(sc, MUSB2_REG_RXMAXP, 2025 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2026 /* Data Toggle */ 2027 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2028 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2029 if (otgpipe->nexttoggle) 2030 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2031 else 2032 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2033 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2034 2035 DPRINTFN(MD_BULK, 2036 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2037 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2038 /* start transaction */ 2039 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2040 otgpipe->hw_ep->phase = DATA_IN; 2041 } 2042 2043 static void 2044 motg_device_data_write(usbd_xfer_handle xfer) 2045 { 2046 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2047 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2048 struct motg_hw_ep *ep = otgpipe->hw_ep; 2049 int datalen; 2050 char *data; 2051 uint32_t val; 2052 2053 KASSERT(xfer!=NULL); 2054 KASSERT(mutex_owned(&sc->sc_lock)); 2055 2056 datalen = min(ep->datalen, 2057 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2058 ep->phase = DATA_OUT; 2059 DPRINTFN(MD_BULK, 2060 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2061 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2062 2063 /* assume endpoint already selected */ 2064 /* write data to fifo */ 2065 data = ep->data; 2066 ep->data += datalen; 2067 ep->datalen -= datalen; 2068 xfer->actlen += datalen; 2069 if (((vaddr_t)data & 0x3) == 0 && 2070 (datalen >> 2) > 0) { 2071 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2072 MUSB2_REG_EPFIFO(ep->ep_number), 2073 (void *)data, datalen >> 2); 2074 data += (datalen & ~0x3); 2075 datalen -= (datalen & ~0x3); 2076 } 2077 if (datalen) { 2078 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2079 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2080 } 2081 2082 motg_setup_endpoint_tx(xfer); 2083 /* Max packet size */ 2084 UWRITE2(sc, MUSB2_REG_TXMAXP, 2085 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2086 /* Data Toggle */ 2087 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2088 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2089 if (otgpipe->nexttoggle) 2090 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2091 else 2092 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2093 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2094 2095 /* start transaction */ 2096 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2097 } 2098 2099 static void 2100 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2101 { 2102 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2103 usbd_xfer_handle xfer = ep->xfer; 2104 uint8_t csr; 2105 int datalen, max_datalen; 2106 char *data; 2107 bool got_short; 2108 usbd_status new_status = USBD_IN_PROGRESS; 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 KASSERT(ep->ep_number == epnumber); 2112 2113 DPRINTFN(MD_BULK, 2114 ("motg_device_intr_rx on ep %d\n", epnumber)); 2115 /* select endpoint */ 2116 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2117 2118 /* read out FIFO status */ 2119 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2120 DPRINTFN(MD_BULK, 2121 ("motg_device_intr_rx phase %d csr 0x%x\n", 2122 ep->phase, csr)); 2123 2124 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2125 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2126 return; 2127 2128 #ifdef DIAGNOSTIC 2129 if (ep->phase != DATA_IN) 2130 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2131 #endif 2132 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2133 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2134 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2135 2136 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2137 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2138 new_status = USBD_TIMEOUT; /* XXX */ 2139 goto complete; 2140 } 2141 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2142 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2143 new_status = USBD_STALLED; 2144 else 2145 new_status = USBD_IOERROR; 2146 /* clear status */ 2147 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2148 goto complete; 2149 } 2150 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2151 2152 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2153 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2154 goto complete; 2155 } 2156 2157 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2158 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2159 2160 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2161 DPRINTFN(MD_BULK, 2162 ("motg_device_intr_rx phase %d datalen %d\n", 2163 ep->phase, datalen)); 2164 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2165 max_datalen = min( 2166 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2167 ep->datalen); 2168 if (datalen > max_datalen) { 2169 new_status = USBD_IOERROR; 2170 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2171 goto complete; 2172 } 2173 got_short = (datalen < max_datalen); 2174 if (datalen > 0) { 2175 KASSERT(ep->phase == DATA_IN); 2176 data = ep->data; 2177 ep->data += datalen; 2178 ep->datalen -= datalen; 2179 xfer->actlen += datalen; 2180 if (((vaddr_t)data & 0x3) == 0 && 2181 (datalen >> 2) > 0) { 2182 DPRINTFN(MD_BULK, 2183 ("motg_device_intr_rx r4 data %p len %d\n", 2184 data, datalen)); 2185 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2186 MUSB2_REG_EPFIFO(ep->ep_number), 2187 (void *)data, datalen >> 2); 2188 data += (datalen & ~0x3); 2189 datalen -= (datalen & ~0x3); 2190 } 2191 DPRINTFN(MD_BULK, 2192 ("motg_device_intr_rx r1 data %p len %d\n", 2193 data, datalen)); 2194 if (datalen) { 2195 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2196 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2197 } 2198 } 2199 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2200 KASSERT(ep->phase == DATA_IN); 2201 if (got_short || (ep->datalen == 0)) { 2202 if (ep->need_short_xfer == 0) { 2203 new_status = USBD_NORMAL_COMPLETION; 2204 goto complete; 2205 } 2206 ep->need_short_xfer = 0; 2207 } 2208 motg_device_data_read(xfer); 2209 return; 2210 complete: 2211 DPRINTFN(MD_BULK, 2212 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2213 (xfer != NULL) ? xfer->status : 0)); 2214 ep->phase = IDLE; 2215 ep->xfer = NULL; 2216 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2217 KASSERT(new_status != USBD_IN_PROGRESS); 2218 xfer->status = new_status; 2219 usb_transfer_complete(xfer); 2220 } 2221 motg_device_data_start1(sc, ep); 2222 } 2223 2224 static void 2225 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2226 { 2227 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2228 usbd_xfer_handle xfer = ep->xfer; 2229 uint8_t csr; 2230 struct motg_pipe *otgpipe; 2231 usbd_status new_status = USBD_IN_PROGRESS; 2232 2233 KASSERT(mutex_owned(&sc->sc_lock)); 2234 KASSERT(ep->ep_number == epnumber); 2235 2236 DPRINTFN(MD_BULK, 2237 ("motg_device_intr_tx on ep %d\n", epnumber)); 2238 /* select endpoint */ 2239 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2240 2241 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2242 DPRINTFN(MD_BULK, 2243 ("motg_device_intr_tx phase %d csr 0x%x\n", 2244 ep->phase, csr)); 2245 2246 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2247 /* command not accepted */ 2248 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2249 new_status = USBD_STALLED; 2250 else 2251 new_status = USBD_IOERROR; 2252 /* clear status */ 2253 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2254 goto complete; 2255 } 2256 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2257 new_status = USBD_TIMEOUT; /* XXX */ 2258 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2259 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2260 /* flush fifo */ 2261 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2262 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2263 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2264 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2265 delay(1000); 2266 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2267 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2268 epnumber, csr)); 2269 } 2270 goto complete; 2271 } 2272 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2273 /* data still not sent */ 2274 return; 2275 } 2276 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2277 goto complete; 2278 #ifdef DIAGNOSTIC 2279 if (ep->phase != DATA_OUT) 2280 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2281 #endif 2282 2283 otgpipe = (struct motg_pipe *)xfer->pipe; 2284 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2285 2286 if (ep->datalen == 0) { 2287 if (ep->need_short_xfer) { 2288 ep->need_short_xfer = 0; 2289 /* one more data phase */ 2290 } else { 2291 new_status = USBD_NORMAL_COMPLETION; 2292 goto complete; 2293 } 2294 } 2295 motg_device_data_write(xfer); 2296 return; 2297 2298 complete: 2299 DPRINTFN(MD_BULK, 2300 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2301 (xfer != NULL) ? xfer->status : 0)); 2302 #ifdef DIAGNOSTIC 2303 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2304 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2305 #endif 2306 ep->phase = IDLE; 2307 ep->xfer = NULL; 2308 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2309 KASSERT(new_status != USBD_IN_PROGRESS); 2310 xfer->status = new_status; 2311 usb_transfer_complete(xfer); 2312 } 2313 motg_device_data_start1(sc, ep); 2314 } 2315 2316 /* Abort a device control request. */ 2317 void 2318 motg_device_data_abort(usbd_xfer_handle xfer) 2319 { 2320 #ifdef DIAGNOSTIC 2321 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2322 #endif 2323 KASSERT(mutex_owned(&sc->sc_lock)); 2324 2325 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2326 motg_device_xfer_abort(xfer); 2327 } 2328 2329 /* Close a device control pipe */ 2330 void 2331 motg_device_data_close(usbd_pipe_handle pipe) 2332 { 2333 struct motg_softc *sc = pipe->device->bus->hci_private; 2334 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2335 struct motg_pipe *otgpipeiter; 2336 2337 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2338 KASSERT(mutex_owned(&sc->sc_lock)); 2339 KASSERT(otgpipe->hw_ep->xfer == NULL || 2340 otgpipe->hw_ep->xfer->pipe != pipe); 2341 2342 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2343 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2344 if (otgpipeiter == otgpipe) { 2345 /* remove from list */ 2346 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2347 motg_pipe, ep_pipe_list); 2348 otgpipe->hw_ep->refcount--; 2349 /* we're done */ 2350 return; 2351 } 2352 } 2353 panic("motg_device_data_close: not found"); 2354 } 2355 2356 void 2357 motg_device_data_done(usbd_xfer_handle xfer) 2358 { 2359 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2360 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2361 KASSERT(otgpipe->hw_ep->xfer != xfer); 2362 } 2363 2364 /* 2365 * Wait here until controller claims to have an interrupt. 2366 * Then call motg_intr and return. Use timeout to avoid waiting 2367 * too long. 2368 * Only used during boot when interrupts are not enabled yet. 2369 */ 2370 void 2371 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2372 { 2373 int timo = xfer->timeout; 2374 2375 mutex_enter(&sc->sc_lock); 2376 2377 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2378 2379 for (; timo >= 0; timo--) { 2380 mutex_exit(&sc->sc_lock); 2381 usb_delay_ms(&sc->sc_bus, 1); 2382 mutex_spin_enter(&sc->sc_intr_lock); 2383 motg_poll(&sc->sc_bus); 2384 mutex_spin_exit(&sc->sc_intr_lock); 2385 mutex_enter(&sc->sc_lock); 2386 if (xfer->status != USBD_IN_PROGRESS) 2387 goto done; 2388 } 2389 2390 /* Timeout */ 2391 DPRINTF(("motg_waitintr: timeout\n")); 2392 panic("motg_waitintr: timeout"); 2393 /* XXX handle timeout ! */ 2394 2395 done: 2396 mutex_exit(&sc->sc_lock); 2397 } 2398 2399 void 2400 motg_device_clear_toggle(usbd_pipe_handle pipe) 2401 { 2402 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2403 otgpipe->nexttoggle = 0; 2404 } 2405 2406 /* Abort a device control request. */ 2407 static void 2408 motg_device_xfer_abort(usbd_xfer_handle xfer) 2409 { 2410 int wake; 2411 uint8_t csr; 2412 #ifdef DIAGNOSTIC 2413 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2414 #endif 2415 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2416 KASSERT(mutex_owned(&sc->sc_lock)); 2417 2418 DPRINTF(("motg_device_xfer_abort:\n")); 2419 if (xfer->hcflags & UXFER_ABORTING) { 2420 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2421 xfer->hcflags |= UXFER_ABORTWAIT; 2422 while (xfer->hcflags & UXFER_ABORTING) 2423 cv_wait(&xfer->hccv, &sc->sc_lock); 2424 return; 2425 } 2426 xfer->hcflags |= UXFER_ABORTING; 2427 if (otgpipe->hw_ep->xfer == xfer) { 2428 KASSERT(xfer->status == USBD_IN_PROGRESS); 2429 otgpipe->hw_ep->xfer = NULL; 2430 if (otgpipe->hw_ep->ep_number > 0) { 2431 /* select endpoint */ 2432 UWRITE1(sc, MUSB2_REG_EPINDEX, 2433 otgpipe->hw_ep->ep_number); 2434 if (otgpipe->hw_ep->phase == DATA_OUT) { 2435 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2436 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2437 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2438 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2439 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2440 } 2441 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2442 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2443 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2444 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2445 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2446 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2447 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2448 } 2449 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2450 } 2451 otgpipe->hw_ep->phase = IDLE; 2452 } 2453 } 2454 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2455 wake = xfer->hcflags & UXFER_ABORTWAIT; 2456 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2457 usb_transfer_complete(xfer); 2458 if (wake) 2459 cv_broadcast(&xfer->hccv); 2460 } 2461
Indexes created Fri Sep 26 08:10:20 GMT 2025