motg.c revision 1.30
1 /* $NetBSD: motg.c,v 1.30 2020/02/18 17:50:20 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.30 2020/02/18 17:50:20 riastradh Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_usb.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usbhist.h> 69 70 #include <dev/usb/motgreg.h> 71 #include <dev/usb/motgvar.h> 72 #include <dev/usb/usbroothub.h> 73 74 #ifdef USB_DEBUG 75 #ifndef MOTG_DEBUG 76 #define motgdebug 0 77 #else 78 int motgdebug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 88 SYSCTL_DESCR("motg global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 107 #endif /* MOTG_DEBUG */ 108 #endif /* USB_DEBUG */ 109 110 #define MD_ROOT 0x0002 111 #define MD_CTRL 0x0004 112 #define MD_BULK 0x0008 113 114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 116 #define MOTGHIST_FUNC() USBHIST_FUNC() 117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 118 119 120 /* various timeouts, for various speeds */ 121 /* control NAK timeouts */ 122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 124 125 /* intr/iso polling intervals */ 126 #define POLL_TO 100 /* 100 frames, about 0.1s */ 127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 128 129 /* bulk NAK timeouts */ 130 #define NAK_TO_BULK 0 /* disabled */ 131 #define NAK_TO_BULK_HIGH 0 132 133 static void motg_hub_change(struct motg_softc *); 134 135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 136 static usbd_status motg_root_intr_start(struct usbd_xfer *); 137 static void motg_root_intr_abort(struct usbd_xfer *); 138 static void motg_root_intr_close(struct usbd_pipe *); 139 static void motg_root_intr_done(struct usbd_xfer *); 140 141 static usbd_status motg_open(struct usbd_pipe *); 142 static void motg_poll(struct usbd_bus *); 143 static void motg_softintr(void *); 144 static struct usbd_xfer * 145 motg_allocx(struct usbd_bus *, unsigned int); 146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 147 static bool motg_dying(struct usbd_bus *); 148 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 149 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 150 void *, int); 151 152 static void motg_noop(struct usbd_pipe *pipe); 153 static usbd_status motg_portreset(struct motg_softc*); 154 155 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 156 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 157 static void motg_device_ctrl_abort(struct usbd_xfer *); 158 static void motg_device_ctrl_close(struct usbd_pipe *); 159 static void motg_device_ctrl_done(struct usbd_xfer *); 160 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 161 static void motg_device_ctrl_read(struct usbd_xfer *); 162 static void motg_device_ctrl_intr_rx(struct motg_softc *); 163 static void motg_device_ctrl_intr_tx(struct motg_softc *); 164 165 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 166 static usbd_status motg_device_data_start(struct usbd_xfer *); 167 static usbd_status motg_device_data_start1(struct motg_softc *, 168 struct motg_hw_ep *); 169 static void motg_device_data_abort(struct usbd_xfer *); 170 static void motg_device_data_close(struct usbd_pipe *); 171 static void motg_device_data_done(struct usbd_xfer *); 172 static void motg_device_intr_rx(struct motg_softc *, int); 173 static void motg_device_intr_tx(struct motg_softc *, int); 174 static void motg_device_data_read(struct usbd_xfer *); 175 static void motg_device_data_write(struct usbd_xfer *); 176 177 static void motg_device_clear_toggle(struct usbd_pipe *); 178 static void motg_abortx(struct usbd_xfer *); 179 180 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 181 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 182 #define UWRITE1(sc, r, x) \ 183 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 184 } while (/*CONSTCOND*/0) 185 #define UWRITE2(sc, r, x) \ 186 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 187 } while (/*CONSTCOND*/0) 188 #define UWRITE4(sc, r, x) \ 189 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 190 } while (/*CONSTCOND*/0) 191 192 static __inline uint32_t 193 UREAD1(struct motg_softc *sc, bus_size_t r) 194 { 195 196 UBARR(sc); 197 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 198 } 199 static __inline uint32_t 200 UREAD2(struct motg_softc *sc, bus_size_t r) 201 { 202 203 UBARR(sc); 204 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 205 } 206 207 #if 0 208 static __inline uint32_t 209 UREAD4(struct motg_softc *sc, bus_size_t r) 210 { 211 212 UBARR(sc); 213 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 214 } 215 #endif 216 217 static void 218 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 219 { 220 uint8_t val; 221 222 val = UREAD1(sc, MUSB2_REG_POWER); 223 if (on) 224 val |= MUSB2_MASK_SOFTC; 225 else 226 val &= ~MUSB2_MASK_SOFTC; 227 228 UWRITE1(sc, MUSB2_REG_POWER, val); 229 } 230 231 const struct usbd_bus_methods motg_bus_methods = { 232 .ubm_open = motg_open, 233 .ubm_softint = motg_softintr, 234 .ubm_dopoll = motg_poll, 235 .ubm_allocx = motg_allocx, 236 .ubm_freex = motg_freex, 237 .ubm_abortx = motg_abortx, 238 .ubm_dying = motg_dying, 239 .ubm_getlock = motg_get_lock, 240 .ubm_rhctrl = motg_roothub_ctrl, 241 }; 242 243 const struct usbd_pipe_methods motg_root_intr_methods = { 244 .upm_transfer = motg_root_intr_transfer, 245 .upm_start = motg_root_intr_start, 246 .upm_abort = motg_root_intr_abort, 247 .upm_close = motg_root_intr_close, 248 .upm_cleartoggle = motg_noop, 249 .upm_done = motg_root_intr_done, 250 }; 251 252 const struct usbd_pipe_methods motg_device_ctrl_methods = { 253 .upm_transfer = motg_device_ctrl_transfer, 254 .upm_start = motg_device_ctrl_start, 255 .upm_abort = motg_device_ctrl_abort, 256 .upm_close = motg_device_ctrl_close, 257 .upm_cleartoggle = motg_noop, 258 .upm_done = motg_device_ctrl_done, 259 }; 260 261 const struct usbd_pipe_methods motg_device_data_methods = { 262 .upm_transfer = motg_device_data_transfer, 263 .upm_start = motg_device_data_start, 264 .upm_abort = motg_device_data_abort, 265 .upm_close = motg_device_data_close, 266 .upm_cleartoggle = motg_device_clear_toggle, 267 .upm_done = motg_device_data_done, 268 }; 269 270 int 271 motg_init(struct motg_softc *sc) 272 { 273 uint32_t nrx, ntx, val; 274 int dynfifo; 275 int offset, i; 276 277 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 278 279 if (sc->sc_mode == MOTG_MODE_DEVICE) 280 return ENOTSUP; /* not supported */ 281 282 /* disable all interrupts */ 283 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 284 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 285 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 286 /* disable pullup */ 287 288 musbotg_pull_common(sc, 0); 289 290 #ifdef MUSB2_REG_RXDBDIS 291 /* disable double packet buffering XXX what's this ? */ 292 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 293 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 294 #endif 295 296 /* enable HighSpeed and ISO Update flags */ 297 298 UWRITE1(sc, MUSB2_REG_POWER, 299 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 300 301 if (sc->sc_mode == MOTG_MODE_DEVICE) { 302 /* clear Session bit, if set */ 303 val = UREAD1(sc, MUSB2_REG_DEVCTL); 304 val &= ~MUSB2_MASK_SESS; 305 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 306 } else { 307 /* Enter session for Host mode */ 308 val = UREAD1(sc, MUSB2_REG_DEVCTL); 309 val |= MUSB2_MASK_SESS; 310 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 311 } 312 delay(1000); 313 DPRINTF("DEVCTL 0x%jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 314 315 /* disable testmode */ 316 317 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 318 319 #ifdef MUSB2_REG_MISC 320 /* set default value */ 321 322 UWRITE1(sc, MUSB2_REG_MISC, 0); 323 #endif 324 325 /* select endpoint index 0 */ 326 327 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 328 329 if (sc->sc_ep_max == 0) { 330 /* read out number of endpoints */ 331 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 332 333 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 334 335 /* these numbers exclude the control endpoint */ 336 337 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 338 339 sc->sc_ep_max = MAX(nrx, ntx); 340 } else { 341 nrx = ntx = sc->sc_ep_max; 342 } 343 if (sc->sc_ep_max == 0) { 344 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 345 return -1; 346 } 347 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 348 /* read out configuration data */ 349 val = UREAD1(sc, MUSB2_REG_CONFDATA); 350 351 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 352 353 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 354 355 if (dynfifo) { 356 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 357 "assuming 16Kbytes of FIFO RAM\n"); 358 } 359 360 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 361 362 /* initialise endpoint profiles */ 363 sc->sc_in_ep[0].ep_fifo_size = 64; 364 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 365 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 366 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 367 offset = 64; 368 369 for (i = 1; i <= sc->sc_ep_max; i++) { 370 int fiforx_size, fifotx_size, fifo_size; 371 372 /* select endpoint */ 373 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 374 375 if (sc->sc_ep_fifosize) { 376 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 377 } else { 378 val = UREAD1(sc, MUSB2_REG_FSIZE); 379 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 380 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 381 } 382 383 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 384 i, fifotx_size, fiforx_size, dynfifo); 385 386 if (dynfifo) { 387 if (sc->sc_ep_fifosize) { 388 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 389 } else { 390 if (i < 3) { 391 fifo_size = 12; /* 4K */ 392 } else if (i < 10) { 393 fifo_size = 10; /* 1K */ 394 } else { 395 fifo_size = 7; /* 128 bytes */ 396 } 397 } 398 if (fiforx_size && (i <= nrx)) { 399 fiforx_size = fifo_size; 400 if (fifo_size > 7) { 401 #if 0 402 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size) | 404 MUSB2_MASK_FIFODB); 405 #else 406 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size)); 408 #endif 409 } else { 410 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 411 MUSB2_VAL_FIFOSZ(fifo_size)); 412 } 413 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 414 offset >> 3); 415 offset += (1 << fiforx_size); 416 } 417 if (fifotx_size && (i <= ntx)) { 418 fifotx_size = fifo_size; 419 if (fifo_size > 7) { 420 #if 0 421 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 422 MUSB2_VAL_FIFOSZ(fifo_size) | 423 MUSB2_MASK_FIFODB); 424 #else 425 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 426 MUSB2_VAL_FIFOSZ(fifo_size)); 427 #endif 428 } else { 429 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 430 MUSB2_VAL_FIFOSZ(fifo_size)); 431 } 432 433 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 434 offset >> 3); 435 436 offset += (1 << fifotx_size); 437 } 438 } 439 if (fiforx_size && (i <= nrx)) { 440 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 441 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 442 } 443 if (fifotx_size && (i <= ntx)) { 444 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 445 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 446 } 447 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 448 } 449 450 451 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 452 453 /* turn on default interrupts */ 454 455 if (sc->sc_mode == MOTG_MODE_HOST) { 456 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 457 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 458 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 459 } else 460 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 461 462 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 463 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 464 465 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 466 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.ub_methods = &motg_bus_methods; 470 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 471 sc->sc_bus.ub_revision = USBREV_2_0; 472 sc->sc_bus.ub_usedma = false; 473 sc->sc_bus.ub_hcpriv = sc; 474 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 475 return 0; 476 } 477 478 static int 479 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 480 { 481 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 482 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 483 struct motg_hw_ep *ep; 484 int i, size; 485 486 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 487 488 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 489 sc->sc_in_ep : sc->sc_out_ep; 490 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 491 492 for (i = sc->sc_ep_max; i >= 1; i--) { 493 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 494 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 495 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 496 ep[i].ep_fifo_size, size, ep[i].refcount); 497 if (ep[i].ep_fifo_size >= size) { 498 /* found a suitable endpoint */ 499 otgpipe->hw_ep = &ep[i]; 500 mutex_enter(&sc->sc_lock); 501 if (otgpipe->hw_ep->refcount > 0) { 502 /* no luck, try next */ 503 mutex_exit(&sc->sc_lock); 504 otgpipe->hw_ep = NULL; 505 } else { 506 otgpipe->hw_ep->refcount++; 507 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 508 otgpipe, ep_pipe_list); 509 mutex_exit(&sc->sc_lock); 510 return 0; 511 } 512 } 513 } 514 return -1; 515 } 516 517 /* Open a new pipe. */ 518 usbd_status 519 motg_open(struct usbd_pipe *pipe) 520 { 521 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 522 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 523 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 524 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 525 526 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 527 528 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 529 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 530 531 if (sc->sc_dying) 532 return USBD_IOERROR; 533 534 /* toggle state needed for bulk endpoints */ 535 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 536 537 if (pipe->up_dev->ud_addr == rhaddr) { 538 switch (ed->bEndpointAddress) { 539 case USB_CONTROL_ENDPOINT: 540 pipe->up_methods = &roothub_ctrl_methods; 541 break; 542 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 543 pipe->up_methods = &motg_root_intr_methods; 544 break; 545 default: 546 return USBD_INVAL; 547 } 548 } else { 549 switch (ed->bmAttributes & UE_XFERTYPE) { 550 case UE_CONTROL: 551 pipe->up_methods = &motg_device_ctrl_methods; 552 /* always use sc_in_ep[0] for in and out */ 553 otgpipe->hw_ep = &sc->sc_in_ep[0]; 554 mutex_enter(&sc->sc_lock); 555 otgpipe->hw_ep->refcount++; 556 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 557 otgpipe, ep_pipe_list); 558 mutex_exit(&sc->sc_lock); 559 break; 560 case UE_BULK: 561 case UE_INTERRUPT: 562 DPRINTFN(MD_BULK, 563 "type %jd dir %jd pipe wMaxPacketSize %jd", 564 UE_GET_XFERTYPE(ed->bmAttributes), 565 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 566 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 567 if (motg_select_ep(sc, pipe) != 0) 568 goto bad; 569 KASSERT(otgpipe->hw_ep != NULL); 570 pipe->up_methods = &motg_device_data_methods; 571 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 572 break; 573 default: 574 goto bad; 575 #ifdef notyet 576 case UE_ISOCHRONOUS: 577 ... 578 break; 579 #endif /* notyet */ 580 } 581 } 582 return USBD_NORMAL_COMPLETION; 583 584 bad: 585 return USBD_NOMEM; 586 } 587 588 void 589 motg_softintr(void *v) 590 { 591 struct usbd_bus *bus = v; 592 struct motg_softc *sc = MOTG_BUS2SC(bus); 593 uint16_t rx_status, tx_status; 594 uint8_t ctrl_status; 595 uint32_t val; 596 int i; 597 598 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 599 600 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 601 602 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 603 604 mutex_spin_enter(&sc->sc_intr_lock); 605 rx_status = sc->sc_intr_rx_ep; 606 sc->sc_intr_rx_ep = 0; 607 tx_status = sc->sc_intr_tx_ep; 608 sc->sc_intr_tx_ep = 0; 609 ctrl_status = sc->sc_intr_ctrl; 610 sc->sc_intr_ctrl = 0; 611 mutex_spin_exit(&sc->sc_intr_lock); 612 613 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 614 615 if (ctrl_status & (MUSB2_MASK_IRESET | 616 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 617 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 618 DPRINTFN(MD_ROOT | MD_CTRL, "bus 0x%jx", ctrl_status, 0, 0, 0); 619 620 if (ctrl_status & MUSB2_MASK_IRESET) { 621 sc->sc_isreset = 1; 622 sc->sc_port_suspended = 0; 623 sc->sc_port_suspended_change = 1; 624 sc->sc_connected_changed = 1; 625 sc->sc_port_enabled = 1; 626 627 val = UREAD1(sc, MUSB2_REG_POWER); 628 if (val & MUSB2_MASK_HSMODE) 629 sc->sc_high_speed = 1; 630 else 631 sc->sc_high_speed = 0; 632 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 633 0, 0, 0); 634 635 /* turn off interrupts */ 636 val = MUSB2_MASK_IRESET; 637 val &= ~MUSB2_MASK_IRESUME; 638 val |= MUSB2_MASK_ISUSP; 639 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 640 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 641 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 642 } 643 if (ctrl_status & MUSB2_MASK_IRESUME) { 644 if (sc->sc_port_suspended) { 645 sc->sc_port_suspended = 0; 646 sc->sc_port_suspended_change = 1; 647 val = UREAD1(sc, MUSB2_REG_INTUSBE); 648 /* disable resume interrupt */ 649 val &= ~MUSB2_MASK_IRESUME; 650 /* enable suspend interrupt */ 651 val |= MUSB2_MASK_ISUSP; 652 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 653 } 654 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 655 if (!sc->sc_port_suspended) { 656 sc->sc_port_suspended = 1; 657 sc->sc_port_suspended_change = 1; 658 659 val = UREAD1(sc, MUSB2_REG_INTUSBE); 660 /* disable suspend interrupt */ 661 val &= ~MUSB2_MASK_ISUSP; 662 /* enable resume interrupt */ 663 val |= MUSB2_MASK_IRESUME; 664 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 665 } 666 } 667 if (ctrl_status & MUSB2_MASK_ICONN) { 668 sc->sc_connected = 1; 669 sc->sc_connected_changed = 1; 670 sc->sc_isreset = 1; 671 sc->sc_port_enabled = 1; 672 } else if (ctrl_status & MUSB2_MASK_IDISC) { 673 sc->sc_connected = 0; 674 sc->sc_connected_changed = 1; 675 sc->sc_isreset = 0; 676 sc->sc_port_enabled = 0; 677 } 678 679 /* complete root HUB interrupt endpoint */ 680 681 motg_hub_change(sc); 682 } 683 /* 684 * read in interrupt status and mix with the status we 685 * got from the wrapper 686 */ 687 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 688 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 689 690 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 691 if (tx_status & 0x01) 692 motg_device_ctrl_intr_tx(sc); 693 for (i = 1; i <= sc->sc_ep_max; i++) { 694 if (rx_status & (0x01 << i)) 695 motg_device_intr_rx(sc, i); 696 if (tx_status & (0x01 << i)) 697 motg_device_intr_tx(sc, i); 698 } 699 return; 700 } 701 702 void 703 motg_poll(struct usbd_bus *bus) 704 { 705 struct motg_softc *sc = MOTG_BUS2SC(bus); 706 707 sc->sc_intr_poll(sc->sc_intr_poll_arg); 708 mutex_enter(&sc->sc_lock); 709 motg_softintr(bus); 710 mutex_exit(&sc->sc_lock); 711 } 712 713 int 714 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 715 uint8_t ctrl) 716 { 717 KASSERT(mutex_owned(&sc->sc_intr_lock)); 718 sc->sc_intr_tx_ep = tx_ep; 719 sc->sc_intr_rx_ep = rx_ep; 720 sc->sc_intr_ctrl = ctrl; 721 722 if (!sc->sc_bus.ub_usepolling) { 723 usb_schedsoftintr(&sc->sc_bus); 724 } 725 return 1; 726 } 727 728 int 729 motg_intr_vbus(struct motg_softc *sc, int vbus) 730 { 731 uint8_t val; 732 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 733 734 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 735 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 736 /* try to re-enter session for Host mode */ 737 val = UREAD1(sc, MUSB2_REG_DEVCTL); 738 val |= MUSB2_MASK_SESS; 739 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 740 } 741 return 1; 742 } 743 744 struct usbd_xfer * 745 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 746 { 747 struct motg_softc *sc = MOTG_BUS2SC(bus); 748 struct usbd_xfer *xfer; 749 750 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 751 if (xfer != NULL) { 752 memset(xfer, 0, sizeof(struct motg_xfer)); 753 #ifdef DIAGNOSTIC 754 xfer->ux_state = XFER_BUSY; 755 #endif 756 } 757 return xfer; 758 } 759 760 void 761 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 762 { 763 struct motg_softc *sc = MOTG_BUS2SC(bus); 764 765 #ifdef DIAGNOSTIC 766 if (xfer->ux_state != XFER_BUSY && 767 xfer->ux_status != USBD_NOT_STARTED) { 768 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 769 xfer->ux_state); 770 } 771 xfer->ux_state = XFER_FREE; 772 #endif 773 pool_cache_put(sc->sc_xferpool, xfer); 774 } 775 776 static bool 777 motg_dying(struct usbd_bus *bus) 778 { 779 struct motg_softc *sc = MOTG_BUS2SC(bus); 780 781 return sc->sc_dying; 782 } 783 784 static void 785 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 786 { 787 struct motg_softc *sc = MOTG_BUS2SC(bus); 788 789 *lock = &sc->sc_lock; 790 } 791 792 /* 793 * Routines to emulate the root hub. 794 */ 795 Static int 796 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 797 void *buf, int buflen) 798 { 799 struct motg_softc *sc = MOTG_BUS2SC(bus); 800 int status, change, totlen = 0; 801 uint16_t len, value, index; 802 usb_port_status_t ps; 803 usbd_status err; 804 uint32_t val; 805 806 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 807 808 if (sc->sc_dying) 809 return -1; 810 811 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 812 req->bRequest, 0, 0); 813 814 len = UGETW(req->wLength); 815 value = UGETW(req->wValue); 816 index = UGETW(req->wIndex); 817 818 #define C(x,y) ((x) | ((y) << 8)) 819 switch (C(req->bRequest, req->bmRequestType)) { 820 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 821 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 822 switch (value) { 823 #define sd ((usb_string_descriptor_t *)buf) 824 case C(2, UDESC_STRING): 825 /* Product */ 826 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 827 break; 828 #undef sd 829 default: 830 /* default from usbroothub */ 831 return buflen; 832 } 833 break; 834 /* Hub requests */ 835 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 836 break; 837 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 838 DPRINTFN(MD_ROOT, 839 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 840 0, 0); 841 if (index != 1) { 842 return -1; 843 } 844 switch (value) { 845 case UHF_PORT_ENABLE: 846 sc->sc_port_enabled = 0; 847 break; 848 case UHF_PORT_SUSPEND: 849 if (sc->sc_port_suspended != 0) { 850 val = UREAD1(sc, MUSB2_REG_POWER); 851 val &= ~MUSB2_MASK_SUSPMODE; 852 val |= MUSB2_MASK_RESUME; 853 UWRITE1(sc, MUSB2_REG_POWER, val); 854 /* wait 20 milliseconds */ 855 usb_delay_ms(&sc->sc_bus, 20); 856 val = UREAD1(sc, MUSB2_REG_POWER); 857 val &= ~MUSB2_MASK_RESUME; 858 UWRITE1(sc, MUSB2_REG_POWER, val); 859 sc->sc_port_suspended = 0; 860 sc->sc_port_suspended_change = 1; 861 } 862 break; 863 case UHF_PORT_RESET: 864 break; 865 case UHF_C_PORT_CONNECTION: 866 break; 867 case UHF_C_PORT_ENABLE: 868 break; 869 case UHF_C_PORT_OVER_CURRENT: 870 break; 871 case UHF_C_PORT_RESET: 872 sc->sc_isreset = 0; 873 break; 874 case UHF_PORT_POWER: 875 /* XXX todo */ 876 break; 877 case UHF_PORT_CONNECTION: 878 case UHF_PORT_OVER_CURRENT: 879 case UHF_PORT_LOW_SPEED: 880 case UHF_C_PORT_SUSPEND: 881 default: 882 return -1; 883 } 884 break; 885 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 886 return -1; 887 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 888 if (len == 0) 889 break; 890 if ((value & 0xff) != 0) { 891 return -1; 892 } 893 totlen = buflen; 894 break; 895 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 896 if (len != 4) { 897 return -1; 898 } 899 memset(buf, 0, len); 900 totlen = len; 901 break; 902 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 903 if (index != 1) { 904 return -1; 905 } 906 if (len != 4) { 907 return -1; 908 } 909 status = change = 0; 910 if (sc->sc_connected) 911 status |= UPS_CURRENT_CONNECT_STATUS; 912 if (sc->sc_connected_changed) { 913 change |= UPS_C_CONNECT_STATUS; 914 sc->sc_connected_changed = 0; 915 } 916 if (sc->sc_port_enabled) 917 status |= UPS_PORT_ENABLED; 918 if (sc->sc_port_enabled_changed) { 919 change |= UPS_C_PORT_ENABLED; 920 sc->sc_port_enabled_changed = 0; 921 } 922 if (sc->sc_port_suspended) 923 status |= UPS_SUSPEND; 924 if (sc->sc_high_speed) 925 status |= UPS_HIGH_SPEED; 926 status |= UPS_PORT_POWER; /* XXX */ 927 if (sc->sc_isreset) 928 change |= UPS_C_PORT_RESET; 929 USETW(ps.wPortStatus, status); 930 USETW(ps.wPortChange, change); 931 totlen = uimin(len, sizeof(ps)); 932 memcpy(buf, &ps, totlen); 933 break; 934 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 935 return -1; 936 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 937 break; 938 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 939 if (index != 1) { 940 return -1; 941 } 942 switch(value) { 943 case UHF_PORT_ENABLE: 944 sc->sc_port_enabled = 1; 945 break; 946 case UHF_PORT_SUSPEND: 947 if (sc->sc_port_suspended == 0) { 948 val = UREAD1(sc, MUSB2_REG_POWER); 949 val |= MUSB2_MASK_SUSPMODE; 950 UWRITE1(sc, MUSB2_REG_POWER, val); 951 /* wait 20 milliseconds */ 952 usb_delay_ms(&sc->sc_bus, 20); 953 sc->sc_port_suspended = 1; 954 sc->sc_port_suspended_change = 1; 955 } 956 break; 957 case UHF_PORT_RESET: 958 err = motg_portreset(sc); 959 if (err != USBD_NORMAL_COMPLETION) 960 return -1; 961 return 0; 962 case UHF_PORT_POWER: 963 /* XXX todo */ 964 return 0; 965 case UHF_C_PORT_CONNECTION: 966 case UHF_C_PORT_ENABLE: 967 case UHF_C_PORT_OVER_CURRENT: 968 case UHF_PORT_CONNECTION: 969 case UHF_PORT_OVER_CURRENT: 970 case UHF_PORT_LOW_SPEED: 971 case UHF_C_PORT_SUSPEND: 972 case UHF_C_PORT_RESET: 973 default: 974 return -1; 975 } 976 break; 977 default: 978 /* default from usbroothub */ 979 return buflen; 980 } 981 982 return totlen; 983 } 984 985 /* Abort a root interrupt request. */ 986 void 987 motg_root_intr_abort(struct usbd_xfer *xfer) 988 { 989 struct motg_softc *sc = MOTG_XFER2SC(xfer); 990 991 KASSERT(mutex_owned(&sc->sc_lock)); 992 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 993 994 /* If xfer has already completed, nothing to do here. */ 995 if (sc->sc_intr_xfer == NULL) 996 return; 997 998 /* 999 * Otherwise, sc->sc_intr_xfer had better be this transfer. 1000 * Cancel it. 1001 */ 1002 KASSERT(sc->sc_intr_xfer == xfer); 1003 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1004 xfer->ux_status = USBD_CANCELLED; 1005 usb_transfer_complete(xfer); 1006 } 1007 1008 usbd_status 1009 motg_root_intr_transfer(struct usbd_xfer *xfer) 1010 { 1011 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1012 usbd_status err; 1013 1014 /* Insert last in queue. */ 1015 mutex_enter(&sc->sc_lock); 1016 err = usb_insert_transfer(xfer); 1017 mutex_exit(&sc->sc_lock); 1018 if (err) 1019 return err; 1020 1021 /* 1022 * Pipe isn't running (otherwise err would be USBD_INPROG), 1023 * start first 1024 */ 1025 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1026 } 1027 1028 /* Start a transfer on the root interrupt pipe */ 1029 usbd_status 1030 motg_root_intr_start(struct usbd_xfer *xfer) 1031 { 1032 struct usbd_pipe *pipe = xfer->ux_pipe; 1033 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1034 const bool polling = sc->sc_bus.ub_usepolling; 1035 1036 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1037 1038 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1039 xfer->ux_length, xfer->ux_flags, 0); 1040 1041 if (sc->sc_dying) 1042 return USBD_IOERROR; 1043 1044 if (!polling) 1045 mutex_enter(&sc->sc_lock); 1046 KASSERT(sc->sc_intr_xfer == NULL); 1047 sc->sc_intr_xfer = xfer; 1048 xfer->ux_status = USBD_IN_PROGRESS; 1049 if (!polling) 1050 mutex_exit(&sc->sc_lock); 1051 1052 return USBD_IN_PROGRESS; 1053 } 1054 1055 /* Close the root interrupt pipe. */ 1056 void 1057 motg_root_intr_close(struct usbd_pipe *pipe) 1058 { 1059 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1060 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1061 1062 KASSERT(mutex_owned(&sc->sc_lock)); 1063 1064 /* 1065 * Caller must guarantee the xfer has completed first, by 1066 * closing the pipe only after normal completion or an abort. 1067 */ 1068 KASSERT(sc->sc_intr_xfer == NULL); 1069 } 1070 1071 void 1072 motg_root_intr_done(struct usbd_xfer *xfer) 1073 { 1074 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1075 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1076 1077 KASSERT(mutex_owned(&sc->sc_lock)); 1078 1079 /* Claim the xfer so it doesn't get completed again. */ 1080 KASSERT(sc->sc_intr_xfer == xfer); 1081 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1082 sc->sc_intr_xfer = NULL; 1083 } 1084 1085 void 1086 motg_noop(struct usbd_pipe *pipe) 1087 { 1088 } 1089 1090 static usbd_status 1091 motg_portreset(struct motg_softc *sc) 1092 { 1093 uint32_t val; 1094 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1095 1096 val = UREAD1(sc, MUSB2_REG_POWER); 1097 val |= MUSB2_MASK_RESET; 1098 UWRITE1(sc, MUSB2_REG_POWER, val); 1099 /* Wait for 20 msec */ 1100 usb_delay_ms(&sc->sc_bus, 20); 1101 1102 val = UREAD1(sc, MUSB2_REG_POWER); 1103 val &= ~MUSB2_MASK_RESET; 1104 UWRITE1(sc, MUSB2_REG_POWER, val); 1105 1106 /* determine line speed */ 1107 val = UREAD1(sc, MUSB2_REG_POWER); 1108 if (val & MUSB2_MASK_HSMODE) 1109 sc->sc_high_speed = 1; 1110 else 1111 sc->sc_high_speed = 0; 1112 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1113 1114 sc->sc_isreset = 1; 1115 sc->sc_port_enabled = 1; 1116 return USBD_NORMAL_COMPLETION; 1117 } 1118 1119 /* 1120 * This routine is executed when an interrupt on the root hub is detected 1121 */ 1122 static void 1123 motg_hub_change(struct motg_softc *sc) 1124 { 1125 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1126 struct usbd_pipe *pipe; 1127 u_char *p; 1128 1129 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1130 1131 if (xfer == NULL) 1132 return; /* the interrupt pipe is not open */ 1133 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1134 1135 pipe = xfer->ux_pipe; 1136 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1137 return; /* device has detached */ 1138 1139 p = xfer->ux_buf; 1140 p[0] = 1<<1; 1141 xfer->ux_actlen = 1; 1142 xfer->ux_status = USBD_NORMAL_COMPLETION; 1143 usb_transfer_complete(xfer); 1144 } 1145 1146 static uint8_t 1147 motg_speed(uint8_t speed) 1148 { 1149 switch(speed) { 1150 case USB_SPEED_LOW: 1151 return MUSB2_MASK_TI_SPEED_LO; 1152 case USB_SPEED_FULL: 1153 return MUSB2_MASK_TI_SPEED_FS; 1154 case USB_SPEED_HIGH: 1155 return MUSB2_MASK_TI_SPEED_HS; 1156 default: 1157 panic("motg: unknown speed %d", speed); 1158 /* NOTREACHED */ 1159 } 1160 } 1161 1162 static uint8_t 1163 motg_type(uint8_t type) 1164 { 1165 switch(type) { 1166 case UE_CONTROL: 1167 return MUSB2_MASK_TI_PROTO_CTRL; 1168 case UE_ISOCHRONOUS: 1169 return MUSB2_MASK_TI_PROTO_ISOC; 1170 case UE_BULK: 1171 return MUSB2_MASK_TI_PROTO_BULK; 1172 case UE_INTERRUPT: 1173 return MUSB2_MASK_TI_PROTO_INTR; 1174 default: 1175 panic("motg: unknown type %d", type); 1176 /* NOTREACHED */ 1177 } 1178 } 1179 1180 static void 1181 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1182 { 1183 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1184 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1185 struct usbd_device *dev = otgpipe->pipe.up_dev; 1186 int epnumber = otgpipe->hw_ep->ep_number; 1187 1188 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1189 if (dev->ud_myhsport) { 1190 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1191 dev->ud_myhsport->up_parent->ud_addr); 1192 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1193 dev->ud_myhsport->up_portno); 1194 } else { 1195 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1196 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1197 } 1198 UWRITE1(sc, MUSB2_REG_TXTI, 1199 motg_speed(dev->ud_speed) | 1200 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1201 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1202 ); 1203 if (epnumber == 0) { 1204 if (sc->sc_high_speed) { 1205 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1206 NAK_TO_CTRL_HIGH); 1207 } else { 1208 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1209 } 1210 } else { 1211 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1212 == UE_BULK) { 1213 if (sc->sc_high_speed) { 1214 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1215 NAK_TO_BULK_HIGH); 1216 } else { 1217 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1218 } 1219 } else { 1220 if (sc->sc_high_speed) { 1221 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1222 } else { 1223 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1224 } 1225 } 1226 } 1227 } 1228 1229 static void 1230 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1231 { 1232 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1233 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1234 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1235 int epnumber = otgpipe->hw_ep->ep_number; 1236 1237 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1238 if (dev->ud_myhsport) { 1239 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1240 dev->ud_myhsport->up_parent->ud_addr); 1241 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1242 dev->ud_myhsport->up_portno); 1243 } else { 1244 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1245 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1246 } 1247 UWRITE1(sc, MUSB2_REG_RXTI, 1248 motg_speed(dev->ud_speed) | 1249 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1250 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1251 ); 1252 if (epnumber == 0) { 1253 if (sc->sc_high_speed) { 1254 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1255 NAK_TO_CTRL_HIGH); 1256 } else { 1257 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1258 } 1259 } else { 1260 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1261 == UE_BULK) { 1262 if (sc->sc_high_speed) { 1263 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1264 NAK_TO_BULK_HIGH); 1265 } else { 1266 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1267 } 1268 } else { 1269 if (sc->sc_high_speed) { 1270 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1271 } else { 1272 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1273 } 1274 } 1275 } 1276 } 1277 1278 static usbd_status 1279 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1280 { 1281 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1282 usbd_status err; 1283 1284 /* Insert last in queue. */ 1285 mutex_enter(&sc->sc_lock); 1286 err = usb_insert_transfer(xfer); 1287 xfer->ux_status = USBD_NOT_STARTED; 1288 mutex_exit(&sc->sc_lock); 1289 if (err) 1290 return err; 1291 1292 /* 1293 * Pipe isn't running (otherwise err would be USBD_INPROG), 1294 * so start it first. 1295 */ 1296 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1297 } 1298 1299 static usbd_status 1300 motg_device_ctrl_start(struct usbd_xfer *xfer) 1301 { 1302 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1303 usbd_status err; 1304 mutex_enter(&sc->sc_lock); 1305 err = motg_device_ctrl_start1(sc); 1306 mutex_exit(&sc->sc_lock); 1307 if (err != USBD_IN_PROGRESS) 1308 return err; 1309 return USBD_IN_PROGRESS; 1310 } 1311 1312 static usbd_status 1313 motg_device_ctrl_start1(struct motg_softc *sc) 1314 { 1315 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1316 struct usbd_xfer *xfer = NULL; 1317 struct motg_pipe *otgpipe; 1318 usbd_status err = 0; 1319 1320 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1321 1322 KASSERT(mutex_owned(&sc->sc_lock)); 1323 if (sc->sc_dying) 1324 return USBD_IOERROR; 1325 1326 if (!sc->sc_connected) 1327 return USBD_IOERROR; 1328 1329 if (ep->xfer != NULL) { 1330 err = USBD_IN_PROGRESS; 1331 goto end; 1332 } 1333 /* locate the first pipe with work to do */ 1334 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1335 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1336 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1337 (uintptr_t)otgpipe, (uintptr_t)xfer, 1338 (xfer != NULL) ? xfer->ux_status : 0, 0); 1339 1340 if (xfer != NULL) { 1341 /* move this pipe to the end of the list */ 1342 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1343 motg_pipe, ep_pipe_list); 1344 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1345 otgpipe, ep_pipe_list); 1346 break; 1347 } 1348 } 1349 if (xfer == NULL) { 1350 err = USBD_NOT_STARTED; 1351 goto end; 1352 } 1353 xfer->ux_status = USBD_IN_PROGRESS; 1354 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1355 KASSERT(otgpipe->hw_ep == ep); 1356 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1357 // KASSERT(xfer->ux_actlen == 0); 1358 xfer->ux_actlen = 0; 1359 1360 ep->xfer = xfer; 1361 ep->datalen = xfer->ux_length; 1362 if (ep->datalen > 0) 1363 ep->data = xfer->ux_buf; 1364 else 1365 ep->data = NULL; 1366 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1367 (ep->datalen % 64) == 0) 1368 ep->need_short_xfer = 1; 1369 else 1370 ep->need_short_xfer = 0; 1371 /* now we need send this request */ 1372 DPRINTFN(MD_CTRL, 1373 "xfer %#jx send data %#jx len %jd short %jd", 1374 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1375 ep->need_short_xfer); 1376 DPRINTFN(MD_CTRL, 1377 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1378 xfer->ux_pipe->up_dev->ud_speed, 1379 xfer->ux_pipe->up_dev->ud_addr, 0); 1380 KASSERT(ep->phase == IDLE); 1381 ep->phase = SETUP; 1382 /* select endpoint 0 */ 1383 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1384 /* fifo should be empty at this point */ 1385 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1386 /* send data */ 1387 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1388 KASSERT(sizeof(xfer->ux_request) == 8); 1389 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1390 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1391 1392 motg_setup_endpoint_tx(xfer); 1393 /* start transaction */ 1394 UWRITE1(sc, MUSB2_REG_TXCSRL, 1395 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1396 1397 end: 1398 if (err) 1399 return err; 1400 1401 return USBD_IN_PROGRESS; 1402 } 1403 1404 static void 1405 motg_device_ctrl_read(struct usbd_xfer *xfer) 1406 { 1407 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1408 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1409 /* assume endpoint already selected */ 1410 motg_setup_endpoint_rx(xfer); 1411 /* start transaction */ 1412 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1413 otgpipe->hw_ep->phase = DATA_IN; 1414 } 1415 1416 static void 1417 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1418 { 1419 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1420 struct usbd_xfer *xfer = ep->xfer; 1421 uint8_t csr; 1422 int datalen, max_datalen; 1423 char *data; 1424 bool got_short; 1425 usbd_status new_status = USBD_IN_PROGRESS; 1426 1427 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1428 1429 KASSERT(mutex_owned(&sc->sc_lock)); 1430 1431 /* 1432 * Try to claim this xfer for completion. If it has already 1433 * completed or aborted, drop it on the floor. 1434 */ 1435 if (!usbd_xfer_trycomplete(xfer)) 1436 return; 1437 1438 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1439 /* select endpoint 0 */ 1440 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1441 1442 /* read out FIFO status */ 1443 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1444 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1445 ep->phase, csr, (uintptr_t)xfer, 1446 (xfer != NULL) ? xfer->ux_status : 0); 1447 1448 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1449 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1450 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1451 1452 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1453 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1454 new_status = USBD_TIMEOUT; /* XXX */ 1455 goto complete; 1456 } 1457 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1458 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1459 new_status = USBD_STALLED; 1460 else 1461 new_status = USBD_IOERROR; 1462 /* clear status */ 1463 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1464 goto complete; 1465 } 1466 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1467 return; /* no data yet */ 1468 1469 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1470 goto complete; 1471 1472 if (ep->phase == STATUS_IN) { 1473 new_status = USBD_NORMAL_COMPLETION; 1474 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1475 goto complete; 1476 } 1477 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1478 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1479 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1480 max_datalen = uimin(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1481 ep->datalen); 1482 if (datalen > max_datalen) { 1483 new_status = USBD_IOERROR; 1484 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1485 goto complete; 1486 } 1487 got_short = (datalen < max_datalen); 1488 if (datalen > 0) { 1489 KASSERT(ep->phase == DATA_IN); 1490 data = ep->data; 1491 ep->data += datalen; 1492 ep->datalen -= datalen; 1493 xfer->ux_actlen += datalen; 1494 if (((vaddr_t)data & 0x3) == 0 && 1495 (datalen >> 2) > 0) { 1496 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1497 (uintptr_t)data, datalen, 0, 0); 1498 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1499 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1500 data += (datalen & ~0x3); 1501 datalen -= (datalen & ~0x3); 1502 } 1503 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1504 datalen, 0, 0); 1505 if (datalen) { 1506 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1507 MUSB2_REG_EPFIFO(0), data, datalen); 1508 } 1509 } 1510 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1511 KASSERT(ep->phase == DATA_IN); 1512 if (got_short || (ep->datalen == 0)) { 1513 if (ep->need_short_xfer == 0) { 1514 ep->phase = STATUS_OUT; 1515 UWRITE1(sc, MUSB2_REG_TXCSRH, 1516 UREAD1(sc, MUSB2_REG_TXCSRH) | 1517 MUSB2_MASK_CSR0H_PING_DIS); 1518 motg_setup_endpoint_tx(xfer); 1519 UWRITE1(sc, MUSB2_REG_TXCSRL, 1520 MUSB2_MASK_CSR0L_STATUSPKT | 1521 MUSB2_MASK_CSR0L_TXPKTRDY); 1522 return; 1523 } 1524 ep->need_short_xfer = 0; 1525 } 1526 motg_device_ctrl_read(xfer); 1527 return; 1528 complete: 1529 ep->phase = IDLE; 1530 ep->xfer = NULL; 1531 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1532 KASSERT(new_status != USBD_IN_PROGRESS); 1533 xfer->ux_status = new_status; 1534 usb_transfer_complete(xfer); 1535 } 1536 motg_device_ctrl_start1(sc); 1537 } 1538 1539 static void 1540 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1541 { 1542 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1543 struct usbd_xfer *xfer = ep->xfer; 1544 uint8_t csr; 1545 int datalen; 1546 char *data; 1547 usbd_status new_status = USBD_IN_PROGRESS; 1548 1549 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1550 1551 KASSERT(mutex_owned(&sc->sc_lock)); 1552 1553 /* 1554 * Try to claim this xfer for completion. If it has already 1555 * completed or aborted, drop it on the floor. 1556 */ 1557 if (!usbd_xfer_trycomplete(xfer)) 1558 return; 1559 1560 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1561 motg_device_ctrl_intr_rx(sc); 1562 return; 1563 } 1564 1565 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1566 ep->phase == STATUS_OUT); 1567 1568 /* select endpoint 0 */ 1569 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1570 1571 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1572 DPRINTFN(MD_CTRL, "phase %jd csr 0x%jx xfer %#jx status %jd", 1573 ep->phase, csr, (uintptr_t)xfer, 1574 (xfer != NULL) ? xfer->ux_status : 0); 1575 1576 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1577 /* command not accepted */ 1578 new_status = USBD_STALLED; 1579 /* clear status */ 1580 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1581 goto complete; 1582 } 1583 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1584 new_status = USBD_TIMEOUT; /* XXX */ 1585 /* flush fifo */ 1586 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1587 UWRITE1(sc, MUSB2_REG_TXCSRH, 1588 UREAD1(sc, MUSB2_REG_TXCSRH) | 1589 MUSB2_MASK_CSR0H_FFLUSH); 1590 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1591 } 1592 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1593 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1594 goto complete; 1595 } 1596 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1597 new_status = USBD_IOERROR; 1598 /* clear status */ 1599 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1600 goto complete; 1601 } 1602 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1603 /* data still not sent */ 1604 return; 1605 } 1606 if (xfer == NULL) 1607 goto complete; 1608 if (ep->phase == STATUS_OUT) { 1609 /* 1610 * we have sent status and got no error; 1611 * declare transfer complete 1612 */ 1613 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1614 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1615 new_status = USBD_NORMAL_COMPLETION; 1616 goto complete; 1617 } 1618 if (ep->datalen == 0) { 1619 if (ep->need_short_xfer) { 1620 ep->need_short_xfer = 0; 1621 /* one more data phase */ 1622 if (xfer->ux_request.bmRequestType & UT_READ) { 1623 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1624 (uintptr_t)xfer, 0, 0, 0); 1625 motg_device_ctrl_read(xfer); 1626 return; 1627 } /* else fall back to DATA_OUT */ 1628 } else { 1629 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh 0x%jx", 1630 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1631 0, 0); 1632 ep->phase = STATUS_IN; 1633 UWRITE1(sc, MUSB2_REG_RXCSRH, 1634 UREAD1(sc, MUSB2_REG_RXCSRH) | 1635 MUSB2_MASK_CSR0H_PING_DIS); 1636 motg_setup_endpoint_rx(xfer); 1637 UWRITE1(sc, MUSB2_REG_TXCSRL, 1638 MUSB2_MASK_CSR0L_STATUSPKT | 1639 MUSB2_MASK_CSR0L_REQPKT); 1640 return; 1641 } 1642 } 1643 if (xfer->ux_request.bmRequestType & UT_READ) { 1644 motg_device_ctrl_read(xfer); 1645 return; 1646 } 1647 /* setup a dataout phase */ 1648 datalen = uimin(ep->datalen, 1649 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1650 ep->phase = DATA_OUT; 1651 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh 0x%jx", (uintptr_t)xfer, 1652 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1653 if (datalen) { 1654 data = ep->data; 1655 ep->data += datalen; 1656 ep->datalen -= datalen; 1657 xfer->ux_actlen += datalen; 1658 if (((vaddr_t)data & 0x3) == 0 && 1659 (datalen >> 2) > 0) { 1660 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1661 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1662 data += (datalen & ~0x3); 1663 datalen -= (datalen & ~0x3); 1664 } 1665 if (datalen) { 1666 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1667 MUSB2_REG_EPFIFO(0), data, datalen); 1668 } 1669 } 1670 /* send data */ 1671 motg_setup_endpoint_tx(xfer); 1672 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1673 return; 1674 1675 complete: 1676 ep->phase = IDLE; 1677 ep->xfer = NULL; 1678 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 1679 KASSERT(new_status != USBD_IN_PROGRESS); 1680 xfer->ux_status = new_status; 1681 usb_transfer_complete(xfer); 1682 } 1683 motg_device_ctrl_start1(sc); 1684 } 1685 1686 /* Abort a device control request. */ 1687 void 1688 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1689 { 1690 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1691 1692 usbd_xfer_abort(xfer); 1693 } 1694 1695 /* Close a device control pipe */ 1696 void 1697 motg_device_ctrl_close(struct usbd_pipe *pipe) 1698 { 1699 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1700 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1701 struct motg_pipe *otgpipeiter; 1702 1703 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1704 1705 KASSERT(mutex_owned(&sc->sc_lock)); 1706 KASSERT(otgpipe->hw_ep->xfer == NULL || 1707 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1708 1709 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1710 if (otgpipeiter == otgpipe) { 1711 /* remove from list */ 1712 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1713 motg_pipe, ep_pipe_list); 1714 otgpipe->hw_ep->refcount--; 1715 /* we're done */ 1716 return; 1717 } 1718 } 1719 panic("motg_device_ctrl_close: not found"); 1720 } 1721 1722 void 1723 motg_device_ctrl_done(struct usbd_xfer *xfer) 1724 { 1725 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1726 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1727 1728 KASSERT(otgpipe->hw_ep->xfer != xfer); 1729 } 1730 1731 static usbd_status 1732 motg_device_data_transfer(struct usbd_xfer *xfer) 1733 { 1734 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1735 usbd_status err; 1736 1737 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1738 1739 /* Insert last in queue. */ 1740 mutex_enter(&sc->sc_lock); 1741 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1742 err = usb_insert_transfer(xfer); 1743 xfer->ux_status = USBD_NOT_STARTED; 1744 mutex_exit(&sc->sc_lock); 1745 if (err) 1746 return err; 1747 1748 /* 1749 * Pipe isn't running (otherwise err would be USBD_INPROG), 1750 * so start it first. 1751 */ 1752 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1753 } 1754 1755 static usbd_status 1756 motg_device_data_start(struct usbd_xfer *xfer) 1757 { 1758 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1759 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1760 usbd_status err; 1761 1762 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1763 1764 mutex_enter(&sc->sc_lock); 1765 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1766 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1767 mutex_exit(&sc->sc_lock); 1768 if (err != USBD_IN_PROGRESS) 1769 return err; 1770 return USBD_IN_PROGRESS; 1771 } 1772 1773 static usbd_status 1774 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1775 { 1776 struct usbd_xfer *xfer = NULL; 1777 struct motg_pipe *otgpipe; 1778 usbd_status err = 0; 1779 uint32_t val __diagused; 1780 1781 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1782 1783 KASSERT(mutex_owned(&sc->sc_lock)); 1784 if (sc->sc_dying) 1785 return USBD_IOERROR; 1786 1787 if (!sc->sc_connected) 1788 return USBD_IOERROR; 1789 1790 if (ep->xfer != NULL) { 1791 err = USBD_IN_PROGRESS; 1792 goto end; 1793 } 1794 /* locate the first pipe with work to do */ 1795 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1796 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1797 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1798 (uintptr_t)otgpipe, (uintptr_t)xfer, 1799 (xfer != NULL) ? xfer->ux_status : 0, 0); 1800 if (xfer != NULL) { 1801 /* move this pipe to the end of the list */ 1802 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1803 motg_pipe, ep_pipe_list); 1804 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1805 otgpipe, ep_pipe_list); 1806 break; 1807 } 1808 } 1809 if (xfer == NULL) { 1810 err = USBD_NOT_STARTED; 1811 goto end; 1812 } 1813 xfer->ux_status = USBD_IN_PROGRESS; 1814 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1815 KASSERT(otgpipe->hw_ep == ep); 1816 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1817 // KASSERT(xfer->ux_actlen == 0); 1818 xfer->ux_actlen = 0; 1819 1820 ep->xfer = xfer; 1821 ep->datalen = xfer->ux_length; 1822 KASSERT(ep->datalen > 0); 1823 ep->data = xfer->ux_buf; 1824 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1825 (ep->datalen % 64) == 0) 1826 ep->need_short_xfer = 1; 1827 else 1828 ep->need_short_xfer = 0; 1829 /* now we need send this request */ 1830 DPRINTFN(MD_BULK, 1831 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1832 "xfer %#jx in data %#jx len %jd short %jd" : 1833 "xfer %#jx out data %#jx len %jd short %jd", 1834 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1835 ep->need_short_xfer); 1836 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1837 xfer->ux_pipe->up_dev->ud_speed, 1838 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1839 KASSERT(ep->phase == IDLE); 1840 /* select endpoint */ 1841 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1842 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1843 == UE_DIR_IN) { 1844 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1845 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1846 motg_device_data_read(xfer); 1847 } else { 1848 ep->phase = DATA_OUT; 1849 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1850 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1851 motg_device_data_write(xfer); 1852 } 1853 end: 1854 if (err) 1855 return err; 1856 1857 return USBD_IN_PROGRESS; 1858 } 1859 1860 static void 1861 motg_device_data_read(struct usbd_xfer *xfer) 1862 { 1863 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1864 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1865 uint32_t val; 1866 1867 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1868 1869 KASSERT(mutex_owned(&sc->sc_lock)); 1870 /* assume endpoint already selected */ 1871 motg_setup_endpoint_rx(xfer); 1872 /* Max packet size */ 1873 UWRITE2(sc, MUSB2_REG_RXMAXP, 1874 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1875 /* Data Toggle */ 1876 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1877 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1878 if (otgpipe->nexttoggle) 1879 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1880 else 1881 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1882 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1883 1884 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh 0x%jx", 1885 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1886 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1887 /* start transaction */ 1888 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1889 otgpipe->hw_ep->phase = DATA_IN; 1890 } 1891 1892 static void 1893 motg_device_data_write(struct usbd_xfer *xfer) 1894 { 1895 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1896 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1897 struct motg_hw_ep *ep = otgpipe->hw_ep; 1898 int datalen; 1899 char *data; 1900 uint32_t val; 1901 1902 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1903 1904 KASSERT(xfer!=NULL); 1905 KASSERT(mutex_owned(&sc->sc_lock)); 1906 1907 datalen = uimin(ep->datalen, 1908 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1909 ep->phase = DATA_OUT; 1910 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh 0x%jx", 1911 (uintptr_t)xfer, ep->ep_number, datalen, 1912 UREAD1(sc, MUSB2_REG_TXCSRH)); 1913 1914 /* assume endpoint already selected */ 1915 /* write data to fifo */ 1916 data = ep->data; 1917 ep->data += datalen; 1918 ep->datalen -= datalen; 1919 xfer->ux_actlen += datalen; 1920 if (((vaddr_t)data & 0x3) == 0 && 1921 (datalen >> 2) > 0) { 1922 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1923 MUSB2_REG_EPFIFO(ep->ep_number), 1924 (void *)data, datalen >> 2); 1925 data += (datalen & ~0x3); 1926 datalen -= (datalen & ~0x3); 1927 } 1928 if (datalen) { 1929 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1930 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1931 } 1932 1933 motg_setup_endpoint_tx(xfer); 1934 /* Max packet size */ 1935 UWRITE2(sc, MUSB2_REG_TXMAXP, 1936 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1937 /* Data Toggle */ 1938 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1939 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1940 if (otgpipe->nexttoggle) 1941 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1942 else 1943 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1944 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1945 1946 /* start transaction */ 1947 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1948 } 1949 1950 static void 1951 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1952 { 1953 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1954 struct usbd_xfer *xfer = ep->xfer; 1955 uint8_t csr; 1956 int datalen, max_datalen; 1957 char *data; 1958 bool got_short; 1959 usbd_status new_status = USBD_IN_PROGRESS; 1960 1961 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1962 1963 KASSERT(mutex_owned(&sc->sc_lock)); 1964 KASSERT(ep->ep_number == epnumber); 1965 1966 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1967 /* select endpoint */ 1968 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1969 1970 /* read out FIFO status */ 1971 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1972 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr ,0 ,0); 1973 1974 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1975 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1976 return; 1977 1978 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1979 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1980 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1981 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1982 1983 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1984 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1985 new_status = USBD_TIMEOUT; /* XXX */ 1986 goto complete; 1987 } 1988 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1989 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1990 new_status = USBD_STALLED; 1991 else 1992 new_status = USBD_IOERROR; 1993 /* clear status */ 1994 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1995 goto complete; 1996 } 1997 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 1998 1999 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 2000 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2001 goto complete; 2002 } 2003 2004 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2005 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2006 2007 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2008 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 2009 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 2010 max_datalen = uimin( 2011 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 2012 ep->datalen); 2013 if (datalen > max_datalen) { 2014 new_status = USBD_IOERROR; 2015 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2016 goto complete; 2017 } 2018 got_short = (datalen < max_datalen); 2019 if (datalen > 0) { 2020 KASSERT(ep->phase == DATA_IN); 2021 data = ep->data; 2022 ep->data += datalen; 2023 ep->datalen -= datalen; 2024 xfer->ux_actlen += datalen; 2025 if (((vaddr_t)data & 0x3) == 0 && 2026 (datalen >> 2) > 0) { 2027 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 2028 (uintptr_t)data, datalen, 0, 0); 2029 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2030 MUSB2_REG_EPFIFO(ep->ep_number), 2031 (void *)data, datalen >> 2); 2032 data += (datalen & ~0x3); 2033 datalen -= (datalen & ~0x3); 2034 } 2035 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 2036 datalen ,0 ,0); 2037 if (datalen) { 2038 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2039 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2040 } 2041 } 2042 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2043 KASSERT(ep->phase == DATA_IN); 2044 if (got_short || (ep->datalen == 0)) { 2045 if (ep->need_short_xfer == 0) { 2046 new_status = USBD_NORMAL_COMPLETION; 2047 goto complete; 2048 } 2049 ep->need_short_xfer = 0; 2050 } 2051 motg_device_data_read(xfer); 2052 return; 2053 complete: 2054 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2055 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2056 ep->phase = IDLE; 2057 ep->xfer = NULL; 2058 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2059 KASSERT(new_status != USBD_IN_PROGRESS); 2060 xfer->ux_status = new_status; 2061 usb_transfer_complete(xfer); 2062 } 2063 motg_device_data_start1(sc, ep); 2064 } 2065 2066 static void 2067 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2068 { 2069 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2070 struct usbd_xfer *xfer = ep->xfer; 2071 uint8_t csr; 2072 struct motg_pipe *otgpipe; 2073 usbd_status new_status = USBD_IN_PROGRESS; 2074 2075 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2076 2077 KASSERT(mutex_owned(&sc->sc_lock)); 2078 2079 /* 2080 * Try to claim this xfer for completion. If it has already 2081 * completed or aborted, drop it on the floor. 2082 */ 2083 if (!usbd_xfer_trycomplete(xfer)) 2084 return; 2085 2086 KASSERT(ep->ep_number == epnumber); 2087 2088 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2089 /* select endpoint */ 2090 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2091 2092 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2093 DPRINTFN(MD_BULK, "phase %jd csr 0x%jx", ep->phase, csr, 0, 0); 2094 2095 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2096 /* command not accepted */ 2097 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2098 new_status = USBD_STALLED; 2099 else 2100 new_status = USBD_IOERROR; 2101 /* clear status */ 2102 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2103 goto complete; 2104 } 2105 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2106 new_status = USBD_TIMEOUT; /* XXX */ 2107 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2108 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2109 /* flush fifo */ 2110 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2111 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2112 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2113 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2114 delay(1000); 2115 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2116 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR 0x%jx", 2117 epnumber, csr, 0, 0); 2118 } 2119 goto complete; 2120 } 2121 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2122 /* data still not sent */ 2123 return; 2124 } 2125 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2126 goto complete; 2127 KASSERT(ep->phase == DATA_OUT); 2128 2129 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2130 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2131 2132 if (ep->datalen == 0) { 2133 if (ep->need_short_xfer) { 2134 ep->need_short_xfer = 0; 2135 /* one more data phase */ 2136 } else { 2137 new_status = USBD_NORMAL_COMPLETION; 2138 goto complete; 2139 } 2140 } 2141 motg_device_data_write(xfer); 2142 return; 2143 2144 complete: 2145 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2146 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2147 KASSERTMSG(xfer && xfer->ux_status == USBD_IN_PROGRESS && 2148 ep->phase == DATA_OUT, "xfer %p status %d phase %d", 2149 xfer, xfer->ux_status, ep->phase); 2150 ep->phase = IDLE; 2151 ep->xfer = NULL; 2152 if (xfer && xfer->ux_status == USBD_IN_PROGRESS) { 2153 KASSERT(new_status != USBD_IN_PROGRESS); 2154 xfer->ux_status = new_status; 2155 usb_transfer_complete(xfer); 2156 } 2157 motg_device_data_start1(sc, ep); 2158 } 2159 2160 /* Abort a device control request. */ 2161 void 2162 motg_device_data_abort(struct usbd_xfer *xfer) 2163 { 2164 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2165 KASSERT(mutex_owned(&sc->sc_lock)); 2166 2167 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2168 2169 usbd_xfer_abort(xfer); 2170 } 2171 2172 /* Close a device control pipe */ 2173 void 2174 motg_device_data_close(struct usbd_pipe *pipe) 2175 { 2176 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2177 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2178 struct motg_pipe *otgpipeiter; 2179 2180 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2181 2182 KASSERT(mutex_owned(&sc->sc_lock)); 2183 KASSERT(otgpipe->hw_ep->xfer == NULL || 2184 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2185 2186 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2187 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2188 if (otgpipeiter == otgpipe) { 2189 /* remove from list */ 2190 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2191 motg_pipe, ep_pipe_list); 2192 otgpipe->hw_ep->refcount--; 2193 /* we're done */ 2194 return; 2195 } 2196 } 2197 panic("motg_device_data_close: not found"); 2198 } 2199 2200 void 2201 motg_device_data_done(struct usbd_xfer *xfer) 2202 { 2203 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2204 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2205 2206 KASSERT(otgpipe->hw_ep->xfer != xfer); 2207 } 2208 2209 void 2210 motg_device_clear_toggle(struct usbd_pipe *pipe) 2211 { 2212 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2213 otgpipe->nexttoggle = 0; 2214 } 2215 2216 /* Abort a device control request. */ 2217 static void 2218 motg_abortx(struct usbd_xfer *xfer) 2219 { 2220 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2221 uint8_t csr; 2222 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2223 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2224 2225 KASSERT(mutex_owned(&sc->sc_lock)); 2226 ASSERT_SLEEPABLE(); 2227 2228 /* 2229 * If we're dying, skip the hardware action and just notify the 2230 * software that we're done. 2231 */ 2232 if (sc->sc_dying) { 2233 goto dying; 2234 } 2235 2236 if (otgpipe->hw_ep->xfer == xfer) { 2237 otgpipe->hw_ep->xfer = NULL; 2238 if (otgpipe->hw_ep->ep_number > 0) { 2239 /* select endpoint */ 2240 UWRITE1(sc, MUSB2_REG_EPINDEX, 2241 otgpipe->hw_ep->ep_number); 2242 if (otgpipe->hw_ep->phase == DATA_OUT) { 2243 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2244 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2245 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2246 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2247 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2248 } 2249 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2250 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2251 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2252 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2253 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2254 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2255 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2256 } 2257 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2258 } 2259 otgpipe->hw_ep->phase = IDLE; 2260 } 2261 } 2262 dying: 2263 usb_transfer_complete(xfer); 2264 KASSERT(mutex_owned(&sc->sc_lock)); 2265 } 2266
Indexes created Mon Oct 13 08:09:50 GMT 2025