motg.c revision 1.36
1 /* $NetBSD: motg.c,v 1.36 2021/04/24 23:36:59 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.36 2021/04/24 23:36:59 thorpej Exp $"); 44 45 #ifdef _KERNEL_OPT 46 #include "opt_usb.h" 47 #endif 48 49 #include <sys/param.h> 50 51 #include <sys/bus.h> 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usbhist.h> 69 70 #include <dev/usb/motgreg.h> 71 #include <dev/usb/motgvar.h> 72 #include <dev/usb/usbroothub.h> 73 74 #ifdef USB_DEBUG 75 #ifndef MOTG_DEBUG 76 #define motgdebug 0 77 #else 78 int motgdebug = 0; 79 80 SYSCTL_SETUP(sysctl_hw_motg_setup, "sysctl hw.motg setup") 81 { 82 int err; 83 const struct sysctlnode *rnode; 84 const struct sysctlnode *cnode; 85 86 err = sysctl_createv(clog, 0, NULL, &rnode, 87 CTLFLAG_PERMANENT, CTLTYPE_NODE, "motg", 88 SYSCTL_DESCR("motg global controls"), 89 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 90 91 if (err) 92 goto fail; 93 94 /* control debugging printfs */ 95 err = sysctl_createv(clog, 0, &rnode, &cnode, 96 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 97 "debug", SYSCTL_DESCR("Enable debugging output"), 98 NULL, 0, &motgdebug, sizeof(motgdebug), CTL_CREATE, CTL_EOL); 99 if (err) 100 goto fail; 101 102 return; 103 fail: 104 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 105 } 106 107 #endif /* MOTG_DEBUG */ 108 #endif /* USB_DEBUG */ 109 110 #define MD_ROOT 0x0002 111 #define MD_CTRL 0x0004 112 #define MD_BULK 0x0008 113 114 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOGN(motgdebug,1,FMT,A,B,C,D) 115 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGM(motgdebug,N,FMT,A,B,C,D) 116 #define MOTGHIST_FUNC() USBHIST_FUNC() 117 #define MOTGHIST_CALLED(name) USBHIST_CALLED(motgdebug) 118 119 120 /* various timeouts, for various speeds */ 121 /* control NAK timeouts */ 122 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 123 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 124 125 /* intr/iso polling intervals */ 126 #define POLL_TO 100 /* 100 frames, about 0.1s */ 127 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 128 129 /* bulk NAK timeouts */ 130 #define NAK_TO_BULK 0 /* disabled */ 131 #define NAK_TO_BULK_HIGH 0 132 133 static void motg_hub_change(struct motg_softc *); 134 135 static usbd_status motg_root_intr_transfer(struct usbd_xfer *); 136 static usbd_status motg_root_intr_start(struct usbd_xfer *); 137 static void motg_root_intr_abort(struct usbd_xfer *); 138 static void motg_root_intr_close(struct usbd_pipe *); 139 static void motg_root_intr_done(struct usbd_xfer *); 140 141 static usbd_status motg_open(struct usbd_pipe *); 142 static void motg_poll(struct usbd_bus *); 143 static void motg_softintr(void *); 144 static struct usbd_xfer * 145 motg_allocx(struct usbd_bus *, unsigned int); 146 static void motg_freex(struct usbd_bus *, struct usbd_xfer *); 147 static bool motg_dying(struct usbd_bus *); 148 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 149 static int motg_roothub_ctrl(struct usbd_bus *, usb_device_request_t *, 150 void *, int); 151 152 static void motg_noop(struct usbd_pipe *pipe); 153 static usbd_status motg_portreset(struct motg_softc*); 154 155 static usbd_status motg_device_ctrl_transfer(struct usbd_xfer *); 156 static usbd_status motg_device_ctrl_start(struct usbd_xfer *); 157 static void motg_device_ctrl_abort(struct usbd_xfer *); 158 static void motg_device_ctrl_close(struct usbd_pipe *); 159 static void motg_device_ctrl_done(struct usbd_xfer *); 160 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 161 static void motg_device_ctrl_read(struct usbd_xfer *); 162 static void motg_device_ctrl_intr_rx(struct motg_softc *); 163 static void motg_device_ctrl_intr_tx(struct motg_softc *); 164 165 static usbd_status motg_device_data_transfer(struct usbd_xfer *); 166 static usbd_status motg_device_data_start(struct usbd_xfer *); 167 static usbd_status motg_device_data_start1(struct motg_softc *, 168 struct motg_hw_ep *); 169 static void motg_device_data_abort(struct usbd_xfer *); 170 static void motg_device_data_close(struct usbd_pipe *); 171 static void motg_device_data_done(struct usbd_xfer *); 172 static void motg_device_intr_rx(struct motg_softc *, int); 173 static void motg_device_intr_tx(struct motg_softc *, int); 174 static void motg_device_data_read(struct usbd_xfer *); 175 static void motg_device_data_write(struct usbd_xfer *); 176 177 static void motg_device_clear_toggle(struct usbd_pipe *); 178 static void motg_abortx(struct usbd_xfer *); 179 180 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 181 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 182 #define UWRITE1(sc, r, x) \ 183 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 184 } while (/*CONSTCOND*/0) 185 #define UWRITE2(sc, r, x) \ 186 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 187 } while (/*CONSTCOND*/0) 188 #define UWRITE4(sc, r, x) \ 189 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 190 } while (/*CONSTCOND*/0) 191 192 static __inline uint32_t 193 UREAD1(struct motg_softc *sc, bus_size_t r) 194 { 195 196 UBARR(sc); 197 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 198 } 199 static __inline uint32_t 200 UREAD2(struct motg_softc *sc, bus_size_t r) 201 { 202 203 UBARR(sc); 204 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 205 } 206 207 #if 0 208 static __inline uint32_t 209 UREAD4(struct motg_softc *sc, bus_size_t r) 210 { 211 212 UBARR(sc); 213 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 214 } 215 #endif 216 217 static void 218 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 219 { 220 uint8_t val; 221 222 val = UREAD1(sc, MUSB2_REG_POWER); 223 if (on) 224 val |= MUSB2_MASK_SOFTC; 225 else 226 val &= ~MUSB2_MASK_SOFTC; 227 228 UWRITE1(sc, MUSB2_REG_POWER, val); 229 } 230 231 const struct usbd_bus_methods motg_bus_methods = { 232 .ubm_open = motg_open, 233 .ubm_softint = motg_softintr, 234 .ubm_dopoll = motg_poll, 235 .ubm_allocx = motg_allocx, 236 .ubm_freex = motg_freex, 237 .ubm_abortx = motg_abortx, 238 .ubm_dying = motg_dying, 239 .ubm_getlock = motg_get_lock, 240 .ubm_rhctrl = motg_roothub_ctrl, 241 }; 242 243 const struct usbd_pipe_methods motg_root_intr_methods = { 244 .upm_transfer = motg_root_intr_transfer, 245 .upm_start = motg_root_intr_start, 246 .upm_abort = motg_root_intr_abort, 247 .upm_close = motg_root_intr_close, 248 .upm_cleartoggle = motg_noop, 249 .upm_done = motg_root_intr_done, 250 }; 251 252 const struct usbd_pipe_methods motg_device_ctrl_methods = { 253 .upm_transfer = motg_device_ctrl_transfer, 254 .upm_start = motg_device_ctrl_start, 255 .upm_abort = motg_device_ctrl_abort, 256 .upm_close = motg_device_ctrl_close, 257 .upm_cleartoggle = motg_noop, 258 .upm_done = motg_device_ctrl_done, 259 }; 260 261 const struct usbd_pipe_methods motg_device_data_methods = { 262 .upm_transfer = motg_device_data_transfer, 263 .upm_start = motg_device_data_start, 264 .upm_abort = motg_device_data_abort, 265 .upm_close = motg_device_data_close, 266 .upm_cleartoggle = motg_device_clear_toggle, 267 .upm_done = motg_device_data_done, 268 }; 269 270 int 271 motg_init(struct motg_softc *sc) 272 { 273 uint32_t nrx, ntx, val; 274 int dynfifo; 275 int offset, i; 276 277 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 278 279 if (sc->sc_mode == MOTG_MODE_DEVICE) 280 return ENOTSUP; /* not supported */ 281 282 /* disable all interrupts */ 283 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 284 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 285 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 286 /* disable pullup */ 287 288 musbotg_pull_common(sc, 0); 289 290 #ifdef MUSB2_REG_RXDBDIS 291 /* disable double packet buffering XXX what's this ? */ 292 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 293 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 294 #endif 295 296 /* enable HighSpeed and ISO Update flags */ 297 298 UWRITE1(sc, MUSB2_REG_POWER, 299 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 300 301 if (sc->sc_mode == MOTG_MODE_DEVICE) { 302 /* clear Session bit, if set */ 303 val = UREAD1(sc, MUSB2_REG_DEVCTL); 304 val &= ~MUSB2_MASK_SESS; 305 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 306 } else { 307 /* Enter session for Host mode */ 308 val = UREAD1(sc, MUSB2_REG_DEVCTL); 309 val |= MUSB2_MASK_SESS; 310 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 311 } 312 delay(1000); 313 DPRINTF("DEVCTL %#jx", UREAD1(sc, MUSB2_REG_DEVCTL), 0, 0, 0); 314 315 /* disable testmode */ 316 317 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 318 319 #ifdef MUSB2_REG_MISC 320 /* set default value */ 321 322 UWRITE1(sc, MUSB2_REG_MISC, 0); 323 #endif 324 325 /* select endpoint index 0 */ 326 327 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 328 329 if (sc->sc_ep_max == 0) { 330 /* read out number of endpoints */ 331 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 332 333 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 334 335 /* these numbers exclude the control endpoint */ 336 337 DPRINTFN(1,"RX/TX endpoints: %ju/%ju", nrx, ntx, 0, 0); 338 339 sc->sc_ep_max = MAX(nrx, ntx); 340 } else { 341 nrx = ntx = sc->sc_ep_max; 342 } 343 if (sc->sc_ep_max == 0) { 344 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 345 return -1; 346 } 347 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 348 /* read out configuration data */ 349 val = UREAD1(sc, MUSB2_REG_CONFDATA); 350 351 DPRINTF("Config Data: 0x%02jx", val, 0, 0, 0); 352 353 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 354 355 if (dynfifo) { 356 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 357 "assuming 16Kbytes of FIFO RAM\n"); 358 } 359 360 DPRINTF("HW version: 0x%04jx\n", UREAD1(sc, MUSB2_REG_HWVERS), 0, 0, 0); 361 362 /* initialise endpoint profiles */ 363 sc->sc_in_ep[0].ep_fifo_size = 64; 364 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 365 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 366 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 367 offset = 64; 368 369 for (i = 1; i <= sc->sc_ep_max; i++) { 370 int fiforx_size, fifotx_size, fifo_size; 371 372 /* select endpoint */ 373 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 374 375 if (sc->sc_ep_fifosize) { 376 fiforx_size = fifotx_size = sc->sc_ep_fifosize; 377 } else { 378 val = UREAD1(sc, MUSB2_REG_FSIZE); 379 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 380 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 381 } 382 383 DPRINTF("Endpoint %ju FIFO size: IN=%ju, OUT=%ju, DYN=%jd", 384 i, fifotx_size, fiforx_size, dynfifo); 385 386 if (dynfifo) { 387 if (sc->sc_ep_fifosize) { 388 fifo_size = ffs(sc->sc_ep_fifosize) - 1; 389 } else { 390 if (i < 3) { 391 fifo_size = 12; /* 4K */ 392 } else if (i < 10) { 393 fifo_size = 10; /* 1K */ 394 } else { 395 fifo_size = 7; /* 128 bytes */ 396 } 397 } 398 if (fiforx_size && (i <= nrx)) { 399 fiforx_size = fifo_size; 400 if (fifo_size > 7) { 401 #if 0 402 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 403 MUSB2_VAL_FIFOSZ(fifo_size) | 404 MUSB2_MASK_FIFODB); 405 #else 406 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 407 MUSB2_VAL_FIFOSZ(fifo_size)); 408 #endif 409 } else { 410 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 411 MUSB2_VAL_FIFOSZ(fifo_size)); 412 } 413 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 414 offset >> 3); 415 offset += (1 << fiforx_size); 416 } 417 if (fifotx_size && (i <= ntx)) { 418 fifotx_size = fifo_size; 419 if (fifo_size > 7) { 420 #if 0 421 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 422 MUSB2_VAL_FIFOSZ(fifo_size) | 423 MUSB2_MASK_FIFODB); 424 #else 425 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 426 MUSB2_VAL_FIFOSZ(fifo_size)); 427 #endif 428 } else { 429 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 430 MUSB2_VAL_FIFOSZ(fifo_size)); 431 } 432 433 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 434 offset >> 3); 435 436 offset += (1 << fifotx_size); 437 } 438 } 439 if (fiforx_size && (i <= nrx)) { 440 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 441 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 442 } 443 if (fifotx_size && (i <= ntx)) { 444 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 445 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 446 } 447 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 448 } 449 450 451 DPRINTF("Dynamic FIFO size = %jd bytes", offset, 0, 0, 0); 452 453 /* turn on default interrupts */ 454 455 if (sc->sc_mode == MOTG_MODE_HOST) { 456 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 457 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 458 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 459 } else 460 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 461 462 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 463 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 464 465 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 466 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.ub_methods = &motg_bus_methods; 470 sc->sc_bus.ub_pipesize= sizeof(struct motg_pipe); 471 sc->sc_bus.ub_revision = USBREV_2_0; 472 sc->sc_bus.ub_usedma = false; 473 sc->sc_bus.ub_hcpriv = sc; 474 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint, 475 CFARG_EOL); 476 return 0; 477 } 478 479 static int 480 motg_select_ep(struct motg_softc *sc, struct usbd_pipe *pipe) 481 { 482 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 483 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 484 struct motg_hw_ep *ep; 485 int i, size; 486 487 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 488 489 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 490 sc->sc_in_ep : sc->sc_out_ep; 491 size = UE_GET_SIZE(UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 492 493 for (i = sc->sc_ep_max; i >= 1; i--) { 494 DPRINTF(UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN ? 495 "in_ep[%jd].ep_fifo_size %jd size %jd ref %jd" : 496 "out_ep[%jd].ep_fifo_size %jd size %jd ref %jd", i, 497 ep[i].ep_fifo_size, size, ep[i].refcount); 498 if (ep[i].ep_fifo_size >= size) { 499 /* found a suitable endpoint */ 500 otgpipe->hw_ep = &ep[i]; 501 mutex_enter(&sc->sc_lock); 502 if (otgpipe->hw_ep->refcount > 0) { 503 /* no luck, try next */ 504 mutex_exit(&sc->sc_lock); 505 otgpipe->hw_ep = NULL; 506 } else { 507 otgpipe->hw_ep->refcount++; 508 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 509 otgpipe, ep_pipe_list); 510 mutex_exit(&sc->sc_lock); 511 return 0; 512 } 513 } 514 } 515 return -1; 516 } 517 518 /* Open a new pipe. */ 519 usbd_status 520 motg_open(struct usbd_pipe *pipe) 521 { 522 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 523 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 524 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 525 uint8_t rhaddr = pipe->up_dev->ud_bus->ub_rhaddr; 526 527 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 528 529 DPRINTF("pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 530 pipe->up_dev->ud_addr, ed->bEndpointAddress, rhaddr); 531 532 if (sc->sc_dying) 533 return USBD_IOERROR; 534 535 /* toggle state needed for bulk endpoints */ 536 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 537 538 if (pipe->up_dev->ud_addr == rhaddr) { 539 switch (ed->bEndpointAddress) { 540 case USB_CONTROL_ENDPOINT: 541 pipe->up_methods = &roothub_ctrl_methods; 542 break; 543 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 544 pipe->up_methods = &motg_root_intr_methods; 545 break; 546 default: 547 return USBD_INVAL; 548 } 549 } else { 550 switch (ed->bmAttributes & UE_XFERTYPE) { 551 case UE_CONTROL: 552 pipe->up_methods = &motg_device_ctrl_methods; 553 /* always use sc_in_ep[0] for in and out */ 554 otgpipe->hw_ep = &sc->sc_in_ep[0]; 555 mutex_enter(&sc->sc_lock); 556 otgpipe->hw_ep->refcount++; 557 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 558 otgpipe, ep_pipe_list); 559 mutex_exit(&sc->sc_lock); 560 break; 561 case UE_BULK: 562 case UE_INTERRUPT: 563 DPRINTFN(MD_BULK, 564 "type %jd dir %jd pipe wMaxPacketSize %jd", 565 UE_GET_XFERTYPE(ed->bmAttributes), 566 UE_GET_DIR(pipe->up_endpoint->ue_edesc->bEndpointAddress), 567 UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize), 0); 568 if (motg_select_ep(sc, pipe) != 0) 569 goto bad; 570 KASSERT(otgpipe->hw_ep != NULL); 571 pipe->up_methods = &motg_device_data_methods; 572 otgpipe->nexttoggle = pipe->up_endpoint->ue_toggle; 573 break; 574 default: 575 goto bad; 576 #ifdef notyet 577 case UE_ISOCHRONOUS: 578 ... 579 break; 580 #endif /* notyet */ 581 } 582 } 583 return USBD_NORMAL_COMPLETION; 584 585 bad: 586 return USBD_NOMEM; 587 } 588 589 void 590 motg_softintr(void *v) 591 { 592 struct usbd_bus *bus = v; 593 struct motg_softc *sc = MOTG_BUS2SC(bus); 594 uint16_t rx_status, tx_status; 595 uint8_t ctrl_status; 596 uint32_t val; 597 int i; 598 599 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 600 601 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 602 603 DPRINTFN(MD_ROOT | MD_CTRL, "sc %#jx", (uintptr_t)sc, 0 ,0 ,0); 604 605 mutex_spin_enter(&sc->sc_intr_lock); 606 rx_status = sc->sc_intr_rx_ep; 607 sc->sc_intr_rx_ep = 0; 608 tx_status = sc->sc_intr_tx_ep; 609 sc->sc_intr_tx_ep = 0; 610 ctrl_status = sc->sc_intr_ctrl; 611 sc->sc_intr_ctrl = 0; 612 mutex_spin_exit(&sc->sc_intr_lock); 613 614 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 615 616 if (ctrl_status & (MUSB2_MASK_IRESET | 617 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 618 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 619 DPRINTFN(MD_ROOT | MD_CTRL, "bus %#jx", ctrl_status, 0, 0, 0); 620 621 if (ctrl_status & MUSB2_MASK_IRESET) { 622 sc->sc_isreset = 1; 623 sc->sc_port_suspended = 0; 624 sc->sc_port_suspended_change = 1; 625 sc->sc_connected_changed = 1; 626 sc->sc_port_enabled = 1; 627 628 val = UREAD1(sc, MUSB2_REG_POWER); 629 if (val & MUSB2_MASK_HSMODE) 630 sc->sc_high_speed = 1; 631 else 632 sc->sc_high_speed = 0; 633 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 634 0, 0, 0); 635 636 /* turn off interrupts */ 637 val = MUSB2_MASK_IRESET; 638 val &= ~MUSB2_MASK_IRESUME; 639 val |= MUSB2_MASK_ISUSP; 640 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 641 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 642 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 643 } 644 if (ctrl_status & MUSB2_MASK_IRESUME) { 645 if (sc->sc_port_suspended) { 646 sc->sc_port_suspended = 0; 647 sc->sc_port_suspended_change = 1; 648 val = UREAD1(sc, MUSB2_REG_INTUSBE); 649 /* disable resume interrupt */ 650 val &= ~MUSB2_MASK_IRESUME; 651 /* enable suspend interrupt */ 652 val |= MUSB2_MASK_ISUSP; 653 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 654 } 655 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 656 if (!sc->sc_port_suspended) { 657 sc->sc_port_suspended = 1; 658 sc->sc_port_suspended_change = 1; 659 660 val = UREAD1(sc, MUSB2_REG_INTUSBE); 661 /* disable suspend interrupt */ 662 val &= ~MUSB2_MASK_ISUSP; 663 /* enable resume interrupt */ 664 val |= MUSB2_MASK_IRESUME; 665 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 666 } 667 } 668 if (ctrl_status & MUSB2_MASK_ICONN) { 669 sc->sc_connected = 1; 670 sc->sc_connected_changed = 1; 671 sc->sc_isreset = 1; 672 sc->sc_port_enabled = 1; 673 } else if (ctrl_status & MUSB2_MASK_IDISC) { 674 sc->sc_connected = 0; 675 sc->sc_connected_changed = 1; 676 sc->sc_isreset = 0; 677 sc->sc_port_enabled = 0; 678 } 679 680 /* complete root HUB interrupt endpoint */ 681 682 motg_hub_change(sc); 683 } 684 /* 685 * read in interrupt status and mix with the status we 686 * got from the wrapper 687 */ 688 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 689 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 690 691 KASSERTMSG((rx_status & 0x01) == 0, "ctrl_rx %08x", rx_status); 692 if (tx_status & 0x01) 693 motg_device_ctrl_intr_tx(sc); 694 for (i = 1; i <= sc->sc_ep_max; i++) { 695 if (rx_status & (0x01 << i)) 696 motg_device_intr_rx(sc, i); 697 if (tx_status & (0x01 << i)) 698 motg_device_intr_tx(sc, i); 699 } 700 return; 701 } 702 703 void 704 motg_poll(struct usbd_bus *bus) 705 { 706 struct motg_softc *sc = MOTG_BUS2SC(bus); 707 708 sc->sc_intr_poll(sc->sc_intr_poll_arg); 709 mutex_enter(&sc->sc_lock); 710 motg_softintr(bus); 711 mutex_exit(&sc->sc_lock); 712 } 713 714 int 715 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 716 uint8_t ctrl) 717 { 718 KASSERT(mutex_owned(&sc->sc_intr_lock)); 719 sc->sc_intr_tx_ep = tx_ep; 720 sc->sc_intr_rx_ep = rx_ep; 721 sc->sc_intr_ctrl = ctrl; 722 723 if (!sc->sc_bus.ub_usepolling) { 724 usb_schedsoftintr(&sc->sc_bus); 725 } 726 return 1; 727 } 728 729 int 730 motg_intr_vbus(struct motg_softc *sc, int vbus) 731 { 732 uint8_t val; 733 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 734 735 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 736 DPRINTF("vbus down, try to re-enable", 0, 0, 0, 0); 737 /* try to re-enter session for Host mode */ 738 val = UREAD1(sc, MUSB2_REG_DEVCTL); 739 val |= MUSB2_MASK_SESS; 740 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 741 } 742 return 1; 743 } 744 745 struct usbd_xfer * 746 motg_allocx(struct usbd_bus *bus, unsigned int nframes) 747 { 748 struct motg_softc *sc = MOTG_BUS2SC(bus); 749 struct usbd_xfer *xfer; 750 751 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 752 if (xfer != NULL) { 753 memset(xfer, 0, sizeof(struct motg_xfer)); 754 #ifdef DIAGNOSTIC 755 xfer->ux_state = XFER_BUSY; 756 #endif 757 } 758 return xfer; 759 } 760 761 void 762 motg_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 763 { 764 struct motg_softc *sc = MOTG_BUS2SC(bus); 765 766 #ifdef DIAGNOSTIC 767 if (xfer->ux_state != XFER_BUSY && 768 xfer->ux_status != USBD_NOT_STARTED) { 769 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 770 xfer->ux_state); 771 } 772 xfer->ux_state = XFER_FREE; 773 #endif 774 pool_cache_put(sc->sc_xferpool, xfer); 775 } 776 777 static bool 778 motg_dying(struct usbd_bus *bus) 779 { 780 struct motg_softc *sc = MOTG_BUS2SC(bus); 781 782 return sc->sc_dying; 783 } 784 785 static void 786 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 787 { 788 struct motg_softc *sc = MOTG_BUS2SC(bus); 789 790 *lock = &sc->sc_lock; 791 } 792 793 /* 794 * Routines to emulate the root hub. 795 */ 796 Static int 797 motg_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 798 void *buf, int buflen) 799 { 800 struct motg_softc *sc = MOTG_BUS2SC(bus); 801 int status, change, totlen = 0; 802 uint16_t len, value, index; 803 usb_port_status_t ps; 804 usbd_status err; 805 uint32_t val; 806 807 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 808 809 if (sc->sc_dying) 810 return -1; 811 812 DPRINTFN(MD_ROOT, "type=0x%02jx request=%02jx", req->bmRequestType, 813 req->bRequest, 0, 0); 814 815 len = UGETW(req->wLength); 816 value = UGETW(req->wValue); 817 index = UGETW(req->wIndex); 818 819 #define C(x,y) ((x) | ((y) << 8)) 820 switch (C(req->bRequest, req->bmRequestType)) { 821 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 822 DPRINTFN(MD_ROOT, "wValue=0x%04jx", value, 0, 0, 0); 823 switch (value) { 824 #define sd ((usb_string_descriptor_t *)buf) 825 case C(2, UDESC_STRING): 826 /* Product */ 827 totlen = usb_makestrdesc(sd, len, "MOTG root hub"); 828 break; 829 #undef sd 830 default: 831 /* default from usbroothub */ 832 return buflen; 833 } 834 break; 835 /* Hub requests */ 836 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 837 break; 838 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 839 DPRINTFN(MD_ROOT, 840 "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", index, value, 841 0, 0); 842 if (index != 1) { 843 return -1; 844 } 845 switch (value) { 846 case UHF_PORT_ENABLE: 847 sc->sc_port_enabled = 0; 848 break; 849 case UHF_PORT_SUSPEND: 850 if (sc->sc_port_suspended != 0) { 851 val = UREAD1(sc, MUSB2_REG_POWER); 852 val &= ~MUSB2_MASK_SUSPMODE; 853 val |= MUSB2_MASK_RESUME; 854 UWRITE1(sc, MUSB2_REG_POWER, val); 855 /* wait 20 milliseconds */ 856 usb_delay_ms(&sc->sc_bus, 20); 857 val = UREAD1(sc, MUSB2_REG_POWER); 858 val &= ~MUSB2_MASK_RESUME; 859 UWRITE1(sc, MUSB2_REG_POWER, val); 860 sc->sc_port_suspended = 0; 861 sc->sc_port_suspended_change = 1; 862 } 863 break; 864 case UHF_PORT_RESET: 865 break; 866 case UHF_C_PORT_CONNECTION: 867 break; 868 case UHF_C_PORT_ENABLE: 869 break; 870 case UHF_C_PORT_OVER_CURRENT: 871 break; 872 case UHF_C_PORT_RESET: 873 sc->sc_isreset = 0; 874 break; 875 case UHF_PORT_POWER: 876 /* XXX todo */ 877 break; 878 case UHF_PORT_CONNECTION: 879 case UHF_PORT_OVER_CURRENT: 880 case UHF_PORT_LOW_SPEED: 881 case UHF_C_PORT_SUSPEND: 882 default: 883 return -1; 884 } 885 break; 886 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 887 return -1; 888 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 889 if (len == 0) 890 break; 891 if ((value & 0xff) != 0) { 892 return -1; 893 } 894 totlen = buflen; 895 break; 896 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 897 if (len != 4) { 898 return -1; 899 } 900 memset(buf, 0, len); 901 totlen = len; 902 break; 903 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 904 if (index != 1) { 905 return -1; 906 } 907 if (len != 4) { 908 return -1; 909 } 910 status = change = 0; 911 if (sc->sc_connected) 912 status |= UPS_CURRENT_CONNECT_STATUS; 913 if (sc->sc_connected_changed) { 914 change |= UPS_C_CONNECT_STATUS; 915 sc->sc_connected_changed = 0; 916 } 917 if (sc->sc_port_enabled) 918 status |= UPS_PORT_ENABLED; 919 if (sc->sc_port_enabled_changed) { 920 change |= UPS_C_PORT_ENABLED; 921 sc->sc_port_enabled_changed = 0; 922 } 923 if (sc->sc_port_suspended) 924 status |= UPS_SUSPEND; 925 if (sc->sc_high_speed) 926 status |= UPS_HIGH_SPEED; 927 status |= UPS_PORT_POWER; /* XXX */ 928 if (sc->sc_isreset) 929 change |= UPS_C_PORT_RESET; 930 USETW(ps.wPortStatus, status); 931 USETW(ps.wPortChange, change); 932 totlen = uimin(len, sizeof(ps)); 933 memcpy(buf, &ps, totlen); 934 break; 935 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 936 return -1; 937 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 938 break; 939 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 940 if (index != 1) { 941 return -1; 942 } 943 switch(value) { 944 case UHF_PORT_ENABLE: 945 sc->sc_port_enabled = 1; 946 break; 947 case UHF_PORT_SUSPEND: 948 if (sc->sc_port_suspended == 0) { 949 val = UREAD1(sc, MUSB2_REG_POWER); 950 val |= MUSB2_MASK_SUSPMODE; 951 UWRITE1(sc, MUSB2_REG_POWER, val); 952 /* wait 20 milliseconds */ 953 usb_delay_ms(&sc->sc_bus, 20); 954 sc->sc_port_suspended = 1; 955 sc->sc_port_suspended_change = 1; 956 } 957 break; 958 case UHF_PORT_RESET: 959 err = motg_portreset(sc); 960 if (err != USBD_NORMAL_COMPLETION) 961 return -1; 962 return 0; 963 case UHF_PORT_POWER: 964 /* XXX todo */ 965 return 0; 966 case UHF_C_PORT_CONNECTION: 967 case UHF_C_PORT_ENABLE: 968 case UHF_C_PORT_OVER_CURRENT: 969 case UHF_PORT_CONNECTION: 970 case UHF_PORT_OVER_CURRENT: 971 case UHF_PORT_LOW_SPEED: 972 case UHF_C_PORT_SUSPEND: 973 case UHF_C_PORT_RESET: 974 default: 975 return -1; 976 } 977 break; 978 default: 979 /* default from usbroothub */ 980 return buflen; 981 } 982 983 return totlen; 984 } 985 986 /* Abort a root interrupt request. */ 987 void 988 motg_root_intr_abort(struct usbd_xfer *xfer) 989 { 990 struct motg_softc *sc = MOTG_XFER2SC(xfer); 991 992 KASSERT(mutex_owned(&sc->sc_lock)); 993 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 994 995 /* If xfer has already completed, nothing to do here. */ 996 if (sc->sc_intr_xfer == NULL) 997 return; 998 999 /* 1000 * Otherwise, sc->sc_intr_xfer had better be this transfer. 1001 * Cancel it. 1002 */ 1003 KASSERT(sc->sc_intr_xfer == xfer); 1004 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1005 xfer->ux_status = USBD_CANCELLED; 1006 usb_transfer_complete(xfer); 1007 } 1008 1009 usbd_status 1010 motg_root_intr_transfer(struct usbd_xfer *xfer) 1011 { 1012 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1013 usbd_status err; 1014 1015 /* Insert last in queue. */ 1016 mutex_enter(&sc->sc_lock); 1017 err = usb_insert_transfer(xfer); 1018 mutex_exit(&sc->sc_lock); 1019 if (err) 1020 return err; 1021 1022 /* 1023 * Pipe isn't running (otherwise err would be USBD_INPROG), 1024 * start first 1025 */ 1026 return motg_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1027 } 1028 1029 /* Start a transfer on the root interrupt pipe */ 1030 usbd_status 1031 motg_root_intr_start(struct usbd_xfer *xfer) 1032 { 1033 struct usbd_pipe *pipe = xfer->ux_pipe; 1034 struct motg_softc *sc = MOTG_PIPE2SC(pipe); 1035 const bool polling = sc->sc_bus.ub_usepolling; 1036 1037 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1038 1039 DPRINTFN(MD_ROOT, "xfer=%#jx len=%jd flags=%jd", (uintptr_t)xfer, 1040 xfer->ux_length, xfer->ux_flags, 0); 1041 1042 if (sc->sc_dying) 1043 return USBD_IOERROR; 1044 1045 if (!polling) 1046 mutex_enter(&sc->sc_lock); 1047 KASSERT(sc->sc_intr_xfer == NULL); 1048 sc->sc_intr_xfer = xfer; 1049 xfer->ux_status = USBD_IN_PROGRESS; 1050 if (!polling) 1051 mutex_exit(&sc->sc_lock); 1052 1053 return USBD_IN_PROGRESS; 1054 } 1055 1056 /* Close the root interrupt pipe. */ 1057 void 1058 motg_root_intr_close(struct usbd_pipe *pipe) 1059 { 1060 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1061 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1062 1063 KASSERT(mutex_owned(&sc->sc_lock)); 1064 1065 /* 1066 * Caller must guarantee the xfer has completed first, by 1067 * closing the pipe only after normal completion or an abort. 1068 */ 1069 KASSERT(sc->sc_intr_xfer == NULL); 1070 } 1071 1072 void 1073 motg_root_intr_done(struct usbd_xfer *xfer) 1074 { 1075 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1076 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1077 1078 KASSERT(mutex_owned(&sc->sc_lock)); 1079 1080 /* Claim the xfer so it doesn't get completed again. */ 1081 KASSERT(sc->sc_intr_xfer == xfer); 1082 KASSERT(xfer->ux_status != USBD_IN_PROGRESS); 1083 sc->sc_intr_xfer = NULL; 1084 } 1085 1086 void 1087 motg_noop(struct usbd_pipe *pipe) 1088 { 1089 } 1090 1091 static usbd_status 1092 motg_portreset(struct motg_softc *sc) 1093 { 1094 uint32_t val; 1095 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1096 1097 val = UREAD1(sc, MUSB2_REG_POWER); 1098 val |= MUSB2_MASK_RESET; 1099 UWRITE1(sc, MUSB2_REG_POWER, val); 1100 /* Wait for 20 msec */ 1101 usb_delay_ms(&sc->sc_bus, 20); 1102 1103 val = UREAD1(sc, MUSB2_REG_POWER); 1104 val &= ~MUSB2_MASK_RESET; 1105 UWRITE1(sc, MUSB2_REG_POWER, val); 1106 1107 /* determine line speed */ 1108 val = UREAD1(sc, MUSB2_REG_POWER); 1109 if (val & MUSB2_MASK_HSMODE) 1110 sc->sc_high_speed = 1; 1111 else 1112 sc->sc_high_speed = 0; 1113 DPRINTFN(MD_ROOT | MD_CTRL, "speed %jd", sc->sc_high_speed, 0, 0, 0); 1114 1115 sc->sc_isreset = 1; 1116 sc->sc_port_enabled = 1; 1117 return USBD_NORMAL_COMPLETION; 1118 } 1119 1120 /* 1121 * This routine is executed when an interrupt on the root hub is detected 1122 */ 1123 static void 1124 motg_hub_change(struct motg_softc *sc) 1125 { 1126 struct usbd_xfer *xfer = sc->sc_intr_xfer; 1127 struct usbd_pipe *pipe; 1128 u_char *p; 1129 1130 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1131 1132 if (xfer == NULL) 1133 return; /* the interrupt pipe is not open */ 1134 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1135 1136 pipe = xfer->ux_pipe; 1137 if (pipe->up_dev == NULL || pipe->up_dev->ud_bus == NULL) 1138 return; /* device has detached */ 1139 1140 p = xfer->ux_buf; 1141 p[0] = 1<<1; 1142 xfer->ux_actlen = 1; 1143 xfer->ux_status = USBD_NORMAL_COMPLETION; 1144 usb_transfer_complete(xfer); 1145 } 1146 1147 static uint8_t 1148 motg_speed(uint8_t speed) 1149 { 1150 switch(speed) { 1151 case USB_SPEED_LOW: 1152 return MUSB2_MASK_TI_SPEED_LO; 1153 case USB_SPEED_FULL: 1154 return MUSB2_MASK_TI_SPEED_FS; 1155 case USB_SPEED_HIGH: 1156 return MUSB2_MASK_TI_SPEED_HS; 1157 default: 1158 panic("motg: unknown speed %d", speed); 1159 /* NOTREACHED */ 1160 } 1161 } 1162 1163 static uint8_t 1164 motg_type(uint8_t type) 1165 { 1166 switch(type) { 1167 case UE_CONTROL: 1168 return MUSB2_MASK_TI_PROTO_CTRL; 1169 case UE_ISOCHRONOUS: 1170 return MUSB2_MASK_TI_PROTO_ISOC; 1171 case UE_BULK: 1172 return MUSB2_MASK_TI_PROTO_BULK; 1173 case UE_INTERRUPT: 1174 return MUSB2_MASK_TI_PROTO_INTR; 1175 default: 1176 panic("motg: unknown type %d", type); 1177 /* NOTREACHED */ 1178 } 1179 } 1180 1181 static void 1182 motg_setup_endpoint_tx(struct usbd_xfer *xfer) 1183 { 1184 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1185 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1186 struct usbd_device *dev = otgpipe->pipe.up_dev; 1187 int epnumber = otgpipe->hw_ep->ep_number; 1188 1189 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->ud_addr); 1190 if (dev->ud_myhsport) { 1191 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1192 dev->ud_myhsport->up_parent->ud_addr); 1193 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1194 dev->ud_myhsport->up_portno); 1195 } else { 1196 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1197 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1198 } 1199 UWRITE1(sc, MUSB2_REG_TXTI, 1200 motg_speed(dev->ud_speed) | 1201 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1202 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1203 ); 1204 if (epnumber == 0) { 1205 if (sc->sc_high_speed) { 1206 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1207 NAK_TO_CTRL_HIGH); 1208 } else { 1209 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1210 } 1211 } else { 1212 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1213 == UE_BULK) { 1214 if (sc->sc_high_speed) { 1215 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1216 NAK_TO_BULK_HIGH); 1217 } else { 1218 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1219 } 1220 } else { 1221 if (sc->sc_high_speed) { 1222 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1223 } else { 1224 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1225 } 1226 } 1227 } 1228 } 1229 1230 static void 1231 motg_setup_endpoint_rx(struct usbd_xfer *xfer) 1232 { 1233 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1234 struct usbd_device *dev = xfer->ux_pipe->up_dev; 1235 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1236 int epnumber = otgpipe->hw_ep->ep_number; 1237 1238 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->ud_addr); 1239 if (dev->ud_myhsport) { 1240 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1241 dev->ud_myhsport->up_parent->ud_addr); 1242 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1243 dev->ud_myhsport->up_portno); 1244 } else { 1245 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1246 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1247 } 1248 UWRITE1(sc, MUSB2_REG_RXTI, 1249 motg_speed(dev->ud_speed) | 1250 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) | 1251 motg_type(UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes)) 1252 ); 1253 if (epnumber == 0) { 1254 if (sc->sc_high_speed) { 1255 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1256 NAK_TO_CTRL_HIGH); 1257 } else { 1258 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_CTRL); 1259 } 1260 } else { 1261 if ((xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes & UE_XFERTYPE) 1262 == UE_BULK) { 1263 if (sc->sc_high_speed) { 1264 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1265 NAK_TO_BULK_HIGH); 1266 } else { 1267 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1268 } 1269 } else { 1270 if (sc->sc_high_speed) { 1271 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1272 } else { 1273 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1274 } 1275 } 1276 } 1277 } 1278 1279 static usbd_status 1280 motg_device_ctrl_transfer(struct usbd_xfer *xfer) 1281 { 1282 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1283 usbd_status err; 1284 1285 /* Insert last in queue. */ 1286 mutex_enter(&sc->sc_lock); 1287 err = usb_insert_transfer(xfer); 1288 KASSERT(xfer->ux_status == USBD_NOT_STARTED); 1289 mutex_exit(&sc->sc_lock); 1290 if (err) 1291 return err; 1292 1293 /* 1294 * Pipe isn't running (otherwise err would be USBD_INPROG), 1295 * so start it first. 1296 */ 1297 return motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1298 } 1299 1300 static usbd_status 1301 motg_device_ctrl_start(struct usbd_xfer *xfer) 1302 { 1303 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1304 usbd_status err; 1305 mutex_enter(&sc->sc_lock); 1306 err = motg_device_ctrl_start1(sc); 1307 mutex_exit(&sc->sc_lock); 1308 return err; 1309 } 1310 1311 static usbd_status 1312 motg_device_ctrl_start1(struct motg_softc *sc) 1313 { 1314 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1315 struct usbd_xfer *xfer = NULL; 1316 struct motg_pipe *otgpipe; 1317 usbd_status err = 0; 1318 1319 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1320 1321 KASSERT(mutex_owned(&sc->sc_lock)); 1322 if (sc->sc_dying) 1323 return USBD_IOERROR; 1324 1325 if (!sc->sc_connected) 1326 return USBD_IOERROR; 1327 1328 if (ep->xfer != NULL) { 1329 err = USBD_IN_PROGRESS; 1330 goto end; 1331 } 1332 /* locate the first pipe with work to do */ 1333 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1334 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1335 DPRINTFN(MD_CTRL, "pipe %#jx xfer %#jx status %jd", 1336 (uintptr_t)otgpipe, (uintptr_t)xfer, 1337 (xfer != NULL) ? xfer->ux_status : 0, 0); 1338 1339 if (xfer != NULL) { 1340 /* move this pipe to the end of the list */ 1341 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1342 motg_pipe, ep_pipe_list); 1343 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1344 otgpipe, ep_pipe_list); 1345 break; 1346 } 1347 } 1348 if (xfer == NULL) { 1349 err = USBD_NOT_STARTED; 1350 goto end; 1351 } 1352 if (xfer->ux_status == USBD_NOT_STARTED) { 1353 usbd_xfer_schedule_timeout(xfer); 1354 xfer->ux_status = USBD_IN_PROGRESS; 1355 } else { 1356 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1357 } 1358 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1359 KASSERT(otgpipe->hw_ep == ep); 1360 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1361 // KASSERT(xfer->ux_actlen == 0); 1362 xfer->ux_actlen = 0; 1363 1364 ep->xfer = xfer; 1365 ep->datalen = xfer->ux_length; 1366 if (ep->datalen > 0) 1367 ep->data = xfer->ux_buf; 1368 else 1369 ep->data = NULL; 1370 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1371 (ep->datalen % 64) == 0) 1372 ep->need_short_xfer = 1; 1373 else 1374 ep->need_short_xfer = 0; 1375 /* now we need send this request */ 1376 DPRINTFN(MD_CTRL, 1377 "xfer %#jx send data %#jx len %jd short %jd", 1378 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1379 ep->need_short_xfer); 1380 DPRINTFN(MD_CTRL, 1381 "xfer %#jx ... speed %jd to %jd", (uintptr_t)xfer, 1382 xfer->ux_pipe->up_dev->ud_speed, 1383 xfer->ux_pipe->up_dev->ud_addr, 0); 1384 KASSERT(ep->phase == IDLE); 1385 ep->phase = SETUP; 1386 /* select endpoint 0 */ 1387 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1388 /* fifo should be empty at this point */ 1389 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1390 /* send data */ 1391 // KASSERT(((vaddr_t)(&xfer->ux_request) & 3) == 0); 1392 KASSERT(sizeof(xfer->ux_request) == 8); 1393 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1394 (void *)&xfer->ux_request, sizeof(xfer->ux_request)); 1395 1396 motg_setup_endpoint_tx(xfer); 1397 /* start transaction */ 1398 UWRITE1(sc, MUSB2_REG_TXCSRL, 1399 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1400 1401 end: 1402 if (err) 1403 return err; 1404 1405 return USBD_IN_PROGRESS; 1406 } 1407 1408 static void 1409 motg_device_ctrl_read(struct usbd_xfer *xfer) 1410 { 1411 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1412 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1413 /* assume endpoint already selected */ 1414 motg_setup_endpoint_rx(xfer); 1415 /* start transaction */ 1416 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1417 otgpipe->hw_ep->phase = DATA_IN; 1418 } 1419 1420 static void 1421 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1422 { 1423 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1424 struct usbd_xfer *xfer = ep->xfer; 1425 uint8_t csr; 1426 int datalen, max_datalen; 1427 char *data; 1428 bool got_short; 1429 usbd_status new_status = USBD_IN_PROGRESS; 1430 1431 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1432 1433 KASSERT(mutex_owned(&sc->sc_lock)); 1434 KASSERT(ep->phase == DATA_IN || ep->phase == STATUS_IN); 1435 1436 /* select endpoint 0 */ 1437 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1438 1439 /* read out FIFO status */ 1440 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1441 DPRINTFN(MD_CTRL, "phase %jd csr %#jx xfer %#jx status %jd", 1442 ep->phase, csr, (uintptr_t)xfer, 1443 (xfer != NULL) ? xfer->ux_status : 0); 1444 1445 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1446 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1447 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1448 1449 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1450 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1451 new_status = USBD_TIMEOUT; /* XXX */ 1452 goto complete; 1453 } 1454 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1455 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1456 new_status = USBD_STALLED; 1457 else 1458 new_status = USBD_IOERROR; 1459 /* clear status */ 1460 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1461 goto complete; 1462 } 1463 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1464 return; /* no data yet */ 1465 1466 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1467 goto complete; 1468 1469 if (ep->phase == STATUS_IN) { 1470 new_status = USBD_NORMAL_COMPLETION; 1471 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1472 goto complete; 1473 } 1474 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1475 DPRINTFN(MD_CTRL, "phase %jd datalen %jd", ep->phase, datalen, 0, 0); 1476 KASSERT(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize) > 0); 1477 max_datalen = uimin(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize), 1478 ep->datalen); 1479 if (datalen > max_datalen) { 1480 new_status = USBD_IOERROR; 1481 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1482 goto complete; 1483 } 1484 got_short = (datalen < max_datalen); 1485 if (datalen > 0) { 1486 KASSERT(ep->phase == DATA_IN); 1487 data = ep->data; 1488 ep->data += datalen; 1489 ep->datalen -= datalen; 1490 xfer->ux_actlen += datalen; 1491 if (((vaddr_t)data & 0x3) == 0 && 1492 (datalen >> 2) > 0) { 1493 DPRINTFN(MD_CTRL, "r4 data %#jx len %jd", 1494 (uintptr_t)data, datalen, 0, 0); 1495 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1496 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1497 data += (datalen & ~0x3); 1498 datalen -= (datalen & ~0x3); 1499 } 1500 DPRINTFN(MD_CTRL, "r1 data %#jx len %jd", (uintptr_t)data, 1501 datalen, 0, 0); 1502 if (datalen) { 1503 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1504 MUSB2_REG_EPFIFO(0), data, datalen); 1505 } 1506 } 1507 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1508 KASSERT(ep->phase == DATA_IN); 1509 if (got_short || (ep->datalen == 0)) { 1510 if (ep->need_short_xfer == 0) { 1511 ep->phase = STATUS_OUT; 1512 UWRITE1(sc, MUSB2_REG_TXCSRH, 1513 UREAD1(sc, MUSB2_REG_TXCSRH) | 1514 MUSB2_MASK_CSR0H_PING_DIS); 1515 motg_setup_endpoint_tx(xfer); 1516 UWRITE1(sc, MUSB2_REG_TXCSRL, 1517 MUSB2_MASK_CSR0L_STATUSPKT | 1518 MUSB2_MASK_CSR0L_TXPKTRDY); 1519 return; 1520 } 1521 ep->need_short_xfer = 0; 1522 } 1523 motg_device_ctrl_read(xfer); 1524 return; 1525 complete: 1526 ep->phase = IDLE; 1527 ep->xfer = NULL; 1528 /* 1529 * Try to claim this xfer for completion. If it has already 1530 * completed or aborted, drop it on the floor. 1531 */ 1532 if (xfer && usbd_xfer_trycomplete(xfer)) { 1533 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1534 KASSERT(new_status != USBD_IN_PROGRESS); 1535 xfer->ux_status = new_status; 1536 usb_transfer_complete(xfer); 1537 } 1538 motg_device_ctrl_start1(sc); 1539 } 1540 1541 static void 1542 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1543 { 1544 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1545 struct usbd_xfer *xfer = ep->xfer; 1546 uint8_t csr; 1547 int datalen; 1548 char *data; 1549 usbd_status new_status = USBD_IN_PROGRESS; 1550 1551 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1552 1553 KASSERT(mutex_owned(&sc->sc_lock)); 1554 1555 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1556 motg_device_ctrl_intr_rx(sc); 1557 return; 1558 } 1559 1560 KASSERT(ep->phase == SETUP || ep->phase == DATA_OUT || 1561 ep->phase == STATUS_OUT); 1562 1563 /* select endpoint 0 */ 1564 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1565 1566 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1567 DPRINTFN(MD_CTRL, "phase %jd csr %#jx xfer %#jx status %jd", 1568 ep->phase, csr, (uintptr_t)xfer, 1569 (xfer != NULL) ? xfer->ux_status : 0); 1570 1571 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1572 /* command not accepted */ 1573 new_status = USBD_STALLED; 1574 /* clear status */ 1575 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1576 goto complete; 1577 } 1578 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1579 new_status = USBD_TIMEOUT; /* XXX */ 1580 /* flush fifo */ 1581 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1582 UWRITE1(sc, MUSB2_REG_TXCSRH, 1583 UREAD1(sc, MUSB2_REG_TXCSRH) | 1584 MUSB2_MASK_CSR0H_FFLUSH); 1585 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1586 } 1587 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1588 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1589 goto complete; 1590 } 1591 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1592 new_status = USBD_IOERROR; 1593 /* clear status */ 1594 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1595 goto complete; 1596 } 1597 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1598 /* data still not sent */ 1599 return; 1600 } 1601 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 1602 goto complete; 1603 if (ep->phase == STATUS_OUT) { 1604 /* 1605 * we have sent status and got no error; 1606 * declare transfer complete 1607 */ 1608 DPRINTFN(MD_CTRL, "xfer %#jx status %jd complete", 1609 (uintptr_t)xfer, xfer->ux_status, 0, 0); 1610 new_status = USBD_NORMAL_COMPLETION; 1611 goto complete; 1612 } 1613 if (ep->datalen == 0) { 1614 if (ep->need_short_xfer) { 1615 ep->need_short_xfer = 0; 1616 /* one more data phase */ 1617 if (xfer->ux_request.bmRequestType & UT_READ) { 1618 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_IN", 1619 (uintptr_t)xfer, 0, 0, 0); 1620 motg_device_ctrl_read(xfer); 1621 return; 1622 } /* else fall back to DATA_OUT */ 1623 } else { 1624 DPRINTFN(MD_CTRL, "xfer %#jx to STATUS_IN, csrh %#jx", 1625 (uintptr_t)xfer, UREAD1(sc, MUSB2_REG_TXCSRH), 1626 0, 0); 1627 ep->phase = STATUS_IN; 1628 UWRITE1(sc, MUSB2_REG_RXCSRH, 1629 UREAD1(sc, MUSB2_REG_RXCSRH) | 1630 MUSB2_MASK_CSR0H_PING_DIS); 1631 motg_setup_endpoint_rx(xfer); 1632 UWRITE1(sc, MUSB2_REG_TXCSRL, 1633 MUSB2_MASK_CSR0L_STATUSPKT | 1634 MUSB2_MASK_CSR0L_REQPKT); 1635 return; 1636 } 1637 } 1638 if (xfer->ux_request.bmRequestType & UT_READ) { 1639 motg_device_ctrl_read(xfer); 1640 return; 1641 } 1642 /* setup a dataout phase */ 1643 datalen = uimin(ep->datalen, 1644 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1645 ep->phase = DATA_OUT; 1646 DPRINTFN(MD_CTRL, "xfer %#jx to DATA_OUT, csrh %#jx", (uintptr_t)xfer, 1647 UREAD1(sc, MUSB2_REG_TXCSRH), 0, 0); 1648 if (datalen) { 1649 data = ep->data; 1650 ep->data += datalen; 1651 ep->datalen -= datalen; 1652 xfer->ux_actlen += datalen; 1653 if (((vaddr_t)data & 0x3) == 0 && 1654 (datalen >> 2) > 0) { 1655 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1656 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1657 data += (datalen & ~0x3); 1658 datalen -= (datalen & ~0x3); 1659 } 1660 if (datalen) { 1661 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1662 MUSB2_REG_EPFIFO(0), data, datalen); 1663 } 1664 } 1665 /* send data */ 1666 motg_setup_endpoint_tx(xfer); 1667 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1668 return; 1669 1670 complete: 1671 ep->phase = IDLE; 1672 ep->xfer = NULL; 1673 /* 1674 * Try to claim this xfer for completion. If it has already 1675 * completed or aborted, drop it on the floor. 1676 */ 1677 if (xfer && usbd_xfer_trycomplete(xfer)) { 1678 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1679 KASSERT(new_status != USBD_IN_PROGRESS); 1680 xfer->ux_status = new_status; 1681 usb_transfer_complete(xfer); 1682 } 1683 motg_device_ctrl_start1(sc); 1684 } 1685 1686 /* Abort a device control request. */ 1687 void 1688 motg_device_ctrl_abort(struct usbd_xfer *xfer) 1689 { 1690 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1691 1692 usbd_xfer_abort(xfer); 1693 } 1694 1695 /* Close a device control pipe */ 1696 void 1697 motg_device_ctrl_close(struct usbd_pipe *pipe) 1698 { 1699 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 1700 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 1701 struct motg_pipe *otgpipeiter; 1702 1703 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1704 1705 KASSERT(mutex_owned(&sc->sc_lock)); 1706 KASSERT(otgpipe->hw_ep->xfer == NULL || 1707 otgpipe->hw_ep->xfer->ux_pipe != pipe); 1708 1709 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1710 if (otgpipeiter == otgpipe) { 1711 /* remove from list */ 1712 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1713 motg_pipe, ep_pipe_list); 1714 otgpipe->hw_ep->refcount--; 1715 /* we're done */ 1716 return; 1717 } 1718 } 1719 panic("motg_device_ctrl_close: not found"); 1720 } 1721 1722 void 1723 motg_device_ctrl_done(struct usbd_xfer *xfer) 1724 { 1725 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1726 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1727 1728 KASSERT(otgpipe->hw_ep->xfer != xfer); 1729 } 1730 1731 static usbd_status 1732 motg_device_data_transfer(struct usbd_xfer *xfer) 1733 { 1734 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1735 usbd_status err; 1736 1737 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1738 1739 /* Insert last in queue. */ 1740 mutex_enter(&sc->sc_lock); 1741 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1742 err = usb_insert_transfer(xfer); 1743 KASSERT(xfer->ux_status == USBD_NOT_STARTED); 1744 mutex_exit(&sc->sc_lock); 1745 if (err) 1746 return err; 1747 1748 /* 1749 * Pipe isn't running (otherwise err would be USBD_INPROG), 1750 * so start it first. 1751 */ 1752 return motg_device_data_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 1753 } 1754 1755 static usbd_status 1756 motg_device_data_start(struct usbd_xfer *xfer) 1757 { 1758 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1759 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1760 usbd_status err; 1761 1762 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1763 1764 mutex_enter(&sc->sc_lock); 1765 DPRINTF("xfer %#jx status %jd", (uintptr_t)xfer, xfer->ux_status, 0, 0); 1766 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1767 mutex_exit(&sc->sc_lock); 1768 return err; 1769 } 1770 1771 static usbd_status 1772 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1773 { 1774 struct usbd_xfer *xfer = NULL; 1775 struct motg_pipe *otgpipe; 1776 usbd_status err = 0; 1777 uint32_t val __diagused; 1778 1779 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1780 1781 KASSERT(mutex_owned(&sc->sc_lock)); 1782 if (sc->sc_dying) 1783 return USBD_IOERROR; 1784 1785 if (!sc->sc_connected) 1786 return USBD_IOERROR; 1787 1788 if (ep->xfer != NULL) { 1789 err = USBD_IN_PROGRESS; 1790 goto end; 1791 } 1792 /* locate the first pipe with work to do */ 1793 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1794 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.up_queue); 1795 DPRINTFN(MD_BULK, "pipe %#jx xfer %#jx status %jd", 1796 (uintptr_t)otgpipe, (uintptr_t)xfer, 1797 (xfer != NULL) ? xfer->ux_status : 0, 0); 1798 if (xfer != NULL) { 1799 /* move this pipe to the end of the list */ 1800 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1801 motg_pipe, ep_pipe_list); 1802 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1803 otgpipe, ep_pipe_list); 1804 break; 1805 } 1806 } 1807 if (xfer == NULL) { 1808 err = USBD_NOT_STARTED; 1809 goto end; 1810 } 1811 if (xfer->ux_status == USBD_NOT_STARTED) { 1812 usbd_xfer_schedule_timeout(xfer); 1813 xfer->ux_status = USBD_IN_PROGRESS; 1814 } else { 1815 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 1816 } 1817 KASSERT(otgpipe == MOTG_PIPE2MPIPE(xfer->ux_pipe)); 1818 KASSERT(otgpipe->hw_ep == ep); 1819 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 1820 // KASSERT(xfer->ux_actlen == 0); 1821 xfer->ux_actlen = 0; 1822 1823 ep->xfer = xfer; 1824 ep->datalen = xfer->ux_length; 1825 KASSERT(ep->datalen > 0); 1826 ep->data = xfer->ux_buf; 1827 if ((xfer->ux_flags & USBD_FORCE_SHORT_XFER) && 1828 (ep->datalen % 64) == 0) 1829 ep->need_short_xfer = 1; 1830 else 1831 ep->need_short_xfer = 0; 1832 /* now we need send this request */ 1833 DPRINTFN(MD_BULK, 1834 UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN ? 1835 "xfer %#jx in data %#jx len %jd short %jd" : 1836 "xfer %#jx out data %#jx len %jd short %jd", 1837 (uintptr_t)xfer, (uintptr_t)ep->data, ep->datalen, 1838 ep->need_short_xfer); 1839 DPRINTFN(MD_BULK, "... speed %jd to %jd", 1840 xfer->ux_pipe->up_dev->ud_speed, 1841 xfer->ux_pipe->up_dev->ud_addr, 0, 0); 1842 KASSERT(ep->phase == IDLE); 1843 /* select endpoint */ 1844 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1845 if (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) 1846 == UE_DIR_IN) { 1847 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1848 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1849 motg_device_data_read(xfer); 1850 } else { 1851 ep->phase = DATA_OUT; 1852 val = UREAD1(sc, MUSB2_REG_TXCSRL); 1853 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 1854 motg_device_data_write(xfer); 1855 } 1856 end: 1857 if (err) 1858 return err; 1859 1860 return USBD_IN_PROGRESS; 1861 } 1862 1863 static void 1864 motg_device_data_read(struct usbd_xfer *xfer) 1865 { 1866 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1867 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1868 uint32_t val; 1869 1870 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1871 1872 KASSERT(mutex_owned(&sc->sc_lock)); 1873 /* assume endpoint already selected */ 1874 motg_setup_endpoint_rx(xfer); 1875 /* Max packet size */ 1876 UWRITE2(sc, MUSB2_REG_RXMAXP, 1877 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1878 /* Data Toggle */ 1879 val = UREAD1(sc, MUSB2_REG_RXCSRH); 1880 val |= MUSB2_MASK_CSRH_RXDT_WREN; 1881 if (otgpipe->nexttoggle) 1882 val |= MUSB2_MASK_CSRH_RXDT_VAL; 1883 else 1884 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 1885 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 1886 1887 DPRINTFN(MD_BULK, "%#jx to DATA_IN on ep %jd, csrh %#jx", 1888 (uintptr_t)xfer, otgpipe->hw_ep->ep_number, 1889 UREAD1(sc, MUSB2_REG_RXCSRH), 0); 1890 /* start transaction */ 1891 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 1892 otgpipe->hw_ep->phase = DATA_IN; 1893 } 1894 1895 static void 1896 motg_device_data_write(struct usbd_xfer *xfer) 1897 { 1898 struct motg_softc *sc = MOTG_XFER2SC(xfer); 1899 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 1900 struct motg_hw_ep *ep = otgpipe->hw_ep; 1901 int datalen; 1902 char *data; 1903 uint32_t val; 1904 1905 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1906 1907 KASSERT(xfer!=NULL); 1908 KASSERT(mutex_owned(&sc->sc_lock)); 1909 1910 datalen = uimin(ep->datalen, 1911 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1912 ep->phase = DATA_OUT; 1913 DPRINTFN(MD_BULK, "%#jx to DATA_OUT on ep %jd, len %jd csrh %#jx", 1914 (uintptr_t)xfer, ep->ep_number, datalen, 1915 UREAD1(sc, MUSB2_REG_TXCSRH)); 1916 1917 /* assume endpoint already selected */ 1918 /* write data to fifo */ 1919 data = ep->data; 1920 ep->data += datalen; 1921 ep->datalen -= datalen; 1922 xfer->ux_actlen += datalen; 1923 if (((vaddr_t)data & 0x3) == 0 && 1924 (datalen >> 2) > 0) { 1925 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1926 MUSB2_REG_EPFIFO(ep->ep_number), 1927 (void *)data, datalen >> 2); 1928 data += (datalen & ~0x3); 1929 datalen -= (datalen & ~0x3); 1930 } 1931 if (datalen) { 1932 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1933 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 1934 } 1935 1936 motg_setup_endpoint_tx(xfer); 1937 /* Max packet size */ 1938 UWRITE2(sc, MUSB2_REG_TXMAXP, 1939 UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)); 1940 /* Data Toggle */ 1941 val = UREAD1(sc, MUSB2_REG_TXCSRH); 1942 val |= MUSB2_MASK_CSRH_TXDT_WREN; 1943 if (otgpipe->nexttoggle) 1944 val |= MUSB2_MASK_CSRH_TXDT_VAL; 1945 else 1946 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 1947 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 1948 1949 /* start transaction */ 1950 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 1951 } 1952 1953 static void 1954 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 1955 { 1956 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 1957 struct usbd_xfer *xfer = ep->xfer; 1958 uint8_t csr; 1959 int datalen, max_datalen; 1960 char *data; 1961 bool got_short; 1962 usbd_status new_status = USBD_IN_PROGRESS; 1963 1964 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 1965 1966 KASSERT(mutex_owned(&sc->sc_lock)); 1967 KASSERT(ep->ep_number == epnumber); 1968 1969 DPRINTFN(MD_BULK, "on ep %jd", epnumber, 0, 0, 0); 1970 /* select endpoint */ 1971 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 1972 1973 /* read out FIFO status */ 1974 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 1975 DPRINTFN(MD_BULK, "phase %jd csr %#jx", ep->phase, csr ,0 ,0); 1976 1977 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 1978 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 1979 return; 1980 1981 KASSERTMSG(ep->phase == DATA_IN, "phase %d", ep->phase); 1982 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 1983 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 1984 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1985 1986 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 1987 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 1988 new_status = USBD_TIMEOUT; /* XXX */ 1989 goto complete; 1990 } 1991 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 1992 if (csr & MUSB2_MASK_CSRL_RXSTALL) 1993 new_status = USBD_STALLED; 1994 else 1995 new_status = USBD_IOERROR; 1996 /* clear status */ 1997 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 1998 goto complete; 1999 } 2000 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2001 2002 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) { 2003 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2004 goto complete; 2005 } 2006 2007 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2008 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2009 2010 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2011 DPRINTFN(MD_BULK, "phase %jd datalen %jd", ep->phase, datalen ,0 ,0); 2012 KASSERT(UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)) > 0); 2013 max_datalen = uimin( 2014 UE_GET_SIZE(UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize)), 2015 ep->datalen); 2016 if (datalen > max_datalen) { 2017 new_status = USBD_IOERROR; 2018 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2019 goto complete; 2020 } 2021 got_short = (datalen < max_datalen); 2022 if (datalen > 0) { 2023 KASSERT(ep->phase == DATA_IN); 2024 data = ep->data; 2025 ep->data += datalen; 2026 ep->datalen -= datalen; 2027 xfer->ux_actlen += datalen; 2028 if (((vaddr_t)data & 0x3) == 0 && 2029 (datalen >> 2) > 0) { 2030 DPRINTFN(MD_BULK, "r4 data %#jx len %jd", 2031 (uintptr_t)data, datalen, 0, 0); 2032 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2033 MUSB2_REG_EPFIFO(ep->ep_number), 2034 (void *)data, datalen >> 2); 2035 data += (datalen & ~0x3); 2036 datalen -= (datalen & ~0x3); 2037 } 2038 DPRINTFN(MD_BULK, "r1 data %#jx len %jd", (uintptr_t)data, 2039 datalen ,0 ,0); 2040 if (datalen) { 2041 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2042 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2043 } 2044 } 2045 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2046 KASSERT(ep->phase == DATA_IN); 2047 if (got_short || (ep->datalen == 0)) { 2048 if (ep->need_short_xfer == 0) { 2049 new_status = USBD_NORMAL_COMPLETION; 2050 goto complete; 2051 } 2052 ep->need_short_xfer = 0; 2053 } 2054 motg_device_data_read(xfer); 2055 return; 2056 complete: 2057 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2058 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2059 ep->phase = IDLE; 2060 ep->xfer = NULL; 2061 /* 2062 * Try to claim this xfer for completion. If it has already 2063 * completed or aborted, drop it on the floor. 2064 */ 2065 if (xfer && usbd_xfer_trycomplete(xfer)) { 2066 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2067 KASSERT(new_status != USBD_IN_PROGRESS); 2068 xfer->ux_status = new_status; 2069 usb_transfer_complete(xfer); 2070 } 2071 motg_device_data_start1(sc, ep); 2072 } 2073 2074 static void 2075 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2076 { 2077 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2078 struct usbd_xfer *xfer = ep->xfer; 2079 uint8_t csr; 2080 struct motg_pipe *otgpipe; 2081 usbd_status new_status = USBD_IN_PROGRESS; 2082 2083 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2084 2085 KASSERT(mutex_owned(&sc->sc_lock)); 2086 KASSERT(ep->ep_number == epnumber); 2087 2088 DPRINTFN(MD_BULK, " on ep %jd", epnumber, 0, 0, 0); 2089 /* select endpoint */ 2090 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2091 2092 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2093 DPRINTFN(MD_BULK, "phase %jd csr %#jx", ep->phase, csr, 0, 0); 2094 2095 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2096 /* command not accepted */ 2097 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2098 new_status = USBD_STALLED; 2099 else 2100 new_status = USBD_IOERROR; 2101 /* clear status */ 2102 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2103 goto complete; 2104 } 2105 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2106 new_status = USBD_TIMEOUT; /* XXX */ 2107 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2108 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2109 /* flush fifo */ 2110 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2111 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2112 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2113 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2114 delay(1000); 2115 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2116 DPRINTFN(MD_BULK, "TX fifo flush ep %jd CSR %#jx", 2117 epnumber, csr, 0, 0); 2118 } 2119 goto complete; 2120 } 2121 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2122 /* data still not sent */ 2123 return; 2124 } 2125 if (xfer == NULL || xfer->ux_status != USBD_IN_PROGRESS) 2126 goto complete; 2127 KASSERT(ep->phase == DATA_OUT); 2128 2129 otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2130 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2131 2132 if (ep->datalen == 0) { 2133 if (ep->need_short_xfer) { 2134 ep->need_short_xfer = 0; 2135 /* one more data phase */ 2136 } else { 2137 new_status = USBD_NORMAL_COMPLETION; 2138 goto complete; 2139 } 2140 } 2141 motg_device_data_write(xfer); 2142 return; 2143 2144 complete: 2145 DPRINTFN(MD_BULK, "xfer %#jx complete, status %jd", (uintptr_t)xfer, 2146 (xfer != NULL) ? xfer->ux_status : 0, 0, 0); 2147 ep->phase = IDLE; 2148 ep->xfer = NULL; 2149 /* 2150 * Try to claim this xfer for completion. If it has already 2151 * completed or aborted, drop it on the floor. 2152 */ 2153 if (xfer && usbd_xfer_trycomplete(xfer)) { 2154 KASSERT(xfer->ux_status == USBD_IN_PROGRESS); 2155 KASSERT(new_status != USBD_IN_PROGRESS); 2156 xfer->ux_status = new_status; 2157 usb_transfer_complete(xfer); 2158 } 2159 motg_device_data_start1(sc, ep); 2160 } 2161 2162 /* Abort a device control request. */ 2163 void 2164 motg_device_data_abort(struct usbd_xfer *xfer) 2165 { 2166 struct motg_softc __diagused *sc = MOTG_XFER2SC(xfer); 2167 KASSERT(mutex_owned(&sc->sc_lock)); 2168 2169 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2170 2171 usbd_xfer_abort(xfer); 2172 } 2173 2174 /* Close a device control pipe */ 2175 void 2176 motg_device_data_close(struct usbd_pipe *pipe) 2177 { 2178 struct motg_softc *sc __diagused = MOTG_PIPE2SC(pipe); 2179 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2180 struct motg_pipe *otgpipeiter; 2181 2182 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2183 2184 KASSERT(mutex_owned(&sc->sc_lock)); 2185 KASSERT(otgpipe->hw_ep->xfer == NULL || 2186 otgpipe->hw_ep->xfer->ux_pipe != pipe); 2187 2188 pipe->up_endpoint->ue_toggle = otgpipe->nexttoggle; 2189 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2190 if (otgpipeiter == otgpipe) { 2191 /* remove from list */ 2192 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2193 motg_pipe, ep_pipe_list); 2194 otgpipe->hw_ep->refcount--; 2195 /* we're done */ 2196 return; 2197 } 2198 } 2199 panic("motg_device_data_close: not found"); 2200 } 2201 2202 void 2203 motg_device_data_done(struct usbd_xfer *xfer) 2204 { 2205 struct motg_pipe *otgpipe __diagused = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2206 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2207 2208 KASSERT(otgpipe->hw_ep->xfer != xfer); 2209 } 2210 2211 void 2212 motg_device_clear_toggle(struct usbd_pipe *pipe) 2213 { 2214 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(pipe); 2215 otgpipe->nexttoggle = 0; 2216 } 2217 2218 /* Abort a device control request. */ 2219 static void 2220 motg_abortx(struct usbd_xfer *xfer) 2221 { 2222 MOTGHIST_FUNC(); MOTGHIST_CALLED(); 2223 uint8_t csr; 2224 struct motg_softc *sc = MOTG_XFER2SC(xfer); 2225 struct motg_pipe *otgpipe = MOTG_PIPE2MPIPE(xfer->ux_pipe); 2226 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 ASSERT_SLEEPABLE(); 2229 2230 /* 2231 * If we're dying, skip the hardware action and just notify the 2232 * software that we're done. 2233 */ 2234 if (sc->sc_dying) { 2235 goto dying; 2236 } 2237 2238 if (otgpipe->hw_ep->xfer == xfer) { 2239 otgpipe->hw_ep->xfer = NULL; 2240 if (otgpipe->hw_ep->ep_number > 0) { 2241 /* select endpoint */ 2242 UWRITE1(sc, MUSB2_REG_EPINDEX, 2243 otgpipe->hw_ep->ep_number); 2244 if (otgpipe->hw_ep->phase == DATA_OUT) { 2245 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2246 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2247 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2248 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2249 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2250 } 2251 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2252 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2253 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2254 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2255 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2256 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2257 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2258 } 2259 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2260 } 2261 otgpipe->hw_ep->phase = IDLE; 2262 } 2263 } 2264 dying: 2265 usb_transfer_complete(xfer); 2266 KASSERT(mutex_owned(&sc->sc_lock)); 2267 } 2268
Indexes created Wed Sep 24 05:09:52 GMT 2025