motg.c revision 1.8
1 /* $NetBSD: motg.c,v 1.8 2014/08/12 08:06:46 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.8 2014/08/12 08:06:46 skrll Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/device.h> 50 #include <sys/select.h> 51 #include <sys/extent.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/motgreg.h> 66 #include <dev/usb/motgvar.h> 67 #include <dev/usb/usbroothub_subr.h> 68 69 #define MOTG_DEBUG 70 #ifdef MOTG_DEBUG 71 #define DPRINTF(x) if (motgdebug) printf x 72 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 73 #define MD_ROOT 0x0002 74 #define MD_CTRL 0x0004 75 #define MD_BULK 0x0008 76 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 77 int motgdebug = 0; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 /* various timeouts, for various speeds */ 84 /* control NAK timeouts */ 85 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 86 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 87 88 /* intr/iso polling intervals */ 89 #define POLL_TO 100 /* 100 frames, about 0.1s */ 90 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 91 92 /* bulk NAK timeouts */ 93 #define NAK_TO_BULK 0 /* disabled */ 94 #define NAK_TO_BULK_HIGH 0 95 96 static void motg_hub_change(struct motg_softc *); 97 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 98 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 99 static void motg_root_ctrl_abort(usbd_xfer_handle); 100 static void motg_root_ctrl_close(usbd_pipe_handle); 101 static void motg_root_ctrl_done(usbd_xfer_handle); 102 103 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 104 static usbd_status motg_root_intr_start(usbd_xfer_handle); 105 static void motg_root_intr_abort(usbd_xfer_handle); 106 static void motg_root_intr_close(usbd_pipe_handle); 107 static void motg_root_intr_done(usbd_xfer_handle); 108 109 static usbd_status motg_open(usbd_pipe_handle); 110 static void motg_poll(struct usbd_bus *); 111 static void motg_softintr(void *); 112 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 113 static void motg_freem(struct usbd_bus *, usb_dma_t *); 114 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 115 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 116 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 117 static void motg_noop(usbd_pipe_handle pipe); 118 static usbd_status motg_portreset(struct motg_softc*); 119 120 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 121 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 122 static void motg_device_ctrl_abort(usbd_xfer_handle); 123 static void motg_device_ctrl_close(usbd_pipe_handle); 124 static void motg_device_ctrl_done(usbd_xfer_handle); 125 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 126 static void motg_device_ctrl_read(usbd_xfer_handle); 127 static void motg_device_ctrl_intr_rx(struct motg_softc *); 128 static void motg_device_ctrl_intr_tx(struct motg_softc *); 129 130 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 131 static usbd_status motg_device_data_start(usbd_xfer_handle); 132 static usbd_status motg_device_data_start1(struct motg_softc *, 133 struct motg_hw_ep *); 134 static void motg_device_data_abort(usbd_xfer_handle); 135 static void motg_device_data_close(usbd_pipe_handle); 136 static void motg_device_data_done(usbd_xfer_handle); 137 static void motg_device_intr_rx(struct motg_softc *, int); 138 static void motg_device_intr_tx(struct motg_softc *, int); 139 static void motg_device_data_read(usbd_xfer_handle); 140 static void motg_device_data_write(usbd_xfer_handle); 141 142 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 143 static void motg_device_clear_toggle(usbd_pipe_handle); 144 static void motg_device_xfer_abort(usbd_xfer_handle); 145 146 #define MOTG_INTR_ENDPT 1 147 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 148 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 149 #define UWRITE1(sc, r, x) \ 150 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 151 } while (/*CONSTCOND*/0) 152 #define UWRITE2(sc, r, x) \ 153 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 154 } while (/*CONSTCOND*/0) 155 #define UWRITE4(sc, r, x) \ 156 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 157 } while (/*CONSTCOND*/0) 158 159 static __inline uint32_t 160 UREAD1(struct motg_softc *sc, bus_size_t r) 161 { 162 163 UBARR(sc); 164 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 165 } 166 static __inline uint32_t 167 UREAD2(struct motg_softc *sc, bus_size_t r) 168 { 169 170 UBARR(sc); 171 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 172 } 173 174 #if 0 175 static __inline uint32_t 176 UREAD4(struct motg_softc *sc, bus_size_t r) 177 { 178 179 UBARR(sc); 180 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 181 } 182 #endif 183 184 static void 185 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 186 { 187 uint8_t val; 188 189 val = UREAD1(sc, MUSB2_REG_POWER); 190 if (on) 191 val |= MUSB2_MASK_SOFTC; 192 else 193 val &= ~MUSB2_MASK_SOFTC; 194 195 UWRITE1(sc, MUSB2_REG_POWER, val); 196 } 197 198 const struct usbd_bus_methods motg_bus_methods = { 199 .open_pipe = motg_open, 200 .soft_intr = motg_softintr, 201 .do_poll = motg_poll, 202 .allocm = motg_allocm, 203 .freem = motg_freem, 204 .allocx = motg_allocx, 205 .freex = motg_freex, 206 .get_lock = motg_get_lock, 207 .new_device = NULL, 208 }; 209 210 const struct usbd_pipe_methods motg_root_ctrl_methods = { 211 .transfer = motg_root_ctrl_transfer, 212 .start = motg_root_ctrl_start, 213 .abort = motg_root_ctrl_abort, 214 .close = motg_root_ctrl_close, 215 .cleartoggle = motg_noop, 216 .done = motg_root_ctrl_done, 217 }; 218 219 const struct usbd_pipe_methods motg_root_intr_methods = { 220 .transfer = motg_root_intr_transfer, 221 .start = motg_root_intr_start, 222 .abort = motg_root_intr_abort, 223 .close = motg_root_intr_close, 224 .cleartoggle = motg_noop, 225 .done = motg_root_intr_done, 226 }; 227 228 const struct usbd_pipe_methods motg_device_ctrl_methods = { 229 .transfer = motg_device_ctrl_transfer, 230 .start = motg_device_ctrl_start, 231 .abort = motg_device_ctrl_abort, 232 .close = motg_device_ctrl_close, 233 .cleartoggle = motg_noop, 234 .done = motg_device_ctrl_done, 235 }; 236 237 const struct usbd_pipe_methods motg_device_data_methods = { 238 .transfer = motg_device_data_transfer, 239 .start = motg_device_data_start, 240 .abort = motg_device_data_abort, 241 .close = motg_device_data_close, 242 .cleartoggle = motg_device_clear_toggle, 243 .done = motg_device_data_done, 244 }; 245 246 usbd_status 247 motg_init(struct motg_softc *sc) 248 { 249 uint32_t nrx, ntx, val; 250 int dynfifo; 251 int offset, i; 252 253 if (sc->sc_mode == MOTG_MODE_DEVICE) 254 return USBD_NORMAL_COMPLETION; /* not supported */ 255 256 /* disable all interrupts */ 257 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 258 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 259 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 260 /* disable pullup */ 261 262 musbotg_pull_common(sc, 0); 263 264 /* disable double packet buffering XXX what's this ? */ 265 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 266 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 267 268 /* enable HighSpeed and ISO Update flags */ 269 270 UWRITE1(sc, MUSB2_REG_POWER, 271 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 272 273 if (sc->sc_mode == MOTG_MODE_DEVICE) { 274 /* clear Session bit, if set */ 275 val = UREAD1(sc, MUSB2_REG_DEVCTL); 276 val &= ~MUSB2_MASK_SESS; 277 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 278 } else { 279 /* Enter session for Host mode */ 280 val = UREAD1(sc, MUSB2_REG_DEVCTL); 281 val |= MUSB2_MASK_SESS; 282 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 283 } 284 delay(1000); 285 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 286 287 /* disable testmode */ 288 289 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 290 291 /* set default value */ 292 293 UWRITE1(sc, MUSB2_REG_MISC, 0); 294 295 /* select endpoint index 0 */ 296 297 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 298 299 /* read out number of endpoints */ 300 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 301 302 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 303 304 /* these numbers exclude the control endpoint */ 305 306 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 307 308 sc->sc_ep_max = MAX(nrx, ntx); 309 if (sc->sc_ep_max == 0) { 310 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 311 return USBD_INVAL; 312 } 313 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 314 /* read out configuration data */ 315 val = UREAD1(sc, MUSB2_REG_CONFDATA); 316 317 DPRINTF(("Config Data: 0x%02x\n", val)); 318 319 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 320 321 if (dynfifo) { 322 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 323 "assuming 16Kbytes of FIFO RAM\n"); 324 } 325 326 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 327 328 /* initialise endpoint profiles */ 329 sc->sc_in_ep[0].ep_fifo_size = 64; 330 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 331 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 332 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 333 offset = 64; 334 335 for (i = 1; i <= sc->sc_ep_max; i++) { 336 int fiforx_size, fifotx_size, fifo_size; 337 338 /* select endpoint */ 339 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 340 341 val = UREAD1(sc, MUSB2_REG_FSIZE); 342 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 343 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 344 345 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 346 i, fifotx_size, fiforx_size, dynfifo)); 347 348 if (dynfifo) { 349 if (i < 3) { 350 fifo_size = 12; /* 4K */ 351 } else if (i < 10) { 352 fifo_size = 10; /* 1K */ 353 } else { 354 fifo_size = 7; /* 128 bytes */ 355 } 356 if (fiforx_size && (i <= nrx)) { 357 fiforx_size = fifo_size; 358 if (fifo_size > 7) { 359 #if 0 360 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 361 MUSB2_VAL_FIFOSZ(fifo_size) | 362 MUSB2_MASK_FIFODB); 363 #else 364 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 365 MUSB2_VAL_FIFOSZ(fifo_size)); 366 #endif 367 } else { 368 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 369 MUSB2_VAL_FIFOSZ(fifo_size)); 370 } 371 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 372 offset >> 3); 373 offset += (1 << fiforx_size); 374 } 375 if (fifotx_size && (i <= ntx)) { 376 fifotx_size = fifo_size; 377 if (fifo_size > 7) { 378 #if 0 379 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 380 MUSB2_VAL_FIFOSZ(fifo_size) | 381 MUSB2_MASK_FIFODB); 382 #else 383 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 384 MUSB2_VAL_FIFOSZ(fifo_size)); 385 #endif 386 } else { 387 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 388 MUSB2_VAL_FIFOSZ(fifo_size)); 389 } 390 391 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 392 offset >> 3); 393 394 offset += (1 << fifotx_size); 395 } 396 } 397 if (fiforx_size && (i <= nrx)) { 398 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 399 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 400 } 401 if (fifotx_size && (i <= ntx)) { 402 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 403 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 404 } 405 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 406 } 407 408 409 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 410 411 /* turn on default interrupts */ 412 413 if (sc->sc_mode == MOTG_MODE_HOST) { 414 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 415 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 416 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 417 } else 418 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 419 420 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 421 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 422 423 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 424 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 425 426 /* Set up the bus struct. */ 427 sc->sc_bus.methods = &motg_bus_methods; 428 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 429 sc->sc_bus.usbrev = USBREV_2_0; 430 sc->sc_bus.hci_private = sc; 431 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 432 "Mentor Graphics"); 433 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 434 return USBD_NORMAL_COMPLETION; 435 } 436 437 static int 438 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 439 { 440 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 441 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 442 struct motg_hw_ep *ep; 443 int i, size; 444 445 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 446 sc->sc_in_ep : sc->sc_out_ep; 447 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 448 449 for (i = sc->sc_ep_max; i >= 1; i--) { 450 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 451 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 452 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 453 if (ep[i].ep_fifo_size >= size) { 454 /* found a suitable endpoint */ 455 otgpipe->hw_ep = &ep[i]; 456 mutex_enter(&sc->sc_lock); 457 if (otgpipe->hw_ep->refcount > 0) { 458 /* no luck, try next */ 459 mutex_exit(&sc->sc_lock); 460 otgpipe->hw_ep = NULL; 461 } else { 462 otgpipe->hw_ep->refcount++; 463 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 464 otgpipe, ep_pipe_list); 465 mutex_exit(&sc->sc_lock); 466 return 0; 467 } 468 } 469 } 470 return -1; 471 } 472 473 /* Open a new pipe. */ 474 usbd_status 475 motg_open(usbd_pipe_handle pipe) 476 { 477 struct motg_softc *sc = pipe->device->bus->hci_private; 478 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 479 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 480 481 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 482 pipe, pipe->device->address, 483 ed->bEndpointAddress, sc->sc_root_addr)); 484 485 if (sc->sc_dying) 486 return USBD_IOERROR; 487 488 /* toggle state needed for bulk endpoints */ 489 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 490 491 if (pipe->device->address == sc->sc_root_addr) { 492 switch (ed->bEndpointAddress) { 493 case USB_CONTROL_ENDPOINT: 494 pipe->methods = &motg_root_ctrl_methods; 495 break; 496 case UE_DIR_IN | MOTG_INTR_ENDPT: 497 pipe->methods = &motg_root_intr_methods; 498 break; 499 default: 500 return (USBD_INVAL); 501 } 502 } else { 503 switch (ed->bmAttributes & UE_XFERTYPE) { 504 case UE_CONTROL: 505 pipe->methods = &motg_device_ctrl_methods; 506 /* always use sc_in_ep[0] for in and out */ 507 otgpipe->hw_ep = &sc->sc_in_ep[0]; 508 mutex_enter(&sc->sc_lock); 509 otgpipe->hw_ep->refcount++; 510 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 511 otgpipe, ep_pipe_list); 512 mutex_exit(&sc->sc_lock); 513 break; 514 case UE_BULK: 515 case UE_INTERRUPT: 516 DPRINTFN(MD_BULK, 517 ("new %s %s pipe wMaxPacketSize %d\n", 518 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 519 "bulk" : "interrupt", 520 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 521 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 522 if (motg_select_ep(sc, pipe) != 0) 523 goto bad; 524 KASSERT(otgpipe->hw_ep != NULL); 525 pipe->methods = &motg_device_data_methods; 526 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 527 break; 528 default: 529 goto bad; 530 #ifdef notyet 531 case UE_ISOCHRONOUS: 532 ... 533 break; 534 #endif /* notyet */ 535 } 536 } 537 return (USBD_NORMAL_COMPLETION); 538 539 bad: 540 return (USBD_NOMEM); 541 } 542 543 void 544 motg_softintr(void *v) 545 { 546 struct usbd_bus *bus = v; 547 struct motg_softc *sc = bus->hci_private; 548 uint16_t rx_status, tx_status; 549 uint8_t ctrl_status; 550 uint32_t val; 551 int i; 552 553 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 554 555 DPRINTFN(MD_ROOT | MD_CTRL, 556 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 557 558 mutex_spin_enter(&sc->sc_intr_lock); 559 rx_status = sc->sc_intr_rx_ep; 560 sc->sc_intr_rx_ep = 0; 561 tx_status = sc->sc_intr_tx_ep; 562 sc->sc_intr_tx_ep = 0; 563 ctrl_status = sc->sc_intr_ctrl; 564 sc->sc_intr_ctrl = 0; 565 mutex_spin_exit(&sc->sc_intr_lock); 566 567 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 568 569 if (ctrl_status & (MUSB2_MASK_IRESET | 570 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 571 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 572 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 573 ctrl_status)); 574 575 if (ctrl_status & MUSB2_MASK_IRESET) { 576 sc->sc_isreset = 1; 577 sc->sc_port_suspended = 0; 578 sc->sc_port_suspended_change = 1; 579 sc->sc_connected_changed = 1; 580 sc->sc_port_enabled = 1; 581 582 val = UREAD1(sc, MUSB2_REG_POWER); 583 if (val & MUSB2_MASK_HSMODE) 584 sc->sc_high_speed = 1; 585 else 586 sc->sc_high_speed = 0; 587 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 588 sc->sc_high_speed)); 589 590 /* turn off interrupts */ 591 val = MUSB2_MASK_IRESET; 592 val &= ~MUSB2_MASK_IRESUME; 593 val |= MUSB2_MASK_ISUSP; 594 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 595 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 596 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 597 } 598 if (ctrl_status & MUSB2_MASK_IRESUME) { 599 if (sc->sc_port_suspended) { 600 sc->sc_port_suspended = 0; 601 sc->sc_port_suspended_change = 1; 602 val = UREAD1(sc, MUSB2_REG_INTUSBE); 603 /* disable resume interrupt */ 604 val &= ~MUSB2_MASK_IRESUME; 605 /* enable suspend interrupt */ 606 val |= MUSB2_MASK_ISUSP; 607 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 608 } 609 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 610 if (!sc->sc_port_suspended) { 611 sc->sc_port_suspended = 1; 612 sc->sc_port_suspended_change = 1; 613 614 val = UREAD1(sc, MUSB2_REG_INTUSBE); 615 /* disable suspend interrupt */ 616 val &= ~MUSB2_MASK_ISUSP; 617 /* enable resume interrupt */ 618 val |= MUSB2_MASK_IRESUME; 619 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 620 } 621 } 622 if (ctrl_status & MUSB2_MASK_ICONN) { 623 sc->sc_connected = 1; 624 sc->sc_connected_changed = 1; 625 sc->sc_isreset = 1; 626 sc->sc_port_enabled = 1; 627 } else if (ctrl_status & MUSB2_MASK_IDISC) { 628 sc->sc_connected = 0; 629 sc->sc_connected_changed = 1; 630 sc->sc_isreset = 0; 631 sc->sc_port_enabled = 0; 632 } 633 634 /* complete root HUB interrupt endpoint */ 635 636 motg_hub_change(sc); 637 } 638 /* 639 * read in interrupt status and mix with the status we 640 * got from the wrapper 641 */ 642 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 643 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 644 645 if (rx_status & 0x01) 646 panic("ctrl_rx"); 647 if (tx_status & 0x01) 648 motg_device_ctrl_intr_tx(sc); 649 for (i = 1; i <= sc->sc_ep_max; i++) { 650 if (rx_status & (0x01 << i)) 651 motg_device_intr_rx(sc, i); 652 if (tx_status & (0x01 << i)) 653 motg_device_intr_tx(sc, i); 654 } 655 return; 656 } 657 658 void 659 motg_poll(struct usbd_bus *bus) 660 { 661 struct motg_softc *sc = bus->hci_private; 662 663 sc->sc_intr_poll(sc->sc_intr_poll_arg); 664 mutex_enter(&sc->sc_lock); 665 motg_softintr(bus); 666 mutex_exit(&sc->sc_lock); 667 } 668 669 int 670 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 671 uint8_t ctrl) 672 { 673 KASSERT(mutex_owned(&sc->sc_intr_lock)); 674 sc->sc_intr_tx_ep = tx_ep; 675 sc->sc_intr_rx_ep = rx_ep; 676 sc->sc_intr_ctrl = ctrl; 677 678 if (!sc->sc_bus.use_polling) { 679 sc->sc_bus.no_intrs++; 680 usb_schedsoftintr(&sc->sc_bus); 681 } 682 return 1; 683 } 684 685 int 686 motg_intr_vbus(struct motg_softc *sc, int vbus) 687 { 688 uint8_t val; 689 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 690 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 691 /* try to re-enter session for Host mode */ 692 val = UREAD1(sc, MUSB2_REG_DEVCTL); 693 val |= MUSB2_MASK_SESS; 694 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 695 } 696 return 1; 697 } 698 699 usbd_status 700 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 701 { 702 struct motg_softc *sc = bus->hci_private; 703 usbd_status status; 704 705 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 706 if (status == USBD_NOMEM) 707 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 708 return status; 709 } 710 711 void 712 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 713 { 714 if (dma->block->flags & USB_DMA_RESERVE) { 715 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 716 dma); 717 return; 718 } 719 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 720 } 721 722 usbd_xfer_handle 723 motg_allocx(struct usbd_bus *bus) 724 { 725 struct motg_softc *sc = bus->hci_private; 726 usbd_xfer_handle xfer; 727 728 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 729 if (xfer != NULL) { 730 memset(xfer, 0, sizeof(struct motg_xfer)); 731 UXFER(xfer)->sc = sc; 732 #ifdef DIAGNOSTIC 733 // XXX UXFER(xfer)->iinfo.isdone = 1; 734 xfer->busy_free = XFER_BUSY; 735 #endif 736 } 737 return (xfer); 738 } 739 740 void 741 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 742 { 743 struct motg_softc *sc = bus->hci_private; 744 745 #ifdef DIAGNOSTIC 746 if (xfer->busy_free != XFER_BUSY) { 747 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 748 xfer->busy_free); 749 } 750 xfer->busy_free = XFER_FREE; 751 #endif 752 pool_cache_put(sc->sc_xferpool, xfer); 753 } 754 755 static void 756 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 757 { 758 struct motg_softc *sc = bus->hci_private; 759 760 *lock = &sc->sc_lock; 761 } 762 763 /* 764 * Data structures and routines to emulate the root hub. 765 */ 766 usb_device_descriptor_t motg_devd = { 767 USB_DEVICE_DESCRIPTOR_SIZE, 768 UDESC_DEVICE, /* type */ 769 {0x00, 0x01}, /* USB version */ 770 UDCLASS_HUB, /* class */ 771 UDSUBCLASS_HUB, /* subclass */ 772 UDPROTO_FSHUB, /* protocol */ 773 64, /* max packet */ 774 {0},{0},{0x00,0x01}, /* device id */ 775 1,2,0, /* string indicies */ 776 1 /* # of configurations */ 777 }; 778 779 const usb_config_descriptor_t motg_confd = { 780 USB_CONFIG_DESCRIPTOR_SIZE, 781 UDESC_CONFIG, 782 {USB_CONFIG_DESCRIPTOR_SIZE + 783 USB_INTERFACE_DESCRIPTOR_SIZE + 784 USB_ENDPOINT_DESCRIPTOR_SIZE}, 785 1, 786 1, 787 0, 788 UC_ATTR_MBO | UC_SELF_POWERED, 789 0 /* max power */ 790 }; 791 792 const usb_interface_descriptor_t motg_ifcd = { 793 USB_INTERFACE_DESCRIPTOR_SIZE, 794 UDESC_INTERFACE, 795 0, 796 0, 797 1, 798 UICLASS_HUB, 799 UISUBCLASS_HUB, 800 UIPROTO_FSHUB, 801 0 802 }; 803 804 const usb_endpoint_descriptor_t motg_endpd = { 805 USB_ENDPOINT_DESCRIPTOR_SIZE, 806 UDESC_ENDPOINT, 807 UE_DIR_IN | MOTG_INTR_ENDPT, 808 UE_INTERRUPT, 809 {8}, 810 255 811 }; 812 813 const usb_hub_descriptor_t motg_hubd = { 814 USB_HUB_DESCRIPTOR_SIZE, 815 UDESC_HUB, 816 1, 817 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 818 50, /* power on to power good */ 819 0, 820 { 0x00 }, /* port is removable */ 821 { 0 }, 822 }; 823 824 /* 825 * Simulate a hardware hub by handling all the necessary requests. 826 */ 827 usbd_status 828 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 829 { 830 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 831 usbd_status err; 832 833 /* Insert last in queue. */ 834 mutex_enter(&sc->sc_lock); 835 err = usb_insert_transfer(xfer); 836 mutex_exit(&sc->sc_lock); 837 if (err) 838 return (err); 839 840 /* 841 * Pipe isn't running (otherwise err would be USBD_INPROG), 842 * so start it first. 843 */ 844 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 845 } 846 847 usbd_status 848 motg_root_ctrl_start(usbd_xfer_handle xfer) 849 { 850 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 851 usb_device_request_t *req; 852 void *buf = NULL; 853 int len, value, index, status, change, l, totlen = 0; 854 usb_port_status_t ps; 855 usbd_status err; 856 uint32_t val; 857 858 if (sc->sc_dying) 859 return (USBD_IOERROR); 860 861 #ifdef DIAGNOSTIC 862 if (!(xfer->rqflags & URQ_REQUEST)) 863 panic("motg_root_ctrl_start: not a request"); 864 #endif 865 req = &xfer->request; 866 867 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 868 req->bmRequestType, req->bRequest)); 869 870 len = UGETW(req->wLength); 871 value = UGETW(req->wValue); 872 index = UGETW(req->wIndex); 873 874 if (len != 0) 875 buf = KERNADDR(&xfer->dmabuf, 0); 876 877 #define C(x,y) ((x) | ((y) << 8)) 878 switch(C(req->bRequest, req->bmRequestType)) { 879 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 880 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 881 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 882 /* 883 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 884 * for the integrated root hub. 885 */ 886 break; 887 case C(UR_GET_CONFIG, UT_READ_DEVICE): 888 if (len > 0) { 889 *(u_int8_t *)buf = sc->sc_root_conf; 890 totlen = 1; 891 } 892 break; 893 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 894 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 895 if (len == 0) 896 break; 897 switch(value >> 8) { 898 case UDESC_DEVICE: 899 if ((value & 0xff) != 0) { 900 err = USBD_IOERROR; 901 goto ret; 902 } 903 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 904 USETW(motg_devd.idVendor, sc->sc_id_vendor); 905 memcpy(buf, &motg_devd, l); 906 break; 907 case UDESC_CONFIG: 908 if ((value & 0xff) != 0) { 909 err = USBD_IOERROR; 910 goto ret; 911 } 912 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 913 memcpy(buf, &motg_confd, l); 914 buf = (char *)buf + l; 915 len -= l; 916 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 917 totlen += l; 918 memcpy(buf, &motg_ifcd, l); 919 buf = (char *)buf + l; 920 len -= l; 921 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 922 totlen += l; 923 memcpy(buf, &motg_endpd, l); 924 break; 925 case UDESC_STRING: 926 #define sd ((usb_string_descriptor_t *)buf) 927 switch (value & 0xff) { 928 case 0: /* Language table */ 929 totlen = usb_makelangtbl(sd, len); 930 break; 931 case 1: /* Vendor */ 932 totlen = usb_makestrdesc(sd, len, 933 sc->sc_vendor); 934 break; 935 case 2: /* Product */ 936 totlen = usb_makestrdesc(sd, len, 937 "MOTG root hub"); 938 break; 939 } 940 #undef sd 941 break; 942 default: 943 err = USBD_IOERROR; 944 goto ret; 945 } 946 break; 947 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 948 if (len > 0) { 949 *(u_int8_t *)buf = 0; 950 totlen = 1; 951 } 952 break; 953 case C(UR_GET_STATUS, UT_READ_DEVICE): 954 if (len > 1) { 955 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 956 totlen = 2; 957 } 958 break; 959 case C(UR_GET_STATUS, UT_READ_INTERFACE): 960 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 961 if (len > 1) { 962 USETW(((usb_status_t *)buf)->wStatus, 0); 963 totlen = 2; 964 } 965 break; 966 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 967 if (value >= USB_MAX_DEVICES) { 968 err = USBD_IOERROR; 969 goto ret; 970 } 971 sc->sc_root_addr = value; 972 break; 973 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 974 if (value != 0 && value != 1) { 975 err = USBD_IOERROR; 976 goto ret; 977 } 978 sc->sc_root_conf = value; 979 break; 980 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 981 break; 982 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 983 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 984 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 985 err = USBD_IOERROR; 986 goto ret; 987 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 988 break; 989 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 990 break; 991 /* Hub requests */ 992 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 993 break; 994 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 995 DPRINTFN(MD_ROOT, 996 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 997 "port=%d feature=%d\n", 998 index, value)); 999 if (index != 1) { 1000 err = USBD_IOERROR; 1001 goto ret; 1002 } 1003 switch(value) { 1004 case UHF_PORT_ENABLE: 1005 sc->sc_port_enabled = 0; 1006 break; 1007 case UHF_PORT_SUSPEND: 1008 if (sc->sc_port_suspended != 0) { 1009 val = UREAD1(sc, MUSB2_REG_POWER); 1010 val &= ~MUSB2_MASK_SUSPMODE; 1011 val |= MUSB2_MASK_RESUME; 1012 UWRITE1(sc, MUSB2_REG_POWER, val); 1013 /* wait 20 milliseconds */ 1014 usb_delay_ms(&sc->sc_bus, 20); 1015 val = UREAD1(sc, MUSB2_REG_POWER); 1016 val &= ~MUSB2_MASK_RESUME; 1017 UWRITE1(sc, MUSB2_REG_POWER, val); 1018 sc->sc_port_suspended = 0; 1019 sc->sc_port_suspended_change = 1; 1020 } 1021 break; 1022 case UHF_PORT_RESET: 1023 break; 1024 case UHF_C_PORT_CONNECTION: 1025 break; 1026 case UHF_C_PORT_ENABLE: 1027 break; 1028 case UHF_C_PORT_OVER_CURRENT: 1029 break; 1030 case UHF_C_PORT_RESET: 1031 sc->sc_isreset = 0; 1032 err = USBD_NORMAL_COMPLETION; 1033 goto ret; 1034 case UHF_PORT_POWER: 1035 /* XXX todo */ 1036 break; 1037 case UHF_PORT_CONNECTION: 1038 case UHF_PORT_OVER_CURRENT: 1039 case UHF_PORT_LOW_SPEED: 1040 case UHF_C_PORT_SUSPEND: 1041 default: 1042 err = USBD_IOERROR; 1043 goto ret; 1044 } 1045 break; 1046 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1047 err = USBD_IOERROR; 1048 goto ret; 1049 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1050 if (len == 0) 1051 break; 1052 if ((value & 0xff) != 0) { 1053 err = USBD_IOERROR; 1054 goto ret; 1055 } 1056 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1057 totlen = l; 1058 memcpy(buf, &motg_hubd, l); 1059 break; 1060 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1061 if (len != 4) { 1062 err = USBD_IOERROR; 1063 goto ret; 1064 } 1065 memset(buf, 0, len); 1066 totlen = len; 1067 break; 1068 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1069 if (index != 1) { 1070 err = USBD_IOERROR; 1071 goto ret; 1072 } 1073 if (len != 4) { 1074 err = USBD_IOERROR; 1075 goto ret; 1076 } 1077 status = change = 0; 1078 if (sc->sc_connected) 1079 status |= UPS_CURRENT_CONNECT_STATUS; 1080 if (sc->sc_connected_changed) { 1081 change |= UPS_C_CONNECT_STATUS; 1082 sc->sc_connected_changed = 0; 1083 } 1084 if (sc->sc_port_enabled) 1085 status |= UPS_PORT_ENABLED; 1086 if (sc->sc_port_enabled_changed) { 1087 change |= UPS_C_PORT_ENABLED; 1088 sc->sc_port_enabled_changed = 0; 1089 } 1090 if (sc->sc_port_suspended) 1091 status |= UPS_SUSPEND; 1092 if (sc->sc_high_speed) 1093 status |= UPS_HIGH_SPEED; 1094 status |= UPS_PORT_POWER; /* XXX */ 1095 if (sc->sc_isreset) 1096 change |= UPS_C_PORT_RESET; 1097 USETW(ps.wPortStatus, status); 1098 USETW(ps.wPortChange, change); 1099 l = min(len, sizeof ps); 1100 memcpy(buf, &ps, l); 1101 totlen = l; 1102 break; 1103 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1104 err = USBD_IOERROR; 1105 goto ret; 1106 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1107 break; 1108 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1109 if (index != 1) { 1110 err = USBD_IOERROR; 1111 goto ret; 1112 } 1113 switch(value) { 1114 case UHF_PORT_ENABLE: 1115 sc->sc_port_enabled = 1; 1116 break; 1117 case UHF_PORT_SUSPEND: 1118 if (sc->sc_port_suspended == 0) { 1119 val = UREAD1(sc, MUSB2_REG_POWER); 1120 val |= MUSB2_MASK_SUSPMODE; 1121 UWRITE1(sc, MUSB2_REG_POWER, val); 1122 /* wait 20 milliseconds */ 1123 usb_delay_ms(&sc->sc_bus, 20); 1124 sc->sc_port_suspended = 1; 1125 sc->sc_port_suspended_change = 1; 1126 } 1127 break; 1128 case UHF_PORT_RESET: 1129 err = motg_portreset(sc); 1130 goto ret; 1131 case UHF_PORT_POWER: 1132 /* XXX todo */ 1133 err = USBD_NORMAL_COMPLETION; 1134 goto ret; 1135 case UHF_C_PORT_CONNECTION: 1136 case UHF_C_PORT_ENABLE: 1137 case UHF_C_PORT_OVER_CURRENT: 1138 case UHF_PORT_CONNECTION: 1139 case UHF_PORT_OVER_CURRENT: 1140 case UHF_PORT_LOW_SPEED: 1141 case UHF_C_PORT_SUSPEND: 1142 case UHF_C_PORT_RESET: 1143 default: 1144 err = USBD_IOERROR; 1145 goto ret; 1146 } 1147 break; 1148 default: 1149 err = USBD_IOERROR; 1150 goto ret; 1151 } 1152 xfer->actlen = totlen; 1153 err = USBD_NORMAL_COMPLETION; 1154 ret: 1155 xfer->status = err; 1156 mutex_enter(&sc->sc_lock); 1157 usb_transfer_complete(xfer); 1158 mutex_exit(&sc->sc_lock); 1159 return (USBD_IN_PROGRESS); 1160 } 1161 1162 /* Abort a root control request. */ 1163 void 1164 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1165 { 1166 /* Nothing to do, all transfers are synchronous. */ 1167 } 1168 1169 /* Close the root pipe. */ 1170 void 1171 motg_root_ctrl_close(usbd_pipe_handle pipe) 1172 { 1173 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1174 } 1175 1176 void 1177 motg_root_ctrl_done(usbd_xfer_handle xfer) 1178 { 1179 } 1180 1181 /* Abort a root interrupt request. */ 1182 void 1183 motg_root_intr_abort(usbd_xfer_handle xfer) 1184 { 1185 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1186 1187 KASSERT(mutex_owned(&sc->sc_lock)); 1188 KASSERT(xfer->pipe->intrxfer == xfer); 1189 1190 sc->sc_intr_xfer = NULL; 1191 1192 #ifdef DIAGNOSTIC 1193 // XXX UXFER(xfer)->iinfo.isdone = 1; 1194 #endif 1195 xfer->status = USBD_CANCELLED; 1196 usb_transfer_complete(xfer); 1197 } 1198 1199 usbd_status 1200 motg_root_intr_transfer(usbd_xfer_handle xfer) 1201 { 1202 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1203 usbd_status err; 1204 1205 /* Insert last in queue. */ 1206 mutex_enter(&sc->sc_lock); 1207 err = usb_insert_transfer(xfer); 1208 mutex_exit(&sc->sc_lock); 1209 if (err) 1210 return (err); 1211 1212 /* 1213 * Pipe isn't running (otherwise err would be USBD_INPROG), 1214 * start first 1215 */ 1216 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1217 } 1218 1219 /* Start a transfer on the root interrupt pipe */ 1220 usbd_status 1221 motg_root_intr_start(usbd_xfer_handle xfer) 1222 { 1223 usbd_pipe_handle pipe = xfer->pipe; 1224 struct motg_softc *sc = pipe->device->bus->hci_private; 1225 1226 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1227 xfer, xfer->length, xfer->flags)); 1228 1229 if (sc->sc_dying) 1230 return (USBD_IOERROR); 1231 1232 sc->sc_intr_xfer = xfer; 1233 return (USBD_IN_PROGRESS); 1234 } 1235 1236 /* Close the root interrupt pipe. */ 1237 void 1238 motg_root_intr_close(usbd_pipe_handle pipe) 1239 { 1240 struct motg_softc *sc = pipe->device->bus->hci_private; 1241 1242 KASSERT(mutex_owned(&sc->sc_lock)); 1243 1244 sc->sc_intr_xfer = NULL; 1245 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1246 } 1247 1248 void 1249 motg_root_intr_done(usbd_xfer_handle xfer) 1250 { 1251 } 1252 1253 void 1254 motg_noop(usbd_pipe_handle pipe) 1255 { 1256 } 1257 1258 static usbd_status 1259 motg_portreset(struct motg_softc *sc) 1260 { 1261 uint32_t val; 1262 1263 val = UREAD1(sc, MUSB2_REG_POWER); 1264 val |= MUSB2_MASK_RESET; 1265 UWRITE1(sc, MUSB2_REG_POWER, val); 1266 /* Wait for 20 msec */ 1267 usb_delay_ms(&sc->sc_bus, 20); 1268 1269 val = UREAD1(sc, MUSB2_REG_POWER); 1270 val &= ~MUSB2_MASK_RESET; 1271 UWRITE1(sc, MUSB2_REG_POWER, val); 1272 1273 /* determine line speed */ 1274 val = UREAD1(sc, MUSB2_REG_POWER); 1275 if (val & MUSB2_MASK_HSMODE) 1276 sc->sc_high_speed = 1; 1277 else 1278 sc->sc_high_speed = 0; 1279 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1280 sc->sc_high_speed)); 1281 1282 sc->sc_isreset = 1; 1283 sc->sc_port_enabled = 1; 1284 return (USBD_NORMAL_COMPLETION); 1285 } 1286 1287 /* 1288 * This routine is executed when an interrupt on the root hub is detected 1289 */ 1290 static void 1291 motg_hub_change(struct motg_softc *sc) 1292 { 1293 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1294 usbd_pipe_handle pipe; 1295 u_char *p; 1296 1297 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1298 1299 if (xfer == NULL) 1300 return; /* the interrupt pipe is not open */ 1301 1302 pipe = xfer->pipe; 1303 if (pipe->device == NULL || pipe->device->bus == NULL) 1304 return; /* device has detached */ 1305 1306 p = KERNADDR(&xfer->dmabuf, 0); 1307 p[0] = 1<<1; 1308 xfer->actlen = 1; 1309 xfer->status = USBD_NORMAL_COMPLETION; 1310 usb_transfer_complete(xfer); 1311 } 1312 1313 static uint8_t 1314 motg_speed(u_int8_t speed) 1315 { 1316 switch(speed) { 1317 case USB_SPEED_LOW: 1318 return MUSB2_MASK_TI_SPEED_LO; 1319 case USB_SPEED_FULL: 1320 return MUSB2_MASK_TI_SPEED_FS; 1321 case USB_SPEED_HIGH: 1322 return MUSB2_MASK_TI_SPEED_HS; 1323 default: 1324 panic("motg: unknown speed %d", speed); 1325 /* NOTREACHED */ 1326 } 1327 } 1328 1329 static uint8_t 1330 motg_type(u_int8_t type) 1331 { 1332 switch(type) { 1333 case UE_CONTROL: 1334 return MUSB2_MASK_TI_PROTO_CTRL; 1335 case UE_ISOCHRONOUS: 1336 return MUSB2_MASK_TI_PROTO_ISOC; 1337 case UE_BULK: 1338 return MUSB2_MASK_TI_PROTO_BULK; 1339 case UE_INTERRUPT: 1340 return MUSB2_MASK_TI_PROTO_INTR; 1341 default: 1342 panic("motg: unknown type %d", type); 1343 /* NOTREACHED */ 1344 } 1345 } 1346 1347 static void 1348 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1349 { 1350 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1351 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1352 usbd_device_handle dev = otgpipe->pipe.device; 1353 int epnumber = otgpipe->hw_ep->ep_number; 1354 1355 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1356 if (dev->myhsport) { 1357 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1358 dev->myhsport->parent->address); 1359 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1360 dev->myhsport->portno); 1361 } else { 1362 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1363 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1364 } 1365 UWRITE1(sc, MUSB2_REG_TXTI, 1366 motg_speed(dev->speed) | 1367 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1368 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1369 ); 1370 if (epnumber == 0) { 1371 if (sc->sc_high_speed) { 1372 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1373 NAK_TO_CTRL_HIGH); 1374 } else { 1375 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1376 } 1377 } else { 1378 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1379 == UE_BULK) { 1380 if (sc->sc_high_speed) { 1381 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1382 NAK_TO_BULK_HIGH); 1383 } else { 1384 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1385 } 1386 } else { 1387 if (sc->sc_high_speed) { 1388 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1389 } else { 1390 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1391 } 1392 } 1393 } 1394 } 1395 1396 static void 1397 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1398 { 1399 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1400 usbd_device_handle dev = xfer->pipe->device; 1401 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1402 int epnumber = otgpipe->hw_ep->ep_number; 1403 1404 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1405 if (dev->myhsport) { 1406 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1407 dev->myhsport->parent->address); 1408 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1409 dev->myhsport->portno); 1410 } else { 1411 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1412 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1413 } 1414 UWRITE1(sc, MUSB2_REG_RXTI, 1415 motg_speed(dev->speed) | 1416 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1417 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1418 ); 1419 if (epnumber == 0) { 1420 if (sc->sc_high_speed) { 1421 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1422 NAK_TO_CTRL_HIGH); 1423 } else { 1424 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1425 } 1426 } else { 1427 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1428 == UE_BULK) { 1429 if (sc->sc_high_speed) { 1430 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1431 NAK_TO_BULK_HIGH); 1432 } else { 1433 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1434 } 1435 } else { 1436 if (sc->sc_high_speed) { 1437 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1438 } else { 1439 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1440 } 1441 } 1442 } 1443 } 1444 1445 static usbd_status 1446 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1447 { 1448 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1449 usbd_status err; 1450 1451 /* Insert last in queue. */ 1452 mutex_enter(&sc->sc_lock); 1453 err = usb_insert_transfer(xfer); 1454 xfer->status = USBD_NOT_STARTED; 1455 mutex_exit(&sc->sc_lock); 1456 if (err) 1457 return (err); 1458 1459 /* 1460 * Pipe isn't running (otherwise err would be USBD_INPROG), 1461 * so start it first. 1462 */ 1463 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1464 } 1465 1466 static usbd_status 1467 motg_device_ctrl_start(usbd_xfer_handle xfer) 1468 { 1469 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1470 usbd_status err; 1471 mutex_enter(&sc->sc_lock); 1472 err = motg_device_ctrl_start1(sc); 1473 mutex_exit(&sc->sc_lock); 1474 if (err != USBD_IN_PROGRESS) 1475 return err; 1476 if (sc->sc_bus.use_polling) 1477 motg_waitintr(sc, xfer); 1478 return USBD_IN_PROGRESS; 1479 } 1480 1481 static usbd_status 1482 motg_device_ctrl_start1(struct motg_softc *sc) 1483 { 1484 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1485 usbd_xfer_handle xfer = NULL; 1486 struct motg_pipe *otgpipe; 1487 usbd_status err = 0; 1488 1489 KASSERT(mutex_owned(&sc->sc_lock)); 1490 if (sc->sc_dying) 1491 return (USBD_IOERROR); 1492 1493 if (!sc->sc_connected) 1494 return (USBD_IOERROR); 1495 1496 if (ep->xfer != NULL) { 1497 err = USBD_IN_PROGRESS; 1498 goto end; 1499 } 1500 /* locate the first pipe with work to do */ 1501 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1502 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1503 DPRINTFN(MD_CTRL, 1504 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1505 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1506 1507 if (xfer != NULL) { 1508 /* move this pipe to the end of the list */ 1509 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1510 motg_pipe, ep_pipe_list); 1511 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1512 otgpipe, ep_pipe_list); 1513 break; 1514 } 1515 } 1516 if (xfer == NULL) { 1517 err = USBD_NOT_STARTED; 1518 goto end; 1519 } 1520 xfer->status = USBD_IN_PROGRESS; 1521 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1522 KASSERT(otgpipe->hw_ep == ep); 1523 #ifdef DIAGNOSTIC 1524 if (!(xfer->rqflags & URQ_REQUEST)) 1525 panic("motg_device_ctrl_transfer: not a request"); 1526 #endif 1527 // KASSERT(xfer->actlen == 0); 1528 xfer->actlen = 0; 1529 1530 ep->xfer = xfer; 1531 ep->datalen = xfer->length; 1532 if (ep->datalen > 0) 1533 ep->data = KERNADDR(&xfer->dmabuf, 0); 1534 else 1535 ep->data = NULL; 1536 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1537 (ep->datalen % 64) == 0) 1538 ep->need_short_xfer = 1; 1539 else 1540 ep->need_short_xfer = 0; 1541 /* now we need send this request */ 1542 DPRINTFN(MD_CTRL, 1543 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1544 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1545 xfer->pipe->device->address)); 1546 KASSERT(ep->phase == IDLE); 1547 ep->phase = SETUP; 1548 /* select endpoint 0 */ 1549 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1550 /* fifo should be empty at this point */ 1551 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1552 /* send data */ 1553 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1554 KASSERT(sizeof(xfer->request) == 8); 1555 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1556 (void *)&xfer->request, sizeof(xfer->request)); 1557 1558 motg_setup_endpoint_tx(xfer); 1559 /* start transaction */ 1560 UWRITE1(sc, MUSB2_REG_TXCSRL, 1561 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1562 1563 end: 1564 if (err) 1565 return (err); 1566 1567 return (USBD_IN_PROGRESS); 1568 } 1569 1570 static void 1571 motg_device_ctrl_read(usbd_xfer_handle xfer) 1572 { 1573 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1574 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1575 /* assume endpoint already selected */ 1576 motg_setup_endpoint_rx(xfer); 1577 /* start transaction */ 1578 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1579 otgpipe->hw_ep->phase = DATA_IN; 1580 } 1581 1582 static void 1583 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1584 { 1585 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1586 usbd_xfer_handle xfer = ep->xfer; 1587 uint8_t csr; 1588 int datalen, max_datalen; 1589 char *data; 1590 bool got_short; 1591 usbd_status new_status = USBD_IN_PROGRESS; 1592 1593 KASSERT(mutex_owned(&sc->sc_lock)); 1594 1595 #ifdef DIAGNOSTIC 1596 if (ep->phase != DATA_IN && 1597 ep->phase != STATUS_IN) 1598 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1599 #endif 1600 /* select endpoint 0 */ 1601 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1602 1603 /* read out FIFO status */ 1604 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1605 DPRINTFN(MD_CTRL, 1606 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1607 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1608 1609 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1610 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1611 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1612 1613 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1614 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1615 new_status = USBD_TIMEOUT; /* XXX */ 1616 goto complete; 1617 } 1618 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1619 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1620 new_status = USBD_STALLED; 1621 else 1622 new_status = USBD_IOERROR; 1623 /* clear status */ 1624 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1625 goto complete; 1626 } 1627 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1628 return; /* no data yet */ 1629 1630 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1631 goto complete; 1632 1633 if (ep->phase == STATUS_IN) { 1634 new_status = USBD_NORMAL_COMPLETION; 1635 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1636 goto complete; 1637 } 1638 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1639 DPRINTFN(MD_CTRL, 1640 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1641 ep->phase, datalen)); 1642 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1643 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1644 ep->datalen); 1645 if (datalen > max_datalen) { 1646 new_status = USBD_IOERROR; 1647 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1648 goto complete; 1649 } 1650 got_short = (datalen < max_datalen); 1651 if (datalen > 0) { 1652 KASSERT(ep->phase == DATA_IN); 1653 data = ep->data; 1654 ep->data += datalen; 1655 ep->datalen -= datalen; 1656 xfer->actlen += datalen; 1657 if (((vaddr_t)data & 0x3) == 0 && 1658 (datalen >> 2) > 0) { 1659 DPRINTFN(MD_CTRL, 1660 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1661 data, datalen)); 1662 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1663 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1664 data += (datalen & ~0x3); 1665 datalen -= (datalen & ~0x3); 1666 } 1667 DPRINTFN(MD_CTRL, 1668 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1669 data, datalen)); 1670 if (datalen) { 1671 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1672 MUSB2_REG_EPFIFO(0), data, datalen); 1673 } 1674 } 1675 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1676 KASSERT(ep->phase == DATA_IN); 1677 if (got_short || (ep->datalen == 0)) { 1678 if (ep->need_short_xfer == 0) { 1679 ep->phase = STATUS_OUT; 1680 UWRITE1(sc, MUSB2_REG_TXCSRH, 1681 UREAD1(sc, MUSB2_REG_TXCSRH) | 1682 MUSB2_MASK_CSR0H_PING_DIS); 1683 motg_setup_endpoint_tx(xfer); 1684 UWRITE1(sc, MUSB2_REG_TXCSRL, 1685 MUSB2_MASK_CSR0L_STATUSPKT | 1686 MUSB2_MASK_CSR0L_TXPKTRDY); 1687 return; 1688 } 1689 ep->need_short_xfer = 0; 1690 } 1691 motg_device_ctrl_read(xfer); 1692 return; 1693 complete: 1694 ep->phase = IDLE; 1695 ep->xfer = NULL; 1696 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1697 KASSERT(new_status != USBD_IN_PROGRESS); 1698 xfer->status = new_status; 1699 usb_transfer_complete(xfer); 1700 } 1701 motg_device_ctrl_start1(sc); 1702 } 1703 1704 static void 1705 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1706 { 1707 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1708 usbd_xfer_handle xfer = ep->xfer; 1709 uint8_t csr; 1710 int datalen; 1711 char *data; 1712 usbd_status new_status = USBD_IN_PROGRESS; 1713 1714 KASSERT(mutex_owned(&sc->sc_lock)); 1715 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1716 motg_device_ctrl_intr_rx(sc); 1717 return; 1718 } 1719 1720 #ifdef DIAGNOSTIC 1721 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1722 ep->phase != STATUS_OUT) 1723 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1724 #endif 1725 /* select endpoint 0 */ 1726 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1727 1728 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1729 DPRINTFN(MD_CTRL, 1730 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1731 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1732 1733 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1734 /* command not accepted */ 1735 new_status = USBD_STALLED; 1736 /* clear status */ 1737 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1738 goto complete; 1739 } 1740 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1741 new_status = USBD_TIMEOUT; /* XXX */ 1742 /* flush fifo */ 1743 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1744 UWRITE1(sc, MUSB2_REG_TXCSRH, 1745 UREAD1(sc, MUSB2_REG_TXCSRH) | 1746 MUSB2_MASK_CSR0H_FFLUSH); 1747 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1748 } 1749 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1750 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1751 goto complete; 1752 } 1753 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1754 new_status = USBD_IOERROR; 1755 /* clear status */ 1756 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1757 goto complete; 1758 } 1759 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1760 /* data still not sent */ 1761 return; 1762 } 1763 if (xfer == NULL) 1764 goto complete; 1765 if (ep->phase == STATUS_OUT) { 1766 /* 1767 * we have sent status and got no error; 1768 * declare transfer complete 1769 */ 1770 DPRINTFN(MD_CTRL, 1771 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1772 xfer, xfer->status)); 1773 new_status = USBD_NORMAL_COMPLETION; 1774 goto complete; 1775 } 1776 if (ep->datalen == 0) { 1777 if (ep->need_short_xfer) { 1778 ep->need_short_xfer = 0; 1779 /* one more data phase */ 1780 if (xfer->request.bmRequestType & UT_READ) { 1781 DPRINTFN(MD_CTRL, 1782 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1783 motg_device_ctrl_read(xfer); 1784 return; 1785 } /* else fall back to DATA_OUT */ 1786 } else { 1787 DPRINTFN(MD_CTRL, 1788 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1789 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1790 ep->phase = STATUS_IN; 1791 UWRITE1(sc, MUSB2_REG_RXCSRH, 1792 UREAD1(sc, MUSB2_REG_RXCSRH) | 1793 MUSB2_MASK_CSR0H_PING_DIS); 1794 motg_setup_endpoint_rx(xfer); 1795 UWRITE1(sc, MUSB2_REG_TXCSRL, 1796 MUSB2_MASK_CSR0L_STATUSPKT | 1797 MUSB2_MASK_CSR0L_REQPKT); 1798 return; 1799 } 1800 } 1801 if (xfer->request.bmRequestType & UT_READ) { 1802 motg_device_ctrl_read(xfer); 1803 return; 1804 } 1805 /* setup a dataout phase */ 1806 datalen = min(ep->datalen, 1807 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1808 ep->phase = DATA_OUT; 1809 DPRINTFN(MD_CTRL, 1810 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1811 UREAD1(sc, MUSB2_REG_TXCSRH))); 1812 if (datalen) { 1813 data = ep->data; 1814 ep->data += datalen; 1815 ep->datalen -= datalen; 1816 xfer->actlen += datalen; 1817 if (((vaddr_t)data & 0x3) == 0 && 1818 (datalen >> 2) > 0) { 1819 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1820 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1821 data += (datalen & ~0x3); 1822 datalen -= (datalen & ~0x3); 1823 } 1824 if (datalen) { 1825 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1826 MUSB2_REG_EPFIFO(0), data, datalen); 1827 } 1828 } 1829 /* send data */ 1830 motg_setup_endpoint_tx(xfer); 1831 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1832 return; 1833 1834 complete: 1835 ep->phase = IDLE; 1836 ep->xfer = NULL; 1837 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1838 KASSERT(new_status != USBD_IN_PROGRESS); 1839 xfer->status = new_status; 1840 usb_transfer_complete(xfer); 1841 } 1842 motg_device_ctrl_start1(sc); 1843 } 1844 1845 /* Abort a device control request. */ 1846 void 1847 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1848 { 1849 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1850 motg_device_xfer_abort(xfer); 1851 } 1852 1853 /* Close a device control pipe */ 1854 void 1855 motg_device_ctrl_close(usbd_pipe_handle pipe) 1856 { 1857 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 1858 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1859 struct motg_pipe *otgpipeiter; 1860 1861 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1862 KASSERT(mutex_owned(&sc->sc_lock)); 1863 KASSERT(otgpipe->hw_ep->xfer == NULL || 1864 otgpipe->hw_ep->xfer->pipe != pipe); 1865 1866 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1867 if (otgpipeiter == otgpipe) { 1868 /* remove from list */ 1869 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1870 motg_pipe, ep_pipe_list); 1871 otgpipe->hw_ep->refcount--; 1872 /* we're done */ 1873 return; 1874 } 1875 } 1876 panic("motg_device_ctrl_close: not found"); 1877 } 1878 1879 void 1880 motg_device_ctrl_done(usbd_xfer_handle xfer) 1881 { 1882 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 1883 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1884 KASSERT(otgpipe->hw_ep->xfer != xfer); 1885 } 1886 1887 static usbd_status 1888 motg_device_data_transfer(usbd_xfer_handle xfer) 1889 { 1890 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1891 usbd_status err; 1892 1893 /* Insert last in queue. */ 1894 mutex_enter(&sc->sc_lock); 1895 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1896 xfer, xfer->status)); 1897 err = usb_insert_transfer(xfer); 1898 xfer->status = USBD_NOT_STARTED; 1899 mutex_exit(&sc->sc_lock); 1900 if (err) 1901 return (err); 1902 1903 /* 1904 * Pipe isn't running (otherwise err would be USBD_INPROG), 1905 * so start it first. 1906 */ 1907 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1908 } 1909 1910 static usbd_status 1911 motg_device_data_start(usbd_xfer_handle xfer) 1912 { 1913 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1914 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1915 usbd_status err; 1916 mutex_enter(&sc->sc_lock); 1917 DPRINTF(("motg_device_data_start(%p) status %d\n", 1918 xfer, xfer->status)); 1919 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1920 mutex_exit(&sc->sc_lock); 1921 if (err != USBD_IN_PROGRESS) 1922 return err; 1923 if (sc->sc_bus.use_polling) 1924 motg_waitintr(sc, xfer); 1925 return USBD_IN_PROGRESS; 1926 } 1927 1928 static usbd_status 1929 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1930 { 1931 usbd_xfer_handle xfer = NULL; 1932 struct motg_pipe *otgpipe; 1933 usbd_status err = 0; 1934 uint32_t val __diagused; 1935 1936 KASSERT(mutex_owned(&sc->sc_lock)); 1937 if (sc->sc_dying) 1938 return (USBD_IOERROR); 1939 1940 if (!sc->sc_connected) 1941 return (USBD_IOERROR); 1942 1943 if (ep->xfer != NULL) { 1944 err = USBD_IN_PROGRESS; 1945 goto end; 1946 } 1947 /* locate the first pipe with work to do */ 1948 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1949 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1950 DPRINTFN(MD_BULK, 1951 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1952 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1953 if (xfer != NULL) { 1954 /* move this pipe to the end of the list */ 1955 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1956 motg_pipe, ep_pipe_list); 1957 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1958 otgpipe, ep_pipe_list); 1959 break; 1960 } 1961 } 1962 if (xfer == NULL) { 1963 err = USBD_NOT_STARTED; 1964 goto end; 1965 } 1966 xfer->status = USBD_IN_PROGRESS; 1967 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1968 KASSERT(otgpipe->hw_ep == ep); 1969 #ifdef DIAGNOSTIC 1970 if (xfer->rqflags & URQ_REQUEST) 1971 panic("motg_device_data_transfer: a request"); 1972 #endif 1973 // KASSERT(xfer->actlen == 0); 1974 xfer->actlen = 0; 1975 1976 ep->xfer = xfer; 1977 ep->datalen = xfer->length; 1978 KASSERT(ep->datalen > 0); 1979 ep->data = KERNADDR(&xfer->dmabuf, 0); 1980 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1981 (ep->datalen % 64) == 0) 1982 ep->need_short_xfer = 1; 1983 else 1984 ep->need_short_xfer = 0; 1985 /* now we need send this request */ 1986 DPRINTFN(MD_BULK, 1987 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 1988 xfer, 1989 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 1990 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1991 xfer->pipe->device->address)); 1992 KASSERT(ep->phase == IDLE); 1993 /* select endpoint */ 1994 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1995 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 1996 == UE_DIR_IN) { 1997 val = UREAD1(sc, MUSB2_REG_RXCSRL); 1998 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 1999 motg_device_data_read(xfer); 2000 } else { 2001 ep->phase = DATA_OUT; 2002 val = UREAD1(sc, MUSB2_REG_TXCSRL); 2003 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 2004 motg_device_data_write(xfer); 2005 } 2006 end: 2007 if (err) 2008 return (err); 2009 2010 return (USBD_IN_PROGRESS); 2011 } 2012 2013 static void 2014 motg_device_data_read(usbd_xfer_handle xfer) 2015 { 2016 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2017 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2018 uint32_t val; 2019 2020 KASSERT(mutex_owned(&sc->sc_lock)); 2021 /* assume endpoint already selected */ 2022 motg_setup_endpoint_rx(xfer); 2023 /* Max packet size */ 2024 UWRITE2(sc, MUSB2_REG_RXMAXP, 2025 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2026 /* Data Toggle */ 2027 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2028 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2029 if (otgpipe->nexttoggle) 2030 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2031 else 2032 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2033 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2034 2035 DPRINTFN(MD_BULK, 2036 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2037 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2038 /* start transaction */ 2039 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2040 otgpipe->hw_ep->phase = DATA_IN; 2041 } 2042 2043 static void 2044 motg_device_data_write(usbd_xfer_handle xfer) 2045 { 2046 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2047 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2048 struct motg_hw_ep *ep = otgpipe->hw_ep; 2049 int datalen; 2050 char *data; 2051 uint32_t val; 2052 2053 KASSERT(xfer!=NULL); 2054 KASSERT(mutex_owned(&sc->sc_lock)); 2055 2056 datalen = min(ep->datalen, 2057 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2058 ep->phase = DATA_OUT; 2059 DPRINTFN(MD_BULK, 2060 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2061 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2062 2063 /* assume endpoint already selected */ 2064 /* write data to fifo */ 2065 data = ep->data; 2066 ep->data += datalen; 2067 ep->datalen -= datalen; 2068 xfer->actlen += datalen; 2069 if (((vaddr_t)data & 0x3) == 0 && 2070 (datalen >> 2) > 0) { 2071 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2072 MUSB2_REG_EPFIFO(ep->ep_number), 2073 (void *)data, datalen >> 2); 2074 data += (datalen & ~0x3); 2075 datalen -= (datalen & ~0x3); 2076 } 2077 if (datalen) { 2078 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2079 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2080 } 2081 2082 motg_setup_endpoint_tx(xfer); 2083 /* Max packet size */ 2084 UWRITE2(sc, MUSB2_REG_TXMAXP, 2085 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2086 /* Data Toggle */ 2087 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2088 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2089 if (otgpipe->nexttoggle) 2090 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2091 else 2092 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2093 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2094 2095 /* start transaction */ 2096 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2097 } 2098 2099 static void 2100 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2101 { 2102 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2103 usbd_xfer_handle xfer = ep->xfer; 2104 uint8_t csr; 2105 int datalen, max_datalen; 2106 char *data; 2107 bool got_short; 2108 usbd_status new_status = USBD_IN_PROGRESS; 2109 2110 KASSERT(mutex_owned(&sc->sc_lock)); 2111 KASSERT(ep->ep_number == epnumber); 2112 2113 DPRINTFN(MD_BULK, 2114 ("motg_device_intr_rx on ep %d\n", epnumber)); 2115 /* select endpoint */ 2116 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2117 2118 /* read out FIFO status */ 2119 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2120 DPRINTFN(MD_BULK, 2121 ("motg_device_intr_rx phase %d csr 0x%x\n", 2122 ep->phase, csr)); 2123 2124 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2125 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2126 return; 2127 2128 #ifdef DIAGNOSTIC 2129 if (ep->phase != DATA_IN) 2130 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2131 #endif 2132 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2133 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2134 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2135 2136 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2137 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2138 new_status = USBD_TIMEOUT; /* XXX */ 2139 goto complete; 2140 } 2141 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2142 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2143 new_status = USBD_STALLED; 2144 else 2145 new_status = USBD_IOERROR; 2146 /* clear status */ 2147 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2148 goto complete; 2149 } 2150 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2151 2152 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2153 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2154 goto complete; 2155 } 2156 2157 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2158 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2159 2160 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2161 DPRINTFN(MD_BULK, 2162 ("motg_device_intr_rx phase %d datalen %d\n", 2163 ep->phase, datalen)); 2164 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2165 max_datalen = min( 2166 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2167 ep->datalen); 2168 if (datalen > max_datalen) { 2169 new_status = USBD_IOERROR; 2170 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2171 goto complete; 2172 } 2173 got_short = (datalen < max_datalen); 2174 if (datalen > 0) { 2175 KASSERT(ep->phase == DATA_IN); 2176 data = ep->data; 2177 ep->data += datalen; 2178 ep->datalen -= datalen; 2179 xfer->actlen += datalen; 2180 if (((vaddr_t)data & 0x3) == 0 && 2181 (datalen >> 2) > 0) { 2182 DPRINTFN(MD_BULK, 2183 ("motg_device_intr_rx r4 data %p len %d\n", 2184 data, datalen)); 2185 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2186 MUSB2_REG_EPFIFO(ep->ep_number), 2187 (void *)data, datalen >> 2); 2188 data += (datalen & ~0x3); 2189 datalen -= (datalen & ~0x3); 2190 } 2191 DPRINTFN(MD_BULK, 2192 ("motg_device_intr_rx r1 data %p len %d\n", 2193 data, datalen)); 2194 if (datalen) { 2195 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2196 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2197 } 2198 } 2199 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2200 KASSERT(ep->phase == DATA_IN); 2201 if (got_short || (ep->datalen == 0)) { 2202 if (ep->need_short_xfer == 0) { 2203 new_status = USBD_NORMAL_COMPLETION; 2204 goto complete; 2205 } 2206 ep->need_short_xfer = 0; 2207 } 2208 motg_device_data_read(xfer); 2209 return; 2210 complete: 2211 DPRINTFN(MD_BULK, 2212 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2213 (xfer != NULL) ? xfer->status : 0)); 2214 ep->phase = IDLE; 2215 ep->xfer = NULL; 2216 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2217 KASSERT(new_status != USBD_IN_PROGRESS); 2218 xfer->status = new_status; 2219 usb_transfer_complete(xfer); 2220 } 2221 motg_device_data_start1(sc, ep); 2222 } 2223 2224 static void 2225 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2226 { 2227 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2228 usbd_xfer_handle xfer = ep->xfer; 2229 uint8_t csr; 2230 struct motg_pipe *otgpipe; 2231 usbd_status new_status = USBD_IN_PROGRESS; 2232 2233 KASSERT(mutex_owned(&sc->sc_lock)); 2234 KASSERT(ep->ep_number == epnumber); 2235 2236 DPRINTFN(MD_BULK, 2237 ("motg_device_intr_tx on ep %d\n", epnumber)); 2238 /* select endpoint */ 2239 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2240 2241 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2242 DPRINTFN(MD_BULK, 2243 ("motg_device_intr_tx phase %d csr 0x%x\n", 2244 ep->phase, csr)); 2245 2246 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2247 /* command not accepted */ 2248 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2249 new_status = USBD_STALLED; 2250 else 2251 new_status = USBD_IOERROR; 2252 /* clear status */ 2253 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2254 goto complete; 2255 } 2256 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2257 new_status = USBD_TIMEOUT; /* XXX */ 2258 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2259 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2260 /* flush fifo */ 2261 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2262 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2263 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2264 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2265 delay(1000); 2266 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2267 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2268 epnumber, csr)); 2269 } 2270 goto complete; 2271 } 2272 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2273 /* data still not sent */ 2274 return; 2275 } 2276 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2277 goto complete; 2278 #ifdef DIAGNOSTIC 2279 if (ep->phase != DATA_OUT) 2280 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2281 #endif 2282 2283 otgpipe = (struct motg_pipe *)xfer->pipe; 2284 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2285 2286 if (ep->datalen == 0) { 2287 if (ep->need_short_xfer) { 2288 ep->need_short_xfer = 0; 2289 /* one more data phase */ 2290 } else { 2291 new_status = USBD_NORMAL_COMPLETION; 2292 goto complete; 2293 } 2294 } 2295 motg_device_data_write(xfer); 2296 return; 2297 2298 complete: 2299 DPRINTFN(MD_BULK, 2300 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2301 (xfer != NULL) ? xfer->status : 0)); 2302 #ifdef DIAGNOSTIC 2303 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2304 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2305 #endif 2306 ep->phase = IDLE; 2307 ep->xfer = NULL; 2308 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2309 KASSERT(new_status != USBD_IN_PROGRESS); 2310 xfer->status = new_status; 2311 usb_transfer_complete(xfer); 2312 } 2313 motg_device_data_start1(sc, ep); 2314 } 2315 2316 /* Abort a device control request. */ 2317 void 2318 motg_device_data_abort(usbd_xfer_handle xfer) 2319 { 2320 #ifdef DIAGNOSTIC 2321 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2322 #endif 2323 KASSERT(mutex_owned(&sc->sc_lock)); 2324 2325 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2326 motg_device_xfer_abort(xfer); 2327 } 2328 2329 /* Close a device control pipe */ 2330 void 2331 motg_device_data_close(usbd_pipe_handle pipe) 2332 { 2333 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 2334 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2335 struct motg_pipe *otgpipeiter; 2336 2337 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2338 KASSERT(mutex_owned(&sc->sc_lock)); 2339 KASSERT(otgpipe->hw_ep->xfer == NULL || 2340 otgpipe->hw_ep->xfer->pipe != pipe); 2341 2342 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2343 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2344 if (otgpipeiter == otgpipe) { 2345 /* remove from list */ 2346 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2347 motg_pipe, ep_pipe_list); 2348 otgpipe->hw_ep->refcount--; 2349 /* we're done */ 2350 return; 2351 } 2352 } 2353 panic("motg_device_data_close: not found"); 2354 } 2355 2356 void 2357 motg_device_data_done(usbd_xfer_handle xfer) 2358 { 2359 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 2360 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2361 KASSERT(otgpipe->hw_ep->xfer != xfer); 2362 } 2363 2364 /* 2365 * Wait here until controller claims to have an interrupt. 2366 * Then call motg_intr and return. Use timeout to avoid waiting 2367 * too long. 2368 * Only used during boot when interrupts are not enabled yet. 2369 */ 2370 void 2371 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2372 { 2373 int timo = xfer->timeout; 2374 2375 mutex_enter(&sc->sc_lock); 2376 2377 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2378 2379 for (; timo >= 0; timo--) { 2380 mutex_exit(&sc->sc_lock); 2381 usb_delay_ms(&sc->sc_bus, 1); 2382 mutex_spin_enter(&sc->sc_intr_lock); 2383 motg_poll(&sc->sc_bus); 2384 mutex_spin_exit(&sc->sc_intr_lock); 2385 mutex_enter(&sc->sc_lock); 2386 if (xfer->status != USBD_IN_PROGRESS) 2387 goto done; 2388 } 2389 2390 /* Timeout */ 2391 DPRINTF(("motg_waitintr: timeout\n")); 2392 panic("motg_waitintr: timeout"); 2393 /* XXX handle timeout ! */ 2394 2395 done: 2396 mutex_exit(&sc->sc_lock); 2397 } 2398 2399 void 2400 motg_device_clear_toggle(usbd_pipe_handle pipe) 2401 { 2402 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2403 otgpipe->nexttoggle = 0; 2404 } 2405 2406 /* Abort a device control request. */ 2407 static void 2408 motg_device_xfer_abort(usbd_xfer_handle xfer) 2409 { 2410 int wake; 2411 uint8_t csr; 2412 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2413 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2414 KASSERT(mutex_owned(&sc->sc_lock)); 2415 2416 DPRINTF(("motg_device_xfer_abort:\n")); 2417 if (xfer->hcflags & UXFER_ABORTING) { 2418 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2419 xfer->hcflags |= UXFER_ABORTWAIT; 2420 while (xfer->hcflags & UXFER_ABORTING) 2421 cv_wait(&xfer->hccv, &sc->sc_lock); 2422 return; 2423 } 2424 xfer->hcflags |= UXFER_ABORTING; 2425 if (otgpipe->hw_ep->xfer == xfer) { 2426 KASSERT(xfer->status == USBD_IN_PROGRESS); 2427 otgpipe->hw_ep->xfer = NULL; 2428 if (otgpipe->hw_ep->ep_number > 0) { 2429 /* select endpoint */ 2430 UWRITE1(sc, MUSB2_REG_EPINDEX, 2431 otgpipe->hw_ep->ep_number); 2432 if (otgpipe->hw_ep->phase == DATA_OUT) { 2433 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2434 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2435 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2436 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2437 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2438 } 2439 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2440 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2441 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2442 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2443 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2444 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2445 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2446 } 2447 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2448 } 2449 otgpipe->hw_ep->phase = IDLE; 2450 } 2451 } 2452 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2453 wake = xfer->hcflags & UXFER_ABORTWAIT; 2454 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2455 usb_transfer_complete(xfer); 2456 if (wake) 2457 cv_broadcast(&xfer->hccv); 2458 } 2459
Indexes created Wed Sep 24 02:09:48 GMT 2025