motg.c revision 1.9
1 /* $NetBSD: motg.c,v 1.9 2014/09/13 14:46:50 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2011, 2012, 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca), 10 * Matthew R. Green (mrg (at) eterna.com.au), and Manuel Bouyer (bouyer (at) netbsd.org). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 35 /* 36 * This file contains the driver for the Mentor Graphics Inventra USB 37 * 2.0 High Speed Dual-Role controller. 38 * 39 * NOTE: The current implementation only supports Device Side Mode! 40 */ 41 42 #include <sys/cdefs.h> 43 __KERNEL_RCSID(0, "$NetBSD: motg.c,v 1.9 2014/09/13 14:46:50 jmcneill Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/kmem.h> 49 #include <sys/device.h> 50 #include <sys/select.h> 51 #include <sys/extent.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/bus.h> 55 #include <sys/cpu.h> 56 57 #include <machine/endian.h> 58 59 #include <dev/usb/usb.h> 60 #include <dev/usb/usbdi.h> 61 #include <dev/usb/usbdivar.h> 62 #include <dev/usb/usb_mem.h> 63 #include <dev/usb/usb_quirks.h> 64 65 #include <dev/usb/motgreg.h> 66 #include <dev/usb/motgvar.h> 67 #include <dev/usb/usbroothub_subr.h> 68 69 #define MOTG_DEBUG 70 #ifdef MOTG_DEBUG 71 #define DPRINTF(x) if (motgdebug) printf x 72 #define DPRINTFN(n,x) if (motgdebug & (n)) printf x 73 #define MD_ROOT 0x0002 74 #define MD_CTRL 0x0004 75 #define MD_BULK 0x0008 76 // int motgdebug = MD_ROOT | MD_CTRL | MD_BULK; 77 int motgdebug = 0; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 /* various timeouts, for various speeds */ 84 /* control NAK timeouts */ 85 #define NAK_TO_CTRL 10 /* 1024 frames, about 1s */ 86 #define NAK_TO_CTRL_HIGH 13 /* 8k microframes, about 0.8s */ 87 88 /* intr/iso polling intervals */ 89 #define POLL_TO 100 /* 100 frames, about 0.1s */ 90 #define POLL_TO_HIGH 10 /* 100 microframes, about 0.12s */ 91 92 /* bulk NAK timeouts */ 93 #define NAK_TO_BULK 0 /* disabled */ 94 #define NAK_TO_BULK_HIGH 0 95 96 static void motg_hub_change(struct motg_softc *); 97 static usbd_status motg_root_ctrl_transfer(usbd_xfer_handle); 98 static usbd_status motg_root_ctrl_start(usbd_xfer_handle); 99 static void motg_root_ctrl_abort(usbd_xfer_handle); 100 static void motg_root_ctrl_close(usbd_pipe_handle); 101 static void motg_root_ctrl_done(usbd_xfer_handle); 102 103 static usbd_status motg_root_intr_transfer(usbd_xfer_handle); 104 static usbd_status motg_root_intr_start(usbd_xfer_handle); 105 static void motg_root_intr_abort(usbd_xfer_handle); 106 static void motg_root_intr_close(usbd_pipe_handle); 107 static void motg_root_intr_done(usbd_xfer_handle); 108 109 static usbd_status motg_open(usbd_pipe_handle); 110 static void motg_poll(struct usbd_bus *); 111 static void motg_softintr(void *); 112 static usbd_status motg_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 113 static void motg_freem(struct usbd_bus *, usb_dma_t *); 114 static usbd_xfer_handle motg_allocx(struct usbd_bus *); 115 static void motg_freex(struct usbd_bus *, usbd_xfer_handle); 116 static void motg_get_lock(struct usbd_bus *, kmutex_t **); 117 static void motg_noop(usbd_pipe_handle pipe); 118 static usbd_status motg_portreset(struct motg_softc*); 119 120 static usbd_status motg_device_ctrl_transfer(usbd_xfer_handle); 121 static usbd_status motg_device_ctrl_start(usbd_xfer_handle); 122 static void motg_device_ctrl_abort(usbd_xfer_handle); 123 static void motg_device_ctrl_close(usbd_pipe_handle); 124 static void motg_device_ctrl_done(usbd_xfer_handle); 125 static usbd_status motg_device_ctrl_start1(struct motg_softc *); 126 static void motg_device_ctrl_read(usbd_xfer_handle); 127 static void motg_device_ctrl_intr_rx(struct motg_softc *); 128 static void motg_device_ctrl_intr_tx(struct motg_softc *); 129 130 static usbd_status motg_device_data_transfer(usbd_xfer_handle); 131 static usbd_status motg_device_data_start(usbd_xfer_handle); 132 static usbd_status motg_device_data_start1(struct motg_softc *, 133 struct motg_hw_ep *); 134 static void motg_device_data_abort(usbd_xfer_handle); 135 static void motg_device_data_close(usbd_pipe_handle); 136 static void motg_device_data_done(usbd_xfer_handle); 137 static void motg_device_intr_rx(struct motg_softc *, int); 138 static void motg_device_intr_tx(struct motg_softc *, int); 139 static void motg_device_data_read(usbd_xfer_handle); 140 static void motg_device_data_write(usbd_xfer_handle); 141 142 static void motg_waitintr(struct motg_softc *, usbd_xfer_handle); 143 static void motg_device_clear_toggle(usbd_pipe_handle); 144 static void motg_device_xfer_abort(usbd_xfer_handle); 145 146 #define MOTG_INTR_ENDPT 1 147 #define UBARR(sc) bus_space_barrier((sc)->sc_iot, (sc)->sc_ioh, 0, (sc)->sc_size, \ 148 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 149 #define UWRITE1(sc, r, x) \ 150 do { UBARR(sc); bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 151 } while (/*CONSTCOND*/0) 152 #define UWRITE2(sc, r, x) \ 153 do { UBARR(sc); bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 154 } while (/*CONSTCOND*/0) 155 #define UWRITE4(sc, r, x) \ 156 do { UBARR(sc); bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (r), (x)); \ 157 } while (/*CONSTCOND*/0) 158 159 static __inline uint32_t 160 UREAD1(struct motg_softc *sc, bus_size_t r) 161 { 162 163 UBARR(sc); 164 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, r); 165 } 166 static __inline uint32_t 167 UREAD2(struct motg_softc *sc, bus_size_t r) 168 { 169 170 UBARR(sc); 171 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, r); 172 } 173 174 #if 0 175 static __inline uint32_t 176 UREAD4(struct motg_softc *sc, bus_size_t r) 177 { 178 179 UBARR(sc); 180 return bus_space_read_4(sc->sc_iot, sc->sc_ioh, r); 181 } 182 #endif 183 184 static void 185 musbotg_pull_common(struct motg_softc *sc, uint8_t on) 186 { 187 uint8_t val; 188 189 val = UREAD1(sc, MUSB2_REG_POWER); 190 if (on) 191 val |= MUSB2_MASK_SOFTC; 192 else 193 val &= ~MUSB2_MASK_SOFTC; 194 195 UWRITE1(sc, MUSB2_REG_POWER, val); 196 } 197 198 const struct usbd_bus_methods motg_bus_methods = { 199 .open_pipe = motg_open, 200 .soft_intr = motg_softintr, 201 .do_poll = motg_poll, 202 .allocm = motg_allocm, 203 .freem = motg_freem, 204 .allocx = motg_allocx, 205 .freex = motg_freex, 206 .get_lock = motg_get_lock, 207 .new_device = NULL, 208 }; 209 210 const struct usbd_pipe_methods motg_root_ctrl_methods = { 211 .transfer = motg_root_ctrl_transfer, 212 .start = motg_root_ctrl_start, 213 .abort = motg_root_ctrl_abort, 214 .close = motg_root_ctrl_close, 215 .cleartoggle = motg_noop, 216 .done = motg_root_ctrl_done, 217 }; 218 219 const struct usbd_pipe_methods motg_root_intr_methods = { 220 .transfer = motg_root_intr_transfer, 221 .start = motg_root_intr_start, 222 .abort = motg_root_intr_abort, 223 .close = motg_root_intr_close, 224 .cleartoggle = motg_noop, 225 .done = motg_root_intr_done, 226 }; 227 228 const struct usbd_pipe_methods motg_device_ctrl_methods = { 229 .transfer = motg_device_ctrl_transfer, 230 .start = motg_device_ctrl_start, 231 .abort = motg_device_ctrl_abort, 232 .close = motg_device_ctrl_close, 233 .cleartoggle = motg_noop, 234 .done = motg_device_ctrl_done, 235 }; 236 237 const struct usbd_pipe_methods motg_device_data_methods = { 238 .transfer = motg_device_data_transfer, 239 .start = motg_device_data_start, 240 .abort = motg_device_data_abort, 241 .close = motg_device_data_close, 242 .cleartoggle = motg_device_clear_toggle, 243 .done = motg_device_data_done, 244 }; 245 246 usbd_status 247 motg_init(struct motg_softc *sc) 248 { 249 uint32_t nrx, ntx, val; 250 int dynfifo; 251 int offset, i; 252 253 if (sc->sc_mode == MOTG_MODE_DEVICE) 254 return USBD_NORMAL_COMPLETION; /* not supported */ 255 256 /* disable all interrupts */ 257 UWRITE1(sc, MUSB2_REG_INTUSBE, 0); 258 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 259 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 260 /* disable pullup */ 261 262 musbotg_pull_common(sc, 0); 263 264 /* disable double packet buffering XXX what's this ? */ 265 UWRITE2(sc, MUSB2_REG_RXDBDIS, 0xFFFF); 266 UWRITE2(sc, MUSB2_REG_TXDBDIS, 0xFFFF); 267 268 /* enable HighSpeed and ISO Update flags */ 269 270 UWRITE1(sc, MUSB2_REG_POWER, 271 MUSB2_MASK_HSENAB | MUSB2_MASK_ISOUPD); 272 273 if (sc->sc_mode == MOTG_MODE_DEVICE) { 274 /* clear Session bit, if set */ 275 val = UREAD1(sc, MUSB2_REG_DEVCTL); 276 val &= ~MUSB2_MASK_SESS; 277 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 278 } else { 279 /* Enter session for Host mode */ 280 val = UREAD1(sc, MUSB2_REG_DEVCTL); 281 val |= MUSB2_MASK_SESS; 282 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 283 } 284 delay(1000); 285 DPRINTF(("DEVCTL 0x%x\n", UREAD1(sc, MUSB2_REG_DEVCTL))); 286 287 /* disable testmode */ 288 289 UWRITE1(sc, MUSB2_REG_TESTMODE, 0); 290 291 /* set default value */ 292 293 UWRITE1(sc, MUSB2_REG_MISC, 0); 294 295 /* select endpoint index 0 */ 296 297 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 298 299 if (sc->sc_ep_max == 0) { 300 /* read out number of endpoints */ 301 nrx = (UREAD1(sc, MUSB2_REG_EPINFO) / 16); 302 303 ntx = (UREAD1(sc, MUSB2_REG_EPINFO) % 16); 304 305 /* these numbers exclude the control endpoint */ 306 307 DPRINTF(("RX/TX endpoints: %u/%u\n", nrx, ntx)); 308 309 sc->sc_ep_max = MAX(nrx, ntx); 310 } else { 311 nrx = ntx = sc->sc_ep_max; 312 } 313 if (sc->sc_ep_max == 0) { 314 aprint_error_dev(sc->sc_dev, " no endpoints\n"); 315 return USBD_INVAL; 316 } 317 KASSERT(sc->sc_ep_max <= MOTG_MAX_HW_EP); 318 /* read out configuration data */ 319 val = UREAD1(sc, MUSB2_REG_CONFDATA); 320 321 DPRINTF(("Config Data: 0x%02x\n", val)); 322 323 dynfifo = (val & MUSB2_MASK_CD_DYNFIFOSZ) ? 1 : 0; 324 325 if (dynfifo) { 326 aprint_normal_dev(sc->sc_dev, "Dynamic FIFO sizing detected, " 327 "assuming 16Kbytes of FIFO RAM\n"); 328 } 329 330 DPRINTF(("HW version: 0x%04x\n", UREAD1(sc, MUSB2_REG_HWVERS))); 331 332 /* initialise endpoint profiles */ 333 sc->sc_in_ep[0].ep_fifo_size = 64; 334 sc->sc_out_ep[0].ep_fifo_size = 0; /* not used */ 335 sc->sc_out_ep[0].ep_number = sc->sc_in_ep[0].ep_number = 0; 336 SIMPLEQ_INIT(&sc->sc_in_ep[0].ep_pipes); 337 offset = 64; 338 339 for (i = 1; i <= sc->sc_ep_max; i++) { 340 int fiforx_size, fifotx_size, fifo_size; 341 342 /* select endpoint */ 343 UWRITE1(sc, MUSB2_REG_EPINDEX, i); 344 345 val = UREAD1(sc, MUSB2_REG_FSIZE); 346 fiforx_size = (val & MUSB2_MASK_RX_FSIZE) >> 4; 347 fifotx_size = (val & MUSB2_MASK_TX_FSIZE); 348 349 DPRINTF(("Endpoint %u FIFO size: IN=%u, OUT=%u, DYN=%d\n", 350 i, fifotx_size, fiforx_size, dynfifo)); 351 352 if (dynfifo) { 353 if (i < 3) { 354 fifo_size = 12; /* 4K */ 355 } else if (i < 10) { 356 fifo_size = 10; /* 1K */ 357 } else { 358 fifo_size = 7; /* 128 bytes */ 359 } 360 if (fiforx_size && (i <= nrx)) { 361 fiforx_size = fifo_size; 362 if (fifo_size > 7) { 363 #if 0 364 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 365 MUSB2_VAL_FIFOSZ(fifo_size) | 366 MUSB2_MASK_FIFODB); 367 #else 368 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 369 MUSB2_VAL_FIFOSZ(fifo_size)); 370 #endif 371 } else { 372 UWRITE1(sc, MUSB2_REG_RXFIFOSZ, 373 MUSB2_VAL_FIFOSZ(fifo_size)); 374 } 375 UWRITE2(sc, MUSB2_REG_RXFIFOADD, 376 offset >> 3); 377 offset += (1 << fiforx_size); 378 } 379 if (fifotx_size && (i <= ntx)) { 380 fifotx_size = fifo_size; 381 if (fifo_size > 7) { 382 #if 0 383 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 384 MUSB2_VAL_FIFOSZ(fifo_size) | 385 MUSB2_MASK_FIFODB); 386 #else 387 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 388 MUSB2_VAL_FIFOSZ(fifo_size)); 389 #endif 390 } else { 391 UWRITE1(sc, MUSB2_REG_TXFIFOSZ, 392 MUSB2_VAL_FIFOSZ(fifo_size)); 393 } 394 395 UWRITE2(sc, MUSB2_REG_TXFIFOADD, 396 offset >> 3); 397 398 offset += (1 << fifotx_size); 399 } 400 } 401 if (fiforx_size && (i <= nrx)) { 402 sc->sc_in_ep[i].ep_fifo_size = (1 << fiforx_size); 403 SIMPLEQ_INIT(&sc->sc_in_ep[i].ep_pipes); 404 } 405 if (fifotx_size && (i <= ntx)) { 406 sc->sc_out_ep[i].ep_fifo_size = (1 << fifotx_size); 407 SIMPLEQ_INIT(&sc->sc_out_ep[i].ep_pipes); 408 } 409 sc->sc_out_ep[i].ep_number = sc->sc_in_ep[i].ep_number = i; 410 } 411 412 413 DPRINTF(("Dynamic FIFO size = %d bytes\n", offset)); 414 415 /* turn on default interrupts */ 416 417 if (sc->sc_mode == MOTG_MODE_HOST) { 418 UWRITE1(sc, MUSB2_REG_INTUSBE, 0xff); 419 UWRITE2(sc, MUSB2_REG_INTTXE, 0xffff); 420 UWRITE2(sc, MUSB2_REG_INTRXE, 0xffff); 421 } else 422 UWRITE1(sc, MUSB2_REG_INTUSBE, MUSB2_MASK_IRESET); 423 424 sc->sc_xferpool = pool_cache_init(sizeof(struct motg_xfer), 0, 0, 0, 425 "motgxfer", NULL, IPL_USB, NULL, NULL, NULL); 426 427 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 428 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 429 430 /* Set up the bus struct. */ 431 sc->sc_bus.methods = &motg_bus_methods; 432 sc->sc_bus.pipe_size = sizeof(struct motg_pipe); 433 sc->sc_bus.usbrev = USBREV_2_0; 434 sc->sc_bus.hci_private = sc; 435 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 436 "Mentor Graphics"); 437 sc->sc_child = config_found(sc->sc_dev, &sc->sc_bus, usbctlprint); 438 return USBD_NORMAL_COMPLETION; 439 } 440 441 static int 442 motg_select_ep(struct motg_softc *sc, usbd_pipe_handle pipe) 443 { 444 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 445 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 446 struct motg_hw_ep *ep; 447 int i, size; 448 449 ep = (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 450 sc->sc_in_ep : sc->sc_out_ep; 451 size = UE_GET_SIZE(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 452 453 for (i = sc->sc_ep_max; i >= 1; i--) { 454 DPRINTF(("%s_ep[%d].ep_fifo_size %d size %d ref %d\n", 455 (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) ? 456 "in" : "out", i, ep[i].ep_fifo_size, size, ep[i].refcount)); 457 if (ep[i].ep_fifo_size >= size) { 458 /* found a suitable endpoint */ 459 otgpipe->hw_ep = &ep[i]; 460 mutex_enter(&sc->sc_lock); 461 if (otgpipe->hw_ep->refcount > 0) { 462 /* no luck, try next */ 463 mutex_exit(&sc->sc_lock); 464 otgpipe->hw_ep = NULL; 465 } else { 466 otgpipe->hw_ep->refcount++; 467 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 468 otgpipe, ep_pipe_list); 469 mutex_exit(&sc->sc_lock); 470 return 0; 471 } 472 } 473 } 474 return -1; 475 } 476 477 /* Open a new pipe. */ 478 usbd_status 479 motg_open(usbd_pipe_handle pipe) 480 { 481 struct motg_softc *sc = pipe->device->bus->hci_private; 482 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 483 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 484 485 DPRINTF(("motg_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 486 pipe, pipe->device->address, 487 ed->bEndpointAddress, sc->sc_root_addr)); 488 489 if (sc->sc_dying) 490 return USBD_IOERROR; 491 492 /* toggle state needed for bulk endpoints */ 493 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 494 495 if (pipe->device->address == sc->sc_root_addr) { 496 switch (ed->bEndpointAddress) { 497 case USB_CONTROL_ENDPOINT: 498 pipe->methods = &motg_root_ctrl_methods; 499 break; 500 case UE_DIR_IN | MOTG_INTR_ENDPT: 501 pipe->methods = &motg_root_intr_methods; 502 break; 503 default: 504 return (USBD_INVAL); 505 } 506 } else { 507 switch (ed->bmAttributes & UE_XFERTYPE) { 508 case UE_CONTROL: 509 pipe->methods = &motg_device_ctrl_methods; 510 /* always use sc_in_ep[0] for in and out */ 511 otgpipe->hw_ep = &sc->sc_in_ep[0]; 512 mutex_enter(&sc->sc_lock); 513 otgpipe->hw_ep->refcount++; 514 SIMPLEQ_INSERT_TAIL(&otgpipe->hw_ep->ep_pipes, 515 otgpipe, ep_pipe_list); 516 mutex_exit(&sc->sc_lock); 517 break; 518 case UE_BULK: 519 case UE_INTERRUPT: 520 DPRINTFN(MD_BULK, 521 ("new %s %s pipe wMaxPacketSize %d\n", 522 (ed->bmAttributes & UE_XFERTYPE) == UE_BULK ? 523 "bulk" : "interrupt", 524 (UE_GET_DIR(pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN) ? "read" : "write", 525 UGETW(pipe->endpoint->edesc->wMaxPacketSize))); 526 if (motg_select_ep(sc, pipe) != 0) 527 goto bad; 528 KASSERT(otgpipe->hw_ep != NULL); 529 pipe->methods = &motg_device_data_methods; 530 otgpipe->nexttoggle = pipe->endpoint->datatoggle; 531 break; 532 default: 533 goto bad; 534 #ifdef notyet 535 case UE_ISOCHRONOUS: 536 ... 537 break; 538 #endif /* notyet */ 539 } 540 } 541 return (USBD_NORMAL_COMPLETION); 542 543 bad: 544 return (USBD_NOMEM); 545 } 546 547 void 548 motg_softintr(void *v) 549 { 550 struct usbd_bus *bus = v; 551 struct motg_softc *sc = bus->hci_private; 552 uint16_t rx_status, tx_status; 553 uint8_t ctrl_status; 554 uint32_t val; 555 int i; 556 557 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 558 559 DPRINTFN(MD_ROOT | MD_CTRL, 560 ("%s: motg_softintr\n", device_xname(sc->sc_dev))); 561 562 mutex_spin_enter(&sc->sc_intr_lock); 563 rx_status = sc->sc_intr_rx_ep; 564 sc->sc_intr_rx_ep = 0; 565 tx_status = sc->sc_intr_tx_ep; 566 sc->sc_intr_tx_ep = 0; 567 ctrl_status = sc->sc_intr_ctrl; 568 sc->sc_intr_ctrl = 0; 569 mutex_spin_exit(&sc->sc_intr_lock); 570 571 ctrl_status |= UREAD1(sc, MUSB2_REG_INTUSB); 572 573 if (ctrl_status & (MUSB2_MASK_IRESET | 574 MUSB2_MASK_IRESUME | MUSB2_MASK_ISUSP | 575 MUSB2_MASK_ICONN | MUSB2_MASK_IDISC)) { 576 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr bus 0x%x\n", 577 ctrl_status)); 578 579 if (ctrl_status & MUSB2_MASK_IRESET) { 580 sc->sc_isreset = 1; 581 sc->sc_port_suspended = 0; 582 sc->sc_port_suspended_change = 1; 583 sc->sc_connected_changed = 1; 584 sc->sc_port_enabled = 1; 585 586 val = UREAD1(sc, MUSB2_REG_POWER); 587 if (val & MUSB2_MASK_HSMODE) 588 sc->sc_high_speed = 1; 589 else 590 sc->sc_high_speed = 0; 591 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_softintr speed %d\n", 592 sc->sc_high_speed)); 593 594 /* turn off interrupts */ 595 val = MUSB2_MASK_IRESET; 596 val &= ~MUSB2_MASK_IRESUME; 597 val |= MUSB2_MASK_ISUSP; 598 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 599 UWRITE2(sc, MUSB2_REG_INTTXE, 0); 600 UWRITE2(sc, MUSB2_REG_INTRXE, 0); 601 } 602 if (ctrl_status & MUSB2_MASK_IRESUME) { 603 if (sc->sc_port_suspended) { 604 sc->sc_port_suspended = 0; 605 sc->sc_port_suspended_change = 1; 606 val = UREAD1(sc, MUSB2_REG_INTUSBE); 607 /* disable resume interrupt */ 608 val &= ~MUSB2_MASK_IRESUME; 609 /* enable suspend interrupt */ 610 val |= MUSB2_MASK_ISUSP; 611 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 612 } 613 } else if (ctrl_status & MUSB2_MASK_ISUSP) { 614 if (!sc->sc_port_suspended) { 615 sc->sc_port_suspended = 1; 616 sc->sc_port_suspended_change = 1; 617 618 val = UREAD1(sc, MUSB2_REG_INTUSBE); 619 /* disable suspend interrupt */ 620 val &= ~MUSB2_MASK_ISUSP; 621 /* enable resume interrupt */ 622 val |= MUSB2_MASK_IRESUME; 623 UWRITE1(sc, MUSB2_REG_INTUSBE, val); 624 } 625 } 626 if (ctrl_status & MUSB2_MASK_ICONN) { 627 sc->sc_connected = 1; 628 sc->sc_connected_changed = 1; 629 sc->sc_isreset = 1; 630 sc->sc_port_enabled = 1; 631 } else if (ctrl_status & MUSB2_MASK_IDISC) { 632 sc->sc_connected = 0; 633 sc->sc_connected_changed = 1; 634 sc->sc_isreset = 0; 635 sc->sc_port_enabled = 0; 636 } 637 638 /* complete root HUB interrupt endpoint */ 639 640 motg_hub_change(sc); 641 } 642 /* 643 * read in interrupt status and mix with the status we 644 * got from the wrapper 645 */ 646 rx_status |= UREAD2(sc, MUSB2_REG_INTRX); 647 tx_status |= UREAD2(sc, MUSB2_REG_INTTX); 648 649 if (rx_status & 0x01) 650 panic("ctrl_rx"); 651 if (tx_status & 0x01) 652 motg_device_ctrl_intr_tx(sc); 653 for (i = 1; i <= sc->sc_ep_max; i++) { 654 if (rx_status & (0x01 << i)) 655 motg_device_intr_rx(sc, i); 656 if (tx_status & (0x01 << i)) 657 motg_device_intr_tx(sc, i); 658 } 659 return; 660 } 661 662 void 663 motg_poll(struct usbd_bus *bus) 664 { 665 struct motg_softc *sc = bus->hci_private; 666 667 sc->sc_intr_poll(sc->sc_intr_poll_arg); 668 mutex_enter(&sc->sc_lock); 669 motg_softintr(bus); 670 mutex_exit(&sc->sc_lock); 671 } 672 673 int 674 motg_intr(struct motg_softc *sc, uint16_t rx_ep, uint16_t tx_ep, 675 uint8_t ctrl) 676 { 677 KASSERT(mutex_owned(&sc->sc_intr_lock)); 678 sc->sc_intr_tx_ep = tx_ep; 679 sc->sc_intr_rx_ep = rx_ep; 680 sc->sc_intr_ctrl = ctrl; 681 682 if (!sc->sc_bus.use_polling) { 683 sc->sc_bus.no_intrs++; 684 usb_schedsoftintr(&sc->sc_bus); 685 } 686 return 1; 687 } 688 689 int 690 motg_intr_vbus(struct motg_softc *sc, int vbus) 691 { 692 uint8_t val; 693 if (sc->sc_mode == MOTG_MODE_HOST && vbus == 0) { 694 DPRINTF(("motg_intr_vbus: vbus down, try to re-enable\n")); 695 /* try to re-enter session for Host mode */ 696 val = UREAD1(sc, MUSB2_REG_DEVCTL); 697 val |= MUSB2_MASK_SESS; 698 UWRITE1(sc, MUSB2_REG_DEVCTL, val); 699 } 700 return 1; 701 } 702 703 usbd_status 704 motg_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 705 { 706 struct motg_softc *sc = bus->hci_private; 707 usbd_status status; 708 709 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 710 if (status == USBD_NOMEM) 711 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 712 return status; 713 } 714 715 void 716 motg_freem(struct usbd_bus *bus, usb_dma_t *dma) 717 { 718 if (dma->block->flags & USB_DMA_RESERVE) { 719 usb_reserve_freem(&((struct motg_softc *)bus)->sc_dma_reserve, 720 dma); 721 return; 722 } 723 usb_freemem(&((struct motg_softc *)bus)->sc_bus, dma); 724 } 725 726 usbd_xfer_handle 727 motg_allocx(struct usbd_bus *bus) 728 { 729 struct motg_softc *sc = bus->hci_private; 730 usbd_xfer_handle xfer; 731 732 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 733 if (xfer != NULL) { 734 memset(xfer, 0, sizeof(struct motg_xfer)); 735 UXFER(xfer)->sc = sc; 736 #ifdef DIAGNOSTIC 737 // XXX UXFER(xfer)->iinfo.isdone = 1; 738 xfer->busy_free = XFER_BUSY; 739 #endif 740 } 741 return (xfer); 742 } 743 744 void 745 motg_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 746 { 747 struct motg_softc *sc = bus->hci_private; 748 749 #ifdef DIAGNOSTIC 750 if (xfer->busy_free != XFER_BUSY) { 751 printf("motg_freex: xfer=%p not busy, 0x%08x\n", xfer, 752 xfer->busy_free); 753 } 754 xfer->busy_free = XFER_FREE; 755 #endif 756 pool_cache_put(sc->sc_xferpool, xfer); 757 } 758 759 static void 760 motg_get_lock(struct usbd_bus *bus, kmutex_t **lock) 761 { 762 struct motg_softc *sc = bus->hci_private; 763 764 *lock = &sc->sc_lock; 765 } 766 767 /* 768 * Data structures and routines to emulate the root hub. 769 */ 770 usb_device_descriptor_t motg_devd = { 771 USB_DEVICE_DESCRIPTOR_SIZE, 772 UDESC_DEVICE, /* type */ 773 {0x00, 0x01}, /* USB version */ 774 UDCLASS_HUB, /* class */ 775 UDSUBCLASS_HUB, /* subclass */ 776 UDPROTO_FSHUB, /* protocol */ 777 64, /* max packet */ 778 {0},{0},{0x00,0x01}, /* device id */ 779 1,2,0, /* string indicies */ 780 1 /* # of configurations */ 781 }; 782 783 const usb_config_descriptor_t motg_confd = { 784 USB_CONFIG_DESCRIPTOR_SIZE, 785 UDESC_CONFIG, 786 {USB_CONFIG_DESCRIPTOR_SIZE + 787 USB_INTERFACE_DESCRIPTOR_SIZE + 788 USB_ENDPOINT_DESCRIPTOR_SIZE}, 789 1, 790 1, 791 0, 792 UC_ATTR_MBO | UC_SELF_POWERED, 793 0 /* max power */ 794 }; 795 796 const usb_interface_descriptor_t motg_ifcd = { 797 USB_INTERFACE_DESCRIPTOR_SIZE, 798 UDESC_INTERFACE, 799 0, 800 0, 801 1, 802 UICLASS_HUB, 803 UISUBCLASS_HUB, 804 UIPROTO_FSHUB, 805 0 806 }; 807 808 const usb_endpoint_descriptor_t motg_endpd = { 809 USB_ENDPOINT_DESCRIPTOR_SIZE, 810 UDESC_ENDPOINT, 811 UE_DIR_IN | MOTG_INTR_ENDPT, 812 UE_INTERRUPT, 813 {8}, 814 255 815 }; 816 817 const usb_hub_descriptor_t motg_hubd = { 818 USB_HUB_DESCRIPTOR_SIZE, 819 UDESC_HUB, 820 1, 821 { UHD_PWR_NO_SWITCH | UHD_OC_INDIVIDUAL, 0 }, 822 50, /* power on to power good */ 823 0, 824 { 0x00 }, /* port is removable */ 825 { 0 }, 826 }; 827 828 /* 829 * Simulate a hardware hub by handling all the necessary requests. 830 */ 831 usbd_status 832 motg_root_ctrl_transfer(usbd_xfer_handle xfer) 833 { 834 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 835 usbd_status err; 836 837 /* Insert last in queue. */ 838 mutex_enter(&sc->sc_lock); 839 err = usb_insert_transfer(xfer); 840 mutex_exit(&sc->sc_lock); 841 if (err) 842 return (err); 843 844 /* 845 * Pipe isn't running (otherwise err would be USBD_INPROG), 846 * so start it first. 847 */ 848 return (motg_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 849 } 850 851 usbd_status 852 motg_root_ctrl_start(usbd_xfer_handle xfer) 853 { 854 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 855 usb_device_request_t *req; 856 void *buf = NULL; 857 int len, value, index, status, change, l, totlen = 0; 858 usb_port_status_t ps; 859 usbd_status err; 860 uint32_t val; 861 862 if (sc->sc_dying) 863 return (USBD_IOERROR); 864 865 #ifdef DIAGNOSTIC 866 if (!(xfer->rqflags & URQ_REQUEST)) 867 panic("motg_root_ctrl_start: not a request"); 868 #endif 869 req = &xfer->request; 870 871 DPRINTFN(MD_ROOT,("motg_root_ctrl_control type=0x%02x request=%02x\n", 872 req->bmRequestType, req->bRequest)); 873 874 len = UGETW(req->wLength); 875 value = UGETW(req->wValue); 876 index = UGETW(req->wIndex); 877 878 if (len != 0) 879 buf = KERNADDR(&xfer->dmabuf, 0); 880 881 #define C(x,y) ((x) | ((y) << 8)) 882 switch(C(req->bRequest, req->bmRequestType)) { 883 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 884 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 885 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 886 /* 887 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 888 * for the integrated root hub. 889 */ 890 break; 891 case C(UR_GET_CONFIG, UT_READ_DEVICE): 892 if (len > 0) { 893 *(u_int8_t *)buf = sc->sc_root_conf; 894 totlen = 1; 895 } 896 break; 897 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 898 DPRINTFN(MD_ROOT,("motg_root_ctrl_control wValue=0x%04x\n", value)); 899 if (len == 0) 900 break; 901 switch(value >> 8) { 902 case UDESC_DEVICE: 903 if ((value & 0xff) != 0) { 904 err = USBD_IOERROR; 905 goto ret; 906 } 907 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 908 USETW(motg_devd.idVendor, sc->sc_id_vendor); 909 memcpy(buf, &motg_devd, l); 910 break; 911 case UDESC_CONFIG: 912 if ((value & 0xff) != 0) { 913 err = USBD_IOERROR; 914 goto ret; 915 } 916 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 917 memcpy(buf, &motg_confd, l); 918 buf = (char *)buf + l; 919 len -= l; 920 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 921 totlen += l; 922 memcpy(buf, &motg_ifcd, l); 923 buf = (char *)buf + l; 924 len -= l; 925 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 926 totlen += l; 927 memcpy(buf, &motg_endpd, l); 928 break; 929 case UDESC_STRING: 930 #define sd ((usb_string_descriptor_t *)buf) 931 switch (value & 0xff) { 932 case 0: /* Language table */ 933 totlen = usb_makelangtbl(sd, len); 934 break; 935 case 1: /* Vendor */ 936 totlen = usb_makestrdesc(sd, len, 937 sc->sc_vendor); 938 break; 939 case 2: /* Product */ 940 totlen = usb_makestrdesc(sd, len, 941 "MOTG root hub"); 942 break; 943 } 944 #undef sd 945 break; 946 default: 947 err = USBD_IOERROR; 948 goto ret; 949 } 950 break; 951 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 952 if (len > 0) { 953 *(u_int8_t *)buf = 0; 954 totlen = 1; 955 } 956 break; 957 case C(UR_GET_STATUS, UT_READ_DEVICE): 958 if (len > 1) { 959 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 960 totlen = 2; 961 } 962 break; 963 case C(UR_GET_STATUS, UT_READ_INTERFACE): 964 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 965 if (len > 1) { 966 USETW(((usb_status_t *)buf)->wStatus, 0); 967 totlen = 2; 968 } 969 break; 970 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 971 if (value >= USB_MAX_DEVICES) { 972 err = USBD_IOERROR; 973 goto ret; 974 } 975 sc->sc_root_addr = value; 976 break; 977 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 978 if (value != 0 && value != 1) { 979 err = USBD_IOERROR; 980 goto ret; 981 } 982 sc->sc_root_conf = value; 983 break; 984 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 985 break; 986 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 987 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 988 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 989 err = USBD_IOERROR; 990 goto ret; 991 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 992 break; 993 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 994 break; 995 /* Hub requests */ 996 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 997 break; 998 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 999 DPRINTFN(MD_ROOT, 1000 ("motg_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1001 "port=%d feature=%d\n", 1002 index, value)); 1003 if (index != 1) { 1004 err = USBD_IOERROR; 1005 goto ret; 1006 } 1007 switch(value) { 1008 case UHF_PORT_ENABLE: 1009 sc->sc_port_enabled = 0; 1010 break; 1011 case UHF_PORT_SUSPEND: 1012 if (sc->sc_port_suspended != 0) { 1013 val = UREAD1(sc, MUSB2_REG_POWER); 1014 val &= ~MUSB2_MASK_SUSPMODE; 1015 val |= MUSB2_MASK_RESUME; 1016 UWRITE1(sc, MUSB2_REG_POWER, val); 1017 /* wait 20 milliseconds */ 1018 usb_delay_ms(&sc->sc_bus, 20); 1019 val = UREAD1(sc, MUSB2_REG_POWER); 1020 val &= ~MUSB2_MASK_RESUME; 1021 UWRITE1(sc, MUSB2_REG_POWER, val); 1022 sc->sc_port_suspended = 0; 1023 sc->sc_port_suspended_change = 1; 1024 } 1025 break; 1026 case UHF_PORT_RESET: 1027 break; 1028 case UHF_C_PORT_CONNECTION: 1029 break; 1030 case UHF_C_PORT_ENABLE: 1031 break; 1032 case UHF_C_PORT_OVER_CURRENT: 1033 break; 1034 case UHF_C_PORT_RESET: 1035 sc->sc_isreset = 0; 1036 err = USBD_NORMAL_COMPLETION; 1037 goto ret; 1038 case UHF_PORT_POWER: 1039 /* XXX todo */ 1040 break; 1041 case UHF_PORT_CONNECTION: 1042 case UHF_PORT_OVER_CURRENT: 1043 case UHF_PORT_LOW_SPEED: 1044 case UHF_C_PORT_SUSPEND: 1045 default: 1046 err = USBD_IOERROR; 1047 goto ret; 1048 } 1049 break; 1050 case C(UR_GET_BUS_STATE, UT_READ_CLASS_OTHER): 1051 err = USBD_IOERROR; 1052 goto ret; 1053 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1054 if (len == 0) 1055 break; 1056 if ((value & 0xff) != 0) { 1057 err = USBD_IOERROR; 1058 goto ret; 1059 } 1060 l = min(len, USB_HUB_DESCRIPTOR_SIZE); 1061 totlen = l; 1062 memcpy(buf, &motg_hubd, l); 1063 break; 1064 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1065 if (len != 4) { 1066 err = USBD_IOERROR; 1067 goto ret; 1068 } 1069 memset(buf, 0, len); 1070 totlen = len; 1071 break; 1072 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1073 if (index != 1) { 1074 err = USBD_IOERROR; 1075 goto ret; 1076 } 1077 if (len != 4) { 1078 err = USBD_IOERROR; 1079 goto ret; 1080 } 1081 status = change = 0; 1082 if (sc->sc_connected) 1083 status |= UPS_CURRENT_CONNECT_STATUS; 1084 if (sc->sc_connected_changed) { 1085 change |= UPS_C_CONNECT_STATUS; 1086 sc->sc_connected_changed = 0; 1087 } 1088 if (sc->sc_port_enabled) 1089 status |= UPS_PORT_ENABLED; 1090 if (sc->sc_port_enabled_changed) { 1091 change |= UPS_C_PORT_ENABLED; 1092 sc->sc_port_enabled_changed = 0; 1093 } 1094 if (sc->sc_port_suspended) 1095 status |= UPS_SUSPEND; 1096 if (sc->sc_high_speed) 1097 status |= UPS_HIGH_SPEED; 1098 status |= UPS_PORT_POWER; /* XXX */ 1099 if (sc->sc_isreset) 1100 change |= UPS_C_PORT_RESET; 1101 USETW(ps.wPortStatus, status); 1102 USETW(ps.wPortChange, change); 1103 l = min(len, sizeof ps); 1104 memcpy(buf, &ps, l); 1105 totlen = l; 1106 break; 1107 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1108 err = USBD_IOERROR; 1109 goto ret; 1110 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1111 break; 1112 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1113 if (index != 1) { 1114 err = USBD_IOERROR; 1115 goto ret; 1116 } 1117 switch(value) { 1118 case UHF_PORT_ENABLE: 1119 sc->sc_port_enabled = 1; 1120 break; 1121 case UHF_PORT_SUSPEND: 1122 if (sc->sc_port_suspended == 0) { 1123 val = UREAD1(sc, MUSB2_REG_POWER); 1124 val |= MUSB2_MASK_SUSPMODE; 1125 UWRITE1(sc, MUSB2_REG_POWER, val); 1126 /* wait 20 milliseconds */ 1127 usb_delay_ms(&sc->sc_bus, 20); 1128 sc->sc_port_suspended = 1; 1129 sc->sc_port_suspended_change = 1; 1130 } 1131 break; 1132 case UHF_PORT_RESET: 1133 err = motg_portreset(sc); 1134 goto ret; 1135 case UHF_PORT_POWER: 1136 /* XXX todo */ 1137 err = USBD_NORMAL_COMPLETION; 1138 goto ret; 1139 case UHF_C_PORT_CONNECTION: 1140 case UHF_C_PORT_ENABLE: 1141 case UHF_C_PORT_OVER_CURRENT: 1142 case UHF_PORT_CONNECTION: 1143 case UHF_PORT_OVER_CURRENT: 1144 case UHF_PORT_LOW_SPEED: 1145 case UHF_C_PORT_SUSPEND: 1146 case UHF_C_PORT_RESET: 1147 default: 1148 err = USBD_IOERROR; 1149 goto ret; 1150 } 1151 break; 1152 default: 1153 err = USBD_IOERROR; 1154 goto ret; 1155 } 1156 xfer->actlen = totlen; 1157 err = USBD_NORMAL_COMPLETION; 1158 ret: 1159 xfer->status = err; 1160 mutex_enter(&sc->sc_lock); 1161 usb_transfer_complete(xfer); 1162 mutex_exit(&sc->sc_lock); 1163 return (USBD_IN_PROGRESS); 1164 } 1165 1166 /* Abort a root control request. */ 1167 void 1168 motg_root_ctrl_abort(usbd_xfer_handle xfer) 1169 { 1170 /* Nothing to do, all transfers are synchronous. */ 1171 } 1172 1173 /* Close the root pipe. */ 1174 void 1175 motg_root_ctrl_close(usbd_pipe_handle pipe) 1176 { 1177 DPRINTFN(MD_ROOT, ("motg_root_ctrl_close\n")); 1178 } 1179 1180 void 1181 motg_root_ctrl_done(usbd_xfer_handle xfer) 1182 { 1183 } 1184 1185 /* Abort a root interrupt request. */ 1186 void 1187 motg_root_intr_abort(usbd_xfer_handle xfer) 1188 { 1189 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1190 1191 KASSERT(mutex_owned(&sc->sc_lock)); 1192 KASSERT(xfer->pipe->intrxfer == xfer); 1193 1194 sc->sc_intr_xfer = NULL; 1195 1196 #ifdef DIAGNOSTIC 1197 // XXX UXFER(xfer)->iinfo.isdone = 1; 1198 #endif 1199 xfer->status = USBD_CANCELLED; 1200 usb_transfer_complete(xfer); 1201 } 1202 1203 usbd_status 1204 motg_root_intr_transfer(usbd_xfer_handle xfer) 1205 { 1206 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1207 usbd_status err; 1208 1209 /* Insert last in queue. */ 1210 mutex_enter(&sc->sc_lock); 1211 err = usb_insert_transfer(xfer); 1212 mutex_exit(&sc->sc_lock); 1213 if (err) 1214 return (err); 1215 1216 /* 1217 * Pipe isn't running (otherwise err would be USBD_INPROG), 1218 * start first 1219 */ 1220 return (motg_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1221 } 1222 1223 /* Start a transfer on the root interrupt pipe */ 1224 usbd_status 1225 motg_root_intr_start(usbd_xfer_handle xfer) 1226 { 1227 usbd_pipe_handle pipe = xfer->pipe; 1228 struct motg_softc *sc = pipe->device->bus->hci_private; 1229 1230 DPRINTFN(MD_ROOT, ("motg_root_intr_start: xfer=%p len=%d flags=%d\n", 1231 xfer, xfer->length, xfer->flags)); 1232 1233 if (sc->sc_dying) 1234 return (USBD_IOERROR); 1235 1236 sc->sc_intr_xfer = xfer; 1237 return (USBD_IN_PROGRESS); 1238 } 1239 1240 /* Close the root interrupt pipe. */ 1241 void 1242 motg_root_intr_close(usbd_pipe_handle pipe) 1243 { 1244 struct motg_softc *sc = pipe->device->bus->hci_private; 1245 1246 KASSERT(mutex_owned(&sc->sc_lock)); 1247 1248 sc->sc_intr_xfer = NULL; 1249 DPRINTFN(MD_ROOT, ("motg_root_intr_close\n")); 1250 } 1251 1252 void 1253 motg_root_intr_done(usbd_xfer_handle xfer) 1254 { 1255 } 1256 1257 void 1258 motg_noop(usbd_pipe_handle pipe) 1259 { 1260 } 1261 1262 static usbd_status 1263 motg_portreset(struct motg_softc *sc) 1264 { 1265 uint32_t val; 1266 1267 val = UREAD1(sc, MUSB2_REG_POWER); 1268 val |= MUSB2_MASK_RESET; 1269 UWRITE1(sc, MUSB2_REG_POWER, val); 1270 /* Wait for 20 msec */ 1271 usb_delay_ms(&sc->sc_bus, 20); 1272 1273 val = UREAD1(sc, MUSB2_REG_POWER); 1274 val &= ~MUSB2_MASK_RESET; 1275 UWRITE1(sc, MUSB2_REG_POWER, val); 1276 1277 /* determine line speed */ 1278 val = UREAD1(sc, MUSB2_REG_POWER); 1279 if (val & MUSB2_MASK_HSMODE) 1280 sc->sc_high_speed = 1; 1281 else 1282 sc->sc_high_speed = 0; 1283 DPRINTFN(MD_ROOT | MD_CTRL, ("motg_portreset speed %d\n", 1284 sc->sc_high_speed)); 1285 1286 sc->sc_isreset = 1; 1287 sc->sc_port_enabled = 1; 1288 return (USBD_NORMAL_COMPLETION); 1289 } 1290 1291 /* 1292 * This routine is executed when an interrupt on the root hub is detected 1293 */ 1294 static void 1295 motg_hub_change(struct motg_softc *sc) 1296 { 1297 usbd_xfer_handle xfer = sc->sc_intr_xfer; 1298 usbd_pipe_handle pipe; 1299 u_char *p; 1300 1301 DPRINTFN(MD_ROOT, ("motg_hub_change\n")); 1302 1303 if (xfer == NULL) 1304 return; /* the interrupt pipe is not open */ 1305 1306 pipe = xfer->pipe; 1307 if (pipe->device == NULL || pipe->device->bus == NULL) 1308 return; /* device has detached */ 1309 1310 p = KERNADDR(&xfer->dmabuf, 0); 1311 p[0] = 1<<1; 1312 xfer->actlen = 1; 1313 xfer->status = USBD_NORMAL_COMPLETION; 1314 usb_transfer_complete(xfer); 1315 } 1316 1317 static uint8_t 1318 motg_speed(u_int8_t speed) 1319 { 1320 switch(speed) { 1321 case USB_SPEED_LOW: 1322 return MUSB2_MASK_TI_SPEED_LO; 1323 case USB_SPEED_FULL: 1324 return MUSB2_MASK_TI_SPEED_FS; 1325 case USB_SPEED_HIGH: 1326 return MUSB2_MASK_TI_SPEED_HS; 1327 default: 1328 panic("motg: unknown speed %d", speed); 1329 /* NOTREACHED */ 1330 } 1331 } 1332 1333 static uint8_t 1334 motg_type(u_int8_t type) 1335 { 1336 switch(type) { 1337 case UE_CONTROL: 1338 return MUSB2_MASK_TI_PROTO_CTRL; 1339 case UE_ISOCHRONOUS: 1340 return MUSB2_MASK_TI_PROTO_ISOC; 1341 case UE_BULK: 1342 return MUSB2_MASK_TI_PROTO_BULK; 1343 case UE_INTERRUPT: 1344 return MUSB2_MASK_TI_PROTO_INTR; 1345 default: 1346 panic("motg: unknown type %d", type); 1347 /* NOTREACHED */ 1348 } 1349 } 1350 1351 static void 1352 motg_setup_endpoint_tx(usbd_xfer_handle xfer) 1353 { 1354 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1355 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1356 usbd_device_handle dev = otgpipe->pipe.device; 1357 int epnumber = otgpipe->hw_ep->ep_number; 1358 1359 UWRITE1(sc, MUSB2_REG_TXFADDR(epnumber), dev->address); 1360 if (dev->myhsport) { 1361 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 1362 dev->myhsport->parent->address); 1363 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 1364 dev->myhsport->portno); 1365 } else { 1366 UWRITE1(sc, MUSB2_REG_TXHADDR(epnumber), 0); 1367 UWRITE1(sc, MUSB2_REG_TXHUBPORT(epnumber), 0); 1368 } 1369 UWRITE1(sc, MUSB2_REG_TXTI, 1370 motg_speed(dev->speed) | 1371 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1372 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1373 ); 1374 if (epnumber == 0) { 1375 if (sc->sc_high_speed) { 1376 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1377 NAK_TO_CTRL_HIGH); 1378 } else { 1379 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1380 } 1381 } else { 1382 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1383 == UE_BULK) { 1384 if (sc->sc_high_speed) { 1385 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1386 NAK_TO_BULK_HIGH); 1387 } else { 1388 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_BULK); 1389 } 1390 } else { 1391 if (sc->sc_high_speed) { 1392 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO_HIGH); 1393 } else { 1394 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, POLL_TO); 1395 } 1396 } 1397 } 1398 } 1399 1400 static void 1401 motg_setup_endpoint_rx(usbd_xfer_handle xfer) 1402 { 1403 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1404 usbd_device_handle dev = xfer->pipe->device; 1405 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1406 int epnumber = otgpipe->hw_ep->ep_number; 1407 1408 UWRITE1(sc, MUSB2_REG_RXFADDR(epnumber), dev->address); 1409 if (dev->myhsport) { 1410 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 1411 dev->myhsport->parent->address); 1412 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 1413 dev->myhsport->portno); 1414 } else { 1415 UWRITE1(sc, MUSB2_REG_RXHADDR(epnumber), 0); 1416 UWRITE1(sc, MUSB2_REG_RXHUBPORT(epnumber), 0); 1417 } 1418 UWRITE1(sc, MUSB2_REG_RXTI, 1419 motg_speed(dev->speed) | 1420 UE_GET_ADDR(xfer->pipe->endpoint->edesc->bEndpointAddress) | 1421 motg_type(UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes)) 1422 ); 1423 if (epnumber == 0) { 1424 if (sc->sc_high_speed) { 1425 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, 1426 NAK_TO_CTRL_HIGH); 1427 } else { 1428 UWRITE1(sc, MUSB2_REG_TXNAKLIMIT, NAK_TO_CTRL); 1429 } 1430 } else { 1431 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) 1432 == UE_BULK) { 1433 if (sc->sc_high_speed) { 1434 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, 1435 NAK_TO_BULK_HIGH); 1436 } else { 1437 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, NAK_TO_BULK); 1438 } 1439 } else { 1440 if (sc->sc_high_speed) { 1441 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO_HIGH); 1442 } else { 1443 UWRITE1(sc, MUSB2_REG_RXNAKLIMIT, POLL_TO); 1444 } 1445 } 1446 } 1447 } 1448 1449 static usbd_status 1450 motg_device_ctrl_transfer(usbd_xfer_handle xfer) 1451 { 1452 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1453 usbd_status err; 1454 1455 /* Insert last in queue. */ 1456 mutex_enter(&sc->sc_lock); 1457 err = usb_insert_transfer(xfer); 1458 xfer->status = USBD_NOT_STARTED; 1459 mutex_exit(&sc->sc_lock); 1460 if (err) 1461 return (err); 1462 1463 /* 1464 * Pipe isn't running (otherwise err would be USBD_INPROG), 1465 * so start it first. 1466 */ 1467 return (motg_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1468 } 1469 1470 static usbd_status 1471 motg_device_ctrl_start(usbd_xfer_handle xfer) 1472 { 1473 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1474 usbd_status err; 1475 mutex_enter(&sc->sc_lock); 1476 err = motg_device_ctrl_start1(sc); 1477 mutex_exit(&sc->sc_lock); 1478 if (err != USBD_IN_PROGRESS) 1479 return err; 1480 if (sc->sc_bus.use_polling) 1481 motg_waitintr(sc, xfer); 1482 return USBD_IN_PROGRESS; 1483 } 1484 1485 static usbd_status 1486 motg_device_ctrl_start1(struct motg_softc *sc) 1487 { 1488 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1489 usbd_xfer_handle xfer = NULL; 1490 struct motg_pipe *otgpipe; 1491 usbd_status err = 0; 1492 1493 KASSERT(mutex_owned(&sc->sc_lock)); 1494 if (sc->sc_dying) 1495 return (USBD_IOERROR); 1496 1497 if (!sc->sc_connected) 1498 return (USBD_IOERROR); 1499 1500 if (ep->xfer != NULL) { 1501 err = USBD_IN_PROGRESS; 1502 goto end; 1503 } 1504 /* locate the first pipe with work to do */ 1505 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1506 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1507 DPRINTFN(MD_CTRL, 1508 ("motg_device_ctrl_start1 pipe %p xfer %p status %d\n", 1509 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1510 1511 if (xfer != NULL) { 1512 /* move this pipe to the end of the list */ 1513 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1514 motg_pipe, ep_pipe_list); 1515 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1516 otgpipe, ep_pipe_list); 1517 break; 1518 } 1519 } 1520 if (xfer == NULL) { 1521 err = USBD_NOT_STARTED; 1522 goto end; 1523 } 1524 xfer->status = USBD_IN_PROGRESS; 1525 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1526 KASSERT(otgpipe->hw_ep == ep); 1527 #ifdef DIAGNOSTIC 1528 if (!(xfer->rqflags & URQ_REQUEST)) 1529 panic("motg_device_ctrl_transfer: not a request"); 1530 #endif 1531 // KASSERT(xfer->actlen == 0); 1532 xfer->actlen = 0; 1533 1534 ep->xfer = xfer; 1535 ep->datalen = xfer->length; 1536 if (ep->datalen > 0) 1537 ep->data = KERNADDR(&xfer->dmabuf, 0); 1538 else 1539 ep->data = NULL; 1540 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1541 (ep->datalen % 64) == 0) 1542 ep->need_short_xfer = 1; 1543 else 1544 ep->need_short_xfer = 0; 1545 /* now we need send this request */ 1546 DPRINTFN(MD_CTRL, 1547 ("motg_device_ctrl_start1(%p) send data %p len %d short %d speed %d to %d\n", 1548 xfer, ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1549 xfer->pipe->device->address)); 1550 KASSERT(ep->phase == IDLE); 1551 ep->phase = SETUP; 1552 /* select endpoint 0 */ 1553 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1554 /* fifo should be empty at this point */ 1555 KASSERT((UREAD1(sc, MUSB2_REG_TXCSRL) & MUSB2_MASK_CSR0L_TXPKTRDY) == 0); 1556 /* send data */ 1557 // KASSERT(((vaddr_t)(&xfer->request) & 3) == 0); 1558 KASSERT(sizeof(xfer->request) == 8); 1559 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, MUSB2_REG_EPFIFO(0), 1560 (void *)&xfer->request, sizeof(xfer->request)); 1561 1562 motg_setup_endpoint_tx(xfer); 1563 /* start transaction */ 1564 UWRITE1(sc, MUSB2_REG_TXCSRL, 1565 MUSB2_MASK_CSR0L_TXPKTRDY | MUSB2_MASK_CSR0L_SETUPPKT); 1566 1567 end: 1568 if (err) 1569 return (err); 1570 1571 return (USBD_IN_PROGRESS); 1572 } 1573 1574 static void 1575 motg_device_ctrl_read(usbd_xfer_handle xfer) 1576 { 1577 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1578 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1579 /* assume endpoint already selected */ 1580 motg_setup_endpoint_rx(xfer); 1581 /* start transaction */ 1582 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_REQPKT); 1583 otgpipe->hw_ep->phase = DATA_IN; 1584 } 1585 1586 static void 1587 motg_device_ctrl_intr_rx(struct motg_softc *sc) 1588 { 1589 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1590 usbd_xfer_handle xfer = ep->xfer; 1591 uint8_t csr; 1592 int datalen, max_datalen; 1593 char *data; 1594 bool got_short; 1595 usbd_status new_status = USBD_IN_PROGRESS; 1596 1597 KASSERT(mutex_owned(&sc->sc_lock)); 1598 1599 #ifdef DIAGNOSTIC 1600 if (ep->phase != DATA_IN && 1601 ep->phase != STATUS_IN) 1602 panic("motg_device_ctrl_intr_rx: bad phase %d", ep->phase); 1603 #endif 1604 /* select endpoint 0 */ 1605 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1606 1607 /* read out FIFO status */ 1608 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1609 DPRINTFN(MD_CTRL, 1610 ("motg_device_ctrl_intr_rx phase %d csr 0x%x xfer %p status %d\n", 1611 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1612 1613 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1614 csr &= ~MUSB2_MASK_CSR0L_REQPKT; 1615 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1616 1617 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1618 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1619 new_status = USBD_TIMEOUT; /* XXX */ 1620 goto complete; 1621 } 1622 if (csr & (MUSB2_MASK_CSR0L_RXSTALL | MUSB2_MASK_CSR0L_ERROR)) { 1623 if (csr & MUSB2_MASK_CSR0L_RXSTALL) 1624 new_status = USBD_STALLED; 1625 else 1626 new_status = USBD_IOERROR; 1627 /* clear status */ 1628 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1629 goto complete; 1630 } 1631 if ((csr & MUSB2_MASK_CSR0L_RXPKTRDY) == 0) 1632 return; /* no data yet */ 1633 1634 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 1635 goto complete; 1636 1637 if (ep->phase == STATUS_IN) { 1638 new_status = USBD_NORMAL_COMPLETION; 1639 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1640 goto complete; 1641 } 1642 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 1643 DPRINTFN(MD_CTRL, 1644 ("motg_device_ctrl_intr_rx phase %d datalen %d\n", 1645 ep->phase, datalen)); 1646 KASSERT(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize) > 0); 1647 max_datalen = min(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize), 1648 ep->datalen); 1649 if (datalen > max_datalen) { 1650 new_status = USBD_IOERROR; 1651 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1652 goto complete; 1653 } 1654 got_short = (datalen < max_datalen); 1655 if (datalen > 0) { 1656 KASSERT(ep->phase == DATA_IN); 1657 data = ep->data; 1658 ep->data += datalen; 1659 ep->datalen -= datalen; 1660 xfer->actlen += datalen; 1661 if (((vaddr_t)data & 0x3) == 0 && 1662 (datalen >> 2) > 0) { 1663 DPRINTFN(MD_CTRL, 1664 ("motg_device_ctrl_intr_rx r4 data %p len %d\n", 1665 data, datalen)); 1666 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 1667 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1668 data += (datalen & ~0x3); 1669 datalen -= (datalen & ~0x3); 1670 } 1671 DPRINTFN(MD_CTRL, 1672 ("motg_device_ctrl_intr_rx r1 data %p len %d\n", 1673 data, datalen)); 1674 if (datalen) { 1675 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 1676 MUSB2_REG_EPFIFO(0), data, datalen); 1677 } 1678 } 1679 UWRITE1(sc, MUSB2_REG_TXCSRL, csr & ~MUSB2_MASK_CSR0L_RXPKTRDY); 1680 KASSERT(ep->phase == DATA_IN); 1681 if (got_short || (ep->datalen == 0)) { 1682 if (ep->need_short_xfer == 0) { 1683 ep->phase = STATUS_OUT; 1684 UWRITE1(sc, MUSB2_REG_TXCSRH, 1685 UREAD1(sc, MUSB2_REG_TXCSRH) | 1686 MUSB2_MASK_CSR0H_PING_DIS); 1687 motg_setup_endpoint_tx(xfer); 1688 UWRITE1(sc, MUSB2_REG_TXCSRL, 1689 MUSB2_MASK_CSR0L_STATUSPKT | 1690 MUSB2_MASK_CSR0L_TXPKTRDY); 1691 return; 1692 } 1693 ep->need_short_xfer = 0; 1694 } 1695 motg_device_ctrl_read(xfer); 1696 return; 1697 complete: 1698 ep->phase = IDLE; 1699 ep->xfer = NULL; 1700 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1701 KASSERT(new_status != USBD_IN_PROGRESS); 1702 xfer->status = new_status; 1703 usb_transfer_complete(xfer); 1704 } 1705 motg_device_ctrl_start1(sc); 1706 } 1707 1708 static void 1709 motg_device_ctrl_intr_tx(struct motg_softc *sc) 1710 { 1711 struct motg_hw_ep *ep = &sc->sc_in_ep[0]; 1712 usbd_xfer_handle xfer = ep->xfer; 1713 uint8_t csr; 1714 int datalen; 1715 char *data; 1716 usbd_status new_status = USBD_IN_PROGRESS; 1717 1718 KASSERT(mutex_owned(&sc->sc_lock)); 1719 if (ep->phase == DATA_IN || ep->phase == STATUS_IN) { 1720 motg_device_ctrl_intr_rx(sc); 1721 return; 1722 } 1723 1724 #ifdef DIAGNOSTIC 1725 if (ep->phase != SETUP && ep->phase != DATA_OUT && 1726 ep->phase != STATUS_OUT) 1727 panic("motg_device_ctrl_intr_tx: bad phase %d", ep->phase); 1728 #endif 1729 /* select endpoint 0 */ 1730 UWRITE1(sc, MUSB2_REG_EPINDEX, 0); 1731 1732 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1733 DPRINTFN(MD_CTRL, 1734 ("motg_device_ctrl_intr_tx phase %d csr 0x%x xfer %p status %d\n", 1735 ep->phase, csr, xfer, (xfer != NULL) ? xfer->status : 0)); 1736 1737 if (csr & MUSB2_MASK_CSR0L_RXSTALL) { 1738 /* command not accepted */ 1739 new_status = USBD_STALLED; 1740 /* clear status */ 1741 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1742 goto complete; 1743 } 1744 if (csr & MUSB2_MASK_CSR0L_NAKTIMO) { 1745 new_status = USBD_TIMEOUT; /* XXX */ 1746 /* flush fifo */ 1747 while (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1748 UWRITE1(sc, MUSB2_REG_TXCSRH, 1749 UREAD1(sc, MUSB2_REG_TXCSRH) | 1750 MUSB2_MASK_CSR0H_FFLUSH); 1751 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 1752 } 1753 csr &= ~MUSB2_MASK_CSR0L_NAKTIMO; 1754 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 1755 goto complete; 1756 } 1757 if (csr & MUSB2_MASK_CSR0L_ERROR) { 1758 new_status = USBD_IOERROR; 1759 /* clear status */ 1760 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 1761 goto complete; 1762 } 1763 if (csr & MUSB2_MASK_CSR0L_TXFIFONEMPTY) { 1764 /* data still not sent */ 1765 return; 1766 } 1767 if (xfer == NULL) 1768 goto complete; 1769 if (ep->phase == STATUS_OUT) { 1770 /* 1771 * we have sent status and got no error; 1772 * declare transfer complete 1773 */ 1774 DPRINTFN(MD_CTRL, 1775 ("motg_device_ctrl_intr_tx %p status %d complete\n", 1776 xfer, xfer->status)); 1777 new_status = USBD_NORMAL_COMPLETION; 1778 goto complete; 1779 } 1780 if (ep->datalen == 0) { 1781 if (ep->need_short_xfer) { 1782 ep->need_short_xfer = 0; 1783 /* one more data phase */ 1784 if (xfer->request.bmRequestType & UT_READ) { 1785 DPRINTFN(MD_CTRL, 1786 ("motg_device_ctrl_intr_tx %p to DATA_IN\n", xfer)); 1787 motg_device_ctrl_read(xfer); 1788 return; 1789 } /* else fall back to DATA_OUT */ 1790 } else { 1791 DPRINTFN(MD_CTRL, 1792 ("motg_device_ctrl_intr_tx %p to STATUS_IN, csrh 0x%x\n", 1793 xfer, UREAD1(sc, MUSB2_REG_TXCSRH))); 1794 ep->phase = STATUS_IN; 1795 UWRITE1(sc, MUSB2_REG_RXCSRH, 1796 UREAD1(sc, MUSB2_REG_RXCSRH) | 1797 MUSB2_MASK_CSR0H_PING_DIS); 1798 motg_setup_endpoint_rx(xfer); 1799 UWRITE1(sc, MUSB2_REG_TXCSRL, 1800 MUSB2_MASK_CSR0L_STATUSPKT | 1801 MUSB2_MASK_CSR0L_REQPKT); 1802 return; 1803 } 1804 } 1805 if (xfer->request.bmRequestType & UT_READ) { 1806 motg_device_ctrl_read(xfer); 1807 return; 1808 } 1809 /* setup a dataout phase */ 1810 datalen = min(ep->datalen, 1811 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 1812 ep->phase = DATA_OUT; 1813 DPRINTFN(MD_CTRL, 1814 ("motg_device_ctrl_intr_tx %p to DATA_OUT, csrh 0x%x\n", xfer, 1815 UREAD1(sc, MUSB2_REG_TXCSRH))); 1816 if (datalen) { 1817 data = ep->data; 1818 ep->data += datalen; 1819 ep->datalen -= datalen; 1820 xfer->actlen += datalen; 1821 if (((vaddr_t)data & 0x3) == 0 && 1822 (datalen >> 2) > 0) { 1823 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 1824 MUSB2_REG_EPFIFO(0), (void *)data, datalen >> 2); 1825 data += (datalen & ~0x3); 1826 datalen -= (datalen & ~0x3); 1827 } 1828 if (datalen) { 1829 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 1830 MUSB2_REG_EPFIFO(0), data, datalen); 1831 } 1832 } 1833 /* send data */ 1834 motg_setup_endpoint_tx(xfer); 1835 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSR0L_TXPKTRDY); 1836 return; 1837 1838 complete: 1839 ep->phase = IDLE; 1840 ep->xfer = NULL; 1841 if (xfer && xfer->status == USBD_IN_PROGRESS) { 1842 KASSERT(new_status != USBD_IN_PROGRESS); 1843 xfer->status = new_status; 1844 usb_transfer_complete(xfer); 1845 } 1846 motg_device_ctrl_start1(sc); 1847 } 1848 1849 /* Abort a device control request. */ 1850 void 1851 motg_device_ctrl_abort(usbd_xfer_handle xfer) 1852 { 1853 DPRINTFN(MD_CTRL, ("motg_device_ctrl_abort:\n")); 1854 motg_device_xfer_abort(xfer); 1855 } 1856 1857 /* Close a device control pipe */ 1858 void 1859 motg_device_ctrl_close(usbd_pipe_handle pipe) 1860 { 1861 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 1862 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 1863 struct motg_pipe *otgpipeiter; 1864 1865 DPRINTFN(MD_CTRL, ("motg_device_ctrl_close:\n")); 1866 KASSERT(mutex_owned(&sc->sc_lock)); 1867 KASSERT(otgpipe->hw_ep->xfer == NULL || 1868 otgpipe->hw_ep->xfer->pipe != pipe); 1869 1870 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 1871 if (otgpipeiter == otgpipe) { 1872 /* remove from list */ 1873 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 1874 motg_pipe, ep_pipe_list); 1875 otgpipe->hw_ep->refcount--; 1876 /* we're done */ 1877 return; 1878 } 1879 } 1880 panic("motg_device_ctrl_close: not found"); 1881 } 1882 1883 void 1884 motg_device_ctrl_done(usbd_xfer_handle xfer) 1885 { 1886 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 1887 DPRINTFN(MD_CTRL, ("motg_device_ctrl_done:\n")); 1888 KASSERT(otgpipe->hw_ep->xfer != xfer); 1889 } 1890 1891 static usbd_status 1892 motg_device_data_transfer(usbd_xfer_handle xfer) 1893 { 1894 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1895 usbd_status err; 1896 1897 /* Insert last in queue. */ 1898 mutex_enter(&sc->sc_lock); 1899 DPRINTF(("motg_device_data_transfer(%p) status %d\n", 1900 xfer, xfer->status)); 1901 err = usb_insert_transfer(xfer); 1902 xfer->status = USBD_NOT_STARTED; 1903 mutex_exit(&sc->sc_lock); 1904 if (err) 1905 return (err); 1906 1907 /* 1908 * Pipe isn't running (otherwise err would be USBD_INPROG), 1909 * so start it first. 1910 */ 1911 return (motg_device_data_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1912 } 1913 1914 static usbd_status 1915 motg_device_data_start(usbd_xfer_handle xfer) 1916 { 1917 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 1918 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 1919 usbd_status err; 1920 mutex_enter(&sc->sc_lock); 1921 DPRINTF(("motg_device_data_start(%p) status %d\n", 1922 xfer, xfer->status)); 1923 err = motg_device_data_start1(sc, otgpipe->hw_ep); 1924 mutex_exit(&sc->sc_lock); 1925 if (err != USBD_IN_PROGRESS) 1926 return err; 1927 if (sc->sc_bus.use_polling) 1928 motg_waitintr(sc, xfer); 1929 return USBD_IN_PROGRESS; 1930 } 1931 1932 static usbd_status 1933 motg_device_data_start1(struct motg_softc *sc, struct motg_hw_ep *ep) 1934 { 1935 usbd_xfer_handle xfer = NULL; 1936 struct motg_pipe *otgpipe; 1937 usbd_status err = 0; 1938 uint32_t val __diagused; 1939 1940 KASSERT(mutex_owned(&sc->sc_lock)); 1941 if (sc->sc_dying) 1942 return (USBD_IOERROR); 1943 1944 if (!sc->sc_connected) 1945 return (USBD_IOERROR); 1946 1947 if (ep->xfer != NULL) { 1948 err = USBD_IN_PROGRESS; 1949 goto end; 1950 } 1951 /* locate the first pipe with work to do */ 1952 SIMPLEQ_FOREACH(otgpipe, &ep->ep_pipes, ep_pipe_list) { 1953 xfer = SIMPLEQ_FIRST(&otgpipe->pipe.queue); 1954 DPRINTFN(MD_BULK, 1955 ("motg_device_data_start1 pipe %p xfer %p status %d\n", 1956 otgpipe, xfer, (xfer != NULL) ? xfer->status : 0)); 1957 if (xfer != NULL) { 1958 /* move this pipe to the end of the list */ 1959 SIMPLEQ_REMOVE(&ep->ep_pipes, otgpipe, 1960 motg_pipe, ep_pipe_list); 1961 SIMPLEQ_INSERT_TAIL(&ep->ep_pipes, 1962 otgpipe, ep_pipe_list); 1963 break; 1964 } 1965 } 1966 if (xfer == NULL) { 1967 err = USBD_NOT_STARTED; 1968 goto end; 1969 } 1970 xfer->status = USBD_IN_PROGRESS; 1971 KASSERT(otgpipe == (struct motg_pipe *)xfer->pipe); 1972 KASSERT(otgpipe->hw_ep == ep); 1973 #ifdef DIAGNOSTIC 1974 if (xfer->rqflags & URQ_REQUEST) 1975 panic("motg_device_data_transfer: a request"); 1976 #endif 1977 // KASSERT(xfer->actlen == 0); 1978 xfer->actlen = 0; 1979 1980 ep->xfer = xfer; 1981 ep->datalen = xfer->length; 1982 KASSERT(ep->datalen > 0); 1983 ep->data = KERNADDR(&xfer->dmabuf, 0); 1984 if ((xfer->flags & USBD_FORCE_SHORT_XFER) && 1985 (ep->datalen % 64) == 0) 1986 ep->need_short_xfer = 1; 1987 else 1988 ep->need_short_xfer = 0; 1989 /* now we need send this request */ 1990 DPRINTFN(MD_BULK, 1991 ("motg_device_data_start1(%p) %s data %p len %d short %d speed %d to %d\n", 1992 xfer, 1993 UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN ? "read" : "write", 1994 ep->data, ep->datalen, ep->need_short_xfer, xfer->pipe->device->speed, 1995 xfer->pipe->device->address)); 1996 KASSERT(ep->phase == IDLE); 1997 /* select endpoint */ 1998 UWRITE1(sc, MUSB2_REG_EPINDEX, ep->ep_number); 1999 if (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) 2000 == UE_DIR_IN) { 2001 val = UREAD1(sc, MUSB2_REG_RXCSRL); 2002 KASSERT((val & MUSB2_MASK_CSRL_RXPKTRDY) == 0); 2003 motg_device_data_read(xfer); 2004 } else { 2005 ep->phase = DATA_OUT; 2006 val = UREAD1(sc, MUSB2_REG_TXCSRL); 2007 KASSERT((val & MUSB2_MASK_CSRL_TXPKTRDY) == 0); 2008 motg_device_data_write(xfer); 2009 } 2010 end: 2011 if (err) 2012 return (err); 2013 2014 return (USBD_IN_PROGRESS); 2015 } 2016 2017 static void 2018 motg_device_data_read(usbd_xfer_handle xfer) 2019 { 2020 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2021 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2022 uint32_t val; 2023 2024 KASSERT(mutex_owned(&sc->sc_lock)); 2025 /* assume endpoint already selected */ 2026 motg_setup_endpoint_rx(xfer); 2027 /* Max packet size */ 2028 UWRITE2(sc, MUSB2_REG_RXMAXP, 2029 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2030 /* Data Toggle */ 2031 val = UREAD1(sc, MUSB2_REG_RXCSRH); 2032 val |= MUSB2_MASK_CSRH_RXDT_WREN; 2033 if (otgpipe->nexttoggle) 2034 val |= MUSB2_MASK_CSRH_RXDT_VAL; 2035 else 2036 val &= ~MUSB2_MASK_CSRH_RXDT_VAL; 2037 UWRITE1(sc, MUSB2_REG_RXCSRH, val); 2038 2039 DPRINTFN(MD_BULK, 2040 ("motg_device_data_read %p to DATA_IN on ep %d, csrh 0x%x\n", 2041 xfer, otgpipe->hw_ep->ep_number, UREAD1(sc, MUSB2_REG_RXCSRH))); 2042 /* start transaction */ 2043 UWRITE1(sc, MUSB2_REG_RXCSRL, MUSB2_MASK_CSRL_RXREQPKT); 2044 otgpipe->hw_ep->phase = DATA_IN; 2045 } 2046 2047 static void 2048 motg_device_data_write(usbd_xfer_handle xfer) 2049 { 2050 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2051 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2052 struct motg_hw_ep *ep = otgpipe->hw_ep; 2053 int datalen; 2054 char *data; 2055 uint32_t val; 2056 2057 KASSERT(xfer!=NULL); 2058 KASSERT(mutex_owned(&sc->sc_lock)); 2059 2060 datalen = min(ep->datalen, 2061 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2062 ep->phase = DATA_OUT; 2063 DPRINTFN(MD_BULK, 2064 ("motg_device_data_write %p to DATA_OUT on ep %d, len %d csrh 0x%x\n", 2065 xfer, ep->ep_number, datalen, UREAD1(sc, MUSB2_REG_TXCSRH))); 2066 2067 /* assume endpoint already selected */ 2068 /* write data to fifo */ 2069 data = ep->data; 2070 ep->data += datalen; 2071 ep->datalen -= datalen; 2072 xfer->actlen += datalen; 2073 if (((vaddr_t)data & 0x3) == 0 && 2074 (datalen >> 2) > 0) { 2075 bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh, 2076 MUSB2_REG_EPFIFO(ep->ep_number), 2077 (void *)data, datalen >> 2); 2078 data += (datalen & ~0x3); 2079 datalen -= (datalen & ~0x3); 2080 } 2081 if (datalen) { 2082 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, 2083 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2084 } 2085 2086 motg_setup_endpoint_tx(xfer); 2087 /* Max packet size */ 2088 UWRITE2(sc, MUSB2_REG_TXMAXP, 2089 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)); 2090 /* Data Toggle */ 2091 val = UREAD1(sc, MUSB2_REG_TXCSRH); 2092 val |= MUSB2_MASK_CSRH_TXDT_WREN; 2093 if (otgpipe->nexttoggle) 2094 val |= MUSB2_MASK_CSRH_TXDT_VAL; 2095 else 2096 val &= ~MUSB2_MASK_CSRH_TXDT_VAL; 2097 UWRITE1(sc, MUSB2_REG_TXCSRH, val); 2098 2099 /* start transaction */ 2100 UWRITE1(sc, MUSB2_REG_TXCSRL, MUSB2_MASK_CSRL_TXPKTRDY); 2101 } 2102 2103 static void 2104 motg_device_intr_rx(struct motg_softc *sc, int epnumber) 2105 { 2106 struct motg_hw_ep *ep = &sc->sc_in_ep[epnumber]; 2107 usbd_xfer_handle xfer = ep->xfer; 2108 uint8_t csr; 2109 int datalen, max_datalen; 2110 char *data; 2111 bool got_short; 2112 usbd_status new_status = USBD_IN_PROGRESS; 2113 2114 KASSERT(mutex_owned(&sc->sc_lock)); 2115 KASSERT(ep->ep_number == epnumber); 2116 2117 DPRINTFN(MD_BULK, 2118 ("motg_device_intr_rx on ep %d\n", epnumber)); 2119 /* select endpoint */ 2120 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2121 2122 /* read out FIFO status */ 2123 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2124 DPRINTFN(MD_BULK, 2125 ("motg_device_intr_rx phase %d csr 0x%x\n", 2126 ep->phase, csr)); 2127 2128 if ((csr & (MUSB2_MASK_CSRL_RXNAKTO | MUSB2_MASK_CSRL_RXSTALL | 2129 MUSB2_MASK_CSRL_RXERROR | MUSB2_MASK_CSRL_RXPKTRDY)) == 0) 2130 return; 2131 2132 #ifdef DIAGNOSTIC 2133 if (ep->phase != DATA_IN) 2134 panic("motg_device_intr_rx: bad phase %d", ep->phase); 2135 #endif 2136 if (csr & MUSB2_MASK_CSRL_RXNAKTO) { 2137 csr &= ~MUSB2_MASK_CSRL_RXREQPKT; 2138 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2139 2140 csr &= ~MUSB2_MASK_CSRL_RXNAKTO; 2141 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2142 new_status = USBD_TIMEOUT; /* XXX */ 2143 goto complete; 2144 } 2145 if (csr & (MUSB2_MASK_CSRL_RXSTALL | MUSB2_MASK_CSRL_RXERROR)) { 2146 if (csr & MUSB2_MASK_CSRL_RXSTALL) 2147 new_status = USBD_STALLED; 2148 else 2149 new_status = USBD_IOERROR; 2150 /* clear status */ 2151 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2152 goto complete; 2153 } 2154 KASSERT(csr & MUSB2_MASK_CSRL_RXPKTRDY); 2155 2156 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) { 2157 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2158 goto complete; 2159 } 2160 2161 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2162 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2163 2164 datalen = UREAD2(sc, MUSB2_REG_RXCOUNT); 2165 DPRINTFN(MD_BULK, 2166 ("motg_device_intr_rx phase %d datalen %d\n", 2167 ep->phase, datalen)); 2168 KASSERT(UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)) > 0); 2169 max_datalen = min( 2170 UE_GET_SIZE(UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize)), 2171 ep->datalen); 2172 if (datalen > max_datalen) { 2173 new_status = USBD_IOERROR; 2174 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2175 goto complete; 2176 } 2177 got_short = (datalen < max_datalen); 2178 if (datalen > 0) { 2179 KASSERT(ep->phase == DATA_IN); 2180 data = ep->data; 2181 ep->data += datalen; 2182 ep->datalen -= datalen; 2183 xfer->actlen += datalen; 2184 if (((vaddr_t)data & 0x3) == 0 && 2185 (datalen >> 2) > 0) { 2186 DPRINTFN(MD_BULK, 2187 ("motg_device_intr_rx r4 data %p len %d\n", 2188 data, datalen)); 2189 bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh, 2190 MUSB2_REG_EPFIFO(ep->ep_number), 2191 (void *)data, datalen >> 2); 2192 data += (datalen & ~0x3); 2193 datalen -= (datalen & ~0x3); 2194 } 2195 DPRINTFN(MD_BULK, 2196 ("motg_device_intr_rx r1 data %p len %d\n", 2197 data, datalen)); 2198 if (datalen) { 2199 bus_space_read_multi_1(sc->sc_iot, sc->sc_ioh, 2200 MUSB2_REG_EPFIFO(ep->ep_number), data, datalen); 2201 } 2202 } 2203 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2204 KASSERT(ep->phase == DATA_IN); 2205 if (got_short || (ep->datalen == 0)) { 2206 if (ep->need_short_xfer == 0) { 2207 new_status = USBD_NORMAL_COMPLETION; 2208 goto complete; 2209 } 2210 ep->need_short_xfer = 0; 2211 } 2212 motg_device_data_read(xfer); 2213 return; 2214 complete: 2215 DPRINTFN(MD_BULK, 2216 ("motg_device_intr_rx xfer %p complete, status %d\n", xfer, 2217 (xfer != NULL) ? xfer->status : 0)); 2218 ep->phase = IDLE; 2219 ep->xfer = NULL; 2220 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2221 KASSERT(new_status != USBD_IN_PROGRESS); 2222 xfer->status = new_status; 2223 usb_transfer_complete(xfer); 2224 } 2225 motg_device_data_start1(sc, ep); 2226 } 2227 2228 static void 2229 motg_device_intr_tx(struct motg_softc *sc, int epnumber) 2230 { 2231 struct motg_hw_ep *ep = &sc->sc_out_ep[epnumber]; 2232 usbd_xfer_handle xfer = ep->xfer; 2233 uint8_t csr; 2234 struct motg_pipe *otgpipe; 2235 usbd_status new_status = USBD_IN_PROGRESS; 2236 2237 KASSERT(mutex_owned(&sc->sc_lock)); 2238 KASSERT(ep->ep_number == epnumber); 2239 2240 DPRINTFN(MD_BULK, 2241 ("motg_device_intr_tx on ep %d\n", epnumber)); 2242 /* select endpoint */ 2243 UWRITE1(sc, MUSB2_REG_EPINDEX, epnumber); 2244 2245 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2246 DPRINTFN(MD_BULK, 2247 ("motg_device_intr_tx phase %d csr 0x%x\n", 2248 ep->phase, csr)); 2249 2250 if (csr & (MUSB2_MASK_CSRL_TXSTALLED|MUSB2_MASK_CSRL_TXERROR)) { 2251 /* command not accepted */ 2252 if (csr & MUSB2_MASK_CSRL_TXSTALLED) 2253 new_status = USBD_STALLED; 2254 else 2255 new_status = USBD_IOERROR; 2256 /* clear status */ 2257 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2258 goto complete; 2259 } 2260 if (csr & MUSB2_MASK_CSRL_TXNAKTO) { 2261 new_status = USBD_TIMEOUT; /* XXX */ 2262 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2263 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2264 /* flush fifo */ 2265 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2266 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2267 csr &= ~MUSB2_MASK_CSRL_TXNAKTO; 2268 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2269 delay(1000); 2270 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2271 DPRINTFN(MD_BULK, ("TX fifo flush ep %d CSR 0x%x\n", 2272 epnumber, csr)); 2273 } 2274 goto complete; 2275 } 2276 if (csr & (MUSB2_MASK_CSRL_TXFIFONEMPTY|MUSB2_MASK_CSRL_TXPKTRDY)) { 2277 /* data still not sent */ 2278 return; 2279 } 2280 if (xfer == NULL || xfer->status != USBD_IN_PROGRESS) 2281 goto complete; 2282 #ifdef DIAGNOSTIC 2283 if (ep->phase != DATA_OUT) 2284 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2285 #endif 2286 2287 otgpipe = (struct motg_pipe *)xfer->pipe; 2288 otgpipe->nexttoggle = otgpipe->nexttoggle ^ 1; 2289 2290 if (ep->datalen == 0) { 2291 if (ep->need_short_xfer) { 2292 ep->need_short_xfer = 0; 2293 /* one more data phase */ 2294 } else { 2295 new_status = USBD_NORMAL_COMPLETION; 2296 goto complete; 2297 } 2298 } 2299 motg_device_data_write(xfer); 2300 return; 2301 2302 complete: 2303 DPRINTFN(MD_BULK, 2304 ("motg_device_intr_tx xfer %p complete, status %d\n", xfer, 2305 (xfer != NULL) ? xfer->status : 0)); 2306 #ifdef DIAGNOSTIC 2307 if (xfer && xfer->status == USBD_IN_PROGRESS && ep->phase != DATA_OUT) 2308 panic("motg_device_intr_tx: bad phase %d", ep->phase); 2309 #endif 2310 ep->phase = IDLE; 2311 ep->xfer = NULL; 2312 if (xfer && xfer->status == USBD_IN_PROGRESS) { 2313 KASSERT(new_status != USBD_IN_PROGRESS); 2314 xfer->status = new_status; 2315 usb_transfer_complete(xfer); 2316 } 2317 motg_device_data_start1(sc, ep); 2318 } 2319 2320 /* Abort a device control request. */ 2321 void 2322 motg_device_data_abort(usbd_xfer_handle xfer) 2323 { 2324 #ifdef DIAGNOSTIC 2325 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2326 #endif 2327 KASSERT(mutex_owned(&sc->sc_lock)); 2328 2329 DPRINTFN(MD_BULK, ("motg_device_data_abort:\n")); 2330 motg_device_xfer_abort(xfer); 2331 } 2332 2333 /* Close a device control pipe */ 2334 void 2335 motg_device_data_close(usbd_pipe_handle pipe) 2336 { 2337 struct motg_softc *sc __diagused = pipe->device->bus->hci_private; 2338 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2339 struct motg_pipe *otgpipeiter; 2340 2341 DPRINTFN(MD_CTRL, ("motg_device_data_close:\n")); 2342 KASSERT(mutex_owned(&sc->sc_lock)); 2343 KASSERT(otgpipe->hw_ep->xfer == NULL || 2344 otgpipe->hw_ep->xfer->pipe != pipe); 2345 2346 pipe->endpoint->datatoggle = otgpipe->nexttoggle; 2347 SIMPLEQ_FOREACH(otgpipeiter, &otgpipe->hw_ep->ep_pipes, ep_pipe_list) { 2348 if (otgpipeiter == otgpipe) { 2349 /* remove from list */ 2350 SIMPLEQ_REMOVE(&otgpipe->hw_ep->ep_pipes, otgpipe, 2351 motg_pipe, ep_pipe_list); 2352 otgpipe->hw_ep->refcount--; 2353 /* we're done */ 2354 return; 2355 } 2356 } 2357 panic("motg_device_data_close: not found"); 2358 } 2359 2360 void 2361 motg_device_data_done(usbd_xfer_handle xfer) 2362 { 2363 struct motg_pipe *otgpipe __diagused = (struct motg_pipe *)xfer->pipe; 2364 DPRINTFN(MD_CTRL, ("motg_device_data_done:\n")); 2365 KASSERT(otgpipe->hw_ep->xfer != xfer); 2366 } 2367 2368 /* 2369 * Wait here until controller claims to have an interrupt. 2370 * Then call motg_intr and return. Use timeout to avoid waiting 2371 * too long. 2372 * Only used during boot when interrupts are not enabled yet. 2373 */ 2374 void 2375 motg_waitintr(struct motg_softc *sc, usbd_xfer_handle xfer) 2376 { 2377 int timo = xfer->timeout; 2378 2379 mutex_enter(&sc->sc_lock); 2380 2381 DPRINTF(("motg_waitintr: timeout = %dms\n", timo)); 2382 2383 for (; timo >= 0; timo--) { 2384 mutex_exit(&sc->sc_lock); 2385 usb_delay_ms(&sc->sc_bus, 1); 2386 mutex_spin_enter(&sc->sc_intr_lock); 2387 motg_poll(&sc->sc_bus); 2388 mutex_spin_exit(&sc->sc_intr_lock); 2389 mutex_enter(&sc->sc_lock); 2390 if (xfer->status != USBD_IN_PROGRESS) 2391 goto done; 2392 } 2393 2394 /* Timeout */ 2395 DPRINTF(("motg_waitintr: timeout\n")); 2396 panic("motg_waitintr: timeout"); 2397 /* XXX handle timeout ! */ 2398 2399 done: 2400 mutex_exit(&sc->sc_lock); 2401 } 2402 2403 void 2404 motg_device_clear_toggle(usbd_pipe_handle pipe) 2405 { 2406 struct motg_pipe *otgpipe = (struct motg_pipe *)pipe; 2407 otgpipe->nexttoggle = 0; 2408 } 2409 2410 /* Abort a device control request. */ 2411 static void 2412 motg_device_xfer_abort(usbd_xfer_handle xfer) 2413 { 2414 int wake; 2415 uint8_t csr; 2416 struct motg_softc *sc = xfer->pipe->device->bus->hci_private; 2417 struct motg_pipe *otgpipe = (struct motg_pipe *)xfer->pipe; 2418 KASSERT(mutex_owned(&sc->sc_lock)); 2419 2420 DPRINTF(("motg_device_xfer_abort:\n")); 2421 if (xfer->hcflags & UXFER_ABORTING) { 2422 DPRINTF(("motg_device_xfer_abort: already aborting\n")); 2423 xfer->hcflags |= UXFER_ABORTWAIT; 2424 while (xfer->hcflags & UXFER_ABORTING) 2425 cv_wait(&xfer->hccv, &sc->sc_lock); 2426 return; 2427 } 2428 xfer->hcflags |= UXFER_ABORTING; 2429 if (otgpipe->hw_ep->xfer == xfer) { 2430 KASSERT(xfer->status == USBD_IN_PROGRESS); 2431 otgpipe->hw_ep->xfer = NULL; 2432 if (otgpipe->hw_ep->ep_number > 0) { 2433 /* select endpoint */ 2434 UWRITE1(sc, MUSB2_REG_EPINDEX, 2435 otgpipe->hw_ep->ep_number); 2436 if (otgpipe->hw_ep->phase == DATA_OUT) { 2437 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2438 while (csr & MUSB2_MASK_CSRL_TXFIFONEMPTY) { 2439 csr |= MUSB2_MASK_CSRL_TXFFLUSH; 2440 UWRITE1(sc, MUSB2_REG_TXCSRL, csr); 2441 csr = UREAD1(sc, MUSB2_REG_TXCSRL); 2442 } 2443 UWRITE1(sc, MUSB2_REG_TXCSRL, 0); 2444 } else if (otgpipe->hw_ep->phase == DATA_IN) { 2445 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2446 while (csr & MUSB2_MASK_CSRL_RXPKTRDY) { 2447 csr |= MUSB2_MASK_CSRL_RXFFLUSH; 2448 UWRITE1(sc, MUSB2_REG_RXCSRL, csr); 2449 csr = UREAD1(sc, MUSB2_REG_RXCSRL); 2450 } 2451 UWRITE1(sc, MUSB2_REG_RXCSRL, 0); 2452 } 2453 otgpipe->hw_ep->phase = IDLE; 2454 } 2455 } 2456 xfer->status = USBD_CANCELLED; /* make software ignore it */ 2457 wake = xfer->hcflags & UXFER_ABORTWAIT; 2458 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2459 usb_transfer_complete(xfer); 2460 if (wake) 2461 cv_broadcast(&xfer->hccv); 2462 } 2463
Indexes created Wed Sep 24 02:09:48 GMT 2025