ohci.c revision 1.218.6.7 1 1.218.6.7 mrg /* $NetBSD: ohci.c,v 1.218.6.7 2011/12/08 22:38:47 mrg Exp $ */
2 1.55 augustss /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */
3 1.1 augustss
4 1.1 augustss /*
5 1.218.6.2 jmcneill * Copyright (c) 1998, 2004, 2005, 2011 The NetBSD Foundation, Inc.
6 1.1 augustss * All rights reserved.
7 1.1 augustss *
8 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
9 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
10 1.218.6.2 jmcneill * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
11 1.218.6.2 jmcneill * and Matthew R. Green.
12 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
13 1.157 mycroft * by Charles M. Hannum.
14 1.1 augustss *
15 1.1 augustss * Redistribution and use in source and binary forms, with or without
16 1.1 augustss * modification, are permitted provided that the following conditions
17 1.1 augustss * are met:
18 1.1 augustss * 1. Redistributions of source code must retain the above copyright
19 1.1 augustss * notice, this list of conditions and the following disclaimer.
20 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
21 1.1 augustss * notice, this list of conditions and the following disclaimer in the
22 1.1 augustss * documentation and/or other materials provided with the distribution.
23 1.1 augustss *
24 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
35 1.1 augustss */
36 1.1 augustss
37 1.1 augustss /*
38 1.1 augustss * USB Open Host Controller driver.
39 1.1 augustss *
40 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
41 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
42 1.1 augustss */
43 1.108 lukem
44 1.108 lukem #include <sys/cdefs.h>
45 1.218.6.7 mrg __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.218.6.7 2011/12/08 22:38:47 mrg Exp $");
46 1.216 matt
47 1.216 matt #include "opt_usb.h"
48 1.1 augustss
49 1.1 augustss #include <sys/param.h>
50 1.1 augustss #include <sys/systm.h>
51 1.218.6.2 jmcneill #include <sys/kmem.h>
52 1.55 augustss #include <sys/kernel.h>
53 1.1 augustss #include <sys/device.h>
54 1.55 augustss #include <sys/select.h>
55 1.1 augustss #include <sys/proc.h>
56 1.1 augustss #include <sys/queue.h>
57 1.1 augustss
58 1.184 ad #include <sys/bus.h>
59 1.16 augustss #include <machine/endian.h>
60 1.4 augustss
61 1.1 augustss #include <dev/usb/usb.h>
62 1.1 augustss #include <dev/usb/usbdi.h>
63 1.1 augustss #include <dev/usb/usbdivar.h>
64 1.38 augustss #include <dev/usb/usb_mem.h>
65 1.1 augustss #include <dev/usb/usb_quirks.h>
66 1.1 augustss
67 1.1 augustss #include <dev/usb/ohcireg.h>
68 1.1 augustss #include <dev/usb/ohcivar.h>
69 1.186 drochner #include <dev/usb/usbroothub_subr.h>
70 1.1 augustss
71 1.1 augustss
72 1.36 augustss
73 1.52 augustss #ifdef OHCI_DEBUG
74 1.209 dyoung #define DPRINTF(x) if (ohcidebug) printf x
75 1.209 dyoung #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x
76 1.52 augustss int ohcidebug = 0;
77 1.52 augustss #else
78 1.52 augustss #define DPRINTF(x)
79 1.52 augustss #define DPRINTFN(n,x)
80 1.52 augustss #endif
81 1.52 augustss
82 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
83 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
84 1.16 augustss #else
85 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
86 1.16 augustss #endif
87 1.16 augustss
88 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
89 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
90 1.169 tron #define HTOO16(val) O16TOH(val)
91 1.169 tron #define HTOO32(val) O32TOH(val)
92 1.168 augustss
93 1.1 augustss struct ohci_pipe;
94 1.1 augustss
95 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
96 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
97 1.1 augustss
98 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
99 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
100 1.1 augustss
101 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
102 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
103 1.60 augustss
104 1.53 augustss #if 0
105 1.91 augustss Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *,
106 1.91 augustss ohci_soft_td_t *);
107 1.53 augustss #endif
108 1.91 augustss Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *,
109 1.77 augustss ohci_softc_t *, int, int, usbd_xfer_handle,
110 1.91 augustss ohci_soft_td_t *, ohci_soft_td_t **);
111 1.53 augustss
112 1.91 augustss Static usbd_status ohci_open(usbd_pipe_handle);
113 1.91 augustss Static void ohci_poll(struct usbd_bus *);
114 1.99 augustss Static void ohci_softintr(void *);
115 1.91 augustss Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle);
116 1.91 augustss Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle);
117 1.218.6.2 jmcneill Static void ohci_rhsc_softint(void *arg);
118 1.91 augustss
119 1.91 augustss Static usbd_status ohci_device_request(usbd_xfer_handle xfer);
120 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
121 1.168 augustss ohci_soft_ed_t *);
122 1.168 augustss
123 1.218.6.6 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
124 1.218.6.6 mrg ohci_soft_ed_t *);
125 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
126 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
127 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
128 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
129 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
130 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
131 1.91 augustss
132 1.91 augustss Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe);
133 1.91 augustss Static void ohci_device_isoc_enter(usbd_xfer_handle);
134 1.91 augustss
135 1.91 augustss Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
136 1.91 augustss Static void ohci_freem(struct usbd_bus *, usb_dma_t *);
137 1.91 augustss
138 1.91 augustss Static usbd_xfer_handle ohci_allocx(struct usbd_bus *);
139 1.91 augustss Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle);
140 1.218.6.2 jmcneill Static void ohci_get_locks(struct usbd_bus *, kmutex_t **,
141 1.218.6.2 jmcneill kmutex_t **);
142 1.91 augustss
143 1.91 augustss Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle);
144 1.91 augustss Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle);
145 1.91 augustss Static void ohci_root_ctrl_abort(usbd_xfer_handle);
146 1.91 augustss Static void ohci_root_ctrl_close(usbd_pipe_handle);
147 1.91 augustss Static void ohci_root_ctrl_done(usbd_xfer_handle);
148 1.91 augustss
149 1.91 augustss Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle);
150 1.91 augustss Static usbd_status ohci_root_intr_start(usbd_xfer_handle);
151 1.91 augustss Static void ohci_root_intr_abort(usbd_xfer_handle);
152 1.91 augustss Static void ohci_root_intr_close(usbd_pipe_handle);
153 1.91 augustss Static void ohci_root_intr_done(usbd_xfer_handle);
154 1.91 augustss
155 1.91 augustss Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle);
156 1.91 augustss Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle);
157 1.91 augustss Static void ohci_device_ctrl_abort(usbd_xfer_handle);
158 1.91 augustss Static void ohci_device_ctrl_close(usbd_pipe_handle);
159 1.91 augustss Static void ohci_device_ctrl_done(usbd_xfer_handle);
160 1.91 augustss
161 1.91 augustss Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle);
162 1.91 augustss Static usbd_status ohci_device_bulk_start(usbd_xfer_handle);
163 1.91 augustss Static void ohci_device_bulk_abort(usbd_xfer_handle);
164 1.91 augustss Static void ohci_device_bulk_close(usbd_pipe_handle);
165 1.91 augustss Static void ohci_device_bulk_done(usbd_xfer_handle);
166 1.91 augustss
167 1.91 augustss Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle);
168 1.91 augustss Static usbd_status ohci_device_intr_start(usbd_xfer_handle);
169 1.91 augustss Static void ohci_device_intr_abort(usbd_xfer_handle);
170 1.91 augustss Static void ohci_device_intr_close(usbd_pipe_handle);
171 1.91 augustss Static void ohci_device_intr_done(usbd_xfer_handle);
172 1.91 augustss
173 1.91 augustss Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle);
174 1.91 augustss Static usbd_status ohci_device_isoc_start(usbd_xfer_handle);
175 1.91 augustss Static void ohci_device_isoc_abort(usbd_xfer_handle);
176 1.91 augustss Static void ohci_device_isoc_close(usbd_pipe_handle);
177 1.91 augustss Static void ohci_device_isoc_done(usbd_xfer_handle);
178 1.91 augustss
179 1.120 augustss Static usbd_status ohci_device_setintr(ohci_softc_t *sc,
180 1.91 augustss struct ohci_pipe *pipe, int ival);
181 1.91 augustss
182 1.91 augustss Static void ohci_timeout(void *);
183 1.114 augustss Static void ohci_timeout_task(void *);
184 1.104 augustss Static void ohci_rhsc_enable(void *);
185 1.91 augustss
186 1.91 augustss Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *);
187 1.91 augustss Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status);
188 1.53 augustss
189 1.91 augustss Static void ohci_device_clear_toggle(usbd_pipe_handle pipe);
190 1.91 augustss Static void ohci_noop(usbd_pipe_handle pipe);
191 1.37 augustss
192 1.52 augustss #ifdef OHCI_DEBUG
193 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
194 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
195 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
196 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
197 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
198 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
199 1.1 augustss #endif
200 1.1 augustss
201 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
202 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
203 1.88 augustss #define OWRITE1(sc, r, x) \
204 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
205 1.88 augustss #define OWRITE2(sc, r, x) \
206 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
207 1.88 augustss #define OWRITE4(sc, r, x) \
208 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
209 1.174 mrg static __inline uint8_t
210 1.174 mrg OREAD1(ohci_softc_t *sc, bus_size_t r)
211 1.174 mrg {
212 1.174 mrg
213 1.174 mrg OBARR(sc);
214 1.174 mrg return bus_space_read_1(sc->iot, sc->ioh, r);
215 1.174 mrg }
216 1.174 mrg
217 1.174 mrg static __inline uint16_t
218 1.174 mrg OREAD2(ohci_softc_t *sc, bus_size_t r)
219 1.174 mrg {
220 1.174 mrg
221 1.174 mrg OBARR(sc);
222 1.174 mrg return bus_space_read_2(sc->iot, sc->ioh, r);
223 1.174 mrg }
224 1.174 mrg
225 1.174 mrg static __inline uint32_t
226 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
227 1.174 mrg {
228 1.174 mrg
229 1.174 mrg OBARR(sc);
230 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
231 1.174 mrg }
232 1.1 augustss
233 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
234 1.120 augustss Static u_int8_t revbits[OHCI_NO_INTRS] =
235 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
236 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
237 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
238 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
239 1.1 augustss
240 1.1 augustss struct ohci_pipe {
241 1.1 augustss struct usbd_pipe pipe;
242 1.1 augustss ohci_soft_ed_t *sed;
243 1.60 augustss union {
244 1.60 augustss ohci_soft_td_t *td;
245 1.60 augustss ohci_soft_itd_t *itd;
246 1.60 augustss } tail;
247 1.1 augustss /* Info needed for different pipe kinds. */
248 1.1 augustss union {
249 1.1 augustss /* Control pipe */
250 1.1 augustss struct {
251 1.4 augustss usb_dma_t reqdma;
252 1.1 augustss u_int length;
253 1.48 augustss ohci_soft_td_t *setup, *data, *stat;
254 1.1 augustss } ctl;
255 1.1 augustss /* Interrupt pipe */
256 1.1 augustss struct {
257 1.1 augustss int nslots;
258 1.1 augustss int pos;
259 1.1 augustss } intr;
260 1.3 augustss /* Bulk pipe */
261 1.3 augustss struct {
262 1.3 augustss u_int length;
263 1.32 augustss int isread;
264 1.3 augustss } bulk;
265 1.43 augustss /* Iso pipe */
266 1.43 augustss struct iso {
267 1.60 augustss int next, inuse;
268 1.43 augustss } iso;
269 1.1 augustss } u;
270 1.1 augustss };
271 1.1 augustss
272 1.1 augustss #define OHCI_INTR_ENDPT 1
273 1.1 augustss
274 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
275 1.218.6.6 mrg .open_pipe = ohci_open,
276 1.218.6.6 mrg .soft_intr = ohci_softintr,
277 1.218.6.6 mrg .do_poll = ohci_poll,
278 1.218.6.6 mrg .allocm = ohci_allocm,
279 1.218.6.6 mrg .freem = ohci_freem,
280 1.218.6.6 mrg .allocx = ohci_allocx,
281 1.218.6.6 mrg .freex = ohci_freex,
282 1.218.6.6 mrg .get_locks = ohci_get_locks,
283 1.42 augustss };
284 1.42 augustss
285 1.182 drochner Static const struct usbd_pipe_methods ohci_root_ctrl_methods = {
286 1.218.6.6 mrg .transfer = ohci_root_ctrl_transfer,
287 1.218.6.6 mrg .start = ohci_root_ctrl_start,
288 1.218.6.6 mrg .abort = ohci_root_ctrl_abort,
289 1.218.6.6 mrg .close = ohci_root_ctrl_close,
290 1.218.6.6 mrg .cleartoggle = ohci_noop,
291 1.218.6.6 mrg .done = ohci_root_ctrl_done,
292 1.1 augustss };
293 1.1 augustss
294 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
295 1.218.6.6 mrg .transfer = ohci_root_intr_transfer,
296 1.218.6.6 mrg .start = ohci_root_intr_start,
297 1.218.6.6 mrg .abort = ohci_root_intr_abort,
298 1.218.6.6 mrg .close = ohci_root_intr_close,
299 1.218.6.6 mrg .cleartoggle = ohci_noop,
300 1.218.6.6 mrg .done = ohci_root_intr_done,
301 1.1 augustss };
302 1.1 augustss
303 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
304 1.218.6.6 mrg .transfer = ohci_device_ctrl_transfer,
305 1.218.6.6 mrg .start = ohci_device_ctrl_start,
306 1.218.6.6 mrg .abort = ohci_device_ctrl_abort,
307 1.218.6.6 mrg .close = ohci_device_ctrl_close,
308 1.218.6.6 mrg .cleartoggle = ohci_noop,
309 1.218.6.6 mrg .done = ohci_device_ctrl_done,
310 1.1 augustss };
311 1.1 augustss
312 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
313 1.218.6.6 mrg .transfer = ohci_device_intr_transfer,
314 1.218.6.6 mrg .start = ohci_device_intr_start,
315 1.218.6.6 mrg .abort = ohci_device_intr_abort,
316 1.218.6.6 mrg .close = ohci_device_intr_close,
317 1.218.6.6 mrg .cleartoggle = ohci_device_clear_toggle,
318 1.218.6.6 mrg .done = ohci_device_intr_done,
319 1.1 augustss };
320 1.1 augustss
321 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
322 1.218.6.6 mrg .transfer = ohci_device_bulk_transfer,
323 1.218.6.6 mrg .start = ohci_device_bulk_start,
324 1.218.6.6 mrg .abort = ohci_device_bulk_abort,
325 1.218.6.6 mrg .close = ohci_device_bulk_close,
326 1.218.6.6 mrg .cleartoggle = ohci_device_clear_toggle,
327 1.218.6.6 mrg .done = ohci_device_bulk_done,
328 1.3 augustss };
329 1.3 augustss
330 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
331 1.218.6.6 mrg .transfer = ohci_device_isoc_transfer,
332 1.218.6.6 mrg .start = ohci_device_isoc_start,
333 1.218.6.6 mrg .abort = ohci_device_isoc_abort,
334 1.218.6.6 mrg .close = ohci_device_isoc_close,
335 1.218.6.6 mrg .cleartoggle = ohci_noop,
336 1.218.6.6 mrg .done = ohci_device_isoc_done,
337 1.43 augustss };
338 1.43 augustss
339 1.47 augustss int
340 1.189 dyoung ohci_activate(device_t self, enum devact act)
341 1.47 augustss {
342 1.189 dyoung struct ohci_softc *sc = device_private(self);
343 1.47 augustss
344 1.47 augustss switch (act) {
345 1.47 augustss case DVACT_DEACTIVATE:
346 1.183 kiyohara sc->sc_dying = 1;
347 1.203 dyoung return 0;
348 1.203 dyoung default:
349 1.203 dyoung return EOPNOTSUPP;
350 1.47 augustss }
351 1.47 augustss }
352 1.47 augustss
353 1.187 dyoung void
354 1.187 dyoung ohci_childdet(device_t self, device_t child)
355 1.187 dyoung {
356 1.187 dyoung struct ohci_softc *sc = device_private(self);
357 1.187 dyoung
358 1.187 dyoung KASSERT(sc->sc_child == child);
359 1.187 dyoung sc->sc_child = NULL;
360 1.187 dyoung }
361 1.187 dyoung
362 1.47 augustss int
363 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
364 1.47 augustss {
365 1.47 augustss int rv = 0;
366 1.196 drochner usbd_xfer_handle xfer;
367 1.47 augustss
368 1.47 augustss if (sc->sc_child != NULL)
369 1.47 augustss rv = config_detach(sc->sc_child, flags);
370 1.120 augustss
371 1.47 augustss if (rv != 0)
372 1.47 augustss return (rv);
373 1.47 augustss
374 1.209 dyoung callout_stop(&sc->sc_tmo_rhsc);
375 1.104 augustss
376 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
377 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
378 1.116 augustss
379 1.218.6.2 jmcneill softint_disestablish(sc->sc_rhsc_si);
380 1.218.6.2 jmcneill
381 1.218.6.2 jmcneill cv_destroy(&sc->sc_softwake_cv);
382 1.218.6.2 jmcneill
383 1.218.6.2 jmcneill mutex_destroy(&sc->sc_lock);
384 1.218.6.2 jmcneill mutex_destroy(&sc->sc_intr_lock);
385 1.218.6.2 jmcneill
386 1.198 cegger if (sc->sc_hcca != NULL)
387 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
388 1.196 drochner while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) {
389 1.196 drochner SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
390 1.218.6.2 jmcneill kmem_free(xfer, sizeof(struct ohci_xfer));
391 1.196 drochner }
392 1.47 augustss
393 1.47 augustss return (rv);
394 1.47 augustss }
395 1.47 augustss
396 1.1 augustss ohci_soft_ed_t *
397 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
398 1.1 augustss {
399 1.1 augustss ohci_soft_ed_t *sed;
400 1.53 augustss usbd_status err;
401 1.1 augustss int i, offs;
402 1.4 augustss usb_dma_t dma;
403 1.1 augustss
404 1.53 augustss if (sc->sc_freeeds == NULL) {
405 1.1 augustss DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
406 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
407 1.53 augustss OHCI_ED_ALIGN, &dma);
408 1.53 augustss if (err)
409 1.39 augustss return (0);
410 1.39 augustss for(i = 0; i < OHCI_SED_CHUNK; i++) {
411 1.39 augustss offs = i * OHCI_SED_SIZE;
412 1.123 augustss sed = KERNADDR(&dma, offs);
413 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
414 1.195 bouyer sed->dma = dma;
415 1.195 bouyer sed->offs = offs;
416 1.1 augustss sed->next = sc->sc_freeeds;
417 1.1 augustss sc->sc_freeeds = sed;
418 1.1 augustss }
419 1.1 augustss }
420 1.1 augustss sed = sc->sc_freeeds;
421 1.1 augustss sc->sc_freeeds = sed->next;
422 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
423 1.1 augustss sed->next = 0;
424 1.39 augustss return (sed);
425 1.1 augustss }
426 1.1 augustss
427 1.1 augustss void
428 1.91 augustss ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
429 1.1 augustss {
430 1.1 augustss sed->next = sc->sc_freeeds;
431 1.1 augustss sc->sc_freeeds = sed;
432 1.1 augustss }
433 1.1 augustss
434 1.1 augustss ohci_soft_td_t *
435 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
436 1.1 augustss {
437 1.1 augustss ohci_soft_td_t *std;
438 1.53 augustss usbd_status err;
439 1.1 augustss int i, offs;
440 1.4 augustss usb_dma_t dma;
441 1.1 augustss
442 1.53 augustss if (sc->sc_freetds == NULL) {
443 1.1 augustss DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
444 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
445 1.53 augustss OHCI_TD_ALIGN, &dma);
446 1.53 augustss if (err)
447 1.83 augustss return (NULL);
448 1.39 augustss for(i = 0; i < OHCI_STD_CHUNK; i++) {
449 1.39 augustss offs = i * OHCI_STD_SIZE;
450 1.123 augustss std = KERNADDR(&dma, offs);
451 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
452 1.195 bouyer std->dma = dma;
453 1.195 bouyer std->offs = offs;
454 1.1 augustss std->nexttd = sc->sc_freetds;
455 1.1 augustss sc->sc_freetds = std;
456 1.1 augustss }
457 1.1 augustss }
458 1.69 augustss
459 1.1 augustss std = sc->sc_freetds;
460 1.1 augustss sc->sc_freetds = std->nexttd;
461 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
462 1.83 augustss std->nexttd = NULL;
463 1.83 augustss std->xfer = NULL;
464 1.69 augustss ohci_hash_add_td(sc, std);
465 1.69 augustss
466 1.1 augustss return (std);
467 1.1 augustss }
468 1.1 augustss
469 1.1 augustss void
470 1.91 augustss ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
471 1.1 augustss {
472 1.69 augustss
473 1.69 augustss ohci_hash_rem_td(sc, std);
474 1.1 augustss std->nexttd = sc->sc_freetds;
475 1.1 augustss sc->sc_freetds = std;
476 1.1 augustss }
477 1.1 augustss
478 1.1 augustss usbd_status
479 1.91 augustss ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc,
480 1.91 augustss int alen, int rd, usbd_xfer_handle xfer,
481 1.91 augustss ohci_soft_td_t *sp, ohci_soft_td_t **ep)
482 1.48 augustss {
483 1.48 augustss ohci_soft_td_t *next, *cur;
484 1.48 augustss ohci_physaddr_t dataphys, dataphysend;
485 1.77 augustss u_int32_t tdflags;
486 1.75 augustss int len, curlen;
487 1.77 augustss usb_dma_t *dma = &xfer->dmabuf;
488 1.77 augustss u_int16_t flags = xfer->flags;
489 1.48 augustss
490 1.75 augustss DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen));
491 1.75 augustss
492 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
493 1.218.6.2 jmcneill
494 1.75 augustss len = alen;
495 1.48 augustss cur = sp;
496 1.125 augustss dataphys = DMAADDR(dma, 0);
497 1.48 augustss dataphysend = OHCI_PAGE(dataphys + len - 1);
498 1.195 bouyer usb_syncmem(dma, 0, len,
499 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
500 1.168 augustss tdflags = HTOO32(
501 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
502 1.77 augustss (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) |
503 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
504 1.61 augustss
505 1.48 augustss for (;;) {
506 1.48 augustss next = ohci_alloc_std(sc);
507 1.75 augustss if (next == NULL)
508 1.61 augustss goto nomem;
509 1.48 augustss
510 1.48 augustss /* The OHCI hardware can handle at most one page crossing. */
511 1.48 augustss if (OHCI_PAGE(dataphys) == dataphysend ||
512 1.48 augustss OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
513 1.48 augustss /* we can handle it in this TD */
514 1.48 augustss curlen = len;
515 1.48 augustss } else {
516 1.48 augustss /* must use multiple TDs, fill as much as possible. */
517 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
518 1.48 augustss (dataphys & (OHCI_PAGE_SIZE-1));
519 1.78 augustss /* the length must be a multiple of the max size */
520 1.78 augustss curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize);
521 1.78 augustss #ifdef DIAGNOSTIC
522 1.78 augustss if (curlen == 0)
523 1.128 provos panic("ohci_alloc_std: curlen == 0");
524 1.78 augustss #endif
525 1.48 augustss }
526 1.48 augustss DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x "
527 1.48 augustss "dataphysend=0x%08x len=%d curlen=%d\n",
528 1.48 augustss dataphys, dataphysend,
529 1.48 augustss len, curlen));
530 1.48 augustss len -= curlen;
531 1.48 augustss
532 1.77 augustss cur->td.td_flags = tdflags;
533 1.168 augustss cur->td.td_cbp = HTOO32(dataphys);
534 1.48 augustss cur->nexttd = next;
535 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
536 1.168 augustss cur->td.td_be = HTOO32(dataphys + curlen - 1);
537 1.48 augustss cur->len = curlen;
538 1.48 augustss cur->flags = OHCI_ADD_LEN;
539 1.77 augustss cur->xfer = xfer;
540 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
541 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
542 1.48 augustss DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n",
543 1.48 augustss dataphys, dataphys + curlen - 1));
544 1.48 augustss if (len == 0)
545 1.48 augustss break;
546 1.48 augustss DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n"));
547 1.48 augustss dataphys += curlen;
548 1.48 augustss cur = next;
549 1.48 augustss }
550 1.164 augustss if (!rd && (flags & USBD_FORCE_SHORT_XFER) &&
551 1.75 augustss alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) {
552 1.61 augustss /* Force a 0 length transfer at the end. */
553 1.75 augustss
554 1.75 augustss cur = next;
555 1.61 augustss next = ohci_alloc_std(sc);
556 1.75 augustss if (next == NULL)
557 1.61 augustss goto nomem;
558 1.61 augustss
559 1.77 augustss cur->td.td_flags = tdflags;
560 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
561 1.61 augustss cur->nexttd = next;
562 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
563 1.75 augustss cur->td.td_be = ~0;
564 1.61 augustss cur->len = 0;
565 1.61 augustss cur->flags = 0;
566 1.77 augustss cur->xfer = xfer;
567 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
568 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
569 1.61 augustss DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n"));
570 1.61 augustss }
571 1.77 augustss *ep = cur;
572 1.48 augustss
573 1.48 augustss return (USBD_NORMAL_COMPLETION);
574 1.61 augustss
575 1.61 augustss nomem:
576 1.61 augustss /* XXX free chain */
577 1.61 augustss return (USBD_NOMEM);
578 1.48 augustss }
579 1.48 augustss
580 1.53 augustss #if 0
581 1.82 augustss Static void
582 1.120 augustss ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std,
583 1.91 augustss ohci_soft_td_t *stdend)
584 1.48 augustss {
585 1.48 augustss ohci_soft_td_t *p;
586 1.48 augustss
587 1.48 augustss for (; std != stdend; std = p) {
588 1.48 augustss p = std->nexttd;
589 1.48 augustss ohci_free_std(sc, std);
590 1.48 augustss }
591 1.48 augustss }
592 1.53 augustss #endif
593 1.48 augustss
594 1.60 augustss ohci_soft_itd_t *
595 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
596 1.60 augustss {
597 1.60 augustss ohci_soft_itd_t *sitd;
598 1.60 augustss usbd_status err;
599 1.218.6.2 jmcneill int i, offs;
600 1.60 augustss usb_dma_t dma;
601 1.60 augustss
602 1.60 augustss if (sc->sc_freeitds == NULL) {
603 1.60 augustss DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n"));
604 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
605 1.83 augustss OHCI_ITD_ALIGN, &dma);
606 1.60 augustss if (err)
607 1.83 augustss return (NULL);
608 1.83 augustss for(i = 0; i < OHCI_SITD_CHUNK; i++) {
609 1.83 augustss offs = i * OHCI_SITD_SIZE;
610 1.123 augustss sitd = KERNADDR(&dma, offs);
611 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
612 1.195 bouyer sitd->dma = dma;
613 1.195 bouyer sitd->offs = offs;
614 1.60 augustss sitd->nextitd = sc->sc_freeitds;
615 1.60 augustss sc->sc_freeitds = sitd;
616 1.60 augustss }
617 1.60 augustss }
618 1.83 augustss
619 1.60 augustss sitd = sc->sc_freeitds;
620 1.60 augustss sc->sc_freeitds = sitd->nextitd;
621 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
622 1.83 augustss sitd->nextitd = NULL;
623 1.83 augustss sitd->xfer = NULL;
624 1.83 augustss ohci_hash_add_itd(sc, sitd);
625 1.83 augustss
626 1.83 augustss #ifdef DIAGNOSTIC
627 1.83 augustss sitd->isdone = 0;
628 1.83 augustss #endif
629 1.83 augustss
630 1.60 augustss return (sitd);
631 1.60 augustss }
632 1.60 augustss
633 1.60 augustss void
634 1.91 augustss ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
635 1.60 augustss {
636 1.83 augustss
637 1.83 augustss DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd));
638 1.83 augustss
639 1.83 augustss #ifdef DIAGNOSTIC
640 1.83 augustss if (!sitd->isdone) {
641 1.128 provos panic("ohci_free_sitd: sitd=%p not done", sitd);
642 1.83 augustss return;
643 1.83 augustss }
644 1.134 toshii /* Warn double free */
645 1.134 toshii sitd->isdone = 0;
646 1.83 augustss #endif
647 1.83 augustss
648 1.83 augustss ohci_hash_rem_itd(sc, sitd);
649 1.60 augustss sitd->nextitd = sc->sc_freeitds;
650 1.60 augustss sc->sc_freeitds = sitd;
651 1.60 augustss }
652 1.60 augustss
653 1.48 augustss usbd_status
654 1.91 augustss ohci_init(ohci_softc_t *sc)
655 1.1 augustss {
656 1.1 augustss ohci_soft_ed_t *sed, *psed;
657 1.53 augustss usbd_status err;
658 1.1 augustss int i;
659 1.161 augustss u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb;
660 1.16 augustss
661 1.1 augustss DPRINTF(("ohci_init: start\n"));
662 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
663 1.199 jmcneill
664 1.198 cegger sc->sc_hcca = NULL;
665 1.218.6.2 jmcneill callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
666 1.218.6.2 jmcneill
667 1.218.6.2 jmcneill mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
668 1.218.6.2 jmcneill mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
669 1.218.6.2 jmcneill cv_init(&sc->sc_softwake_cv, "ohciab");
670 1.218.6.2 jmcneill
671 1.218.6.2 jmcneill sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
672 1.218.6.2 jmcneill ohci_rhsc_softint, sc);
673 1.198 cegger
674 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
675 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
676 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
677 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
678 1.198 cegger
679 1.198 cegger SIMPLEQ_INIT(&sc->sc_free_xfers);
680 1.198 cegger
681 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
682 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
683 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
684 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
685 1.55 augustss
686 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
687 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
688 1.56 augustss sc->sc_bus.usbrev = USBREV_UNKNOWN;
689 1.1 augustss return (USBD_INVAL);
690 1.1 augustss }
691 1.56 augustss sc->sc_bus.usbrev = USBREV_1_0;
692 1.1 augustss
693 1.193 drochner usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag,
694 1.153 fvdl USB_MEM_RESERVE);
695 1.153 fvdl
696 1.73 augustss /* XXX determine alignment by R/W */
697 1.1 augustss /* Allocate the HCCA area. */
698 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
699 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
700 1.198 cegger if (err) {
701 1.198 cegger sc->sc_hcca = NULL;
702 1.198 cegger return err;
703 1.198 cegger }
704 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
705 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
706 1.1 augustss
707 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
708 1.1 augustss
709 1.60 augustss /* Allocate dummy ED that starts the control list. */
710 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
711 1.53 augustss if (sc->sc_ctrl_head == NULL) {
712 1.53 augustss err = USBD_NOMEM;
713 1.1 augustss goto bad1;
714 1.1 augustss }
715 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
716 1.34 augustss
717 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
718 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
719 1.53 augustss if (sc->sc_bulk_head == NULL) {
720 1.53 augustss err = USBD_NOMEM;
721 1.1 augustss goto bad2;
722 1.1 augustss }
723 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
724 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
725 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
726 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
727 1.1 augustss
728 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
729 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
730 1.60 augustss if (sc->sc_isoc_head == NULL) {
731 1.60 augustss err = USBD_NOMEM;
732 1.60 augustss goto bad3;
733 1.60 augustss }
734 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
735 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
736 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
737 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
738 1.60 augustss
739 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
740 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
741 1.1 augustss sed = ohci_alloc_sed(sc);
742 1.53 augustss if (sed == NULL) {
743 1.1 augustss while (--i >= 0)
744 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
745 1.53 augustss err = USBD_NOMEM;
746 1.60 augustss goto bad4;
747 1.1 augustss }
748 1.1 augustss /* All ED fields are set to 0. */
749 1.1 augustss sc->sc_eds[i] = sed;
750 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
751 1.60 augustss if (i != 0)
752 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
753 1.60 augustss else
754 1.60 augustss psed= sc->sc_isoc_head;
755 1.60 augustss sed->next = psed;
756 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
757 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
758 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
759 1.1 augustss }
760 1.120 augustss /*
761 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
762 1.1 augustss * the tree set up properly to spread the interrupts.
763 1.1 augustss */
764 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
765 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
766 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
767 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
768 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
769 1.1 augustss
770 1.73 augustss #ifdef OHCI_DEBUG
771 1.73 augustss if (ohcidebug > 15) {
772 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
773 1.73 augustss printf("ed#%d ", i);
774 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
775 1.73 augustss }
776 1.73 augustss printf("iso ");
777 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
778 1.73 augustss }
779 1.73 augustss #endif
780 1.73 augustss
781 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
782 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
783 1.161 augustss rwc = ctl & OHCI_RWC;
784 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
785 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
786 1.161 augustss descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
787 1.161 augustss
788 1.1 augustss /* Determine in what context we are running. */
789 1.1 augustss if (ctl & OHCI_IR) {
790 1.1 augustss /* SMM active, request change */
791 1.1 augustss DPRINTF(("ohci_init: SMM active, request owner change\n"));
792 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
793 1.160 augustss (OHCI_OC | OHCI_MIE))
794 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
795 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
796 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
797 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
798 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
799 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
800 1.1 augustss }
801 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
802 1.1 augustss if ((ctl & OHCI_IR) == 0) {
803 1.199 jmcneill aprint_error_dev(sc->sc_dev,
804 1.199 jmcneill "SMM does not respond, resetting\n");
805 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
806 1.1 augustss goto reset;
807 1.1 augustss }
808 1.103 augustss #if 0
809 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
810 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
811 1.1 augustss /* BIOS started controller. */
812 1.1 augustss DPRINTF(("ohci_init: BIOS active\n"));
813 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
814 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
815 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
816 1.1 augustss }
817 1.103 augustss #endif
818 1.1 augustss } else {
819 1.1 augustss DPRINTF(("ohci_init: cold started\n"));
820 1.1 augustss reset:
821 1.1 augustss /* Controller was cold started. */
822 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
823 1.1 augustss }
824 1.1 augustss
825 1.16 augustss /*
826 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
827 1.25 augustss * without it some controllers do not start.
828 1.16 augustss */
829 1.190 drochner DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev)));
830 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
831 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
832 1.16 augustss
833 1.1 augustss /* We now own the host controller and the bus has been reset. */
834 1.1 augustss
835 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
836 1.1 augustss /* Nominal time for a reset is 10 us. */
837 1.1 augustss for (i = 0; i < 10; i++) {
838 1.1 augustss delay(10);
839 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
840 1.1 augustss if (!hcr)
841 1.1 augustss break;
842 1.1 augustss }
843 1.1 augustss if (hcr) {
844 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
845 1.53 augustss err = USBD_IOERROR;
846 1.60 augustss goto bad5;
847 1.1 augustss }
848 1.52 augustss #ifdef OHCI_DEBUG
849 1.1 augustss if (ohcidebug > 15)
850 1.1 augustss ohci_dumpregs(sc);
851 1.1 augustss #endif
852 1.1 augustss
853 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
854 1.1 augustss
855 1.1 augustss /* Set up HC registers. */
856 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
857 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
858 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
859 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
860 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
861 1.55 augustss /* switch on desired functional features */
862 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
863 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
864 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
865 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
866 1.1 augustss /* And finally start it! */
867 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
868 1.1 augustss
869 1.1 augustss /*
870 1.1 augustss * The controller is now OPERATIONAL. Set a some final
871 1.1 augustss * registers that should be set earlier, but that the
872 1.1 augustss * controller ignores when in the SUSPEND state.
873 1.1 augustss */
874 1.161 augustss ival = OHCI_GET_IVAL(fm);
875 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
876 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
877 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
878 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
879 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
880 1.1 augustss
881 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
882 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
883 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
884 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
885 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
886 1.1 augustss
887 1.85 augustss /*
888 1.85 augustss * The AMD756 requires a delay before re-reading the register,
889 1.85 augustss * otherwise it will occasionally report 0 ports.
890 1.85 augustss */
891 1.145 augustss sc->sc_noport = 0;
892 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
893 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
894 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
895 1.145 augustss }
896 1.1 augustss
897 1.52 augustss #ifdef OHCI_DEBUG
898 1.1 augustss if (ohcidebug > 5)
899 1.1 augustss ohci_dumpregs(sc);
900 1.1 augustss #endif
901 1.120 augustss
902 1.1 augustss /* Set up the bus struct. */
903 1.42 augustss sc->sc_bus.methods = &ohci_bus_methods;
904 1.1 augustss sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
905 1.1 augustss
906 1.101 minoura sc->sc_control = sc->sc_intre = 0;
907 1.59 augustss
908 1.167 augustss /* Finally, turn on interrupts. */
909 1.211 matt DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE));
910 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
911 1.167 augustss
912 1.1 augustss return (USBD_NORMAL_COMPLETION);
913 1.1 augustss
914 1.60 augustss bad5:
915 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
916 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
917 1.60 augustss bad4:
918 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
919 1.1 augustss bad3:
920 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
921 1.144 augustss bad2:
922 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
923 1.1 augustss bad1:
924 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
925 1.198 cegger sc->sc_hcca = NULL;
926 1.53 augustss return (err);
927 1.1 augustss }
928 1.1 augustss
929 1.42 augustss usbd_status
930 1.91 augustss ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
931 1.42 augustss {
932 1.191 nakayama struct ohci_softc *sc = bus->hci_private;
933 1.153 fvdl usbd_status status;
934 1.42 augustss
935 1.153 fvdl status = usb_allocmem(&sc->sc_bus, size, 0, dma);
936 1.153 fvdl if (status == USBD_NOMEM)
937 1.153 fvdl status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size);
938 1.153 fvdl return status;
939 1.42 augustss }
940 1.42 augustss
941 1.42 augustss void
942 1.91 augustss ohci_freem(struct usbd_bus *bus, usb_dma_t *dma)
943 1.42 augustss {
944 1.191 nakayama struct ohci_softc *sc = bus->hci_private;
945 1.153 fvdl if (dma->block->flags & USB_DMA_RESERVE) {
946 1.191 nakayama usb_reserve_freem(&sc->sc_dma_reserve, dma);
947 1.153 fvdl return;
948 1.153 fvdl }
949 1.44 augustss usb_freemem(&sc->sc_bus, dma);
950 1.62 augustss }
951 1.62 augustss
952 1.62 augustss usbd_xfer_handle
953 1.91 augustss ohci_allocx(struct usbd_bus *bus)
954 1.62 augustss {
955 1.191 nakayama struct ohci_softc *sc = bus->hci_private;
956 1.62 augustss usbd_xfer_handle xfer;
957 1.62 augustss
958 1.62 augustss xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
959 1.118 augustss if (xfer != NULL) {
960 1.126 lukem SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
961 1.118 augustss #ifdef DIAGNOSTIC
962 1.118 augustss if (xfer->busy_free != XFER_FREE) {
963 1.118 augustss printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer,
964 1.118 augustss xfer->busy_free);
965 1.118 augustss }
966 1.118 augustss #endif
967 1.118 augustss } else {
968 1.218.6.2 jmcneill xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP);
969 1.118 augustss }
970 1.118 augustss if (xfer != NULL) {
971 1.215 tsutsui memset(xfer, 0, sizeof (struct ohci_xfer));
972 1.118 augustss #ifdef DIAGNOSTIC
973 1.118 augustss xfer->busy_free = XFER_BUSY;
974 1.118 augustss #endif
975 1.118 augustss }
976 1.62 augustss return (xfer);
977 1.62 augustss }
978 1.62 augustss
979 1.62 augustss void
980 1.91 augustss ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
981 1.62 augustss {
982 1.191 nakayama struct ohci_softc *sc = bus->hci_private;
983 1.62 augustss
984 1.118 augustss #ifdef DIAGNOSTIC
985 1.118 augustss if (xfer->busy_free != XFER_BUSY) {
986 1.118 augustss printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer,
987 1.118 augustss xfer->busy_free);
988 1.118 augustss }
989 1.118 augustss xfer->busy_free = XFER_FREE;
990 1.118 augustss #endif
991 1.62 augustss SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
992 1.42 augustss }
993 1.42 augustss
994 1.218.6.2 jmcneill Static void
995 1.218.6.2 jmcneill ohci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread)
996 1.218.6.2 jmcneill {
997 1.218.6.2 jmcneill struct ohci_softc *sc = bus->hci_private;
998 1.218.6.2 jmcneill
999 1.218.6.2 jmcneill *intr = &sc->sc_intr_lock;
1000 1.218.6.2 jmcneill *thread = &sc->sc_lock;
1001 1.218.6.2 jmcneill }
1002 1.218.6.2 jmcneill
1003 1.59 augustss /*
1004 1.59 augustss * Shut down the controller when the system is going down.
1005 1.59 augustss */
1006 1.188 dyoung bool
1007 1.188 dyoung ohci_shutdown(device_t self, int flags)
1008 1.59 augustss {
1009 1.188 dyoung ohci_softc_t *sc = device_private(self);
1010 1.59 augustss
1011 1.59 augustss DPRINTF(("ohci_shutdown: stopping the HC\n"));
1012 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1013 1.188 dyoung return true;
1014 1.59 augustss }
1015 1.59 augustss
1016 1.185 jmcneill bool
1017 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1018 1.33 augustss {
1019 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1020 1.185 jmcneill uint32_t ctl;
1021 1.33 augustss
1022 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1023 1.185 jmcneill sc->sc_bus.use_polling++;
1024 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1025 1.218.6.2 jmcneill
1026 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1027 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1028 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1029 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1030 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1031 1.185 jmcneill sc->sc_bulk_head->physaddr);
1032 1.185 jmcneill if (sc->sc_intre)
1033 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1034 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1035 1.185 jmcneill if (sc->sc_control)
1036 1.185 jmcneill ctl = sc->sc_control;
1037 1.185 jmcneill else
1038 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1039 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1040 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1041 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1042 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1043 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1044 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1045 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1046 1.218.6.2 jmcneill
1047 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1048 1.185 jmcneill sc->sc_bus.use_polling--;
1049 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1050 1.185 jmcneill
1051 1.185 jmcneill return true;
1052 1.185 jmcneill }
1053 1.185 jmcneill
1054 1.185 jmcneill bool
1055 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1056 1.185 jmcneill {
1057 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1058 1.185 jmcneill uint32_t ctl;
1059 1.95 augustss
1060 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1061 1.185 jmcneill sc->sc_bus.use_polling++;
1062 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1063 1.218.6.2 jmcneill
1064 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1065 1.185 jmcneill if (sc->sc_control == 0) {
1066 1.185 jmcneill /*
1067 1.185 jmcneill * Preserve register values, in case that BIOS
1068 1.185 jmcneill * does not recover them.
1069 1.185 jmcneill */
1070 1.185 jmcneill sc->sc_control = ctl;
1071 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1072 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1073 1.95 augustss }
1074 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1075 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1076 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1077 1.218.6.2 jmcneill
1078 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1079 1.185 jmcneill sc->sc_bus.use_polling--;
1080 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1081 1.185 jmcneill
1082 1.185 jmcneill return true;
1083 1.33 augustss }
1084 1.33 augustss
1085 1.52 augustss #ifdef OHCI_DEBUG
1086 1.1 augustss void
1087 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1088 1.1 augustss {
1089 1.41 augustss DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
1090 1.41 augustss OREAD4(sc, OHCI_REVISION),
1091 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1092 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
1093 1.41 augustss DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
1094 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1095 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1096 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_DISABLE)));
1097 1.41 augustss DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
1098 1.41 augustss OREAD4(sc, OHCI_HCCA),
1099 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1100 1.41 augustss OREAD4(sc, OHCI_CONTROL_HEAD_ED)));
1101 1.41 augustss DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
1102 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1103 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1104 1.41 augustss OREAD4(sc, OHCI_BULK_CURRENT_ED)));
1105 1.41 augustss DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
1106 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1107 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1108 1.41 augustss OREAD4(sc, OHCI_FM_REMAINING)));
1109 1.41 augustss DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
1110 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1111 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1112 1.41 augustss OREAD4(sc, OHCI_LS_THRESHOLD)));
1113 1.41 augustss DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n",
1114 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1115 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1116 1.41 augustss OREAD4(sc, OHCI_RH_STATUS)));
1117 1.41 augustss DPRINTF((" port1=0x%08x port2=0x%08x\n",
1118 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1119 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(2))));
1120 1.41 augustss DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n",
1121 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1122 1.168 augustss O32TOH(sc->sc_hcca->hcca_done_head)));
1123 1.1 augustss }
1124 1.1 augustss #endif
1125 1.1 augustss
1126 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1127 1.53 augustss
1128 1.1 augustss int
1129 1.91 augustss ohci_intr(void *p)
1130 1.1 augustss {
1131 1.1 augustss ohci_softc_t *sc = p;
1132 1.218.6.2 jmcneill int ret = 0;
1133 1.111 augustss
1134 1.218.6.2 jmcneill if (sc == NULL)
1135 1.111 augustss return (0);
1136 1.53 augustss
1137 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1138 1.218.6.2 jmcneill
1139 1.218.6.2 jmcneill if (sc->sc_dying || !device_has_power(sc->sc_dev))
1140 1.218.6.2 jmcneill goto done;
1141 1.218.6.2 jmcneill
1142 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1143 1.57 augustss if (sc->sc_bus.use_polling) {
1144 1.57 augustss #ifdef DIAGNOSTIC
1145 1.149 mycroft DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n"));
1146 1.57 augustss #endif
1147 1.154 joff /* for level triggered intrs, should do something to ack */
1148 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1149 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1150 1.155 perry
1151 1.218.6.4 mrg goto done;
1152 1.57 augustss }
1153 1.53 augustss
1154 1.218.6.2 jmcneill ret = ohci_intr1(sc);
1155 1.218.6.2 jmcneill
1156 1.218.6.2 jmcneill done:
1157 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1158 1.218.6.2 jmcneill return ret;
1159 1.53 augustss }
1160 1.53 augustss
1161 1.82 augustss Static int
1162 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1163 1.53 augustss {
1164 1.1 augustss u_int32_t intrs, eintrs;
1165 1.1 augustss
1166 1.105 augustss DPRINTFN(14,("ohci_intr1: enter\n"));
1167 1.105 augustss
1168 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1169 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1170 1.15 augustss #ifdef DIAGNOSTIC
1171 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1172 1.15 augustss #endif
1173 1.15 augustss return (0);
1174 1.15 augustss }
1175 1.15 augustss
1176 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_intr_lock));
1177 1.218.6.2 jmcneill
1178 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1179 1.1 augustss if (!intrs)
1180 1.1 augustss return (0);
1181 1.55 augustss
1182 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */
1183 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1184 1.211 matt DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n",
1185 1.211 matt sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
1186 1.211 matt (u_int)eintrs, sc->sc_eintrs));
1187 1.211 matt
1188 1.211 matt if (!eintrs) {
1189 1.1 augustss return (0);
1190 1.211 matt }
1191 1.1 augustss
1192 1.45 augustss sc->sc_bus.intr_context++;
1193 1.44 augustss sc->sc_bus.no_intrs++;
1194 1.1 augustss if (eintrs & OHCI_SO) {
1195 1.100 augustss sc->sc_overrun_cnt++;
1196 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1197 1.100 augustss printf("%s: %u scheduling overruns\n",
1198 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1199 1.100 augustss sc->sc_overrun_cnt = 0;
1200 1.100 augustss }
1201 1.1 augustss /* XXX do what */
1202 1.106 augustss eintrs &= ~OHCI_SO;
1203 1.1 augustss }
1204 1.1 augustss if (eintrs & OHCI_WDH) {
1205 1.157 mycroft /*
1206 1.157 mycroft * We block the interrupt below, and reenable it later from
1207 1.157 mycroft * ohci_softintr().
1208 1.157 mycroft */
1209 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1210 1.1 augustss }
1211 1.1 augustss if (eintrs & OHCI_RD) {
1212 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1213 1.1 augustss /* XXX process resume detect */
1214 1.1 augustss }
1215 1.1 augustss if (eintrs & OHCI_UE) {
1216 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1217 1.190 drochner device_xname(sc->sc_dev));
1218 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1219 1.1 augustss /* XXX what else */
1220 1.1 augustss }
1221 1.1 augustss if (eintrs & OHCI_RHSC) {
1222 1.120 augustss /*
1223 1.157 mycroft * We block the interrupt below, and reenable it later from
1224 1.157 mycroft * a timeout.
1225 1.1 augustss */
1226 1.218.6.2 jmcneill softint_schedule(sc->sc_rhsc_si);
1227 1.1 augustss }
1228 1.1 augustss
1229 1.45 augustss sc->sc_bus.intr_context--;
1230 1.44 augustss
1231 1.106 augustss if (eintrs != 0) {
1232 1.157 mycroft /* Block unprocessed interrupts. */
1233 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1234 1.106 augustss sc->sc_eintrs &= ~eintrs;
1235 1.157 mycroft DPRINTFN(1, ("%s: blocking intrs 0x%x\n",
1236 1.190 drochner device_xname(sc->sc_dev), eintrs));
1237 1.106 augustss }
1238 1.1 augustss
1239 1.1 augustss return (1);
1240 1.1 augustss }
1241 1.1 augustss
1242 1.1 augustss void
1243 1.104 augustss ohci_rhsc_enable(void *v_sc)
1244 1.104 augustss {
1245 1.104 augustss ohci_softc_t *sc = v_sc;
1246 1.104 augustss
1247 1.218.6.2 jmcneill DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev)));
1248 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1249 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1250 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1251 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1252 1.1 augustss }
1253 1.1 augustss
1254 1.52 augustss #ifdef OHCI_DEBUG
1255 1.166 drochner const char *ohci_cc_strs[] = {
1256 1.13 augustss "NO_ERROR",
1257 1.13 augustss "CRC",
1258 1.13 augustss "BIT_STUFFING",
1259 1.13 augustss "DATA_TOGGLE_MISMATCH",
1260 1.13 augustss "STALL",
1261 1.13 augustss "DEVICE_NOT_RESPONDING",
1262 1.13 augustss "PID_CHECK_FAILURE",
1263 1.13 augustss "UNEXPECTED_PID",
1264 1.13 augustss "DATA_OVERRUN",
1265 1.13 augustss "DATA_UNDERRUN",
1266 1.13 augustss "BUFFER_OVERRUN",
1267 1.13 augustss "BUFFER_UNDERRUN",
1268 1.67 augustss "reserved",
1269 1.67 augustss "reserved",
1270 1.67 augustss "NOT_ACCESSED",
1271 1.13 augustss "NOT_ACCESSED",
1272 1.13 augustss };
1273 1.13 augustss #endif
1274 1.13 augustss
1275 1.1 augustss void
1276 1.157 mycroft ohci_softintr(void *v)
1277 1.83 augustss {
1278 1.190 drochner struct usbd_bus *bus = v;
1279 1.190 drochner ohci_softc_t *sc = bus->hci_private;
1280 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1281 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1282 1.157 mycroft usbd_xfer_handle xfer;
1283 1.157 mycroft struct ohci_pipe *opipe;
1284 1.218.6.2 jmcneill int len, cc;
1285 1.157 mycroft int i, j, actlen, iframes, uedir;
1286 1.157 mycroft ohci_physaddr_t done;
1287 1.157 mycroft
1288 1.157 mycroft DPRINTFN(10,("ohci_softintr: enter\n"));
1289 1.157 mycroft
1290 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
1291 1.218.6.2 jmcneill
1292 1.157 mycroft sc->sc_bus.intr_context++;
1293 1.157 mycroft
1294 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1295 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1296 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1297 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1298 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1299 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1300 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1301 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1302 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1303 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1304 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1305 1.83 augustss
1306 1.83 augustss /* Reverse the done list. */
1307 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1308 1.83 augustss std = ohci_hash_find_td(sc, done);
1309 1.83 augustss if (std != NULL) {
1310 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1311 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1312 1.83 augustss std->dnext = sdone;
1313 1.168 augustss done = O32TOH(std->td.td_nexttd);
1314 1.83 augustss sdone = std;
1315 1.83 augustss DPRINTFN(10,("add TD %p\n", std));
1316 1.83 augustss continue;
1317 1.83 augustss }
1318 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1319 1.83 augustss if (sitd != NULL) {
1320 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1321 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1322 1.83 augustss sitd->dnext = sidone;
1323 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1324 1.83 augustss sidone = sitd;
1325 1.83 augustss DPRINTFN(5,("add ITD %p\n", sitd));
1326 1.83 augustss continue;
1327 1.83 augustss }
1328 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1329 1.218 jmcneill (u_long)done);
1330 1.218 jmcneill break;
1331 1.83 augustss }
1332 1.83 augustss
1333 1.105 augustss DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone));
1334 1.1 augustss
1335 1.52 augustss #ifdef OHCI_DEBUG
1336 1.1 augustss if (ohcidebug > 10) {
1337 1.41 augustss DPRINTF(("ohci_process_done: TD done:\n"));
1338 1.168 augustss ohci_dump_tds(sc, sdone);
1339 1.1 augustss }
1340 1.1 augustss #endif
1341 1.1 augustss
1342 1.48 augustss for (std = sdone; std; std = stdnext) {
1343 1.53 augustss xfer = std->xfer;
1344 1.48 augustss stdnext = std->dnext;
1345 1.53 augustss DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n",
1346 1.69 augustss std, xfer, xfer ? xfer->hcpriv : 0));
1347 1.71 augustss if (xfer == NULL) {
1348 1.117 augustss /*
1349 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1350 1.71 augustss * with this TD. It is tailp that happened to end up on
1351 1.71 augustss * the done queue.
1352 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1353 1.71 augustss */
1354 1.71 augustss continue;
1355 1.71 augustss }
1356 1.53 augustss if (xfer->status == USBD_CANCELLED ||
1357 1.53 augustss xfer->status == USBD_TIMEOUT) {
1358 1.34 augustss DPRINTF(("ohci_process_done: cancel/timeout %p\n",
1359 1.53 augustss xfer));
1360 1.38 augustss /* Handled by abort routine. */
1361 1.83 augustss continue;
1362 1.83 augustss }
1363 1.209 dyoung callout_stop(&xfer->timeout_handle);
1364 1.141 mycroft
1365 1.141 mycroft len = std->len;
1366 1.141 mycroft if (std->td.td_cbp != 0)
1367 1.168 augustss len -= O32TOH(std->td.td_be) -
1368 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1369 1.141 mycroft DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len,
1370 1.141 mycroft std->flags));
1371 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1372 1.141 mycroft xfer->actlen += len;
1373 1.141 mycroft
1374 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1375 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1376 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1377 1.53 augustss xfer->status = USBD_NORMAL_COMPLETION;
1378 1.53 augustss usb_transfer_complete(xfer);
1379 1.21 augustss }
1380 1.48 augustss ohci_free_std(sc, std);
1381 1.1 augustss } else {
1382 1.48 augustss /*
1383 1.48 augustss * Endpoint is halted. First unlink all the TDs
1384 1.48 augustss * belonging to the failed transfer, and then restart
1385 1.48 augustss * the endpoint.
1386 1.48 augustss */
1387 1.1 augustss ohci_soft_td_t *p, *n;
1388 1.134 toshii opipe = (struct ohci_pipe *)xfer->pipe;
1389 1.48 augustss
1390 1.71 augustss DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n",
1391 1.168 augustss OHCI_TD_GET_CC(O32TOH(std->td.td_flags)),
1392 1.168 augustss ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))]));
1393 1.48 augustss
1394 1.48 augustss /* remove TDs */
1395 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1396 1.1 augustss n = p->nexttd;
1397 1.1 augustss ohci_free_std(sc, p);
1398 1.1 augustss }
1399 1.48 augustss
1400 1.16 augustss /* clear halt */
1401 1.168 augustss opipe->sed->ed.ed_headp = HTOO32(p->physaddr);
1402 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1403 1.48 augustss
1404 1.1 augustss if (cc == OHCI_CC_STALL)
1405 1.53 augustss xfer->status = USBD_STALLED;
1406 1.1 augustss else
1407 1.53 augustss xfer->status = USBD_IOERROR;
1408 1.53 augustss usb_transfer_complete(xfer);
1409 1.1 augustss }
1410 1.1 augustss }
1411 1.72 augustss
1412 1.83 augustss #ifdef OHCI_DEBUG
1413 1.83 augustss if (ohcidebug > 10) {
1414 1.105 augustss DPRINTF(("ohci_softintr: ITD done:\n"));
1415 1.168 augustss ohci_dump_itds(sc, sidone);
1416 1.83 augustss }
1417 1.83 augustss #endif
1418 1.83 augustss
1419 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1420 1.83 augustss xfer = sitd->xfer;
1421 1.83 augustss sitdnext = sitd->dnext;
1422 1.83 augustss DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n",
1423 1.83 augustss sitd, xfer, xfer ? xfer->hcpriv : 0));
1424 1.83 augustss if (xfer == NULL)
1425 1.83 augustss continue;
1426 1.83 augustss if (xfer->status == USBD_CANCELLED ||
1427 1.83 augustss xfer->status == USBD_TIMEOUT) {
1428 1.83 augustss DPRINTF(("ohci_process_done: cancel/timeout %p\n",
1429 1.83 augustss xfer));
1430 1.83 augustss /* Handled by abort routine. */
1431 1.83 augustss continue;
1432 1.83 augustss }
1433 1.83 augustss #ifdef DIAGNOSTIC
1434 1.83 augustss if (sitd->isdone)
1435 1.83 augustss printf("ohci_softintr: sitd=%p is done\n", sitd);
1436 1.83 augustss sitd->isdone = 1;
1437 1.83 augustss #endif
1438 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1439 1.134 toshii ohci_soft_itd_t *next;
1440 1.134 toshii
1441 1.134 toshii opipe = (struct ohci_pipe *)xfer->pipe;
1442 1.134 toshii opipe->u.iso.inuse -= xfer->nframes;
1443 1.134 toshii uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc->
1444 1.134 toshii bEndpointAddress);
1445 1.134 toshii xfer->status = USBD_NORMAL_COMPLETION;
1446 1.134 toshii actlen = 0;
1447 1.137 simonb for (i = 0, sitd = xfer->hcpriv;;
1448 1.134 toshii sitd = next) {
1449 1.134 toshii next = sitd->nextitd;
1450 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1451 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1452 1.134 toshii xfer->status = USBD_IOERROR;
1453 1.134 toshii /* For input, update frlengths with actual */
1454 1.134 toshii /* XXX anything necessary for output? */
1455 1.134 toshii if (uedir == UE_DIR_IN &&
1456 1.134 toshii xfer->status == USBD_NORMAL_COMPLETION) {
1457 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1458 1.135 toshii sitd->itd.itd_flags));
1459 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1460 1.168 augustss len = O16TOH(sitd->
1461 1.134 toshii itd.itd_offset[j]);
1462 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1463 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1464 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1465 1.158 toshii len = 0;
1466 1.158 toshii else
1467 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1468 1.134 toshii xfer->frlengths[i] = len;
1469 1.134 toshii actlen += len;
1470 1.134 toshii }
1471 1.134 toshii }
1472 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1473 1.134 toshii break;
1474 1.134 toshii ohci_free_sitd(sc, sitd);
1475 1.83 augustss }
1476 1.134 toshii ohci_free_sitd(sc, sitd);
1477 1.134 toshii if (uedir == UE_DIR_IN &&
1478 1.134 toshii xfer->status == USBD_NORMAL_COMPLETION)
1479 1.134 toshii xfer->actlen = actlen;
1480 1.151 mycroft xfer->hcpriv = NULL;
1481 1.134 toshii
1482 1.83 augustss usb_transfer_complete(xfer);
1483 1.83 augustss }
1484 1.83 augustss }
1485 1.83 augustss
1486 1.119 augustss if (sc->sc_softwake) {
1487 1.119 augustss sc->sc_softwake = 0;
1488 1.218.6.2 jmcneill cv_broadcast(&sc->sc_softwake_cv);
1489 1.119 augustss }
1490 1.119 augustss
1491 1.72 augustss sc->sc_bus.intr_context--;
1492 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
1493 1.218.6.2 jmcneill
1494 1.105 augustss DPRINTFN(10,("ohci_softintr: done:\n"));
1495 1.1 augustss }
1496 1.1 augustss
1497 1.1 augustss void
1498 1.179 christos ohci_device_ctrl_done(usbd_xfer_handle xfer)
1499 1.1 augustss {
1500 1.195 bouyer struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
1501 1.218.6.5 macallan #ifdef DIAGNOSTIC
1502 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1503 1.218.6.5 macallan #endif
1504 1.195 bouyer int len = UGETW(xfer->request.wLength);
1505 1.195 bouyer int isread = (xfer->request.bmRequestType & UT_READ);
1506 1.195 bouyer
1507 1.140 gson DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer));
1508 1.1 augustss
1509 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
1510 1.218.6.2 jmcneill
1511 1.38 augustss #ifdef DIAGNOSTIC
1512 1.53 augustss if (!(xfer->rqflags & URQ_REQUEST)) {
1513 1.140 gson panic("ohci_device_ctrl_done: not a request");
1514 1.1 augustss }
1515 1.38 augustss #endif
1516 1.195 bouyer if (len)
1517 1.195 bouyer usb_syncmem(&xfer->dmabuf, 0, len,
1518 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1519 1.195 bouyer usb_syncmem(&opipe->u.ctl.reqdma, 0,
1520 1.195 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1521 1.1 augustss }
1522 1.1 augustss
1523 1.1 augustss void
1524 1.91 augustss ohci_device_intr_done(usbd_xfer_handle xfer)
1525 1.1 augustss {
1526 1.53 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
1527 1.190 drochner ohci_softc_t *sc = opipe->pipe.device->bus->hci_private;
1528 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
1529 1.48 augustss ohci_soft_td_t *data, *tail;
1530 1.195 bouyer int isread =
1531 1.195 bouyer (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN);
1532 1.1 augustss
1533 1.140 gson DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n",
1534 1.53 augustss xfer, xfer->actlen));
1535 1.1 augustss
1536 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
1537 1.218.6.2 jmcneill
1538 1.195 bouyer usb_syncmem(&xfer->dmabuf, 0, xfer->length,
1539 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1540 1.53 augustss if (xfer->pipe->repeat) {
1541 1.60 augustss data = opipe->tail.td;
1542 1.1 augustss tail = ohci_alloc_std(sc); /* XXX should reuse TD */
1543 1.53 augustss if (tail == NULL) {
1544 1.53 augustss xfer->status = USBD_NOMEM;
1545 1.1 augustss return;
1546 1.1 augustss }
1547 1.55 augustss tail->xfer = NULL;
1548 1.120 augustss
1549 1.168 augustss data->td.td_flags = HTOO32(
1550 1.120 augustss OHCI_TD_IN | OHCI_TD_NOCC |
1551 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
1552 1.53 augustss if (xfer->flags & USBD_SHORT_XFER_OK)
1553 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
1554 1.168 augustss data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0));
1555 1.48 augustss data->nexttd = tail;
1556 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
1557 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) +
1558 1.76 tsutsui xfer->length - 1);
1559 1.53 augustss data->len = xfer->length;
1560 1.53 augustss data->xfer = xfer;
1561 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
1562 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
1563 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1564 1.53 augustss xfer->hcpriv = data;
1565 1.53 augustss xfer->actlen = 0;
1566 1.1 augustss
1567 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
1568 1.195 bouyer usb_syncmem(&sed->dma,
1569 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_tailp),
1570 1.195 bouyer sizeof(sed->ed.ed_tailp),
1571 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1572 1.60 augustss opipe->tail.td = tail;
1573 1.1 augustss }
1574 1.1 augustss }
1575 1.1 augustss
1576 1.1 augustss void
1577 1.179 christos ohci_device_bulk_done(usbd_xfer_handle xfer)
1578 1.3 augustss {
1579 1.218.6.5 macallan #ifdef DIAGNOSTIC
1580 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
1581 1.218.6.5 macallan #endif
1582 1.195 bouyer int isread =
1583 1.195 bouyer (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN);
1584 1.195 bouyer
1585 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
1586 1.218.6.2 jmcneill
1587 1.140 gson DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n",
1588 1.53 augustss xfer, xfer->actlen));
1589 1.195 bouyer usb_syncmem(&xfer->dmabuf, 0, xfer->length,
1590 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1591 1.3 augustss }
1592 1.3 augustss
1593 1.218.6.2 jmcneill Static void
1594 1.218.6.2 jmcneill ohci_rhsc_softint(void *arg)
1595 1.218.6.2 jmcneill {
1596 1.218.6.2 jmcneill ohci_softc_t *sc = arg;
1597 1.218.6.2 jmcneill
1598 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
1599 1.218.6.2 jmcneill
1600 1.218.6.2 jmcneill ohci_rhsc(sc, sc->sc_intrxfer);
1601 1.218.6.2 jmcneill
1602 1.218.6.2 jmcneill /* Do not allow RHSC interrupts > 1 per second */
1603 1.218.6.2 jmcneill callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1604 1.218.6.2 jmcneill
1605 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
1606 1.218.6.2 jmcneill }
1607 1.218.6.2 jmcneill
1608 1.3 augustss void
1609 1.91 augustss ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer)
1610 1.1 augustss {
1611 1.1 augustss usbd_pipe_handle pipe;
1612 1.1 augustss u_char *p;
1613 1.1 augustss int i, m;
1614 1.1 augustss int hstatus;
1615 1.1 augustss
1616 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
1617 1.218.6.2 jmcneill
1618 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1619 1.120 augustss DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n",
1620 1.53 augustss sc, xfer, hstatus));
1621 1.1 augustss
1622 1.53 augustss if (xfer == NULL) {
1623 1.1 augustss /* Just ignore the change. */
1624 1.1 augustss return;
1625 1.1 augustss }
1626 1.1 augustss
1627 1.53 augustss pipe = xfer->pipe;
1628 1.1 augustss
1629 1.123 augustss p = KERNADDR(&xfer->dmabuf, 0);
1630 1.53 augustss m = min(sc->sc_noport, xfer->length * 8 - 1);
1631 1.53 augustss memset(p, 0, xfer->length);
1632 1.1 augustss for (i = 1; i <= m; i++) {
1633 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1634 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1635 1.1 augustss p[i/8] |= 1 << (i%8);
1636 1.1 augustss }
1637 1.1 augustss DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
1638 1.53 augustss xfer->actlen = xfer->length;
1639 1.53 augustss xfer->status = USBD_NORMAL_COMPLETION;
1640 1.1 augustss
1641 1.53 augustss usb_transfer_complete(xfer);
1642 1.38 augustss }
1643 1.38 augustss
1644 1.38 augustss void
1645 1.179 christos ohci_root_intr_done(usbd_xfer_handle xfer)
1646 1.65 augustss {
1647 1.65 augustss }
1648 1.65 augustss
1649 1.65 augustss void
1650 1.179 christos ohci_root_ctrl_done(usbd_xfer_handle xfer)
1651 1.38 augustss {
1652 1.1 augustss }
1653 1.1 augustss
1654 1.1 augustss /*
1655 1.1 augustss * Wait here until controller claims to have an interrupt.
1656 1.1 augustss * Then call ohci_intr and return. Use timeout to avoid waiting
1657 1.1 augustss * too long.
1658 1.1 augustss */
1659 1.1 augustss void
1660 1.91 augustss ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer)
1661 1.1 augustss {
1662 1.163 augustss int timo;
1663 1.1 augustss u_int32_t intrs;
1664 1.1 augustss
1665 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
1666 1.218.6.2 jmcneill
1667 1.53 augustss xfer->status = USBD_IN_PROGRESS;
1668 1.163 augustss for (timo = xfer->timeout; timo >= 0; timo--) {
1669 1.20 augustss usb_delay_ms(&sc->sc_bus, 1);
1670 1.116 augustss if (sc->sc_dying)
1671 1.116 augustss break;
1672 1.1 augustss intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
1673 1.27 augustss DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs));
1674 1.52 augustss #ifdef OHCI_DEBUG
1675 1.1 augustss if (ohcidebug > 15)
1676 1.1 augustss ohci_dumpregs(sc);
1677 1.1 augustss #endif
1678 1.1 augustss if (intrs) {
1679 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1680 1.53 augustss ohci_intr1(sc);
1681 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1682 1.53 augustss if (xfer->status != USBD_IN_PROGRESS)
1683 1.1 augustss return;
1684 1.1 augustss }
1685 1.1 augustss }
1686 1.15 augustss
1687 1.15 augustss /* Timeout */
1688 1.1 augustss DPRINTF(("ohci_waitintr: timeout\n"));
1689 1.53 augustss xfer->status = USBD_TIMEOUT;
1690 1.53 augustss usb_transfer_complete(xfer);
1691 1.218.6.2 jmcneill
1692 1.15 augustss /* XXX should free TD */
1693 1.218.6.2 jmcneill
1694 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
1695 1.5 augustss }
1696 1.5 augustss
1697 1.5 augustss void
1698 1.91 augustss ohci_poll(struct usbd_bus *bus)
1699 1.5 augustss {
1700 1.190 drochner ohci_softc_t *sc = bus->hci_private;
1701 1.105 augustss #ifdef OHCI_DEBUG
1702 1.105 augustss static int last;
1703 1.105 augustss int new;
1704 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1705 1.105 augustss if (new != last) {
1706 1.105 augustss DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new));
1707 1.105 augustss last = new;
1708 1.105 augustss }
1709 1.105 augustss #endif
1710 1.5 augustss
1711 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1712 1.218.6.2 jmcneill if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1713 1.218.6.2 jmcneill mutex_spin_enter(&sc->sc_intr_lock);
1714 1.53 augustss ohci_intr1(sc);
1715 1.218.6.2 jmcneill mutex_spin_exit(&sc->sc_intr_lock);
1716 1.218.6.2 jmcneill }
1717 1.1 augustss }
1718 1.1 augustss
1719 1.1 augustss usbd_status
1720 1.91 augustss ohci_device_request(usbd_xfer_handle xfer)
1721 1.1 augustss {
1722 1.53 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
1723 1.53 augustss usb_device_request_t *req = &xfer->request;
1724 1.1 augustss usbd_device_handle dev = opipe->pipe.device;
1725 1.190 drochner ohci_softc_t *sc = dev->bus->hci_private;
1726 1.1 augustss int addr = dev->address;
1727 1.77 augustss ohci_soft_td_t *setup, *stat, *next, *tail;
1728 1.1 augustss ohci_soft_ed_t *sed;
1729 1.1 augustss int isread;
1730 1.1 augustss int len;
1731 1.53 augustss usbd_status err;
1732 1.218.6.2 jmcneill
1733 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
1734 1.1 augustss
1735 1.1 augustss isread = req->bmRequestType & UT_READ;
1736 1.1 augustss len = UGETW(req->wLength);
1737 1.1 augustss
1738 1.14 augustss DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, "
1739 1.14 augustss "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
1740 1.1 augustss req->bmRequestType, req->bRequest, UGETW(req->wValue),
1741 1.120 augustss UGETW(req->wIndex), len, addr,
1742 1.1 augustss opipe->pipe.endpoint->edesc->bEndpointAddress));
1743 1.1 augustss
1744 1.60 augustss setup = opipe->tail.td;
1745 1.1 augustss stat = ohci_alloc_std(sc);
1746 1.53 augustss if (stat == NULL) {
1747 1.53 augustss err = USBD_NOMEM;
1748 1.1 augustss goto bad1;
1749 1.1 augustss }
1750 1.1 augustss tail = ohci_alloc_std(sc);
1751 1.53 augustss if (tail == NULL) {
1752 1.53 augustss err = USBD_NOMEM;
1753 1.1 augustss goto bad2;
1754 1.1 augustss }
1755 1.55 augustss tail->xfer = NULL;
1756 1.1 augustss
1757 1.1 augustss sed = opipe->sed;
1758 1.1 augustss opipe->u.ctl.length = len;
1759 1.1 augustss
1760 1.148 mycroft /* Update device address and length since they may have changed
1761 1.148 mycroft during the setup of the control pipe in usbd_new_device(). */
1762 1.10 augustss /* XXX This only needs to be done once, but it's too early in open. */
1763 1.77 augustss /* XXXX Should not touch ED here! */
1764 1.195 bouyer
1765 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
1766 1.195 bouyer sizeof(sed->ed.ed_flags),
1767 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1768 1.168 augustss sed->ed.ed_flags = HTOO32(
1769 1.168 augustss (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
1770 1.16 augustss OHCI_ED_SET_FA(addr) |
1771 1.16 augustss OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize)));
1772 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
1773 1.195 bouyer sizeof(sed->ed.ed_flags),
1774 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1775 1.1 augustss
1776 1.77 augustss next = stat;
1777 1.77 augustss
1778 1.1 augustss /* Set up data transaction */
1779 1.1 augustss if (len != 0) {
1780 1.77 augustss ohci_soft_td_t *std = stat;
1781 1.77 augustss
1782 1.77 augustss err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
1783 1.77 augustss std, &stat);
1784 1.77 augustss stat = stat->nexttd; /* point at free TD */
1785 1.77 augustss if (err)
1786 1.1 augustss goto bad3;
1787 1.77 augustss /* Start toggle at 1 and then use the carried toggle. */
1788 1.168 augustss std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
1789 1.168 augustss std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
1790 1.195 bouyer usb_syncmem(&std->dma,
1791 1.195 bouyer std->offs + offsetof(ohci_td_t, td_flags),
1792 1.195 bouyer sizeof(std->td.td_flags),
1793 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1794 1.34 augustss }
1795 1.1 augustss
1796 1.123 augustss memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req);
1797 1.195 bouyer usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE);
1798 1.1 augustss
1799 1.168 augustss setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
1800 1.76 tsutsui OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1801 1.168 augustss setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0));
1802 1.1 augustss setup->nexttd = next;
1803 1.168 augustss setup->td.td_nexttd = HTOO32(next->physaddr);
1804 1.168 augustss setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1);
1805 1.77 augustss setup->len = 0;
1806 1.53 augustss setup->xfer = xfer;
1807 1.34 augustss setup->flags = 0;
1808 1.53 augustss xfer->hcpriv = setup;
1809 1.195 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
1810 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1811 1.1 augustss
1812 1.168 augustss stat->td.td_flags = HTOO32(
1813 1.77 augustss (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
1814 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1815 1.39 augustss stat->td.td_cbp = 0;
1816 1.1 augustss stat->nexttd = tail;
1817 1.168 augustss stat->td.td_nexttd = HTOO32(tail->physaddr);
1818 1.39 augustss stat->td.td_be = 0;
1819 1.77 augustss stat->flags = OHCI_CALL_DONE;
1820 1.1 augustss stat->len = 0;
1821 1.53 augustss stat->xfer = xfer;
1822 1.195 bouyer usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
1823 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1824 1.1 augustss
1825 1.52 augustss #ifdef OHCI_DEBUG
1826 1.1 augustss if (ohcidebug > 5) {
1827 1.41 augustss DPRINTF(("ohci_device_request:\n"));
1828 1.168 augustss ohci_dump_ed(sc, sed);
1829 1.168 augustss ohci_dump_tds(sc, setup);
1830 1.1 augustss }
1831 1.1 augustss #endif
1832 1.1 augustss
1833 1.1 augustss /* Insert ED in schedule */
1834 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
1835 1.195 bouyer usb_syncmem(&sed->dma,
1836 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_tailp),
1837 1.195 bouyer sizeof(sed->ed.ed_tailp),
1838 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1839 1.60 augustss opipe->tail.td = tail;
1840 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1841 1.53 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
1842 1.209 dyoung callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
1843 1.80 augustss ohci_timeout, xfer);
1844 1.15 augustss }
1845 1.1 augustss
1846 1.115 itojun #ifdef OHCI_DEBUG
1847 1.113 augustss if (ohcidebug > 20) {
1848 1.77 augustss delay(10000);
1849 1.41 augustss DPRINTF(("ohci_device_request: status=%x\n",
1850 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
1851 1.113 augustss ohci_dumpregs(sc);
1852 1.113 augustss printf("ctrl head:\n");
1853 1.168 augustss ohci_dump_ed(sc, sc->sc_ctrl_head);
1854 1.113 augustss printf("sed:\n");
1855 1.168 augustss ohci_dump_ed(sc, sed);
1856 1.168 augustss ohci_dump_tds(sc, setup);
1857 1.1 augustss }
1858 1.1 augustss #endif
1859 1.1 augustss
1860 1.1 augustss return (USBD_NORMAL_COMPLETION);
1861 1.1 augustss
1862 1.1 augustss bad3:
1863 1.1 augustss ohci_free_std(sc, tail);
1864 1.1 augustss bad2:
1865 1.1 augustss ohci_free_std(sc, stat);
1866 1.1 augustss bad1:
1867 1.53 augustss return (err);
1868 1.1 augustss }
1869 1.1 augustss
1870 1.1 augustss /*
1871 1.1 augustss * Add an ED to the schedule. Called at splusb().
1872 1.1 augustss */
1873 1.218.6.6 mrg Static void
1874 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1875 1.1 augustss {
1876 1.113 augustss DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head));
1877 1.113 augustss
1878 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1879 1.218.6.6 mrg
1880 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1881 1.195 bouyer sizeof(head->ed.ed_nexted),
1882 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1883 1.1 augustss sed->next = head->next;
1884 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1885 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1886 1.195 bouyer sizeof(sed->ed.ed_nexted),
1887 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1888 1.1 augustss head->next = sed;
1889 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1890 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1891 1.195 bouyer sizeof(head->ed.ed_nexted),
1892 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1893 1.1 augustss }
1894 1.1 augustss
1895 1.1 augustss /*
1896 1.3 augustss * Remove an ED from the schedule. Called at splusb().
1897 1.3 augustss */
1898 1.218.6.6 mrg Static void
1899 1.218.6.6 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1900 1.3 augustss {
1901 1.120 augustss ohci_soft_ed_t *p;
1902 1.3 augustss
1903 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1904 1.46 augustss
1905 1.3 augustss /* XXX */
1906 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1907 1.3 augustss ;
1908 1.55 augustss if (p == NULL)
1909 1.128 provos panic("ohci_rem_ed: ED not found");
1910 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1911 1.195 bouyer sizeof(sed->ed.ed_nexted),
1912 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1913 1.3 augustss p->next = sed->next;
1914 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1915 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1916 1.195 bouyer sizeof(p->ed.ed_nexted),
1917 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1918 1.3 augustss }
1919 1.3 augustss
1920 1.3 augustss /*
1921 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1922 1.1 augustss * the host controller. This queue is the processed by software.
1923 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1924 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1925 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1926 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1927 1.1 augustss * hash value.
1928 1.1 augustss */
1929 1.1 augustss
1930 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1931 1.1 augustss /* Called at splusb() */
1932 1.1 augustss void
1933 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1934 1.1 augustss {
1935 1.1 augustss int h = HASH(std->physaddr);
1936 1.1 augustss
1937 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1938 1.46 augustss
1939 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1940 1.1 augustss }
1941 1.1 augustss
1942 1.1 augustss /* Called at splusb() */
1943 1.1 augustss void
1944 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1945 1.1 augustss {
1946 1.218.6.6 mrg
1947 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1948 1.46 augustss
1949 1.1 augustss LIST_REMOVE(std, hnext);
1950 1.1 augustss }
1951 1.1 augustss
1952 1.1 augustss ohci_soft_td_t *
1953 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1954 1.1 augustss {
1955 1.1 augustss int h = HASH(a);
1956 1.1 augustss ohci_soft_td_t *std;
1957 1.1 augustss
1958 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1959 1.53 augustss std != NULL;
1960 1.1 augustss std = LIST_NEXT(std, hnext))
1961 1.1 augustss if (std->physaddr == a)
1962 1.1 augustss return (std);
1963 1.83 augustss return (NULL);
1964 1.83 augustss }
1965 1.83 augustss
1966 1.83 augustss /* Called at splusb() */
1967 1.83 augustss void
1968 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1969 1.83 augustss {
1970 1.83 augustss int h = HASH(sitd->physaddr);
1971 1.83 augustss
1972 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1973 1.83 augustss
1974 1.120 augustss DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n",
1975 1.83 augustss sitd, (u_long)sitd->physaddr));
1976 1.83 augustss
1977 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1978 1.83 augustss }
1979 1.83 augustss
1980 1.83 augustss /* Called at splusb() */
1981 1.83 augustss void
1982 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1983 1.83 augustss {
1984 1.218.6.6 mrg KASSERT(mutex_owned(&sc->sc_lock));
1985 1.83 augustss
1986 1.120 augustss DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n",
1987 1.83 augustss sitd, (u_long)sitd->physaddr));
1988 1.83 augustss
1989 1.83 augustss LIST_REMOVE(sitd, hnext);
1990 1.83 augustss }
1991 1.83 augustss
1992 1.83 augustss ohci_soft_itd_t *
1993 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1994 1.83 augustss {
1995 1.83 augustss int h = HASH(a);
1996 1.83 augustss ohci_soft_itd_t *sitd;
1997 1.83 augustss
1998 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1999 1.83 augustss sitd != NULL;
2000 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
2001 1.83 augustss if (sitd->physaddr == a)
2002 1.83 augustss return (sitd);
2003 1.83 augustss return (NULL);
2004 1.1 augustss }
2005 1.1 augustss
2006 1.1 augustss void
2007 1.91 augustss ohci_timeout(void *addr)
2008 1.1 augustss {
2009 1.114 augustss struct ohci_xfer *oxfer = addr;
2010 1.116 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe;
2011 1.190 drochner ohci_softc_t *sc = opipe->pipe.device->bus->hci_private;
2012 1.114 augustss
2013 1.114 augustss DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer));
2014 1.114 augustss
2015 1.116 augustss if (sc->sc_dying) {
2016 1.116 augustss ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT);
2017 1.116 augustss return;
2018 1.116 augustss }
2019 1.116 augustss
2020 1.114 augustss /* Execute the abort in a process context. */
2021 1.215 tsutsui usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr);
2022 1.178 joerg usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task,
2023 1.178 joerg USB_TASKQ_HC);
2024 1.114 augustss }
2025 1.114 augustss
2026 1.114 augustss void
2027 1.114 augustss ohci_timeout_task(void *addr)
2028 1.114 augustss {
2029 1.53 augustss usbd_xfer_handle xfer = addr;
2030 1.1 augustss
2031 1.114 augustss DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer));
2032 1.45 augustss
2033 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
2034 1.1 augustss }
2035 1.1 augustss
2036 1.52 augustss #ifdef OHCI_DEBUG
2037 1.1 augustss void
2038 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
2039 1.1 augustss {
2040 1.1 augustss for (; std; std = std->nexttd)
2041 1.168 augustss ohci_dump_td(sc, std);
2042 1.1 augustss }
2043 1.1 augustss
2044 1.1 augustss void
2045 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
2046 1.1 augustss {
2047 1.92 tv char sbuf[128];
2048 1.92 tv
2049 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2050 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2051 1.197 christos snprintb(sbuf, sizeof(sbuf),
2052 1.197 christos "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
2053 1.197 christos (u_int32_t)O32TOH(std->td.td_flags));
2054 1.107 augustss printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx "
2055 1.120 augustss "nexttd=0x%08lx be=0x%08lx\n",
2056 1.107 augustss std, (u_long)std->physaddr, sbuf,
2057 1.168 augustss OHCI_TD_GET_DI(O32TOH(std->td.td_flags)),
2058 1.168 augustss OHCI_TD_GET_EC(O32TOH(std->td.td_flags)),
2059 1.168 augustss OHCI_TD_GET_CC(O32TOH(std->td.td_flags)),
2060 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
2061 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
2062 1.168 augustss (u_long)O32TOH(std->td.td_be));
2063 1.1 augustss }
2064 1.1 augustss
2065 1.1 augustss void
2066 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2067 1.83 augustss {
2068 1.83 augustss int i;
2069 1.83 augustss
2070 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
2071 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2072 1.107 augustss printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n"
2073 1.120 augustss "bp0=0x%08lx next=0x%08lx be=0x%08lx\n",
2074 1.107 augustss sitd, (u_long)sitd->physaddr,
2075 1.168 augustss OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)),
2076 1.168 augustss OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)),
2077 1.168 augustss OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)),
2078 1.168 augustss OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)),
2079 1.168 augustss (u_long)O32TOH(sitd->itd.itd_bp0),
2080 1.168 augustss (u_long)O32TOH(sitd->itd.itd_nextitd),
2081 1.168 augustss (u_long)O32TOH(sitd->itd.itd_be));
2082 1.83 augustss for (i = 0; i < OHCI_ITD_NOFFSET; i++)
2083 1.107 augustss printf("offs[%d]=0x%04x ", i,
2084 1.168 augustss (u_int)O16TOH(sitd->itd.itd_offset[i]));
2085 1.107 augustss printf("\n");
2086 1.83 augustss }
2087 1.83 augustss
2088 1.83 augustss void
2089 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2090 1.83 augustss {
2091 1.83 augustss for (; sitd; sitd = sitd->nextitd)
2092 1.168 augustss ohci_dump_itd(sc, sitd);
2093 1.83 augustss }
2094 1.83 augustss
2095 1.83 augustss void
2096 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2097 1.1 augustss {
2098 1.92 tv char sbuf[128], sbuf2[128];
2099 1.92 tv
2100 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2101 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2102 1.197 christos snprintb(sbuf, sizeof(sbuf),
2103 1.197 christos "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO",
2104 1.197 christos (u_int32_t)O32TOH(sed->ed.ed_flags));
2105 1.197 christos snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY",
2106 1.197 christos (u_int32_t)O32TOH(sed->ed.ed_headp));
2107 1.92 tv
2108 1.107 augustss printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx "
2109 1.92 tv "headflags=%s headp=0x%08lx nexted=0x%08lx\n",
2110 1.120 augustss sed, (u_long)sed->physaddr,
2111 1.168 augustss OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)),
2112 1.168 augustss OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)),
2113 1.168 augustss OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf,
2114 1.168 augustss (u_long)O32TOH(sed->ed.ed_tailp), sbuf2,
2115 1.168 augustss (u_long)O32TOH(sed->ed.ed_headp),
2116 1.168 augustss (u_long)O32TOH(sed->ed.ed_nexted));
2117 1.1 augustss }
2118 1.1 augustss #endif
2119 1.1 augustss
2120 1.1 augustss usbd_status
2121 1.91 augustss ohci_open(usbd_pipe_handle pipe)
2122 1.1 augustss {
2123 1.1 augustss usbd_device_handle dev = pipe->device;
2124 1.190 drochner ohci_softc_t *sc = dev->bus->hci_private;
2125 1.1 augustss usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
2126 1.1 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2127 1.1 augustss u_int8_t addr = dev->address;
2128 1.60 augustss u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2129 1.1 augustss ohci_soft_ed_t *sed;
2130 1.1 augustss ohci_soft_td_t *std;
2131 1.60 augustss ohci_soft_itd_t *sitd;
2132 1.60 augustss ohci_physaddr_t tdphys;
2133 1.60 augustss u_int32_t fmt;
2134 1.218.6.2 jmcneill usbd_status err = USBD_NOMEM;
2135 1.64 augustss int ival;
2136 1.1 augustss
2137 1.1 augustss DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
2138 1.1 augustss pipe, addr, ed->bEndpointAddress, sc->sc_addr));
2139 1.81 augustss
2140 1.218.6.2 jmcneill if (sc->sc_dying) {
2141 1.218.6.2 jmcneill err = USBD_IOERROR;
2142 1.218.6.2 jmcneill goto bad0;
2143 1.218.6.2 jmcneill }
2144 1.116 augustss
2145 1.90 thorpej std = NULL;
2146 1.90 thorpej sed = NULL;
2147 1.90 thorpej
2148 1.1 augustss if (addr == sc->sc_addr) {
2149 1.1 augustss switch (ed->bEndpointAddress) {
2150 1.1 augustss case USB_CONTROL_ENDPOINT:
2151 1.1 augustss pipe->methods = &ohci_root_ctrl_methods;
2152 1.1 augustss break;
2153 1.40 augustss case UE_DIR_IN | OHCI_INTR_ENDPT:
2154 1.1 augustss pipe->methods = &ohci_root_intr_methods;
2155 1.1 augustss break;
2156 1.1 augustss default:
2157 1.218.6.2 jmcneill err = USBD_INVAL;
2158 1.218.6.2 jmcneill goto bad0;
2159 1.1 augustss }
2160 1.1 augustss } else {
2161 1.1 augustss sed = ohci_alloc_sed(sc);
2162 1.53 augustss if (sed == NULL)
2163 1.1 augustss goto bad0;
2164 1.1 augustss opipe->sed = sed;
2165 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2166 1.218.6.7 mrg mutex_enter(&sc->sc_lock);
2167 1.60 augustss sitd = ohci_alloc_sitd(sc);
2168 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
2169 1.127 augustss if (sitd == NULL)
2170 1.60 augustss goto bad1;
2171 1.60 augustss opipe->tail.itd = sitd;
2172 1.76 tsutsui tdphys = sitd->physaddr;
2173 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2174 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2175 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2176 1.83 augustss else
2177 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2178 1.60 augustss } else {
2179 1.218.6.7 mrg mutex_enter(&sc->sc_lock);
2180 1.60 augustss std = ohci_alloc_std(sc);
2181 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
2182 1.127 augustss if (std == NULL)
2183 1.60 augustss goto bad1;
2184 1.60 augustss opipe->tail.td = std;
2185 1.76 tsutsui tdphys = std->physaddr;
2186 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2187 1.60 augustss }
2188 1.168 augustss sed->ed.ed_flags = HTOO32(
2189 1.120 augustss OHCI_ED_SET_FA(addr) |
2190 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2191 1.109 augustss (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2192 1.109 augustss fmt |
2193 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2194 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2195 1.214 jakllsch (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0));
2196 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2197 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2198 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2199 1.1 augustss
2200 1.60 augustss switch (xfertype) {
2201 1.1 augustss case UE_CONTROL:
2202 1.1 augustss pipe->methods = &ohci_device_ctrl_methods;
2203 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2204 1.120 augustss sizeof(usb_device_request_t),
2205 1.53 augustss 0, &opipe->u.ctl.reqdma);
2206 1.53 augustss if (err)
2207 1.1 augustss goto bad;
2208 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2209 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2210 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2211 1.1 augustss break;
2212 1.1 augustss case UE_INTERRUPT:
2213 1.1 augustss pipe->methods = &ohci_device_intr_methods;
2214 1.64 augustss ival = pipe->interval;
2215 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2216 1.64 augustss ival = ed->bInterval;
2217 1.64 augustss return (ohci_device_setintr(sc, opipe, ival));
2218 1.1 augustss case UE_ISOCHRONOUS:
2219 1.60 augustss pipe->methods = &ohci_device_isoc_methods;
2220 1.60 augustss return (ohci_setup_isoc(pipe));
2221 1.1 augustss case UE_BULK:
2222 1.3 augustss pipe->methods = &ohci_device_bulk_methods;
2223 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2224 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2225 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2226 1.3 augustss break;
2227 1.1 augustss }
2228 1.1 augustss }
2229 1.218.6.2 jmcneill
2230 1.218.6.2 jmcneill return USBD_NORMAL_COMPLETION;
2231 1.1 augustss
2232 1.1 augustss bad:
2233 1.90 thorpej if (std != NULL)
2234 1.90 thorpej ohci_free_std(sc, std);
2235 1.1 augustss bad1:
2236 1.90 thorpej if (sed != NULL)
2237 1.90 thorpej ohci_free_sed(sc, sed);
2238 1.1 augustss bad0:
2239 1.218.6.2 jmcneill return err;
2240 1.120 augustss
2241 1.1 augustss }
2242 1.1 augustss
2243 1.1 augustss /*
2244 1.34 augustss * Close a reqular pipe.
2245 1.34 augustss * Assumes that there are no pending transactions.
2246 1.34 augustss */
2247 1.34 augustss void
2248 1.91 augustss ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head)
2249 1.34 augustss {
2250 1.34 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2251 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
2252 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2253 1.34 augustss
2254 1.218.6.2 jmcneill KASSERT(mutex_owned(&sc->sc_lock));
2255 1.218.6.2 jmcneill
2256 1.34 augustss #ifdef DIAGNOSTIC
2257 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2258 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2259 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2260 1.34 augustss ohci_soft_td_t *std;
2261 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2262 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2263 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2264 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2265 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2266 1.34 augustss pipe, std);
2267 1.107 augustss #ifdef USB_DEBUG
2268 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2269 1.107 augustss #endif
2270 1.106 augustss #ifdef OHCI_DEBUG
2271 1.168 augustss ohci_dump_ed(sc, sed);
2272 1.106 augustss if (std)
2273 1.168 augustss ohci_dump_td(sc, std);
2274 1.106 augustss #endif
2275 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2276 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2277 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2278 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2279 1.34 augustss }
2280 1.34 augustss #endif
2281 1.218.6.6 mrg ohci_rem_ed(sc, sed, head);
2282 1.133 toshii /* Make sure the host controller is not touching this ED */
2283 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2284 1.214 jakllsch pipe->endpoint->datatoggle =
2285 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2286 1.34 augustss ohci_free_sed(sc, opipe->sed);
2287 1.34 augustss }
2288 1.34 augustss
2289 1.120 augustss /*
2290 1.34 augustss * Abort a device request.
2291 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2292 1.34 augustss * will be removed from the hardware scheduling and that the callback
2293 1.34 augustss * for it will be called with USBD_CANCELLED status.
2294 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2295 1.34 augustss * have happened since the hardware runs concurrently.
2296 1.34 augustss * If the transaction has already happened we rely on the ordinary
2297 1.34 augustss * interrupt processing to process it.
2298 1.34 augustss */
2299 1.34 augustss void
2300 1.91 augustss ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2301 1.34 augustss {
2302 1.53 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
2303 1.190 drochner ohci_softc_t *sc = opipe->pipe.device->bus->hci_private;
2304 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2305 1.106 augustss ohci_soft_td_t *p, *n;
2306 1.106 augustss ohci_physaddr_t headp;
2307 1.218.6.2 jmcneill int hit;
2308 1.159 augustss int wake;
2309 1.34 augustss
2310 1.106 augustss DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed));
2311 1.34 augustss
2312 1.116 augustss if (sc->sc_dying) {
2313 1.116 augustss /* If we're dying, just do the software part. */
2314 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2315 1.116 augustss xfer->status = status; /* make software ignore it */
2316 1.218.6.2 jmcneill callout_halt(&xfer->timeout_handle, &sc->sc_lock);
2317 1.116 augustss usb_transfer_complete(xfer);
2318 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2319 1.170 christos return;
2320 1.116 augustss }
2321 1.116 augustss
2322 1.106 augustss if (xfer->device->bus->intr_context || !curproc)
2323 1.128 provos panic("ohci_abort_xfer: not in process context");
2324 1.34 augustss
2325 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2326 1.218.6.2 jmcneill
2327 1.106 augustss /*
2328 1.159 augustss * If an abort is already in progress then just wait for it to
2329 1.159 augustss * complete and return.
2330 1.159 augustss */
2331 1.159 augustss if (xfer->hcflags & UXFER_ABORTING) {
2332 1.159 augustss DPRINTFN(2, ("ohci_abort_xfer: already aborting\n"));
2333 1.159 augustss #ifdef DIAGNOSTIC
2334 1.159 augustss if (status == USBD_TIMEOUT)
2335 1.159 augustss printf("0hci_abort_xfer: TIMEOUT while aborting\n");
2336 1.159 augustss #endif
2337 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2338 1.159 augustss xfer->status = status;
2339 1.159 augustss DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n"));
2340 1.159 augustss xfer->hcflags |= UXFER_ABORTWAIT;
2341 1.159 augustss while (xfer->hcflags & UXFER_ABORTING)
2342 1.218.6.2 jmcneill cv_wait(&xfer->hccv, &sc->sc_lock);
2343 1.218.6.2 jmcneill goto done;
2344 1.159 augustss return;
2345 1.159 augustss }
2346 1.159 augustss xfer->hcflags |= UXFER_ABORTING;
2347 1.159 augustss
2348 1.159 augustss /*
2349 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2350 1.106 augustss */
2351 1.106 augustss xfer->status = status; /* make software ignore it */
2352 1.209 dyoung callout_stop(&xfer->timeout_handle);
2353 1.54 augustss DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed));
2354 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2355 1.195 bouyer sizeof(sed->ed.ed_flags),
2356 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2357 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2358 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2359 1.195 bouyer sizeof(sed->ed.ed_flags),
2360 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2361 1.34 augustss
2362 1.120 augustss /*
2363 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2364 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2365 1.106 augustss * has run.
2366 1.106 augustss */
2367 1.119 augustss usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */
2368 1.119 augustss sc->sc_softwake = 1;
2369 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2370 1.218.6.2 jmcneill cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2371 1.119 augustss
2372 1.120 augustss /*
2373 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2374 1.106 augustss * The complication here is that the hardware may have executed
2375 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2376 1.106 augustss * the TDs of this xfer we check if the hardware points to
2377 1.106 augustss * any of them.
2378 1.106 augustss */
2379 1.53 augustss p = xfer->hcpriv;
2380 1.34 augustss #ifdef DIAGNOSTIC
2381 1.55 augustss if (p == NULL) {
2382 1.159 augustss xfer->hcflags &= ~UXFER_ABORTING; /* XXX */
2383 1.106 augustss printf("ohci_abort_xfer: hcpriv is NULL\n");
2384 1.218.6.2 jmcneill goto done;
2385 1.38 augustss }
2386 1.34 augustss #endif
2387 1.106 augustss #ifdef OHCI_DEBUG
2388 1.106 augustss if (ohcidebug > 1) {
2389 1.106 augustss DPRINTF(("ohci_abort_xfer: sed=\n"));
2390 1.168 augustss ohci_dump_ed(sc, sed);
2391 1.168 augustss ohci_dump_tds(sc, p);
2392 1.106 augustss }
2393 1.106 augustss #endif
2394 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2395 1.106 augustss hit = 0;
2396 1.53 augustss for (; p->xfer == xfer; p = n) {
2397 1.106 augustss hit |= headp == p->physaddr;
2398 1.38 augustss n = p->nexttd;
2399 1.38 augustss ohci_free_std(sc, p);
2400 1.34 augustss }
2401 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2402 1.106 augustss if (hit) {
2403 1.150 mycroft DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n",
2404 1.168 augustss (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp)));
2405 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2406 1.195 bouyer usb_syncmem(&sed->dma,
2407 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2408 1.195 bouyer sizeof(sed->ed.ed_headp),
2409 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2410 1.106 augustss } else {
2411 1.106 augustss DPRINTFN(1,("ohci_abort_xfer: no hit\n"));
2412 1.106 augustss }
2413 1.34 augustss
2414 1.106 augustss /*
2415 1.106 augustss * Step 4: Turn on hardware again.
2416 1.106 augustss */
2417 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2418 1.195 bouyer sizeof(sed->ed.ed_flags),
2419 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2420 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2421 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2422 1.195 bouyer sizeof(sed->ed.ed_flags),
2423 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2424 1.38 augustss
2425 1.106 augustss /*
2426 1.106 augustss * Step 5: Execute callback.
2427 1.106 augustss */
2428 1.159 augustss wake = xfer->hcflags & UXFER_ABORTWAIT;
2429 1.159 augustss xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2430 1.53 augustss usb_transfer_complete(xfer);
2431 1.159 augustss if (wake)
2432 1.218.6.2 jmcneill cv_broadcast(&xfer->hccv);
2433 1.38 augustss
2434 1.218.6.2 jmcneill done:
2435 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2436 1.34 augustss }
2437 1.34 augustss
2438 1.34 augustss /*
2439 1.1 augustss * Data structures and routines to emulate the root hub.
2440 1.1 augustss */
2441 1.82 augustss Static usb_device_descriptor_t ohci_devd = {
2442 1.1 augustss USB_DEVICE_DESCRIPTOR_SIZE,
2443 1.1 augustss UDESC_DEVICE, /* type */
2444 1.1 augustss {0x00, 0x01}, /* USB version */
2445 1.74 augustss UDCLASS_HUB, /* class */
2446 1.74 augustss UDSUBCLASS_HUB, /* subclass */
2447 1.202 uebayasi UDPROTO_FSHUB, /* protocol */
2448 1.1 augustss 64, /* max packet */
2449 1.1 augustss {0},{0},{0x00,0x01}, /* device id */
2450 1.1 augustss 1,2,0, /* string indicies */
2451 1.1 augustss 1 /* # of configurations */
2452 1.1 augustss };
2453 1.1 augustss
2454 1.182 drochner Static const usb_config_descriptor_t ohci_confd = {
2455 1.1 augustss USB_CONFIG_DESCRIPTOR_SIZE,
2456 1.1 augustss UDESC_CONFIG,
2457 1.1 augustss {USB_CONFIG_DESCRIPTOR_SIZE +
2458 1.1 augustss USB_INTERFACE_DESCRIPTOR_SIZE +
2459 1.1 augustss USB_ENDPOINT_DESCRIPTOR_SIZE},
2460 1.1 augustss 1,
2461 1.1 augustss 1,
2462 1.1 augustss 0,
2463 1.180 drochner UC_ATTR_MBO | UC_SELF_POWERED,
2464 1.1 augustss 0 /* max power */
2465 1.1 augustss };
2466 1.1 augustss
2467 1.182 drochner Static const usb_interface_descriptor_t ohci_ifcd = {
2468 1.1 augustss USB_INTERFACE_DESCRIPTOR_SIZE,
2469 1.1 augustss UDESC_INTERFACE,
2470 1.1 augustss 0,
2471 1.1 augustss 0,
2472 1.1 augustss 1,
2473 1.74 augustss UICLASS_HUB,
2474 1.74 augustss UISUBCLASS_HUB,
2475 1.109 augustss UIPROTO_FSHUB,
2476 1.1 augustss 0
2477 1.1 augustss };
2478 1.1 augustss
2479 1.182 drochner Static const usb_endpoint_descriptor_t ohci_endpd = {
2480 1.175 christos .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE,
2481 1.175 christos .bDescriptorType = UDESC_ENDPOINT,
2482 1.175 christos .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT,
2483 1.175 christos .bmAttributes = UE_INTERRUPT,
2484 1.175 christos .wMaxPacketSize = {8, 0}, /* max packet */
2485 1.175 christos .bInterval = 255,
2486 1.1 augustss };
2487 1.1 augustss
2488 1.182 drochner Static const usb_hub_descriptor_t ohci_hubd = {
2489 1.175 christos .bDescLength = USB_HUB_DESCRIPTOR_SIZE,
2490 1.175 christos .bDescriptorType = UDESC_HUB,
2491 1.1 augustss };
2492 1.1 augustss
2493 1.1 augustss /*
2494 1.1 augustss * Simulate a hardware hub by handling all the necessary requests.
2495 1.1 augustss */
2496 1.82 augustss Static usbd_status
2497 1.91 augustss ohci_root_ctrl_transfer(usbd_xfer_handle xfer)
2498 1.1 augustss {
2499 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2500 1.53 augustss usbd_status err;
2501 1.17 augustss
2502 1.46 augustss /* Insert last in queue. */
2503 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2504 1.53 augustss err = usb_insert_transfer(xfer);
2505 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2506 1.53 augustss if (err)
2507 1.53 augustss return (err);
2508 1.46 augustss
2509 1.46 augustss /* Pipe isn't running, start first */
2510 1.53 augustss return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2511 1.17 augustss }
2512 1.17 augustss
2513 1.82 augustss Static usbd_status
2514 1.91 augustss ohci_root_ctrl_start(usbd_xfer_handle xfer)
2515 1.17 augustss {
2516 1.190 drochner ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2517 1.1 augustss usb_device_request_t *req;
2518 1.52 augustss void *buf = NULL;
2519 1.1 augustss int port, i;
2520 1.218.6.2 jmcneill int len, value, index, l, totlen = 0;
2521 1.1 augustss usb_port_status_t ps;
2522 1.1 augustss usb_hub_descriptor_t hubd;
2523 1.53 augustss usbd_status err;
2524 1.1 augustss u_int32_t v;
2525 1.1 augustss
2526 1.83 augustss if (sc->sc_dying)
2527 1.83 augustss return (USBD_IOERROR);
2528 1.83 augustss
2529 1.42 augustss #ifdef DIAGNOSTIC
2530 1.53 augustss if (!(xfer->rqflags & URQ_REQUEST))
2531 1.1 augustss /* XXX panic */
2532 1.1 augustss return (USBD_INVAL);
2533 1.42 augustss #endif
2534 1.53 augustss req = &xfer->request;
2535 1.1 augustss
2536 1.120 augustss DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
2537 1.1 augustss req->bmRequestType, req->bRequest));
2538 1.1 augustss
2539 1.1 augustss len = UGETW(req->wLength);
2540 1.1 augustss value = UGETW(req->wValue);
2541 1.1 augustss index = UGETW(req->wIndex);
2542 1.43 augustss
2543 1.43 augustss if (len != 0)
2544 1.123 augustss buf = KERNADDR(&xfer->dmabuf, 0);
2545 1.43 augustss
2546 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2547 1.1 augustss switch(C(req->bRequest, req->bmRequestType)) {
2548 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
2549 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
2550 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
2551 1.120 augustss /*
2552 1.15 augustss * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
2553 1.1 augustss * for the integrated root hub.
2554 1.1 augustss */
2555 1.1 augustss break;
2556 1.1 augustss case C(UR_GET_CONFIG, UT_READ_DEVICE):
2557 1.1 augustss if (len > 0) {
2558 1.1 augustss *(u_int8_t *)buf = sc->sc_conf;
2559 1.1 augustss totlen = 1;
2560 1.1 augustss }
2561 1.1 augustss break;
2562 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2563 1.1 augustss DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
2564 1.171 christos if (len == 0)
2565 1.171 christos break;
2566 1.1 augustss switch(value >> 8) {
2567 1.1 augustss case UDESC_DEVICE:
2568 1.1 augustss if ((value & 0xff) != 0) {
2569 1.53 augustss err = USBD_IOERROR;
2570 1.1 augustss goto ret;
2571 1.1 augustss }
2572 1.1 augustss totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
2573 1.29 augustss USETW(ohci_devd.idVendor, sc->sc_id_vendor);
2574 1.1 augustss memcpy(buf, &ohci_devd, l);
2575 1.1 augustss break;
2576 1.1 augustss case UDESC_CONFIG:
2577 1.1 augustss if ((value & 0xff) != 0) {
2578 1.53 augustss err = USBD_IOERROR;
2579 1.1 augustss goto ret;
2580 1.1 augustss }
2581 1.1 augustss totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
2582 1.1 augustss memcpy(buf, &ohci_confd, l);
2583 1.1 augustss buf = (char *)buf + l;
2584 1.1 augustss len -= l;
2585 1.1 augustss l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
2586 1.1 augustss totlen += l;
2587 1.1 augustss memcpy(buf, &ohci_ifcd, l);
2588 1.1 augustss buf = (char *)buf + l;
2589 1.1 augustss len -= l;
2590 1.1 augustss l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
2591 1.1 augustss totlen += l;
2592 1.1 augustss memcpy(buf, &ohci_endpd, l);
2593 1.1 augustss break;
2594 1.1 augustss case UDESC_STRING:
2595 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2596 1.1 augustss switch (value & 0xff) {
2597 1.152 augustss case 0: /* Language table */
2598 1.186 drochner totlen = usb_makelangtbl(sd, len);
2599 1.152 augustss break;
2600 1.1 augustss case 1: /* Vendor */
2601 1.186 drochner totlen = usb_makestrdesc(sd, len,
2602 1.186 drochner sc->sc_vendor);
2603 1.1 augustss break;
2604 1.1 augustss case 2: /* Product */
2605 1.186 drochner totlen = usb_makestrdesc(sd, len,
2606 1.186 drochner "OHCI root hub");
2607 1.1 augustss break;
2608 1.1 augustss }
2609 1.186 drochner #undef sd
2610 1.1 augustss break;
2611 1.1 augustss default:
2612 1.53 augustss err = USBD_IOERROR;
2613 1.1 augustss goto ret;
2614 1.1 augustss }
2615 1.1 augustss break;
2616 1.1 augustss case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
2617 1.1 augustss if (len > 0) {
2618 1.1 augustss *(u_int8_t *)buf = 0;
2619 1.1 augustss totlen = 1;
2620 1.1 augustss }
2621 1.1 augustss break;
2622 1.1 augustss case C(UR_GET_STATUS, UT_READ_DEVICE):
2623 1.1 augustss if (len > 1) {
2624 1.1 augustss USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
2625 1.1 augustss totlen = 2;
2626 1.1 augustss }
2627 1.1 augustss break;
2628 1.1 augustss case C(UR_GET_STATUS, UT_READ_INTERFACE):
2629 1.1 augustss case C(UR_GET_STATUS, UT_READ_ENDPOINT):
2630 1.1 augustss if (len > 1) {
2631 1.1 augustss USETW(((usb_status_t *)buf)->wStatus, 0);
2632 1.1 augustss totlen = 2;
2633 1.1 augustss }
2634 1.1 augustss break;
2635 1.1 augustss case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
2636 1.1 augustss if (value >= USB_MAX_DEVICES) {
2637 1.53 augustss err = USBD_IOERROR;
2638 1.1 augustss goto ret;
2639 1.1 augustss }
2640 1.1 augustss sc->sc_addr = value;
2641 1.1 augustss break;
2642 1.1 augustss case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
2643 1.1 augustss if (value != 0 && value != 1) {
2644 1.53 augustss err = USBD_IOERROR;
2645 1.1 augustss goto ret;
2646 1.1 augustss }
2647 1.1 augustss sc->sc_conf = value;
2648 1.1 augustss break;
2649 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
2650 1.1 augustss break;
2651 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
2652 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
2653 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
2654 1.53 augustss err = USBD_IOERROR;
2655 1.1 augustss goto ret;
2656 1.1 augustss case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
2657 1.1 augustss break;
2658 1.1 augustss case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
2659 1.1 augustss break;
2660 1.1 augustss /* Hub requests */
2661 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2662 1.1 augustss break;
2663 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2664 1.14 augustss DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
2665 1.14 augustss "port=%d feature=%d\n",
2666 1.1 augustss index, value));
2667 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2668 1.53 augustss err = USBD_IOERROR;
2669 1.1 augustss goto ret;
2670 1.1 augustss }
2671 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2672 1.1 augustss switch(value) {
2673 1.1 augustss case UHF_PORT_ENABLE:
2674 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2675 1.1 augustss break;
2676 1.1 augustss case UHF_PORT_SUSPEND:
2677 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2678 1.1 augustss break;
2679 1.1 augustss case UHF_PORT_POWER:
2680 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2681 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2682 1.1 augustss break;
2683 1.1 augustss case UHF_C_PORT_CONNECTION:
2684 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2685 1.1 augustss break;
2686 1.1 augustss case UHF_C_PORT_ENABLE:
2687 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2688 1.1 augustss break;
2689 1.1 augustss case UHF_C_PORT_SUSPEND:
2690 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2691 1.1 augustss break;
2692 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2693 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2694 1.1 augustss break;
2695 1.1 augustss case UHF_C_PORT_RESET:
2696 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2697 1.1 augustss break;
2698 1.1 augustss default:
2699 1.53 augustss err = USBD_IOERROR;
2700 1.1 augustss goto ret;
2701 1.1 augustss }
2702 1.1 augustss switch(value) {
2703 1.1 augustss case UHF_C_PORT_CONNECTION:
2704 1.1 augustss case UHF_C_PORT_ENABLE:
2705 1.1 augustss case UHF_C_PORT_SUSPEND:
2706 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2707 1.1 augustss case UHF_C_PORT_RESET:
2708 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2709 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2710 1.157 mycroft ohci_rhsc_enable(sc);
2711 1.1 augustss break;
2712 1.1 augustss default:
2713 1.1 augustss break;
2714 1.1 augustss }
2715 1.1 augustss break;
2716 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2717 1.171 christos if (len == 0)
2718 1.171 christos break;
2719 1.146 toshii if ((value & 0xff) != 0) {
2720 1.53 augustss err = USBD_IOERROR;
2721 1.1 augustss goto ret;
2722 1.1 augustss }
2723 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2724 1.1 augustss hubd = ohci_hubd;
2725 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2726 1.15 augustss USETW(hubd.wHubCharacteristics,
2727 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2728 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2729 1.1 augustss /* XXX overcurrent */
2730 1.1 augustss );
2731 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2732 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2733 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2734 1.15 augustss hubd.DeviceRemovable[i++] = (u_int8_t)v;
2735 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2736 1.1 augustss l = min(len, hubd.bDescLength);
2737 1.1 augustss totlen = l;
2738 1.1 augustss memcpy(buf, &hubd, l);
2739 1.1 augustss break;
2740 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2741 1.1 augustss if (len != 4) {
2742 1.53 augustss err = USBD_IOERROR;
2743 1.1 augustss goto ret;
2744 1.1 augustss }
2745 1.1 augustss memset(buf, 0, len); /* ? XXX */
2746 1.1 augustss totlen = len;
2747 1.1 augustss break;
2748 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2749 1.1 augustss DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
2750 1.1 augustss index));
2751 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2752 1.53 augustss err = USBD_IOERROR;
2753 1.1 augustss goto ret;
2754 1.1 augustss }
2755 1.1 augustss if (len != 4) {
2756 1.53 augustss err = USBD_IOERROR;
2757 1.1 augustss goto ret;
2758 1.1 augustss }
2759 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2760 1.1 augustss DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
2761 1.1 augustss v));
2762 1.1 augustss USETW(ps.wPortStatus, v);
2763 1.1 augustss USETW(ps.wPortChange, v >> 16);
2764 1.1 augustss l = min(len, sizeof ps);
2765 1.1 augustss memcpy(buf, &ps, l);
2766 1.1 augustss totlen = l;
2767 1.1 augustss break;
2768 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2769 1.53 augustss err = USBD_IOERROR;
2770 1.1 augustss goto ret;
2771 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2772 1.1 augustss break;
2773 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2774 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2775 1.53 augustss err = USBD_IOERROR;
2776 1.1 augustss goto ret;
2777 1.1 augustss }
2778 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2779 1.1 augustss switch(value) {
2780 1.1 augustss case UHF_PORT_ENABLE:
2781 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2782 1.1 augustss break;
2783 1.1 augustss case UHF_PORT_SUSPEND:
2784 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2785 1.1 augustss break;
2786 1.1 augustss case UHF_PORT_RESET:
2787 1.14 augustss DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n",
2788 1.14 augustss index));
2789 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2790 1.110 augustss for (i = 0; i < 5; i++) {
2791 1.110 augustss usb_delay_ms(&sc->sc_bus,
2792 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2793 1.116 augustss if (sc->sc_dying) {
2794 1.116 augustss err = USBD_IOERROR;
2795 1.116 augustss goto ret;
2796 1.116 augustss }
2797 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2798 1.1 augustss break;
2799 1.1 augustss }
2800 1.1 augustss DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
2801 1.1 augustss index, OREAD4(sc, port)));
2802 1.1 augustss break;
2803 1.1 augustss case UHF_PORT_POWER:
2804 1.14 augustss DPRINTFN(2,("ohci_root_ctrl_transfer: set port power "
2805 1.14 augustss "%d\n", index));
2806 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2807 1.1 augustss break;
2808 1.1 augustss default:
2809 1.53 augustss err = USBD_IOERROR;
2810 1.1 augustss goto ret;
2811 1.1 augustss }
2812 1.1 augustss break;
2813 1.1 augustss default:
2814 1.53 augustss err = USBD_IOERROR;
2815 1.1 augustss goto ret;
2816 1.1 augustss }
2817 1.53 augustss xfer->actlen = totlen;
2818 1.53 augustss err = USBD_NORMAL_COMPLETION;
2819 1.1 augustss ret:
2820 1.53 augustss xfer->status = err;
2821 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2822 1.53 augustss usb_transfer_complete(xfer);
2823 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2824 1.1 augustss return (USBD_IN_PROGRESS);
2825 1.1 augustss }
2826 1.1 augustss
2827 1.1 augustss /* Abort a root control request. */
2828 1.82 augustss Static void
2829 1.179 christos ohci_root_ctrl_abort(usbd_xfer_handle xfer)
2830 1.1 augustss {
2831 1.9 augustss /* Nothing to do, all transfers are synchronous. */
2832 1.1 augustss }
2833 1.1 augustss
2834 1.1 augustss /* Close the root pipe. */
2835 1.82 augustss Static void
2836 1.179 christos ohci_root_ctrl_close(usbd_pipe_handle pipe)
2837 1.1 augustss {
2838 1.1 augustss DPRINTF(("ohci_root_ctrl_close\n"));
2839 1.34 augustss /* Nothing to do. */
2840 1.1 augustss }
2841 1.1 augustss
2842 1.82 augustss Static usbd_status
2843 1.91 augustss ohci_root_intr_transfer(usbd_xfer_handle xfer)
2844 1.1 augustss {
2845 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2846 1.53 augustss usbd_status err;
2847 1.17 augustss
2848 1.46 augustss /* Insert last in queue. */
2849 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2850 1.53 augustss err = usb_insert_transfer(xfer);
2851 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2852 1.53 augustss if (err)
2853 1.53 augustss return (err);
2854 1.46 augustss
2855 1.46 augustss /* Pipe isn't running, start first */
2856 1.53 augustss return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2857 1.17 augustss }
2858 1.17 augustss
2859 1.82 augustss Static usbd_status
2860 1.91 augustss ohci_root_intr_start(usbd_xfer_handle xfer)
2861 1.17 augustss {
2862 1.53 augustss usbd_pipe_handle pipe = xfer->pipe;
2863 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
2864 1.1 augustss
2865 1.83 augustss if (sc->sc_dying)
2866 1.83 augustss return (USBD_IOERROR);
2867 1.83 augustss
2868 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2869 1.218.6.2 jmcneill KASSERT(sc->sc_intrxfer == NULL);
2870 1.53 augustss sc->sc_intrxfer = xfer;
2871 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2872 1.1 augustss
2873 1.1 augustss return (USBD_IN_PROGRESS);
2874 1.1 augustss }
2875 1.1 augustss
2876 1.3 augustss /* Abort a root interrupt request. */
2877 1.82 augustss Static void
2878 1.91 augustss ohci_root_intr_abort(usbd_xfer_handle xfer)
2879 1.1 augustss {
2880 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2881 1.53 augustss
2882 1.53 augustss if (xfer->pipe->intrxfer == xfer) {
2883 1.51 augustss DPRINTF(("ohci_root_intr_abort: remove\n"));
2884 1.53 augustss xfer->pipe->intrxfer = NULL;
2885 1.51 augustss }
2886 1.53 augustss xfer->status = USBD_CANCELLED;
2887 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2888 1.53 augustss usb_transfer_complete(xfer);
2889 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2890 1.1 augustss }
2891 1.1 augustss
2892 1.1 augustss /* Close the root pipe. */
2893 1.82 augustss Static void
2894 1.91 augustss ohci_root_intr_close(usbd_pipe_handle pipe)
2895 1.1 augustss {
2896 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
2897 1.120 augustss
2898 1.1 augustss DPRINTF(("ohci_root_intr_close\n"));
2899 1.34 augustss
2900 1.53 augustss sc->sc_intrxfer = NULL;
2901 1.1 augustss }
2902 1.1 augustss
2903 1.1 augustss /************************/
2904 1.1 augustss
2905 1.82 augustss Static usbd_status
2906 1.91 augustss ohci_device_ctrl_transfer(usbd_xfer_handle xfer)
2907 1.1 augustss {
2908 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2909 1.53 augustss usbd_status err;
2910 1.17 augustss
2911 1.46 augustss /* Insert last in queue. */
2912 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2913 1.53 augustss err = usb_insert_transfer(xfer);
2914 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2915 1.53 augustss if (err)
2916 1.53 augustss return (err);
2917 1.46 augustss
2918 1.46 augustss /* Pipe isn't running, start first */
2919 1.53 augustss return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2920 1.17 augustss }
2921 1.17 augustss
2922 1.82 augustss Static usbd_status
2923 1.91 augustss ohci_device_ctrl_start(usbd_xfer_handle xfer)
2924 1.17 augustss {
2925 1.190 drochner ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2926 1.53 augustss usbd_status err;
2927 1.1 augustss
2928 1.83 augustss if (sc->sc_dying)
2929 1.83 augustss return (USBD_IOERROR);
2930 1.83 augustss
2931 1.42 augustss #ifdef DIAGNOSTIC
2932 1.53 augustss if (!(xfer->rqflags & URQ_REQUEST)) {
2933 1.1 augustss /* XXX panic */
2934 1.1 augustss printf("ohci_device_ctrl_transfer: not a request\n");
2935 1.1 augustss return (USBD_INVAL);
2936 1.1 augustss }
2937 1.42 augustss #endif
2938 1.1 augustss
2939 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2940 1.53 augustss err = ohci_device_request(xfer);
2941 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2942 1.53 augustss if (err)
2943 1.53 augustss return (err);
2944 1.1 augustss
2945 1.6 augustss if (sc->sc_bus.use_polling)
2946 1.53 augustss ohci_waitintr(sc, xfer);
2947 1.1 augustss return (USBD_IN_PROGRESS);
2948 1.1 augustss }
2949 1.1 augustss
2950 1.1 augustss /* Abort a device control request. */
2951 1.82 augustss Static void
2952 1.91 augustss ohci_device_ctrl_abort(usbd_xfer_handle xfer)
2953 1.1 augustss {
2954 1.53 augustss DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer));
2955 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2956 1.1 augustss }
2957 1.1 augustss
2958 1.1 augustss /* Close a device control pipe. */
2959 1.82 augustss Static void
2960 1.91 augustss ohci_device_ctrl_close(usbd_pipe_handle pipe)
2961 1.1 augustss {
2962 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2963 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
2964 1.1 augustss
2965 1.34 augustss DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe));
2966 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2967 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2968 1.60 augustss ohci_free_std(sc, opipe->tail.td);
2969 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
2970 1.3 augustss }
2971 1.3 augustss
2972 1.3 augustss /************************/
2973 1.37 augustss
2974 1.82 augustss Static void
2975 1.91 augustss ohci_device_clear_toggle(usbd_pipe_handle pipe)
2976 1.37 augustss {
2977 1.37 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2978 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
2979 1.37 augustss
2980 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2981 1.37 augustss }
2982 1.37 augustss
2983 1.82 augustss Static void
2984 1.179 christos ohci_noop(usbd_pipe_handle pipe)
2985 1.37 augustss {
2986 1.37 augustss }
2987 1.3 augustss
2988 1.82 augustss Static usbd_status
2989 1.91 augustss ohci_device_bulk_transfer(usbd_xfer_handle xfer)
2990 1.3 augustss {
2991 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
2992 1.53 augustss usbd_status err;
2993 1.17 augustss
2994 1.46 augustss /* Insert last in queue. */
2995 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
2996 1.53 augustss err = usb_insert_transfer(xfer);
2997 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
2998 1.53 augustss if (err)
2999 1.53 augustss return (err);
3000 1.46 augustss
3001 1.46 augustss /* Pipe isn't running, start first */
3002 1.53 augustss return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3003 1.17 augustss }
3004 1.17 augustss
3005 1.82 augustss Static usbd_status
3006 1.91 augustss ohci_device_bulk_start(usbd_xfer_handle xfer)
3007 1.17 augustss {
3008 1.53 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
3009 1.3 augustss usbd_device_handle dev = opipe->pipe.device;
3010 1.190 drochner ohci_softc_t *sc = dev->bus->hci_private;
3011 1.3 augustss int addr = dev->address;
3012 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
3013 1.3 augustss ohci_soft_ed_t *sed;
3014 1.218.6.2 jmcneill int len, isread, endpt;
3015 1.53 augustss usbd_status err;
3016 1.3 augustss
3017 1.83 augustss if (sc->sc_dying)
3018 1.83 augustss return (USBD_IOERROR);
3019 1.83 augustss
3020 1.34 augustss #ifdef DIAGNOSTIC
3021 1.53 augustss if (xfer->rqflags & URQ_REQUEST) {
3022 1.3 augustss /* XXX panic */
3023 1.34 augustss printf("ohci_device_bulk_start: a request\n");
3024 1.3 augustss return (USBD_INVAL);
3025 1.3 augustss }
3026 1.34 augustss #endif
3027 1.3 augustss
3028 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3029 1.218.6.2 jmcneill
3030 1.53 augustss len = xfer->length;
3031 1.53 augustss endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;
3032 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3033 1.3 augustss sed = opipe->sed;
3034 1.3 augustss
3035 1.53 augustss DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d "
3036 1.53 augustss "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags,
3037 1.40 augustss endpt));
3038 1.34 augustss
3039 1.32 augustss opipe->u.bulk.isread = isread;
3040 1.3 augustss opipe->u.bulk.length = len;
3041 1.3 augustss
3042 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3043 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3044 1.3 augustss /* Update device address */
3045 1.168 augustss sed->ed.ed_flags = HTOO32(
3046 1.168 augustss (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) |
3047 1.16 augustss OHCI_ED_SET_FA(addr));
3048 1.3 augustss
3049 1.48 augustss /* Allocate a chain of new TDs (including a new tail). */
3050 1.60 augustss data = opipe->tail.td;
3051 1.77 augustss err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
3052 1.77 augustss data, &tail);
3053 1.77 augustss /* We want interrupt at the end of the transfer. */
3054 1.168 augustss tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3055 1.168 augustss tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3056 1.77 augustss tail->flags |= OHCI_CALL_DONE;
3057 1.77 augustss tail = tail->nexttd; /* point at sentinel */
3058 1.195 bouyer usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags),
3059 1.195 bouyer sizeof(tail->td.td_flags),
3060 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3061 1.218.6.2 jmcneill if (err) {
3062 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3063 1.53 augustss return (err);
3064 1.218.6.2 jmcneill }
3065 1.48 augustss
3066 1.53 augustss tail->xfer = NULL;
3067 1.53 augustss xfer->hcpriv = data;
3068 1.3 augustss
3069 1.34 augustss DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x "
3070 1.34 augustss "td_cbp=0x%08x td_be=0x%08x\n",
3071 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3072 1.168 augustss (int)O32TOH(data->td.td_flags),
3073 1.168 augustss (int)O32TOH(data->td.td_cbp),
3074 1.168 augustss (int)O32TOH(data->td.td_be)));
3075 1.34 augustss
3076 1.52 augustss #ifdef OHCI_DEBUG
3077 1.75 augustss if (ohcidebug > 5) {
3078 1.168 augustss ohci_dump_ed(sc, sed);
3079 1.168 augustss ohci_dump_tds(sc, data);
3080 1.34 augustss }
3081 1.34 augustss #endif
3082 1.34 augustss
3083 1.3 augustss /* Insert ED in schedule */
3084 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3085 1.53 augustss tdp->xfer = xfer;
3086 1.48 augustss }
3087 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3088 1.60 augustss opipe->tail.td = tail;
3089 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3090 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3091 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3092 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3093 1.53 augustss if (xfer->timeout && !sc->sc_bus.use_polling) {
3094 1.209 dyoung callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout),
3095 1.80 augustss ohci_timeout, xfer);
3096 1.15 augustss }
3097 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3098 1.34 augustss
3099 1.52 augustss #if 0
3100 1.52 augustss /* This goes wrong if we are too slow. */
3101 1.75 augustss if (ohcidebug > 10) {
3102 1.75 augustss delay(10000);
3103 1.41 augustss DPRINTF(("ohci_device_intr_transfer: status=%x\n",
3104 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
3105 1.168 augustss ohci_dump_ed(sc, sed);
3106 1.168 augustss ohci_dump_tds(sc, data);
3107 1.34 augustss }
3108 1.34 augustss #endif
3109 1.34 augustss
3110 1.3 augustss return (USBD_IN_PROGRESS);
3111 1.3 augustss }
3112 1.3 augustss
3113 1.82 augustss Static void
3114 1.91 augustss ohci_device_bulk_abort(usbd_xfer_handle xfer)
3115 1.3 augustss {
3116 1.53 augustss DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer));
3117 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3118 1.3 augustss }
3119 1.3 augustss
3120 1.120 augustss /*
3121 1.34 augustss * Close a device bulk pipe.
3122 1.34 augustss */
3123 1.82 augustss Static void
3124 1.91 augustss ohci_device_bulk_close(usbd_pipe_handle pipe)
3125 1.3 augustss {
3126 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3127 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
3128 1.3 augustss
3129 1.34 augustss DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe));
3130 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3131 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3132 1.60 augustss ohci_free_std(sc, opipe->tail.td);
3133 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
3134 1.1 augustss }
3135 1.1 augustss
3136 1.1 augustss /************************/
3137 1.1 augustss
3138 1.82 augustss Static usbd_status
3139 1.91 augustss ohci_device_intr_transfer(usbd_xfer_handle xfer)
3140 1.17 augustss {
3141 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3142 1.53 augustss usbd_status err;
3143 1.17 augustss
3144 1.46 augustss /* Insert last in queue. */
3145 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3146 1.53 augustss err = usb_insert_transfer(xfer);
3147 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3148 1.53 augustss if (err)
3149 1.53 augustss return (err);
3150 1.46 augustss
3151 1.46 augustss /* Pipe isn't running, start first */
3152 1.53 augustss return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
3153 1.17 augustss }
3154 1.17 augustss
3155 1.82 augustss Static usbd_status
3156 1.91 augustss ohci_device_intr_start(usbd_xfer_handle xfer)
3157 1.1 augustss {
3158 1.53 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
3159 1.1 augustss usbd_device_handle dev = opipe->pipe.device;
3160 1.190 drochner ohci_softc_t *sc = dev->bus->hci_private;
3161 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3162 1.48 augustss ohci_soft_td_t *data, *tail;
3163 1.218.6.2 jmcneill int len, isread, endpt;
3164 1.1 augustss
3165 1.83 augustss if (sc->sc_dying)
3166 1.83 augustss return (USBD_IOERROR);
3167 1.83 augustss
3168 1.53 augustss DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d "
3169 1.14 augustss "flags=%d priv=%p\n",
3170 1.53 augustss xfer, xfer->length, xfer->flags, xfer->priv));
3171 1.1 augustss
3172 1.42 augustss #ifdef DIAGNOSTIC
3173 1.53 augustss if (xfer->rqflags & URQ_REQUEST)
3174 1.128 provos panic("ohci_device_intr_transfer: a request");
3175 1.42 augustss #endif
3176 1.1 augustss
3177 1.53 augustss len = xfer->length;
3178 1.165 skrll endpt = xfer->pipe->endpoint->edesc->bEndpointAddress;
3179 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3180 1.1 augustss
3181 1.60 augustss data = opipe->tail.td;
3182 1.218.6.7 mrg mutex_enter(&sc->sc_lock);
3183 1.1 augustss tail = ohci_alloc_std(sc);
3184 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
3185 1.55 augustss if (tail == NULL)
3186 1.43 augustss return (USBD_NOMEM);
3187 1.53 augustss tail->xfer = NULL;
3188 1.1 augustss
3189 1.168 augustss data->td.td_flags = HTOO32(
3190 1.165 skrll isread ? OHCI_TD_IN : OHCI_TD_OUT |
3191 1.165 skrll OHCI_TD_NOCC |
3192 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
3193 1.53 augustss if (xfer->flags & USBD_SHORT_XFER_OK)
3194 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
3195 1.168 augustss data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0));
3196 1.48 augustss data->nexttd = tail;
3197 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
3198 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1);
3199 1.48 augustss data->len = len;
3200 1.53 augustss data->xfer = xfer;
3201 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
3202 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
3203 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3204 1.53 augustss xfer->hcpriv = data;
3205 1.1 augustss
3206 1.52 augustss #ifdef OHCI_DEBUG
3207 1.1 augustss if (ohcidebug > 5) {
3208 1.41 augustss DPRINTF(("ohci_device_intr_transfer:\n"));
3209 1.168 augustss ohci_dump_ed(sc, sed);
3210 1.168 augustss ohci_dump_tds(sc, data);
3211 1.1 augustss }
3212 1.1 augustss #endif
3213 1.1 augustss
3214 1.1 augustss /* Insert ED in schedule */
3215 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3216 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3217 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3218 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3219 1.60 augustss opipe->tail.td = tail;
3220 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3221 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3222 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3223 1.1 augustss
3224 1.52 augustss #if 0
3225 1.52 augustss /*
3226 1.52 augustss * This goes horribly wrong, printing thousands of descriptors,
3227 1.52 augustss * because false references are followed due to the fact that the
3228 1.52 augustss * TD is gone.
3229 1.52 augustss */
3230 1.1 augustss if (ohcidebug > 5) {
3231 1.55 augustss usb_delay_ms(&sc->sc_bus, 5);
3232 1.41 augustss DPRINTF(("ohci_device_intr_transfer: status=%x\n",
3233 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
3234 1.168 augustss ohci_dump_ed(sc, sed);
3235 1.168 augustss ohci_dump_tds(sc, data);
3236 1.1 augustss }
3237 1.1 augustss #endif
3238 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3239 1.1 augustss
3240 1.1 augustss return (USBD_IN_PROGRESS);
3241 1.1 augustss }
3242 1.1 augustss
3243 1.1 augustss /* Abort a device control request. */
3244 1.82 augustss Static void
3245 1.91 augustss ohci_device_intr_abort(usbd_xfer_handle xfer)
3246 1.1 augustss {
3247 1.53 augustss if (xfer->pipe->intrxfer == xfer) {
3248 1.1 augustss DPRINTF(("ohci_device_intr_abort: remove\n"));
3249 1.55 augustss xfer->pipe->intrxfer = NULL;
3250 1.1 augustss }
3251 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3252 1.1 augustss }
3253 1.1 augustss
3254 1.1 augustss /* Close a device interrupt pipe. */
3255 1.82 augustss Static void
3256 1.91 augustss ohci_device_intr_close(usbd_pipe_handle pipe)
3257 1.1 augustss {
3258 1.1 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3259 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
3260 1.1 augustss int nslots = opipe->u.intr.nslots;
3261 1.1 augustss int pos = opipe->u.intr.pos;
3262 1.1 augustss int j;
3263 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3264 1.1 augustss
3265 1.1 augustss DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
3266 1.1 augustss pipe, nslots, pos));
3267 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3268 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3269 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3270 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3271 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3272 1.195 bouyer sizeof(sed->ed.ed_flags),
3273 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3274 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3275 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3276 1.20 augustss usb_delay_ms(&sc->sc_bus, 2);
3277 1.1 augustss
3278 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3279 1.172 christos continue;
3280 1.53 augustss #ifdef DIAGNOSTIC
3281 1.173 christos if (p == NULL)
3282 1.128 provos panic("ohci_device_intr_close: ED not found");
3283 1.53 augustss #endif
3284 1.173 christos p->next = sed->next;
3285 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3286 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3287 1.195 bouyer sizeof(p->ed.ed_nexted),
3288 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3289 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3290 1.1 augustss
3291 1.1 augustss for (j = 0; j < nslots; j++)
3292 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3293 1.1 augustss
3294 1.60 augustss ohci_free_std(sc, opipe->tail.td);
3295 1.1 augustss ohci_free_sed(sc, opipe->sed);
3296 1.1 augustss }
3297 1.1 augustss
3298 1.82 augustss Static usbd_status
3299 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3300 1.1 augustss {
3301 1.218.6.2 jmcneill int i, j, best;
3302 1.1 augustss u_int npoll, slow, shigh, nslots;
3303 1.1 augustss u_int bestbw, bw;
3304 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3305 1.1 augustss
3306 1.1 augustss DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
3307 1.1 augustss if (ival == 0) {
3308 1.1 augustss printf("ohci_setintr: 0 interval\n");
3309 1.1 augustss return (USBD_INVAL);
3310 1.1 augustss }
3311 1.1 augustss
3312 1.1 augustss npoll = OHCI_NO_INTRS;
3313 1.1 augustss while (npoll > ival)
3314 1.1 augustss npoll /= 2;
3315 1.1 augustss DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
3316 1.1 augustss
3317 1.1 augustss /*
3318 1.1 augustss * We now know which level in the tree the ED must go into.
3319 1.1 augustss * Figure out which slot has most bandwidth left over.
3320 1.1 augustss * Slots to examine:
3321 1.1 augustss * npoll
3322 1.1 augustss * 1 0
3323 1.1 augustss * 2 1 2
3324 1.1 augustss * 4 3 4 5 6
3325 1.1 augustss * 8 7 8 9 10 11 12 13 14
3326 1.1 augustss * N (N-1) .. (N-1+N-1)
3327 1.1 augustss */
3328 1.1 augustss slow = npoll-1;
3329 1.1 augustss shigh = slow + npoll;
3330 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3331 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3332 1.1 augustss bw = 0;
3333 1.1 augustss for (j = 0; j < nslots; j++)
3334 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3335 1.1 augustss if (bw < bestbw) {
3336 1.1 augustss best = i;
3337 1.1 augustss bestbw = bw;
3338 1.1 augustss }
3339 1.1 augustss }
3340 1.120 augustss DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
3341 1.1 augustss best, slow, shigh, bestbw));
3342 1.1 augustss
3343 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3344 1.1 augustss hsed = sc->sc_eds[best];
3345 1.1 augustss sed->next = hsed->next;
3346 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3347 1.195 bouyer sizeof(hsed->ed.ed_flags),
3348 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3349 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3350 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3351 1.195 bouyer sizeof(sed->ed.ed_flags),
3352 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3353 1.1 augustss hsed->next = sed;
3354 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3355 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3356 1.195 bouyer sizeof(hsed->ed.ed_flags),
3357 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3358 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3359 1.1 augustss
3360 1.1 augustss for (j = 0; j < nslots; j++)
3361 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3362 1.1 augustss opipe->u.intr.nslots = nslots;
3363 1.1 augustss opipe->u.intr.pos = best;
3364 1.1 augustss
3365 1.1 augustss DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
3366 1.1 augustss return (USBD_NORMAL_COMPLETION);
3367 1.60 augustss }
3368 1.60 augustss
3369 1.60 augustss /***********************/
3370 1.60 augustss
3371 1.60 augustss usbd_status
3372 1.91 augustss ohci_device_isoc_transfer(usbd_xfer_handle xfer)
3373 1.60 augustss {
3374 1.218.6.2 jmcneill ohci_softc_t *sc = xfer->pipe->device->bus->hci_private;
3375 1.60 augustss usbd_status err;
3376 1.60 augustss
3377 1.60 augustss DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer));
3378 1.60 augustss
3379 1.60 augustss /* Put it on our queue, */
3380 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3381 1.60 augustss err = usb_insert_transfer(xfer);
3382 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3383 1.60 augustss
3384 1.60 augustss /* bail out on error, */
3385 1.60 augustss if (err && err != USBD_IN_PROGRESS)
3386 1.60 augustss return (err);
3387 1.60 augustss
3388 1.60 augustss /* XXX should check inuse here */
3389 1.60 augustss
3390 1.60 augustss /* insert into schedule, */
3391 1.60 augustss ohci_device_isoc_enter(xfer);
3392 1.60 augustss
3393 1.83 augustss /* and start if the pipe wasn't running */
3394 1.60 augustss if (!err)
3395 1.60 augustss ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue));
3396 1.60 augustss
3397 1.60 augustss return (err);
3398 1.60 augustss }
3399 1.60 augustss
3400 1.60 augustss void
3401 1.91 augustss ohci_device_isoc_enter(usbd_xfer_handle xfer)
3402 1.60 augustss {
3403 1.61 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
3404 1.61 augustss usbd_device_handle dev = opipe->pipe.device;
3405 1.190 drochner ohci_softc_t *sc = dev->bus->hci_private;
3406 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3407 1.61 augustss struct iso *iso = &opipe->u.iso;
3408 1.120 augustss ohci_soft_itd_t *sitd, *nsitd;
3409 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3410 1.61 augustss int i, ncur, nframes;
3411 1.61 augustss
3412 1.83 augustss DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p "
3413 1.83 augustss "nframes=%d\n",
3414 1.83 augustss iso->inuse, iso->next, xfer, xfer->nframes));
3415 1.83 augustss
3416 1.83 augustss if (sc->sc_dying)
3417 1.83 augustss return;
3418 1.83 augustss
3419 1.83 augustss if (iso->next == -1) {
3420 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3421 1.168 augustss iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3422 1.120 augustss DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n",
3423 1.83 augustss iso->next));
3424 1.83 augustss }
3425 1.83 augustss
3426 1.61 augustss sitd = opipe->tail.itd;
3427 1.125 augustss buf = DMAADDR(&xfer->dmabuf, 0);
3428 1.83 augustss bp0 = OHCI_PAGE(buf);
3429 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3430 1.61 augustss nframes = xfer->nframes;
3431 1.83 augustss xfer->hcpriv = sitd;
3432 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3433 1.83 augustss noffs = offs + xfer->frlengths[i];
3434 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3435 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3436 1.120 augustss
3437 1.83 augustss /* Allocate next ITD */
3438 1.218.6.7 mrg mutex_enter(&sc->sc_lock);
3439 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3440 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
3441 1.61 augustss if (nsitd == NULL) {
3442 1.61 augustss /* XXX what now? */
3443 1.83 augustss printf("%s: isoc TD alloc failed\n",
3444 1.190 drochner device_xname(sc->sc_dev));
3445 1.61 augustss return;
3446 1.61 augustss }
3447 1.83 augustss
3448 1.83 augustss /* Fill current ITD */
3449 1.168 augustss sitd->itd.itd_flags = HTOO32(
3450 1.120 augustss OHCI_ITD_NOCC |
3451 1.61 augustss OHCI_ITD_SET_SF(iso->next) |
3452 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3453 1.83 augustss OHCI_ITD_SET_FC(ncur));
3454 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3455 1.83 augustss sitd->nextitd = nsitd;
3456 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3457 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3458 1.83 augustss sitd->xfer = xfer;
3459 1.83 augustss sitd->flags = 0;
3460 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3461 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3462 1.83 augustss
3463 1.61 augustss sitd = nsitd;
3464 1.120 augustss iso->next = iso->next + ncur;
3465 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3466 1.61 augustss ncur = 0;
3467 1.61 augustss }
3468 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3469 1.83 augustss offs = noffs;
3470 1.61 augustss }
3471 1.218.6.7 mrg mutex_enter(&sc->sc_lock);
3472 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3473 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
3474 1.61 augustss if (nsitd == NULL) {
3475 1.61 augustss /* XXX what now? */
3476 1.120 augustss printf("%s: isoc TD alloc failed\n",
3477 1.190 drochner device_xname(sc->sc_dev));
3478 1.61 augustss return;
3479 1.61 augustss }
3480 1.83 augustss /* Fixup last used ITD */
3481 1.168 augustss sitd->itd.itd_flags = HTOO32(
3482 1.120 augustss OHCI_ITD_NOCC |
3483 1.61 augustss OHCI_ITD_SET_SF(iso->next) |
3484 1.61 augustss OHCI_ITD_SET_DI(0) |
3485 1.61 augustss OHCI_ITD_SET_FC(ncur));
3486 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3487 1.83 augustss sitd->nextitd = nsitd;
3488 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3489 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3490 1.83 augustss sitd->xfer = xfer;
3491 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3492 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3493 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3494 1.83 augustss
3495 1.61 augustss iso->next = iso->next + ncur;
3496 1.83 augustss iso->inuse += nframes;
3497 1.83 augustss
3498 1.83 augustss xfer->actlen = offs; /* XXX pretend we did it all */
3499 1.83 augustss
3500 1.83 augustss xfer->status = USBD_IN_PROGRESS;
3501 1.83 augustss
3502 1.83 augustss #ifdef OHCI_DEBUG
3503 1.83 augustss if (ohcidebug > 5) {
3504 1.83 augustss DPRINTF(("ohci_device_isoc_enter: frame=%d\n",
3505 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number)));
3506 1.168 augustss ohci_dump_itds(sc, xfer->hcpriv);
3507 1.168 augustss ohci_dump_ed(sc, sed);
3508 1.83 augustss }
3509 1.83 augustss #endif
3510 1.61 augustss
3511 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3512 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3513 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3514 1.168 augustss sed->ed.ed_tailp = HTOO32(nsitd->physaddr);
3515 1.61 augustss opipe->tail.itd = nsitd;
3516 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3517 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3518 1.195 bouyer sizeof(sed->ed.ed_flags),
3519 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3520 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3521 1.83 augustss
3522 1.83 augustss #ifdef OHCI_DEBUG
3523 1.83 augustss if (ohcidebug > 5) {
3524 1.83 augustss delay(150000);
3525 1.83 augustss DPRINTF(("ohci_device_isoc_enter: after frame=%d\n",
3526 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number)));
3527 1.168 augustss ohci_dump_itds(sc, xfer->hcpriv);
3528 1.168 augustss ohci_dump_ed(sc, sed);
3529 1.83 augustss }
3530 1.83 augustss #endif
3531 1.60 augustss }
3532 1.60 augustss
3533 1.60 augustss usbd_status
3534 1.91 augustss ohci_device_isoc_start(usbd_xfer_handle xfer)
3535 1.60 augustss {
3536 1.83 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
3537 1.190 drochner ohci_softc_t *sc = opipe->pipe.device->bus->hci_private;
3538 1.83 augustss
3539 1.83 augustss DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer));
3540 1.83 augustss
3541 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3542 1.218.6.2 jmcneill
3543 1.218.6.2 jmcneill if (sc->sc_dying) {
3544 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3545 1.83 augustss return (USBD_IOERROR);
3546 1.218.6.2 jmcneill }
3547 1.83 augustss
3548 1.83 augustss #ifdef DIAGNOSTIC
3549 1.83 augustss if (xfer->status != USBD_IN_PROGRESS)
3550 1.121 tsutsui printf("ohci_device_isoc_start: not in progress %p\n", xfer);
3551 1.83 augustss #endif
3552 1.83 augustss
3553 1.83 augustss /* XXX anything to do? */
3554 1.83 augustss
3555 1.218.6.3 mrg mutex_exit(&sc->sc_lock);
3556 1.218.6.3 mrg
3557 1.83 augustss return (USBD_IN_PROGRESS);
3558 1.60 augustss }
3559 1.60 augustss
3560 1.60 augustss void
3561 1.91 augustss ohci_device_isoc_abort(usbd_xfer_handle xfer)
3562 1.60 augustss {
3563 1.83 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe;
3564 1.190 drochner ohci_softc_t *sc = opipe->pipe.device->bus->hci_private;
3565 1.83 augustss ohci_soft_ed_t *sed;
3566 1.83 augustss ohci_soft_itd_t *sitd;
3567 1.83 augustss
3568 1.218.6.3 mrg DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock));
3569 1.83 augustss
3570 1.218.6.3 mrg mutex_enter(&sc->sc_lock);
3571 1.218.6.2 jmcneill
3572 1.83 augustss /* Transfer is already done. */
3573 1.120 augustss if (xfer->status != USBD_NOT_STARTED &&
3574 1.83 augustss xfer->status != USBD_IN_PROGRESS) {
3575 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3576 1.218.6.2 jmcneill goto done;
3577 1.83 augustss }
3578 1.83 augustss
3579 1.83 augustss /* Give xfer the requested abort code. */
3580 1.83 augustss xfer->status = USBD_CANCELLED;
3581 1.83 augustss
3582 1.83 augustss sed = opipe->sed;
3583 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3584 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3585 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3586 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3587 1.195 bouyer sizeof(sed->ed.ed_flags),
3588 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3589 1.83 augustss
3590 1.83 augustss sitd = xfer->hcpriv;
3591 1.83 augustss #ifdef DIAGNOSTIC
3592 1.83 augustss if (sitd == NULL) {
3593 1.83 augustss printf("ohci_device_isoc_abort: hcpriv==0\n");
3594 1.218.6.2 jmcneill goto done;
3595 1.83 augustss }
3596 1.83 augustss #endif
3597 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3598 1.83 augustss #ifdef DIAGNOSTIC
3599 1.83 augustss DPRINTFN(1,("abort sets done sitd=%p\n", sitd));
3600 1.83 augustss sitd->isdone = 1;
3601 1.83 augustss #endif
3602 1.83 augustss }
3603 1.83 augustss
3604 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3605 1.83 augustss
3606 1.83 augustss usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET);
3607 1.83 augustss
3608 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3609 1.83 augustss
3610 1.83 augustss /* Run callback. */
3611 1.83 augustss usb_transfer_complete(xfer);
3612 1.83 augustss
3613 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3614 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3615 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3616 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3617 1.83 augustss
3618 1.218.6.2 jmcneill done:
3619 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3620 1.60 augustss }
3621 1.60 augustss
3622 1.60 augustss void
3623 1.179 christos ohci_device_isoc_done(usbd_xfer_handle xfer)
3624 1.60 augustss {
3625 1.83 augustss DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer));
3626 1.60 augustss }
3627 1.60 augustss
3628 1.60 augustss usbd_status
3629 1.91 augustss ohci_setup_isoc(usbd_pipe_handle pipe)
3630 1.60 augustss {
3631 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3632 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
3633 1.60 augustss struct iso *iso = &opipe->u.iso;
3634 1.60 augustss
3635 1.60 augustss iso->next = -1;
3636 1.60 augustss iso->inuse = 0;
3637 1.60 augustss
3638 1.218.6.2 jmcneill mutex_enter(&sc->sc_lock);
3639 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3640 1.218.6.2 jmcneill mutex_exit(&sc->sc_lock);
3641 1.83 augustss
3642 1.60 augustss return (USBD_NORMAL_COMPLETION);
3643 1.60 augustss }
3644 1.60 augustss
3645 1.60 augustss void
3646 1.91 augustss ohci_device_isoc_close(usbd_pipe_handle pipe)
3647 1.60 augustss {
3648 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3649 1.190 drochner ohci_softc_t *sc = pipe->device->bus->hci_private;
3650 1.60 augustss
3651 1.60 augustss DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe));
3652 1.218.6.3 mrg mutex_enter(&sc->sc_lock);
3653 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3654 1.83 augustss #ifdef DIAGNOSTIC
3655 1.83 augustss opipe->tail.itd->isdone = 1;
3656 1.83 augustss #endif
3657 1.60 augustss ohci_free_sitd(sc, opipe->tail.itd);
3658 1.218.6.7 mrg mutex_exit(&sc->sc_lock);
3659 1.1 augustss }
3660