ohci.c revision 1.253.2.2.2.2 1 1.253.2.2.2.2 skrll /* $NetBSD: ohci.c,v 1.253.2.2.2.2 2017/01/31 07:26:39 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.253.2.2.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.253.2.2.2.2 2017/01/31 07:26:39 skrll Exp $");
45 1.253.2.2.2.1 skrll
46 1.253.2.2.2.1 skrll #ifdef _KERNEL_OPT
47 1.253.2.2.2.1 skrll #include "opt_usb.h"
48 1.253.2.2.2.1 skrll #endif
49 1.1 augustss
50 1.1 augustss #include <sys/param.h>
51 1.253.2.2.2.1 skrll
52 1.253.2.2.2.1 skrll #include <sys/cpu.h>
53 1.1 augustss #include <sys/device.h>
54 1.253.2.2.2.1 skrll #include <sys/kernel.h>
55 1.253.2.2.2.1 skrll #include <sys/kmem.h>
56 1.1 augustss #include <sys/proc.h>
57 1.1 augustss #include <sys/queue.h>
58 1.253.2.2.2.1 skrll #include <sys/select.h>
59 1.253.2.2.2.1 skrll #include <sys/sysctl.h>
60 1.253.2.2.2.1 skrll #include <sys/systm.h>
61 1.1 augustss
62 1.16 augustss #include <machine/endian.h>
63 1.4 augustss
64 1.1 augustss #include <dev/usb/usb.h>
65 1.1 augustss #include <dev/usb/usbdi.h>
66 1.1 augustss #include <dev/usb/usbdivar.h>
67 1.38 augustss #include <dev/usb/usb_mem.h>
68 1.1 augustss #include <dev/usb/usb_quirks.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/ohcireg.h>
71 1.1 augustss #include <dev/usb/ohcivar.h>
72 1.253.2.2.2.1 skrll #include <dev/usb/usbroothub.h>
73 1.253.2.2.2.1 skrll #include <dev/usb/usbhist.h>
74 1.1 augustss
75 1.253.2.2.2.1 skrll #ifdef USB_DEBUG
76 1.253.2.2.2.1 skrll #ifndef OHCI_DEBUG
77 1.253.2.2.2.1 skrll #define ohcidebug 0
78 1.253.2.2.2.1 skrll #else
79 1.253.2.2.2.1 skrll static int ohcidebug = 10;
80 1.1 augustss
81 1.253.2.2.2.1 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
82 1.253.2.2.2.1 skrll {
83 1.253.2.2.2.1 skrll int err;
84 1.253.2.2.2.1 skrll const struct sysctlnode *rnode;
85 1.253.2.2.2.1 skrll const struct sysctlnode *cnode;
86 1.253.2.2.2.1 skrll
87 1.253.2.2.2.1 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
88 1.253.2.2.2.1 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
89 1.253.2.2.2.1 skrll SYSCTL_DESCR("ohci global controls"),
90 1.253.2.2.2.1 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
91 1.36 augustss
92 1.253.2.2.2.1 skrll if (err)
93 1.253.2.2.2.1 skrll goto fail;
94 1.253.2.2.2.1 skrll
95 1.253.2.2.2.1 skrll /* control debugging printfs */
96 1.253.2.2.2.1 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
97 1.253.2.2.2.1 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
98 1.253.2.2.2.1 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
99 1.253.2.2.2.1 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
100 1.253.2.2.2.1 skrll if (err)
101 1.253.2.2.2.1 skrll goto fail;
102 1.253.2.2.2.1 skrll
103 1.253.2.2.2.1 skrll return;
104 1.253.2.2.2.1 skrll fail:
105 1.253.2.2.2.1 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
106 1.253.2.2.2.1 skrll }
107 1.253.2.2.2.1 skrll
108 1.253.2.2.2.1 skrll #endif /* OHCI_DEBUG */
109 1.253.2.2.2.1 skrll #endif /* USB_DEBUG */
110 1.253.2.2.2.1 skrll
111 1.253.2.2.2.1 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
112 1.253.2.2.2.1 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
113 1.253.2.2.2.1 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
114 1.253.2.2.2.1 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
115 1.52 augustss
116 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
117 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
118 1.16 augustss #else
119 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
120 1.16 augustss #endif
121 1.16 augustss
122 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
123 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
124 1.169 tron #define HTOO16(val) O16TOH(val)
125 1.169 tron #define HTOO32(val) O32TOH(val)
126 1.168 augustss
127 1.1 augustss struct ohci_pipe;
128 1.1 augustss
129 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
130 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
131 1.1 augustss
132 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
133 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
134 1.253.2.2.2.1 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
135 1.1 augustss
136 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
137 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
138 1.253.2.2.2.1 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
139 1.253.2.2.2.1 skrll ohci_soft_itd_t *);
140 1.253.2.2.2.1 skrll
141 1.253.2.2.2.1 skrll Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
142 1.253.2.2.2.1 skrll int, int);
143 1.253.2.2.2.1 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
144 1.60 augustss
145 1.253.2.2.2.1 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
146 1.253.2.2.2.1 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
147 1.53 augustss
148 1.253.2.2.2.1 skrll Static usbd_status ohci_open(struct usbd_pipe *);
149 1.91 augustss Static void ohci_poll(struct usbd_bus *);
150 1.99 augustss Static void ohci_softintr(void *);
151 1.253.2.2.2.1 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
152 1.253.2.2.2.1 skrll Static void ohci_rhsc_softint(void *);
153 1.91 augustss
154 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
155 1.168 augustss ohci_soft_ed_t *);
156 1.168 augustss
157 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
158 1.224 mrg ohci_soft_ed_t *);
159 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
161 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
162 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
164 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
165 1.91 augustss
166 1.253.2.2.2.1 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
167 1.253.2.2.2.1 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
168 1.91 augustss
169 1.253.2.2.2.1 skrll Static struct usbd_xfer *
170 1.253.2.2.2.1 skrll ohci_allocx(struct usbd_bus *, unsigned int);
171 1.253.2.2.2.1 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
172 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
173 1.253.2.2.2.1 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
174 1.253.2.2.2.1 skrll usb_device_request_t *, void *, int);
175 1.91 augustss
176 1.253.2.2.2.1 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
177 1.253.2.2.2.1 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
178 1.253.2.2.2.1 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
179 1.253.2.2.2.1 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
180 1.253.2.2.2.1 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
181 1.253.2.2.2.1 skrll
182 1.253.2.2.2.1 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
183 1.253.2.2.2.1 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
184 1.253.2.2.2.1 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
185 1.253.2.2.2.1 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
186 1.253.2.2.2.1 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
187 1.253.2.2.2.1 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
188 1.253.2.2.2.1 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
189 1.253.2.2.2.1 skrll
190 1.253.2.2.2.1 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
191 1.253.2.2.2.1 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
192 1.253.2.2.2.1 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
193 1.253.2.2.2.1 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
194 1.253.2.2.2.1 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
195 1.253.2.2.2.1 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
196 1.253.2.2.2.1 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
197 1.253.2.2.2.1 skrll
198 1.253.2.2.2.1 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
199 1.253.2.2.2.1 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
200 1.253.2.2.2.1 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
201 1.253.2.2.2.1 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
202 1.253.2.2.2.1 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
203 1.253.2.2.2.1 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
204 1.253.2.2.2.1 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
205 1.253.2.2.2.1 skrll
206 1.253.2.2.2.1 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
207 1.253.2.2.2.1 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
208 1.253.2.2.2.1 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
209 1.253.2.2.2.1 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
210 1.253.2.2.2.1 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
211 1.253.2.2.2.1 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
212 1.91 augustss
213 1.253.2.2.2.1 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
214 1.253.2.2.2.1 skrll struct ohci_pipe *, int);
215 1.91 augustss
216 1.91 augustss Static void ohci_timeout(void *);
217 1.114 augustss Static void ohci_timeout_task(void *);
218 1.104 augustss Static void ohci_rhsc_enable(void *);
219 1.91 augustss
220 1.253.2.2.2.1 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
221 1.253.2.2.2.1 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
222 1.53 augustss
223 1.253.2.2.2.1 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
224 1.253.2.2.2.1 skrll Static void ohci_noop(struct usbd_pipe *);
225 1.37 augustss
226 1.52 augustss #ifdef OHCI_DEBUG
227 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
228 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
230 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
231 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
232 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
233 1.1 augustss #endif
234 1.1 augustss
235 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
236 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
237 1.88 augustss #define OWRITE1(sc, r, x) \
238 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
239 1.88 augustss #define OWRITE2(sc, r, x) \
240 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
241 1.88 augustss #define OWRITE4(sc, r, x) \
242 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
243 1.174 mrg
244 1.174 mrg static __inline uint32_t
245 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
246 1.174 mrg {
247 1.174 mrg
248 1.174 mrg OBARR(sc);
249 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
250 1.174 mrg }
251 1.1 augustss
252 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
253 1.253.2.2.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
254 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
255 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
256 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
257 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
258 1.1 augustss
259 1.1 augustss struct ohci_pipe {
260 1.1 augustss struct usbd_pipe pipe;
261 1.1 augustss ohci_soft_ed_t *sed;
262 1.60 augustss union {
263 1.60 augustss ohci_soft_td_t *td;
264 1.60 augustss ohci_soft_itd_t *itd;
265 1.60 augustss } tail;
266 1.1 augustss /* Info needed for different pipe kinds. */
267 1.1 augustss union {
268 1.1 augustss /* Control pipe */
269 1.1 augustss struct {
270 1.4 augustss usb_dma_t reqdma;
271 1.253.2.2.2.1 skrll } ctrl;
272 1.1 augustss /* Interrupt pipe */
273 1.1 augustss struct {
274 1.1 augustss int nslots;
275 1.1 augustss int pos;
276 1.1 augustss } intr;
277 1.253.2.2.2.1 skrll /* Isochronous pipe */
278 1.253.2.2.2.1 skrll struct isoc {
279 1.60 augustss int next, inuse;
280 1.253.2.2.2.1 skrll } isoc;
281 1.253.2.2.2.1 skrll };
282 1.1 augustss };
283 1.1 augustss
284 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
285 1.253.2.2.2.1 skrll .ubm_open = ohci_open,
286 1.253.2.2.2.1 skrll .ubm_softint = ohci_softintr,
287 1.253.2.2.2.1 skrll .ubm_dopoll = ohci_poll,
288 1.253.2.2.2.1 skrll .ubm_allocx = ohci_allocx,
289 1.253.2.2.2.1 skrll .ubm_freex = ohci_freex,
290 1.253.2.2.2.1 skrll .ubm_getlock = ohci_get_lock,
291 1.253.2.2.2.1 skrll .ubm_rhctrl = ohci_roothub_ctrl,
292 1.1 augustss };
293 1.1 augustss
294 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
295 1.253.2.2.2.1 skrll .upm_transfer = ohci_root_intr_transfer,
296 1.253.2.2.2.1 skrll .upm_start = ohci_root_intr_start,
297 1.253.2.2.2.1 skrll .upm_abort = ohci_root_intr_abort,
298 1.253.2.2.2.1 skrll .upm_close = ohci_root_intr_close,
299 1.253.2.2.2.1 skrll .upm_cleartoggle = ohci_noop,
300 1.253.2.2.2.1 skrll .upm_done = ohci_root_intr_done,
301 1.1 augustss };
302 1.1 augustss
303 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
304 1.253.2.2.2.1 skrll .upm_init = ohci_device_ctrl_init,
305 1.253.2.2.2.1 skrll .upm_fini = ohci_device_ctrl_fini,
306 1.253.2.2.2.1 skrll .upm_transfer = ohci_device_ctrl_transfer,
307 1.253.2.2.2.1 skrll .upm_start = ohci_device_ctrl_start,
308 1.253.2.2.2.1 skrll .upm_abort = ohci_device_ctrl_abort,
309 1.253.2.2.2.1 skrll .upm_close = ohci_device_ctrl_close,
310 1.253.2.2.2.1 skrll .upm_cleartoggle = ohci_noop,
311 1.253.2.2.2.1 skrll .upm_done = ohci_device_ctrl_done,
312 1.1 augustss };
313 1.1 augustss
314 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
315 1.253.2.2.2.1 skrll .upm_init = ohci_device_intr_init,
316 1.253.2.2.2.1 skrll .upm_fini = ohci_device_intr_fini,
317 1.253.2.2.2.1 skrll .upm_transfer = ohci_device_intr_transfer,
318 1.253.2.2.2.1 skrll .upm_start = ohci_device_intr_start,
319 1.253.2.2.2.1 skrll .upm_abort = ohci_device_intr_abort,
320 1.253.2.2.2.1 skrll .upm_close = ohci_device_intr_close,
321 1.253.2.2.2.1 skrll .upm_cleartoggle = ohci_device_clear_toggle,
322 1.253.2.2.2.1 skrll .upm_done = ohci_device_intr_done,
323 1.1 augustss };
324 1.1 augustss
325 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
326 1.253.2.2.2.1 skrll .upm_init = ohci_device_bulk_init,
327 1.253.2.2.2.1 skrll .upm_fini = ohci_device_bulk_fini,
328 1.253.2.2.2.1 skrll .upm_transfer = ohci_device_bulk_transfer,
329 1.253.2.2.2.1 skrll .upm_start = ohci_device_bulk_start,
330 1.253.2.2.2.1 skrll .upm_abort = ohci_device_bulk_abort,
331 1.253.2.2.2.1 skrll .upm_close = ohci_device_bulk_close,
332 1.253.2.2.2.1 skrll .upm_cleartoggle = ohci_device_clear_toggle,
333 1.253.2.2.2.1 skrll .upm_done = ohci_device_bulk_done,
334 1.3 augustss };
335 1.3 augustss
336 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
337 1.253.2.2.2.1 skrll .upm_init = ohci_device_isoc_init,
338 1.253.2.2.2.1 skrll .upm_fini = ohci_device_isoc_fini,
339 1.253.2.2.2.1 skrll .upm_transfer = ohci_device_isoc_transfer,
340 1.253.2.2.2.1 skrll .upm_abort = ohci_device_isoc_abort,
341 1.253.2.2.2.1 skrll .upm_close = ohci_device_isoc_close,
342 1.253.2.2.2.1 skrll .upm_cleartoggle = ohci_noop,
343 1.253.2.2.2.1 skrll .upm_done = ohci_device_isoc_done,
344 1.43 augustss };
345 1.43 augustss
346 1.47 augustss int
347 1.189 dyoung ohci_activate(device_t self, enum devact act)
348 1.47 augustss {
349 1.189 dyoung struct ohci_softc *sc = device_private(self);
350 1.47 augustss
351 1.47 augustss switch (act) {
352 1.47 augustss case DVACT_DEACTIVATE:
353 1.183 kiyohara sc->sc_dying = 1;
354 1.203 dyoung return 0;
355 1.203 dyoung default:
356 1.203 dyoung return EOPNOTSUPP;
357 1.47 augustss }
358 1.47 augustss }
359 1.47 augustss
360 1.187 dyoung void
361 1.187 dyoung ohci_childdet(device_t self, device_t child)
362 1.187 dyoung {
363 1.187 dyoung struct ohci_softc *sc = device_private(self);
364 1.187 dyoung
365 1.187 dyoung KASSERT(sc->sc_child == child);
366 1.187 dyoung sc->sc_child = NULL;
367 1.187 dyoung }
368 1.187 dyoung
369 1.47 augustss int
370 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
371 1.47 augustss {
372 1.47 augustss int rv = 0;
373 1.47 augustss
374 1.47 augustss if (sc->sc_child != NULL)
375 1.47 augustss rv = config_detach(sc->sc_child, flags);
376 1.120 augustss
377 1.47 augustss if (rv != 0)
378 1.253.2.2.2.1 skrll return rv;
379 1.47 augustss
380 1.253.2.1 martin callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
381 1.104 augustss
382 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
383 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
384 1.116 augustss
385 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
386 1.224 mrg
387 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
388 1.224 mrg
389 1.224 mrg mutex_destroy(&sc->sc_lock);
390 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
391 1.224 mrg
392 1.198 cegger if (sc->sc_hcca != NULL)
393 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
394 1.232 christos pool_cache_destroy(sc->sc_xferpool);
395 1.47 augustss
396 1.253.2.2.2.1 skrll return rv;
397 1.47 augustss }
398 1.47 augustss
399 1.1 augustss ohci_soft_ed_t *
400 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
401 1.1 augustss {
402 1.1 augustss ohci_soft_ed_t *sed;
403 1.53 augustss usbd_status err;
404 1.1 augustss int i, offs;
405 1.4 augustss usb_dma_t dma;
406 1.1 augustss
407 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
408 1.253.2.2.2.1 skrll
409 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
410 1.53 augustss if (sc->sc_freeeds == NULL) {
411 1.253.2.2.2.1 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
412 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
413 1.253.2.2.2.1 skrll
414 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
415 1.53 augustss OHCI_ED_ALIGN, &dma);
416 1.53 augustss if (err)
417 1.253.2.2.2.1 skrll return 0;
418 1.253.2.2.2.1 skrll
419 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
420 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
421 1.39 augustss offs = i * OHCI_SED_SIZE;
422 1.123 augustss sed = KERNADDR(&dma, offs);
423 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
424 1.195 bouyer sed->dma = dma;
425 1.195 bouyer sed->offs = offs;
426 1.1 augustss sed->next = sc->sc_freeeds;
427 1.1 augustss sc->sc_freeeds = sed;
428 1.1 augustss }
429 1.1 augustss }
430 1.1 augustss sed = sc->sc_freeeds;
431 1.1 augustss sc->sc_freeeds = sed->next;
432 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
433 1.253.2.2.2.1 skrll
434 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
435 1.1 augustss sed->next = 0;
436 1.253.2.2.2.1 skrll return sed;
437 1.1 augustss }
438 1.1 augustss
439 1.253.2.2.2.1 skrll static inline void
440 1.253.2.2.2.1 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
441 1.1 augustss {
442 1.253.2.2.2.1 skrll
443 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
444 1.253.2.2.2.1 skrll
445 1.1 augustss sed->next = sc->sc_freeeds;
446 1.1 augustss sc->sc_freeeds = sed;
447 1.1 augustss }
448 1.1 augustss
449 1.253.2.2.2.1 skrll void
450 1.253.2.2.2.1 skrll ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
451 1.253.2.2.2.1 skrll {
452 1.253.2.2.2.1 skrll
453 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
454 1.253.2.2.2.1 skrll ohci_free_sed_locked(sc, sed);
455 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
456 1.253.2.2.2.1 skrll }
457 1.253.2.2.2.1 skrll
458 1.1 augustss ohci_soft_td_t *
459 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
460 1.1 augustss {
461 1.1 augustss ohci_soft_td_t *std;
462 1.53 augustss usbd_status err;
463 1.1 augustss int i, offs;
464 1.4 augustss usb_dma_t dma;
465 1.1 augustss
466 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
467 1.240 skrll
468 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
469 1.53 augustss if (sc->sc_freetds == NULL) {
470 1.253.2.2.2.1 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
471 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
472 1.253.2.2.2.1 skrll
473 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
474 1.53 augustss OHCI_TD_ALIGN, &dma);
475 1.53 augustss if (err)
476 1.253.2.2.2.1 skrll return NULL;
477 1.253.2.2.2.1 skrll
478 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
479 1.253.2.2.2.1 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
480 1.39 augustss offs = i * OHCI_STD_SIZE;
481 1.123 augustss std = KERNADDR(&dma, offs);
482 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
483 1.195 bouyer std->dma = dma;
484 1.195 bouyer std->offs = offs;
485 1.1 augustss std->nexttd = sc->sc_freetds;
486 1.1 augustss sc->sc_freetds = std;
487 1.1 augustss }
488 1.1 augustss }
489 1.69 augustss
490 1.1 augustss std = sc->sc_freetds;
491 1.1 augustss sc->sc_freetds = std->nexttd;
492 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
493 1.253.2.2.2.1 skrll
494 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
495 1.83 augustss std->nexttd = NULL;
496 1.83 augustss std->xfer = NULL;
497 1.69 augustss
498 1.253.2.2.2.1 skrll return std;
499 1.1 augustss }
500 1.1 augustss
501 1.1 augustss void
502 1.253.2.2.2.1 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
503 1.1 augustss {
504 1.253.2.2.2.1 skrll
505 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
506 1.253.2.2.2.1 skrll
507 1.1 augustss std->nexttd = sc->sc_freetds;
508 1.1 augustss sc->sc_freetds = std;
509 1.1 augustss }
510 1.1 augustss
511 1.253.2.2.2.1 skrll void
512 1.253.2.2.2.1 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
513 1.48 augustss {
514 1.253.2.2.2.1 skrll
515 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
516 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, std);
517 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
518 1.253.2.2.2.1 skrll }
519 1.253.2.2.2.1 skrll
520 1.253.2.2.2.1 skrll Static int
521 1.253.2.2.2.1 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd)
522 1.253.2.2.2.1 skrll {
523 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
524 1.253.2.2.2.1 skrll uint16_t flags = xfer->ux_flags;
525 1.253.2.2.2.1 skrll
526 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
527 1.253.2.2.2.1 skrll
528 1.253.2.2.2.1 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
529 1.253.2.2.2.1 skrll xfer->ux_pipe->up_dev->ud_addr,
530 1.253.2.2.2.1 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
531 1.253.2.2.2.1 skrll length, xfer->ux_pipe->up_dev->ud_speed);
532 1.253.2.2.2.1 skrll
533 1.253.2.2.2.1 skrll ASSERT_SLEEPABLE();
534 1.253.2.2.2.1 skrll KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
535 1.253.2.2.2.1 skrll
536 1.253.2.2.2.1 skrll size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
537 1.253.2.2.2.1 skrll nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
538 1.253.2.2.2.1 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
539 1.253.2.2.2.1 skrll KM_SLEEP);
540 1.253.2.2.2.1 skrll ox->ox_nstd = nstd;
541 1.253.2.2.2.1 skrll
542 1.253.2.2.2.1 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0);
543 1.253.2.2.2.1 skrll
544 1.253.2.2.2.1 skrll for (size_t j = 0; j < ox->ox_nstd;) {
545 1.253.2.2.2.1 skrll ohci_soft_td_t *cur = ohci_alloc_std(sc);
546 1.253.2.2.2.1 skrll if (cur == NULL)
547 1.253.2.2.2.1 skrll goto nomem;
548 1.253.2.2.2.1 skrll
549 1.253.2.2.2.1 skrll ox->ox_stds[j++] = cur;
550 1.253.2.2.2.1 skrll cur->xfer = xfer;
551 1.253.2.2.2.1 skrll cur->flags = 0;
552 1.253.2.2.2.1 skrll }
553 1.253.2.2.2.1 skrll
554 1.253.2.2.2.1 skrll return 0;
555 1.253.2.2.2.1 skrll
556 1.253.2.2.2.1 skrll nomem:
557 1.253.2.2.2.1 skrll ohci_free_stds(sc, ox);
558 1.253.2.2.2.1 skrll kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd);
559 1.253.2.2.2.1 skrll
560 1.253.2.2.2.1 skrll return ENOMEM;
561 1.253.2.2.2.1 skrll }
562 1.253.2.2.2.1 skrll
563 1.253.2.2.2.1 skrll Static void
564 1.253.2.2.2.1 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
565 1.253.2.2.2.1 skrll {
566 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
567 1.253.2.2.2.1 skrll DPRINTF("ox=%p", ox, 0, 0, 0);
568 1.253.2.2.2.1 skrll
569 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
570 1.253.2.2.2.1 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
571 1.253.2.2.2.1 skrll ohci_soft_td_t *std = ox->ox_stds[i];
572 1.253.2.2.2.1 skrll if (std == NULL)
573 1.253.2.2.2.1 skrll break;
574 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, std);
575 1.253.2.2.2.1 skrll }
576 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
577 1.253.2.2.2.1 skrll }
578 1.253.2.2.2.1 skrll
579 1.253.2.2.2.1 skrll void
580 1.253.2.2.2.1 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
581 1.253.2.2.2.1 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
582 1.253.2.2.2.1 skrll {
583 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
584 1.48 augustss ohci_soft_td_t *next, *cur;
585 1.75 augustss int len, curlen;
586 1.253.2.2.2.1 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
587 1.253.2.2.2.1 skrll uint16_t flags = xfer->ux_flags;
588 1.48 augustss
589 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
590 1.253.2.2.2.1 skrll DPRINTF("start len=%d", alen, 0, 0, 0);
591 1.75 augustss
592 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
593 1.224 mrg
594 1.253.2.2.2.1 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
595 1.253.2.2.2.1 skrll xfer->ux_pipe->up_dev->ud_addr,
596 1.253.2.2.2.1 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
597 1.253.2.2.2.1 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
598 1.253.2.2.2.1 skrll
599 1.253.2.2.2.1 skrll KASSERT(sp);
600 1.253.2.2.2.1 skrll
601 1.253.2.2.2.1 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
602 1.253.2.2.2.1 skrll
603 1.253.2.2.2.1 skrll /*
604 1.253.2.2.2.1 skrll * Assign next for the len == 0 case where we don't go through the
605 1.253.2.2.2.1 skrll * main loop.
606 1.253.2.2.2.1 skrll */
607 1.75 augustss len = alen;
608 1.253.2.2.2.1 skrll cur = next = sp;
609 1.253.2.2.2.1 skrll
610 1.195 bouyer usb_syncmem(dma, 0, len,
611 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
612 1.253.2.2.2.1 skrll const uint32_t tdflags = HTOO32(
613 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
614 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
615 1.61 augustss
616 1.253.2.2.2.1 skrll size_t curoffs = 0;
617 1.253.2.2.2.1 skrll for (size_t j = 1; len != 0;) {
618 1.253.2.2.2.1 skrll if (j == ox->ox_nstd)
619 1.253.2.2.2.1 skrll next = NULL;
620 1.253.2.2.2.1 skrll else
621 1.253.2.2.2.1 skrll next = ox->ox_stds[j++];
622 1.253.2.2.2.1 skrll KASSERT(next != cur);
623 1.48 augustss
624 1.253.2.2.2.1 skrll curlen = 0;
625 1.253.2.2.2.2 skrll const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
626 1.253.2.2.2.1 skrll ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1);
627 1.253.2.2.2.1 skrll
628 1.253.2.2.2.2 skrll const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys);
629 1.253.2.2.2.1 skrll ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys);
630 1.253.2.2.2.1 skrll /*
631 1.253.2.2.2.1 skrll * The OHCI hardware can handle at most one page
632 1.253.2.2.2.1 skrll * crossing per TD
633 1.253.2.2.2.1 skrll */
634 1.253.2.2.2.1 skrll curlen = len;
635 1.253.2.2.2.2 skrll if (sphyspg != ephyspg &&
636 1.253.2.2.2.2 skrll sphyspg + OHCI_PAGE_SIZE != ephyspg) {
637 1.48 augustss /* must use multiple TDs, fill as much as possible. */
638 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
639 1.253.2.2.2.2 skrll OHCI_PAGE_OFFSET(sdataphys);
640 1.78 augustss /* the length must be a multiple of the max size */
641 1.253.2.2.2.1 skrll curlen -= curlen % mps;
642 1.253.2.2.2.2 skrll edataphys = DMAADDR(dma, curoffs + curlen - 1);
643 1.48 augustss }
644 1.253.2.2.2.1 skrll KASSERT(curlen != 0);
645 1.253.2.2.2.1 skrll DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x "
646 1.253.2.2.2.1 skrll "len=%d curlen=%d", sdataphys, edataphys, len, curlen);
647 1.48 augustss
648 1.77 augustss cur->td.td_flags = tdflags;
649 1.253.2.2.2.1 skrll cur->td.td_cbp = HTOO32(sdataphys);
650 1.253.2.2.2.1 skrll cur->td.td_be = HTOO32(edataphys);
651 1.253.2.2.2.1 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
652 1.48 augustss cur->nexttd = next;
653 1.48 augustss cur->len = curlen;
654 1.48 augustss cur->flags = OHCI_ADD_LEN;
655 1.77 augustss cur->xfer = xfer;
656 1.253.2.2.2.1 skrll ohci_hash_add_td(sc, cur);
657 1.253.2.2.2.1 skrll
658 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
659 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
660 1.253.2.2.2.1 skrll
661 1.253.2.2.2.1 skrll curoffs += curlen;
662 1.253.2.2.2.1 skrll len -= curlen;
663 1.253.2.2.2.1 skrll
664 1.253.2.2.2.1 skrll if (len != 0) {
665 1.253.2.2.2.1 skrll KASSERT(next != NULL);
666 1.253.2.2.2.1 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
667 1.253.2.2.2.1 skrll cur = next;
668 1.253.2.2.2.1 skrll }
669 1.48 augustss }
670 1.253.2.2.2.1 skrll cur->td.td_flags |=
671 1.253.2.2.2.1 skrll HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
672 1.253.2.2.2.1 skrll
673 1.253.2.2.2.1 skrll if (!rd &&
674 1.253.2.2.2.1 skrll (flags & USBD_FORCE_SHORT_XFER) &&
675 1.253.2.2.2.1 skrll alen % mps == 0) {
676 1.61 augustss /* Force a 0 length transfer at the end. */
677 1.75 augustss
678 1.253.2.2.2.1 skrll KASSERT(next != NULL);
679 1.75 augustss cur = next;
680 1.61 augustss
681 1.77 augustss cur->td.td_flags = tdflags;
682 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
683 1.253.2.2.2.1 skrll cur->td.td_nexttd = 0;
684 1.75 augustss cur->td.td_be = ~0;
685 1.253.2.2.2.1 skrll cur->nexttd = NULL;
686 1.61 augustss cur->len = 0;
687 1.61 augustss cur->flags = 0;
688 1.77 augustss cur->xfer = xfer;
689 1.253.2.2.2.1 skrll ohci_hash_add_td(sc, cur);
690 1.253.2.2.2.1 skrll
691 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
692 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
693 1.253.2.2.2.1 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
694 1.61 augustss }
695 1.77 augustss *ep = cur;
696 1.48 augustss }
697 1.48 augustss
698 1.60 augustss ohci_soft_itd_t *
699 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
700 1.60 augustss {
701 1.60 augustss ohci_soft_itd_t *sitd;
702 1.60 augustss usbd_status err;
703 1.224 mrg int i, offs;
704 1.60 augustss usb_dma_t dma;
705 1.60 augustss
706 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
707 1.253.2.2.2.1 skrll
708 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
709 1.60 augustss if (sc->sc_freeitds == NULL) {
710 1.253.2.2.2.1 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
711 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
712 1.253.2.2.2.1 skrll
713 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
714 1.83 augustss OHCI_ITD_ALIGN, &dma);
715 1.60 augustss if (err)
716 1.253.2.2.2.1 skrll return NULL;
717 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
718 1.253.2.2.2.1 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
719 1.83 augustss offs = i * OHCI_SITD_SIZE;
720 1.123 augustss sitd = KERNADDR(&dma, offs);
721 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
722 1.195 bouyer sitd->dma = dma;
723 1.195 bouyer sitd->offs = offs;
724 1.60 augustss sitd->nextitd = sc->sc_freeitds;
725 1.60 augustss sc->sc_freeitds = sitd;
726 1.60 augustss }
727 1.60 augustss }
728 1.83 augustss
729 1.60 augustss sitd = sc->sc_freeitds;
730 1.60 augustss sc->sc_freeitds = sitd->nextitd;
731 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
732 1.253.2.2.2.1 skrll
733 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
734 1.83 augustss sitd->nextitd = NULL;
735 1.83 augustss sitd->xfer = NULL;
736 1.83 augustss
737 1.83 augustss #ifdef DIAGNOSTIC
738 1.253.2.2.2.1 skrll sitd->isdone = true;
739 1.83 augustss #endif
740 1.83 augustss
741 1.253.2.2.2.1 skrll return sitd;
742 1.60 augustss }
743 1.60 augustss
744 1.253.2.2.2.1 skrll Static void
745 1.253.2.2.2.1 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
746 1.60 augustss {
747 1.83 augustss
748 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
749 1.253.2.2.2.1 skrll DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
750 1.83 augustss
751 1.253.2.2.2.1 skrll KASSERT(sitd->isdone);
752 1.83 augustss #ifdef DIAGNOSTIC
753 1.134 toshii /* Warn double free */
754 1.253.2.2.2.1 skrll sitd->isdone = false;
755 1.83 augustss #endif
756 1.83 augustss
757 1.60 augustss sitd->nextitd = sc->sc_freeitds;
758 1.60 augustss sc->sc_freeitds = sitd;
759 1.60 augustss }
760 1.60 augustss
761 1.253.2.2.2.1 skrll void
762 1.253.2.2.2.1 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
763 1.253.2.2.2.1 skrll {
764 1.253.2.2.2.1 skrll
765 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
766 1.253.2.2.2.1 skrll
767 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
768 1.253.2.2.2.1 skrll ohci_free_sitd_locked(sc, sitd);
769 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
770 1.253.2.2.2.1 skrll }
771 1.253.2.2.2.1 skrll
772 1.253.2.2.2.1 skrll int
773 1.91 augustss ohci_init(ohci_softc_t *sc)
774 1.1 augustss {
775 1.1 augustss ohci_soft_ed_t *sed, *psed;
776 1.53 augustss usbd_status err;
777 1.1 augustss int i;
778 1.253.2.2.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
779 1.253.2.2.2.1 skrll
780 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
781 1.16 augustss
782 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
783 1.199 jmcneill
784 1.198 cegger sc->sc_hcca = NULL;
785 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
786 1.224 mrg
787 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
788 1.253.2.2.2.1 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
789 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
790 1.224 mrg
791 1.253.2.2.2.1 skrll sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
792 1.224 mrg ohci_rhsc_softint, sc);
793 1.198 cegger
794 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
795 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
796 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
797 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
798 1.198 cegger
799 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
800 1.232 christos "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
801 1.198 cegger
802 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
803 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
804 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
805 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
806 1.55 augustss
807 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
808 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
809 1.253.2.2.2.1 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
810 1.253.2.2.2.1 skrll return -1;
811 1.1 augustss }
812 1.253.2.2.2.1 skrll sc->sc_bus.ub_revision = USBREV_1_0;
813 1.253.2.2.2.1 skrll sc->sc_bus.ub_usedma = true;
814 1.153 fvdl
815 1.73 augustss /* XXX determine alignment by R/W */
816 1.1 augustss /* Allocate the HCCA area. */
817 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
818 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
819 1.198 cegger if (err) {
820 1.198 cegger sc->sc_hcca = NULL;
821 1.198 cegger return err;
822 1.198 cegger }
823 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
824 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
825 1.1 augustss
826 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
827 1.1 augustss
828 1.60 augustss /* Allocate dummy ED that starts the control list. */
829 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
830 1.53 augustss if (sc->sc_ctrl_head == NULL) {
831 1.253.2.2.2.1 skrll err = ENOMEM;
832 1.1 augustss goto bad1;
833 1.1 augustss }
834 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
835 1.34 augustss
836 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
837 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
838 1.53 augustss if (sc->sc_bulk_head == NULL) {
839 1.253.2.2.2.1 skrll err = ENOMEM;
840 1.1 augustss goto bad2;
841 1.1 augustss }
842 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
843 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
844 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
845 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
846 1.1 augustss
847 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
848 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
849 1.60 augustss if (sc->sc_isoc_head == NULL) {
850 1.253.2.2.2.1 skrll err = ENOMEM;
851 1.60 augustss goto bad3;
852 1.60 augustss }
853 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
854 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
855 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
856 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
857 1.60 augustss
858 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
859 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
860 1.1 augustss sed = ohci_alloc_sed(sc);
861 1.53 augustss if (sed == NULL) {
862 1.1 augustss while (--i >= 0)
863 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
864 1.253.2.2.2.1 skrll err = ENOMEM;
865 1.60 augustss goto bad4;
866 1.1 augustss }
867 1.1 augustss /* All ED fields are set to 0. */
868 1.1 augustss sc->sc_eds[i] = sed;
869 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
870 1.60 augustss if (i != 0)
871 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
872 1.60 augustss else
873 1.60 augustss psed= sc->sc_isoc_head;
874 1.60 augustss sed->next = psed;
875 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
876 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
877 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
878 1.1 augustss }
879 1.120 augustss /*
880 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
881 1.1 augustss * the tree set up properly to spread the interrupts.
882 1.1 augustss */
883 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
884 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
885 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
886 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
887 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
888 1.1 augustss
889 1.73 augustss #ifdef OHCI_DEBUG
890 1.253.2.2.2.1 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
891 1.253.2.2.2.1 skrll if (ohcidebug >= 15) {
892 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
893 1.253.2.2.2.1 skrll DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
894 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
895 1.73 augustss }
896 1.253.2.2.2.1 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
897 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
898 1.73 augustss }
899 1.253.2.2.2.1 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
900 1.73 augustss #endif
901 1.73 augustss
902 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
903 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
904 1.161 augustss rwc = ctl & OHCI_RWC;
905 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
906 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
907 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
908 1.161 augustss
909 1.1 augustss /* Determine in what context we are running. */
910 1.1 augustss if (ctl & OHCI_IR) {
911 1.1 augustss /* SMM active, request change */
912 1.253.2.2.2.1 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
913 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
914 1.160 augustss (OHCI_OC | OHCI_MIE))
915 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
916 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
917 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
918 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
919 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
920 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
921 1.1 augustss }
922 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
923 1.1 augustss if ((ctl & OHCI_IR) == 0) {
924 1.199 jmcneill aprint_error_dev(sc->sc_dev,
925 1.199 jmcneill "SMM does not respond, resetting\n");
926 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
927 1.1 augustss goto reset;
928 1.1 augustss }
929 1.103 augustss #if 0
930 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
931 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
932 1.1 augustss /* BIOS started controller. */
933 1.253.2.2.2.1 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
934 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
935 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
936 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
937 1.1 augustss }
938 1.103 augustss #endif
939 1.1 augustss } else {
940 1.253.2.2.2.1 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
941 1.1 augustss reset:
942 1.1 augustss /* Controller was cold started. */
943 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
944 1.1 augustss }
945 1.1 augustss
946 1.16 augustss /*
947 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
948 1.25 augustss * without it some controllers do not start.
949 1.16 augustss */
950 1.253.2.2.2.1 skrll DPRINTF("sc %p: resetting", sc, 0, 0, 0);
951 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
952 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
953 1.16 augustss
954 1.1 augustss /* We now own the host controller and the bus has been reset. */
955 1.1 augustss
956 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
957 1.1 augustss /* Nominal time for a reset is 10 us. */
958 1.1 augustss for (i = 0; i < 10; i++) {
959 1.1 augustss delay(10);
960 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
961 1.1 augustss if (!hcr)
962 1.1 augustss break;
963 1.1 augustss }
964 1.1 augustss if (hcr) {
965 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
966 1.253.2.2.2.1 skrll err = EIO;
967 1.60 augustss goto bad5;
968 1.1 augustss }
969 1.52 augustss #ifdef OHCI_DEBUG
970 1.253.2.2.2.1 skrll if (ohcidebug >= 15)
971 1.1 augustss ohci_dumpregs(sc);
972 1.1 augustss #endif
973 1.1 augustss
974 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
975 1.1 augustss
976 1.1 augustss /* Set up HC registers. */
977 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
978 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
979 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
980 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
981 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
982 1.55 augustss /* switch on desired functional features */
983 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
984 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
985 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
986 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
987 1.1 augustss /* And finally start it! */
988 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
989 1.1 augustss
990 1.1 augustss /*
991 1.1 augustss * The controller is now OPERATIONAL. Set a some final
992 1.1 augustss * registers that should be set earlier, but that the
993 1.1 augustss * controller ignores when in the SUSPEND state.
994 1.1 augustss */
995 1.161 augustss ival = OHCI_GET_IVAL(fm);
996 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
997 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
998 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
999 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
1000 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
1001 1.1 augustss
1002 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
1003 1.249 skrll /* no overcurrent protection */
1004 1.249 skrll desca |= OHCI_NOCP;
1005 1.249 skrll /*
1006 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1007 1.249 skrll * that
1008 1.249 skrll * - ports are always power switched
1009 1.249 skrll * - don't wait for powered root hub port
1010 1.249 skrll */
1011 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1012 1.249 skrll }
1013 1.249 skrll
1014 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1015 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1016 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1017 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1018 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1019 1.1 augustss
1020 1.85 augustss /*
1021 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1022 1.85 augustss * otherwise it will occasionally report 0 ports.
1023 1.85 augustss */
1024 1.145 augustss sc->sc_noport = 0;
1025 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1026 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1027 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1028 1.145 augustss }
1029 1.1 augustss
1030 1.52 augustss #ifdef OHCI_DEBUG
1031 1.253.2.2.2.1 skrll if (ohcidebug >= 5)
1032 1.1 augustss ohci_dumpregs(sc);
1033 1.1 augustss #endif
1034 1.120 augustss
1035 1.1 augustss /* Set up the bus struct. */
1036 1.253.2.2.2.1 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1037 1.253.2.2.2.1 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1038 1.1 augustss
1039 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1040 1.59 augustss
1041 1.167 augustss /* Finally, turn on interrupts. */
1042 1.253.2.2.2.1 skrll DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1043 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1044 1.167 augustss
1045 1.253.2.2.2.1 skrll return 0;
1046 1.1 augustss
1047 1.60 augustss bad5:
1048 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1049 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1050 1.60 augustss bad4:
1051 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1052 1.1 augustss bad3:
1053 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1054 1.144 augustss bad2:
1055 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1056 1.1 augustss bad1:
1057 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1058 1.198 cegger sc->sc_hcca = NULL;
1059 1.253.2.2.2.1 skrll return err;
1060 1.62 augustss }
1061 1.62 augustss
1062 1.253.2.2.2.1 skrll struct usbd_xfer *
1063 1.253.2.2.2.1 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1064 1.62 augustss {
1065 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1066 1.253.2.2.2.1 skrll struct usbd_xfer *xfer;
1067 1.62 augustss
1068 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
1069 1.118 augustss if (xfer != NULL) {
1070 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1071 1.118 augustss #ifdef DIAGNOSTIC
1072 1.253.2.2.2.1 skrll xfer->ux_state = XFER_BUSY;
1073 1.118 augustss #endif
1074 1.118 augustss }
1075 1.253.2.2.2.1 skrll return xfer;
1076 1.62 augustss }
1077 1.62 augustss
1078 1.62 augustss void
1079 1.253.2.2.2.1 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1080 1.62 augustss {
1081 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1082 1.62 augustss
1083 1.253.2.2.2.1 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
1084 1.253.2.2.2.1 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1085 1.118 augustss #ifdef DIAGNOSTIC
1086 1.253.2.2.2.1 skrll xfer->ux_state = XFER_FREE;
1087 1.118 augustss #endif
1088 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1089 1.42 augustss }
1090 1.42 augustss
1091 1.224 mrg Static void
1092 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1093 1.224 mrg {
1094 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1095 1.224 mrg
1096 1.224 mrg *lock = &sc->sc_lock;
1097 1.224 mrg }
1098 1.224 mrg
1099 1.59 augustss /*
1100 1.59 augustss * Shut down the controller when the system is going down.
1101 1.59 augustss */
1102 1.188 dyoung bool
1103 1.188 dyoung ohci_shutdown(device_t self, int flags)
1104 1.59 augustss {
1105 1.188 dyoung ohci_softc_t *sc = device_private(self);
1106 1.59 augustss
1107 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1108 1.253.2.2.2.1 skrll
1109 1.253.2.2.2.1 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1110 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1111 1.188 dyoung return true;
1112 1.59 augustss }
1113 1.59 augustss
1114 1.185 jmcneill bool
1115 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1116 1.33 augustss {
1117 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1118 1.185 jmcneill uint32_t ctl;
1119 1.33 augustss
1120 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1121 1.253.2.2.2.1 skrll sc->sc_bus.ub_usepolling++;
1122 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1123 1.224 mrg
1124 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1125 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1126 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1127 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1128 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1129 1.185 jmcneill sc->sc_bulk_head->physaddr);
1130 1.185 jmcneill if (sc->sc_intre)
1131 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1132 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1133 1.185 jmcneill if (sc->sc_control)
1134 1.185 jmcneill ctl = sc->sc_control;
1135 1.185 jmcneill else
1136 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1137 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1138 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1139 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1140 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1141 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1142 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1143 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1144 1.224 mrg
1145 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1146 1.253.2.2.2.1 skrll sc->sc_bus.ub_usepolling--;
1147 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1148 1.185 jmcneill
1149 1.185 jmcneill return true;
1150 1.185 jmcneill }
1151 1.185 jmcneill
1152 1.185 jmcneill bool
1153 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1154 1.185 jmcneill {
1155 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1156 1.185 jmcneill uint32_t ctl;
1157 1.95 augustss
1158 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1159 1.253.2.2.2.1 skrll sc->sc_bus.ub_usepolling++;
1160 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1161 1.224 mrg
1162 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1163 1.185 jmcneill if (sc->sc_control == 0) {
1164 1.185 jmcneill /*
1165 1.185 jmcneill * Preserve register values, in case that BIOS
1166 1.185 jmcneill * does not recover them.
1167 1.185 jmcneill */
1168 1.185 jmcneill sc->sc_control = ctl;
1169 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1170 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1171 1.95 augustss }
1172 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1173 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1174 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1175 1.224 mrg
1176 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1177 1.253.2.2.2.1 skrll sc->sc_bus.ub_usepolling--;
1178 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1179 1.185 jmcneill
1180 1.185 jmcneill return true;
1181 1.33 augustss }
1182 1.33 augustss
1183 1.52 augustss #ifdef OHCI_DEBUG
1184 1.1 augustss void
1185 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1186 1.1 augustss {
1187 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1188 1.253.2.2.2.1 skrll
1189 1.253.2.2.2.1 skrll DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
1190 1.41 augustss OREAD4(sc, OHCI_REVISION),
1191 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1192 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1193 1.253.2.2.2.1 skrll DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x",
1194 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1195 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1196 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1197 1.253.2.2.2.1 skrll DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
1198 1.41 augustss OREAD4(sc, OHCI_HCCA),
1199 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1200 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1201 1.253.2.2.2.1 skrll DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
1202 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1203 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1204 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1205 1.253.2.2.2.1 skrll DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x",
1206 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1207 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1208 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1209 1.253.2.2.2.1 skrll DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
1210 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1211 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1212 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1213 1.253.2.2.2.1 skrll DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x",
1214 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1215 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1216 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1217 1.253.2.2.2.1 skrll DPRINTF(" port1=0x%08x port2=0x%08x",
1218 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1219 1.253.2.2.2.1 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1220 1.253.2.2.2.1 skrll DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x",
1221 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1222 1.253.2.2.2.1 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1223 1.1 augustss }
1224 1.1 augustss #endif
1225 1.1 augustss
1226 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1227 1.53 augustss
1228 1.1 augustss int
1229 1.91 augustss ohci_intr(void *p)
1230 1.1 augustss {
1231 1.1 augustss ohci_softc_t *sc = p;
1232 1.224 mrg int ret = 0;
1233 1.111 augustss
1234 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1235 1.253.2.2.2.1 skrll
1236 1.224 mrg if (sc == NULL)
1237 1.253.2.2.2.1 skrll return 0;
1238 1.53 augustss
1239 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1240 1.224 mrg
1241 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1242 1.224 mrg goto done;
1243 1.224 mrg
1244 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1245 1.253.2.2.2.1 skrll if (sc->sc_bus.ub_usepolling) {
1246 1.253.2.2.2.1 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1247 1.154 joff /* for level triggered intrs, should do something to ack */
1248 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1249 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1250 1.155 perry
1251 1.224 mrg goto done;
1252 1.57 augustss }
1253 1.53 augustss
1254 1.224 mrg ret = ohci_intr1(sc);
1255 1.224 mrg
1256 1.224 mrg done:
1257 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1258 1.224 mrg return ret;
1259 1.53 augustss }
1260 1.53 augustss
1261 1.82 augustss Static int
1262 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1263 1.53 augustss {
1264 1.253.2.2.2.1 skrll uint32_t intrs, eintrs;
1265 1.1 augustss
1266 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1267 1.105 augustss
1268 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1269 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1270 1.15 augustss #ifdef DIAGNOSTIC
1271 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1272 1.15 augustss #endif
1273 1.253.2.2.2.1 skrll return 0;
1274 1.15 augustss }
1275 1.15 augustss
1276 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1277 1.224 mrg
1278 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1279 1.1 augustss if (!intrs)
1280 1.253.2.2.2.1 skrll return 0;
1281 1.55 augustss
1282 1.253.2.2.2.1 skrll /* Acknowledge */
1283 1.253.2.2.2.1 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1284 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1285 1.253.2.2.2.1 skrll DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
1286 1.253.2.2.2.1 skrll DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
1287 1.253.2.2.2.1 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1288 1.253.2.2.2.1 skrll sc->sc_eintrs);
1289 1.211 matt
1290 1.211 matt if (!eintrs) {
1291 1.253.2.2.2.1 skrll return 0;
1292 1.211 matt }
1293 1.1 augustss
1294 1.1 augustss if (eintrs & OHCI_SO) {
1295 1.100 augustss sc->sc_overrun_cnt++;
1296 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1297 1.100 augustss printf("%s: %u scheduling overruns\n",
1298 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1299 1.100 augustss sc->sc_overrun_cnt = 0;
1300 1.100 augustss }
1301 1.1 augustss /* XXX do what */
1302 1.106 augustss eintrs &= ~OHCI_SO;
1303 1.1 augustss }
1304 1.1 augustss if (eintrs & OHCI_WDH) {
1305 1.157 mycroft /*
1306 1.157 mycroft * We block the interrupt below, and reenable it later from
1307 1.157 mycroft * ohci_softintr().
1308 1.157 mycroft */
1309 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1310 1.1 augustss }
1311 1.1 augustss if (eintrs & OHCI_RD) {
1312 1.253.2.2.2.1 skrll DPRINTFN(5, "resume detect", sc, 0, 0, 0);
1313 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1314 1.1 augustss /* XXX process resume detect */
1315 1.1 augustss }
1316 1.1 augustss if (eintrs & OHCI_UE) {
1317 1.253.2.2.2.1 skrll DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0);
1318 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1319 1.190 drochner device_xname(sc->sc_dev));
1320 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1321 1.1 augustss /* XXX what else */
1322 1.1 augustss }
1323 1.1 augustss if (eintrs & OHCI_RHSC) {
1324 1.120 augustss /*
1325 1.157 mycroft * We block the interrupt below, and reenable it later from
1326 1.157 mycroft * a timeout.
1327 1.1 augustss */
1328 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1329 1.1 augustss }
1330 1.1 augustss
1331 1.106 augustss if (eintrs != 0) {
1332 1.157 mycroft /* Block unprocessed interrupts. */
1333 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1334 1.106 augustss sc->sc_eintrs &= ~eintrs;
1335 1.253.2.2.2.1 skrll DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0);
1336 1.106 augustss }
1337 1.1 augustss
1338 1.253.2.2.2.1 skrll return 1;
1339 1.1 augustss }
1340 1.1 augustss
1341 1.1 augustss void
1342 1.104 augustss ohci_rhsc_enable(void *v_sc)
1343 1.104 augustss {
1344 1.104 augustss ohci_softc_t *sc = v_sc;
1345 1.104 augustss
1346 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1347 1.253.2.2.2.1 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1348 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1349 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1350 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1351 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1352 1.1 augustss }
1353 1.1 augustss
1354 1.52 augustss #ifdef OHCI_DEBUG
1355 1.166 drochner const char *ohci_cc_strs[] = {
1356 1.13 augustss "NO_ERROR",
1357 1.13 augustss "CRC",
1358 1.13 augustss "BIT_STUFFING",
1359 1.13 augustss "DATA_TOGGLE_MISMATCH",
1360 1.13 augustss "STALL",
1361 1.13 augustss "DEVICE_NOT_RESPONDING",
1362 1.13 augustss "PID_CHECK_FAILURE",
1363 1.13 augustss "UNEXPECTED_PID",
1364 1.13 augustss "DATA_OVERRUN",
1365 1.13 augustss "DATA_UNDERRUN",
1366 1.13 augustss "BUFFER_OVERRUN",
1367 1.13 augustss "BUFFER_UNDERRUN",
1368 1.67 augustss "reserved",
1369 1.67 augustss "reserved",
1370 1.67 augustss "NOT_ACCESSED",
1371 1.13 augustss "NOT_ACCESSED",
1372 1.13 augustss };
1373 1.13 augustss #endif
1374 1.13 augustss
1375 1.1 augustss void
1376 1.157 mycroft ohci_softintr(void *v)
1377 1.83 augustss {
1378 1.190 drochner struct usbd_bus *bus = v;
1379 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1380 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1381 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1382 1.253.2.2.2.1 skrll struct usbd_xfer *xfer;
1383 1.157 mycroft struct ohci_pipe *opipe;
1384 1.224 mrg int len, cc;
1385 1.157 mycroft int i, j, actlen, iframes, uedir;
1386 1.157 mycroft ohci_physaddr_t done;
1387 1.157 mycroft
1388 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1389 1.224 mrg
1390 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1391 1.157 mycroft
1392 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1393 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1394 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1395 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1396 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1397 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1398 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1399 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1400 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1401 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1402 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1403 1.83 augustss
1404 1.83 augustss /* Reverse the done list. */
1405 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1406 1.83 augustss std = ohci_hash_find_td(sc, done);
1407 1.83 augustss if (std != NULL) {
1408 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1409 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1410 1.83 augustss std->dnext = sdone;
1411 1.168 augustss done = O32TOH(std->td.td_nexttd);
1412 1.83 augustss sdone = std;
1413 1.253.2.2.2.1 skrll DPRINTFN(10, "add TD %p", std, 0, 0, 0);
1414 1.83 augustss continue;
1415 1.83 augustss }
1416 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1417 1.83 augustss if (sitd != NULL) {
1418 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1419 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1420 1.83 augustss sitd->dnext = sidone;
1421 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1422 1.83 augustss sidone = sitd;
1423 1.253.2.2.2.1 skrll DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
1424 1.83 augustss continue;
1425 1.83 augustss }
1426 1.253.2.2.2.1 skrll DPRINTFN(10, "addr %p not found", done, 0, 0, 0);
1427 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1428 1.218 jmcneill (u_long)done);
1429 1.218 jmcneill break;
1430 1.83 augustss }
1431 1.83 augustss
1432 1.253.2.2.2.1 skrll DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
1433 1.253.2.2.2.1 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1434 1.52 augustss #ifdef OHCI_DEBUG
1435 1.253.2.2.2.1 skrll if (ohcidebug >= 10) {
1436 1.234 skrll for (std = sdone; std; std = std->dnext)
1437 1.253.2.2.2.1 skrll ohci_dump_td(sc, std);
1438 1.1 augustss }
1439 1.1 augustss #endif
1440 1.253.2.2.2.1 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1441 1.1 augustss
1442 1.48 augustss for (std = sdone; std; std = stdnext) {
1443 1.53 augustss xfer = std->xfer;
1444 1.48 augustss stdnext = std->dnext;
1445 1.253.2.2.2.1 skrll DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer,
1446 1.253.2.2.2.1 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1447 1.71 augustss if (xfer == NULL) {
1448 1.117 augustss /*
1449 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1450 1.71 augustss * with this TD. It is tailp that happened to end up on
1451 1.71 augustss * the done queue.
1452 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1453 1.71 augustss */
1454 1.71 augustss continue;
1455 1.71 augustss }
1456 1.253.2.2.2.1 skrll if (xfer->ux_status == USBD_CANCELLED ||
1457 1.253.2.2.2.1 skrll xfer->ux_status == USBD_TIMEOUT) {
1458 1.253.2.2.2.1 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1459 1.38 augustss /* Handled by abort routine. */
1460 1.83 augustss continue;
1461 1.83 augustss }
1462 1.253.2.2.2.1 skrll callout_stop(&xfer->ux_callout);
1463 1.141 mycroft
1464 1.141 mycroft len = std->len;
1465 1.141 mycroft if (std->td.td_cbp != 0)
1466 1.168 augustss len -= O32TOH(std->td.td_be) -
1467 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1468 1.253.2.2.2.1 skrll DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
1469 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1470 1.253.2.2.2.1 skrll xfer->ux_actlen += len;
1471 1.141 mycroft
1472 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1473 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1474 1.253.2.2.2.1 skrll ohci_hash_rem_td(sc, std);
1475 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1476 1.253.2.2.2.1 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1477 1.53 augustss usb_transfer_complete(xfer);
1478 1.21 augustss }
1479 1.1 augustss } else {
1480 1.48 augustss /*
1481 1.48 augustss * Endpoint is halted. First unlink all the TDs
1482 1.48 augustss * belonging to the failed transfer, and then restart
1483 1.48 augustss * the endpoint.
1484 1.48 augustss */
1485 1.1 augustss ohci_soft_td_t *p, *n;
1486 1.253.2.2.2.1 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1487 1.48 augustss
1488 1.253.2.2.2.1 skrll DPRINTFN(10, "error cc=%d", cc, 0, 0, 0);
1489 1.48 augustss
1490 1.253.2.2.2.1 skrll /* remove xfer's TDs from the hash */
1491 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1492 1.1 augustss n = p->nexttd;
1493 1.253.2.2.2.1 skrll ohci_hash_rem_td(sc, p);
1494 1.1 augustss }
1495 1.48 augustss
1496 1.253.2.2.2.1 skrll ohci_soft_ed_t *sed = opipe->sed;
1497 1.253.2.2.2.1 skrll
1498 1.253.2.2.2.1 skrll /* clear halt and TD chain */
1499 1.253.2.2.2.1 skrll sed->ed.ed_headp = HTOO32(p->physaddr);
1500 1.253.2.2.2.1 skrll usb_syncmem(&sed->dma,
1501 1.253.2.2.2.1 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1502 1.253.2.2.2.1 skrll sizeof(sed->ed.ed_headp),
1503 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1504 1.253.2.2.2.1 skrll
1505 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1506 1.48 augustss
1507 1.253.2.2.2.1 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1508 1.253.2.2.2.1 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1509 1.253.2.2.2.1 skrll else if (cc == OHCI_CC_STALL)
1510 1.253.2.2.2.1 skrll xfer->ux_status = USBD_STALLED;
1511 1.1 augustss else
1512 1.253.2.2.2.1 skrll xfer->ux_status = USBD_IOERROR;
1513 1.53 augustss usb_transfer_complete(xfer);
1514 1.1 augustss }
1515 1.1 augustss }
1516 1.253.2.2.2.1 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1517 1.83 augustss #ifdef OHCI_DEBUG
1518 1.253.2.2.2.1 skrll if (ohcidebug >= 10) {
1519 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1520 1.253.2.2.2.1 skrll ohci_dump_itd(sc, sitd);
1521 1.83 augustss }
1522 1.83 augustss #endif
1523 1.253.2.2.2.1 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1524 1.83 augustss
1525 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1526 1.83 augustss xfer = sitd->xfer;
1527 1.83 augustss sitdnext = sitd->dnext;
1528 1.253.2.2.2.1 skrll DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
1529 1.253.2.2.2.1 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1530 1.83 augustss if (xfer == NULL)
1531 1.83 augustss continue;
1532 1.253.2.2.2.1 skrll if (xfer->ux_status == USBD_CANCELLED ||
1533 1.253.2.2.2.1 skrll xfer->ux_status == USBD_TIMEOUT) {
1534 1.253.2.2.2.1 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1535 1.83 augustss /* Handled by abort routine. */
1536 1.83 augustss continue;
1537 1.83 augustss }
1538 1.253.2.2.2.1 skrll KASSERT(!sitd->isdone);
1539 1.83 augustss #ifdef DIAGNOSTIC
1540 1.253.2.2.2.1 skrll sitd->isdone = true;
1541 1.83 augustss #endif
1542 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1543 1.134 toshii ohci_soft_itd_t *next;
1544 1.134 toshii
1545 1.253.2.2.2.1 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1546 1.253.2.2.2.1 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1547 1.253.2.2.2.1 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1548 1.134 toshii bEndpointAddress);
1549 1.253.2.2.2.1 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1550 1.134 toshii actlen = 0;
1551 1.253.2.2.2.1 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1552 1.134 toshii sitd = next) {
1553 1.134 toshii next = sitd->nextitd;
1554 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1555 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1556 1.253.2.2.2.1 skrll xfer->ux_status = USBD_IOERROR;
1557 1.134 toshii /* For input, update frlengths with actual */
1558 1.134 toshii /* XXX anything necessary for output? */
1559 1.134 toshii if (uedir == UE_DIR_IN &&
1560 1.253.2.2.2.1 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1561 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1562 1.135 toshii sitd->itd.itd_flags));
1563 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1564 1.168 augustss len = O16TOH(sitd->
1565 1.134 toshii itd.itd_offset[j]);
1566 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1567 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1568 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1569 1.158 toshii len = 0;
1570 1.158 toshii else
1571 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1572 1.253.2.2.2.1 skrll xfer->ux_frlengths[i] = len;
1573 1.134 toshii actlen += len;
1574 1.134 toshii }
1575 1.134 toshii }
1576 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1577 1.134 toshii break;
1578 1.253.2.2.2.1 skrll ohci_hash_rem_itd(sc, sitd);
1579 1.253.2.2.2.1 skrll
1580 1.83 augustss }
1581 1.253.2.2.2.1 skrll ohci_hash_rem_itd(sc, sitd);
1582 1.134 toshii if (uedir == UE_DIR_IN &&
1583 1.253.2.2.2.1 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1584 1.253.2.2.2.1 skrll xfer->ux_actlen = actlen;
1585 1.253.2.2.2.1 skrll xfer->ux_hcpriv = NULL;
1586 1.134 toshii
1587 1.83 augustss usb_transfer_complete(xfer);
1588 1.83 augustss }
1589 1.83 augustss }
1590 1.83 augustss
1591 1.119 augustss if (sc->sc_softwake) {
1592 1.119 augustss sc->sc_softwake = 0;
1593 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1594 1.119 augustss }
1595 1.119 augustss
1596 1.253.2.2.2.1 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1597 1.1 augustss }
1598 1.1 augustss
1599 1.1 augustss void
1600 1.253.2.2.2.1 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1601 1.1 augustss {
1602 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1603 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1604 1.253.2.2.2.1 skrll int len = UGETW(xfer->ux_request.wLength);
1605 1.253.2.2.2.1 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1606 1.195 bouyer
1607 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1608 1.253.2.2.2.1 skrll DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
1609 1.1 augustss
1610 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1611 1.253.2.2.2.1 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1612 1.224 mrg
1613 1.195 bouyer if (len)
1614 1.253.2.2.2.1 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1615 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1616 1.253.2.2.2.1 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1617 1.253.2.2.2.1 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1618 1.1 augustss }
1619 1.1 augustss
1620 1.1 augustss void
1621 1.253.2.2.2.1 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1622 1.1 augustss {
1623 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1624 1.195 bouyer int isread =
1625 1.253.2.2.2.1 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1626 1.1 augustss
1627 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1628 1.253.2.2.2.1 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1629 1.1 augustss
1630 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1631 1.224 mrg
1632 1.253.2.2.2.1 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1633 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1634 1.1 augustss }
1635 1.1 augustss
1636 1.1 augustss void
1637 1.253.2.2.2.1 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1638 1.3 augustss {
1639 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1640 1.253.2.2.2.1 skrll
1641 1.195 bouyer int isread =
1642 1.253.2.2.2.1 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1643 1.195 bouyer
1644 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1645 1.224 mrg
1646 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1647 1.253.2.2.2.1 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1648 1.253.2.2.2.1 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1649 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1650 1.3 augustss }
1651 1.3 augustss
1652 1.224 mrg Static void
1653 1.224 mrg ohci_rhsc_softint(void *arg)
1654 1.224 mrg {
1655 1.224 mrg ohci_softc_t *sc = arg;
1656 1.224 mrg
1657 1.224 mrg mutex_enter(&sc->sc_lock);
1658 1.224 mrg
1659 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1660 1.224 mrg
1661 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1662 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1663 1.224 mrg
1664 1.224 mrg mutex_exit(&sc->sc_lock);
1665 1.224 mrg }
1666 1.224 mrg
1667 1.3 augustss void
1668 1.253.2.2.2.1 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1669 1.1 augustss {
1670 1.1 augustss u_char *p;
1671 1.1 augustss int i, m;
1672 1.243 martin int hstatus __unused;
1673 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1674 1.1 augustss
1675 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1676 1.224 mrg
1677 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1678 1.253.2.2.2.1 skrll DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0);
1679 1.1 augustss
1680 1.53 augustss if (xfer == NULL) {
1681 1.1 augustss /* Just ignore the change. */
1682 1.1 augustss return;
1683 1.1 augustss }
1684 1.1 augustss
1685 1.253.2.2.2.1 skrll p = xfer->ux_buf;
1686 1.253.2.2.2.1 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1687 1.253.2.2.2.1 skrll memset(p, 0, xfer->ux_length);
1688 1.1 augustss for (i = 1; i <= m; i++) {
1689 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1690 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1691 1.1 augustss p[i/8] |= 1 << (i%8);
1692 1.1 augustss }
1693 1.253.2.2.2.1 skrll DPRINTF("change=0x%02x", *p, 0, 0, 0);
1694 1.253.2.2.2.1 skrll xfer->ux_actlen = xfer->ux_length;
1695 1.253.2.2.2.1 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1696 1.1 augustss
1697 1.53 augustss usb_transfer_complete(xfer);
1698 1.38 augustss }
1699 1.38 augustss
1700 1.38 augustss void
1701 1.253.2.2.2.1 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1702 1.1 augustss {
1703 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1704 1.15 augustss
1705 1.253.2.2.2.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
1706 1.224 mrg
1707 1.253.2.2.2.1 skrll KASSERT(sc->sc_intrxfer == xfer);
1708 1.253.2.2.2.1 skrll sc->sc_intrxfer = NULL;
1709 1.5 augustss }
1710 1.5 augustss
1711 1.5 augustss void
1712 1.91 augustss ohci_poll(struct usbd_bus *bus)
1713 1.5 augustss {
1714 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1715 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1716 1.253.2.2.2.1 skrll
1717 1.105 augustss #ifdef OHCI_DEBUG
1718 1.105 augustss static int last;
1719 1.105 augustss int new;
1720 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1721 1.105 augustss if (new != last) {
1722 1.253.2.2.2.1 skrll DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0);
1723 1.105 augustss last = new;
1724 1.105 augustss }
1725 1.105 augustss #endif
1726 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1727 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1728 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1729 1.53 augustss ohci_intr1(sc);
1730 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1731 1.224 mrg }
1732 1.1 augustss }
1733 1.1 augustss
1734 1.253.2.2.2.1 skrll /*
1735 1.253.2.2.2.1 skrll * Add an ED to the schedule. Called with USB lock held.
1736 1.253.2.2.2.1 skrll */
1737 1.253.2.2.2.1 skrll Static void
1738 1.253.2.2.2.1 skrll ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1739 1.1 augustss {
1740 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1741 1.253.2.2.2.1 skrll DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0);
1742 1.113 augustss
1743 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1744 1.224 mrg
1745 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1746 1.195 bouyer sizeof(head->ed.ed_nexted),
1747 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1748 1.1 augustss sed->next = head->next;
1749 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1750 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1751 1.195 bouyer sizeof(sed->ed.ed_nexted),
1752 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1753 1.1 augustss head->next = sed;
1754 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1755 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1756 1.195 bouyer sizeof(head->ed.ed_nexted),
1757 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1758 1.1 augustss }
1759 1.1 augustss
1760 1.1 augustss /*
1761 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1762 1.3 augustss */
1763 1.224 mrg Static void
1764 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1765 1.3 augustss {
1766 1.120 augustss ohci_soft_ed_t *p;
1767 1.3 augustss
1768 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1769 1.224 mrg
1770 1.3 augustss /* XXX */
1771 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1772 1.3 augustss ;
1773 1.253.2.2.2.1 skrll KASSERT(p != NULL);
1774 1.253.2.2.2.1 skrll
1775 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1776 1.195 bouyer sizeof(sed->ed.ed_nexted),
1777 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1778 1.3 augustss p->next = sed->next;
1779 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1780 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1781 1.195 bouyer sizeof(p->ed.ed_nexted),
1782 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1783 1.3 augustss }
1784 1.3 augustss
1785 1.3 augustss /*
1786 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1787 1.1 augustss * the host controller. This queue is the processed by software.
1788 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1789 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1790 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1791 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1792 1.1 augustss * hash value.
1793 1.1 augustss */
1794 1.1 augustss
1795 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1796 1.224 mrg /* Called with USB lock held. */
1797 1.1 augustss void
1798 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1799 1.1 augustss {
1800 1.1 augustss int h = HASH(std->physaddr);
1801 1.1 augustss
1802 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1803 1.224 mrg
1804 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1805 1.1 augustss }
1806 1.1 augustss
1807 1.224 mrg /* Called with USB lock held. */
1808 1.1 augustss void
1809 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1810 1.1 augustss {
1811 1.46 augustss
1812 1.253.2.2.2.1 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1813 1.224 mrg
1814 1.1 augustss LIST_REMOVE(std, hnext);
1815 1.1 augustss }
1816 1.1 augustss
1817 1.1 augustss ohci_soft_td_t *
1818 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1819 1.1 augustss {
1820 1.1 augustss int h = HASH(a);
1821 1.1 augustss ohci_soft_td_t *std;
1822 1.1 augustss
1823 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1824 1.53 augustss std != NULL;
1825 1.1 augustss std = LIST_NEXT(std, hnext))
1826 1.1 augustss if (std->physaddr == a)
1827 1.253.2.2.2.1 skrll return std;
1828 1.253.2.2.2.1 skrll return NULL;
1829 1.83 augustss }
1830 1.83 augustss
1831 1.224 mrg /* Called with USB lock held. */
1832 1.83 augustss void
1833 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1834 1.83 augustss {
1835 1.83 augustss int h = HASH(sitd->physaddr);
1836 1.83 augustss
1837 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1838 1.253.2.2.2.1 skrll
1839 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1840 1.224 mrg
1841 1.253.2.2.2.1 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1842 1.253.2.2.2.1 skrll 0, 0);
1843 1.83 augustss
1844 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1845 1.83 augustss }
1846 1.83 augustss
1847 1.224 mrg /* Called with USB lock held. */
1848 1.83 augustss void
1849 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1850 1.83 augustss {
1851 1.83 augustss
1852 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1853 1.253.2.2.2.1 skrll
1854 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1855 1.224 mrg
1856 1.253.2.2.2.1 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1857 1.253.2.2.2.1 skrll 0, 0);
1858 1.83 augustss
1859 1.83 augustss LIST_REMOVE(sitd, hnext);
1860 1.83 augustss }
1861 1.83 augustss
1862 1.83 augustss ohci_soft_itd_t *
1863 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1864 1.83 augustss {
1865 1.83 augustss int h = HASH(a);
1866 1.83 augustss ohci_soft_itd_t *sitd;
1867 1.83 augustss
1868 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1869 1.83 augustss sitd != NULL;
1870 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1871 1.83 augustss if (sitd->physaddr == a)
1872 1.253.2.2.2.1 skrll return sitd;
1873 1.253.2.2.2.1 skrll return NULL;
1874 1.1 augustss }
1875 1.1 augustss
1876 1.1 augustss void
1877 1.91 augustss ohci_timeout(void *addr)
1878 1.1 augustss {
1879 1.253.2.2.2.1 skrll struct usbd_xfer *xfer = addr;
1880 1.253.2.2.2.1 skrll struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer);
1881 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1882 1.114 augustss
1883 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1884 1.253.2.2.2.1 skrll DPRINTF("oxfer=%p", oxfer, 0, 0, 0);
1885 1.114 augustss
1886 1.116 augustss if (sc->sc_dying) {
1887 1.224 mrg mutex_enter(&sc->sc_lock);
1888 1.253.2.2.2.1 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1889 1.224 mrg mutex_exit(&sc->sc_lock);
1890 1.116 augustss return;
1891 1.116 augustss }
1892 1.116 augustss
1893 1.114 augustss /* Execute the abort in a process context. */
1894 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1895 1.231 jmcneill USB_TASKQ_MPSAFE);
1896 1.253.2.2.2.1 skrll usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task,
1897 1.178 joerg USB_TASKQ_HC);
1898 1.114 augustss }
1899 1.114 augustss
1900 1.114 augustss void
1901 1.114 augustss ohci_timeout_task(void *addr)
1902 1.114 augustss {
1903 1.253.2.2.2.1 skrll struct usbd_xfer *xfer = addr;
1904 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1905 1.253.2.2.2.1 skrll
1906 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1907 1.1 augustss
1908 1.253.2.2.2.1 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1909 1.45 augustss
1910 1.224 mrg mutex_enter(&sc->sc_lock);
1911 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1912 1.224 mrg mutex_exit(&sc->sc_lock);
1913 1.1 augustss }
1914 1.1 augustss
1915 1.52 augustss #ifdef OHCI_DEBUG
1916 1.1 augustss void
1917 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1918 1.1 augustss {
1919 1.253.2.2.2.1 skrll for (; std; std = std->nexttd) {
1920 1.168 augustss ohci_dump_td(sc, std);
1921 1.253.2.2.2.1 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
1922 1.253.2.2.2.1 skrll "std %p next %p", std, std->nexttd);
1923 1.253.2.2.2.1 skrll }
1924 1.1 augustss }
1925 1.1 augustss
1926 1.1 augustss void
1927 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1928 1.1 augustss {
1929 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1930 1.92 tv
1931 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1932 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1933 1.253.2.2.2.1 skrll
1934 1.253.2.2.2.1 skrll uint32_t flags = O32TOH(std->td.td_flags);
1935 1.253.2.2.2.1 skrll DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0);
1936 1.253.2.2.2.1 skrll DPRINTF(" round=%d DP=%x DI=%x T=%x",
1937 1.253.2.2.2.1 skrll !!(flags & OHCI_TD_R),
1938 1.253.2.2.2.1 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1939 1.253.2.2.2.1 skrll OHCI_TD_GET_DI(flags),
1940 1.253.2.2.2.1 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1941 1.253.2.2.2.1 skrll DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags),
1942 1.253.2.2.2.1 skrll 0, 0);
1943 1.253.2.2.2.1 skrll DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx",
1944 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1945 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1946 1.253.2.2.2.1 skrll (u_long)O32TOH(std->td.td_be), 0);
1947 1.1 augustss }
1948 1.1 augustss
1949 1.1 augustss void
1950 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1951 1.83 augustss {
1952 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1953 1.83 augustss
1954 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1955 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1956 1.253.2.2.2.1 skrll
1957 1.253.2.2.2.1 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
1958 1.253.2.2.2.1 skrll DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0);
1959 1.253.2.2.2.1 skrll DPRINTF(" sf=%d di=%d fc=%d cc=%d",
1960 1.253.2.2.2.1 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
1961 1.253.2.2.2.1 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
1962 1.253.2.2.2.1 skrll DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x",
1963 1.253.2.2.2.1 skrll O32TOH(sitd->itd.itd_bp0),
1964 1.253.2.2.2.1 skrll O32TOH(sitd->itd.itd_nextitd),
1965 1.253.2.2.2.1 skrll O32TOH(sitd->itd.itd_be), 0);
1966 1.253.2.2.2.1 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
1967 1.253.2.2.2.1 skrll DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x "
1968 1.253.2.2.2.1 skrll "offs[2] = 0x%04x offs[3] = 0x%04x",
1969 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[0]),
1970 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[1]),
1971 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[2]),
1972 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[3]));
1973 1.253.2.2.2.1 skrll DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x "
1974 1.253.2.2.2.1 skrll "offs[6] = 0x%04x offs[7] = 0x%04x",
1975 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[4]),
1976 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[5]),
1977 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[6]),
1978 1.253.2.2.2.1 skrll O16TOH(sitd->itd.itd_offset[7]));
1979 1.83 augustss }
1980 1.83 augustss
1981 1.83 augustss void
1982 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1983 1.83 augustss {
1984 1.83 augustss for (; sitd; sitd = sitd->nextitd)
1985 1.168 augustss ohci_dump_itd(sc, sitd);
1986 1.83 augustss }
1987 1.83 augustss
1988 1.83 augustss void
1989 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
1990 1.1 augustss {
1991 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1992 1.92 tv
1993 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
1994 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1995 1.253.2.2.2.1 skrll
1996 1.253.2.2.2.1 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
1997 1.253.2.2.2.1 skrll DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0);
1998 1.253.2.2.2.1 skrll DPRINTF(" addr=%d endpt=%d maxp=%d",
1999 1.253.2.2.2.1 skrll OHCI_ED_GET_FA(flags),
2000 1.253.2.2.2.1 skrll OHCI_ED_GET_EN(flags),
2001 1.253.2.2.2.1 skrll OHCI_ED_GET_MAXP(flags),
2002 1.253.2.2.2.1 skrll 0);
2003 1.253.2.2.2.1 skrll DPRINTF(" dir=%d speed=%d skip=%d iso=%d",
2004 1.253.2.2.2.1 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
2005 1.253.2.2.2.1 skrll !!(flags & OHCI_ED_SPEED),
2006 1.253.2.2.2.1 skrll !!(flags & OHCI_ED_SKIP),
2007 1.253.2.2.2.1 skrll !!(flags & OHCI_ED_FORMAT_ISO));
2008 1.253.2.2.2.1 skrll DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp),
2009 1.253.2.2.2.1 skrll 0, 0, 0);
2010 1.253.2.2.2.1 skrll DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d",
2011 1.253.2.2.2.1 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
2012 1.253.2.2.2.1 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
2013 1.253.2.2.2.1 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2014 1.1 augustss }
2015 1.1 augustss #endif
2016 1.1 augustss
2017 1.1 augustss usbd_status
2018 1.253.2.2.2.1 skrll ohci_open(struct usbd_pipe *pipe)
2019 1.1 augustss {
2020 1.253.2.2.2.1 skrll struct usbd_device *dev = pipe->up_dev;
2021 1.253.2.2.2.1 skrll struct usbd_bus *bus = dev->ud_bus;
2022 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2023 1.253.2.2.2.1 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2024 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2025 1.253.2.2.2.1 skrll uint8_t addr = dev->ud_addr;
2026 1.253.2.2.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2027 1.1 augustss ohci_soft_ed_t *sed;
2028 1.1 augustss ohci_soft_td_t *std;
2029 1.60 augustss ohci_soft_itd_t *sitd;
2030 1.60 augustss ohci_physaddr_t tdphys;
2031 1.253.2.2.2.1 skrll uint32_t fmt;
2032 1.224 mrg usbd_status err = USBD_NOMEM;
2033 1.64 augustss int ival;
2034 1.1 augustss
2035 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2036 1.253.2.2.2.1 skrll DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr,
2037 1.253.2.2.2.1 skrll ed->bEndpointAddress, bus->ub_rhaddr);
2038 1.81 augustss
2039 1.224 mrg if (sc->sc_dying) {
2040 1.241 skrll return USBD_IOERROR;
2041 1.224 mrg }
2042 1.116 augustss
2043 1.90 thorpej std = NULL;
2044 1.90 thorpej sed = NULL;
2045 1.90 thorpej
2046 1.253.2.2.2.1 skrll if (addr == bus->ub_rhaddr) {
2047 1.1 augustss switch (ed->bEndpointAddress) {
2048 1.1 augustss case USB_CONTROL_ENDPOINT:
2049 1.253.2.2.2.1 skrll pipe->up_methods = &roothub_ctrl_methods;
2050 1.1 augustss break;
2051 1.253.2.2.2.1 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2052 1.253.2.2.2.1 skrll pipe->up_methods = &ohci_root_intr_methods;
2053 1.1 augustss break;
2054 1.1 augustss default:
2055 1.224 mrg err = USBD_INVAL;
2056 1.241 skrll goto bad;
2057 1.1 augustss }
2058 1.1 augustss } else {
2059 1.1 augustss sed = ohci_alloc_sed(sc);
2060 1.53 augustss if (sed == NULL)
2061 1.241 skrll goto bad;
2062 1.1 augustss opipe->sed = sed;
2063 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2064 1.60 augustss sitd = ohci_alloc_sitd(sc);
2065 1.127 augustss if (sitd == NULL)
2066 1.241 skrll goto bad;
2067 1.241 skrll
2068 1.60 augustss opipe->tail.itd = sitd;
2069 1.76 tsutsui tdphys = sitd->physaddr;
2070 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2071 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2072 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2073 1.83 augustss else
2074 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2075 1.60 augustss } else {
2076 1.60 augustss std = ohci_alloc_std(sc);
2077 1.127 augustss if (std == NULL)
2078 1.241 skrll goto bad;
2079 1.241 skrll
2080 1.60 augustss opipe->tail.td = std;
2081 1.76 tsutsui tdphys = std->physaddr;
2082 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2083 1.60 augustss }
2084 1.168 augustss sed->ed.ed_flags = HTOO32(
2085 1.120 augustss OHCI_ED_SET_FA(addr) |
2086 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2087 1.253.2.2.2.1 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2088 1.109 augustss fmt |
2089 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2090 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2091 1.253.2.2.2.1 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2092 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2093 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2094 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2095 1.1 augustss
2096 1.60 augustss switch (xfertype) {
2097 1.1 augustss case UE_CONTROL:
2098 1.253.2.2.2.1 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2099 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2100 1.120 augustss sizeof(usb_device_request_t),
2101 1.253.2.2.2.1 skrll 0, &opipe->ctrl.reqdma);
2102 1.53 augustss if (err)
2103 1.1 augustss goto bad;
2104 1.224 mrg mutex_enter(&sc->sc_lock);
2105 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2106 1.224 mrg mutex_exit(&sc->sc_lock);
2107 1.1 augustss break;
2108 1.1 augustss case UE_INTERRUPT:
2109 1.253.2.2.2.1 skrll pipe->up_methods = &ohci_device_intr_methods;
2110 1.253.2.2.2.1 skrll ival = pipe->up_interval;
2111 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2112 1.64 augustss ival = ed->bInterval;
2113 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2114 1.226 skrll if (err)
2115 1.226 skrll goto bad;
2116 1.226 skrll break;
2117 1.1 augustss case UE_ISOCHRONOUS:
2118 1.253.2.2.2.1 skrll pipe->up_serialise = false;
2119 1.253.2.2.2.1 skrll pipe->up_methods = &ohci_device_isoc_methods;
2120 1.253.2.2.2.1 skrll return ohci_setup_isoc(pipe);
2121 1.1 augustss case UE_BULK:
2122 1.253.2.2.2.1 skrll pipe->up_methods = &ohci_device_bulk_methods;
2123 1.224 mrg mutex_enter(&sc->sc_lock);
2124 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2125 1.224 mrg mutex_exit(&sc->sc_lock);
2126 1.3 augustss break;
2127 1.1 augustss }
2128 1.1 augustss }
2129 1.224 mrg
2130 1.224 mrg return USBD_NORMAL_COMPLETION;
2131 1.1 augustss
2132 1.1 augustss bad:
2133 1.241 skrll if (std != NULL) {
2134 1.90 thorpej ohci_free_std(sc, std);
2135 1.241 skrll }
2136 1.90 thorpej if (sed != NULL)
2137 1.90 thorpej ohci_free_sed(sc, sed);
2138 1.224 mrg return err;
2139 1.120 augustss
2140 1.1 augustss }
2141 1.1 augustss
2142 1.1 augustss /*
2143 1.34 augustss * Close a reqular pipe.
2144 1.34 augustss * Assumes that there are no pending transactions.
2145 1.34 augustss */
2146 1.34 augustss void
2147 1.253.2.2.2.1 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2148 1.34 augustss {
2149 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2150 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2151 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2152 1.34 augustss
2153 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2154 1.224 mrg
2155 1.34 augustss #ifdef DIAGNOSTIC
2156 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2157 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2158 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2159 1.34 augustss ohci_soft_td_t *std;
2160 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2161 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2162 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2163 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2164 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2165 1.34 augustss pipe, std);
2166 1.229 christos #ifdef OHCI_DEBUG
2167 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2168 1.168 augustss ohci_dump_ed(sc, sed);
2169 1.106 augustss if (std)
2170 1.168 augustss ohci_dump_td(sc, std);
2171 1.106 augustss #endif
2172 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2173 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2174 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2175 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2176 1.34 augustss }
2177 1.34 augustss #endif
2178 1.224 mrg ohci_rem_ed(sc, sed, head);
2179 1.133 toshii /* Make sure the host controller is not touching this ED */
2180 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2181 1.253.2.2.2.1 skrll pipe->up_endpoint->ue_toggle =
2182 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2183 1.253.2.2.2.1 skrll ohci_free_sed_locked(sc, opipe->sed);
2184 1.34 augustss }
2185 1.34 augustss
2186 1.120 augustss /*
2187 1.34 augustss * Abort a device request.
2188 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2189 1.34 augustss * will be removed from the hardware scheduling and that the callback
2190 1.34 augustss * for it will be called with USBD_CANCELLED status.
2191 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2192 1.34 augustss * have happened since the hardware runs concurrently.
2193 1.34 augustss * If the transaction has already happened we rely on the ordinary
2194 1.34 augustss * interrupt processing to process it.
2195 1.224 mrg * XXX This is most probably wrong.
2196 1.224 mrg * XXXMRG this doesn't make sense anymore.
2197 1.34 augustss */
2198 1.34 augustss void
2199 1.253.2.2.2.1 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2200 1.34 augustss {
2201 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2202 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2203 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2204 1.106 augustss ohci_soft_td_t *p, *n;
2205 1.106 augustss ohci_physaddr_t headp;
2206 1.224 mrg int hit;
2207 1.159 augustss int wake;
2208 1.34 augustss
2209 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2210 1.253.2.2.2.1 skrll DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0);
2211 1.34 augustss
2212 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2213 1.253.2.2.2.1 skrll ASSERT_SLEEPABLE();
2214 1.224 mrg
2215 1.116 augustss if (sc->sc_dying) {
2216 1.116 augustss /* If we're dying, just do the software part. */
2217 1.253.2.2.2.1 skrll xfer->ux_status = status; /* make software ignore it */
2218 1.253.2.2.2.1 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2219 1.116 augustss usb_transfer_complete(xfer);
2220 1.170 christos return;
2221 1.116 augustss }
2222 1.116 augustss
2223 1.106 augustss /*
2224 1.159 augustss * If an abort is already in progress then just wait for it to
2225 1.159 augustss * complete and return.
2226 1.159 augustss */
2227 1.253.2.2.2.1 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2228 1.253.2.2.2.1 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2229 1.159 augustss #ifdef DIAGNOSTIC
2230 1.159 augustss if (status == USBD_TIMEOUT)
2231 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2232 1.159 augustss #endif
2233 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2234 1.253.2.2.2.1 skrll xfer->ux_status = status;
2235 1.253.2.2.2.1 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2236 1.253.2.2.2.1 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2237 1.253.2.2.2.1 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2238 1.253.2.2.2.1 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2239 1.224 mrg goto done;
2240 1.159 augustss }
2241 1.253.2.2.2.1 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2242 1.159 augustss
2243 1.159 augustss /*
2244 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2245 1.106 augustss */
2246 1.253.2.2.2.1 skrll xfer->ux_status = status; /* make software ignore it */
2247 1.253.2.2.2.1 skrll callout_stop(&xfer->ux_callout);
2248 1.253.2.2.2.1 skrll DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0);
2249 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2250 1.195 bouyer sizeof(sed->ed.ed_flags),
2251 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2252 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2253 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2254 1.195 bouyer sizeof(sed->ed.ed_flags),
2255 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2256 1.34 augustss
2257 1.120 augustss /*
2258 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2259 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2260 1.106 augustss * has run.
2261 1.106 augustss */
2262 1.224 mrg /* Hardware finishes in 1ms */
2263 1.253.2.2.2.1 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2264 1.119 augustss sc->sc_softwake = 1;
2265 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2266 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2267 1.119 augustss
2268 1.120 augustss /*
2269 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2270 1.106 augustss * The complication here is that the hardware may have executed
2271 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2272 1.106 augustss * the TDs of this xfer we check if the hardware points to
2273 1.106 augustss * any of them.
2274 1.106 augustss */
2275 1.253.2.2.2.1 skrll p = xfer->ux_hcpriv;
2276 1.253.2.2.2.1 skrll KASSERT(p);
2277 1.253.2.2.2.1 skrll
2278 1.106 augustss #ifdef OHCI_DEBUG
2279 1.253.2.2.2.1 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2280 1.253.2.2.2.1 skrll
2281 1.253.2.2.2.1 skrll if (ohcidebug >= 2) {
2282 1.253.2.2.2.1 skrll DPRINTF("sed:", 0, 0, 0, 0);
2283 1.168 augustss ohci_dump_ed(sc, sed);
2284 1.168 augustss ohci_dump_tds(sc, p);
2285 1.106 augustss }
2286 1.253.2.2.2.1 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2287 1.106 augustss #endif
2288 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2289 1.106 augustss hit = 0;
2290 1.53 augustss for (; p->xfer == xfer; p = n) {
2291 1.106 augustss hit |= headp == p->physaddr;
2292 1.38 augustss n = p->nexttd;
2293 1.253.2.2.2.1 skrll ohci_hash_rem_td(sc, p);
2294 1.34 augustss }
2295 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2296 1.106 augustss if (hit) {
2297 1.253.2.2.2.1 skrll DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr,
2298 1.253.2.2.2.1 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2299 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2300 1.195 bouyer usb_syncmem(&sed->dma,
2301 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2302 1.195 bouyer sizeof(sed->ed.ed_headp),
2303 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2304 1.106 augustss } else {
2305 1.253.2.2.2.1 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2306 1.106 augustss }
2307 1.34 augustss
2308 1.106 augustss /*
2309 1.106 augustss * Step 4: Turn on hardware again.
2310 1.106 augustss */
2311 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2312 1.195 bouyer sizeof(sed->ed.ed_flags),
2313 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2314 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2315 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2316 1.195 bouyer sizeof(sed->ed.ed_flags),
2317 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2318 1.38 augustss
2319 1.106 augustss /*
2320 1.106 augustss * Step 5: Execute callback.
2321 1.106 augustss */
2322 1.253.2.2.2.1 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2323 1.253.2.2.2.1 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2324 1.53 augustss usb_transfer_complete(xfer);
2325 1.159 augustss if (wake)
2326 1.253.2.2.2.1 skrll cv_broadcast(&xfer->ux_hccv);
2327 1.38 augustss
2328 1.224 mrg done:
2329 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2330 1.34 augustss }
2331 1.34 augustss
2332 1.34 augustss /*
2333 1.1 augustss * Data structures and routines to emulate the root hub.
2334 1.1 augustss */
2335 1.253.2.2.2.1 skrll Static int
2336 1.253.2.2.2.1 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2337 1.253.2.2.2.1 skrll void *buf, int buflen)
2338 1.17 augustss {
2339 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2340 1.1 augustss usb_port_status_t ps;
2341 1.253.2.2.2.1 skrll uint16_t len, value, index;
2342 1.253.2.2.2.1 skrll int l, totlen = 0;
2343 1.253.2.2.2.1 skrll int port, i;
2344 1.253.2.2.2.1 skrll uint32_t v;
2345 1.1 augustss
2346 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2347 1.83 augustss
2348 1.253.2.2.2.1 skrll if (sc->sc_dying)
2349 1.253.2.2.2.1 skrll return -1;
2350 1.1 augustss
2351 1.253.2.2.2.1 skrll DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType,
2352 1.253.2.2.2.1 skrll req->bRequest, 0, 0);
2353 1.1 augustss
2354 1.1 augustss len = UGETW(req->wLength);
2355 1.1 augustss value = UGETW(req->wValue);
2356 1.1 augustss index = UGETW(req->wIndex);
2357 1.43 augustss
2358 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2359 1.253.2.2.2.1 skrll switch (C(req->bRequest, req->bmRequestType)) {
2360 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2361 1.253.2.2.2.1 skrll DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0);
2362 1.171 christos if (len == 0)
2363 1.171 christos break;
2364 1.253.2.2.2.1 skrll switch (value) {
2365 1.253.2.2.2.1 skrll case C(0, UDESC_DEVICE): {
2366 1.253.2.2.2.1 skrll usb_device_descriptor_t devd;
2367 1.253.2.2.2.1 skrll
2368 1.253.2.2.2.1 skrll totlen = min(buflen, sizeof(devd));
2369 1.253.2.2.2.1 skrll memcpy(&devd, buf, totlen);
2370 1.253.2.2.2.1 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2371 1.253.2.2.2.1 skrll memcpy(buf, &devd, totlen);
2372 1.1 augustss break;
2373 1.253.2.2.2.1 skrll }
2374 1.253.2.2.2.1 skrll case C(1, UDESC_STRING):
2375 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2376 1.253.2.2.2.1 skrll /* Vendor */
2377 1.253.2.2.2.1 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2378 1.1 augustss break;
2379 1.253.2.2.2.1 skrll case C(2, UDESC_STRING):
2380 1.253.2.2.2.1 skrll /* Product */
2381 1.253.2.2.2.1 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2382 1.253.2.2.2.1 skrll break;
2383 1.253.2.2.2.1 skrll #undef sd
2384 1.1 augustss default:
2385 1.253.2.2.2.1 skrll /* default from usbroothub */
2386 1.253.2.2.2.1 skrll return buflen;
2387 1.1 augustss }
2388 1.1 augustss break;
2389 1.253.2.2.2.1 skrll
2390 1.1 augustss /* Hub requests */
2391 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2392 1.1 augustss break;
2393 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2394 1.253.2.2.2.1 skrll DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2395 1.253.2.2.2.1 skrll index, value, 0, 0);
2396 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2397 1.253.2.2.2.1 skrll return -1;
2398 1.1 augustss }
2399 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2400 1.1 augustss switch(value) {
2401 1.1 augustss case UHF_PORT_ENABLE:
2402 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2403 1.1 augustss break;
2404 1.1 augustss case UHF_PORT_SUSPEND:
2405 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2406 1.1 augustss break;
2407 1.1 augustss case UHF_PORT_POWER:
2408 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2409 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2410 1.1 augustss break;
2411 1.1 augustss case UHF_C_PORT_CONNECTION:
2412 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2413 1.1 augustss break;
2414 1.1 augustss case UHF_C_PORT_ENABLE:
2415 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2416 1.1 augustss break;
2417 1.1 augustss case UHF_C_PORT_SUSPEND:
2418 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2419 1.1 augustss break;
2420 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2421 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2422 1.1 augustss break;
2423 1.1 augustss case UHF_C_PORT_RESET:
2424 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2425 1.1 augustss break;
2426 1.1 augustss default:
2427 1.253.2.2.2.1 skrll return -1;
2428 1.1 augustss }
2429 1.1 augustss switch(value) {
2430 1.1 augustss case UHF_C_PORT_CONNECTION:
2431 1.1 augustss case UHF_C_PORT_ENABLE:
2432 1.1 augustss case UHF_C_PORT_SUSPEND:
2433 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2434 1.1 augustss case UHF_C_PORT_RESET:
2435 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2436 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2437 1.157 mycroft ohci_rhsc_enable(sc);
2438 1.1 augustss break;
2439 1.1 augustss default:
2440 1.1 augustss break;
2441 1.1 augustss }
2442 1.1 augustss break;
2443 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2444 1.171 christos if (len == 0)
2445 1.171 christos break;
2446 1.146 toshii if ((value & 0xff) != 0) {
2447 1.253.2.2.2.1 skrll return -1;
2448 1.1 augustss }
2449 1.253.2.2.2.1 skrll usb_hub_descriptor_t hubd;
2450 1.253.2.2.2.1 skrll
2451 1.253.2.2.2.1 skrll totlen = min(buflen, sizeof(hubd));
2452 1.253.2.2.2.1 skrll memcpy(&hubd, buf, totlen);
2453 1.253.2.2.2.1 skrll
2454 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2455 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2456 1.15 augustss USETW(hubd.wHubCharacteristics,
2457 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2458 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2459 1.1 augustss /* XXX overcurrent */
2460 1.1 augustss );
2461 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2462 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2463 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2464 1.253.2.2.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2465 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2466 1.253.2.2.2.1 skrll totlen = min(totlen, hubd.bDescLength);
2467 1.253.2.2.2.1 skrll memcpy(buf, &hubd, totlen);
2468 1.1 augustss break;
2469 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2470 1.1 augustss if (len != 4) {
2471 1.253.2.2.2.1 skrll return -1;
2472 1.1 augustss }
2473 1.1 augustss memset(buf, 0, len); /* ? XXX */
2474 1.1 augustss totlen = len;
2475 1.1 augustss break;
2476 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2477 1.253.2.2.2.1 skrll DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
2478 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2479 1.253.2.2.2.1 skrll return -1;
2480 1.1 augustss }
2481 1.1 augustss if (len != 4) {
2482 1.253.2.2.2.1 skrll return -1;
2483 1.1 augustss }
2484 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2485 1.253.2.2.2.1 skrll DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0);
2486 1.1 augustss USETW(ps.wPortStatus, v);
2487 1.1 augustss USETW(ps.wPortChange, v >> 16);
2488 1.253.2.2.2.1 skrll totlen = min(len, sizeof(ps));
2489 1.253.2.2.2.1 skrll memcpy(buf, &ps, totlen);
2490 1.1 augustss break;
2491 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2492 1.253.2.2.2.1 skrll return -1;
2493 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2494 1.1 augustss break;
2495 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2496 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2497 1.253.2.2.2.1 skrll return -1;
2498 1.1 augustss }
2499 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2500 1.1 augustss switch(value) {
2501 1.1 augustss case UHF_PORT_ENABLE:
2502 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2503 1.1 augustss break;
2504 1.1 augustss case UHF_PORT_SUSPEND:
2505 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2506 1.1 augustss break;
2507 1.1 augustss case UHF_PORT_RESET:
2508 1.253.2.2.2.1 skrll DPRINTFN(5, "reset port %d", index, 0, 0, 0);
2509 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2510 1.110 augustss for (i = 0; i < 5; i++) {
2511 1.110 augustss usb_delay_ms(&sc->sc_bus,
2512 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2513 1.116 augustss if (sc->sc_dying) {
2514 1.253.2.2.2.1 skrll return -1;
2515 1.116 augustss }
2516 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2517 1.1 augustss break;
2518 1.1 augustss }
2519 1.253.2.2.2.1 skrll DPRINTFN(8, "port %d reset, status = 0x%04x", index,
2520 1.253.2.2.2.1 skrll OREAD4(sc, port), 0, 0);
2521 1.1 augustss break;
2522 1.1 augustss case UHF_PORT_POWER:
2523 1.253.2.2.2.1 skrll DPRINTFN(2, "set port power %d", index, 0, 0, 0);
2524 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2525 1.1 augustss break;
2526 1.1 augustss default:
2527 1.253.2.2.2.1 skrll return -1;
2528 1.1 augustss }
2529 1.1 augustss break;
2530 1.1 augustss default:
2531 1.253.2.2.2.1 skrll /* default from usbroothub */
2532 1.253.2.2.2.1 skrll return buflen;
2533 1.1 augustss }
2534 1.1 augustss
2535 1.253.2.2.2.1 skrll return totlen;
2536 1.1 augustss }
2537 1.1 augustss
2538 1.82 augustss Static usbd_status
2539 1.253.2.2.2.1 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2540 1.1 augustss {
2541 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2542 1.53 augustss usbd_status err;
2543 1.17 augustss
2544 1.46 augustss /* Insert last in queue. */
2545 1.224 mrg mutex_enter(&sc->sc_lock);
2546 1.53 augustss err = usb_insert_transfer(xfer);
2547 1.224 mrg mutex_exit(&sc->sc_lock);
2548 1.53 augustss if (err)
2549 1.253.2.2.2.1 skrll return err;
2550 1.46 augustss
2551 1.46 augustss /* Pipe isn't running, start first */
2552 1.253.2.2.2.1 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2553 1.17 augustss }
2554 1.17 augustss
2555 1.82 augustss Static usbd_status
2556 1.253.2.2.2.1 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2557 1.17 augustss {
2558 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2559 1.1 augustss
2560 1.83 augustss if (sc->sc_dying)
2561 1.253.2.2.2.1 skrll return USBD_IOERROR;
2562 1.83 augustss
2563 1.224 mrg mutex_enter(&sc->sc_lock);
2564 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2565 1.53 augustss sc->sc_intrxfer = xfer;
2566 1.224 mrg mutex_exit(&sc->sc_lock);
2567 1.1 augustss
2568 1.253.2.2.2.1 skrll return USBD_IN_PROGRESS;
2569 1.1 augustss }
2570 1.1 augustss
2571 1.3 augustss /* Abort a root interrupt request. */
2572 1.82 augustss Static void
2573 1.253.2.2.2.1 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2574 1.1 augustss {
2575 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2576 1.224 mrg
2577 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2578 1.253.2.2.2.1 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2579 1.53 augustss
2580 1.252 skrll sc->sc_intrxfer = NULL;
2581 1.252 skrll
2582 1.253.2.2.2.1 skrll xfer->ux_status = USBD_CANCELLED;
2583 1.53 augustss usb_transfer_complete(xfer);
2584 1.1 augustss }
2585 1.1 augustss
2586 1.1 augustss /* Close the root pipe. */
2587 1.82 augustss Static void
2588 1.253.2.2.2.1 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2589 1.1 augustss {
2590 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2591 1.120 augustss
2592 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2593 1.224 mrg
2594 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2595 1.34 augustss
2596 1.53 augustss sc->sc_intrxfer = NULL;
2597 1.1 augustss }
2598 1.1 augustss
2599 1.1 augustss /************************/
2600 1.1 augustss
2601 1.253.2.2.2.1 skrll int
2602 1.253.2.2.2.1 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2603 1.17 augustss {
2604 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2605 1.253.2.2.2.1 skrll usb_device_request_t *req = &xfer->ux_request;
2606 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2607 1.253.2.2.2.1 skrll ohci_soft_td_t *stat, *setup;
2608 1.253.2.2.2.1 skrll int isread = req->bmRequestType & UT_READ;
2609 1.253.2.2.2.1 skrll int len = xfer->ux_bufsize;
2610 1.253.2.2.2.1 skrll int err = ENOMEM;
2611 1.1 augustss
2612 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2613 1.83 augustss
2614 1.253.2.2.2.1 skrll setup = ohci_alloc_std(sc);
2615 1.253.2.2.2.1 skrll if (setup == NULL) {
2616 1.253.2.2.2.1 skrll goto bad1;
2617 1.253.2.2.2.1 skrll }
2618 1.253.2.2.2.1 skrll stat = ohci_alloc_std(sc);
2619 1.253.2.2.2.1 skrll if (stat == NULL) {
2620 1.253.2.2.2.1 skrll goto bad2;
2621 1.1 augustss }
2622 1.1 augustss
2623 1.253.2.2.2.1 skrll ox->ox_setup = setup;
2624 1.253.2.2.2.1 skrll ox->ox_stat = stat;
2625 1.253.2.2.2.1 skrll ox->ox_nstd = 0;
2626 1.224 mrg
2627 1.253.2.2.2.1 skrll /* Set up data transaction */
2628 1.253.2.2.2.1 skrll if (len != 0) {
2629 1.253.2.2.2.1 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2630 1.253.2.2.2.1 skrll if (err) {
2631 1.253.2.2.2.1 skrll goto bad3;
2632 1.253.2.2.2.1 skrll }
2633 1.253.2.2.2.1 skrll }
2634 1.253.2.2.2.1 skrll return 0;
2635 1.224 mrg
2636 1.253.2.2.2.1 skrll bad3:
2637 1.253.2.2.2.1 skrll ohci_free_std(sc, stat);
2638 1.253.2.2.2.1 skrll bad2:
2639 1.253.2.2.2.1 skrll ohci_free_std(sc, setup);
2640 1.253.2.2.2.1 skrll bad1:
2641 1.253.2.2.2.1 skrll return err;
2642 1.1 augustss }
2643 1.1 augustss
2644 1.253.2.2.2.1 skrll void
2645 1.253.2.2.2.1 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2646 1.1 augustss {
2647 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2648 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2649 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2650 1.37 augustss
2651 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2652 1.253.2.2.2.1 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2653 1.37 augustss
2654 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
2655 1.253.2.2.2.1 skrll if (ox->ox_setup != opipe->tail.td) {
2656 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, ox->ox_setup);
2657 1.253.2.2.2.1 skrll }
2658 1.253.2.2.2.1 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2659 1.253.2.2.2.1 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2660 1.253.2.2.2.1 skrll if (std == NULL)
2661 1.253.2.2.2.1 skrll break;
2662 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, std);
2663 1.253.2.2.2.1 skrll }
2664 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, ox->ox_stat);
2665 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
2666 1.37 augustss
2667 1.253.2.2.2.1 skrll if (ox->ox_nstd) {
2668 1.253.2.2.2.1 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2669 1.253.2.2.2.1 skrll kmem_free(ox->ox_stds, sz);
2670 1.253.2.2.2.1 skrll }
2671 1.37 augustss }
2672 1.3 augustss
2673 1.82 augustss Static usbd_status
2674 1.253.2.2.2.1 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2675 1.3 augustss {
2676 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2677 1.53 augustss usbd_status err;
2678 1.17 augustss
2679 1.46 augustss /* Insert last in queue. */
2680 1.224 mrg mutex_enter(&sc->sc_lock);
2681 1.53 augustss err = usb_insert_transfer(xfer);
2682 1.224 mrg mutex_exit(&sc->sc_lock);
2683 1.53 augustss if (err)
2684 1.253.2.2.2.1 skrll return err;
2685 1.46 augustss
2686 1.46 augustss /* Pipe isn't running, start first */
2687 1.253.2.2.2.1 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2688 1.17 augustss }
2689 1.17 augustss
2690 1.82 augustss Static usbd_status
2691 1.253.2.2.2.1 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2692 1.17 augustss {
2693 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2694 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2695 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2696 1.253.2.2.2.1 skrll usb_device_request_t *req = &xfer->ux_request;
2697 1.253.2.2.2.1 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2698 1.253.2.2.2.1 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2699 1.3 augustss ohci_soft_ed_t *sed;
2700 1.253.2.2.2.1 skrll int isread;
2701 1.253.2.2.2.1 skrll int len;
2702 1.253.2.2.2.1 skrll
2703 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2704 1.3 augustss
2705 1.83 augustss if (sc->sc_dying)
2706 1.253.2.2.2.1 skrll return USBD_IOERROR;
2707 1.83 augustss
2708 1.253.2.2.2.1 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2709 1.3 augustss
2710 1.253.2.2.2.1 skrll isread = req->bmRequestType & UT_READ;
2711 1.253.2.2.2.1 skrll len = UGETW(req->wLength);
2712 1.253.2.2.2.1 skrll
2713 1.253.2.2.2.1 skrll DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr,
2714 1.253.2.2.2.1 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2715 1.253.2.2.2.1 skrll DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x",
2716 1.253.2.2.2.1 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2717 1.253.2.2.2.1 skrll UGETW(req->wIndex));
2718 1.253.2.2.2.1 skrll
2719 1.253.2.2.2.1 skrll /* Need to take lock here for pipe->tail.td */
2720 1.224 mrg mutex_enter(&sc->sc_lock);
2721 1.224 mrg
2722 1.253.2.2.2.1 skrll /*
2723 1.253.2.2.2.1 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2724 1.253.2.2.2.1 skrll * next transfer
2725 1.253.2.2.2.1 skrll */
2726 1.253.2.2.2.1 skrll setup = opipe->tail.td;
2727 1.253.2.2.2.1 skrll opipe->tail.td = ox->ox_setup;
2728 1.253.2.2.2.1 skrll ox->ox_setup = setup;
2729 1.253.2.2.2.1 skrll
2730 1.253.2.2.2.1 skrll stat = ox->ox_stat;
2731 1.253.2.2.2.1 skrll
2732 1.253.2.2.2.1 skrll /* point at sentinel */
2733 1.253.2.2.2.1 skrll tail = opipe->tail.td;
2734 1.3 augustss sed = opipe->sed;
2735 1.3 augustss
2736 1.253.2.2.2.1 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2737 1.253.2.2.2.1 skrll "address ED %d pipe %d\n",
2738 1.253.2.2.2.1 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2739 1.253.2.2.2.1 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2740 1.253.2.2.2.1 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2741 1.253.2.2.2.1 skrll "MPL ED %d pipe %d\n",
2742 1.253.2.2.2.1 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2743 1.253.2.2.2.1 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2744 1.34 augustss
2745 1.253.2.2.2.1 skrll /* next will point to data if len != 0 */
2746 1.253.2.2.2.1 skrll next = stat;
2747 1.3 augustss
2748 1.253.2.2.2.1 skrll /* Set up data transaction */
2749 1.253.2.2.2.1 skrll if (len != 0) {
2750 1.253.2.2.2.1 skrll ohci_soft_td_t *std;
2751 1.253.2.2.2.1 skrll ohci_soft_td_t *end;
2752 1.253.2.2.2.1 skrll
2753 1.253.2.2.2.1 skrll next = ox->ox_stds[0];
2754 1.253.2.2.2.1 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2755 1.253.2.2.2.1 skrll
2756 1.253.2.2.2.1 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2757 1.253.2.2.2.1 skrll end->nexttd = stat;
2758 1.253.2.2.2.1 skrll
2759 1.253.2.2.2.1 skrll usb_syncmem(&end->dma,
2760 1.253.2.2.2.1 skrll end->offs + offsetof(ohci_td_t, td_nexttd),
2761 1.253.2.2.2.1 skrll sizeof(end->td.td_nexttd),
2762 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2763 1.253.2.2.2.1 skrll
2764 1.253.2.2.2.1 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2765 1.253.2.2.2.1 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2766 1.253.2.2.2.1 skrll std = ox->ox_stds[0];
2767 1.253.2.2.2.1 skrll /* Start toggle at 1 and then use the carried toggle. */
2768 1.253.2.2.2.1 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2769 1.253.2.2.2.1 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2770 1.253.2.2.2.1 skrll usb_syncmem(&std->dma,
2771 1.253.2.2.2.1 skrll std->offs + offsetof(ohci_td_t, td_flags),
2772 1.253.2.2.2.1 skrll sizeof(std->td.td_flags),
2773 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2774 1.253.2.2.2.1 skrll }
2775 1.253.2.2.2.1 skrll
2776 1.253.2.2.2.1 skrll DPRINTFN(8, "setup %p data %p stat %p tail %p", setup,
2777 1.253.2.2.2.1 skrll (len != 0 ? ox->ox_stds[0] : NULL), stat, tail);
2778 1.253.2.2.2.1 skrll KASSERT(opipe->tail.td == tail);
2779 1.253.2.2.2.1 skrll
2780 1.253.2.2.2.1 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2781 1.253.2.2.2.1 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2782 1.253.2.2.2.1 skrll
2783 1.253.2.2.2.1 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2784 1.253.2.2.2.1 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2785 1.253.2.2.2.1 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2786 1.253.2.2.2.1 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2787 1.253.2.2.2.1 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2788 1.253.2.2.2.1 skrll setup->nexttd = next;
2789 1.253.2.2.2.1 skrll setup->len = 0;
2790 1.253.2.2.2.1 skrll setup->xfer = xfer;
2791 1.253.2.2.2.1 skrll setup->flags = 0;
2792 1.253.2.2.2.1 skrll ohci_hash_add_td(sc, setup);
2793 1.253.2.2.2.1 skrll
2794 1.253.2.2.2.1 skrll xfer->ux_hcpriv = setup;
2795 1.253.2.2.2.1 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2796 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2797 1.253.2.2.2.1 skrll
2798 1.253.2.2.2.1 skrll stat->td.td_flags = HTOO32(
2799 1.253.2.2.2.1 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2800 1.253.2.2.2.1 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2801 1.253.2.2.2.1 skrll stat->td.td_cbp = 0;
2802 1.253.2.2.2.1 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2803 1.253.2.2.2.1 skrll stat->td.td_be = 0;
2804 1.253.2.2.2.1 skrll stat->nexttd = tail;
2805 1.253.2.2.2.1 skrll stat->flags = OHCI_CALL_DONE;
2806 1.253.2.2.2.1 skrll stat->len = 0;
2807 1.253.2.2.2.1 skrll stat->xfer = xfer;
2808 1.253.2.2.2.1 skrll ohci_hash_add_td(sc, stat);
2809 1.253.2.2.2.1 skrll
2810 1.253.2.2.2.1 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2811 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2812 1.253.2.2.2.1 skrll
2813 1.253.2.2.2.1 skrll memset(&tail->td, 0, sizeof(tail->td));
2814 1.253.2.2.2.1 skrll tail->nexttd = NULL;
2815 1.253.2.2.2.1 skrll tail->xfer = NULL;
2816 1.253.2.2.2.1 skrll
2817 1.253.2.2.2.1 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2818 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2819 1.253.2.2.2.1 skrll
2820 1.253.2.2.2.1 skrll #ifdef OHCI_DEBUG
2821 1.253.2.2.2.1 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2822 1.253.2.2.2.1 skrll if (ohcidebug >= 5) {
2823 1.253.2.2.2.1 skrll ohci_dump_ed(sc, sed);
2824 1.253.2.2.2.1 skrll ohci_dump_tds(sc, setup);
2825 1.253.2.2.2.1 skrll }
2826 1.253.2.2.2.1 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2827 1.253.2.2.2.1 skrll #endif
2828 1.253.2.2.2.1 skrll
2829 1.253.2.2.2.1 skrll /* Insert ED in schedule */
2830 1.253.2.2.2.1 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2831 1.253.2.2.2.1 skrll usb_syncmem(&sed->dma,
2832 1.253.2.2.2.1 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2833 1.253.2.2.2.1 skrll sizeof(sed->ed.ed_tailp),
2834 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2835 1.253.2.2.2.1 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2836 1.253.2.2.2.1 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2837 1.253.2.2.2.1 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2838 1.253.2.2.2.1 skrll ohci_timeout, xfer);
2839 1.253.2.2.2.1 skrll }
2840 1.253.2.2.2.1 skrll
2841 1.253.2.2.2.1 skrll DPRINTF("done", 0, 0, 0, 0);
2842 1.253.2.2.2.1 skrll
2843 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
2844 1.253.2.2.2.1 skrll
2845 1.253.2.2.2.1 skrll return USBD_IN_PROGRESS;
2846 1.253.2.2.2.1 skrll }
2847 1.253.2.2.2.1 skrll
2848 1.253.2.2.2.1 skrll /* Abort a device control request. */
2849 1.253.2.2.2.1 skrll Static void
2850 1.253.2.2.2.1 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2851 1.253.2.2.2.1 skrll {
2852 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2853 1.253.2.2.2.1 skrll
2854 1.253.2.2.2.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
2855 1.253.2.2.2.1 skrll
2856 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2857 1.253.2.2.2.1 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2858 1.253.2.2.2.1 skrll ohci_abort_xfer(xfer, USBD_CANCELLED);
2859 1.253.2.2.2.1 skrll }
2860 1.253.2.2.2.1 skrll
2861 1.253.2.2.2.1 skrll /* Close a device control pipe. */
2862 1.253.2.2.2.1 skrll Static void
2863 1.253.2.2.2.1 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2864 1.253.2.2.2.1 skrll {
2865 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2866 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2867 1.253.2.2.2.1 skrll
2868 1.253.2.2.2.1 skrll KASSERT(mutex_owned(&sc->sc_lock));
2869 1.253.2.2.2.1 skrll
2870 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2871 1.253.2.2.2.1 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2872 1.253.2.2.2.1 skrll ohci_close_pipe(pipe, sc->sc_ctrl_head);
2873 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, opipe->tail.td);
2874 1.253.2.2.2.1 skrll }
2875 1.253.2.2.2.1 skrll
2876 1.253.2.2.2.1 skrll /************************/
2877 1.253.2.2.2.1 skrll
2878 1.253.2.2.2.1 skrll Static void
2879 1.253.2.2.2.1 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2880 1.253.2.2.2.1 skrll {
2881 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2882 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2883 1.253.2.2.2.1 skrll
2884 1.253.2.2.2.1 skrll opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2885 1.253.2.2.2.1 skrll }
2886 1.253.2.2.2.1 skrll
2887 1.253.2.2.2.1 skrll Static void
2888 1.253.2.2.2.1 skrll ohci_noop(struct usbd_pipe *pipe)
2889 1.253.2.2.2.1 skrll {
2890 1.253.2.2.2.1 skrll }
2891 1.253.2.2.2.1 skrll
2892 1.253.2.2.2.1 skrll Static int
2893 1.253.2.2.2.1 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
2894 1.253.2.2.2.1 skrll {
2895 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2896 1.253.2.2.2.1 skrll int len = xfer->ux_bufsize;
2897 1.253.2.2.2.1 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
2898 1.253.2.2.2.1 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2899 1.253.2.2.2.1 skrll int err;
2900 1.253.2.2.2.1 skrll
2901 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2902 1.253.2.2.2.1 skrll
2903 1.253.2.2.2.1 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2904 1.253.2.2.2.1 skrll
2905 1.253.2.2.2.1 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
2906 1.253.2.2.2.1 skrll xfer->ux_flags);
2907 1.253.2.2.2.1 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
2908 1.3 augustss
2909 1.48 augustss /* Allocate a chain of new TDs (including a new tail). */
2910 1.253.2.2.2.1 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2911 1.236 skrll if (err)
2912 1.236 skrll return err;
2913 1.253.2.2.2.1 skrll
2914 1.253.2.2.2.1 skrll return 0;
2915 1.253.2.2.2.1 skrll }
2916 1.253.2.2.2.1 skrll
2917 1.253.2.2.2.1 skrll Static void
2918 1.253.2.2.2.1 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
2919 1.253.2.2.2.1 skrll {
2920 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2921 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2922 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2923 1.253.2.2.2.1 skrll
2924 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2925 1.253.2.2.2.1 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2926 1.253.2.2.2.1 skrll
2927 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
2928 1.253.2.2.2.1 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2929 1.253.2.2.2.1 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2930 1.253.2.2.2.1 skrll if (std == NULL)
2931 1.253.2.2.2.1 skrll break;
2932 1.253.2.2.2.1 skrll if (std != opipe->tail.td)
2933 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, std);
2934 1.224 mrg }
2935 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
2936 1.253.2.2.2.1 skrll
2937 1.253.2.2.2.1 skrll if (ox->ox_nstd) {
2938 1.253.2.2.2.1 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2939 1.253.2.2.2.1 skrll kmem_free(ox->ox_stds, sz);
2940 1.253.2.2.2.1 skrll }
2941 1.253.2.2.2.1 skrll }
2942 1.253.2.2.2.1 skrll
2943 1.253.2.2.2.1 skrll Static usbd_status
2944 1.253.2.2.2.1 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
2945 1.253.2.2.2.1 skrll {
2946 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2947 1.253.2.2.2.1 skrll usbd_status err;
2948 1.253.2.2.2.1 skrll
2949 1.253.2.2.2.1 skrll /* Insert last in queue. */
2950 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
2951 1.253.2.2.2.1 skrll err = usb_insert_transfer(xfer);
2952 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
2953 1.253.2.2.2.1 skrll if (err)
2954 1.253.2.2.2.1 skrll return err;
2955 1.253.2.2.2.1 skrll
2956 1.253.2.2.2.1 skrll /* Pipe isn't running, start first */
2957 1.253.2.2.2.1 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2958 1.253.2.2.2.1 skrll }
2959 1.253.2.2.2.1 skrll
2960 1.253.2.2.2.1 skrll Static usbd_status
2961 1.253.2.2.2.1 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
2962 1.253.2.2.2.1 skrll {
2963 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2964 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2965 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2966 1.253.2.2.2.1 skrll ohci_soft_td_t *last;
2967 1.253.2.2.2.1 skrll ohci_soft_td_t *data, *tail, *tdp;
2968 1.253.2.2.2.1 skrll ohci_soft_ed_t *sed;
2969 1.253.2.2.2.1 skrll int len, isread, endpt;
2970 1.253.2.2.2.1 skrll
2971 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2972 1.253.2.2.2.1 skrll
2973 1.253.2.2.2.1 skrll if (sc->sc_dying)
2974 1.253.2.2.2.1 skrll return USBD_IOERROR;
2975 1.253.2.2.2.1 skrll
2976 1.253.2.2.2.1 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2977 1.253.2.2.2.1 skrll
2978 1.253.2.2.2.1 skrll len = xfer->ux_length;
2979 1.253.2.2.2.1 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2980 1.253.2.2.2.1 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2981 1.253.2.2.2.1 skrll sed = opipe->sed;
2982 1.48 augustss
2983 1.253.2.2.2.1 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
2984 1.253.2.2.2.1 skrll xfer->ux_flags);
2985 1.253.2.2.2.1 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
2986 1.253.2.2.2.1 skrll
2987 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
2988 1.253.2.2.2.1 skrll
2989 1.253.2.2.2.1 skrll /*
2990 1.253.2.2.2.1 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2991 1.253.2.2.2.1 skrll * next transfer
2992 1.253.2.2.2.1 skrll */
2993 1.253.2.2.2.1 skrll data = opipe->tail.td;
2994 1.253.2.2.2.1 skrll opipe->tail.td = ox->ox_stds[0];
2995 1.253.2.2.2.1 skrll ox->ox_stds[0] = data;
2996 1.253.2.2.2.1 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
2997 1.253.2.2.2.1 skrll
2998 1.253.2.2.2.1 skrll /* point at sentinel */
2999 1.253.2.2.2.1 skrll tail = opipe->tail.td;
3000 1.253.2.2.2.1 skrll memset(&tail->td, 0, sizeof(tail->td));
3001 1.253.2.2.2.1 skrll tail->nexttd = NULL;
3002 1.53 augustss tail->xfer = NULL;
3003 1.253.2.2.2.1 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3004 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE);
3005 1.253.2.2.2.1 skrll xfer->ux_hcpriv = data;
3006 1.253.2.2.2.1 skrll
3007 1.253.2.2.2.1 skrll DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0);
3008 1.253.2.2.2.1 skrll KASSERT(opipe->tail.td == tail);
3009 1.253.2.2.2.1 skrll
3010 1.253.2.2.2.1 skrll /* We want interrupt at the end of the transfer. */
3011 1.253.2.2.2.1 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3012 1.253.2.2.2.1 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3013 1.253.2.2.2.1 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3014 1.253.2.2.2.1 skrll last->nexttd = tail;
3015 1.253.2.2.2.1 skrll last->flags |= OHCI_CALL_DONE;
3016 1.253.2.2.2.1 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3017 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3018 1.3 augustss
3019 1.253.2.2.2.1 skrll DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x "
3020 1.253.2.2.2.1 skrll "td_cbp=0x%08x td_be=0x%08x",
3021 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3022 1.168 augustss (int)O32TOH(data->td.td_flags),
3023 1.168 augustss (int)O32TOH(data->td.td_cbp),
3024 1.253.2.2.2.1 skrll (int)O32TOH(data->td.td_be));
3025 1.34 augustss
3026 1.52 augustss #ifdef OHCI_DEBUG
3027 1.253.2.2.2.1 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3028 1.253.2.2.2.1 skrll if (ohcidebug >= 5) {
3029 1.168 augustss ohci_dump_ed(sc, sed);
3030 1.168 augustss ohci_dump_tds(sc, data);
3031 1.34 augustss }
3032 1.253.2.2.2.1 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3033 1.34 augustss #endif
3034 1.34 augustss
3035 1.3 augustss /* Insert ED in schedule */
3036 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3037 1.253.2.2.2.1 skrll KASSERT(tdp->xfer == xfer);
3038 1.48 augustss }
3039 1.253.2.2.2.1 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3040 1.253.2.2.2.1 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3041 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3042 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3043 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3044 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3045 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3046 1.253.2.2.2.1 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3047 1.253.2.2.2.1 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3048 1.80 augustss ohci_timeout, xfer);
3049 1.15 augustss }
3050 1.224 mrg mutex_exit(&sc->sc_lock);
3051 1.34 augustss
3052 1.253.2.2.2.1 skrll return USBD_IN_PROGRESS;
3053 1.3 augustss }
3054 1.3 augustss
3055 1.82 augustss Static void
3056 1.253.2.2.2.1 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3057 1.3 augustss {
3058 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3059 1.253.2.2.2.1 skrll
3060 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3061 1.224 mrg
3062 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3063 1.224 mrg
3064 1.253.2.2.2.1 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
3065 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3066 1.3 augustss }
3067 1.3 augustss
3068 1.120 augustss /*
3069 1.34 augustss * Close a device bulk pipe.
3070 1.34 augustss */
3071 1.82 augustss Static void
3072 1.253.2.2.2.1 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3073 1.3 augustss {
3074 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3075 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3076 1.3 augustss
3077 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3078 1.224 mrg
3079 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3080 1.253.2.2.2.1 skrll
3081 1.253.2.2.2.1 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3082 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3083 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, opipe->tail.td);
3084 1.1 augustss }
3085 1.1 augustss
3086 1.1 augustss /************************/
3087 1.1 augustss
3088 1.253.2.2.2.1 skrll Static int
3089 1.253.2.2.2.1 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3090 1.253.2.2.2.1 skrll {
3091 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3092 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3093 1.253.2.2.2.1 skrll int len = xfer->ux_bufsize;
3094 1.253.2.2.2.1 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3095 1.253.2.2.2.1 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3096 1.253.2.2.2.1 skrll int err;
3097 1.253.2.2.2.1 skrll
3098 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3099 1.253.2.2.2.1 skrll
3100 1.253.2.2.2.1 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3101 1.253.2.2.2.1 skrll KASSERT(len != 0);
3102 1.253.2.2.2.1 skrll
3103 1.253.2.2.2.1 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3104 1.253.2.2.2.1 skrll xfer->ux_flags);
3105 1.253.2.2.2.1 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3106 1.253.2.2.2.1 skrll
3107 1.253.2.2.2.1 skrll ox->ox_nstd = 0;
3108 1.253.2.2.2.1 skrll
3109 1.253.2.2.2.1 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3110 1.253.2.2.2.1 skrll if (err) {
3111 1.253.2.2.2.1 skrll return err;
3112 1.253.2.2.2.1 skrll }
3113 1.253.2.2.2.1 skrll
3114 1.253.2.2.2.1 skrll return 0;
3115 1.253.2.2.2.1 skrll }
3116 1.253.2.2.2.1 skrll
3117 1.253.2.2.2.1 skrll Static void
3118 1.253.2.2.2.1 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3119 1.253.2.2.2.1 skrll {
3120 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3121 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3122 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3123 1.253.2.2.2.1 skrll
3124 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3125 1.253.2.2.2.1 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3126 1.253.2.2.2.1 skrll
3127 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
3128 1.253.2.2.2.1 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3129 1.253.2.2.2.1 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3130 1.253.2.2.2.1 skrll if (std != NULL)
3131 1.253.2.2.2.1 skrll break;
3132 1.253.2.2.2.1 skrll if (std != opipe->tail.td)
3133 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, std);
3134 1.253.2.2.2.1 skrll }
3135 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
3136 1.253.2.2.2.1 skrll
3137 1.253.2.2.2.1 skrll if (ox->ox_nstd) {
3138 1.253.2.2.2.1 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3139 1.253.2.2.2.1 skrll kmem_free(ox->ox_stds, sz);
3140 1.253.2.2.2.1 skrll }
3141 1.253.2.2.2.1 skrll }
3142 1.253.2.2.2.1 skrll
3143 1.82 augustss Static usbd_status
3144 1.253.2.2.2.1 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3145 1.17 augustss {
3146 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3147 1.53 augustss usbd_status err;
3148 1.17 augustss
3149 1.46 augustss /* Insert last in queue. */
3150 1.224 mrg mutex_enter(&sc->sc_lock);
3151 1.53 augustss err = usb_insert_transfer(xfer);
3152 1.224 mrg mutex_exit(&sc->sc_lock);
3153 1.53 augustss if (err)
3154 1.253.2.2.2.1 skrll return err;
3155 1.46 augustss
3156 1.46 augustss /* Pipe isn't running, start first */
3157 1.253.2.2.2.1 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3158 1.17 augustss }
3159 1.17 augustss
3160 1.82 augustss Static usbd_status
3161 1.253.2.2.2.1 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3162 1.1 augustss {
3163 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3164 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3165 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3166 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3167 1.253.2.2.2.1 skrll ohci_soft_td_t *data, *last, *tail;
3168 1.224 mrg int len, isread, endpt;
3169 1.1 augustss
3170 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3171 1.253.2.2.2.1 skrll
3172 1.83 augustss if (sc->sc_dying)
3173 1.253.2.2.2.1 skrll return USBD_IOERROR;
3174 1.83 augustss
3175 1.253.2.2.2.1 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length,
3176 1.253.2.2.2.1 skrll xfer->ux_flags, xfer->ux_priv);
3177 1.1 augustss
3178 1.253.2.2.2.1 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3179 1.1 augustss
3180 1.253.2.2.2.1 skrll len = xfer->ux_length;
3181 1.253.2.2.2.1 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3182 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3183 1.1 augustss
3184 1.224 mrg mutex_enter(&sc->sc_lock);
3185 1.253.2.2.2.1 skrll
3186 1.253.2.2.2.1 skrll /*
3187 1.253.2.2.2.1 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3188 1.253.2.2.2.1 skrll * next transfer.
3189 1.253.2.2.2.1 skrll */
3190 1.253.2.2.2.1 skrll data = opipe->tail.td;
3191 1.253.2.2.2.1 skrll opipe->tail.td = ox->ox_stds[0];
3192 1.253.2.2.2.1 skrll ox->ox_stds[0] = data;
3193 1.253.2.2.2.1 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3194 1.253.2.2.2.1 skrll
3195 1.253.2.2.2.1 skrll /* point at sentinel */
3196 1.253.2.2.2.1 skrll tail = opipe->tail.td;
3197 1.253.2.2.2.1 skrll memset(&tail->td, 0, sizeof(tail->td));
3198 1.253.2.2.2.1 skrll tail->nexttd = NULL;
3199 1.53 augustss tail->xfer = NULL;
3200 1.253.2.2.2.1 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3201 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE);
3202 1.253.2.2.2.1 skrll xfer->ux_hcpriv = data;
3203 1.253.2.2.2.1 skrll
3204 1.253.2.2.2.1 skrll DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0);
3205 1.253.2.2.2.1 skrll KASSERT(opipe->tail.td == tail);
3206 1.1 augustss
3207 1.253.2.2.2.1 skrll /* We want interrupt at the end of the transfer. */
3208 1.253.2.2.2.1 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3209 1.253.2.2.2.1 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3210 1.253.2.2.2.1 skrll
3211 1.253.2.2.2.1 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3212 1.253.2.2.2.1 skrll last->nexttd = tail;
3213 1.253.2.2.2.1 skrll last->flags |= OHCI_CALL_DONE;
3214 1.253.2.2.2.1 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3215 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3216 1.1 augustss
3217 1.52 augustss #ifdef OHCI_DEBUG
3218 1.253.2.2.2.1 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3219 1.253.2.2.2.1 skrll if (ohcidebug >= 5) {
3220 1.168 augustss ohci_dump_ed(sc, sed);
3221 1.168 augustss ohci_dump_tds(sc, data);
3222 1.1 augustss }
3223 1.253.2.2.2.1 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3224 1.1 augustss #endif
3225 1.1 augustss
3226 1.1 augustss /* Insert ED in schedule */
3227 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3228 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3229 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3230 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3231 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3232 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3233 1.1 augustss
3234 1.224 mrg mutex_exit(&sc->sc_lock);
3235 1.1 augustss
3236 1.253.2.2.2.1 skrll return USBD_IN_PROGRESS;
3237 1.1 augustss }
3238 1.1 augustss
3239 1.227 skrll /* Abort a device interrupt request. */
3240 1.82 augustss Static void
3241 1.253.2.2.2.1 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3242 1.1 augustss {
3243 1.253.2.2.2.1 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3244 1.224 mrg
3245 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3246 1.253.2.2.2.1 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3247 1.224 mrg
3248 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3249 1.1 augustss }
3250 1.1 augustss
3251 1.1 augustss /* Close a device interrupt pipe. */
3252 1.82 augustss Static void
3253 1.253.2.2.2.1 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3254 1.1 augustss {
3255 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3256 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3257 1.253.2.2.2.1 skrll int nslots = opipe->intr.nslots;
3258 1.253.2.2.2.1 skrll int pos = opipe->intr.pos;
3259 1.1 augustss int j;
3260 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3261 1.224 mrg
3262 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3263 1.253.2.2.2.1 skrll
3264 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3265 1.1 augustss
3266 1.253.2.2.2.1 skrll DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0);
3267 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3268 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3269 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3270 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3271 1.195 bouyer sizeof(sed->ed.ed_flags),
3272 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3273 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3274 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3275 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3276 1.1 augustss
3277 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3278 1.172 christos continue;
3279 1.253.2.2.2.1 skrll KASSERT(p);
3280 1.173 christos p->next = sed->next;
3281 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3282 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3283 1.195 bouyer sizeof(p->ed.ed_nexted),
3284 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3285 1.1 augustss
3286 1.1 augustss for (j = 0; j < nslots; j++)
3287 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3288 1.1 augustss
3289 1.253.2.2.2.1 skrll ohci_free_std_locked(sc, opipe->tail.td);
3290 1.253.2.2.2.1 skrll ohci_free_sed_locked(sc, opipe->sed);
3291 1.1 augustss }
3292 1.1 augustss
3293 1.82 augustss Static usbd_status
3294 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3295 1.1 augustss {
3296 1.224 mrg int i, j, best;
3297 1.1 augustss u_int npoll, slow, shigh, nslots;
3298 1.1 augustss u_int bestbw, bw;
3299 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3300 1.1 augustss
3301 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3302 1.253.2.2.2.1 skrll
3303 1.253.2.2.2.1 skrll DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0);
3304 1.1 augustss if (ival == 0) {
3305 1.1 augustss printf("ohci_setintr: 0 interval\n");
3306 1.253.2.2.2.1 skrll return USBD_INVAL;
3307 1.1 augustss }
3308 1.1 augustss
3309 1.1 augustss npoll = OHCI_NO_INTRS;
3310 1.1 augustss while (npoll > ival)
3311 1.1 augustss npoll /= 2;
3312 1.253.2.2.2.1 skrll DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0);
3313 1.1 augustss
3314 1.1 augustss /*
3315 1.1 augustss * We now know which level in the tree the ED must go into.
3316 1.1 augustss * Figure out which slot has most bandwidth left over.
3317 1.1 augustss * Slots to examine:
3318 1.1 augustss * npoll
3319 1.1 augustss * 1 0
3320 1.1 augustss * 2 1 2
3321 1.1 augustss * 4 3 4 5 6
3322 1.1 augustss * 8 7 8 9 10 11 12 13 14
3323 1.1 augustss * N (N-1) .. (N-1+N-1)
3324 1.1 augustss */
3325 1.1 augustss slow = npoll-1;
3326 1.1 augustss shigh = slow + npoll;
3327 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3328 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3329 1.1 augustss bw = 0;
3330 1.1 augustss for (j = 0; j < nslots; j++)
3331 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3332 1.1 augustss if (bw < bestbw) {
3333 1.1 augustss best = i;
3334 1.1 augustss bestbw = bw;
3335 1.1 augustss }
3336 1.1 augustss }
3337 1.253.2.2.2.1 skrll DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw);
3338 1.1 augustss
3339 1.224 mrg mutex_enter(&sc->sc_lock);
3340 1.1 augustss hsed = sc->sc_eds[best];
3341 1.1 augustss sed->next = hsed->next;
3342 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3343 1.195 bouyer sizeof(hsed->ed.ed_flags),
3344 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3345 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3346 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3347 1.195 bouyer sizeof(sed->ed.ed_flags),
3348 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3349 1.1 augustss hsed->next = sed;
3350 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3351 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3352 1.195 bouyer sizeof(hsed->ed.ed_flags),
3353 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3354 1.224 mrg mutex_exit(&sc->sc_lock);
3355 1.1 augustss
3356 1.1 augustss for (j = 0; j < nslots; j++)
3357 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3358 1.253.2.2.2.1 skrll opipe->intr.nslots = nslots;
3359 1.253.2.2.2.1 skrll opipe->intr.pos = best;
3360 1.1 augustss
3361 1.253.2.2.2.1 skrll DPRINTFN(5, "returns %p", opipe, 0, 0, 0);
3362 1.253.2.2.2.1 skrll return USBD_NORMAL_COMPLETION;
3363 1.60 augustss }
3364 1.60 augustss
3365 1.60 augustss /***********************/
3366 1.60 augustss
3367 1.253.2.2.2.1 skrll Static int
3368 1.253.2.2.2.1 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3369 1.253.2.2.2.1 skrll {
3370 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3371 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3372 1.253.2.2.2.1 skrll ohci_soft_itd_t *sitd;
3373 1.253.2.2.2.1 skrll size_t i;
3374 1.253.2.2.2.1 skrll int err;
3375 1.253.2.2.2.1 skrll
3376 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3377 1.253.2.2.2.1 skrll
3378 1.253.2.2.2.1 skrll DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length,
3379 1.253.2.2.2.1 skrll xfer->ux_flags, 0);
3380 1.253.2.2.2.1 skrll
3381 1.253.2.2.2.1 skrll const size_t nfsitd =
3382 1.253.2.2.2.1 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3383 1.253.2.2.2.1 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3384 1.253.2.2.2.1 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3385 1.253.2.2.2.1 skrll
3386 1.253.2.2.2.1 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3387 1.253.2.2.2.1 skrll KM_SLEEP);
3388 1.253.2.2.2.1 skrll ox->ox_nsitd = nsitd;
3389 1.253.2.2.2.1 skrll
3390 1.253.2.2.2.1 skrll for (i = 0; i < nsitd; i++) {
3391 1.253.2.2.2.1 skrll /* Allocate next ITD */
3392 1.253.2.2.2.1 skrll sitd = ohci_alloc_sitd(sc);
3393 1.253.2.2.2.1 skrll if (sitd == NULL) {
3394 1.253.2.2.2.1 skrll err = ENOMEM;
3395 1.253.2.2.2.1 skrll goto fail;
3396 1.253.2.2.2.1 skrll }
3397 1.253.2.2.2.1 skrll ox->ox_sitds[i] = sitd;
3398 1.253.2.2.2.1 skrll sitd->xfer = xfer;
3399 1.253.2.2.2.1 skrll sitd->flags = 0;
3400 1.253.2.2.2.1 skrll }
3401 1.253.2.2.2.1 skrll
3402 1.253.2.2.2.1 skrll return 0;
3403 1.253.2.2.2.1 skrll fail:
3404 1.253.2.2.2.1 skrll for (; i > 0;) {
3405 1.253.2.2.2.1 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3406 1.253.2.2.2.1 skrll }
3407 1.253.2.2.2.1 skrll return err;
3408 1.253.2.2.2.1 skrll }
3409 1.253.2.2.2.1 skrll
3410 1.253.2.2.2.1 skrll Static void
3411 1.253.2.2.2.1 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3412 1.253.2.2.2.1 skrll {
3413 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3414 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3415 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3416 1.253.2.2.2.1 skrll
3417 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3418 1.253.2.2.2.1 skrll
3419 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
3420 1.253.2.2.2.1 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3421 1.253.2.2.2.1 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3422 1.253.2.2.2.1 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3423 1.253.2.2.2.1 skrll }
3424 1.253.2.2.2.1 skrll }
3425 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
3426 1.253.2.2.2.1 skrll
3427 1.253.2.2.2.1 skrll if (ox->ox_nsitd) {
3428 1.253.2.2.2.1 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3429 1.253.2.2.2.1 skrll kmem_free(ox->ox_sitds, sz);
3430 1.253.2.2.2.1 skrll }
3431 1.253.2.2.2.1 skrll }
3432 1.253.2.2.2.1 skrll
3433 1.253.2.2.2.1 skrll
3434 1.60 augustss usbd_status
3435 1.253.2.2.2.1 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3436 1.60 augustss {
3437 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3438 1.253.2.2.2.1 skrll usbd_status __diagused err;
3439 1.60 augustss
3440 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3441 1.253.2.2.2.1 skrll
3442 1.253.2.2.2.1 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3443 1.60 augustss
3444 1.60 augustss /* Put it on our queue, */
3445 1.224 mrg mutex_enter(&sc->sc_lock);
3446 1.60 augustss err = usb_insert_transfer(xfer);
3447 1.224 mrg mutex_exit(&sc->sc_lock);
3448 1.60 augustss
3449 1.253.2.2.2.1 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3450 1.60 augustss
3451 1.60 augustss /* insert into schedule, */
3452 1.60 augustss ohci_device_isoc_enter(xfer);
3453 1.60 augustss
3454 1.83 augustss /* and start if the pipe wasn't running */
3455 1.253.2.2.2.1 skrll return USBD_IN_PROGRESS;
3456 1.60 augustss }
3457 1.60 augustss
3458 1.60 augustss void
3459 1.253.2.2.2.1 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3460 1.60 augustss {
3461 1.253.2.2.2.1 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3462 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3463 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3464 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3465 1.253.2.2.2.1 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3466 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3467 1.61 augustss int i, ncur, nframes;
3468 1.61 augustss
3469 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3470 1.253.2.2.2.1 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3471 1.83 augustss
3472 1.253.2.2.2.1 skrll mutex_enter(&sc->sc_lock);
3473 1.253.2.2.2.1 skrll
3474 1.253.2.2.2.1 skrll if (sc->sc_dying) {
3475 1.253.2.2.2.1 skrll mutex_exit(&sc->sc_lock);
3476 1.83 augustss return;
3477 1.253.2.2.2.1 skrll }
3478 1.253.2.2.2.1 skrll
3479 1.253.2.2.2.1 skrll struct isoc *isoc = &opipe->isoc;
3480 1.253.2.2.2.1 skrll
3481 1.253.2.2.2.1 skrll DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d",
3482 1.253.2.2.2.1 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3483 1.83 augustss
3484 1.253.2.2.2.1 skrll if (isoc->next == -1) {
3485 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3486 1.253.2.2.2.1 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3487 1.253.2.2.2.1 skrll DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0);
3488 1.83 augustss }
3489 1.83 augustss
3490 1.61 augustss sitd = opipe->tail.itd;
3491 1.253.2.2.2.1 skrll opipe->tail.itd = ox->ox_sitds[0];
3492 1.253.2.2.2.1 skrll ox->ox_sitds[0] = sitd;
3493 1.253.2.2.2.1 skrll
3494 1.253.2.2.2.1 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3495 1.83 augustss bp0 = OHCI_PAGE(buf);
3496 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3497 1.253.2.2.2.1 skrll nframes = xfer->ux_nframes;
3498 1.253.2.2.2.1 skrll xfer->ux_hcpriv = sitd;
3499 1.253.2.2.2.1 skrll size_t j = 1;
3500 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3501 1.253.2.2.2.1 skrll noffs = offs + xfer->ux_frlengths[i];
3502 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3503 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3504 1.120 augustss
3505 1.83 augustss /* Allocate next ITD */
3506 1.253.2.2.2.1 skrll nsitd = ox->ox_sitds[j++];
3507 1.253.2.2.2.1 skrll KASSERT(nsitd != NULL);
3508 1.253.2.2.2.1 skrll KASSERT(j < ox->ox_nsitd);
3509 1.83 augustss
3510 1.83 augustss /* Fill current ITD */
3511 1.168 augustss sitd->itd.itd_flags = HTOO32(
3512 1.120 augustss OHCI_ITD_NOCC |
3513 1.253.2.2.2.1 skrll OHCI_ITD_SET_SF(isoc->next) |
3514 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3515 1.83 augustss OHCI_ITD_SET_FC(ncur));
3516 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3517 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3518 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3519 1.253.2.2.2.1 skrll sitd->nextitd = nsitd;
3520 1.83 augustss sitd->xfer = xfer;
3521 1.83 augustss sitd->flags = 0;
3522 1.253.2.2.2.1 skrll #ifdef DIAGNOSTIC
3523 1.253.2.2.2.1 skrll sitd->isdone = false;
3524 1.253.2.2.2.1 skrll #endif
3525 1.253.2.2.2.1 skrll ohci_hash_add_itd(sc, sitd);
3526 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3527 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3528 1.83 augustss
3529 1.61 augustss sitd = nsitd;
3530 1.253.2.2.2.1 skrll isoc->next = isoc->next + ncur;
3531 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3532 1.61 augustss ncur = 0;
3533 1.61 augustss }
3534 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3535 1.83 augustss offs = noffs;
3536 1.61 augustss }
3537 1.253.2.2.2.1 skrll KASSERT(j <= ox->ox_nsitd);
3538 1.253.2.2.2.1 skrll
3539 1.253.2.2.2.1 skrll /* point at sentinel */
3540 1.253.2.2.2.1 skrll tail = opipe->tail.itd;
3541 1.253.2.2.2.1 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3542 1.253.2.2.2.1 skrll tail->nextitd = NULL;
3543 1.253.2.2.2.1 skrll tail->xfer = NULL;
3544 1.253.2.2.2.1 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3545 1.253.2.2.2.1 skrll BUS_DMASYNC_PREWRITE);
3546 1.253.2.2.2.1 skrll
3547 1.83 augustss /* Fixup last used ITD */
3548 1.168 augustss sitd->itd.itd_flags = HTOO32(
3549 1.120 augustss OHCI_ITD_NOCC |
3550 1.253.2.2.2.1 skrll OHCI_ITD_SET_SF(isoc->next) |
3551 1.61 augustss OHCI_ITD_SET_DI(0) |
3552 1.61 augustss OHCI_ITD_SET_FC(ncur));
3553 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3554 1.253.2.2.2.1 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3555 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3556 1.253.2.2.2.1 skrll sitd->nextitd = tail;
3557 1.83 augustss sitd->xfer = xfer;
3558 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3559 1.253.2.2.2.1 skrll #ifdef DIAGNOSTIC
3560 1.253.2.2.2.1 skrll sitd->isdone = false;
3561 1.253.2.2.2.1 skrll #endif
3562 1.253.2.2.2.1 skrll ohci_hash_add_itd(sc, sitd);
3563 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3564 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3565 1.83 augustss
3566 1.253.2.2.2.1 skrll isoc->next = isoc->next + ncur;
3567 1.253.2.2.2.1 skrll isoc->inuse += nframes;
3568 1.83 augustss
3569 1.253.2.2.2.1 skrll /* XXX pretend we did it all */
3570 1.253.2.2.2.1 skrll xfer->ux_actlen = offs;
3571 1.253.2.2.2.1 skrll xfer->ux_status = USBD_IN_PROGRESS;
3572 1.83 augustss
3573 1.83 augustss #ifdef OHCI_DEBUG
3574 1.253.2.2.2.1 skrll if (ohcidebug >= 5) {
3575 1.253.2.2.2.1 skrll DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3576 1.253.2.2.2.1 skrll 0, 0, 0);
3577 1.253.2.2.2.1 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3578 1.168 augustss ohci_dump_ed(sc, sed);
3579 1.83 augustss }
3580 1.83 augustss #endif
3581 1.61 augustss
3582 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3583 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3584 1.253.2.2.2.1 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3585 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3586 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3587 1.195 bouyer sizeof(sed->ed.ed_flags),
3588 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3589 1.224 mrg mutex_exit(&sc->sc_lock);
3590 1.60 augustss }
3591 1.60 augustss
3592 1.60 augustss void
3593 1.253.2.2.2.1 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3594 1.60 augustss {
3595 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3596 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3597 1.83 augustss ohci_soft_ed_t *sed;
3598 1.83 augustss ohci_soft_itd_t *sitd;
3599 1.83 augustss
3600 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3601 1.253.2.2.2.1 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3602 1.83 augustss
3603 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3604 1.83 augustss
3605 1.83 augustss /* Transfer is already done. */
3606 1.253.2.2.2.1 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3607 1.253.2.2.2.1 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3608 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3609 1.224 mrg goto done;
3610 1.83 augustss }
3611 1.83 augustss
3612 1.83 augustss /* Give xfer the requested abort code. */
3613 1.253.2.2.2.1 skrll xfer->ux_status = USBD_CANCELLED;
3614 1.83 augustss
3615 1.83 augustss sed = opipe->sed;
3616 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3617 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3618 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3619 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3620 1.195 bouyer sizeof(sed->ed.ed_flags),
3621 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3622 1.83 augustss
3623 1.253.2.2.2.1 skrll sitd = xfer->ux_hcpriv;
3624 1.253.2.2.2.1 skrll KASSERT(sitd);
3625 1.253.2.2.2.1 skrll
3626 1.253.2.2.2.1 skrll usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3627 1.253.2.2.2.1 skrll
3628 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3629 1.253.2.2.2.1 skrll ohci_hash_rem_itd(sc, sitd);
3630 1.83 augustss #ifdef DIAGNOSTIC
3631 1.253.2.2.2.1 skrll DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0);
3632 1.253.2.2.2.1 skrll sitd->isdone = true;
3633 1.83 augustss #endif
3634 1.83 augustss }
3635 1.83 augustss
3636 1.83 augustss /* Run callback. */
3637 1.83 augustss usb_transfer_complete(xfer);
3638 1.83 augustss
3639 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3640 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3641 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3642 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3643 1.83 augustss
3644 1.224 mrg done:
3645 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3646 1.60 augustss }
3647 1.60 augustss
3648 1.60 augustss void
3649 1.253.2.2.2.1 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3650 1.60 augustss {
3651 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3652 1.253.2.2.2.1 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3653 1.60 augustss }
3654 1.60 augustss
3655 1.60 augustss usbd_status
3656 1.253.2.2.2.1 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3657 1.60 augustss {
3658 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3659 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3660 1.253.2.2.2.1 skrll struct isoc *isoc = &opipe->isoc;
3661 1.60 augustss
3662 1.253.2.2.2.1 skrll isoc->next = -1;
3663 1.253.2.2.2.1 skrll isoc->inuse = 0;
3664 1.60 augustss
3665 1.224 mrg mutex_enter(&sc->sc_lock);
3666 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3667 1.224 mrg mutex_exit(&sc->sc_lock);
3668 1.83 augustss
3669 1.253.2.2.2.1 skrll return USBD_NORMAL_COMPLETION;
3670 1.60 augustss }
3671 1.60 augustss
3672 1.60 augustss void
3673 1.253.2.2.2.1 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3674 1.60 augustss {
3675 1.253.2.2.2.1 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3676 1.253.2.2.2.1 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3677 1.60 augustss
3678 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3679 1.224 mrg
3680 1.253.2.2.2.1 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3681 1.253.2.2.2.1 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3682 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3683 1.83 augustss #ifdef DIAGNOSTIC
3684 1.253.2.2.2.1 skrll opipe->tail.itd->isdone = true;
3685 1.83 augustss #endif
3686 1.253.2.2.2.1 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3687 1.1 augustss }
3688