ohci.c revision 1.254.2.17 1 1.254.2.17 skrll /* $NetBSD: ohci.c,v 1.254.2.17 2015/02/22 08:25:02 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.254.2.17 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.17 2015/02/22 08:25:02 skrll Exp $");
45 1.1 augustss
46 1.1 augustss #include <sys/param.h>
47 1.254.2.17 skrll
48 1.254.2.17 skrll #include <sys/cpu.h>
49 1.1 augustss #include <sys/device.h>
50 1.254.2.17 skrll #include <sys/kernel.h>
51 1.254.2.17 skrll #include <sys/kmem.h>
52 1.1 augustss #include <sys/proc.h>
53 1.1 augustss #include <sys/queue.h>
54 1.254.2.17 skrll #include <sys/select.h>
55 1.254.2.17 skrll #include <sys/systm.h>
56 1.1 augustss
57 1.16 augustss #include <machine/endian.h>
58 1.4 augustss
59 1.1 augustss #include <dev/usb/usb.h>
60 1.1 augustss #include <dev/usb/usbdi.h>
61 1.1 augustss #include <dev/usb/usbdivar.h>
62 1.38 augustss #include <dev/usb/usb_mem.h>
63 1.1 augustss #include <dev/usb/usb_quirks.h>
64 1.1 augustss
65 1.1 augustss #include <dev/usb/ohcireg.h>
66 1.1 augustss #include <dev/usb/ohcivar.h>
67 1.254.2.11 skrll #include <dev/usb/usbroothub.h>
68 1.1 augustss
69 1.1 augustss
70 1.36 augustss
71 1.52 augustss #ifdef OHCI_DEBUG
72 1.209 dyoung #define DPRINTF(x) if (ohcidebug) printf x
73 1.209 dyoung #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x
74 1.52 augustss int ohcidebug = 0;
75 1.52 augustss #else
76 1.52 augustss #define DPRINTF(x)
77 1.52 augustss #define DPRINTFN(n,x)
78 1.52 augustss #endif
79 1.52 augustss
80 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
81 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
82 1.16 augustss #else
83 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
84 1.16 augustss #endif
85 1.16 augustss
86 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
87 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
88 1.169 tron #define HTOO16(val) O16TOH(val)
89 1.169 tron #define HTOO32(val) O32TOH(val)
90 1.168 augustss
91 1.1 augustss struct ohci_pipe;
92 1.1 augustss
93 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
94 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
95 1.1 augustss
96 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
97 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
98 1.1 augustss
99 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
100 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
101 1.60 augustss
102 1.91 augustss Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *,
103 1.91 augustss ohci_soft_td_t *);
104 1.91 augustss Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *,
105 1.77 augustss ohci_softc_t *, int, int, usbd_xfer_handle,
106 1.91 augustss ohci_soft_td_t *, ohci_soft_td_t **);
107 1.53 augustss
108 1.91 augustss Static usbd_status ohci_open(usbd_pipe_handle);
109 1.91 augustss Static void ohci_poll(struct usbd_bus *);
110 1.99 augustss Static void ohci_softintr(void *);
111 1.91 augustss Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle);
112 1.91 augustss Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle);
113 1.254.2.15 skrll Static void ohci_rhsc_softint(void *);
114 1.91 augustss
115 1.91 augustss Static usbd_status ohci_device_request(usbd_xfer_handle xfer);
116 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
117 1.168 augustss ohci_soft_ed_t *);
118 1.168 augustss
119 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
120 1.224 mrg ohci_soft_ed_t *);
121 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
122 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
123 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
124 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
125 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
126 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
127 1.91 augustss
128 1.254.2.15 skrll Static usbd_status ohci_setup_isoc(usbd_pipe_handle);
129 1.91 augustss Static void ohci_device_isoc_enter(usbd_xfer_handle);
130 1.91 augustss
131 1.91 augustss Static usbd_xfer_handle ohci_allocx(struct usbd_bus *);
132 1.91 augustss Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle);
133 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
134 1.254.2.13 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
135 1.254.2.12 skrll usb_device_request_t *, void *, int);
136 1.91 augustss
137 1.91 augustss Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle);
138 1.91 augustss Static usbd_status ohci_root_intr_start(usbd_xfer_handle);
139 1.91 augustss Static void ohci_root_intr_abort(usbd_xfer_handle);
140 1.91 augustss Static void ohci_root_intr_close(usbd_pipe_handle);
141 1.91 augustss Static void ohci_root_intr_done(usbd_xfer_handle);
142 1.91 augustss
143 1.91 augustss Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle);
144 1.91 augustss Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle);
145 1.91 augustss Static void ohci_device_ctrl_abort(usbd_xfer_handle);
146 1.91 augustss Static void ohci_device_ctrl_close(usbd_pipe_handle);
147 1.91 augustss Static void ohci_device_ctrl_done(usbd_xfer_handle);
148 1.91 augustss
149 1.91 augustss Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle);
150 1.91 augustss Static usbd_status ohci_device_bulk_start(usbd_xfer_handle);
151 1.91 augustss Static void ohci_device_bulk_abort(usbd_xfer_handle);
152 1.91 augustss Static void ohci_device_bulk_close(usbd_pipe_handle);
153 1.91 augustss Static void ohci_device_bulk_done(usbd_xfer_handle);
154 1.91 augustss
155 1.91 augustss Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle);
156 1.91 augustss Static usbd_status ohci_device_intr_start(usbd_xfer_handle);
157 1.91 augustss Static void ohci_device_intr_abort(usbd_xfer_handle);
158 1.91 augustss Static void ohci_device_intr_close(usbd_pipe_handle);
159 1.91 augustss Static void ohci_device_intr_done(usbd_xfer_handle);
160 1.91 augustss
161 1.91 augustss Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle);
162 1.91 augustss Static usbd_status ohci_device_isoc_start(usbd_xfer_handle);
163 1.91 augustss Static void ohci_device_isoc_abort(usbd_xfer_handle);
164 1.91 augustss Static void ohci_device_isoc_close(usbd_pipe_handle);
165 1.91 augustss Static void ohci_device_isoc_done(usbd_xfer_handle);
166 1.91 augustss
167 1.254.2.15 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
168 1.254.2.15 skrll struct ohci_pipe *, int);
169 1.91 augustss
170 1.91 augustss Static void ohci_timeout(void *);
171 1.114 augustss Static void ohci_timeout_task(void *);
172 1.104 augustss Static void ohci_rhsc_enable(void *);
173 1.91 augustss
174 1.91 augustss Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *);
175 1.91 augustss Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status);
176 1.53 augustss
177 1.254.2.15 skrll Static void ohci_device_clear_toggle(usbd_pipe_handle);
178 1.254.2.15 skrll Static void ohci_noop(usbd_pipe_handle);
179 1.37 augustss
180 1.52 augustss #ifdef OHCI_DEBUG
181 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
182 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
183 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
184 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
185 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
186 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
187 1.1 augustss #endif
188 1.1 augustss
189 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
190 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
191 1.88 augustss #define OWRITE1(sc, r, x) \
192 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
193 1.88 augustss #define OWRITE2(sc, r, x) \
194 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
195 1.88 augustss #define OWRITE4(sc, r, x) \
196 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
197 1.174 mrg
198 1.174 mrg static __inline uint32_t
199 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
200 1.174 mrg {
201 1.174 mrg
202 1.174 mrg OBARR(sc);
203 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
204 1.174 mrg }
205 1.1 augustss
206 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
207 1.254.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
208 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
209 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
210 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
211 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
212 1.1 augustss
213 1.1 augustss struct ohci_pipe {
214 1.1 augustss struct usbd_pipe pipe;
215 1.1 augustss ohci_soft_ed_t *sed;
216 1.60 augustss union {
217 1.60 augustss ohci_soft_td_t *td;
218 1.60 augustss ohci_soft_itd_t *itd;
219 1.60 augustss } tail;
220 1.1 augustss /* Info needed for different pipe kinds. */
221 1.1 augustss union {
222 1.1 augustss /* Control pipe */
223 1.1 augustss struct {
224 1.4 augustss usb_dma_t reqdma;
225 1.1 augustss u_int length;
226 1.48 augustss ohci_soft_td_t *setup, *data, *stat;
227 1.1 augustss } ctl;
228 1.1 augustss /* Interrupt pipe */
229 1.1 augustss struct {
230 1.1 augustss int nslots;
231 1.1 augustss int pos;
232 1.1 augustss } intr;
233 1.3 augustss /* Bulk pipe */
234 1.3 augustss struct {
235 1.3 augustss u_int length;
236 1.32 augustss int isread;
237 1.3 augustss } bulk;
238 1.43 augustss /* Iso pipe */
239 1.43 augustss struct iso {
240 1.60 augustss int next, inuse;
241 1.43 augustss } iso;
242 1.1 augustss } u;
243 1.1 augustss };
244 1.1 augustss
245 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
246 1.254.2.5 skrll .ubm_open = ohci_open,
247 1.254.2.5 skrll .ubm_softint = ohci_softintr,
248 1.254.2.5 skrll .ubm_dopoll = ohci_poll,
249 1.254.2.5 skrll .ubm_allocx = ohci_allocx,
250 1.254.2.5 skrll .ubm_freex = ohci_freex,
251 1.254.2.5 skrll .ubm_getlock = ohci_get_lock,
252 1.254.2.12 skrll .ubm_rhctrl = ohci_roothub_ctrl,
253 1.1 augustss };
254 1.1 augustss
255 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
256 1.254.2.5 skrll .upm_transfer = ohci_root_intr_transfer,
257 1.254.2.5 skrll .upm_start = ohci_root_intr_start,
258 1.254.2.5 skrll .upm_abort = ohci_root_intr_abort,
259 1.254.2.5 skrll .upm_close = ohci_root_intr_close,
260 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
261 1.254.2.5 skrll .upm_done = ohci_root_intr_done,
262 1.1 augustss };
263 1.1 augustss
264 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
265 1.254.2.5 skrll .upm_transfer = ohci_device_ctrl_transfer,
266 1.254.2.5 skrll .upm_start = ohci_device_ctrl_start,
267 1.254.2.5 skrll .upm_abort = ohci_device_ctrl_abort,
268 1.254.2.5 skrll .upm_close = ohci_device_ctrl_close,
269 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
270 1.254.2.5 skrll .upm_done = ohci_device_ctrl_done,
271 1.1 augustss };
272 1.1 augustss
273 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
274 1.254.2.5 skrll .upm_transfer = ohci_device_intr_transfer,
275 1.254.2.5 skrll .upm_start = ohci_device_intr_start,
276 1.254.2.5 skrll .upm_abort = ohci_device_intr_abort,
277 1.254.2.5 skrll .upm_close = ohci_device_intr_close,
278 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
279 1.254.2.5 skrll .upm_done = ohci_device_intr_done,
280 1.1 augustss };
281 1.1 augustss
282 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
283 1.254.2.5 skrll .upm_transfer = ohci_device_bulk_transfer,
284 1.254.2.5 skrll .upm_start = ohci_device_bulk_start,
285 1.254.2.5 skrll .upm_abort = ohci_device_bulk_abort,
286 1.254.2.5 skrll .upm_close = ohci_device_bulk_close,
287 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
288 1.254.2.5 skrll .upm_done = ohci_device_bulk_done,
289 1.3 augustss };
290 1.3 augustss
291 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
292 1.254.2.5 skrll .upm_transfer = ohci_device_isoc_transfer,
293 1.254.2.5 skrll .upm_start = ohci_device_isoc_start,
294 1.254.2.5 skrll .upm_abort = ohci_device_isoc_abort,
295 1.254.2.5 skrll .upm_close = ohci_device_isoc_close,
296 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
297 1.254.2.5 skrll .upm_done = ohci_device_isoc_done,
298 1.43 augustss };
299 1.43 augustss
300 1.47 augustss int
301 1.189 dyoung ohci_activate(device_t self, enum devact act)
302 1.47 augustss {
303 1.189 dyoung struct ohci_softc *sc = device_private(self);
304 1.47 augustss
305 1.47 augustss switch (act) {
306 1.47 augustss case DVACT_DEACTIVATE:
307 1.183 kiyohara sc->sc_dying = 1;
308 1.203 dyoung return 0;
309 1.203 dyoung default:
310 1.203 dyoung return EOPNOTSUPP;
311 1.47 augustss }
312 1.47 augustss }
313 1.47 augustss
314 1.187 dyoung void
315 1.187 dyoung ohci_childdet(device_t self, device_t child)
316 1.187 dyoung {
317 1.187 dyoung struct ohci_softc *sc = device_private(self);
318 1.187 dyoung
319 1.187 dyoung KASSERT(sc->sc_child == child);
320 1.187 dyoung sc->sc_child = NULL;
321 1.187 dyoung }
322 1.187 dyoung
323 1.47 augustss int
324 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
325 1.47 augustss {
326 1.47 augustss int rv = 0;
327 1.47 augustss
328 1.47 augustss if (sc->sc_child != NULL)
329 1.47 augustss rv = config_detach(sc->sc_child, flags);
330 1.120 augustss
331 1.47 augustss if (rv != 0)
332 1.254.2.13 skrll return rv;
333 1.47 augustss
334 1.254 ozaki callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
335 1.104 augustss
336 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
337 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
338 1.116 augustss
339 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
340 1.224 mrg
341 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
342 1.224 mrg
343 1.224 mrg mutex_destroy(&sc->sc_lock);
344 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
345 1.224 mrg
346 1.198 cegger if (sc->sc_hcca != NULL)
347 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
348 1.232 christos pool_cache_destroy(sc->sc_xferpool);
349 1.47 augustss
350 1.254.2.13 skrll return rv;
351 1.47 augustss }
352 1.47 augustss
353 1.1 augustss ohci_soft_ed_t *
354 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
355 1.1 augustss {
356 1.1 augustss ohci_soft_ed_t *sed;
357 1.53 augustss usbd_status err;
358 1.1 augustss int i, offs;
359 1.4 augustss usb_dma_t dma;
360 1.1 augustss
361 1.53 augustss if (sc->sc_freeeds == NULL) {
362 1.1 augustss DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
363 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
364 1.53 augustss OHCI_ED_ALIGN, &dma);
365 1.53 augustss if (err)
366 1.254.2.13 skrll return 0;
367 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
368 1.39 augustss offs = i * OHCI_SED_SIZE;
369 1.123 augustss sed = KERNADDR(&dma, offs);
370 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
371 1.195 bouyer sed->dma = dma;
372 1.195 bouyer sed->offs = offs;
373 1.1 augustss sed->next = sc->sc_freeeds;
374 1.1 augustss sc->sc_freeeds = sed;
375 1.1 augustss }
376 1.1 augustss }
377 1.1 augustss sed = sc->sc_freeeds;
378 1.1 augustss sc->sc_freeeds = sed->next;
379 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
380 1.1 augustss sed->next = 0;
381 1.254.2.13 skrll return sed;
382 1.1 augustss }
383 1.1 augustss
384 1.1 augustss void
385 1.91 augustss ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
386 1.1 augustss {
387 1.1 augustss sed->next = sc->sc_freeeds;
388 1.1 augustss sc->sc_freeeds = sed;
389 1.1 augustss }
390 1.1 augustss
391 1.1 augustss ohci_soft_td_t *
392 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
393 1.1 augustss {
394 1.1 augustss ohci_soft_td_t *std;
395 1.53 augustss usbd_status err;
396 1.1 augustss int i, offs;
397 1.4 augustss usb_dma_t dma;
398 1.1 augustss
399 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
400 1.240 skrll
401 1.53 augustss if (sc->sc_freetds == NULL) {
402 1.1 augustss DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
403 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
404 1.53 augustss OHCI_TD_ALIGN, &dma);
405 1.53 augustss if (err)
406 1.254.2.13 skrll return NULL;
407 1.39 augustss for(i = 0; i < OHCI_STD_CHUNK; i++) {
408 1.39 augustss offs = i * OHCI_STD_SIZE;
409 1.123 augustss std = KERNADDR(&dma, offs);
410 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
411 1.195 bouyer std->dma = dma;
412 1.195 bouyer std->offs = offs;
413 1.1 augustss std->nexttd = sc->sc_freetds;
414 1.1 augustss sc->sc_freetds = std;
415 1.1 augustss }
416 1.1 augustss }
417 1.69 augustss
418 1.1 augustss std = sc->sc_freetds;
419 1.1 augustss sc->sc_freetds = std->nexttd;
420 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
421 1.83 augustss std->nexttd = NULL;
422 1.83 augustss std->xfer = NULL;
423 1.69 augustss ohci_hash_add_td(sc, std);
424 1.69 augustss
425 1.254.2.13 skrll return std;
426 1.1 augustss }
427 1.1 augustss
428 1.1 augustss void
429 1.91 augustss ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
430 1.1 augustss {
431 1.254.2.7 skrll
432 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
433 1.254.2.1 skrll
434 1.69 augustss ohci_hash_rem_td(sc, std);
435 1.1 augustss std->nexttd = sc->sc_freetds;
436 1.1 augustss sc->sc_freetds = std;
437 1.1 augustss }
438 1.1 augustss
439 1.1 augustss usbd_status
440 1.91 augustss ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc,
441 1.91 augustss int alen, int rd, usbd_xfer_handle xfer,
442 1.91 augustss ohci_soft_td_t *sp, ohci_soft_td_t **ep)
443 1.48 augustss {
444 1.48 augustss ohci_soft_td_t *next, *cur;
445 1.48 augustss ohci_physaddr_t dataphys, dataphysend;
446 1.254.2.1 skrll uint32_t tdflags;
447 1.75 augustss int len, curlen;
448 1.254.2.7 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
449 1.254.2.7 skrll uint16_t flags = xfer->ux_flags;
450 1.48 augustss
451 1.75 augustss DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen));
452 1.75 augustss
453 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
454 1.224 mrg
455 1.75 augustss len = alen;
456 1.48 augustss cur = sp;
457 1.125 augustss dataphys = DMAADDR(dma, 0);
458 1.48 augustss dataphysend = OHCI_PAGE(dataphys + len - 1);
459 1.195 bouyer usb_syncmem(dma, 0, len,
460 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
461 1.168 augustss tdflags = HTOO32(
462 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
463 1.77 augustss (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) |
464 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
465 1.61 augustss
466 1.48 augustss for (;;) {
467 1.48 augustss next = ohci_alloc_std(sc);
468 1.75 augustss if (next == NULL)
469 1.61 augustss goto nomem;
470 1.48 augustss
471 1.48 augustss /* The OHCI hardware can handle at most one page crossing. */
472 1.48 augustss if (OHCI_PAGE(dataphys) == dataphysend ||
473 1.48 augustss OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
474 1.48 augustss /* we can handle it in this TD */
475 1.48 augustss curlen = len;
476 1.48 augustss } else {
477 1.48 augustss /* must use multiple TDs, fill as much as possible. */
478 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
479 1.48 augustss (dataphys & (OHCI_PAGE_SIZE-1));
480 1.78 augustss /* the length must be a multiple of the max size */
481 1.254.2.7 skrll curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
482 1.78 augustss #ifdef DIAGNOSTIC
483 1.78 augustss if (curlen == 0)
484 1.128 provos panic("ohci_alloc_std: curlen == 0");
485 1.78 augustss #endif
486 1.48 augustss }
487 1.48 augustss DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x "
488 1.48 augustss "dataphysend=0x%08x len=%d curlen=%d\n",
489 1.48 augustss dataphys, dataphysend,
490 1.48 augustss len, curlen));
491 1.48 augustss len -= curlen;
492 1.48 augustss
493 1.77 augustss cur->td.td_flags = tdflags;
494 1.168 augustss cur->td.td_cbp = HTOO32(dataphys);
495 1.48 augustss cur->nexttd = next;
496 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
497 1.168 augustss cur->td.td_be = HTOO32(dataphys + curlen - 1);
498 1.48 augustss cur->len = curlen;
499 1.48 augustss cur->flags = OHCI_ADD_LEN;
500 1.77 augustss cur->xfer = xfer;
501 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
502 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
503 1.48 augustss DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n",
504 1.48 augustss dataphys, dataphys + curlen - 1));
505 1.48 augustss if (len == 0)
506 1.48 augustss break;
507 1.48 augustss DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n"));
508 1.48 augustss dataphys += curlen;
509 1.48 augustss cur = next;
510 1.48 augustss }
511 1.164 augustss if (!rd && (flags & USBD_FORCE_SHORT_XFER) &&
512 1.254.2.7 skrll alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) {
513 1.61 augustss /* Force a 0 length transfer at the end. */
514 1.75 augustss
515 1.75 augustss cur = next;
516 1.61 augustss next = ohci_alloc_std(sc);
517 1.75 augustss if (next == NULL)
518 1.61 augustss goto nomem;
519 1.61 augustss
520 1.77 augustss cur->td.td_flags = tdflags;
521 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
522 1.61 augustss cur->nexttd = next;
523 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
524 1.75 augustss cur->td.td_be = ~0;
525 1.61 augustss cur->len = 0;
526 1.61 augustss cur->flags = 0;
527 1.77 augustss cur->xfer = xfer;
528 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
529 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
530 1.61 augustss DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n"));
531 1.61 augustss }
532 1.77 augustss *ep = cur;
533 1.48 augustss
534 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
535 1.61 augustss
536 1.61 augustss nomem:
537 1.236 skrll
538 1.236 skrll /* Don't free sp - let the caller do that */
539 1.236 skrll ohci_free_std_chain(sc, sp->nexttd, NULL);
540 1.236 skrll
541 1.254.2.13 skrll return USBD_NOMEM;
542 1.48 augustss }
543 1.48 augustss
544 1.82 augustss Static void
545 1.120 augustss ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std,
546 1.91 augustss ohci_soft_td_t *stdend)
547 1.48 augustss {
548 1.48 augustss ohci_soft_td_t *p;
549 1.48 augustss
550 1.48 augustss for (; std != stdend; std = p) {
551 1.48 augustss p = std->nexttd;
552 1.48 augustss ohci_free_std(sc, std);
553 1.48 augustss }
554 1.48 augustss }
555 1.48 augustss
556 1.60 augustss ohci_soft_itd_t *
557 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
558 1.60 augustss {
559 1.60 augustss ohci_soft_itd_t *sitd;
560 1.60 augustss usbd_status err;
561 1.224 mrg int i, offs;
562 1.60 augustss usb_dma_t dma;
563 1.60 augustss
564 1.60 augustss if (sc->sc_freeitds == NULL) {
565 1.60 augustss DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n"));
566 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
567 1.83 augustss OHCI_ITD_ALIGN, &dma);
568 1.60 augustss if (err)
569 1.254.2.13 skrll return NULL;
570 1.83 augustss for(i = 0; i < OHCI_SITD_CHUNK; i++) {
571 1.83 augustss offs = i * OHCI_SITD_SIZE;
572 1.123 augustss sitd = KERNADDR(&dma, offs);
573 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
574 1.195 bouyer sitd->dma = dma;
575 1.195 bouyer sitd->offs = offs;
576 1.60 augustss sitd->nextitd = sc->sc_freeitds;
577 1.60 augustss sc->sc_freeitds = sitd;
578 1.60 augustss }
579 1.60 augustss }
580 1.83 augustss
581 1.60 augustss sitd = sc->sc_freeitds;
582 1.60 augustss sc->sc_freeitds = sitd->nextitd;
583 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
584 1.83 augustss sitd->nextitd = NULL;
585 1.83 augustss sitd->xfer = NULL;
586 1.83 augustss ohci_hash_add_itd(sc, sitd);
587 1.83 augustss
588 1.83 augustss #ifdef DIAGNOSTIC
589 1.83 augustss sitd->isdone = 0;
590 1.83 augustss #endif
591 1.83 augustss
592 1.254.2.13 skrll return sitd;
593 1.60 augustss }
594 1.60 augustss
595 1.60 augustss void
596 1.91 augustss ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
597 1.60 augustss {
598 1.83 augustss
599 1.83 augustss DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd));
600 1.83 augustss
601 1.83 augustss #ifdef DIAGNOSTIC
602 1.83 augustss if (!sitd->isdone) {
603 1.128 provos panic("ohci_free_sitd: sitd=%p not done", sitd);
604 1.83 augustss return;
605 1.83 augustss }
606 1.134 toshii /* Warn double free */
607 1.134 toshii sitd->isdone = 0;
608 1.83 augustss #endif
609 1.83 augustss
610 1.83 augustss ohci_hash_rem_itd(sc, sitd);
611 1.60 augustss sitd->nextitd = sc->sc_freeitds;
612 1.60 augustss sc->sc_freeitds = sitd;
613 1.60 augustss }
614 1.60 augustss
615 1.254.2.14 skrll int
616 1.91 augustss ohci_init(ohci_softc_t *sc)
617 1.1 augustss {
618 1.1 augustss ohci_soft_ed_t *sed, *psed;
619 1.53 augustss usbd_status err;
620 1.1 augustss int i;
621 1.254.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
622 1.16 augustss
623 1.1 augustss DPRINTF(("ohci_init: start\n"));
624 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
625 1.199 jmcneill
626 1.198 cegger sc->sc_hcca = NULL;
627 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
628 1.224 mrg
629 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
630 1.224 mrg mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED);
631 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
632 1.224 mrg
633 1.224 mrg sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
634 1.224 mrg ohci_rhsc_softint, sc);
635 1.198 cegger
636 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
637 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
638 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
639 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
640 1.198 cegger
641 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
642 1.232 christos "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
643 1.198 cegger
644 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
645 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
646 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
647 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
648 1.55 augustss
649 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
650 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
651 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
652 1.254.2.14 skrll return -1;
653 1.1 augustss }
654 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_1_0;
655 1.254.2.7 skrll sc->sc_bus.ub_usedma = true;
656 1.153 fvdl
657 1.73 augustss /* XXX determine alignment by R/W */
658 1.1 augustss /* Allocate the HCCA area. */
659 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
660 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
661 1.198 cegger if (err) {
662 1.198 cegger sc->sc_hcca = NULL;
663 1.198 cegger return err;
664 1.198 cegger }
665 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
666 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
667 1.1 augustss
668 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
669 1.1 augustss
670 1.60 augustss /* Allocate dummy ED that starts the control list. */
671 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
672 1.53 augustss if (sc->sc_ctrl_head == NULL) {
673 1.254.2.14 skrll err = ENOMEM;
674 1.1 augustss goto bad1;
675 1.1 augustss }
676 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
677 1.34 augustss
678 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
679 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
680 1.53 augustss if (sc->sc_bulk_head == NULL) {
681 1.254.2.14 skrll err = ENOMEM;
682 1.1 augustss goto bad2;
683 1.1 augustss }
684 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
685 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
686 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
687 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
688 1.1 augustss
689 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
690 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
691 1.60 augustss if (sc->sc_isoc_head == NULL) {
692 1.254.2.14 skrll err = ENOMEM;
693 1.60 augustss goto bad3;
694 1.60 augustss }
695 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
696 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
697 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
698 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
699 1.60 augustss
700 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
701 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
702 1.1 augustss sed = ohci_alloc_sed(sc);
703 1.53 augustss if (sed == NULL) {
704 1.1 augustss while (--i >= 0)
705 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
706 1.254.2.14 skrll err = ENOMEM;
707 1.60 augustss goto bad4;
708 1.1 augustss }
709 1.1 augustss /* All ED fields are set to 0. */
710 1.1 augustss sc->sc_eds[i] = sed;
711 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
712 1.60 augustss if (i != 0)
713 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
714 1.60 augustss else
715 1.60 augustss psed= sc->sc_isoc_head;
716 1.60 augustss sed->next = psed;
717 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
718 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
719 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
720 1.1 augustss }
721 1.120 augustss /*
722 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
723 1.1 augustss * the tree set up properly to spread the interrupts.
724 1.1 augustss */
725 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
726 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
727 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
728 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
729 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
730 1.1 augustss
731 1.73 augustss #ifdef OHCI_DEBUG
732 1.73 augustss if (ohcidebug > 15) {
733 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
734 1.73 augustss printf("ed#%d ", i);
735 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
736 1.73 augustss }
737 1.73 augustss printf("iso ");
738 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
739 1.73 augustss }
740 1.73 augustss #endif
741 1.73 augustss
742 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
743 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
744 1.161 augustss rwc = ctl & OHCI_RWC;
745 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
746 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
747 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
748 1.161 augustss
749 1.1 augustss /* Determine in what context we are running. */
750 1.1 augustss if (ctl & OHCI_IR) {
751 1.1 augustss /* SMM active, request change */
752 1.1 augustss DPRINTF(("ohci_init: SMM active, request owner change\n"));
753 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
754 1.160 augustss (OHCI_OC | OHCI_MIE))
755 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
756 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
757 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
758 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
759 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
760 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
761 1.1 augustss }
762 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
763 1.1 augustss if ((ctl & OHCI_IR) == 0) {
764 1.199 jmcneill aprint_error_dev(sc->sc_dev,
765 1.199 jmcneill "SMM does not respond, resetting\n");
766 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
767 1.1 augustss goto reset;
768 1.1 augustss }
769 1.103 augustss #if 0
770 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
771 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
772 1.1 augustss /* BIOS started controller. */
773 1.1 augustss DPRINTF(("ohci_init: BIOS active\n"));
774 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
775 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
776 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
777 1.1 augustss }
778 1.103 augustss #endif
779 1.1 augustss } else {
780 1.1 augustss DPRINTF(("ohci_init: cold started\n"));
781 1.1 augustss reset:
782 1.1 augustss /* Controller was cold started. */
783 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
784 1.1 augustss }
785 1.1 augustss
786 1.16 augustss /*
787 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
788 1.25 augustss * without it some controllers do not start.
789 1.16 augustss */
790 1.190 drochner DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev)));
791 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
792 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
793 1.16 augustss
794 1.1 augustss /* We now own the host controller and the bus has been reset. */
795 1.1 augustss
796 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
797 1.1 augustss /* Nominal time for a reset is 10 us. */
798 1.1 augustss for (i = 0; i < 10; i++) {
799 1.1 augustss delay(10);
800 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
801 1.1 augustss if (!hcr)
802 1.1 augustss break;
803 1.1 augustss }
804 1.1 augustss if (hcr) {
805 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
806 1.254.2.14 skrll err = EIO;
807 1.60 augustss goto bad5;
808 1.1 augustss }
809 1.52 augustss #ifdef OHCI_DEBUG
810 1.1 augustss if (ohcidebug > 15)
811 1.1 augustss ohci_dumpregs(sc);
812 1.1 augustss #endif
813 1.1 augustss
814 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
815 1.1 augustss
816 1.1 augustss /* Set up HC registers. */
817 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
818 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
819 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
820 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
821 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
822 1.55 augustss /* switch on desired functional features */
823 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
824 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
825 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
826 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
827 1.1 augustss /* And finally start it! */
828 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
829 1.1 augustss
830 1.1 augustss /*
831 1.1 augustss * The controller is now OPERATIONAL. Set a some final
832 1.1 augustss * registers that should be set earlier, but that the
833 1.1 augustss * controller ignores when in the SUSPEND state.
834 1.1 augustss */
835 1.161 augustss ival = OHCI_GET_IVAL(fm);
836 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
837 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
838 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
839 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
840 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
841 1.1 augustss
842 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
843 1.249 skrll /* no overcurrent protection */
844 1.249 skrll desca |= OHCI_NOCP;
845 1.249 skrll /*
846 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
847 1.249 skrll * that
848 1.249 skrll * - ports are always power switched
849 1.249 skrll * - don't wait for powered root hub port
850 1.249 skrll */
851 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
852 1.249 skrll }
853 1.249 skrll
854 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
855 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
856 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
857 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
858 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
859 1.1 augustss
860 1.85 augustss /*
861 1.85 augustss * The AMD756 requires a delay before re-reading the register,
862 1.85 augustss * otherwise it will occasionally report 0 ports.
863 1.85 augustss */
864 1.145 augustss sc->sc_noport = 0;
865 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
866 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
867 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
868 1.145 augustss }
869 1.1 augustss
870 1.52 augustss #ifdef OHCI_DEBUG
871 1.1 augustss if (ohcidebug > 5)
872 1.1 augustss ohci_dumpregs(sc);
873 1.1 augustss #endif
874 1.120 augustss
875 1.1 augustss /* Set up the bus struct. */
876 1.254.2.7 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
877 1.254.2.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
878 1.1 augustss
879 1.101 minoura sc->sc_control = sc->sc_intre = 0;
880 1.59 augustss
881 1.167 augustss /* Finally, turn on interrupts. */
882 1.211 matt DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE));
883 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
884 1.167 augustss
885 1.254.2.14 skrll return 0;
886 1.1 augustss
887 1.60 augustss bad5:
888 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
889 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
890 1.60 augustss bad4:
891 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
892 1.1 augustss bad3:
893 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
894 1.144 augustss bad2:
895 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
896 1.1 augustss bad1:
897 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
898 1.198 cegger sc->sc_hcca = NULL;
899 1.254.2.13 skrll return err;
900 1.1 augustss }
901 1.1 augustss
902 1.62 augustss usbd_xfer_handle
903 1.91 augustss ohci_allocx(struct usbd_bus *bus)
904 1.62 augustss {
905 1.254.2.7 skrll struct ohci_softc *sc = bus->ub_hcpriv;
906 1.62 augustss usbd_xfer_handle xfer;
907 1.62 augustss
908 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
909 1.118 augustss if (xfer != NULL) {
910 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
911 1.118 augustss #ifdef DIAGNOSTIC
912 1.254.2.7 skrll xfer->ux_state = XFER_BUSY;
913 1.118 augustss #endif
914 1.118 augustss }
915 1.254.2.13 skrll return xfer;
916 1.62 augustss }
917 1.62 augustss
918 1.62 augustss void
919 1.91 augustss ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
920 1.62 augustss {
921 1.254.2.7 skrll struct ohci_softc *sc = bus->ub_hcpriv;
922 1.62 augustss
923 1.118 augustss #ifdef DIAGNOSTIC
924 1.254.2.7 skrll if (xfer->ux_state != XFER_BUSY) {
925 1.118 augustss printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer,
926 1.254.2.7 skrll xfer->ux_state);
927 1.118 augustss }
928 1.254.2.7 skrll xfer->ux_state = XFER_FREE;
929 1.118 augustss #endif
930 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
931 1.42 augustss }
932 1.42 augustss
933 1.224 mrg Static void
934 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
935 1.224 mrg {
936 1.254.2.7 skrll struct ohci_softc *sc = bus->ub_hcpriv;
937 1.224 mrg
938 1.224 mrg *lock = &sc->sc_lock;
939 1.224 mrg }
940 1.224 mrg
941 1.59 augustss /*
942 1.59 augustss * Shut down the controller when the system is going down.
943 1.59 augustss */
944 1.188 dyoung bool
945 1.188 dyoung ohci_shutdown(device_t self, int flags)
946 1.59 augustss {
947 1.188 dyoung ohci_softc_t *sc = device_private(self);
948 1.59 augustss
949 1.59 augustss DPRINTF(("ohci_shutdown: stopping the HC\n"));
950 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
951 1.188 dyoung return true;
952 1.59 augustss }
953 1.59 augustss
954 1.185 jmcneill bool
955 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
956 1.33 augustss {
957 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
958 1.185 jmcneill uint32_t ctl;
959 1.33 augustss
960 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
961 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
962 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
963 1.224 mrg
964 1.185 jmcneill /* Some broken BIOSes do not recover these values */
965 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
966 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
967 1.185 jmcneill sc->sc_ctrl_head->physaddr);
968 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
969 1.185 jmcneill sc->sc_bulk_head->physaddr);
970 1.185 jmcneill if (sc->sc_intre)
971 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
972 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
973 1.185 jmcneill if (sc->sc_control)
974 1.185 jmcneill ctl = sc->sc_control;
975 1.185 jmcneill else
976 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
977 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
978 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
979 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
980 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
981 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
982 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
983 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
984 1.224 mrg
985 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
986 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
987 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
988 1.185 jmcneill
989 1.185 jmcneill return true;
990 1.185 jmcneill }
991 1.185 jmcneill
992 1.185 jmcneill bool
993 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
994 1.185 jmcneill {
995 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
996 1.185 jmcneill uint32_t ctl;
997 1.95 augustss
998 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
999 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1000 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1001 1.224 mrg
1002 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1003 1.185 jmcneill if (sc->sc_control == 0) {
1004 1.185 jmcneill /*
1005 1.185 jmcneill * Preserve register values, in case that BIOS
1006 1.185 jmcneill * does not recover them.
1007 1.185 jmcneill */
1008 1.185 jmcneill sc->sc_control = ctl;
1009 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1010 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1011 1.95 augustss }
1012 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1013 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1014 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1015 1.224 mrg
1016 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1017 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1018 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1019 1.185 jmcneill
1020 1.185 jmcneill return true;
1021 1.33 augustss }
1022 1.33 augustss
1023 1.52 augustss #ifdef OHCI_DEBUG
1024 1.1 augustss void
1025 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1026 1.1 augustss {
1027 1.41 augustss DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
1028 1.41 augustss OREAD4(sc, OHCI_REVISION),
1029 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1030 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
1031 1.41 augustss DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
1032 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1033 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1034 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_DISABLE)));
1035 1.41 augustss DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
1036 1.41 augustss OREAD4(sc, OHCI_HCCA),
1037 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1038 1.41 augustss OREAD4(sc, OHCI_CONTROL_HEAD_ED)));
1039 1.41 augustss DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
1040 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1041 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1042 1.41 augustss OREAD4(sc, OHCI_BULK_CURRENT_ED)));
1043 1.41 augustss DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
1044 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1045 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1046 1.41 augustss OREAD4(sc, OHCI_FM_REMAINING)));
1047 1.41 augustss DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
1048 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1049 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1050 1.41 augustss OREAD4(sc, OHCI_LS_THRESHOLD)));
1051 1.41 augustss DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n",
1052 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1053 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1054 1.41 augustss OREAD4(sc, OHCI_RH_STATUS)));
1055 1.41 augustss DPRINTF((" port1=0x%08x port2=0x%08x\n",
1056 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1057 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(2))));
1058 1.41 augustss DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n",
1059 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1060 1.168 augustss O32TOH(sc->sc_hcca->hcca_done_head)));
1061 1.1 augustss }
1062 1.1 augustss #endif
1063 1.1 augustss
1064 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1065 1.53 augustss
1066 1.1 augustss int
1067 1.91 augustss ohci_intr(void *p)
1068 1.1 augustss {
1069 1.1 augustss ohci_softc_t *sc = p;
1070 1.224 mrg int ret = 0;
1071 1.111 augustss
1072 1.224 mrg if (sc == NULL)
1073 1.254.2.13 skrll return 0;
1074 1.53 augustss
1075 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1076 1.224 mrg
1077 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1078 1.224 mrg goto done;
1079 1.224 mrg
1080 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1081 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling) {
1082 1.57 augustss #ifdef DIAGNOSTIC
1083 1.149 mycroft DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n"));
1084 1.57 augustss #endif
1085 1.154 joff /* for level triggered intrs, should do something to ack */
1086 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1087 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1088 1.155 perry
1089 1.224 mrg goto done;
1090 1.57 augustss }
1091 1.53 augustss
1092 1.224 mrg ret = ohci_intr1(sc);
1093 1.224 mrg
1094 1.224 mrg done:
1095 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1096 1.224 mrg return ret;
1097 1.53 augustss }
1098 1.53 augustss
1099 1.82 augustss Static int
1100 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1101 1.53 augustss {
1102 1.254.2.1 skrll uint32_t intrs, eintrs;
1103 1.1 augustss
1104 1.105 augustss DPRINTFN(14,("ohci_intr1: enter\n"));
1105 1.105 augustss
1106 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1107 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1108 1.15 augustss #ifdef DIAGNOSTIC
1109 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1110 1.15 augustss #endif
1111 1.254.2.13 skrll return 0;
1112 1.15 augustss }
1113 1.15 augustss
1114 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1115 1.224 mrg
1116 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1117 1.1 augustss if (!intrs)
1118 1.254.2.13 skrll return 0;
1119 1.55 augustss
1120 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */
1121 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1122 1.211 matt DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n",
1123 1.211 matt sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
1124 1.211 matt (u_int)eintrs, sc->sc_eintrs));
1125 1.211 matt
1126 1.211 matt if (!eintrs) {
1127 1.254.2.13 skrll return 0;
1128 1.211 matt }
1129 1.1 augustss
1130 1.1 augustss if (eintrs & OHCI_SO) {
1131 1.100 augustss sc->sc_overrun_cnt++;
1132 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1133 1.100 augustss printf("%s: %u scheduling overruns\n",
1134 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1135 1.100 augustss sc->sc_overrun_cnt = 0;
1136 1.100 augustss }
1137 1.1 augustss /* XXX do what */
1138 1.106 augustss eintrs &= ~OHCI_SO;
1139 1.1 augustss }
1140 1.1 augustss if (eintrs & OHCI_WDH) {
1141 1.157 mycroft /*
1142 1.157 mycroft * We block the interrupt below, and reenable it later from
1143 1.157 mycroft * ohci_softintr().
1144 1.157 mycroft */
1145 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1146 1.1 augustss }
1147 1.1 augustss if (eintrs & OHCI_RD) {
1148 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1149 1.1 augustss /* XXX process resume detect */
1150 1.1 augustss }
1151 1.1 augustss if (eintrs & OHCI_UE) {
1152 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1153 1.190 drochner device_xname(sc->sc_dev));
1154 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1155 1.1 augustss /* XXX what else */
1156 1.1 augustss }
1157 1.1 augustss if (eintrs & OHCI_RHSC) {
1158 1.120 augustss /*
1159 1.157 mycroft * We block the interrupt below, and reenable it later from
1160 1.157 mycroft * a timeout.
1161 1.1 augustss */
1162 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1163 1.1 augustss }
1164 1.1 augustss
1165 1.106 augustss if (eintrs != 0) {
1166 1.157 mycroft /* Block unprocessed interrupts. */
1167 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1168 1.106 augustss sc->sc_eintrs &= ~eintrs;
1169 1.157 mycroft DPRINTFN(1, ("%s: blocking intrs 0x%x\n",
1170 1.190 drochner device_xname(sc->sc_dev), eintrs));
1171 1.106 augustss }
1172 1.1 augustss
1173 1.254.2.13 skrll return 1;
1174 1.1 augustss }
1175 1.1 augustss
1176 1.1 augustss void
1177 1.104 augustss ohci_rhsc_enable(void *v_sc)
1178 1.104 augustss {
1179 1.104 augustss ohci_softc_t *sc = v_sc;
1180 1.104 augustss
1181 1.224 mrg DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev)));
1182 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1183 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1184 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1185 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1186 1.1 augustss }
1187 1.1 augustss
1188 1.52 augustss #ifdef OHCI_DEBUG
1189 1.166 drochner const char *ohci_cc_strs[] = {
1190 1.13 augustss "NO_ERROR",
1191 1.13 augustss "CRC",
1192 1.13 augustss "BIT_STUFFING",
1193 1.13 augustss "DATA_TOGGLE_MISMATCH",
1194 1.13 augustss "STALL",
1195 1.13 augustss "DEVICE_NOT_RESPONDING",
1196 1.13 augustss "PID_CHECK_FAILURE",
1197 1.13 augustss "UNEXPECTED_PID",
1198 1.13 augustss "DATA_OVERRUN",
1199 1.13 augustss "DATA_UNDERRUN",
1200 1.13 augustss "BUFFER_OVERRUN",
1201 1.13 augustss "BUFFER_UNDERRUN",
1202 1.67 augustss "reserved",
1203 1.67 augustss "reserved",
1204 1.67 augustss "NOT_ACCESSED",
1205 1.13 augustss "NOT_ACCESSED",
1206 1.13 augustss };
1207 1.13 augustss #endif
1208 1.13 augustss
1209 1.1 augustss void
1210 1.157 mycroft ohci_softintr(void *v)
1211 1.83 augustss {
1212 1.190 drochner struct usbd_bus *bus = v;
1213 1.254.2.7 skrll ohci_softc_t *sc = bus->ub_hcpriv;
1214 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1215 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1216 1.157 mycroft usbd_xfer_handle xfer;
1217 1.157 mycroft struct ohci_pipe *opipe;
1218 1.224 mrg int len, cc;
1219 1.157 mycroft int i, j, actlen, iframes, uedir;
1220 1.157 mycroft ohci_physaddr_t done;
1221 1.157 mycroft
1222 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1223 1.224 mrg
1224 1.157 mycroft DPRINTFN(10,("ohci_softintr: enter\n"));
1225 1.157 mycroft
1226 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1227 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1228 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1229 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1230 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1231 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1232 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1233 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1234 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1235 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1236 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1237 1.83 augustss
1238 1.83 augustss /* Reverse the done list. */
1239 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1240 1.83 augustss std = ohci_hash_find_td(sc, done);
1241 1.83 augustss if (std != NULL) {
1242 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1243 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1244 1.83 augustss std->dnext = sdone;
1245 1.168 augustss done = O32TOH(std->td.td_nexttd);
1246 1.83 augustss sdone = std;
1247 1.83 augustss DPRINTFN(10,("add TD %p\n", std));
1248 1.83 augustss continue;
1249 1.83 augustss }
1250 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1251 1.83 augustss if (sitd != NULL) {
1252 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1253 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1254 1.83 augustss sitd->dnext = sidone;
1255 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1256 1.83 augustss sidone = sitd;
1257 1.83 augustss DPRINTFN(5,("add ITD %p\n", sitd));
1258 1.83 augustss continue;
1259 1.83 augustss }
1260 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1261 1.218 jmcneill (u_long)done);
1262 1.218 jmcneill break;
1263 1.83 augustss }
1264 1.83 augustss
1265 1.105 augustss DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone));
1266 1.1 augustss
1267 1.52 augustss #ifdef OHCI_DEBUG
1268 1.1 augustss if (ohcidebug > 10) {
1269 1.41 augustss DPRINTF(("ohci_process_done: TD done:\n"));
1270 1.234 skrll for (std = sdone; std; std = std->dnext)
1271 1.254.2.1 skrll ohci_dump_td(sc, std);
1272 1.1 augustss }
1273 1.1 augustss #endif
1274 1.1 augustss
1275 1.48 augustss for (std = sdone; std; std = stdnext) {
1276 1.53 augustss xfer = std->xfer;
1277 1.48 augustss stdnext = std->dnext;
1278 1.53 augustss DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n",
1279 1.254.2.7 skrll std, xfer, xfer ? xfer->ux_hcpriv : 0));
1280 1.71 augustss if (xfer == NULL) {
1281 1.117 augustss /*
1282 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1283 1.71 augustss * with this TD. It is tailp that happened to end up on
1284 1.71 augustss * the done queue.
1285 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1286 1.71 augustss */
1287 1.71 augustss continue;
1288 1.71 augustss }
1289 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1290 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1291 1.34 augustss DPRINTF(("ohci_process_done: cancel/timeout %p\n",
1292 1.53 augustss xfer));
1293 1.38 augustss /* Handled by abort routine. */
1294 1.83 augustss continue;
1295 1.83 augustss }
1296 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
1297 1.141 mycroft
1298 1.141 mycroft len = std->len;
1299 1.141 mycroft if (std->td.td_cbp != 0)
1300 1.168 augustss len -= O32TOH(std->td.td_be) -
1301 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1302 1.141 mycroft DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len,
1303 1.141 mycroft std->flags));
1304 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1305 1.254.2.7 skrll xfer->ux_actlen += len;
1306 1.141 mycroft
1307 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1308 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1309 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1310 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1311 1.53 augustss usb_transfer_complete(xfer);
1312 1.21 augustss }
1313 1.48 augustss ohci_free_std(sc, std);
1314 1.1 augustss } else {
1315 1.48 augustss /*
1316 1.48 augustss * Endpoint is halted. First unlink all the TDs
1317 1.48 augustss * belonging to the failed transfer, and then restart
1318 1.48 augustss * the endpoint.
1319 1.48 augustss */
1320 1.1 augustss ohci_soft_td_t *p, *n;
1321 1.254.2.7 skrll opipe = (struct ohci_pipe *)xfer->ux_pipe;
1322 1.48 augustss
1323 1.71 augustss DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n",
1324 1.168 augustss OHCI_TD_GET_CC(O32TOH(std->td.td_flags)),
1325 1.168 augustss ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))]));
1326 1.48 augustss
1327 1.48 augustss /* remove TDs */
1328 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1329 1.1 augustss n = p->nexttd;
1330 1.1 augustss ohci_free_std(sc, p);
1331 1.1 augustss }
1332 1.48 augustss
1333 1.16 augustss /* clear halt */
1334 1.168 augustss opipe->sed->ed.ed_headp = HTOO32(p->physaddr);
1335 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1336 1.48 augustss
1337 1.1 augustss if (cc == OHCI_CC_STALL)
1338 1.254.2.7 skrll xfer->ux_status = USBD_STALLED;
1339 1.1 augustss else
1340 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1341 1.53 augustss usb_transfer_complete(xfer);
1342 1.1 augustss }
1343 1.1 augustss }
1344 1.72 augustss
1345 1.83 augustss #ifdef OHCI_DEBUG
1346 1.83 augustss if (ohcidebug > 10) {
1347 1.105 augustss DPRINTF(("ohci_softintr: ITD done:\n"));
1348 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1349 1.254.2.1 skrll ohci_dump_itd(sc, sitd);
1350 1.83 augustss }
1351 1.83 augustss #endif
1352 1.83 augustss
1353 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1354 1.83 augustss xfer = sitd->xfer;
1355 1.83 augustss sitdnext = sitd->dnext;
1356 1.83 augustss DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n",
1357 1.254.2.7 skrll sitd, xfer, xfer ? xfer->ux_hcpriv : 0));
1358 1.83 augustss if (xfer == NULL)
1359 1.83 augustss continue;
1360 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1361 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1362 1.83 augustss DPRINTF(("ohci_process_done: cancel/timeout %p\n",
1363 1.83 augustss xfer));
1364 1.83 augustss /* Handled by abort routine. */
1365 1.83 augustss continue;
1366 1.83 augustss }
1367 1.83 augustss #ifdef DIAGNOSTIC
1368 1.83 augustss if (sitd->isdone)
1369 1.83 augustss printf("ohci_softintr: sitd=%p is done\n", sitd);
1370 1.83 augustss sitd->isdone = 1;
1371 1.83 augustss #endif
1372 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1373 1.134 toshii ohci_soft_itd_t *next;
1374 1.134 toshii
1375 1.254.2.7 skrll opipe = (struct ohci_pipe *)xfer->ux_pipe;
1376 1.254.2.7 skrll opipe->u.iso.inuse -= xfer->ux_nframes;
1377 1.254.2.7 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1378 1.134 toshii bEndpointAddress);
1379 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1380 1.134 toshii actlen = 0;
1381 1.254.2.7 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1382 1.134 toshii sitd = next) {
1383 1.134 toshii next = sitd->nextitd;
1384 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1385 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1386 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1387 1.134 toshii /* For input, update frlengths with actual */
1388 1.134 toshii /* XXX anything necessary for output? */
1389 1.134 toshii if (uedir == UE_DIR_IN &&
1390 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1391 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1392 1.135 toshii sitd->itd.itd_flags));
1393 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1394 1.168 augustss len = O16TOH(sitd->
1395 1.134 toshii itd.itd_offset[j]);
1396 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1397 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1398 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1399 1.158 toshii len = 0;
1400 1.158 toshii else
1401 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1402 1.254.2.7 skrll xfer->ux_frlengths[i] = len;
1403 1.134 toshii actlen += len;
1404 1.134 toshii }
1405 1.134 toshii }
1406 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1407 1.134 toshii break;
1408 1.134 toshii ohci_free_sitd(sc, sitd);
1409 1.83 augustss }
1410 1.134 toshii ohci_free_sitd(sc, sitd);
1411 1.134 toshii if (uedir == UE_DIR_IN &&
1412 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1413 1.254.2.7 skrll xfer->ux_actlen = actlen;
1414 1.254.2.7 skrll xfer->ux_hcpriv = NULL;
1415 1.134 toshii
1416 1.83 augustss usb_transfer_complete(xfer);
1417 1.83 augustss }
1418 1.83 augustss }
1419 1.83 augustss
1420 1.119 augustss if (sc->sc_softwake) {
1421 1.119 augustss sc->sc_softwake = 0;
1422 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1423 1.119 augustss }
1424 1.119 augustss
1425 1.105 augustss DPRINTFN(10,("ohci_softintr: done:\n"));
1426 1.1 augustss }
1427 1.1 augustss
1428 1.1 augustss void
1429 1.179 christos ohci_device_ctrl_done(usbd_xfer_handle xfer)
1430 1.1 augustss {
1431 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
1432 1.224 mrg #ifdef DIAGNOSTIC
1433 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1434 1.224 mrg #endif
1435 1.254.2.7 skrll int len = UGETW(xfer->ux_request.wLength);
1436 1.254.2.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1437 1.195 bouyer
1438 1.140 gson DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer));
1439 1.1 augustss
1440 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1441 1.224 mrg
1442 1.38 augustss #ifdef DIAGNOSTIC
1443 1.254.2.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST)) {
1444 1.140 gson panic("ohci_device_ctrl_done: not a request");
1445 1.1 augustss }
1446 1.38 augustss #endif
1447 1.195 bouyer if (len)
1448 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1449 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1450 1.195 bouyer usb_syncmem(&opipe->u.ctl.reqdma, 0,
1451 1.195 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1452 1.1 augustss }
1453 1.1 augustss
1454 1.1 augustss void
1455 1.91 augustss ohci_device_intr_done(usbd_xfer_handle xfer)
1456 1.1 augustss {
1457 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
1458 1.254.2.7 skrll ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv;
1459 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
1460 1.48 augustss ohci_soft_td_t *data, *tail;
1461 1.195 bouyer int isread =
1462 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1463 1.1 augustss
1464 1.140 gson DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n",
1465 1.254.2.7 skrll xfer, xfer->ux_actlen));
1466 1.1 augustss
1467 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1468 1.224 mrg
1469 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1470 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1471 1.254.2.7 skrll if (xfer->ux_pipe->up_repeat) {
1472 1.60 augustss data = opipe->tail.td;
1473 1.1 augustss tail = ohci_alloc_std(sc); /* XXX should reuse TD */
1474 1.53 augustss if (tail == NULL) {
1475 1.254.2.7 skrll xfer->ux_status = USBD_NOMEM;
1476 1.1 augustss return;
1477 1.1 augustss }
1478 1.55 augustss tail->xfer = NULL;
1479 1.120 augustss
1480 1.168 augustss data->td.td_flags = HTOO32(
1481 1.120 augustss OHCI_TD_IN | OHCI_TD_NOCC |
1482 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
1483 1.254.2.7 skrll if (xfer->ux_flags & USBD_SHORT_XFER_OK)
1484 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
1485 1.254.2.7 skrll data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0));
1486 1.48 augustss data->nexttd = tail;
1487 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
1488 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) +
1489 1.254.2.7 skrll xfer->ux_length - 1);
1490 1.254.2.7 skrll data->len = xfer->ux_length;
1491 1.53 augustss data->xfer = xfer;
1492 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
1493 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
1494 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1495 1.254.2.7 skrll xfer->ux_hcpriv = data;
1496 1.254.2.7 skrll xfer->ux_actlen = 0;
1497 1.1 augustss
1498 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
1499 1.195 bouyer usb_syncmem(&sed->dma,
1500 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_tailp),
1501 1.195 bouyer sizeof(sed->ed.ed_tailp),
1502 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1503 1.60 augustss opipe->tail.td = tail;
1504 1.1 augustss }
1505 1.1 augustss }
1506 1.1 augustss
1507 1.1 augustss void
1508 1.179 christos ohci_device_bulk_done(usbd_xfer_handle xfer)
1509 1.3 augustss {
1510 1.224 mrg #ifdef DIAGNOSTIC
1511 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1512 1.224 mrg #endif
1513 1.195 bouyer int isread =
1514 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1515 1.195 bouyer
1516 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1517 1.224 mrg
1518 1.140 gson DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n",
1519 1.254.2.7 skrll xfer, xfer->ux_actlen));
1520 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1521 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1522 1.3 augustss }
1523 1.3 augustss
1524 1.224 mrg Static void
1525 1.224 mrg ohci_rhsc_softint(void *arg)
1526 1.224 mrg {
1527 1.224 mrg ohci_softc_t *sc = arg;
1528 1.224 mrg
1529 1.224 mrg mutex_enter(&sc->sc_lock);
1530 1.224 mrg
1531 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1532 1.224 mrg
1533 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1534 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1535 1.224 mrg
1536 1.224 mrg mutex_exit(&sc->sc_lock);
1537 1.224 mrg }
1538 1.224 mrg
1539 1.3 augustss void
1540 1.91 augustss ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer)
1541 1.1 augustss {
1542 1.1 augustss u_char *p;
1543 1.1 augustss int i, m;
1544 1.243 martin int hstatus __unused;
1545 1.1 augustss
1546 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1547 1.224 mrg
1548 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1549 1.120 augustss DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n",
1550 1.53 augustss sc, xfer, hstatus));
1551 1.1 augustss
1552 1.53 augustss if (xfer == NULL) {
1553 1.1 augustss /* Just ignore the change. */
1554 1.1 augustss return;
1555 1.1 augustss }
1556 1.1 augustss
1557 1.254.2.7 skrll p = xfer->ux_buf;
1558 1.254.2.7 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1559 1.254.2.7 skrll memset(p, 0, xfer->ux_length);
1560 1.1 augustss for (i = 1; i <= m; i++) {
1561 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1562 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1563 1.1 augustss p[i/8] |= 1 << (i%8);
1564 1.1 augustss }
1565 1.1 augustss DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
1566 1.254.2.7 skrll xfer->ux_actlen = xfer->ux_length;
1567 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1568 1.1 augustss
1569 1.53 augustss usb_transfer_complete(xfer);
1570 1.38 augustss }
1571 1.38 augustss
1572 1.38 augustss void
1573 1.179 christos ohci_root_intr_done(usbd_xfer_handle xfer)
1574 1.65 augustss {
1575 1.65 augustss }
1576 1.65 augustss
1577 1.1 augustss /*
1578 1.1 augustss * Wait here until controller claims to have an interrupt.
1579 1.1 augustss * Then call ohci_intr and return. Use timeout to avoid waiting
1580 1.1 augustss * too long.
1581 1.1 augustss */
1582 1.1 augustss void
1583 1.91 augustss ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer)
1584 1.1 augustss {
1585 1.163 augustss int timo;
1586 1.254.2.1 skrll uint32_t intrs;
1587 1.1 augustss
1588 1.224 mrg mutex_enter(&sc->sc_lock);
1589 1.224 mrg
1590 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1591 1.254.2.7 skrll for (timo = xfer->ux_timeout; timo >= 0; timo--) {
1592 1.20 augustss usb_delay_ms(&sc->sc_bus, 1);
1593 1.116 augustss if (sc->sc_dying)
1594 1.116 augustss break;
1595 1.1 augustss intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
1596 1.27 augustss DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs));
1597 1.52 augustss #ifdef OHCI_DEBUG
1598 1.1 augustss if (ohcidebug > 15)
1599 1.1 augustss ohci_dumpregs(sc);
1600 1.1 augustss #endif
1601 1.1 augustss if (intrs) {
1602 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1603 1.53 augustss ohci_intr1(sc);
1604 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1605 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1606 1.230 jmcneill goto done;
1607 1.1 augustss }
1608 1.1 augustss }
1609 1.15 augustss
1610 1.15 augustss /* Timeout */
1611 1.1 augustss DPRINTF(("ohci_waitintr: timeout\n"));
1612 1.254.2.7 skrll xfer->ux_status = USBD_TIMEOUT;
1613 1.53 augustss usb_transfer_complete(xfer);
1614 1.224 mrg
1615 1.15 augustss /* XXX should free TD */
1616 1.224 mrg
1617 1.230 jmcneill done:
1618 1.224 mrg mutex_exit(&sc->sc_lock);
1619 1.5 augustss }
1620 1.5 augustss
1621 1.5 augustss void
1622 1.91 augustss ohci_poll(struct usbd_bus *bus)
1623 1.5 augustss {
1624 1.254.2.7 skrll ohci_softc_t *sc = bus->ub_hcpriv;
1625 1.105 augustss #ifdef OHCI_DEBUG
1626 1.105 augustss static int last;
1627 1.105 augustss int new;
1628 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1629 1.105 augustss if (new != last) {
1630 1.105 augustss DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new));
1631 1.105 augustss last = new;
1632 1.105 augustss }
1633 1.105 augustss #endif
1634 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1635 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1636 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1637 1.53 augustss ohci_intr1(sc);
1638 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1639 1.224 mrg }
1640 1.1 augustss }
1641 1.1 augustss
1642 1.1 augustss usbd_status
1643 1.91 augustss ohci_device_request(usbd_xfer_handle xfer)
1644 1.1 augustss {
1645 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
1646 1.254.2.7 skrll usb_device_request_t *req = &xfer->ux_request;
1647 1.254.2.7 skrll usbd_device_handle dev = opipe->pipe.up_dev;
1648 1.254.2.7 skrll ohci_softc_t *sc = dev->ud_bus->ub_hcpriv;
1649 1.77 augustss ohci_soft_td_t *setup, *stat, *next, *tail;
1650 1.1 augustss ohci_soft_ed_t *sed;
1651 1.1 augustss int isread;
1652 1.1 augustss int len;
1653 1.53 augustss usbd_status err;
1654 1.224 mrg
1655 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1656 1.1 augustss
1657 1.1 augustss isread = req->bmRequestType & UT_READ;
1658 1.1 augustss len = UGETW(req->wLength);
1659 1.1 augustss
1660 1.14 augustss DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, "
1661 1.14 augustss "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
1662 1.1 augustss req->bmRequestType, req->bRequest, UGETW(req->wValue),
1663 1.254.2.7 skrll UGETW(req->wIndex), len, dev->ud_addr,
1664 1.254.2.7 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress));
1665 1.1 augustss
1666 1.60 augustss setup = opipe->tail.td;
1667 1.1 augustss stat = ohci_alloc_std(sc);
1668 1.53 augustss if (stat == NULL) {
1669 1.53 augustss err = USBD_NOMEM;
1670 1.1 augustss goto bad1;
1671 1.1 augustss }
1672 1.1 augustss tail = ohci_alloc_std(sc);
1673 1.53 augustss if (tail == NULL) {
1674 1.53 augustss err = USBD_NOMEM;
1675 1.1 augustss goto bad2;
1676 1.1 augustss }
1677 1.55 augustss tail->xfer = NULL;
1678 1.1 augustss
1679 1.1 augustss sed = opipe->sed;
1680 1.1 augustss opipe->u.ctl.length = len;
1681 1.1 augustss
1682 1.254.2.7 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
1683 1.250 skrll "address ED %d pipe %d\n",
1684 1.254.2.7 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
1685 1.254.2.2 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
1686 1.254.2.7 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
1687 1.250 skrll "MPL ED %d pipe %d\n",
1688 1.250 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
1689 1.254.2.7 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
1690 1.1 augustss
1691 1.77 augustss next = stat;
1692 1.77 augustss
1693 1.1 augustss /* Set up data transaction */
1694 1.1 augustss if (len != 0) {
1695 1.77 augustss ohci_soft_td_t *std = stat;
1696 1.77 augustss
1697 1.77 augustss err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
1698 1.77 augustss std, &stat);
1699 1.236 skrll if (err) {
1700 1.236 skrll /* stat is unchanged if error */
1701 1.236 skrll goto bad3;
1702 1.236 skrll }
1703 1.77 augustss stat = stat->nexttd; /* point at free TD */
1704 1.236 skrll
1705 1.77 augustss /* Start toggle at 1 and then use the carried toggle. */
1706 1.168 augustss std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
1707 1.168 augustss std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
1708 1.195 bouyer usb_syncmem(&std->dma,
1709 1.195 bouyer std->offs + offsetof(ohci_td_t, td_flags),
1710 1.195 bouyer sizeof(std->td.td_flags),
1711 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1712 1.34 augustss }
1713 1.1 augustss
1714 1.254.2.16 skrll memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof(*req));
1715 1.254.2.16 skrll usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
1716 1.1 augustss
1717 1.168 augustss setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
1718 1.76 tsutsui OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1719 1.168 augustss setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0));
1720 1.1 augustss setup->nexttd = next;
1721 1.168 augustss setup->td.td_nexttd = HTOO32(next->physaddr);
1722 1.254.2.16 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
1723 1.77 augustss setup->len = 0;
1724 1.53 augustss setup->xfer = xfer;
1725 1.34 augustss setup->flags = 0;
1726 1.254.2.7 skrll xfer->ux_hcpriv = setup;
1727 1.195 bouyer usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
1728 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1729 1.1 augustss
1730 1.168 augustss stat->td.td_flags = HTOO32(
1731 1.77 augustss (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
1732 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1733 1.39 augustss stat->td.td_cbp = 0;
1734 1.1 augustss stat->nexttd = tail;
1735 1.168 augustss stat->td.td_nexttd = HTOO32(tail->physaddr);
1736 1.39 augustss stat->td.td_be = 0;
1737 1.77 augustss stat->flags = OHCI_CALL_DONE;
1738 1.1 augustss stat->len = 0;
1739 1.53 augustss stat->xfer = xfer;
1740 1.195 bouyer usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
1741 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1742 1.1 augustss
1743 1.52 augustss #ifdef OHCI_DEBUG
1744 1.1 augustss if (ohcidebug > 5) {
1745 1.41 augustss DPRINTF(("ohci_device_request:\n"));
1746 1.168 augustss ohci_dump_ed(sc, sed);
1747 1.168 augustss ohci_dump_tds(sc, setup);
1748 1.1 augustss }
1749 1.1 augustss #endif
1750 1.1 augustss
1751 1.1 augustss /* Insert ED in schedule */
1752 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
1753 1.195 bouyer usb_syncmem(&sed->dma,
1754 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_tailp),
1755 1.195 bouyer sizeof(sed->ed.ed_tailp),
1756 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1757 1.60 augustss opipe->tail.td = tail;
1758 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1759 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
1760 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
1761 1.80 augustss ohci_timeout, xfer);
1762 1.15 augustss }
1763 1.1 augustss
1764 1.115 itojun #ifdef OHCI_DEBUG
1765 1.113 augustss if (ohcidebug > 20) {
1766 1.77 augustss delay(10000);
1767 1.41 augustss DPRINTF(("ohci_device_request: status=%x\n",
1768 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
1769 1.113 augustss ohci_dumpregs(sc);
1770 1.113 augustss printf("ctrl head:\n");
1771 1.168 augustss ohci_dump_ed(sc, sc->sc_ctrl_head);
1772 1.113 augustss printf("sed:\n");
1773 1.168 augustss ohci_dump_ed(sc, sed);
1774 1.168 augustss ohci_dump_tds(sc, setup);
1775 1.1 augustss }
1776 1.1 augustss #endif
1777 1.1 augustss
1778 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
1779 1.1 augustss
1780 1.1 augustss bad3:
1781 1.1 augustss ohci_free_std(sc, tail);
1782 1.1 augustss bad2:
1783 1.1 augustss ohci_free_std(sc, stat);
1784 1.1 augustss bad1:
1785 1.254.2.13 skrll return err;
1786 1.1 augustss }
1787 1.1 augustss
1788 1.1 augustss /*
1789 1.224 mrg * Add an ED to the schedule. Called with USB lock held.
1790 1.1 augustss */
1791 1.224 mrg Static void
1792 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1793 1.1 augustss {
1794 1.113 augustss DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head));
1795 1.113 augustss
1796 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1797 1.224 mrg
1798 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1799 1.195 bouyer sizeof(head->ed.ed_nexted),
1800 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1801 1.1 augustss sed->next = head->next;
1802 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1803 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1804 1.195 bouyer sizeof(sed->ed.ed_nexted),
1805 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1806 1.1 augustss head->next = sed;
1807 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1808 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1809 1.195 bouyer sizeof(head->ed.ed_nexted),
1810 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1811 1.1 augustss }
1812 1.1 augustss
1813 1.1 augustss /*
1814 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1815 1.3 augustss */
1816 1.224 mrg Static void
1817 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1818 1.3 augustss {
1819 1.120 augustss ohci_soft_ed_t *p;
1820 1.3 augustss
1821 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1822 1.224 mrg
1823 1.3 augustss /* XXX */
1824 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1825 1.3 augustss ;
1826 1.55 augustss if (p == NULL)
1827 1.128 provos panic("ohci_rem_ed: ED not found");
1828 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1829 1.195 bouyer sizeof(sed->ed.ed_nexted),
1830 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1831 1.3 augustss p->next = sed->next;
1832 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1833 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1834 1.195 bouyer sizeof(p->ed.ed_nexted),
1835 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1836 1.3 augustss }
1837 1.3 augustss
1838 1.3 augustss /*
1839 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1840 1.1 augustss * the host controller. This queue is the processed by software.
1841 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1842 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1843 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1844 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1845 1.1 augustss * hash value.
1846 1.1 augustss */
1847 1.1 augustss
1848 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1849 1.224 mrg /* Called with USB lock held. */
1850 1.1 augustss void
1851 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1852 1.1 augustss {
1853 1.1 augustss int h = HASH(std->physaddr);
1854 1.1 augustss
1855 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1856 1.224 mrg
1857 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1858 1.1 augustss }
1859 1.1 augustss
1860 1.224 mrg /* Called with USB lock held. */
1861 1.1 augustss void
1862 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1863 1.1 augustss {
1864 1.46 augustss
1865 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1866 1.224 mrg
1867 1.1 augustss LIST_REMOVE(std, hnext);
1868 1.1 augustss }
1869 1.1 augustss
1870 1.1 augustss ohci_soft_td_t *
1871 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1872 1.1 augustss {
1873 1.1 augustss int h = HASH(a);
1874 1.1 augustss ohci_soft_td_t *std;
1875 1.1 augustss
1876 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1877 1.53 augustss std != NULL;
1878 1.1 augustss std = LIST_NEXT(std, hnext))
1879 1.1 augustss if (std->physaddr == a)
1880 1.254.2.13 skrll return std;
1881 1.254.2.13 skrll return NULL;
1882 1.83 augustss }
1883 1.83 augustss
1884 1.224 mrg /* Called with USB lock held. */
1885 1.83 augustss void
1886 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1887 1.83 augustss {
1888 1.83 augustss int h = HASH(sitd->physaddr);
1889 1.83 augustss
1890 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1891 1.224 mrg
1892 1.120 augustss DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n",
1893 1.83 augustss sitd, (u_long)sitd->physaddr));
1894 1.83 augustss
1895 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1896 1.83 augustss }
1897 1.83 augustss
1898 1.224 mrg /* Called with USB lock held. */
1899 1.83 augustss void
1900 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1901 1.83 augustss {
1902 1.83 augustss
1903 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1904 1.224 mrg
1905 1.120 augustss DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n",
1906 1.83 augustss sitd, (u_long)sitd->physaddr));
1907 1.83 augustss
1908 1.83 augustss LIST_REMOVE(sitd, hnext);
1909 1.83 augustss }
1910 1.83 augustss
1911 1.83 augustss ohci_soft_itd_t *
1912 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1913 1.83 augustss {
1914 1.83 augustss int h = HASH(a);
1915 1.83 augustss ohci_soft_itd_t *sitd;
1916 1.83 augustss
1917 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1918 1.83 augustss sitd != NULL;
1919 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1920 1.83 augustss if (sitd->physaddr == a)
1921 1.254.2.13 skrll return sitd;
1922 1.254.2.13 skrll return NULL;
1923 1.1 augustss }
1924 1.1 augustss
1925 1.1 augustss void
1926 1.91 augustss ohci_timeout(void *addr)
1927 1.1 augustss {
1928 1.114 augustss struct ohci_xfer *oxfer = addr;
1929 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.ux_pipe;
1930 1.254.2.7 skrll ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv;
1931 1.114 augustss
1932 1.114 augustss DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer));
1933 1.114 augustss
1934 1.116 augustss if (sc->sc_dying) {
1935 1.224 mrg mutex_enter(&sc->sc_lock);
1936 1.116 augustss ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT);
1937 1.224 mrg mutex_exit(&sc->sc_lock);
1938 1.116 augustss return;
1939 1.116 augustss }
1940 1.116 augustss
1941 1.114 augustss /* Execute the abort in a process context. */
1942 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1943 1.231 jmcneill USB_TASKQ_MPSAFE);
1944 1.254.2.7 skrll usb_add_task(oxfer->xfer.ux_pipe->up_dev, &oxfer->abort_task,
1945 1.178 joerg USB_TASKQ_HC);
1946 1.114 augustss }
1947 1.114 augustss
1948 1.114 augustss void
1949 1.114 augustss ohci_timeout_task(void *addr)
1950 1.114 augustss {
1951 1.53 augustss usbd_xfer_handle xfer = addr;
1952 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
1953 1.1 augustss
1954 1.114 augustss DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer));
1955 1.45 augustss
1956 1.224 mrg mutex_enter(&sc->sc_lock);
1957 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1958 1.224 mrg mutex_exit(&sc->sc_lock);
1959 1.1 augustss }
1960 1.1 augustss
1961 1.52 augustss #ifdef OHCI_DEBUG
1962 1.1 augustss void
1963 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1964 1.1 augustss {
1965 1.1 augustss for (; std; std = std->nexttd)
1966 1.168 augustss ohci_dump_td(sc, std);
1967 1.1 augustss }
1968 1.1 augustss
1969 1.1 augustss void
1970 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1971 1.1 augustss {
1972 1.92 tv char sbuf[128];
1973 1.92 tv
1974 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1975 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1976 1.197 christos snprintb(sbuf, sizeof(sbuf),
1977 1.237 skrll "\177\20"
1978 1.237 skrll "b\22R\0"
1979 1.237 skrll "f\23\02DP\0"
1980 1.237 skrll "=\x0" "setup\0"
1981 1.237 skrll "=\x1" "out\0"
1982 1.237 skrll "=\x2" "in\0"
1983 1.237 skrll "=\x3" "reserved\0"
1984 1.237 skrll "f\25\03DI\0"
1985 1.237 skrll "=\x07" "none\0"
1986 1.237 skrll "f\30\02T\0"
1987 1.237 skrll "=\x0" "carry\0"
1988 1.237 skrll "=\x1" "carry\0"
1989 1.237 skrll "=\x2" "0\0"
1990 1.237 skrll "=\x3" "1\0"
1991 1.237 skrll "f\32\02EC\0"
1992 1.237 skrll "f\34\04CC\0",
1993 1.254.2.1 skrll (uint32_t)O32TOH(std->td.td_flags));
1994 1.238 skrll printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n",
1995 1.107 augustss std, (u_long)std->physaddr, sbuf,
1996 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1997 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1998 1.168 augustss (u_long)O32TOH(std->td.td_be));
1999 1.1 augustss }
2000 1.1 augustss
2001 1.1 augustss void
2002 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2003 1.83 augustss {
2004 1.83 augustss int i;
2005 1.83 augustss
2006 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
2007 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2008 1.107 augustss printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n"
2009 1.120 augustss "bp0=0x%08lx next=0x%08lx be=0x%08lx\n",
2010 1.107 augustss sitd, (u_long)sitd->physaddr,
2011 1.168 augustss OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)),
2012 1.168 augustss OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)),
2013 1.168 augustss OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)),
2014 1.168 augustss OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)),
2015 1.168 augustss (u_long)O32TOH(sitd->itd.itd_bp0),
2016 1.168 augustss (u_long)O32TOH(sitd->itd.itd_nextitd),
2017 1.168 augustss (u_long)O32TOH(sitd->itd.itd_be));
2018 1.83 augustss for (i = 0; i < OHCI_ITD_NOFFSET; i++)
2019 1.107 augustss printf("offs[%d]=0x%04x ", i,
2020 1.168 augustss (u_int)O16TOH(sitd->itd.itd_offset[i]));
2021 1.107 augustss printf("\n");
2022 1.83 augustss }
2023 1.83 augustss
2024 1.83 augustss void
2025 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2026 1.83 augustss {
2027 1.83 augustss for (; sitd; sitd = sitd->nextitd)
2028 1.168 augustss ohci_dump_itd(sc, sitd);
2029 1.83 augustss }
2030 1.83 augustss
2031 1.83 augustss void
2032 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2033 1.1 augustss {
2034 1.92 tv char sbuf[128], sbuf2[128];
2035 1.92 tv
2036 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2037 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2038 1.197 christos snprintb(sbuf, sizeof(sbuf),
2039 1.197 christos "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO",
2040 1.254.2.1 skrll (uint32_t)O32TOH(sed->ed.ed_flags));
2041 1.197 christos snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY",
2042 1.254.2.1 skrll (uint32_t)O32TOH(sed->ed.ed_headp));
2043 1.92 tv
2044 1.107 augustss printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx "
2045 1.92 tv "headflags=%s headp=0x%08lx nexted=0x%08lx\n",
2046 1.120 augustss sed, (u_long)sed->physaddr,
2047 1.168 augustss OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)),
2048 1.168 augustss OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)),
2049 1.168 augustss OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf,
2050 1.168 augustss (u_long)O32TOH(sed->ed.ed_tailp), sbuf2,
2051 1.168 augustss (u_long)O32TOH(sed->ed.ed_headp),
2052 1.168 augustss (u_long)O32TOH(sed->ed.ed_nexted));
2053 1.1 augustss }
2054 1.1 augustss #endif
2055 1.1 augustss
2056 1.1 augustss usbd_status
2057 1.91 augustss ohci_open(usbd_pipe_handle pipe)
2058 1.1 augustss {
2059 1.254.2.7 skrll usbd_device_handle dev = pipe->up_dev;
2060 1.254.2.12 skrll struct usbd_bus *bus = dev->ud_bus;
2061 1.254.2.7 skrll ohci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2062 1.254.2.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2063 1.1 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2064 1.254.2.7 skrll uint8_t addr = dev->ud_addr;
2065 1.254.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2066 1.1 augustss ohci_soft_ed_t *sed;
2067 1.1 augustss ohci_soft_td_t *std;
2068 1.60 augustss ohci_soft_itd_t *sitd;
2069 1.60 augustss ohci_physaddr_t tdphys;
2070 1.254.2.1 skrll uint32_t fmt;
2071 1.224 mrg usbd_status err = USBD_NOMEM;
2072 1.64 augustss int ival;
2073 1.1 augustss
2074 1.1 augustss DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
2075 1.254.2.12 skrll pipe, addr, ed->bEndpointAddress, bus->ub_rhaddr));
2076 1.81 augustss
2077 1.224 mrg if (sc->sc_dying) {
2078 1.241 skrll return USBD_IOERROR;
2079 1.224 mrg }
2080 1.116 augustss
2081 1.90 thorpej std = NULL;
2082 1.90 thorpej sed = NULL;
2083 1.90 thorpej
2084 1.254.2.12 skrll if (addr == bus->ub_rhaddr) {
2085 1.1 augustss switch (ed->bEndpointAddress) {
2086 1.1 augustss case USB_CONTROL_ENDPOINT:
2087 1.254.2.12 skrll pipe->up_methods = &roothub_ctrl_methods;
2088 1.1 augustss break;
2089 1.254.2.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2090 1.254.2.7 skrll pipe->up_methods = &ohci_root_intr_methods;
2091 1.1 augustss break;
2092 1.1 augustss default:
2093 1.224 mrg err = USBD_INVAL;
2094 1.241 skrll goto bad;
2095 1.1 augustss }
2096 1.1 augustss } else {
2097 1.1 augustss sed = ohci_alloc_sed(sc);
2098 1.53 augustss if (sed == NULL)
2099 1.241 skrll goto bad;
2100 1.1 augustss opipe->sed = sed;
2101 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2102 1.224 mrg mutex_enter(&sc->sc_lock);
2103 1.60 augustss sitd = ohci_alloc_sitd(sc);
2104 1.224 mrg mutex_exit(&sc->sc_lock);
2105 1.127 augustss if (sitd == NULL)
2106 1.241 skrll goto bad;
2107 1.241 skrll
2108 1.60 augustss opipe->tail.itd = sitd;
2109 1.76 tsutsui tdphys = sitd->physaddr;
2110 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2111 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2112 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2113 1.83 augustss else
2114 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2115 1.60 augustss } else {
2116 1.224 mrg mutex_enter(&sc->sc_lock);
2117 1.60 augustss std = ohci_alloc_std(sc);
2118 1.224 mrg mutex_exit(&sc->sc_lock);
2119 1.127 augustss if (std == NULL)
2120 1.241 skrll goto bad;
2121 1.241 skrll
2122 1.60 augustss opipe->tail.td = std;
2123 1.76 tsutsui tdphys = std->physaddr;
2124 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2125 1.60 augustss }
2126 1.168 augustss sed->ed.ed_flags = HTOO32(
2127 1.120 augustss OHCI_ED_SET_FA(addr) |
2128 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2129 1.254.2.7 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2130 1.109 augustss fmt |
2131 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2132 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2133 1.254.2.7 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2134 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2135 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2136 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2137 1.1 augustss
2138 1.60 augustss switch (xfertype) {
2139 1.1 augustss case UE_CONTROL:
2140 1.254.2.7 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2141 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2142 1.120 augustss sizeof(usb_device_request_t),
2143 1.53 augustss 0, &opipe->u.ctl.reqdma);
2144 1.53 augustss if (err)
2145 1.1 augustss goto bad;
2146 1.224 mrg mutex_enter(&sc->sc_lock);
2147 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2148 1.224 mrg mutex_exit(&sc->sc_lock);
2149 1.1 augustss break;
2150 1.1 augustss case UE_INTERRUPT:
2151 1.254.2.7 skrll pipe->up_methods = &ohci_device_intr_methods;
2152 1.254.2.7 skrll ival = pipe->up_interval;
2153 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2154 1.64 augustss ival = ed->bInterval;
2155 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2156 1.226 skrll if (err)
2157 1.226 skrll goto bad;
2158 1.226 skrll break;
2159 1.1 augustss case UE_ISOCHRONOUS:
2160 1.254.2.7 skrll pipe->up_methods = &ohci_device_isoc_methods;
2161 1.254.2.13 skrll return ohci_setup_isoc(pipe);
2162 1.1 augustss case UE_BULK:
2163 1.254.2.7 skrll pipe->up_methods = &ohci_device_bulk_methods;
2164 1.224 mrg mutex_enter(&sc->sc_lock);
2165 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2166 1.224 mrg mutex_exit(&sc->sc_lock);
2167 1.3 augustss break;
2168 1.1 augustss }
2169 1.1 augustss }
2170 1.224 mrg
2171 1.224 mrg return USBD_NORMAL_COMPLETION;
2172 1.1 augustss
2173 1.1 augustss bad:
2174 1.241 skrll if (std != NULL) {
2175 1.241 skrll mutex_enter(&sc->sc_lock);
2176 1.90 thorpej ohci_free_std(sc, std);
2177 1.241 skrll mutex_exit(&sc->sc_lock);
2178 1.241 skrll }
2179 1.90 thorpej if (sed != NULL)
2180 1.90 thorpej ohci_free_sed(sc, sed);
2181 1.224 mrg return err;
2182 1.120 augustss
2183 1.1 augustss }
2184 1.1 augustss
2185 1.1 augustss /*
2186 1.34 augustss * Close a reqular pipe.
2187 1.34 augustss * Assumes that there are no pending transactions.
2188 1.34 augustss */
2189 1.34 augustss void
2190 1.91 augustss ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head)
2191 1.34 augustss {
2192 1.34 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2193 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2194 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2195 1.34 augustss
2196 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2197 1.224 mrg
2198 1.34 augustss #ifdef DIAGNOSTIC
2199 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2200 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2201 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2202 1.34 augustss ohci_soft_td_t *std;
2203 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2204 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2205 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2206 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2207 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2208 1.34 augustss pipe, std);
2209 1.229 christos #ifdef OHCI_DEBUG
2210 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2211 1.168 augustss ohci_dump_ed(sc, sed);
2212 1.106 augustss if (std)
2213 1.168 augustss ohci_dump_td(sc, std);
2214 1.106 augustss #endif
2215 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2216 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2217 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2218 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2219 1.34 augustss }
2220 1.34 augustss #endif
2221 1.224 mrg ohci_rem_ed(sc, sed, head);
2222 1.133 toshii /* Make sure the host controller is not touching this ED */
2223 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2224 1.254.2.7 skrll pipe->up_endpoint->ue_toggle =
2225 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2226 1.34 augustss ohci_free_sed(sc, opipe->sed);
2227 1.34 augustss }
2228 1.34 augustss
2229 1.120 augustss /*
2230 1.34 augustss * Abort a device request.
2231 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2232 1.34 augustss * will be removed from the hardware scheduling and that the callback
2233 1.34 augustss * for it will be called with USBD_CANCELLED status.
2234 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2235 1.34 augustss * have happened since the hardware runs concurrently.
2236 1.34 augustss * If the transaction has already happened we rely on the ordinary
2237 1.34 augustss * interrupt processing to process it.
2238 1.224 mrg * XXX This is most probably wrong.
2239 1.224 mrg * XXXMRG this doesn't make sense anymore.
2240 1.34 augustss */
2241 1.34 augustss void
2242 1.91 augustss ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2243 1.34 augustss {
2244 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
2245 1.254.2.7 skrll ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv;
2246 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2247 1.106 augustss ohci_soft_td_t *p, *n;
2248 1.106 augustss ohci_physaddr_t headp;
2249 1.224 mrg int hit;
2250 1.159 augustss int wake;
2251 1.34 augustss
2252 1.106 augustss DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed));
2253 1.34 augustss
2254 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2255 1.254.2.3 skrll ASSERT_SLEEPABLE();
2256 1.224 mrg
2257 1.116 augustss if (sc->sc_dying) {
2258 1.116 augustss /* If we're dying, just do the software part. */
2259 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2260 1.254.2.7 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2261 1.116 augustss usb_transfer_complete(xfer);
2262 1.170 christos return;
2263 1.116 augustss }
2264 1.116 augustss
2265 1.106 augustss /*
2266 1.159 augustss * If an abort is already in progress then just wait for it to
2267 1.159 augustss * complete and return.
2268 1.159 augustss */
2269 1.254.2.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2270 1.159 augustss DPRINTFN(2, ("ohci_abort_xfer: already aborting\n"));
2271 1.159 augustss #ifdef DIAGNOSTIC
2272 1.159 augustss if (status == USBD_TIMEOUT)
2273 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2274 1.159 augustss #endif
2275 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2276 1.254.2.7 skrll xfer->ux_status = status;
2277 1.159 augustss DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n"));
2278 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2279 1.254.2.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2280 1.254.2.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2281 1.224 mrg goto done;
2282 1.159 augustss }
2283 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2284 1.159 augustss
2285 1.159 augustss /*
2286 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2287 1.106 augustss */
2288 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2289 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
2290 1.54 augustss DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed));
2291 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2292 1.195 bouyer sizeof(sed->ed.ed_flags),
2293 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2294 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2295 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2296 1.195 bouyer sizeof(sed->ed.ed_flags),
2297 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2298 1.34 augustss
2299 1.120 augustss /*
2300 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2301 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2302 1.106 augustss * has run.
2303 1.106 augustss */
2304 1.224 mrg /* Hardware finishes in 1ms */
2305 1.254.2.7 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2306 1.119 augustss sc->sc_softwake = 1;
2307 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2308 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2309 1.119 augustss
2310 1.120 augustss /*
2311 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2312 1.106 augustss * The complication here is that the hardware may have executed
2313 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2314 1.106 augustss * the TDs of this xfer we check if the hardware points to
2315 1.106 augustss * any of them.
2316 1.106 augustss */
2317 1.254.2.7 skrll p = xfer->ux_hcpriv;
2318 1.34 augustss #ifdef DIAGNOSTIC
2319 1.55 augustss if (p == NULL) {
2320 1.254.2.7 skrll xfer->ux_hcflags &= ~UXFER_ABORTING; /* XXX */
2321 1.106 augustss printf("ohci_abort_xfer: hcpriv is NULL\n");
2322 1.224 mrg goto done;
2323 1.38 augustss }
2324 1.34 augustss #endif
2325 1.106 augustss #ifdef OHCI_DEBUG
2326 1.106 augustss if (ohcidebug > 1) {
2327 1.106 augustss DPRINTF(("ohci_abort_xfer: sed=\n"));
2328 1.168 augustss ohci_dump_ed(sc, sed);
2329 1.168 augustss ohci_dump_tds(sc, p);
2330 1.106 augustss }
2331 1.106 augustss #endif
2332 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2333 1.106 augustss hit = 0;
2334 1.53 augustss for (; p->xfer == xfer; p = n) {
2335 1.106 augustss hit |= headp == p->physaddr;
2336 1.38 augustss n = p->nexttd;
2337 1.38 augustss ohci_free_std(sc, p);
2338 1.34 augustss }
2339 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2340 1.106 augustss if (hit) {
2341 1.150 mycroft DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n",
2342 1.168 augustss (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp)));
2343 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2344 1.195 bouyer usb_syncmem(&sed->dma,
2345 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2346 1.195 bouyer sizeof(sed->ed.ed_headp),
2347 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2348 1.106 augustss } else {
2349 1.106 augustss DPRINTFN(1,("ohci_abort_xfer: no hit\n"));
2350 1.106 augustss }
2351 1.34 augustss
2352 1.106 augustss /*
2353 1.106 augustss * Step 4: Turn on hardware again.
2354 1.106 augustss */
2355 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2356 1.195 bouyer sizeof(sed->ed.ed_flags),
2357 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2358 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2359 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2360 1.195 bouyer sizeof(sed->ed.ed_flags),
2361 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2362 1.38 augustss
2363 1.106 augustss /*
2364 1.106 augustss * Step 5: Execute callback.
2365 1.106 augustss */
2366 1.254.2.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2367 1.254.2.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2368 1.53 augustss usb_transfer_complete(xfer);
2369 1.159 augustss if (wake)
2370 1.254.2.7 skrll cv_broadcast(&xfer->ux_hccv);
2371 1.38 augustss
2372 1.224 mrg done:
2373 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2374 1.34 augustss }
2375 1.34 augustss
2376 1.34 augustss /*
2377 1.1 augustss * Data structures and routines to emulate the root hub.
2378 1.1 augustss */
2379 1.254.2.12 skrll Static int
2380 1.254.2.12 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2381 1.254.2.12 skrll void *buf, int buflen)
2382 1.17 augustss {
2383 1.254.2.12 skrll ohci_softc_t *sc = bus->ub_hcpriv;
2384 1.1 augustss usb_port_status_t ps;
2385 1.254.2.12 skrll uint16_t len, value, index;
2386 1.254.2.12 skrll int l, totlen = 0;
2387 1.254.2.12 skrll int port, i;
2388 1.254.2.1 skrll uint32_t v;
2389 1.1 augustss
2390 1.83 augustss if (sc->sc_dying)
2391 1.254.2.12 skrll return -1;
2392 1.1 augustss
2393 1.254.2.12 skrll DPRINTFN(4,("%s: type=0x%02x request=%02x\n", __func__,
2394 1.254.2.12 skrll req->bmRequestType, req->bRequest));
2395 1.1 augustss
2396 1.1 augustss len = UGETW(req->wLength);
2397 1.1 augustss value = UGETW(req->wValue);
2398 1.1 augustss index = UGETW(req->wIndex);
2399 1.43 augustss
2400 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2401 1.254.2.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
2402 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2403 1.254.2.12 skrll DPRINTFN(8,("%s: wValue=0x%04x\n", __func__, value));
2404 1.171 christos if (len == 0)
2405 1.171 christos break;
2406 1.254.2.12 skrll switch (value) {
2407 1.254.2.12 skrll case C(0, UDESC_DEVICE): {
2408 1.254.2.12 skrll usb_device_descriptor_t devd;
2409 1.254.2.12 skrll
2410 1.254.2.12 skrll totlen = min(buflen, sizeof(devd));
2411 1.254.2.12 skrll memcpy(&devd, buf, totlen);
2412 1.254.2.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2413 1.254.2.12 skrll memcpy(buf, &devd, totlen);
2414 1.1 augustss break;
2415 1.254.2.12 skrll }
2416 1.254.2.12 skrll case C(1, UDESC_STRING):
2417 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2418 1.254.2.12 skrll /* Vendor */
2419 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2420 1.254.2.12 skrll break;
2421 1.254.2.12 skrll case C(2, UDESC_STRING):
2422 1.254.2.12 skrll /* Product */
2423 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2424 1.1 augustss break;
2425 1.254.2.12 skrll #undef sd
2426 1.1 augustss default:
2427 1.254.2.12 skrll /* default from usbroothub */
2428 1.254.2.12 skrll return buflen;
2429 1.1 augustss }
2430 1.1 augustss break;
2431 1.254.2.12 skrll
2432 1.1 augustss /* Hub requests */
2433 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2434 1.1 augustss break;
2435 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2436 1.254.2.12 skrll DPRINTFN(8, ("%s: UR_CLEAR_PORT_FEATURE "
2437 1.254.2.12 skrll "port=%d feature=%d\n", __func__,
2438 1.1 augustss index, value));
2439 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2440 1.254.2.12 skrll return -1;
2441 1.1 augustss }
2442 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2443 1.1 augustss switch(value) {
2444 1.1 augustss case UHF_PORT_ENABLE:
2445 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2446 1.1 augustss break;
2447 1.1 augustss case UHF_PORT_SUSPEND:
2448 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2449 1.1 augustss break;
2450 1.1 augustss case UHF_PORT_POWER:
2451 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2452 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2453 1.1 augustss break;
2454 1.1 augustss case UHF_C_PORT_CONNECTION:
2455 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2456 1.1 augustss break;
2457 1.1 augustss case UHF_C_PORT_ENABLE:
2458 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2459 1.1 augustss break;
2460 1.1 augustss case UHF_C_PORT_SUSPEND:
2461 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2462 1.1 augustss break;
2463 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2464 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2465 1.1 augustss break;
2466 1.1 augustss case UHF_C_PORT_RESET:
2467 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2468 1.1 augustss break;
2469 1.1 augustss default:
2470 1.254.2.12 skrll return -1;
2471 1.1 augustss }
2472 1.1 augustss switch(value) {
2473 1.1 augustss case UHF_C_PORT_CONNECTION:
2474 1.1 augustss case UHF_C_PORT_ENABLE:
2475 1.1 augustss case UHF_C_PORT_SUSPEND:
2476 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2477 1.1 augustss case UHF_C_PORT_RESET:
2478 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2479 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2480 1.157 mycroft ohci_rhsc_enable(sc);
2481 1.1 augustss break;
2482 1.1 augustss default:
2483 1.1 augustss break;
2484 1.1 augustss }
2485 1.1 augustss break;
2486 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2487 1.171 christos if (len == 0)
2488 1.171 christos break;
2489 1.146 toshii if ((value & 0xff) != 0) {
2490 1.254.2.12 skrll return -1;
2491 1.1 augustss }
2492 1.254.2.12 skrll usb_hub_descriptor_t hubd;
2493 1.254.2.12 skrll
2494 1.254.2.12 skrll totlen = min(buflen, sizeof(hubd));
2495 1.254.2.12 skrll memcpy(&hubd, buf, totlen);
2496 1.254.2.12 skrll
2497 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2498 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2499 1.15 augustss USETW(hubd.wHubCharacteristics,
2500 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2501 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2502 1.1 augustss /* XXX overcurrent */
2503 1.1 augustss );
2504 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2505 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2506 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2507 1.254.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2508 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2509 1.254.2.12 skrll totlen = min(totlen, hubd.bDescLength);
2510 1.254.2.12 skrll memcpy(buf, &hubd, totlen);
2511 1.1 augustss break;
2512 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2513 1.1 augustss if (len != 4) {
2514 1.254.2.12 skrll return -1;
2515 1.1 augustss }
2516 1.1 augustss memset(buf, 0, len); /* ? XXX */
2517 1.1 augustss totlen = len;
2518 1.1 augustss break;
2519 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2520 1.254.2.12 skrll DPRINTFN(8,("%s: get port status i=%d\n", __func__,
2521 1.1 augustss index));
2522 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2523 1.254.2.12 skrll return -1;
2524 1.1 augustss }
2525 1.1 augustss if (len != 4) {
2526 1.254.2.12 skrll return -1;
2527 1.254.2.12 skrll }
2528 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2529 1.254.2.12 skrll DPRINTFN(8,("%s: port status=0x%04x\n", __func__,
2530 1.1 augustss v));
2531 1.1 augustss USETW(ps.wPortStatus, v);
2532 1.1 augustss USETW(ps.wPortChange, v >> 16);
2533 1.254.2.12 skrll totlen = min(len, sizeof(ps));
2534 1.254.2.12 skrll memcpy(buf, &ps, totlen);
2535 1.1 augustss break;
2536 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2537 1.254.2.12 skrll return -1;
2538 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2539 1.1 augustss break;
2540 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2541 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2542 1.254.2.12 skrll return -1;
2543 1.1 augustss }
2544 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2545 1.1 augustss switch(value) {
2546 1.1 augustss case UHF_PORT_ENABLE:
2547 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2548 1.1 augustss break;
2549 1.1 augustss case UHF_PORT_SUSPEND:
2550 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2551 1.1 augustss break;
2552 1.1 augustss case UHF_PORT_RESET:
2553 1.254.2.12 skrll DPRINTFN(5,("%s: reset port %d\n", __func__,
2554 1.14 augustss index));
2555 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2556 1.110 augustss for (i = 0; i < 5; i++) {
2557 1.110 augustss usb_delay_ms(&sc->sc_bus,
2558 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2559 1.116 augustss if (sc->sc_dying) {
2560 1.254.2.12 skrll return -1;
2561 1.116 augustss }
2562 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2563 1.1 augustss break;
2564 1.1 augustss }
2565 1.1 augustss DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
2566 1.1 augustss index, OREAD4(sc, port)));
2567 1.1 augustss break;
2568 1.1 augustss case UHF_PORT_POWER:
2569 1.254.2.12 skrll DPRINTFN(2,("%s: set port power "
2570 1.254.2.12 skrll "%d\n", __func__, index));
2571 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2572 1.1 augustss break;
2573 1.1 augustss default:
2574 1.254.2.12 skrll return -1;
2575 1.1 augustss }
2576 1.1 augustss break;
2577 1.1 augustss default:
2578 1.254.2.12 skrll /* default from usbroothub */
2579 1.254.2.12 skrll return buflen;
2580 1.1 augustss }
2581 1.1 augustss
2582 1.254.2.12 skrll return totlen;
2583 1.1 augustss }
2584 1.1 augustss
2585 1.82 augustss Static usbd_status
2586 1.91 augustss ohci_root_intr_transfer(usbd_xfer_handle xfer)
2587 1.1 augustss {
2588 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2589 1.53 augustss usbd_status err;
2590 1.17 augustss
2591 1.46 augustss /* Insert last in queue. */
2592 1.224 mrg mutex_enter(&sc->sc_lock);
2593 1.53 augustss err = usb_insert_transfer(xfer);
2594 1.224 mrg mutex_exit(&sc->sc_lock);
2595 1.53 augustss if (err)
2596 1.254.2.13 skrll return err;
2597 1.46 augustss
2598 1.46 augustss /* Pipe isn't running, start first */
2599 1.254.2.13 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2600 1.17 augustss }
2601 1.17 augustss
2602 1.82 augustss Static usbd_status
2603 1.91 augustss ohci_root_intr_start(usbd_xfer_handle xfer)
2604 1.17 augustss {
2605 1.254.2.7 skrll usbd_pipe_handle pipe = xfer->ux_pipe;
2606 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2607 1.1 augustss
2608 1.83 augustss if (sc->sc_dying)
2609 1.254.2.13 skrll return USBD_IOERROR;
2610 1.83 augustss
2611 1.224 mrg mutex_enter(&sc->sc_lock);
2612 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2613 1.53 augustss sc->sc_intrxfer = xfer;
2614 1.224 mrg mutex_exit(&sc->sc_lock);
2615 1.1 augustss
2616 1.254.2.13 skrll return USBD_IN_PROGRESS;
2617 1.1 augustss }
2618 1.1 augustss
2619 1.3 augustss /* Abort a root interrupt request. */
2620 1.82 augustss Static void
2621 1.91 augustss ohci_root_intr_abort(usbd_xfer_handle xfer)
2622 1.1 augustss {
2623 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2624 1.224 mrg
2625 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2626 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2627 1.53 augustss
2628 1.252 skrll sc->sc_intrxfer = NULL;
2629 1.252 skrll
2630 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
2631 1.53 augustss usb_transfer_complete(xfer);
2632 1.1 augustss }
2633 1.1 augustss
2634 1.1 augustss /* Close the root pipe. */
2635 1.82 augustss Static void
2636 1.91 augustss ohci_root_intr_close(usbd_pipe_handle pipe)
2637 1.1 augustss {
2638 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2639 1.120 augustss
2640 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2641 1.224 mrg
2642 1.1 augustss DPRINTF(("ohci_root_intr_close\n"));
2643 1.34 augustss
2644 1.53 augustss sc->sc_intrxfer = NULL;
2645 1.1 augustss }
2646 1.1 augustss
2647 1.1 augustss /************************/
2648 1.1 augustss
2649 1.82 augustss Static usbd_status
2650 1.91 augustss ohci_device_ctrl_transfer(usbd_xfer_handle xfer)
2651 1.1 augustss {
2652 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2653 1.53 augustss usbd_status err;
2654 1.17 augustss
2655 1.46 augustss /* Insert last in queue. */
2656 1.224 mrg mutex_enter(&sc->sc_lock);
2657 1.53 augustss err = usb_insert_transfer(xfer);
2658 1.224 mrg mutex_exit(&sc->sc_lock);
2659 1.53 augustss if (err)
2660 1.254.2.13 skrll return err;
2661 1.46 augustss
2662 1.46 augustss /* Pipe isn't running, start first */
2663 1.254.2.13 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2664 1.17 augustss }
2665 1.17 augustss
2666 1.82 augustss Static usbd_status
2667 1.91 augustss ohci_device_ctrl_start(usbd_xfer_handle xfer)
2668 1.17 augustss {
2669 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2670 1.53 augustss usbd_status err;
2671 1.1 augustss
2672 1.83 augustss if (sc->sc_dying)
2673 1.254.2.13 skrll return USBD_IOERROR;
2674 1.83 augustss
2675 1.42 augustss #ifdef DIAGNOSTIC
2676 1.254.2.7 skrll if (!(xfer->ux_rqflags & URQ_REQUEST)) {
2677 1.1 augustss /* XXX panic */
2678 1.1 augustss printf("ohci_device_ctrl_transfer: not a request\n");
2679 1.254.2.13 skrll return USBD_INVAL;
2680 1.1 augustss }
2681 1.42 augustss #endif
2682 1.1 augustss
2683 1.224 mrg mutex_enter(&sc->sc_lock);
2684 1.53 augustss err = ohci_device_request(xfer);
2685 1.224 mrg mutex_exit(&sc->sc_lock);
2686 1.53 augustss if (err)
2687 1.254.2.13 skrll return err;
2688 1.1 augustss
2689 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling)
2690 1.53 augustss ohci_waitintr(sc, xfer);
2691 1.254.2.13 skrll return USBD_IN_PROGRESS;
2692 1.1 augustss }
2693 1.1 augustss
2694 1.1 augustss /* Abort a device control request. */
2695 1.82 augustss Static void
2696 1.91 augustss ohci_device_ctrl_abort(usbd_xfer_handle xfer)
2697 1.1 augustss {
2698 1.224 mrg #ifdef DIAGNOSTIC
2699 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2700 1.224 mrg #endif
2701 1.224 mrg
2702 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2703 1.224 mrg
2704 1.53 augustss DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer));
2705 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2706 1.1 augustss }
2707 1.1 augustss
2708 1.1 augustss /* Close a device control pipe. */
2709 1.82 augustss Static void
2710 1.91 augustss ohci_device_ctrl_close(usbd_pipe_handle pipe)
2711 1.1 augustss {
2712 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2713 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2714 1.1 augustss
2715 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2716 1.224 mrg
2717 1.34 augustss DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe));
2718 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2719 1.60 augustss ohci_free_std(sc, opipe->tail.td);
2720 1.3 augustss }
2721 1.3 augustss
2722 1.3 augustss /************************/
2723 1.37 augustss
2724 1.82 augustss Static void
2725 1.91 augustss ohci_device_clear_toggle(usbd_pipe_handle pipe)
2726 1.37 augustss {
2727 1.37 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2728 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2729 1.37 augustss
2730 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2731 1.37 augustss }
2732 1.37 augustss
2733 1.82 augustss Static void
2734 1.179 christos ohci_noop(usbd_pipe_handle pipe)
2735 1.37 augustss {
2736 1.37 augustss }
2737 1.3 augustss
2738 1.82 augustss Static usbd_status
2739 1.91 augustss ohci_device_bulk_transfer(usbd_xfer_handle xfer)
2740 1.3 augustss {
2741 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2742 1.53 augustss usbd_status err;
2743 1.17 augustss
2744 1.46 augustss /* Insert last in queue. */
2745 1.224 mrg mutex_enter(&sc->sc_lock);
2746 1.53 augustss err = usb_insert_transfer(xfer);
2747 1.224 mrg mutex_exit(&sc->sc_lock);
2748 1.53 augustss if (err)
2749 1.254.2.13 skrll return err;
2750 1.46 augustss
2751 1.46 augustss /* Pipe isn't running, start first */
2752 1.254.2.13 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2753 1.17 augustss }
2754 1.17 augustss
2755 1.82 augustss Static usbd_status
2756 1.91 augustss ohci_device_bulk_start(usbd_xfer_handle xfer)
2757 1.17 augustss {
2758 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
2759 1.254.2.7 skrll usbd_device_handle dev = opipe->pipe.up_dev;
2760 1.254.2.7 skrll ohci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2761 1.254.2.7 skrll int addr = dev->ud_addr;
2762 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
2763 1.3 augustss ohci_soft_ed_t *sed;
2764 1.224 mrg int len, isread, endpt;
2765 1.53 augustss usbd_status err;
2766 1.3 augustss
2767 1.83 augustss if (sc->sc_dying)
2768 1.254.2.13 skrll return USBD_IOERROR;
2769 1.83 augustss
2770 1.34 augustss #ifdef DIAGNOSTIC
2771 1.254.2.7 skrll if (xfer->ux_rqflags & URQ_REQUEST) {
2772 1.3 augustss /* XXX panic */
2773 1.34 augustss printf("ohci_device_bulk_start: a request\n");
2774 1.254.2.13 skrll return USBD_INVAL;
2775 1.3 augustss }
2776 1.34 augustss #endif
2777 1.3 augustss
2778 1.224 mrg mutex_enter(&sc->sc_lock);
2779 1.224 mrg
2780 1.254.2.7 skrll len = xfer->ux_length;
2781 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2782 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2783 1.3 augustss sed = opipe->sed;
2784 1.3 augustss
2785 1.53 augustss DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d "
2786 1.254.2.7 skrll "flags=%d endpt=%d\n", xfer, len, isread, xfer->ux_flags,
2787 1.40 augustss endpt));
2788 1.34 augustss
2789 1.32 augustss opipe->u.bulk.isread = isread;
2790 1.3 augustss opipe->u.bulk.length = len;
2791 1.3 augustss
2792 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2793 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2794 1.3 augustss /* Update device address */
2795 1.168 augustss sed->ed.ed_flags = HTOO32(
2796 1.168 augustss (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) |
2797 1.16 augustss OHCI_ED_SET_FA(addr));
2798 1.3 augustss
2799 1.48 augustss /* Allocate a chain of new TDs (including a new tail). */
2800 1.60 augustss data = opipe->tail.td;
2801 1.77 augustss err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
2802 1.77 augustss data, &tail);
2803 1.236 skrll if (err)
2804 1.236 skrll return err;
2805 1.254.2.1 skrll
2806 1.77 augustss /* We want interrupt at the end of the transfer. */
2807 1.168 augustss tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
2808 1.168 augustss tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
2809 1.77 augustss tail->flags |= OHCI_CALL_DONE;
2810 1.77 augustss tail = tail->nexttd; /* point at sentinel */
2811 1.195 bouyer usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags),
2812 1.195 bouyer sizeof(tail->td.td_flags),
2813 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2814 1.224 mrg if (err) {
2815 1.224 mrg mutex_exit(&sc->sc_lock);
2816 1.254.2.13 skrll return err;
2817 1.224 mrg }
2818 1.48 augustss
2819 1.53 augustss tail->xfer = NULL;
2820 1.254.2.7 skrll xfer->ux_hcpriv = data;
2821 1.3 augustss
2822 1.34 augustss DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x "
2823 1.34 augustss "td_cbp=0x%08x td_be=0x%08x\n",
2824 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
2825 1.168 augustss (int)O32TOH(data->td.td_flags),
2826 1.168 augustss (int)O32TOH(data->td.td_cbp),
2827 1.168 augustss (int)O32TOH(data->td.td_be)));
2828 1.34 augustss
2829 1.52 augustss #ifdef OHCI_DEBUG
2830 1.75 augustss if (ohcidebug > 5) {
2831 1.168 augustss ohci_dump_ed(sc, sed);
2832 1.168 augustss ohci_dump_tds(sc, data);
2833 1.34 augustss }
2834 1.34 augustss #endif
2835 1.34 augustss
2836 1.3 augustss /* Insert ED in schedule */
2837 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
2838 1.53 augustss tdp->xfer = xfer;
2839 1.48 augustss }
2840 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
2841 1.60 augustss opipe->tail.td = tail;
2842 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
2843 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2844 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2845 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
2846 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2847 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2848 1.80 augustss ohci_timeout, xfer);
2849 1.15 augustss }
2850 1.224 mrg mutex_exit(&sc->sc_lock);
2851 1.34 augustss
2852 1.52 augustss #if 0
2853 1.52 augustss /* This goes wrong if we are too slow. */
2854 1.75 augustss if (ohcidebug > 10) {
2855 1.75 augustss delay(10000);
2856 1.41 augustss DPRINTF(("ohci_device_intr_transfer: status=%x\n",
2857 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
2858 1.168 augustss ohci_dump_ed(sc, sed);
2859 1.168 augustss ohci_dump_tds(sc, data);
2860 1.34 augustss }
2861 1.34 augustss #endif
2862 1.34 augustss
2863 1.254.2.13 skrll return USBD_IN_PROGRESS;
2864 1.3 augustss }
2865 1.3 augustss
2866 1.82 augustss Static void
2867 1.91 augustss ohci_device_bulk_abort(usbd_xfer_handle xfer)
2868 1.3 augustss {
2869 1.224 mrg #ifdef DIAGNOSTIC
2870 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2871 1.224 mrg #endif
2872 1.224 mrg
2873 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2874 1.224 mrg
2875 1.53 augustss DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer));
2876 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2877 1.3 augustss }
2878 1.3 augustss
2879 1.120 augustss /*
2880 1.34 augustss * Close a device bulk pipe.
2881 1.34 augustss */
2882 1.82 augustss Static void
2883 1.91 augustss ohci_device_bulk_close(usbd_pipe_handle pipe)
2884 1.3 augustss {
2885 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2886 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
2887 1.3 augustss
2888 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2889 1.224 mrg
2890 1.34 augustss DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe));
2891 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
2892 1.60 augustss ohci_free_std(sc, opipe->tail.td);
2893 1.1 augustss }
2894 1.1 augustss
2895 1.1 augustss /************************/
2896 1.1 augustss
2897 1.82 augustss Static usbd_status
2898 1.91 augustss ohci_device_intr_transfer(usbd_xfer_handle xfer)
2899 1.17 augustss {
2900 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
2901 1.53 augustss usbd_status err;
2902 1.17 augustss
2903 1.46 augustss /* Insert last in queue. */
2904 1.224 mrg mutex_enter(&sc->sc_lock);
2905 1.53 augustss err = usb_insert_transfer(xfer);
2906 1.224 mrg mutex_exit(&sc->sc_lock);
2907 1.53 augustss if (err)
2908 1.254.2.13 skrll return err;
2909 1.46 augustss
2910 1.46 augustss /* Pipe isn't running, start first */
2911 1.254.2.13 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2912 1.17 augustss }
2913 1.17 augustss
2914 1.82 augustss Static usbd_status
2915 1.91 augustss ohci_device_intr_start(usbd_xfer_handle xfer)
2916 1.1 augustss {
2917 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
2918 1.254.2.7 skrll usbd_device_handle dev = opipe->pipe.up_dev;
2919 1.254.2.7 skrll ohci_softc_t *sc = dev->ud_bus->ub_hcpriv;
2920 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
2921 1.48 augustss ohci_soft_td_t *data, *tail;
2922 1.224 mrg int len, isread, endpt;
2923 1.1 augustss
2924 1.83 augustss if (sc->sc_dying)
2925 1.254.2.13 skrll return USBD_IOERROR;
2926 1.83 augustss
2927 1.53 augustss DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d "
2928 1.14 augustss "flags=%d priv=%p\n",
2929 1.254.2.7 skrll xfer, xfer->ux_length, xfer->ux_flags, xfer->ux_priv));
2930 1.1 augustss
2931 1.42 augustss #ifdef DIAGNOSTIC
2932 1.254.2.7 skrll if (xfer->ux_rqflags & URQ_REQUEST)
2933 1.128 provos panic("ohci_device_intr_transfer: a request");
2934 1.42 augustss #endif
2935 1.1 augustss
2936 1.254.2.7 skrll len = xfer->ux_length;
2937 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2938 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2939 1.1 augustss
2940 1.60 augustss data = opipe->tail.td;
2941 1.224 mrg mutex_enter(&sc->sc_lock);
2942 1.1 augustss tail = ohci_alloc_std(sc);
2943 1.224 mrg mutex_exit(&sc->sc_lock);
2944 1.55 augustss if (tail == NULL)
2945 1.254.2.13 skrll return USBD_NOMEM;
2946 1.53 augustss tail->xfer = NULL;
2947 1.1 augustss
2948 1.168 augustss data->td.td_flags = HTOO32(
2949 1.165 skrll isread ? OHCI_TD_IN : OHCI_TD_OUT |
2950 1.165 skrll OHCI_TD_NOCC |
2951 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
2952 1.254.2.7 skrll if (xfer->ux_flags & USBD_SHORT_XFER_OK)
2953 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
2954 1.254.2.7 skrll data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0));
2955 1.48 augustss data->nexttd = tail;
2956 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
2957 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1);
2958 1.48 augustss data->len = len;
2959 1.53 augustss data->xfer = xfer;
2960 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
2961 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
2962 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2963 1.254.2.7 skrll xfer->ux_hcpriv = data;
2964 1.1 augustss
2965 1.52 augustss #ifdef OHCI_DEBUG
2966 1.1 augustss if (ohcidebug > 5) {
2967 1.41 augustss DPRINTF(("ohci_device_intr_transfer:\n"));
2968 1.168 augustss ohci_dump_ed(sc, sed);
2969 1.168 augustss ohci_dump_tds(sc, data);
2970 1.1 augustss }
2971 1.1 augustss #endif
2972 1.1 augustss
2973 1.1 augustss /* Insert ED in schedule */
2974 1.224 mrg mutex_enter(&sc->sc_lock);
2975 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2976 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2977 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
2978 1.60 augustss opipe->tail.td = tail;
2979 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
2980 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2981 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2982 1.1 augustss
2983 1.52 augustss #if 0
2984 1.52 augustss /*
2985 1.52 augustss * This goes horribly wrong, printing thousands of descriptors,
2986 1.52 augustss * because false references are followed due to the fact that the
2987 1.52 augustss * TD is gone.
2988 1.52 augustss */
2989 1.1 augustss if (ohcidebug > 5) {
2990 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock);
2991 1.41 augustss DPRINTF(("ohci_device_intr_transfer: status=%x\n",
2992 1.41 augustss OREAD4(sc, OHCI_COMMAND_STATUS)));
2993 1.168 augustss ohci_dump_ed(sc, sed);
2994 1.168 augustss ohci_dump_tds(sc, data);
2995 1.1 augustss }
2996 1.1 augustss #endif
2997 1.224 mrg mutex_exit(&sc->sc_lock);
2998 1.1 augustss
2999 1.254.2.13 skrll return USBD_IN_PROGRESS;
3000 1.1 augustss }
3001 1.1 augustss
3002 1.227 skrll /* Abort a device interrupt request. */
3003 1.82 augustss Static void
3004 1.91 augustss ohci_device_intr_abort(usbd_xfer_handle xfer)
3005 1.1 augustss {
3006 1.224 mrg #ifdef DIAGNOSTIC
3007 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3008 1.224 mrg #endif
3009 1.224 mrg
3010 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3011 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3012 1.224 mrg
3013 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3014 1.1 augustss }
3015 1.1 augustss
3016 1.1 augustss /* Close a device interrupt pipe. */
3017 1.82 augustss Static void
3018 1.91 augustss ohci_device_intr_close(usbd_pipe_handle pipe)
3019 1.1 augustss {
3020 1.1 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3021 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3022 1.1 augustss int nslots = opipe->u.intr.nslots;
3023 1.1 augustss int pos = opipe->u.intr.pos;
3024 1.1 augustss int j;
3025 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3026 1.224 mrg
3027 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3028 1.1 augustss
3029 1.1 augustss DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
3030 1.1 augustss pipe, nslots, pos));
3031 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3032 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3033 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3034 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3035 1.195 bouyer sizeof(sed->ed.ed_flags),
3036 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3037 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3038 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3039 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3040 1.1 augustss
3041 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3042 1.172 christos continue;
3043 1.53 augustss #ifdef DIAGNOSTIC
3044 1.173 christos if (p == NULL)
3045 1.128 provos panic("ohci_device_intr_close: ED not found");
3046 1.53 augustss #endif
3047 1.173 christos p->next = sed->next;
3048 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3049 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3050 1.195 bouyer sizeof(p->ed.ed_nexted),
3051 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3052 1.1 augustss
3053 1.1 augustss for (j = 0; j < nslots; j++)
3054 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3055 1.1 augustss
3056 1.60 augustss ohci_free_std(sc, opipe->tail.td);
3057 1.1 augustss ohci_free_sed(sc, opipe->sed);
3058 1.1 augustss }
3059 1.1 augustss
3060 1.82 augustss Static usbd_status
3061 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3062 1.1 augustss {
3063 1.224 mrg int i, j, best;
3064 1.1 augustss u_int npoll, slow, shigh, nslots;
3065 1.1 augustss u_int bestbw, bw;
3066 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3067 1.1 augustss
3068 1.1 augustss DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
3069 1.1 augustss if (ival == 0) {
3070 1.1 augustss printf("ohci_setintr: 0 interval\n");
3071 1.254.2.13 skrll return USBD_INVAL;
3072 1.1 augustss }
3073 1.1 augustss
3074 1.1 augustss npoll = OHCI_NO_INTRS;
3075 1.1 augustss while (npoll > ival)
3076 1.1 augustss npoll /= 2;
3077 1.1 augustss DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
3078 1.1 augustss
3079 1.1 augustss /*
3080 1.1 augustss * We now know which level in the tree the ED must go into.
3081 1.1 augustss * Figure out which slot has most bandwidth left over.
3082 1.1 augustss * Slots to examine:
3083 1.1 augustss * npoll
3084 1.1 augustss * 1 0
3085 1.1 augustss * 2 1 2
3086 1.1 augustss * 4 3 4 5 6
3087 1.1 augustss * 8 7 8 9 10 11 12 13 14
3088 1.1 augustss * N (N-1) .. (N-1+N-1)
3089 1.1 augustss */
3090 1.1 augustss slow = npoll-1;
3091 1.1 augustss shigh = slow + npoll;
3092 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3093 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3094 1.1 augustss bw = 0;
3095 1.1 augustss for (j = 0; j < nslots; j++)
3096 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3097 1.1 augustss if (bw < bestbw) {
3098 1.1 augustss best = i;
3099 1.1 augustss bestbw = bw;
3100 1.1 augustss }
3101 1.1 augustss }
3102 1.120 augustss DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
3103 1.1 augustss best, slow, shigh, bestbw));
3104 1.1 augustss
3105 1.224 mrg mutex_enter(&sc->sc_lock);
3106 1.1 augustss hsed = sc->sc_eds[best];
3107 1.1 augustss sed->next = hsed->next;
3108 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3109 1.195 bouyer sizeof(hsed->ed.ed_flags),
3110 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3111 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3112 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3113 1.195 bouyer sizeof(sed->ed.ed_flags),
3114 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3115 1.1 augustss hsed->next = sed;
3116 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3117 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3118 1.195 bouyer sizeof(hsed->ed.ed_flags),
3119 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3120 1.224 mrg mutex_exit(&sc->sc_lock);
3121 1.1 augustss
3122 1.1 augustss for (j = 0; j < nslots; j++)
3123 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3124 1.1 augustss opipe->u.intr.nslots = nslots;
3125 1.1 augustss opipe->u.intr.pos = best;
3126 1.1 augustss
3127 1.1 augustss DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
3128 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3129 1.60 augustss }
3130 1.60 augustss
3131 1.60 augustss /***********************/
3132 1.60 augustss
3133 1.60 augustss usbd_status
3134 1.91 augustss ohci_device_isoc_transfer(usbd_xfer_handle xfer)
3135 1.60 augustss {
3136 1.254.2.7 skrll ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv;
3137 1.60 augustss usbd_status err;
3138 1.60 augustss
3139 1.60 augustss DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer));
3140 1.60 augustss
3141 1.60 augustss /* Put it on our queue, */
3142 1.224 mrg mutex_enter(&sc->sc_lock);
3143 1.60 augustss err = usb_insert_transfer(xfer);
3144 1.224 mrg mutex_exit(&sc->sc_lock);
3145 1.60 augustss
3146 1.60 augustss /* bail out on error, */
3147 1.60 augustss if (err && err != USBD_IN_PROGRESS)
3148 1.254.2.13 skrll return err;
3149 1.60 augustss
3150 1.60 augustss /* XXX should check inuse here */
3151 1.60 augustss
3152 1.60 augustss /* insert into schedule, */
3153 1.60 augustss ohci_device_isoc_enter(xfer);
3154 1.60 augustss
3155 1.83 augustss /* and start if the pipe wasn't running */
3156 1.60 augustss if (!err)
3157 1.254.2.7 skrll ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3158 1.60 augustss
3159 1.254.2.13 skrll return err;
3160 1.60 augustss }
3161 1.60 augustss
3162 1.60 augustss void
3163 1.91 augustss ohci_device_isoc_enter(usbd_xfer_handle xfer)
3164 1.60 augustss {
3165 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
3166 1.254.2.7 skrll usbd_device_handle dev = opipe->pipe.up_dev;
3167 1.254.2.7 skrll ohci_softc_t *sc = dev->ud_bus->ub_hcpriv;
3168 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3169 1.61 augustss struct iso *iso = &opipe->u.iso;
3170 1.120 augustss ohci_soft_itd_t *sitd, *nsitd;
3171 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3172 1.61 augustss int i, ncur, nframes;
3173 1.61 augustss
3174 1.83 augustss DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p "
3175 1.83 augustss "nframes=%d\n",
3176 1.254.2.7 skrll iso->inuse, iso->next, xfer, xfer->ux_nframes));
3177 1.83 augustss
3178 1.83 augustss if (sc->sc_dying)
3179 1.83 augustss return;
3180 1.83 augustss
3181 1.83 augustss if (iso->next == -1) {
3182 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3183 1.168 augustss iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3184 1.120 augustss DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n",
3185 1.83 augustss iso->next));
3186 1.83 augustss }
3187 1.83 augustss
3188 1.61 augustss sitd = opipe->tail.itd;
3189 1.254.2.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3190 1.83 augustss bp0 = OHCI_PAGE(buf);
3191 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3192 1.254.2.7 skrll nframes = xfer->ux_nframes;
3193 1.254.2.7 skrll xfer->ux_hcpriv = sitd;
3194 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3195 1.254.2.7 skrll noffs = offs + xfer->ux_frlengths[i];
3196 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3197 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3198 1.120 augustss
3199 1.83 augustss /* Allocate next ITD */
3200 1.224 mrg mutex_enter(&sc->sc_lock);
3201 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3202 1.224 mrg mutex_exit(&sc->sc_lock);
3203 1.61 augustss if (nsitd == NULL) {
3204 1.61 augustss /* XXX what now? */
3205 1.83 augustss printf("%s: isoc TD alloc failed\n",
3206 1.190 drochner device_xname(sc->sc_dev));
3207 1.61 augustss return;
3208 1.61 augustss }
3209 1.83 augustss
3210 1.83 augustss /* Fill current ITD */
3211 1.168 augustss sitd->itd.itd_flags = HTOO32(
3212 1.120 augustss OHCI_ITD_NOCC |
3213 1.61 augustss OHCI_ITD_SET_SF(iso->next) |
3214 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3215 1.83 augustss OHCI_ITD_SET_FC(ncur));
3216 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3217 1.83 augustss sitd->nextitd = nsitd;
3218 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3219 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3220 1.83 augustss sitd->xfer = xfer;
3221 1.83 augustss sitd->flags = 0;
3222 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3223 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3224 1.83 augustss
3225 1.61 augustss sitd = nsitd;
3226 1.120 augustss iso->next = iso->next + ncur;
3227 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3228 1.61 augustss ncur = 0;
3229 1.61 augustss }
3230 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3231 1.83 augustss offs = noffs;
3232 1.61 augustss }
3233 1.224 mrg mutex_enter(&sc->sc_lock);
3234 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3235 1.224 mrg mutex_exit(&sc->sc_lock);
3236 1.61 augustss if (nsitd == NULL) {
3237 1.61 augustss /* XXX what now? */
3238 1.120 augustss printf("%s: isoc TD alloc failed\n",
3239 1.190 drochner device_xname(sc->sc_dev));
3240 1.61 augustss return;
3241 1.61 augustss }
3242 1.83 augustss /* Fixup last used ITD */
3243 1.168 augustss sitd->itd.itd_flags = HTOO32(
3244 1.120 augustss OHCI_ITD_NOCC |
3245 1.61 augustss OHCI_ITD_SET_SF(iso->next) |
3246 1.61 augustss OHCI_ITD_SET_DI(0) |
3247 1.61 augustss OHCI_ITD_SET_FC(ncur));
3248 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3249 1.83 augustss sitd->nextitd = nsitd;
3250 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3251 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3252 1.83 augustss sitd->xfer = xfer;
3253 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3254 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3255 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3256 1.83 augustss
3257 1.61 augustss iso->next = iso->next + ncur;
3258 1.83 augustss iso->inuse += nframes;
3259 1.83 augustss
3260 1.254.2.7 skrll xfer->ux_actlen = offs; /* XXX pretend we did it all */
3261 1.83 augustss
3262 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3263 1.83 augustss
3264 1.83 augustss #ifdef OHCI_DEBUG
3265 1.83 augustss if (ohcidebug > 5) {
3266 1.83 augustss DPRINTF(("ohci_device_isoc_enter: frame=%d\n",
3267 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number)));
3268 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3269 1.168 augustss ohci_dump_ed(sc, sed);
3270 1.83 augustss }
3271 1.83 augustss #endif
3272 1.61 augustss
3273 1.224 mrg mutex_enter(&sc->sc_lock);
3274 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3275 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3276 1.168 augustss sed->ed.ed_tailp = HTOO32(nsitd->physaddr);
3277 1.61 augustss opipe->tail.itd = nsitd;
3278 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3279 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3280 1.195 bouyer sizeof(sed->ed.ed_flags),
3281 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3282 1.224 mrg mutex_exit(&sc->sc_lock);
3283 1.83 augustss
3284 1.83 augustss #ifdef OHCI_DEBUG
3285 1.83 augustss if (ohcidebug > 5) {
3286 1.83 augustss delay(150000);
3287 1.83 augustss DPRINTF(("ohci_device_isoc_enter: after frame=%d\n",
3288 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number)));
3289 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3290 1.168 augustss ohci_dump_ed(sc, sed);
3291 1.83 augustss }
3292 1.83 augustss #endif
3293 1.60 augustss }
3294 1.60 augustss
3295 1.60 augustss usbd_status
3296 1.91 augustss ohci_device_isoc_start(usbd_xfer_handle xfer)
3297 1.60 augustss {
3298 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
3299 1.254.2.7 skrll ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv;
3300 1.83 augustss
3301 1.83 augustss DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer));
3302 1.83 augustss
3303 1.224 mrg mutex_enter(&sc->sc_lock);
3304 1.224 mrg
3305 1.224 mrg if (sc->sc_dying) {
3306 1.224 mrg mutex_exit(&sc->sc_lock);
3307 1.254.2.13 skrll return USBD_IOERROR;
3308 1.224 mrg }
3309 1.83 augustss
3310 1.83 augustss #ifdef DIAGNOSTIC
3311 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
3312 1.121 tsutsui printf("ohci_device_isoc_start: not in progress %p\n", xfer);
3313 1.83 augustss #endif
3314 1.83 augustss
3315 1.83 augustss /* XXX anything to do? */
3316 1.83 augustss
3317 1.224 mrg mutex_exit(&sc->sc_lock);
3318 1.224 mrg
3319 1.254.2.13 skrll return USBD_IN_PROGRESS;
3320 1.60 augustss }
3321 1.60 augustss
3322 1.60 augustss void
3323 1.91 augustss ohci_device_isoc_abort(usbd_xfer_handle xfer)
3324 1.60 augustss {
3325 1.254.2.7 skrll struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe;
3326 1.254.2.7 skrll ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv;
3327 1.83 augustss ohci_soft_ed_t *sed;
3328 1.83 augustss ohci_soft_itd_t *sitd;
3329 1.83 augustss
3330 1.224 mrg DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock));
3331 1.83 augustss
3332 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3333 1.83 augustss
3334 1.83 augustss /* Transfer is already done. */
3335 1.254.2.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3336 1.254.2.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3337 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3338 1.224 mrg goto done;
3339 1.83 augustss }
3340 1.83 augustss
3341 1.83 augustss /* Give xfer the requested abort code. */
3342 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
3343 1.83 augustss
3344 1.83 augustss sed = opipe->sed;
3345 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3346 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3347 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3348 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3349 1.195 bouyer sizeof(sed->ed.ed_flags),
3350 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3351 1.83 augustss
3352 1.254.2.7 skrll sitd = xfer->ux_hcpriv;
3353 1.83 augustss #ifdef DIAGNOSTIC
3354 1.83 augustss if (sitd == NULL) {
3355 1.83 augustss printf("ohci_device_isoc_abort: hcpriv==0\n");
3356 1.224 mrg goto done;
3357 1.83 augustss }
3358 1.83 augustss #endif
3359 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3360 1.83 augustss #ifdef DIAGNOSTIC
3361 1.83 augustss DPRINTFN(1,("abort sets done sitd=%p\n", sitd));
3362 1.83 augustss sitd->isdone = 1;
3363 1.83 augustss #endif
3364 1.83 augustss }
3365 1.83 augustss
3366 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3367 1.83 augustss
3368 1.83 augustss /* Run callback. */
3369 1.83 augustss usb_transfer_complete(xfer);
3370 1.83 augustss
3371 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3372 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3373 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3374 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3375 1.83 augustss
3376 1.224 mrg done:
3377 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3378 1.60 augustss }
3379 1.60 augustss
3380 1.60 augustss void
3381 1.179 christos ohci_device_isoc_done(usbd_xfer_handle xfer)
3382 1.60 augustss {
3383 1.83 augustss DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer));
3384 1.60 augustss }
3385 1.60 augustss
3386 1.60 augustss usbd_status
3387 1.91 augustss ohci_setup_isoc(usbd_pipe_handle pipe)
3388 1.60 augustss {
3389 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3390 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3391 1.60 augustss struct iso *iso = &opipe->u.iso;
3392 1.60 augustss
3393 1.60 augustss iso->next = -1;
3394 1.60 augustss iso->inuse = 0;
3395 1.60 augustss
3396 1.224 mrg mutex_enter(&sc->sc_lock);
3397 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3398 1.224 mrg mutex_exit(&sc->sc_lock);
3399 1.83 augustss
3400 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3401 1.60 augustss }
3402 1.60 augustss
3403 1.60 augustss void
3404 1.91 augustss ohci_device_isoc_close(usbd_pipe_handle pipe)
3405 1.60 augustss {
3406 1.60 augustss struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
3407 1.254.2.7 skrll ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv;
3408 1.60 augustss
3409 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3410 1.224 mrg
3411 1.60 augustss DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe));
3412 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3413 1.83 augustss #ifdef DIAGNOSTIC
3414 1.83 augustss opipe->tail.itd->isdone = 1;
3415 1.83 augustss #endif
3416 1.60 augustss ohci_free_sitd(sc, opipe->tail.itd);
3417 1.1 augustss }
3418