ohci.c revision 1.254.2.27 1 1.254.2.27 skrll /* $NetBSD: ohci.c,v 1.254.2.27 2015/11/14 10:05:47 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.254.2.27 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.27 2015/11/14 10:05:47 skrll Exp $");
45 1.254.2.18 skrll
46 1.254.2.18 skrll #include "opt_usb.h"
47 1.1 augustss
48 1.1 augustss #include <sys/param.h>
49 1.254.2.17 skrll
50 1.254.2.17 skrll #include <sys/cpu.h>
51 1.1 augustss #include <sys/device.h>
52 1.254.2.17 skrll #include <sys/kernel.h>
53 1.254.2.17 skrll #include <sys/kmem.h>
54 1.1 augustss #include <sys/proc.h>
55 1.1 augustss #include <sys/queue.h>
56 1.254.2.17 skrll #include <sys/select.h>
57 1.254.2.18 skrll #include <sys/sysctl.h>
58 1.254.2.17 skrll #include <sys/systm.h>
59 1.1 augustss
60 1.16 augustss #include <machine/endian.h>
61 1.4 augustss
62 1.1 augustss #include <dev/usb/usb.h>
63 1.1 augustss #include <dev/usb/usbdi.h>
64 1.1 augustss #include <dev/usb/usbdivar.h>
65 1.38 augustss #include <dev/usb/usb_mem.h>
66 1.1 augustss #include <dev/usb/usb_quirks.h>
67 1.1 augustss
68 1.1 augustss #include <dev/usb/ohcireg.h>
69 1.1 augustss #include <dev/usb/ohcivar.h>
70 1.254.2.11 skrll #include <dev/usb/usbroothub.h>
71 1.254.2.18 skrll #include <dev/usb/usbhist.h>
72 1.1 augustss
73 1.254.2.18 skrll #ifdef USB_DEBUG
74 1.254.2.18 skrll #ifndef OHCI_DEBUG
75 1.254.2.18 skrll #define ohcidebug 0
76 1.254.2.18 skrll #else
77 1.254.2.18 skrll static int ohcidebug = 0;
78 1.1 augustss
79 1.254.2.18 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
80 1.254.2.18 skrll {
81 1.254.2.18 skrll int err;
82 1.254.2.18 skrll const struct sysctlnode *rnode;
83 1.254.2.18 skrll const struct sysctlnode *cnode;
84 1.254.2.18 skrll
85 1.254.2.18 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
86 1.254.2.18 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
87 1.254.2.18 skrll SYSCTL_DESCR("ohci global controls"),
88 1.254.2.18 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
89 1.36 augustss
90 1.254.2.18 skrll if (err)
91 1.254.2.18 skrll goto fail;
92 1.254.2.18 skrll
93 1.254.2.18 skrll /* control debugging printfs */
94 1.254.2.18 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
95 1.254.2.18 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
96 1.254.2.18 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
97 1.254.2.18 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
98 1.254.2.18 skrll if (err)
99 1.254.2.18 skrll goto fail;
100 1.254.2.18 skrll
101 1.254.2.18 skrll return;
102 1.254.2.18 skrll fail:
103 1.254.2.18 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
104 1.254.2.18 skrll }
105 1.254.2.18 skrll
106 1.254.2.18 skrll #endif /* OHCI_DEBUG */
107 1.254.2.18 skrll #endif /* USB_DEBUG */
108 1.254.2.18 skrll
109 1.254.2.18 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
110 1.254.2.18 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
111 1.254.2.18 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
112 1.254.2.18 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
113 1.52 augustss
114 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
115 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
116 1.16 augustss #else
117 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
118 1.16 augustss #endif
119 1.16 augustss
120 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
121 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
122 1.169 tron #define HTOO16(val) O16TOH(val)
123 1.169 tron #define HTOO32(val) O32TOH(val)
124 1.168 augustss
125 1.1 augustss struct ohci_pipe;
126 1.1 augustss
127 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
128 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
129 1.1 augustss
130 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
131 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
132 1.1 augustss
133 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
134 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
135 1.60 augustss
136 1.91 augustss Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *,
137 1.91 augustss ohci_soft_td_t *);
138 1.91 augustss Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *,
139 1.254.2.19 skrll ohci_softc_t *, int, int, struct usbd_xfer *,
140 1.91 augustss ohci_soft_td_t *, ohci_soft_td_t **);
141 1.53 augustss
142 1.254.2.19 skrll Static usbd_status ohci_open(struct usbd_pipe *);
143 1.91 augustss Static void ohci_poll(struct usbd_bus *);
144 1.99 augustss Static void ohci_softintr(void *);
145 1.254.2.19 skrll Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *);
146 1.254.2.19 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
147 1.254.2.15 skrll Static void ohci_rhsc_softint(void *);
148 1.91 augustss
149 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
150 1.168 augustss ohci_soft_ed_t *);
151 1.168 augustss
152 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
153 1.224 mrg ohci_soft_ed_t *);
154 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
155 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
156 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
157 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
158 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
159 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
160 1.91 augustss
161 1.254.2.19 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
162 1.254.2.19 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
163 1.91 augustss
164 1.254.2.23 skrll Static struct usbd_xfer *
165 1.254.2.23 skrll ohci_allocx(struct usbd_bus *, unsigned int);
166 1.254.2.19 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
167 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
168 1.254.2.13 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
169 1.254.2.26 skrll usb_device_request_t *, void *, int);
170 1.91 augustss
171 1.254.2.19 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
172 1.254.2.19 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
173 1.254.2.19 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
174 1.254.2.19 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
175 1.254.2.19 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
176 1.254.2.19 skrll
177 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
178 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
179 1.254.2.19 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
180 1.254.2.19 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
181 1.254.2.19 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
182 1.254.2.19 skrll
183 1.254.2.19 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
184 1.254.2.19 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
185 1.254.2.19 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
186 1.254.2.19 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
187 1.254.2.19 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
188 1.254.2.19 skrll
189 1.254.2.19 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
190 1.254.2.19 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
191 1.254.2.19 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
192 1.254.2.19 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
193 1.254.2.19 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
194 1.254.2.19 skrll
195 1.254.2.19 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
196 1.254.2.19 skrll Static usbd_status ohci_device_isoc_start(struct usbd_xfer *);
197 1.254.2.19 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
198 1.254.2.19 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
199 1.254.2.19 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
200 1.91 augustss
201 1.254.2.15 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
202 1.254.2.15 skrll struct ohci_pipe *, int);
203 1.91 augustss
204 1.91 augustss Static void ohci_timeout(void *);
205 1.114 augustss Static void ohci_timeout_task(void *);
206 1.104 augustss Static void ohci_rhsc_enable(void *);
207 1.91 augustss
208 1.254.2.19 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
209 1.254.2.19 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
210 1.53 augustss
211 1.254.2.19 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
212 1.254.2.19 skrll Static void ohci_noop(struct usbd_pipe *);
213 1.37 augustss
214 1.52 augustss #ifdef OHCI_DEBUG
215 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
216 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
217 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
218 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
219 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
220 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
221 1.1 augustss #endif
222 1.1 augustss
223 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
224 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
225 1.88 augustss #define OWRITE1(sc, r, x) \
226 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
227 1.88 augustss #define OWRITE2(sc, r, x) \
228 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
229 1.88 augustss #define OWRITE4(sc, r, x) \
230 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
231 1.174 mrg
232 1.174 mrg static __inline uint32_t
233 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
234 1.174 mrg {
235 1.174 mrg
236 1.174 mrg OBARR(sc);
237 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
238 1.174 mrg }
239 1.1 augustss
240 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
241 1.254.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
242 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
243 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
244 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
245 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
246 1.1 augustss
247 1.1 augustss struct ohci_pipe {
248 1.1 augustss struct usbd_pipe pipe;
249 1.1 augustss ohci_soft_ed_t *sed;
250 1.60 augustss union {
251 1.60 augustss ohci_soft_td_t *td;
252 1.60 augustss ohci_soft_itd_t *itd;
253 1.60 augustss } tail;
254 1.1 augustss /* Info needed for different pipe kinds. */
255 1.1 augustss union {
256 1.1 augustss /* Control pipe */
257 1.1 augustss struct {
258 1.4 augustss usb_dma_t reqdma;
259 1.1 augustss u_int length;
260 1.48 augustss ohci_soft_td_t *setup, *data, *stat;
261 1.254.2.21 skrll } ctrl;
262 1.1 augustss /* Interrupt pipe */
263 1.1 augustss struct {
264 1.1 augustss int nslots;
265 1.1 augustss int pos;
266 1.1 augustss } intr;
267 1.3 augustss /* Bulk pipe */
268 1.3 augustss struct {
269 1.3 augustss u_int length;
270 1.32 augustss int isread;
271 1.3 augustss } bulk;
272 1.254.2.21 skrll /* Isochronous pipe */
273 1.254.2.21 skrll struct isoc {
274 1.60 augustss int next, inuse;
275 1.254.2.21 skrll } isoc;
276 1.254.2.21 skrll };
277 1.1 augustss };
278 1.1 augustss
279 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
280 1.254.2.5 skrll .ubm_open = ohci_open,
281 1.254.2.5 skrll .ubm_softint = ohci_softintr,
282 1.254.2.5 skrll .ubm_dopoll = ohci_poll,
283 1.254.2.5 skrll .ubm_allocx = ohci_allocx,
284 1.254.2.5 skrll .ubm_freex = ohci_freex,
285 1.254.2.5 skrll .ubm_getlock = ohci_get_lock,
286 1.254.2.12 skrll .ubm_rhctrl = ohci_roothub_ctrl,
287 1.1 augustss };
288 1.1 augustss
289 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
290 1.254.2.5 skrll .upm_transfer = ohci_root_intr_transfer,
291 1.254.2.5 skrll .upm_start = ohci_root_intr_start,
292 1.254.2.5 skrll .upm_abort = ohci_root_intr_abort,
293 1.254.2.5 skrll .upm_close = ohci_root_intr_close,
294 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
295 1.254.2.5 skrll .upm_done = ohci_root_intr_done,
296 1.1 augustss };
297 1.1 augustss
298 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
299 1.254.2.5 skrll .upm_transfer = ohci_device_ctrl_transfer,
300 1.254.2.5 skrll .upm_start = ohci_device_ctrl_start,
301 1.254.2.5 skrll .upm_abort = ohci_device_ctrl_abort,
302 1.254.2.5 skrll .upm_close = ohci_device_ctrl_close,
303 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
304 1.254.2.5 skrll .upm_done = ohci_device_ctrl_done,
305 1.1 augustss };
306 1.1 augustss
307 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
308 1.254.2.5 skrll .upm_transfer = ohci_device_intr_transfer,
309 1.254.2.5 skrll .upm_start = ohci_device_intr_start,
310 1.254.2.5 skrll .upm_abort = ohci_device_intr_abort,
311 1.254.2.5 skrll .upm_close = ohci_device_intr_close,
312 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
313 1.254.2.5 skrll .upm_done = ohci_device_intr_done,
314 1.1 augustss };
315 1.1 augustss
316 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
317 1.254.2.5 skrll .upm_transfer = ohci_device_bulk_transfer,
318 1.254.2.5 skrll .upm_start = ohci_device_bulk_start,
319 1.254.2.5 skrll .upm_abort = ohci_device_bulk_abort,
320 1.254.2.5 skrll .upm_close = ohci_device_bulk_close,
321 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
322 1.254.2.5 skrll .upm_done = ohci_device_bulk_done,
323 1.3 augustss };
324 1.3 augustss
325 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
326 1.254.2.5 skrll .upm_transfer = ohci_device_isoc_transfer,
327 1.254.2.5 skrll .upm_start = ohci_device_isoc_start,
328 1.254.2.5 skrll .upm_abort = ohci_device_isoc_abort,
329 1.254.2.5 skrll .upm_close = ohci_device_isoc_close,
330 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
331 1.254.2.5 skrll .upm_done = ohci_device_isoc_done,
332 1.43 augustss };
333 1.43 augustss
334 1.47 augustss int
335 1.189 dyoung ohci_activate(device_t self, enum devact act)
336 1.47 augustss {
337 1.189 dyoung struct ohci_softc *sc = device_private(self);
338 1.47 augustss
339 1.47 augustss switch (act) {
340 1.47 augustss case DVACT_DEACTIVATE:
341 1.183 kiyohara sc->sc_dying = 1;
342 1.203 dyoung return 0;
343 1.203 dyoung default:
344 1.203 dyoung return EOPNOTSUPP;
345 1.47 augustss }
346 1.47 augustss }
347 1.47 augustss
348 1.187 dyoung void
349 1.187 dyoung ohci_childdet(device_t self, device_t child)
350 1.187 dyoung {
351 1.187 dyoung struct ohci_softc *sc = device_private(self);
352 1.187 dyoung
353 1.187 dyoung KASSERT(sc->sc_child == child);
354 1.187 dyoung sc->sc_child = NULL;
355 1.187 dyoung }
356 1.187 dyoung
357 1.47 augustss int
358 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
359 1.47 augustss {
360 1.47 augustss int rv = 0;
361 1.47 augustss
362 1.47 augustss if (sc->sc_child != NULL)
363 1.47 augustss rv = config_detach(sc->sc_child, flags);
364 1.120 augustss
365 1.47 augustss if (rv != 0)
366 1.254.2.13 skrll return rv;
367 1.47 augustss
368 1.254 ozaki callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
369 1.104 augustss
370 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
371 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
372 1.116 augustss
373 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
374 1.224 mrg
375 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
376 1.224 mrg
377 1.224 mrg mutex_destroy(&sc->sc_lock);
378 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
379 1.224 mrg
380 1.198 cegger if (sc->sc_hcca != NULL)
381 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
382 1.232 christos pool_cache_destroy(sc->sc_xferpool);
383 1.47 augustss
384 1.254.2.13 skrll return rv;
385 1.47 augustss }
386 1.47 augustss
387 1.1 augustss ohci_soft_ed_t *
388 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
389 1.1 augustss {
390 1.1 augustss ohci_soft_ed_t *sed;
391 1.53 augustss usbd_status err;
392 1.1 augustss int i, offs;
393 1.4 augustss usb_dma_t dma;
394 1.1 augustss
395 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
396 1.254.2.18 skrll
397 1.53 augustss if (sc->sc_freeeds == NULL) {
398 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
399 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
400 1.53 augustss OHCI_ED_ALIGN, &dma);
401 1.53 augustss if (err)
402 1.254.2.13 skrll return 0;
403 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
404 1.39 augustss offs = i * OHCI_SED_SIZE;
405 1.123 augustss sed = KERNADDR(&dma, offs);
406 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
407 1.195 bouyer sed->dma = dma;
408 1.195 bouyer sed->offs = offs;
409 1.1 augustss sed->next = sc->sc_freeeds;
410 1.1 augustss sc->sc_freeeds = sed;
411 1.1 augustss }
412 1.1 augustss }
413 1.1 augustss sed = sc->sc_freeeds;
414 1.1 augustss sc->sc_freeeds = sed->next;
415 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
416 1.1 augustss sed->next = 0;
417 1.254.2.13 skrll return sed;
418 1.1 augustss }
419 1.1 augustss
420 1.1 augustss void
421 1.91 augustss ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
422 1.1 augustss {
423 1.1 augustss sed->next = sc->sc_freeeds;
424 1.1 augustss sc->sc_freeeds = sed;
425 1.1 augustss }
426 1.1 augustss
427 1.1 augustss ohci_soft_td_t *
428 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
429 1.1 augustss {
430 1.1 augustss ohci_soft_td_t *std;
431 1.53 augustss usbd_status err;
432 1.1 augustss int i, offs;
433 1.4 augustss usb_dma_t dma;
434 1.1 augustss
435 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
436 1.254.2.18 skrll
437 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
438 1.240 skrll
439 1.53 augustss if (sc->sc_freetds == NULL) {
440 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
441 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
442 1.53 augustss OHCI_TD_ALIGN, &dma);
443 1.53 augustss if (err)
444 1.254.2.13 skrll return NULL;
445 1.39 augustss for(i = 0; i < OHCI_STD_CHUNK; i++) {
446 1.39 augustss offs = i * OHCI_STD_SIZE;
447 1.123 augustss std = KERNADDR(&dma, offs);
448 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
449 1.195 bouyer std->dma = dma;
450 1.195 bouyer std->offs = offs;
451 1.1 augustss std->nexttd = sc->sc_freetds;
452 1.1 augustss sc->sc_freetds = std;
453 1.1 augustss }
454 1.1 augustss }
455 1.69 augustss
456 1.1 augustss std = sc->sc_freetds;
457 1.1 augustss sc->sc_freetds = std->nexttd;
458 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
459 1.83 augustss std->nexttd = NULL;
460 1.83 augustss std->xfer = NULL;
461 1.69 augustss ohci_hash_add_td(sc, std);
462 1.69 augustss
463 1.254.2.13 skrll return std;
464 1.1 augustss }
465 1.1 augustss
466 1.1 augustss void
467 1.91 augustss ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
468 1.1 augustss {
469 1.254.2.7 skrll
470 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
471 1.254.2.1 skrll
472 1.69 augustss ohci_hash_rem_td(sc, std);
473 1.1 augustss std->nexttd = sc->sc_freetds;
474 1.1 augustss sc->sc_freetds = std;
475 1.1 augustss }
476 1.1 augustss
477 1.1 augustss usbd_status
478 1.91 augustss ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc,
479 1.254.2.19 skrll int alen, int rd, struct usbd_xfer *xfer,
480 1.91 augustss ohci_soft_td_t *sp, ohci_soft_td_t **ep)
481 1.48 augustss {
482 1.48 augustss ohci_soft_td_t *next, *cur;
483 1.48 augustss ohci_physaddr_t dataphys, dataphysend;
484 1.254.2.1 skrll uint32_t tdflags;
485 1.75 augustss int len, curlen;
486 1.254.2.7 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
487 1.254.2.7 skrll uint16_t flags = xfer->ux_flags;
488 1.48 augustss
489 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
490 1.254.2.18 skrll DPRINTF("start len=%d", alen, 0, 0, 0);
491 1.75 augustss
492 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
493 1.224 mrg
494 1.254.2.18 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
495 1.254.2.18 skrll opipe->pipe.up_dev->ud_addr,
496 1.254.2.18 skrll UE_GET_ADDR(opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress),
497 1.254.2.18 skrll alen, opipe->pipe.up_dev->ud_speed);
498 1.254.2.18 skrll
499 1.75 augustss len = alen;
500 1.48 augustss cur = sp;
501 1.125 augustss dataphys = DMAADDR(dma, 0);
502 1.48 augustss dataphysend = OHCI_PAGE(dataphys + len - 1);
503 1.195 bouyer usb_syncmem(dma, 0, len,
504 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
505 1.168 augustss tdflags = HTOO32(
506 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
507 1.77 augustss (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) |
508 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
509 1.61 augustss
510 1.48 augustss for (;;) {
511 1.48 augustss next = ohci_alloc_std(sc);
512 1.75 augustss if (next == NULL)
513 1.61 augustss goto nomem;
514 1.48 augustss
515 1.48 augustss /* The OHCI hardware can handle at most one page crossing. */
516 1.48 augustss if (OHCI_PAGE(dataphys) == dataphysend ||
517 1.48 augustss OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
518 1.48 augustss /* we can handle it in this TD */
519 1.48 augustss curlen = len;
520 1.48 augustss } else {
521 1.48 augustss /* must use multiple TDs, fill as much as possible. */
522 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
523 1.48 augustss (dataphys & (OHCI_PAGE_SIZE-1));
524 1.78 augustss /* the length must be a multiple of the max size */
525 1.254.2.7 skrll curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize);
526 1.254.2.24 skrll KASSERT(curlen != 0);
527 1.48 augustss }
528 1.254.2.18 skrll DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x "
529 1.254.2.18 skrll "len=%d curlen=%d", dataphys, dataphysend, len, curlen);
530 1.48 augustss len -= curlen;
531 1.48 augustss
532 1.77 augustss cur->td.td_flags = tdflags;
533 1.168 augustss cur->td.td_cbp = HTOO32(dataphys);
534 1.48 augustss cur->nexttd = next;
535 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
536 1.168 augustss cur->td.td_be = HTOO32(dataphys + curlen - 1);
537 1.48 augustss cur->len = curlen;
538 1.48 augustss cur->flags = OHCI_ADD_LEN;
539 1.77 augustss cur->xfer = xfer;
540 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
541 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
542 1.254.2.18 skrll DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys,
543 1.254.2.18 skrll dataphys + curlen - 1, 0, 0);
544 1.48 augustss if (len == 0)
545 1.48 augustss break;
546 1.254.2.18 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
547 1.48 augustss dataphys += curlen;
548 1.48 augustss cur = next;
549 1.48 augustss }
550 1.164 augustss if (!rd && (flags & USBD_FORCE_SHORT_XFER) &&
551 1.254.2.7 skrll alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) {
552 1.61 augustss /* Force a 0 length transfer at the end. */
553 1.75 augustss
554 1.75 augustss cur = next;
555 1.61 augustss next = ohci_alloc_std(sc);
556 1.75 augustss if (next == NULL)
557 1.61 augustss goto nomem;
558 1.61 augustss
559 1.77 augustss cur->td.td_flags = tdflags;
560 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
561 1.61 augustss cur->nexttd = next;
562 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
563 1.75 augustss cur->td.td_be = ~0;
564 1.61 augustss cur->len = 0;
565 1.61 augustss cur->flags = 0;
566 1.77 augustss cur->xfer = xfer;
567 1.195 bouyer usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
568 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
569 1.254.2.18 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
570 1.61 augustss }
571 1.77 augustss *ep = cur;
572 1.48 augustss
573 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
574 1.61 augustss
575 1.61 augustss nomem:
576 1.236 skrll
577 1.236 skrll /* Don't free sp - let the caller do that */
578 1.236 skrll ohci_free_std_chain(sc, sp->nexttd, NULL);
579 1.236 skrll
580 1.254.2.13 skrll return USBD_NOMEM;
581 1.48 augustss }
582 1.48 augustss
583 1.82 augustss Static void
584 1.120 augustss ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std,
585 1.91 augustss ohci_soft_td_t *stdend)
586 1.48 augustss {
587 1.48 augustss ohci_soft_td_t *p;
588 1.48 augustss
589 1.48 augustss for (; std != stdend; std = p) {
590 1.48 augustss p = std->nexttd;
591 1.48 augustss ohci_free_std(sc, std);
592 1.48 augustss }
593 1.48 augustss }
594 1.48 augustss
595 1.60 augustss ohci_soft_itd_t *
596 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
597 1.60 augustss {
598 1.60 augustss ohci_soft_itd_t *sitd;
599 1.60 augustss usbd_status err;
600 1.224 mrg int i, offs;
601 1.60 augustss usb_dma_t dma;
602 1.60 augustss
603 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
604 1.254.2.18 skrll
605 1.60 augustss if (sc->sc_freeitds == NULL) {
606 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
607 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
608 1.83 augustss OHCI_ITD_ALIGN, &dma);
609 1.60 augustss if (err)
610 1.254.2.13 skrll return NULL;
611 1.83 augustss for(i = 0; i < OHCI_SITD_CHUNK; i++) {
612 1.83 augustss offs = i * OHCI_SITD_SIZE;
613 1.123 augustss sitd = KERNADDR(&dma, offs);
614 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
615 1.195 bouyer sitd->dma = dma;
616 1.195 bouyer sitd->offs = offs;
617 1.60 augustss sitd->nextitd = sc->sc_freeitds;
618 1.60 augustss sc->sc_freeitds = sitd;
619 1.60 augustss }
620 1.60 augustss }
621 1.83 augustss
622 1.60 augustss sitd = sc->sc_freeitds;
623 1.60 augustss sc->sc_freeitds = sitd->nextitd;
624 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
625 1.83 augustss sitd->nextitd = NULL;
626 1.83 augustss sitd->xfer = NULL;
627 1.83 augustss ohci_hash_add_itd(sc, sitd);
628 1.83 augustss
629 1.83 augustss #ifdef DIAGNOSTIC
630 1.83 augustss sitd->isdone = 0;
631 1.83 augustss #endif
632 1.83 augustss
633 1.254.2.13 skrll return sitd;
634 1.60 augustss }
635 1.60 augustss
636 1.60 augustss void
637 1.91 augustss ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
638 1.60 augustss {
639 1.83 augustss
640 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
641 1.254.2.18 skrll DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
642 1.83 augustss
643 1.254.2.24 skrll KASSERT(sitd->isdone);
644 1.83 augustss #ifdef DIAGNOSTIC
645 1.134 toshii /* Warn double free */
646 1.134 toshii sitd->isdone = 0;
647 1.83 augustss #endif
648 1.83 augustss
649 1.83 augustss ohci_hash_rem_itd(sc, sitd);
650 1.60 augustss sitd->nextitd = sc->sc_freeitds;
651 1.60 augustss sc->sc_freeitds = sitd;
652 1.60 augustss }
653 1.60 augustss
654 1.254.2.14 skrll int
655 1.91 augustss ohci_init(ohci_softc_t *sc)
656 1.1 augustss {
657 1.1 augustss ohci_soft_ed_t *sed, *psed;
658 1.53 augustss usbd_status err;
659 1.1 augustss int i;
660 1.254.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
661 1.16 augustss
662 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
663 1.254.2.18 skrll
664 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
665 1.199 jmcneill
666 1.198 cegger sc->sc_hcca = NULL;
667 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
668 1.224 mrg
669 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
670 1.254.2.22 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
671 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
672 1.224 mrg
673 1.224 mrg sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
674 1.224 mrg ohci_rhsc_softint, sc);
675 1.198 cegger
676 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
677 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
678 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
679 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
680 1.198 cegger
681 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
682 1.232 christos "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
683 1.198 cegger
684 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
685 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
686 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
687 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
688 1.55 augustss
689 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
690 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
691 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
692 1.254.2.14 skrll return -1;
693 1.1 augustss }
694 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_1_0;
695 1.254.2.7 skrll sc->sc_bus.ub_usedma = true;
696 1.153 fvdl
697 1.73 augustss /* XXX determine alignment by R/W */
698 1.1 augustss /* Allocate the HCCA area. */
699 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
700 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
701 1.198 cegger if (err) {
702 1.198 cegger sc->sc_hcca = NULL;
703 1.198 cegger return err;
704 1.198 cegger }
705 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
706 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
707 1.1 augustss
708 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
709 1.1 augustss
710 1.60 augustss /* Allocate dummy ED that starts the control list. */
711 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
712 1.53 augustss if (sc->sc_ctrl_head == NULL) {
713 1.254.2.14 skrll err = ENOMEM;
714 1.1 augustss goto bad1;
715 1.1 augustss }
716 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
717 1.34 augustss
718 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
719 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
720 1.53 augustss if (sc->sc_bulk_head == NULL) {
721 1.254.2.14 skrll err = ENOMEM;
722 1.1 augustss goto bad2;
723 1.1 augustss }
724 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
725 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
726 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
727 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
728 1.1 augustss
729 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
730 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
731 1.60 augustss if (sc->sc_isoc_head == NULL) {
732 1.254.2.14 skrll err = ENOMEM;
733 1.60 augustss goto bad3;
734 1.60 augustss }
735 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
736 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
737 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
738 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
739 1.60 augustss
740 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
741 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
742 1.1 augustss sed = ohci_alloc_sed(sc);
743 1.53 augustss if (sed == NULL) {
744 1.1 augustss while (--i >= 0)
745 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
746 1.254.2.14 skrll err = ENOMEM;
747 1.60 augustss goto bad4;
748 1.1 augustss }
749 1.1 augustss /* All ED fields are set to 0. */
750 1.1 augustss sc->sc_eds[i] = sed;
751 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
752 1.60 augustss if (i != 0)
753 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
754 1.60 augustss else
755 1.60 augustss psed= sc->sc_isoc_head;
756 1.60 augustss sed->next = psed;
757 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
758 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
759 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
760 1.1 augustss }
761 1.120 augustss /*
762 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
763 1.1 augustss * the tree set up properly to spread the interrupts.
764 1.1 augustss */
765 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
766 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
767 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
768 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
769 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
770 1.1 augustss
771 1.73 augustss #ifdef OHCI_DEBUG
772 1.254.2.18 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
773 1.73 augustss if (ohcidebug > 15) {
774 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
775 1.254.2.18 skrll DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
776 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
777 1.73 augustss }
778 1.254.2.18 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
779 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
780 1.73 augustss }
781 1.254.2.18 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
782 1.73 augustss #endif
783 1.73 augustss
784 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
785 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
786 1.161 augustss rwc = ctl & OHCI_RWC;
787 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
788 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
789 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
790 1.161 augustss
791 1.1 augustss /* Determine in what context we are running. */
792 1.1 augustss if (ctl & OHCI_IR) {
793 1.1 augustss /* SMM active, request change */
794 1.254.2.18 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
795 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
796 1.160 augustss (OHCI_OC | OHCI_MIE))
797 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
798 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
799 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
800 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
801 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
802 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
803 1.1 augustss }
804 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
805 1.1 augustss if ((ctl & OHCI_IR) == 0) {
806 1.199 jmcneill aprint_error_dev(sc->sc_dev,
807 1.199 jmcneill "SMM does not respond, resetting\n");
808 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
809 1.1 augustss goto reset;
810 1.1 augustss }
811 1.103 augustss #if 0
812 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
813 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
814 1.1 augustss /* BIOS started controller. */
815 1.254.2.18 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
816 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
817 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
818 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
819 1.1 augustss }
820 1.103 augustss #endif
821 1.1 augustss } else {
822 1.254.2.18 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
823 1.1 augustss reset:
824 1.1 augustss /* Controller was cold started. */
825 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
826 1.1 augustss }
827 1.1 augustss
828 1.16 augustss /*
829 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
830 1.25 augustss * without it some controllers do not start.
831 1.16 augustss */
832 1.254.2.18 skrll DPRINTF("sc %p: resetting", sc, 0, 0, 0);
833 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
834 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
835 1.16 augustss
836 1.1 augustss /* We now own the host controller and the bus has been reset. */
837 1.1 augustss
838 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
839 1.1 augustss /* Nominal time for a reset is 10 us. */
840 1.1 augustss for (i = 0; i < 10; i++) {
841 1.1 augustss delay(10);
842 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
843 1.1 augustss if (!hcr)
844 1.1 augustss break;
845 1.1 augustss }
846 1.1 augustss if (hcr) {
847 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
848 1.254.2.14 skrll err = EIO;
849 1.60 augustss goto bad5;
850 1.1 augustss }
851 1.52 augustss #ifdef OHCI_DEBUG
852 1.1 augustss if (ohcidebug > 15)
853 1.1 augustss ohci_dumpregs(sc);
854 1.1 augustss #endif
855 1.1 augustss
856 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
857 1.1 augustss
858 1.1 augustss /* Set up HC registers. */
859 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
860 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
861 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
862 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
863 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
864 1.55 augustss /* switch on desired functional features */
865 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
866 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
867 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
868 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
869 1.1 augustss /* And finally start it! */
870 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
871 1.1 augustss
872 1.1 augustss /*
873 1.1 augustss * The controller is now OPERATIONAL. Set a some final
874 1.1 augustss * registers that should be set earlier, but that the
875 1.1 augustss * controller ignores when in the SUSPEND state.
876 1.1 augustss */
877 1.161 augustss ival = OHCI_GET_IVAL(fm);
878 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
879 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
880 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
881 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
882 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
883 1.1 augustss
884 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
885 1.249 skrll /* no overcurrent protection */
886 1.249 skrll desca |= OHCI_NOCP;
887 1.249 skrll /*
888 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
889 1.249 skrll * that
890 1.249 skrll * - ports are always power switched
891 1.249 skrll * - don't wait for powered root hub port
892 1.249 skrll */
893 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
894 1.249 skrll }
895 1.249 skrll
896 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
897 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
898 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
899 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
900 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
901 1.1 augustss
902 1.85 augustss /*
903 1.85 augustss * The AMD756 requires a delay before re-reading the register,
904 1.85 augustss * otherwise it will occasionally report 0 ports.
905 1.85 augustss */
906 1.145 augustss sc->sc_noport = 0;
907 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
908 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
909 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
910 1.145 augustss }
911 1.1 augustss
912 1.52 augustss #ifdef OHCI_DEBUG
913 1.1 augustss if (ohcidebug > 5)
914 1.1 augustss ohci_dumpregs(sc);
915 1.1 augustss #endif
916 1.120 augustss
917 1.1 augustss /* Set up the bus struct. */
918 1.254.2.7 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
919 1.254.2.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
920 1.1 augustss
921 1.101 minoura sc->sc_control = sc->sc_intre = 0;
922 1.59 augustss
923 1.167 augustss /* Finally, turn on interrupts. */
924 1.254.2.18 skrll DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
925 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
926 1.167 augustss
927 1.254.2.14 skrll return 0;
928 1.1 augustss
929 1.60 augustss bad5:
930 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
931 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
932 1.60 augustss bad4:
933 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
934 1.1 augustss bad3:
935 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
936 1.144 augustss bad2:
937 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
938 1.1 augustss bad1:
939 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
940 1.198 cegger sc->sc_hcca = NULL;
941 1.254.2.13 skrll return err;
942 1.1 augustss }
943 1.1 augustss
944 1.254.2.19 skrll struct usbd_xfer *
945 1.254.2.23 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
946 1.62 augustss {
947 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
948 1.254.2.19 skrll struct usbd_xfer *xfer;
949 1.62 augustss
950 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
951 1.118 augustss if (xfer != NULL) {
952 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
953 1.118 augustss #ifdef DIAGNOSTIC
954 1.254.2.7 skrll xfer->ux_state = XFER_BUSY;
955 1.118 augustss #endif
956 1.118 augustss }
957 1.254.2.13 skrll return xfer;
958 1.62 augustss }
959 1.62 augustss
960 1.62 augustss void
961 1.254.2.19 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
962 1.62 augustss {
963 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
964 1.62 augustss
965 1.254.2.24 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
966 1.254.2.24 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
967 1.118 augustss #ifdef DIAGNOSTIC
968 1.254.2.7 skrll xfer->ux_state = XFER_FREE;
969 1.118 augustss #endif
970 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
971 1.42 augustss }
972 1.42 augustss
973 1.224 mrg Static void
974 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
975 1.224 mrg {
976 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
977 1.224 mrg
978 1.224 mrg *lock = &sc->sc_lock;
979 1.224 mrg }
980 1.224 mrg
981 1.59 augustss /*
982 1.59 augustss * Shut down the controller when the system is going down.
983 1.59 augustss */
984 1.188 dyoung bool
985 1.188 dyoung ohci_shutdown(device_t self, int flags)
986 1.59 augustss {
987 1.188 dyoung ohci_softc_t *sc = device_private(self);
988 1.59 augustss
989 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
990 1.254.2.18 skrll
991 1.254.2.18 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
992 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
993 1.188 dyoung return true;
994 1.59 augustss }
995 1.59 augustss
996 1.185 jmcneill bool
997 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
998 1.33 augustss {
999 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1000 1.185 jmcneill uint32_t ctl;
1001 1.33 augustss
1002 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1003 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1004 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1005 1.224 mrg
1006 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1007 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1008 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1009 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1010 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1011 1.185 jmcneill sc->sc_bulk_head->physaddr);
1012 1.185 jmcneill if (sc->sc_intre)
1013 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1014 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1015 1.185 jmcneill if (sc->sc_control)
1016 1.185 jmcneill ctl = sc->sc_control;
1017 1.185 jmcneill else
1018 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1019 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1020 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1021 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1022 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1023 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1024 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1025 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1026 1.224 mrg
1027 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1028 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1029 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1030 1.185 jmcneill
1031 1.185 jmcneill return true;
1032 1.185 jmcneill }
1033 1.185 jmcneill
1034 1.185 jmcneill bool
1035 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1036 1.185 jmcneill {
1037 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1038 1.185 jmcneill uint32_t ctl;
1039 1.95 augustss
1040 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1041 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1042 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1043 1.224 mrg
1044 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1045 1.185 jmcneill if (sc->sc_control == 0) {
1046 1.185 jmcneill /*
1047 1.185 jmcneill * Preserve register values, in case that BIOS
1048 1.185 jmcneill * does not recover them.
1049 1.185 jmcneill */
1050 1.185 jmcneill sc->sc_control = ctl;
1051 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1052 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1053 1.95 augustss }
1054 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1055 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1056 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1057 1.224 mrg
1058 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1059 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1060 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1061 1.185 jmcneill
1062 1.185 jmcneill return true;
1063 1.33 augustss }
1064 1.33 augustss
1065 1.52 augustss #ifdef OHCI_DEBUG
1066 1.1 augustss void
1067 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1068 1.1 augustss {
1069 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1070 1.254.2.18 skrll
1071 1.254.2.18 skrll DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
1072 1.41 augustss OREAD4(sc, OHCI_REVISION),
1073 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1074 1.254.2.18 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1075 1.254.2.18 skrll DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x",
1076 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1077 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1078 1.254.2.18 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1079 1.254.2.18 skrll DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
1080 1.41 augustss OREAD4(sc, OHCI_HCCA),
1081 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1082 1.254.2.18 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1083 1.254.2.18 skrll DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
1084 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1085 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1086 1.254.2.18 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1087 1.254.2.18 skrll DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x",
1088 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1089 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1090 1.254.2.18 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1091 1.254.2.18 skrll DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
1092 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1093 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1094 1.254.2.18 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1095 1.254.2.18 skrll DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x",
1096 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1097 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1098 1.254.2.18 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1099 1.254.2.18 skrll DPRINTF(" port1=0x%08x port2=0x%08x",
1100 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1101 1.254.2.18 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1102 1.254.2.18 skrll DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x",
1103 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1104 1.254.2.18 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1105 1.1 augustss }
1106 1.1 augustss #endif
1107 1.1 augustss
1108 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1109 1.53 augustss
1110 1.1 augustss int
1111 1.91 augustss ohci_intr(void *p)
1112 1.1 augustss {
1113 1.1 augustss ohci_softc_t *sc = p;
1114 1.224 mrg int ret = 0;
1115 1.111 augustss
1116 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1117 1.254.2.18 skrll
1118 1.224 mrg if (sc == NULL)
1119 1.254.2.13 skrll return 0;
1120 1.53 augustss
1121 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1122 1.224 mrg
1123 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1124 1.224 mrg goto done;
1125 1.224 mrg
1126 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1127 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling) {
1128 1.254.2.18 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1129 1.154 joff /* for level triggered intrs, should do something to ack */
1130 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1131 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1132 1.155 perry
1133 1.224 mrg goto done;
1134 1.57 augustss }
1135 1.53 augustss
1136 1.224 mrg ret = ohci_intr1(sc);
1137 1.224 mrg
1138 1.224 mrg done:
1139 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1140 1.224 mrg return ret;
1141 1.53 augustss }
1142 1.53 augustss
1143 1.82 augustss Static int
1144 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1145 1.53 augustss {
1146 1.254.2.1 skrll uint32_t intrs, eintrs;
1147 1.1 augustss
1148 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1149 1.105 augustss
1150 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1151 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1152 1.15 augustss #ifdef DIAGNOSTIC
1153 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1154 1.15 augustss #endif
1155 1.254.2.13 skrll return 0;
1156 1.15 augustss }
1157 1.15 augustss
1158 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1159 1.224 mrg
1160 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1161 1.1 augustss if (!intrs)
1162 1.254.2.13 skrll return 0;
1163 1.55 augustss
1164 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */
1165 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1166 1.254.2.18 skrll DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
1167 1.254.2.18 skrll DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
1168 1.254.2.18 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1169 1.254.2.18 skrll sc->sc_eintrs);
1170 1.211 matt
1171 1.211 matt if (!eintrs) {
1172 1.254.2.13 skrll return 0;
1173 1.211 matt }
1174 1.1 augustss
1175 1.1 augustss if (eintrs & OHCI_SO) {
1176 1.100 augustss sc->sc_overrun_cnt++;
1177 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1178 1.100 augustss printf("%s: %u scheduling overruns\n",
1179 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1180 1.100 augustss sc->sc_overrun_cnt = 0;
1181 1.100 augustss }
1182 1.1 augustss /* XXX do what */
1183 1.106 augustss eintrs &= ~OHCI_SO;
1184 1.1 augustss }
1185 1.1 augustss if (eintrs & OHCI_WDH) {
1186 1.157 mycroft /*
1187 1.157 mycroft * We block the interrupt below, and reenable it later from
1188 1.157 mycroft * ohci_softintr().
1189 1.157 mycroft */
1190 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1191 1.1 augustss }
1192 1.1 augustss if (eintrs & OHCI_RD) {
1193 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1194 1.1 augustss /* XXX process resume detect */
1195 1.1 augustss }
1196 1.1 augustss if (eintrs & OHCI_UE) {
1197 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1198 1.190 drochner device_xname(sc->sc_dev));
1199 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1200 1.1 augustss /* XXX what else */
1201 1.1 augustss }
1202 1.1 augustss if (eintrs & OHCI_RHSC) {
1203 1.120 augustss /*
1204 1.157 mycroft * We block the interrupt below, and reenable it later from
1205 1.157 mycroft * a timeout.
1206 1.1 augustss */
1207 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1208 1.1 augustss }
1209 1.1 augustss
1210 1.106 augustss if (eintrs != 0) {
1211 1.157 mycroft /* Block unprocessed interrupts. */
1212 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1213 1.106 augustss sc->sc_eintrs &= ~eintrs;
1214 1.254.2.18 skrll DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0);
1215 1.106 augustss }
1216 1.1 augustss
1217 1.254.2.13 skrll return 1;
1218 1.1 augustss }
1219 1.1 augustss
1220 1.1 augustss void
1221 1.104 augustss ohci_rhsc_enable(void *v_sc)
1222 1.104 augustss {
1223 1.104 augustss ohci_softc_t *sc = v_sc;
1224 1.104 augustss
1225 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1226 1.254.2.18 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1227 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1228 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1229 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1230 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1231 1.1 augustss }
1232 1.1 augustss
1233 1.52 augustss #ifdef OHCI_DEBUG
1234 1.166 drochner const char *ohci_cc_strs[] = {
1235 1.13 augustss "NO_ERROR",
1236 1.13 augustss "CRC",
1237 1.13 augustss "BIT_STUFFING",
1238 1.13 augustss "DATA_TOGGLE_MISMATCH",
1239 1.13 augustss "STALL",
1240 1.13 augustss "DEVICE_NOT_RESPONDING",
1241 1.13 augustss "PID_CHECK_FAILURE",
1242 1.13 augustss "UNEXPECTED_PID",
1243 1.13 augustss "DATA_OVERRUN",
1244 1.13 augustss "DATA_UNDERRUN",
1245 1.13 augustss "BUFFER_OVERRUN",
1246 1.13 augustss "BUFFER_UNDERRUN",
1247 1.67 augustss "reserved",
1248 1.67 augustss "reserved",
1249 1.67 augustss "NOT_ACCESSED",
1250 1.13 augustss "NOT_ACCESSED",
1251 1.13 augustss };
1252 1.13 augustss #endif
1253 1.13 augustss
1254 1.1 augustss void
1255 1.157 mycroft ohci_softintr(void *v)
1256 1.83 augustss {
1257 1.190 drochner struct usbd_bus *bus = v;
1258 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1259 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1260 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1261 1.254.2.19 skrll struct usbd_xfer *xfer;
1262 1.157 mycroft struct ohci_pipe *opipe;
1263 1.224 mrg int len, cc;
1264 1.157 mycroft int i, j, actlen, iframes, uedir;
1265 1.157 mycroft ohci_physaddr_t done;
1266 1.157 mycroft
1267 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1268 1.224 mrg
1269 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1270 1.157 mycroft
1271 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1272 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1273 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1274 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1275 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1276 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1277 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1278 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1279 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1280 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1281 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1282 1.83 augustss
1283 1.83 augustss /* Reverse the done list. */
1284 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1285 1.83 augustss std = ohci_hash_find_td(sc, done);
1286 1.83 augustss if (std != NULL) {
1287 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1288 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1289 1.83 augustss std->dnext = sdone;
1290 1.168 augustss done = O32TOH(std->td.td_nexttd);
1291 1.83 augustss sdone = std;
1292 1.254.2.18 skrll DPRINTFN(10, "add TD %p", std, 0, 0, 0);
1293 1.83 augustss continue;
1294 1.83 augustss }
1295 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1296 1.83 augustss if (sitd != NULL) {
1297 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1298 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1299 1.83 augustss sitd->dnext = sidone;
1300 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1301 1.83 augustss sidone = sitd;
1302 1.254.2.18 skrll DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
1303 1.83 augustss continue;
1304 1.83 augustss }
1305 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1306 1.218 jmcneill (u_long)done);
1307 1.218 jmcneill break;
1308 1.83 augustss }
1309 1.83 augustss
1310 1.254.2.18 skrll DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
1311 1.254.2.18 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
1312 1.52 augustss #ifdef OHCI_DEBUG
1313 1.1 augustss if (ohcidebug > 10) {
1314 1.234 skrll for (std = sdone; std; std = std->dnext)
1315 1.254.2.1 skrll ohci_dump_td(sc, std);
1316 1.1 augustss }
1317 1.1 augustss #endif
1318 1.254.2.18 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
1319 1.1 augustss
1320 1.48 augustss for (std = sdone; std; std = stdnext) {
1321 1.53 augustss xfer = std->xfer;
1322 1.48 augustss stdnext = std->dnext;
1323 1.254.2.18 skrll DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer,
1324 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1325 1.71 augustss if (xfer == NULL) {
1326 1.117 augustss /*
1327 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1328 1.71 augustss * with this TD. It is tailp that happened to end up on
1329 1.71 augustss * the done queue.
1330 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1331 1.71 augustss */
1332 1.71 augustss continue;
1333 1.71 augustss }
1334 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1335 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1336 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1337 1.38 augustss /* Handled by abort routine. */
1338 1.83 augustss continue;
1339 1.83 augustss }
1340 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
1341 1.141 mycroft
1342 1.141 mycroft len = std->len;
1343 1.141 mycroft if (std->td.td_cbp != 0)
1344 1.168 augustss len -= O32TOH(std->td.td_be) -
1345 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1346 1.254.2.18 skrll DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
1347 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1348 1.254.2.7 skrll xfer->ux_actlen += len;
1349 1.141 mycroft
1350 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1351 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1352 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1353 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1354 1.53 augustss usb_transfer_complete(xfer);
1355 1.21 augustss }
1356 1.48 augustss ohci_free_std(sc, std);
1357 1.1 augustss } else {
1358 1.48 augustss /*
1359 1.48 augustss * Endpoint is halted. First unlink all the TDs
1360 1.48 augustss * belonging to the failed transfer, and then restart
1361 1.48 augustss * the endpoint.
1362 1.48 augustss */
1363 1.1 augustss ohci_soft_td_t *p, *n;
1364 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1365 1.48 augustss
1366 1.254.2.18 skrll DPRINTFN(15, "error cc=%d",
1367 1.254.2.18 skrll OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0);
1368 1.48 augustss
1369 1.48 augustss /* remove TDs */
1370 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1371 1.1 augustss n = p->nexttd;
1372 1.1 augustss ohci_free_std(sc, p);
1373 1.1 augustss }
1374 1.48 augustss
1375 1.16 augustss /* clear halt */
1376 1.168 augustss opipe->sed->ed.ed_headp = HTOO32(p->physaddr);
1377 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1378 1.48 augustss
1379 1.1 augustss if (cc == OHCI_CC_STALL)
1380 1.254.2.7 skrll xfer->ux_status = USBD_STALLED;
1381 1.1 augustss else
1382 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1383 1.53 augustss usb_transfer_complete(xfer);
1384 1.1 augustss }
1385 1.1 augustss }
1386 1.254.2.18 skrll DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0);
1387 1.83 augustss #ifdef OHCI_DEBUG
1388 1.83 augustss if (ohcidebug > 10) {
1389 1.254.2.18 skrll DPRINTFN(10, "ITD done", 0, 0, 0, 0);
1390 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1391 1.254.2.1 skrll ohci_dump_itd(sc, sitd);
1392 1.83 augustss }
1393 1.83 augustss #endif
1394 1.254.2.18 skrll DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0);
1395 1.83 augustss
1396 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1397 1.83 augustss xfer = sitd->xfer;
1398 1.83 augustss sitdnext = sitd->dnext;
1399 1.254.2.18 skrll DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
1400 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1401 1.83 augustss if (xfer == NULL)
1402 1.83 augustss continue;
1403 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1404 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1405 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1406 1.83 augustss /* Handled by abort routine. */
1407 1.83 augustss continue;
1408 1.83 augustss }
1409 1.254.2.24 skrll KASSERT(!sitd->isdone);
1410 1.83 augustss #ifdef DIAGNOSTIC
1411 1.83 augustss sitd->isdone = 1;
1412 1.83 augustss #endif
1413 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1414 1.134 toshii ohci_soft_itd_t *next;
1415 1.134 toshii
1416 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1417 1.254.2.21 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1418 1.254.2.7 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1419 1.134 toshii bEndpointAddress);
1420 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1421 1.134 toshii actlen = 0;
1422 1.254.2.7 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1423 1.134 toshii sitd = next) {
1424 1.134 toshii next = sitd->nextitd;
1425 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1426 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1427 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1428 1.134 toshii /* For input, update frlengths with actual */
1429 1.134 toshii /* XXX anything necessary for output? */
1430 1.134 toshii if (uedir == UE_DIR_IN &&
1431 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1432 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1433 1.135 toshii sitd->itd.itd_flags));
1434 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1435 1.168 augustss len = O16TOH(sitd->
1436 1.134 toshii itd.itd_offset[j]);
1437 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1438 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1439 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1440 1.158 toshii len = 0;
1441 1.158 toshii else
1442 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1443 1.254.2.7 skrll xfer->ux_frlengths[i] = len;
1444 1.134 toshii actlen += len;
1445 1.134 toshii }
1446 1.134 toshii }
1447 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1448 1.134 toshii break;
1449 1.134 toshii ohci_free_sitd(sc, sitd);
1450 1.83 augustss }
1451 1.134 toshii ohci_free_sitd(sc, sitd);
1452 1.134 toshii if (uedir == UE_DIR_IN &&
1453 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1454 1.254.2.7 skrll xfer->ux_actlen = actlen;
1455 1.254.2.7 skrll xfer->ux_hcpriv = NULL;
1456 1.134 toshii
1457 1.83 augustss usb_transfer_complete(xfer);
1458 1.83 augustss }
1459 1.83 augustss }
1460 1.83 augustss
1461 1.119 augustss if (sc->sc_softwake) {
1462 1.119 augustss sc->sc_softwake = 0;
1463 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1464 1.119 augustss }
1465 1.119 augustss
1466 1.254.2.18 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1467 1.1 augustss }
1468 1.1 augustss
1469 1.1 augustss void
1470 1.254.2.19 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1471 1.1 augustss {
1472 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1473 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1474 1.254.2.7 skrll int len = UGETW(xfer->ux_request.wLength);
1475 1.254.2.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1476 1.195 bouyer
1477 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1478 1.254.2.18 skrll DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
1479 1.1 augustss
1480 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1481 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1482 1.224 mrg
1483 1.195 bouyer if (len)
1484 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1485 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1486 1.254.2.21 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1487 1.195 bouyer sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1488 1.1 augustss }
1489 1.1 augustss
1490 1.1 augustss void
1491 1.254.2.19 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1492 1.1 augustss {
1493 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1494 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1495 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
1496 1.48 augustss ohci_soft_td_t *data, *tail;
1497 1.195 bouyer int isread =
1498 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1499 1.1 augustss
1500 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1501 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1502 1.1 augustss
1503 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1504 1.224 mrg
1505 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1506 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1507 1.254.2.7 skrll if (xfer->ux_pipe->up_repeat) {
1508 1.60 augustss data = opipe->tail.td;
1509 1.1 augustss tail = ohci_alloc_std(sc); /* XXX should reuse TD */
1510 1.53 augustss if (tail == NULL) {
1511 1.254.2.7 skrll xfer->ux_status = USBD_NOMEM;
1512 1.1 augustss return;
1513 1.1 augustss }
1514 1.55 augustss tail->xfer = NULL;
1515 1.120 augustss
1516 1.168 augustss data->td.td_flags = HTOO32(
1517 1.120 augustss OHCI_TD_IN | OHCI_TD_NOCC |
1518 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
1519 1.254.2.7 skrll if (xfer->ux_flags & USBD_SHORT_XFER_OK)
1520 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
1521 1.254.2.7 skrll data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0));
1522 1.48 augustss data->nexttd = tail;
1523 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
1524 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) +
1525 1.254.2.7 skrll xfer->ux_length - 1);
1526 1.254.2.7 skrll data->len = xfer->ux_length;
1527 1.53 augustss data->xfer = xfer;
1528 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
1529 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
1530 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1531 1.254.2.7 skrll xfer->ux_hcpriv = data;
1532 1.254.2.7 skrll xfer->ux_actlen = 0;
1533 1.1 augustss
1534 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
1535 1.195 bouyer usb_syncmem(&sed->dma,
1536 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_tailp),
1537 1.195 bouyer sizeof(sed->ed.ed_tailp),
1538 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1539 1.60 augustss opipe->tail.td = tail;
1540 1.1 augustss }
1541 1.1 augustss }
1542 1.1 augustss
1543 1.1 augustss void
1544 1.254.2.19 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1545 1.3 augustss {
1546 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1547 1.254.2.25 skrll
1548 1.195 bouyer int isread =
1549 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1550 1.195 bouyer
1551 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1552 1.224 mrg
1553 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1554 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1555 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1556 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1557 1.3 augustss }
1558 1.3 augustss
1559 1.224 mrg Static void
1560 1.224 mrg ohci_rhsc_softint(void *arg)
1561 1.224 mrg {
1562 1.224 mrg ohci_softc_t *sc = arg;
1563 1.224 mrg
1564 1.224 mrg mutex_enter(&sc->sc_lock);
1565 1.224 mrg
1566 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1567 1.224 mrg
1568 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1569 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1570 1.224 mrg
1571 1.224 mrg mutex_exit(&sc->sc_lock);
1572 1.224 mrg }
1573 1.224 mrg
1574 1.3 augustss void
1575 1.254.2.19 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1576 1.1 augustss {
1577 1.1 augustss u_char *p;
1578 1.1 augustss int i, m;
1579 1.243 martin int hstatus __unused;
1580 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1581 1.1 augustss
1582 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1583 1.224 mrg
1584 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1585 1.254.2.18 skrll DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0);
1586 1.1 augustss
1587 1.53 augustss if (xfer == NULL) {
1588 1.1 augustss /* Just ignore the change. */
1589 1.1 augustss return;
1590 1.1 augustss }
1591 1.1 augustss
1592 1.254.2.7 skrll p = xfer->ux_buf;
1593 1.254.2.7 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1594 1.254.2.7 skrll memset(p, 0, xfer->ux_length);
1595 1.1 augustss for (i = 1; i <= m; i++) {
1596 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1597 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1598 1.1 augustss p[i/8] |= 1 << (i%8);
1599 1.1 augustss }
1600 1.254.2.18 skrll DPRINTF("change=0x%02x", *p, 0, 0, 0);
1601 1.254.2.7 skrll xfer->ux_actlen = xfer->ux_length;
1602 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1603 1.1 augustss
1604 1.53 augustss usb_transfer_complete(xfer);
1605 1.38 augustss }
1606 1.38 augustss
1607 1.38 augustss void
1608 1.254.2.19 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1609 1.65 augustss {
1610 1.65 augustss }
1611 1.65 augustss
1612 1.1 augustss /*
1613 1.1 augustss * Wait here until controller claims to have an interrupt.
1614 1.1 augustss * Then call ohci_intr and return. Use timeout to avoid waiting
1615 1.1 augustss * too long.
1616 1.1 augustss */
1617 1.1 augustss void
1618 1.254.2.19 skrll ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer)
1619 1.1 augustss {
1620 1.163 augustss int timo;
1621 1.254.2.1 skrll uint32_t intrs;
1622 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1623 1.1 augustss
1624 1.224 mrg mutex_enter(&sc->sc_lock);
1625 1.224 mrg
1626 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1627 1.254.2.7 skrll for (timo = xfer->ux_timeout; timo >= 0; timo--) {
1628 1.20 augustss usb_delay_ms(&sc->sc_bus, 1);
1629 1.116 augustss if (sc->sc_dying)
1630 1.116 augustss break;
1631 1.1 augustss intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
1632 1.254.2.18 skrll DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0);
1633 1.52 augustss #ifdef OHCI_DEBUG
1634 1.1 augustss if (ohcidebug > 15)
1635 1.1 augustss ohci_dumpregs(sc);
1636 1.1 augustss #endif
1637 1.1 augustss if (intrs) {
1638 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1639 1.53 augustss ohci_intr1(sc);
1640 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1641 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1642 1.230 jmcneill goto done;
1643 1.1 augustss }
1644 1.1 augustss }
1645 1.15 augustss
1646 1.15 augustss /* Timeout */
1647 1.254.2.18 skrll DPRINTF("timeout", 0, 0, 0, 0);
1648 1.254.2.7 skrll xfer->ux_status = USBD_TIMEOUT;
1649 1.53 augustss usb_transfer_complete(xfer);
1650 1.224 mrg
1651 1.15 augustss /* XXX should free TD */
1652 1.224 mrg
1653 1.230 jmcneill done:
1654 1.224 mrg mutex_exit(&sc->sc_lock);
1655 1.5 augustss }
1656 1.5 augustss
1657 1.5 augustss void
1658 1.91 augustss ohci_poll(struct usbd_bus *bus)
1659 1.5 augustss {
1660 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1661 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1662 1.254.2.18 skrll
1663 1.105 augustss #ifdef OHCI_DEBUG
1664 1.105 augustss static int last;
1665 1.105 augustss int new;
1666 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1667 1.105 augustss if (new != last) {
1668 1.254.2.18 skrll DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0);
1669 1.105 augustss last = new;
1670 1.105 augustss }
1671 1.105 augustss #endif
1672 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1673 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1674 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1675 1.53 augustss ohci_intr1(sc);
1676 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1677 1.224 mrg }
1678 1.1 augustss }
1679 1.1 augustss
1680 1.1 augustss /*
1681 1.224 mrg * Add an ED to the schedule. Called with USB lock held.
1682 1.1 augustss */
1683 1.224 mrg Static void
1684 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1685 1.1 augustss {
1686 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1687 1.254.2.18 skrll DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0);
1688 1.113 augustss
1689 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1690 1.224 mrg
1691 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1692 1.195 bouyer sizeof(head->ed.ed_nexted),
1693 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1694 1.1 augustss sed->next = head->next;
1695 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1696 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1697 1.195 bouyer sizeof(sed->ed.ed_nexted),
1698 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1699 1.1 augustss head->next = sed;
1700 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1701 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1702 1.195 bouyer sizeof(head->ed.ed_nexted),
1703 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1704 1.1 augustss }
1705 1.1 augustss
1706 1.1 augustss /*
1707 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1708 1.3 augustss */
1709 1.224 mrg Static void
1710 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1711 1.3 augustss {
1712 1.120 augustss ohci_soft_ed_t *p;
1713 1.3 augustss
1714 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1715 1.224 mrg
1716 1.3 augustss /* XXX */
1717 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1718 1.3 augustss ;
1719 1.254.2.20 skrll KASSERT(p != NULL);
1720 1.254.2.20 skrll
1721 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1722 1.195 bouyer sizeof(sed->ed.ed_nexted),
1723 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1724 1.3 augustss p->next = sed->next;
1725 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1726 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1727 1.195 bouyer sizeof(p->ed.ed_nexted),
1728 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1729 1.3 augustss }
1730 1.3 augustss
1731 1.3 augustss /*
1732 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1733 1.1 augustss * the host controller. This queue is the processed by software.
1734 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1735 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1736 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1737 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1738 1.1 augustss * hash value.
1739 1.1 augustss */
1740 1.1 augustss
1741 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1742 1.224 mrg /* Called with USB lock held. */
1743 1.1 augustss void
1744 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1745 1.1 augustss {
1746 1.1 augustss int h = HASH(std->physaddr);
1747 1.1 augustss
1748 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1749 1.224 mrg
1750 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1751 1.1 augustss }
1752 1.1 augustss
1753 1.224 mrg /* Called with USB lock held. */
1754 1.1 augustss void
1755 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1756 1.1 augustss {
1757 1.46 augustss
1758 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1759 1.224 mrg
1760 1.1 augustss LIST_REMOVE(std, hnext);
1761 1.1 augustss }
1762 1.1 augustss
1763 1.1 augustss ohci_soft_td_t *
1764 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1765 1.1 augustss {
1766 1.1 augustss int h = HASH(a);
1767 1.1 augustss ohci_soft_td_t *std;
1768 1.1 augustss
1769 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1770 1.53 augustss std != NULL;
1771 1.1 augustss std = LIST_NEXT(std, hnext))
1772 1.1 augustss if (std->physaddr == a)
1773 1.254.2.13 skrll return std;
1774 1.254.2.13 skrll return NULL;
1775 1.83 augustss }
1776 1.83 augustss
1777 1.224 mrg /* Called with USB lock held. */
1778 1.83 augustss void
1779 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1780 1.83 augustss {
1781 1.83 augustss int h = HASH(sitd->physaddr);
1782 1.83 augustss
1783 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1784 1.254.2.18 skrll
1785 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1786 1.224 mrg
1787 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1788 1.254.2.18 skrll 0, 0);
1789 1.83 augustss
1790 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1791 1.83 augustss }
1792 1.83 augustss
1793 1.224 mrg /* Called with USB lock held. */
1794 1.83 augustss void
1795 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1796 1.83 augustss {
1797 1.83 augustss
1798 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1799 1.254.2.18 skrll
1800 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1801 1.224 mrg
1802 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1803 1.254.2.18 skrll 0, 0);
1804 1.83 augustss
1805 1.83 augustss LIST_REMOVE(sitd, hnext);
1806 1.83 augustss }
1807 1.83 augustss
1808 1.83 augustss ohci_soft_itd_t *
1809 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1810 1.83 augustss {
1811 1.83 augustss int h = HASH(a);
1812 1.83 augustss ohci_soft_itd_t *sitd;
1813 1.83 augustss
1814 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1815 1.83 augustss sitd != NULL;
1816 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1817 1.83 augustss if (sitd->physaddr == a)
1818 1.254.2.13 skrll return sitd;
1819 1.254.2.13 skrll return NULL;
1820 1.1 augustss }
1821 1.1 augustss
1822 1.1 augustss void
1823 1.91 augustss ohci_timeout(void *addr)
1824 1.1 augustss {
1825 1.254.2.25 skrll struct usbd_xfer *xfer = addr;
1826 1.254.2.25 skrll struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer);
1827 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1828 1.114 augustss
1829 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1830 1.254.2.18 skrll DPRINTF("oxfer=%p", oxfer, 0, 0, 0);
1831 1.114 augustss
1832 1.116 augustss if (sc->sc_dying) {
1833 1.224 mrg mutex_enter(&sc->sc_lock);
1834 1.254.2.25 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1835 1.224 mrg mutex_exit(&sc->sc_lock);
1836 1.116 augustss return;
1837 1.116 augustss }
1838 1.116 augustss
1839 1.114 augustss /* Execute the abort in a process context. */
1840 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1841 1.231 jmcneill USB_TASKQ_MPSAFE);
1842 1.254.2.25 skrll usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task,
1843 1.178 joerg USB_TASKQ_HC);
1844 1.114 augustss }
1845 1.114 augustss
1846 1.114 augustss void
1847 1.114 augustss ohci_timeout_task(void *addr)
1848 1.114 augustss {
1849 1.254.2.19 skrll struct usbd_xfer *xfer = addr;
1850 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1851 1.1 augustss
1852 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1853 1.254.2.18 skrll
1854 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1855 1.45 augustss
1856 1.224 mrg mutex_enter(&sc->sc_lock);
1857 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1858 1.224 mrg mutex_exit(&sc->sc_lock);
1859 1.1 augustss }
1860 1.1 augustss
1861 1.52 augustss #ifdef OHCI_DEBUG
1862 1.1 augustss void
1863 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1864 1.1 augustss {
1865 1.1 augustss for (; std; std = std->nexttd)
1866 1.168 augustss ohci_dump_td(sc, std);
1867 1.1 augustss }
1868 1.1 augustss
1869 1.1 augustss void
1870 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1871 1.1 augustss {
1872 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1873 1.92 tv
1874 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1875 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1876 1.254.2.18 skrll
1877 1.254.2.18 skrll uint32_t flags = O32TOH(std->td.td_flags);
1878 1.254.2.18 skrll DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0);
1879 1.254.2.18 skrll DPRINTF(" round=%d DP=%x DI=%x T=%x",
1880 1.254.2.18 skrll !!(flags & OHCI_TD_R),
1881 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1882 1.254.2.18 skrll OHCI_TD_GET_DI(flags),
1883 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1884 1.254.2.18 skrll DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags),
1885 1.254.2.18 skrll 0, 0);
1886 1.254.2.18 skrll DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx",
1887 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1888 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1889 1.254.2.18 skrll (u_long)O32TOH(std->td.td_be), 0);
1890 1.1 augustss }
1891 1.1 augustss
1892 1.1 augustss void
1893 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1894 1.83 augustss {
1895 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1896 1.83 augustss
1897 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1898 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1899 1.254.2.18 skrll
1900 1.254.2.18 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
1901 1.254.2.18 skrll DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0);
1902 1.254.2.18 skrll DPRINTF(" sf=%d di=%d fc=%d cc=%d",
1903 1.254.2.18 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
1904 1.254.2.18 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
1905 1.254.2.18 skrll DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x",
1906 1.254.2.18 skrll O32TOH(sitd->itd.itd_bp0),
1907 1.254.2.18 skrll O32TOH(sitd->itd.itd_nextitd),
1908 1.254.2.18 skrll O32TOH(sitd->itd.itd_be), 0);
1909 1.254.2.18 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
1910 1.254.2.18 skrll DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x "
1911 1.254.2.18 skrll "offs[2] = 0x%04x offs[3] = 0x%04x",
1912 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[0]),
1913 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[1]),
1914 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[2]),
1915 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[3]));
1916 1.254.2.18 skrll DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x "
1917 1.254.2.18 skrll "offs[6] = 0x%04x offs[7] = 0x%04x",
1918 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[4]),
1919 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[5]),
1920 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[6]),
1921 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[7]));
1922 1.83 augustss }
1923 1.83 augustss
1924 1.83 augustss void
1925 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1926 1.83 augustss {
1927 1.83 augustss for (; sitd; sitd = sitd->nextitd)
1928 1.168 augustss ohci_dump_itd(sc, sitd);
1929 1.83 augustss }
1930 1.83 augustss
1931 1.83 augustss void
1932 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
1933 1.1 augustss {
1934 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1935 1.92 tv
1936 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
1937 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1938 1.254.2.18 skrll
1939 1.254.2.18 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
1940 1.254.2.18 skrll DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0);
1941 1.254.2.18 skrll DPRINTF(" addr=%d endpt=%d maxp=%d",
1942 1.254.2.18 skrll OHCI_ED_GET_FA(flags),
1943 1.254.2.18 skrll OHCI_ED_GET_EN(flags),
1944 1.254.2.18 skrll OHCI_ED_GET_MAXP(flags),
1945 1.254.2.18 skrll 0);
1946 1.254.2.18 skrll DPRINTF(" dir=%d speed=%d skip=%d iso=%d",
1947 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
1948 1.254.2.18 skrll !!(flags & OHCI_ED_SPEED),
1949 1.254.2.18 skrll !!(flags & OHCI_ED_SKIP),
1950 1.254.2.18 skrll !!(flags & OHCI_ED_FORMAT_ISO));
1951 1.254.2.18 skrll DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp),
1952 1.254.2.18 skrll 0, 0, 0);
1953 1.254.2.18 skrll DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d",
1954 1.254.2.18 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
1955 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
1956 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
1957 1.1 augustss }
1958 1.1 augustss #endif
1959 1.1 augustss
1960 1.1 augustss usbd_status
1961 1.254.2.19 skrll ohci_open(struct usbd_pipe *pipe)
1962 1.1 augustss {
1963 1.254.2.19 skrll struct usbd_device *dev = pipe->up_dev;
1964 1.254.2.12 skrll struct usbd_bus *bus = dev->ud_bus;
1965 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
1966 1.254.2.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
1967 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
1968 1.254.2.7 skrll uint8_t addr = dev->ud_addr;
1969 1.254.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1970 1.1 augustss ohci_soft_ed_t *sed;
1971 1.1 augustss ohci_soft_td_t *std;
1972 1.60 augustss ohci_soft_itd_t *sitd;
1973 1.60 augustss ohci_physaddr_t tdphys;
1974 1.254.2.1 skrll uint32_t fmt;
1975 1.224 mrg usbd_status err = USBD_NOMEM;
1976 1.64 augustss int ival;
1977 1.1 augustss
1978 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1979 1.254.2.18 skrll DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr,
1980 1.254.2.18 skrll ed->bEndpointAddress, bus->ub_rhaddr);
1981 1.81 augustss
1982 1.224 mrg if (sc->sc_dying) {
1983 1.241 skrll return USBD_IOERROR;
1984 1.224 mrg }
1985 1.116 augustss
1986 1.90 thorpej std = NULL;
1987 1.90 thorpej sed = NULL;
1988 1.90 thorpej
1989 1.254.2.12 skrll if (addr == bus->ub_rhaddr) {
1990 1.1 augustss switch (ed->bEndpointAddress) {
1991 1.1 augustss case USB_CONTROL_ENDPOINT:
1992 1.254.2.12 skrll pipe->up_methods = &roothub_ctrl_methods;
1993 1.1 augustss break;
1994 1.254.2.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
1995 1.254.2.7 skrll pipe->up_methods = &ohci_root_intr_methods;
1996 1.1 augustss break;
1997 1.1 augustss default:
1998 1.224 mrg err = USBD_INVAL;
1999 1.241 skrll goto bad;
2000 1.1 augustss }
2001 1.1 augustss } else {
2002 1.1 augustss sed = ohci_alloc_sed(sc);
2003 1.53 augustss if (sed == NULL)
2004 1.241 skrll goto bad;
2005 1.1 augustss opipe->sed = sed;
2006 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2007 1.224 mrg mutex_enter(&sc->sc_lock);
2008 1.60 augustss sitd = ohci_alloc_sitd(sc);
2009 1.224 mrg mutex_exit(&sc->sc_lock);
2010 1.127 augustss if (sitd == NULL)
2011 1.241 skrll goto bad;
2012 1.241 skrll
2013 1.60 augustss opipe->tail.itd = sitd;
2014 1.76 tsutsui tdphys = sitd->physaddr;
2015 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2016 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2017 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2018 1.83 augustss else
2019 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2020 1.60 augustss } else {
2021 1.224 mrg mutex_enter(&sc->sc_lock);
2022 1.60 augustss std = ohci_alloc_std(sc);
2023 1.224 mrg mutex_exit(&sc->sc_lock);
2024 1.127 augustss if (std == NULL)
2025 1.241 skrll goto bad;
2026 1.241 skrll
2027 1.60 augustss opipe->tail.td = std;
2028 1.76 tsutsui tdphys = std->physaddr;
2029 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2030 1.60 augustss }
2031 1.168 augustss sed->ed.ed_flags = HTOO32(
2032 1.120 augustss OHCI_ED_SET_FA(addr) |
2033 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2034 1.254.2.7 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2035 1.109 augustss fmt |
2036 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2037 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2038 1.254.2.7 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2039 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2040 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2041 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2042 1.1 augustss
2043 1.60 augustss switch (xfertype) {
2044 1.1 augustss case UE_CONTROL:
2045 1.254.2.7 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2046 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2047 1.120 augustss sizeof(usb_device_request_t),
2048 1.254.2.21 skrll 0, &opipe->ctrl.reqdma);
2049 1.53 augustss if (err)
2050 1.1 augustss goto bad;
2051 1.224 mrg mutex_enter(&sc->sc_lock);
2052 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2053 1.224 mrg mutex_exit(&sc->sc_lock);
2054 1.1 augustss break;
2055 1.1 augustss case UE_INTERRUPT:
2056 1.254.2.7 skrll pipe->up_methods = &ohci_device_intr_methods;
2057 1.254.2.7 skrll ival = pipe->up_interval;
2058 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2059 1.64 augustss ival = ed->bInterval;
2060 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2061 1.226 skrll if (err)
2062 1.226 skrll goto bad;
2063 1.226 skrll break;
2064 1.1 augustss case UE_ISOCHRONOUS:
2065 1.254.2.7 skrll pipe->up_methods = &ohci_device_isoc_methods;
2066 1.254.2.13 skrll return ohci_setup_isoc(pipe);
2067 1.1 augustss case UE_BULK:
2068 1.254.2.7 skrll pipe->up_methods = &ohci_device_bulk_methods;
2069 1.224 mrg mutex_enter(&sc->sc_lock);
2070 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2071 1.224 mrg mutex_exit(&sc->sc_lock);
2072 1.3 augustss break;
2073 1.1 augustss }
2074 1.1 augustss }
2075 1.224 mrg
2076 1.224 mrg return USBD_NORMAL_COMPLETION;
2077 1.1 augustss
2078 1.1 augustss bad:
2079 1.241 skrll if (std != NULL) {
2080 1.241 skrll mutex_enter(&sc->sc_lock);
2081 1.90 thorpej ohci_free_std(sc, std);
2082 1.241 skrll mutex_exit(&sc->sc_lock);
2083 1.241 skrll }
2084 1.90 thorpej if (sed != NULL)
2085 1.90 thorpej ohci_free_sed(sc, sed);
2086 1.224 mrg return err;
2087 1.120 augustss
2088 1.1 augustss }
2089 1.1 augustss
2090 1.1 augustss /*
2091 1.34 augustss * Close a reqular pipe.
2092 1.34 augustss * Assumes that there are no pending transactions.
2093 1.34 augustss */
2094 1.34 augustss void
2095 1.254.2.19 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2096 1.34 augustss {
2097 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2098 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2099 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2100 1.34 augustss
2101 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2102 1.224 mrg
2103 1.34 augustss #ifdef DIAGNOSTIC
2104 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2105 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2106 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2107 1.34 augustss ohci_soft_td_t *std;
2108 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2109 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2110 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2111 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2112 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2113 1.34 augustss pipe, std);
2114 1.229 christos #ifdef OHCI_DEBUG
2115 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2116 1.168 augustss ohci_dump_ed(sc, sed);
2117 1.106 augustss if (std)
2118 1.168 augustss ohci_dump_td(sc, std);
2119 1.106 augustss #endif
2120 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2121 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2122 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2123 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2124 1.34 augustss }
2125 1.34 augustss #endif
2126 1.224 mrg ohci_rem_ed(sc, sed, head);
2127 1.133 toshii /* Make sure the host controller is not touching this ED */
2128 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2129 1.254.2.7 skrll pipe->up_endpoint->ue_toggle =
2130 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2131 1.34 augustss ohci_free_sed(sc, opipe->sed);
2132 1.34 augustss }
2133 1.34 augustss
2134 1.120 augustss /*
2135 1.34 augustss * Abort a device request.
2136 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2137 1.34 augustss * will be removed from the hardware scheduling and that the callback
2138 1.34 augustss * for it will be called with USBD_CANCELLED status.
2139 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2140 1.34 augustss * have happened since the hardware runs concurrently.
2141 1.34 augustss * If the transaction has already happened we rely on the ordinary
2142 1.34 augustss * interrupt processing to process it.
2143 1.224 mrg * XXX This is most probably wrong.
2144 1.224 mrg * XXXMRG this doesn't make sense anymore.
2145 1.34 augustss */
2146 1.34 augustss void
2147 1.254.2.19 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2148 1.34 augustss {
2149 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2150 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2151 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2152 1.106 augustss ohci_soft_td_t *p, *n;
2153 1.106 augustss ohci_physaddr_t headp;
2154 1.224 mrg int hit;
2155 1.159 augustss int wake;
2156 1.34 augustss
2157 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2158 1.254.2.18 skrll DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0);
2159 1.34 augustss
2160 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2161 1.254.2.3 skrll ASSERT_SLEEPABLE();
2162 1.224 mrg
2163 1.116 augustss if (sc->sc_dying) {
2164 1.116 augustss /* If we're dying, just do the software part. */
2165 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2166 1.254.2.7 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2167 1.116 augustss usb_transfer_complete(xfer);
2168 1.170 christos return;
2169 1.116 augustss }
2170 1.116 augustss
2171 1.106 augustss /*
2172 1.159 augustss * If an abort is already in progress then just wait for it to
2173 1.159 augustss * complete and return.
2174 1.159 augustss */
2175 1.254.2.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2176 1.254.2.18 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2177 1.159 augustss #ifdef DIAGNOSTIC
2178 1.159 augustss if (status == USBD_TIMEOUT)
2179 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2180 1.159 augustss #endif
2181 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2182 1.254.2.7 skrll xfer->ux_status = status;
2183 1.254.2.18 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2184 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2185 1.254.2.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2186 1.254.2.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2187 1.224 mrg goto done;
2188 1.159 augustss }
2189 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2190 1.159 augustss
2191 1.159 augustss /*
2192 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2193 1.106 augustss */
2194 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2195 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
2196 1.254.2.18 skrll DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0);
2197 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2198 1.195 bouyer sizeof(sed->ed.ed_flags),
2199 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2200 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2201 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2202 1.195 bouyer sizeof(sed->ed.ed_flags),
2203 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2204 1.34 augustss
2205 1.120 augustss /*
2206 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2207 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2208 1.106 augustss * has run.
2209 1.106 augustss */
2210 1.224 mrg /* Hardware finishes in 1ms */
2211 1.254.2.7 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2212 1.119 augustss sc->sc_softwake = 1;
2213 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2214 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2215 1.119 augustss
2216 1.120 augustss /*
2217 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2218 1.106 augustss * The complication here is that the hardware may have executed
2219 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2220 1.106 augustss * the TDs of this xfer we check if the hardware points to
2221 1.106 augustss * any of them.
2222 1.106 augustss */
2223 1.254.2.7 skrll p = xfer->ux_hcpriv;
2224 1.254.2.24 skrll KASSERT(p);
2225 1.254.2.24 skrll
2226 1.106 augustss #ifdef OHCI_DEBUG
2227 1.254.2.18 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2228 1.254.2.18 skrll
2229 1.106 augustss if (ohcidebug > 1) {
2230 1.254.2.18 skrll DPRINTF("sed:", 0, 0, 0, 0);
2231 1.168 augustss ohci_dump_ed(sc, sed);
2232 1.168 augustss ohci_dump_tds(sc, p);
2233 1.106 augustss }
2234 1.254.2.18 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2235 1.106 augustss #endif
2236 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2237 1.106 augustss hit = 0;
2238 1.53 augustss for (; p->xfer == xfer; p = n) {
2239 1.106 augustss hit |= headp == p->physaddr;
2240 1.38 augustss n = p->nexttd;
2241 1.38 augustss ohci_free_std(sc, p);
2242 1.34 augustss }
2243 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2244 1.106 augustss if (hit) {
2245 1.254.2.18 skrll DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr,
2246 1.254.2.18 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2247 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2248 1.195 bouyer usb_syncmem(&sed->dma,
2249 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2250 1.195 bouyer sizeof(sed->ed.ed_headp),
2251 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2252 1.106 augustss } else {
2253 1.254.2.18 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2254 1.106 augustss }
2255 1.34 augustss
2256 1.106 augustss /*
2257 1.106 augustss * Step 4: Turn on hardware again.
2258 1.106 augustss */
2259 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2260 1.195 bouyer sizeof(sed->ed.ed_flags),
2261 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2262 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2263 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2264 1.195 bouyer sizeof(sed->ed.ed_flags),
2265 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2266 1.38 augustss
2267 1.106 augustss /*
2268 1.106 augustss * Step 5: Execute callback.
2269 1.106 augustss */
2270 1.254.2.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2271 1.254.2.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2272 1.53 augustss usb_transfer_complete(xfer);
2273 1.159 augustss if (wake)
2274 1.254.2.7 skrll cv_broadcast(&xfer->ux_hccv);
2275 1.38 augustss
2276 1.224 mrg done:
2277 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2278 1.34 augustss }
2279 1.34 augustss
2280 1.34 augustss /*
2281 1.1 augustss * Data structures and routines to emulate the root hub.
2282 1.1 augustss */
2283 1.254.2.12 skrll Static int
2284 1.254.2.12 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2285 1.254.2.12 skrll void *buf, int buflen)
2286 1.17 augustss {
2287 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2288 1.1 augustss usb_port_status_t ps;
2289 1.254.2.12 skrll uint16_t len, value, index;
2290 1.254.2.12 skrll int l, totlen = 0;
2291 1.254.2.12 skrll int port, i;
2292 1.254.2.1 skrll uint32_t v;
2293 1.1 augustss
2294 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2295 1.254.2.18 skrll
2296 1.83 augustss if (sc->sc_dying)
2297 1.254.2.12 skrll return -1;
2298 1.1 augustss
2299 1.254.2.18 skrll DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType,
2300 1.254.2.18 skrll req->bRequest, 0, 0);
2301 1.1 augustss
2302 1.1 augustss len = UGETW(req->wLength);
2303 1.1 augustss value = UGETW(req->wValue);
2304 1.1 augustss index = UGETW(req->wIndex);
2305 1.43 augustss
2306 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2307 1.254.2.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
2308 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2309 1.254.2.18 skrll DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0);
2310 1.171 christos if (len == 0)
2311 1.171 christos break;
2312 1.254.2.12 skrll switch (value) {
2313 1.254.2.12 skrll case C(0, UDESC_DEVICE): {
2314 1.254.2.12 skrll usb_device_descriptor_t devd;
2315 1.254.2.12 skrll
2316 1.254.2.12 skrll totlen = min(buflen, sizeof(devd));
2317 1.254.2.12 skrll memcpy(&devd, buf, totlen);
2318 1.254.2.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2319 1.254.2.12 skrll memcpy(buf, &devd, totlen);
2320 1.1 augustss break;
2321 1.254.2.12 skrll }
2322 1.254.2.12 skrll case C(1, UDESC_STRING):
2323 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2324 1.254.2.12 skrll /* Vendor */
2325 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2326 1.254.2.12 skrll break;
2327 1.254.2.12 skrll case C(2, UDESC_STRING):
2328 1.254.2.12 skrll /* Product */
2329 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2330 1.1 augustss break;
2331 1.254.2.12 skrll #undef sd
2332 1.1 augustss default:
2333 1.254.2.12 skrll /* default from usbroothub */
2334 1.254.2.12 skrll return buflen;
2335 1.1 augustss }
2336 1.1 augustss break;
2337 1.254.2.12 skrll
2338 1.1 augustss /* Hub requests */
2339 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2340 1.1 augustss break;
2341 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2342 1.254.2.18 skrll DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2343 1.254.2.18 skrll index, value, 0, 0);
2344 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2345 1.254.2.12 skrll return -1;
2346 1.1 augustss }
2347 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2348 1.1 augustss switch(value) {
2349 1.1 augustss case UHF_PORT_ENABLE:
2350 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2351 1.1 augustss break;
2352 1.1 augustss case UHF_PORT_SUSPEND:
2353 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2354 1.1 augustss break;
2355 1.1 augustss case UHF_PORT_POWER:
2356 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2357 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2358 1.1 augustss break;
2359 1.1 augustss case UHF_C_PORT_CONNECTION:
2360 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2361 1.1 augustss break;
2362 1.1 augustss case UHF_C_PORT_ENABLE:
2363 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2364 1.1 augustss break;
2365 1.1 augustss case UHF_C_PORT_SUSPEND:
2366 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2367 1.1 augustss break;
2368 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2369 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2370 1.1 augustss break;
2371 1.1 augustss case UHF_C_PORT_RESET:
2372 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2373 1.1 augustss break;
2374 1.1 augustss default:
2375 1.254.2.12 skrll return -1;
2376 1.1 augustss }
2377 1.1 augustss switch(value) {
2378 1.1 augustss case UHF_C_PORT_CONNECTION:
2379 1.1 augustss case UHF_C_PORT_ENABLE:
2380 1.1 augustss case UHF_C_PORT_SUSPEND:
2381 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2382 1.1 augustss case UHF_C_PORT_RESET:
2383 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2384 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2385 1.157 mycroft ohci_rhsc_enable(sc);
2386 1.1 augustss break;
2387 1.1 augustss default:
2388 1.1 augustss break;
2389 1.1 augustss }
2390 1.1 augustss break;
2391 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2392 1.171 christos if (len == 0)
2393 1.171 christos break;
2394 1.146 toshii if ((value & 0xff) != 0) {
2395 1.254.2.12 skrll return -1;
2396 1.1 augustss }
2397 1.254.2.12 skrll usb_hub_descriptor_t hubd;
2398 1.254.2.12 skrll
2399 1.254.2.12 skrll totlen = min(buflen, sizeof(hubd));
2400 1.254.2.12 skrll memcpy(&hubd, buf, totlen);
2401 1.254.2.12 skrll
2402 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2403 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2404 1.15 augustss USETW(hubd.wHubCharacteristics,
2405 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2406 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2407 1.1 augustss /* XXX overcurrent */
2408 1.1 augustss );
2409 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2410 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2411 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2412 1.254.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2413 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2414 1.254.2.12 skrll totlen = min(totlen, hubd.bDescLength);
2415 1.254.2.12 skrll memcpy(buf, &hubd, totlen);
2416 1.1 augustss break;
2417 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2418 1.1 augustss if (len != 4) {
2419 1.254.2.12 skrll return -1;
2420 1.1 augustss }
2421 1.1 augustss memset(buf, 0, len); /* ? XXX */
2422 1.1 augustss totlen = len;
2423 1.1 augustss break;
2424 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2425 1.254.2.18 skrll DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
2426 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2427 1.254.2.12 skrll return -1;
2428 1.1 augustss }
2429 1.1 augustss if (len != 4) {
2430 1.254.2.12 skrll return -1;
2431 1.254.2.12 skrll }
2432 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2433 1.254.2.18 skrll DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0);
2434 1.1 augustss USETW(ps.wPortStatus, v);
2435 1.1 augustss USETW(ps.wPortChange, v >> 16);
2436 1.254.2.12 skrll totlen = min(len, sizeof(ps));
2437 1.254.2.12 skrll memcpy(buf, &ps, totlen);
2438 1.1 augustss break;
2439 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2440 1.254.2.12 skrll return -1;
2441 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2442 1.1 augustss break;
2443 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2444 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2445 1.254.2.12 skrll return -1;
2446 1.1 augustss }
2447 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2448 1.1 augustss switch(value) {
2449 1.1 augustss case UHF_PORT_ENABLE:
2450 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2451 1.1 augustss break;
2452 1.1 augustss case UHF_PORT_SUSPEND:
2453 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2454 1.1 augustss break;
2455 1.1 augustss case UHF_PORT_RESET:
2456 1.254.2.18 skrll DPRINTFN(5, "reset port %d", index, 0, 0, 0);
2457 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2458 1.110 augustss for (i = 0; i < 5; i++) {
2459 1.110 augustss usb_delay_ms(&sc->sc_bus,
2460 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2461 1.116 augustss if (sc->sc_dying) {
2462 1.254.2.12 skrll return -1;
2463 1.116 augustss }
2464 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2465 1.1 augustss break;
2466 1.1 augustss }
2467 1.254.2.18 skrll DPRINTFN(8, "port %d reset, status = 0x%04x", index,
2468 1.254.2.18 skrll OREAD4(sc, port), 0, 0);
2469 1.1 augustss break;
2470 1.1 augustss case UHF_PORT_POWER:
2471 1.254.2.18 skrll DPRINTFN(2, "set port power %d", index, 0, 0, 0);
2472 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2473 1.1 augustss break;
2474 1.1 augustss default:
2475 1.254.2.12 skrll return -1;
2476 1.1 augustss }
2477 1.1 augustss break;
2478 1.1 augustss default:
2479 1.254.2.12 skrll /* default from usbroothub */
2480 1.254.2.12 skrll return buflen;
2481 1.1 augustss }
2482 1.1 augustss
2483 1.254.2.12 skrll return totlen;
2484 1.1 augustss }
2485 1.1 augustss
2486 1.82 augustss Static usbd_status
2487 1.254.2.19 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2488 1.1 augustss {
2489 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2490 1.53 augustss usbd_status err;
2491 1.17 augustss
2492 1.46 augustss /* Insert last in queue. */
2493 1.224 mrg mutex_enter(&sc->sc_lock);
2494 1.53 augustss err = usb_insert_transfer(xfer);
2495 1.224 mrg mutex_exit(&sc->sc_lock);
2496 1.53 augustss if (err)
2497 1.254.2.13 skrll return err;
2498 1.46 augustss
2499 1.46 augustss /* Pipe isn't running, start first */
2500 1.254.2.13 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2501 1.17 augustss }
2502 1.17 augustss
2503 1.82 augustss Static usbd_status
2504 1.254.2.19 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2505 1.17 augustss {
2506 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2507 1.1 augustss
2508 1.83 augustss if (sc->sc_dying)
2509 1.254.2.13 skrll return USBD_IOERROR;
2510 1.83 augustss
2511 1.224 mrg mutex_enter(&sc->sc_lock);
2512 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2513 1.53 augustss sc->sc_intrxfer = xfer;
2514 1.224 mrg mutex_exit(&sc->sc_lock);
2515 1.1 augustss
2516 1.254.2.13 skrll return USBD_IN_PROGRESS;
2517 1.1 augustss }
2518 1.1 augustss
2519 1.3 augustss /* Abort a root interrupt request. */
2520 1.82 augustss Static void
2521 1.254.2.19 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2522 1.1 augustss {
2523 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2524 1.224 mrg
2525 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2526 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2527 1.53 augustss
2528 1.252 skrll sc->sc_intrxfer = NULL;
2529 1.252 skrll
2530 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
2531 1.53 augustss usb_transfer_complete(xfer);
2532 1.1 augustss }
2533 1.1 augustss
2534 1.1 augustss /* Close the root pipe. */
2535 1.82 augustss Static void
2536 1.254.2.19 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2537 1.1 augustss {
2538 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2539 1.120 augustss
2540 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2541 1.224 mrg
2542 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2543 1.34 augustss
2544 1.53 augustss sc->sc_intrxfer = NULL;
2545 1.1 augustss }
2546 1.1 augustss
2547 1.1 augustss /************************/
2548 1.1 augustss
2549 1.82 augustss Static usbd_status
2550 1.254.2.19 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2551 1.1 augustss {
2552 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2553 1.53 augustss usbd_status err;
2554 1.17 augustss
2555 1.46 augustss /* Insert last in queue. */
2556 1.224 mrg mutex_enter(&sc->sc_lock);
2557 1.53 augustss err = usb_insert_transfer(xfer);
2558 1.224 mrg mutex_exit(&sc->sc_lock);
2559 1.53 augustss if (err)
2560 1.254.2.13 skrll return err;
2561 1.46 augustss
2562 1.46 augustss /* Pipe isn't running, start first */
2563 1.254.2.13 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2564 1.17 augustss }
2565 1.17 augustss
2566 1.82 augustss Static usbd_status
2567 1.254.2.19 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2568 1.17 augustss {
2569 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2570 1.254.2.27 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2571 1.254.2.27 skrll usb_device_request_t *req = &xfer->ux_request;
2572 1.254.2.27 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2573 1.254.2.27 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2574 1.254.2.27 skrll ohci_soft_ed_t *sed;
2575 1.254.2.27 skrll int isread;
2576 1.254.2.27 skrll int len;
2577 1.53 augustss usbd_status err;
2578 1.1 augustss
2579 1.254.2.27 skrll
2580 1.254.2.27 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2581 1.254.2.27 skrll
2582 1.83 augustss if (sc->sc_dying)
2583 1.254.2.13 skrll return USBD_IOERROR;
2584 1.83 augustss
2585 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2586 1.1 augustss
2587 1.224 mrg mutex_enter(&sc->sc_lock);
2588 1.254.2.27 skrll
2589 1.254.2.27 skrll isread = req->bmRequestType & UT_READ;
2590 1.254.2.27 skrll len = UGETW(req->wLength);
2591 1.254.2.27 skrll
2592 1.254.2.27 skrll DPRINTF("type=0x%02x, request=0x%02x, "
2593 1.254.2.27 skrll "wValue=0x%04x, wIndex=0x%04x",
2594 1.254.2.27 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2595 1.254.2.27 skrll UGETW(req->wIndex));
2596 1.254.2.27 skrll DPRINTF("len=%d, addr=%d, endpt=%d",
2597 1.254.2.27 skrll len, dev->ud_addr,
2598 1.254.2.27 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0);
2599 1.254.2.27 skrll
2600 1.254.2.27 skrll setup = opipe->tail.td;
2601 1.254.2.27 skrll stat = ohci_alloc_std(sc);
2602 1.254.2.27 skrll if (stat == NULL) {
2603 1.254.2.27 skrll err = USBD_NOMEM;
2604 1.254.2.27 skrll goto bad1;
2605 1.254.2.27 skrll }
2606 1.254.2.27 skrll tail = ohci_alloc_std(sc);
2607 1.254.2.27 skrll if (tail == NULL) {
2608 1.254.2.27 skrll err = USBD_NOMEM;
2609 1.254.2.27 skrll goto bad2;
2610 1.254.2.27 skrll }
2611 1.254.2.27 skrll tail->xfer = NULL;
2612 1.254.2.27 skrll
2613 1.254.2.27 skrll sed = opipe->sed;
2614 1.254.2.27 skrll opipe->ctrl.length = len;
2615 1.254.2.27 skrll
2616 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2617 1.254.2.27 skrll "address ED %d pipe %d\n",
2618 1.254.2.27 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2619 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2620 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2621 1.254.2.27 skrll "MPL ED %d pipe %d\n",
2622 1.254.2.27 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2623 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2624 1.254.2.27 skrll
2625 1.254.2.27 skrll next = stat;
2626 1.254.2.27 skrll
2627 1.254.2.27 skrll /* Set up data transaction */
2628 1.254.2.27 skrll if (len != 0) {
2629 1.254.2.27 skrll ohci_soft_td_t *std = stat;
2630 1.254.2.27 skrll
2631 1.254.2.27 skrll err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
2632 1.254.2.27 skrll std, &stat);
2633 1.254.2.27 skrll if (err) {
2634 1.254.2.27 skrll /* stat is unchanged if error */
2635 1.254.2.27 skrll goto bad3;
2636 1.254.2.27 skrll }
2637 1.254.2.27 skrll stat = stat->nexttd; /* point at free TD */
2638 1.254.2.27 skrll
2639 1.254.2.27 skrll /* Start toggle at 1 and then use the carried toggle. */
2640 1.254.2.27 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2641 1.254.2.27 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2642 1.254.2.27 skrll usb_syncmem(&std->dma,
2643 1.254.2.27 skrll std->offs + offsetof(ohci_td_t, td_flags),
2644 1.254.2.27 skrll sizeof(std->td.td_flags),
2645 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2646 1.254.2.27 skrll }
2647 1.254.2.27 skrll
2648 1.254.2.27 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2649 1.254.2.27 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2650 1.254.2.27 skrll
2651 1.254.2.27 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2652 1.254.2.27 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2653 1.254.2.27 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2654 1.254.2.27 skrll setup->nexttd = next;
2655 1.254.2.27 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2656 1.254.2.27 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2657 1.254.2.27 skrll setup->len = 0;
2658 1.254.2.27 skrll setup->xfer = xfer;
2659 1.254.2.27 skrll setup->flags = 0;
2660 1.254.2.27 skrll xfer->ux_hcpriv = setup;
2661 1.254.2.27 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2662 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2663 1.254.2.27 skrll
2664 1.254.2.27 skrll stat->td.td_flags = HTOO32(
2665 1.254.2.27 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2666 1.254.2.27 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2667 1.254.2.27 skrll stat->td.td_cbp = 0;
2668 1.254.2.27 skrll stat->nexttd = tail;
2669 1.254.2.27 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2670 1.254.2.27 skrll stat->td.td_be = 0;
2671 1.254.2.27 skrll stat->flags = OHCI_CALL_DONE;
2672 1.254.2.27 skrll stat->len = 0;
2673 1.254.2.27 skrll stat->xfer = xfer;
2674 1.254.2.27 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2675 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2676 1.254.2.27 skrll
2677 1.254.2.27 skrll #ifdef OHCI_DEBUG
2678 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2679 1.254.2.27 skrll if (ohcidebug > 5) {
2680 1.254.2.27 skrll ohci_dump_ed(sc, sed);
2681 1.254.2.27 skrll ohci_dump_tds(sc, setup);
2682 1.254.2.27 skrll }
2683 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2684 1.254.2.27 skrll #endif
2685 1.254.2.27 skrll
2686 1.254.2.27 skrll /* Insert ED in schedule */
2687 1.254.2.27 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2688 1.254.2.27 skrll usb_syncmem(&sed->dma,
2689 1.254.2.27 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2690 1.254.2.27 skrll sizeof(sed->ed.ed_tailp),
2691 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2692 1.254.2.27 skrll opipe->tail.td = tail;
2693 1.254.2.27 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2694 1.254.2.27 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2695 1.254.2.27 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2696 1.254.2.27 skrll ohci_timeout, xfer);
2697 1.254.2.27 skrll }
2698 1.254.2.27 skrll
2699 1.254.2.27 skrll #ifdef OHCI_DEBUG
2700 1.254.2.27 skrll DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0);
2701 1.254.2.27 skrll if (ohcidebug > 20) {
2702 1.254.2.27 skrll delay(10000);
2703 1.254.2.27 skrll DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS),
2704 1.254.2.27 skrll 0, 0, 0);
2705 1.254.2.27 skrll ohci_dumpregs(sc);
2706 1.254.2.27 skrll DPRINTFN(20, "ctrl head:", 0, 0, 0, 0);
2707 1.254.2.27 skrll ohci_dump_ed(sc, sc->sc_ctrl_head);
2708 1.254.2.27 skrll DPRINTF("sed:", 0, 0, 0, 0);
2709 1.254.2.27 skrll ohci_dump_ed(sc, sed);
2710 1.254.2.27 skrll ohci_dump_tds(sc, setup);
2711 1.254.2.27 skrll }
2712 1.254.2.27 skrll DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0);
2713 1.254.2.27 skrll #endif
2714 1.254.2.27 skrll
2715 1.224 mrg mutex_exit(&sc->sc_lock);
2716 1.1 augustss
2717 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling)
2718 1.53 augustss ohci_waitintr(sc, xfer);
2719 1.254.2.27 skrll
2720 1.254.2.13 skrll return USBD_IN_PROGRESS;
2721 1.254.2.27 skrll
2722 1.254.2.27 skrll bad3:
2723 1.254.2.27 skrll ohci_free_std(sc, tail);
2724 1.254.2.27 skrll bad2:
2725 1.254.2.27 skrll ohci_free_std(sc, stat);
2726 1.254.2.27 skrll bad1:
2727 1.254.2.27 skrll mutex_exit(&sc->sc_lock);
2728 1.254.2.27 skrll
2729 1.254.2.27 skrll return err;
2730 1.1 augustss }
2731 1.1 augustss
2732 1.1 augustss /* Abort a device control request. */
2733 1.82 augustss Static void
2734 1.254.2.19 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2735 1.1 augustss {
2736 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2737 1.224 mrg
2738 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2739 1.224 mrg
2740 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2741 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2742 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2743 1.1 augustss }
2744 1.1 augustss
2745 1.1 augustss /* Close a device control pipe. */
2746 1.82 augustss Static void
2747 1.254.2.19 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2748 1.1 augustss {
2749 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2750 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2751 1.1 augustss
2752 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2753 1.224 mrg
2754 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2755 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2756 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2757 1.60 augustss ohci_free_std(sc, opipe->tail.td);
2758 1.3 augustss }
2759 1.3 augustss
2760 1.3 augustss /************************/
2761 1.37 augustss
2762 1.82 augustss Static void
2763 1.254.2.19 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2764 1.37 augustss {
2765 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2766 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2767 1.37 augustss
2768 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2769 1.37 augustss }
2770 1.37 augustss
2771 1.82 augustss Static void
2772 1.254.2.19 skrll ohci_noop(struct usbd_pipe *pipe)
2773 1.37 augustss {
2774 1.37 augustss }
2775 1.3 augustss
2776 1.82 augustss Static usbd_status
2777 1.254.2.19 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
2778 1.3 augustss {
2779 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2780 1.53 augustss usbd_status err;
2781 1.17 augustss
2782 1.46 augustss /* Insert last in queue. */
2783 1.224 mrg mutex_enter(&sc->sc_lock);
2784 1.53 augustss err = usb_insert_transfer(xfer);
2785 1.224 mrg mutex_exit(&sc->sc_lock);
2786 1.53 augustss if (err)
2787 1.254.2.13 skrll return err;
2788 1.46 augustss
2789 1.46 augustss /* Pipe isn't running, start first */
2790 1.254.2.13 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2791 1.17 augustss }
2792 1.17 augustss
2793 1.82 augustss Static usbd_status
2794 1.254.2.19 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
2795 1.17 augustss {
2796 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2797 1.254.2.19 skrll struct usbd_device *dev = opipe->pipe.up_dev;
2798 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2799 1.254.2.7 skrll int addr = dev->ud_addr;
2800 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
2801 1.3 augustss ohci_soft_ed_t *sed;
2802 1.224 mrg int len, isread, endpt;
2803 1.53 augustss usbd_status err;
2804 1.3 augustss
2805 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2806 1.254.2.18 skrll
2807 1.83 augustss if (sc->sc_dying)
2808 1.254.2.13 skrll return USBD_IOERROR;
2809 1.83 augustss
2810 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2811 1.3 augustss
2812 1.224 mrg mutex_enter(&sc->sc_lock);
2813 1.224 mrg
2814 1.254.2.7 skrll len = xfer->ux_length;
2815 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2816 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2817 1.3 augustss sed = opipe->sed;
2818 1.3 augustss
2819 1.254.2.18 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
2820 1.254.2.18 skrll xfer->ux_flags);
2821 1.254.2.18 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
2822 1.34 augustss
2823 1.254.2.21 skrll opipe->bulk.isread = isread;
2824 1.254.2.21 skrll opipe->bulk.length = len;
2825 1.3 augustss
2826 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2827 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2828 1.3 augustss /* Update device address */
2829 1.168 augustss sed->ed.ed_flags = HTOO32(
2830 1.168 augustss (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) |
2831 1.16 augustss OHCI_ED_SET_FA(addr));
2832 1.3 augustss
2833 1.48 augustss /* Allocate a chain of new TDs (including a new tail). */
2834 1.60 augustss data = opipe->tail.td;
2835 1.77 augustss err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer,
2836 1.77 augustss data, &tail);
2837 1.236 skrll if (err)
2838 1.236 skrll return err;
2839 1.254.2.1 skrll
2840 1.77 augustss /* We want interrupt at the end of the transfer. */
2841 1.168 augustss tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
2842 1.168 augustss tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
2843 1.77 augustss tail->flags |= OHCI_CALL_DONE;
2844 1.77 augustss tail = tail->nexttd; /* point at sentinel */
2845 1.195 bouyer usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags),
2846 1.195 bouyer sizeof(tail->td.td_flags),
2847 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2848 1.224 mrg if (err) {
2849 1.224 mrg mutex_exit(&sc->sc_lock);
2850 1.254.2.13 skrll return err;
2851 1.224 mrg }
2852 1.48 augustss
2853 1.53 augustss tail->xfer = NULL;
2854 1.254.2.7 skrll xfer->ux_hcpriv = data;
2855 1.3 augustss
2856 1.254.2.18 skrll DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x "
2857 1.254.2.18 skrll "td_cbp=0x%08x td_be=0x%08x",
2858 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
2859 1.168 augustss (int)O32TOH(data->td.td_flags),
2860 1.168 augustss (int)O32TOH(data->td.td_cbp),
2861 1.254.2.18 skrll (int)O32TOH(data->td.td_be));
2862 1.34 augustss
2863 1.52 augustss #ifdef OHCI_DEBUG
2864 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
2865 1.75 augustss if (ohcidebug > 5) {
2866 1.168 augustss ohci_dump_ed(sc, sed);
2867 1.168 augustss ohci_dump_tds(sc, data);
2868 1.34 augustss }
2869 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
2870 1.34 augustss #endif
2871 1.34 augustss
2872 1.3 augustss /* Insert ED in schedule */
2873 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
2874 1.53 augustss tdp->xfer = xfer;
2875 1.48 augustss }
2876 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
2877 1.60 augustss opipe->tail.td = tail;
2878 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
2879 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2880 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2881 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
2882 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2883 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2884 1.80 augustss ohci_timeout, xfer);
2885 1.15 augustss }
2886 1.224 mrg mutex_exit(&sc->sc_lock);
2887 1.34 augustss
2888 1.52 augustss #if 0
2889 1.52 augustss /* This goes wrong if we are too slow. */
2890 1.75 augustss if (ohcidebug > 10) {
2891 1.75 augustss delay(10000);
2892 1.254.2.18 skrll DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS),
2893 1.254.2.18 skrll 0, 0, 0);
2894 1.168 augustss ohci_dump_ed(sc, sed);
2895 1.168 augustss ohci_dump_tds(sc, data);
2896 1.34 augustss }
2897 1.34 augustss #endif
2898 1.34 augustss
2899 1.254.2.13 skrll return USBD_IN_PROGRESS;
2900 1.3 augustss }
2901 1.3 augustss
2902 1.82 augustss Static void
2903 1.254.2.19 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
2904 1.3 augustss {
2905 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2906 1.254.2.25 skrll
2907 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2908 1.224 mrg
2909 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2910 1.224 mrg
2911 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2912 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2913 1.3 augustss }
2914 1.3 augustss
2915 1.120 augustss /*
2916 1.34 augustss * Close a device bulk pipe.
2917 1.34 augustss */
2918 1.82 augustss Static void
2919 1.254.2.19 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
2920 1.3 augustss {
2921 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2922 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2923 1.3 augustss
2924 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2925 1.224 mrg
2926 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2927 1.254.2.18 skrll
2928 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2929 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
2930 1.60 augustss ohci_free_std(sc, opipe->tail.td);
2931 1.1 augustss }
2932 1.1 augustss
2933 1.1 augustss /************************/
2934 1.1 augustss
2935 1.82 augustss Static usbd_status
2936 1.254.2.19 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
2937 1.17 augustss {
2938 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2939 1.53 augustss usbd_status err;
2940 1.17 augustss
2941 1.46 augustss /* Insert last in queue. */
2942 1.224 mrg mutex_enter(&sc->sc_lock);
2943 1.53 augustss err = usb_insert_transfer(xfer);
2944 1.224 mrg mutex_exit(&sc->sc_lock);
2945 1.53 augustss if (err)
2946 1.254.2.13 skrll return err;
2947 1.46 augustss
2948 1.46 augustss /* Pipe isn't running, start first */
2949 1.254.2.13 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2950 1.17 augustss }
2951 1.17 augustss
2952 1.82 augustss Static usbd_status
2953 1.254.2.19 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
2954 1.1 augustss {
2955 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2956 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2957 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
2958 1.48 augustss ohci_soft_td_t *data, *tail;
2959 1.224 mrg int len, isread, endpt;
2960 1.1 augustss
2961 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2962 1.254.2.18 skrll
2963 1.83 augustss if (sc->sc_dying)
2964 1.254.2.13 skrll return USBD_IOERROR;
2965 1.83 augustss
2966 1.254.2.18 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length,
2967 1.254.2.18 skrll xfer->ux_flags, xfer->ux_priv);
2968 1.1 augustss
2969 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2970 1.1 augustss
2971 1.254.2.7 skrll len = xfer->ux_length;
2972 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2973 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2974 1.1 augustss
2975 1.60 augustss data = opipe->tail.td;
2976 1.224 mrg mutex_enter(&sc->sc_lock);
2977 1.1 augustss tail = ohci_alloc_std(sc);
2978 1.224 mrg mutex_exit(&sc->sc_lock);
2979 1.55 augustss if (tail == NULL)
2980 1.254.2.13 skrll return USBD_NOMEM;
2981 1.53 augustss tail->xfer = NULL;
2982 1.1 augustss
2983 1.168 augustss data->td.td_flags = HTOO32(
2984 1.165 skrll isread ? OHCI_TD_IN : OHCI_TD_OUT |
2985 1.165 skrll OHCI_TD_NOCC |
2986 1.16 augustss OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
2987 1.254.2.7 skrll if (xfer->ux_flags & USBD_SHORT_XFER_OK)
2988 1.168 augustss data->td.td_flags |= HTOO32(OHCI_TD_R);
2989 1.254.2.7 skrll data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0));
2990 1.48 augustss data->nexttd = tail;
2991 1.168 augustss data->td.td_nexttd = HTOO32(tail->physaddr);
2992 1.168 augustss data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1);
2993 1.48 augustss data->len = len;
2994 1.53 augustss data->xfer = xfer;
2995 1.48 augustss data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN;
2996 1.195 bouyer usb_syncmem(&data->dma, data->offs, sizeof(data->td),
2997 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2998 1.254.2.7 skrll xfer->ux_hcpriv = data;
2999 1.1 augustss
3000 1.52 augustss #ifdef OHCI_DEBUG
3001 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3002 1.1 augustss if (ohcidebug > 5) {
3003 1.168 augustss ohci_dump_ed(sc, sed);
3004 1.168 augustss ohci_dump_tds(sc, data);
3005 1.1 augustss }
3006 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3007 1.1 augustss #endif
3008 1.1 augustss
3009 1.1 augustss /* Insert ED in schedule */
3010 1.224 mrg mutex_enter(&sc->sc_lock);
3011 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3012 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3013 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3014 1.60 augustss opipe->tail.td = tail;
3015 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3016 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3017 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3018 1.1 augustss
3019 1.52 augustss #if 0
3020 1.52 augustss /*
3021 1.52 augustss * This goes horribly wrong, printing thousands of descriptors,
3022 1.52 augustss * because false references are followed due to the fact that the
3023 1.52 augustss * TD is gone.
3024 1.52 augustss */
3025 1.1 augustss if (ohcidebug > 5) {
3026 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock);
3027 1.254.2.18 skrll DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS),
3028 1.254.2.18 skrll 0, 0, 0);
3029 1.168 augustss ohci_dump_ed(sc, sed);
3030 1.168 augustss ohci_dump_tds(sc, data);
3031 1.1 augustss }
3032 1.1 augustss #endif
3033 1.224 mrg mutex_exit(&sc->sc_lock);
3034 1.1 augustss
3035 1.254.2.13 skrll return USBD_IN_PROGRESS;
3036 1.1 augustss }
3037 1.1 augustss
3038 1.227 skrll /* Abort a device interrupt request. */
3039 1.82 augustss Static void
3040 1.254.2.19 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3041 1.1 augustss {
3042 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3043 1.224 mrg
3044 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3045 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3046 1.224 mrg
3047 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3048 1.1 augustss }
3049 1.1 augustss
3050 1.1 augustss /* Close a device interrupt pipe. */
3051 1.82 augustss Static void
3052 1.254.2.19 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3053 1.1 augustss {
3054 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3055 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3056 1.254.2.21 skrll int nslots = opipe->intr.nslots;
3057 1.254.2.21 skrll int pos = opipe->intr.pos;
3058 1.1 augustss int j;
3059 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3060 1.224 mrg
3061 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3062 1.254.2.18 skrll
3063 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3064 1.1 augustss
3065 1.254.2.18 skrll DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0);
3066 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3067 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3068 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3069 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3070 1.195 bouyer sizeof(sed->ed.ed_flags),
3071 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3072 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3073 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3074 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3075 1.1 augustss
3076 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3077 1.172 christos continue;
3078 1.254.2.24 skrll KASSERT(p);
3079 1.173 christos p->next = sed->next;
3080 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3081 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3082 1.195 bouyer sizeof(p->ed.ed_nexted),
3083 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3084 1.1 augustss
3085 1.1 augustss for (j = 0; j < nslots; j++)
3086 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3087 1.1 augustss
3088 1.60 augustss ohci_free_std(sc, opipe->tail.td);
3089 1.1 augustss ohci_free_sed(sc, opipe->sed);
3090 1.1 augustss }
3091 1.1 augustss
3092 1.82 augustss Static usbd_status
3093 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3094 1.1 augustss {
3095 1.224 mrg int i, j, best;
3096 1.1 augustss u_int npoll, slow, shigh, nslots;
3097 1.1 augustss u_int bestbw, bw;
3098 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3099 1.1 augustss
3100 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3101 1.254.2.18 skrll
3102 1.254.2.18 skrll DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0);
3103 1.1 augustss if (ival == 0) {
3104 1.1 augustss printf("ohci_setintr: 0 interval\n");
3105 1.254.2.13 skrll return USBD_INVAL;
3106 1.1 augustss }
3107 1.1 augustss
3108 1.1 augustss npoll = OHCI_NO_INTRS;
3109 1.1 augustss while (npoll > ival)
3110 1.1 augustss npoll /= 2;
3111 1.254.2.18 skrll DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0);
3112 1.1 augustss
3113 1.1 augustss /*
3114 1.1 augustss * We now know which level in the tree the ED must go into.
3115 1.1 augustss * Figure out which slot has most bandwidth left over.
3116 1.1 augustss * Slots to examine:
3117 1.1 augustss * npoll
3118 1.1 augustss * 1 0
3119 1.1 augustss * 2 1 2
3120 1.1 augustss * 4 3 4 5 6
3121 1.1 augustss * 8 7 8 9 10 11 12 13 14
3122 1.1 augustss * N (N-1) .. (N-1+N-1)
3123 1.1 augustss */
3124 1.1 augustss slow = npoll-1;
3125 1.1 augustss shigh = slow + npoll;
3126 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3127 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3128 1.1 augustss bw = 0;
3129 1.1 augustss for (j = 0; j < nslots; j++)
3130 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3131 1.1 augustss if (bw < bestbw) {
3132 1.1 augustss best = i;
3133 1.1 augustss bestbw = bw;
3134 1.1 augustss }
3135 1.1 augustss }
3136 1.254.2.18 skrll DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw);
3137 1.1 augustss
3138 1.224 mrg mutex_enter(&sc->sc_lock);
3139 1.1 augustss hsed = sc->sc_eds[best];
3140 1.1 augustss sed->next = hsed->next;
3141 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3142 1.195 bouyer sizeof(hsed->ed.ed_flags),
3143 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3144 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3145 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3146 1.195 bouyer sizeof(sed->ed.ed_flags),
3147 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3148 1.1 augustss hsed->next = sed;
3149 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3150 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3151 1.195 bouyer sizeof(hsed->ed.ed_flags),
3152 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3153 1.224 mrg mutex_exit(&sc->sc_lock);
3154 1.1 augustss
3155 1.1 augustss for (j = 0; j < nslots; j++)
3156 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3157 1.254.2.21 skrll opipe->intr.nslots = nslots;
3158 1.254.2.21 skrll opipe->intr.pos = best;
3159 1.1 augustss
3160 1.254.2.18 skrll DPRINTFN(5, "returns %p", opipe, 0, 0, 0);
3161 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3162 1.60 augustss }
3163 1.60 augustss
3164 1.60 augustss /***********************/
3165 1.60 augustss
3166 1.60 augustss usbd_status
3167 1.254.2.19 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3168 1.60 augustss {
3169 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3170 1.60 augustss usbd_status err;
3171 1.60 augustss
3172 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3173 1.254.2.18 skrll
3174 1.254.2.18 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3175 1.60 augustss
3176 1.60 augustss /* Put it on our queue, */
3177 1.224 mrg mutex_enter(&sc->sc_lock);
3178 1.60 augustss err = usb_insert_transfer(xfer);
3179 1.224 mrg mutex_exit(&sc->sc_lock);
3180 1.60 augustss
3181 1.60 augustss /* bail out on error, */
3182 1.60 augustss if (err && err != USBD_IN_PROGRESS)
3183 1.254.2.13 skrll return err;
3184 1.60 augustss
3185 1.60 augustss /* XXX should check inuse here */
3186 1.60 augustss
3187 1.60 augustss /* insert into schedule, */
3188 1.60 augustss ohci_device_isoc_enter(xfer);
3189 1.60 augustss
3190 1.83 augustss /* and start if the pipe wasn't running */
3191 1.60 augustss if (!err)
3192 1.254.2.7 skrll ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3193 1.60 augustss
3194 1.254.2.13 skrll return err;
3195 1.60 augustss }
3196 1.60 augustss
3197 1.60 augustss void
3198 1.254.2.19 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3199 1.60 augustss {
3200 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3201 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3202 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3203 1.254.2.21 skrll struct isoc *isoc = &opipe->isoc;
3204 1.120 augustss ohci_soft_itd_t *sitd, *nsitd;
3205 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3206 1.61 augustss int i, ncur, nframes;
3207 1.61 augustss
3208 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3209 1.254.2.18 skrll
3210 1.254.2.18 skrll DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d",
3211 1.254.2.21 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3212 1.83 augustss
3213 1.83 augustss if (sc->sc_dying)
3214 1.83 augustss return;
3215 1.83 augustss
3216 1.254.2.21 skrll if (isoc->next == -1) {
3217 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3218 1.254.2.21 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3219 1.254.2.21 skrll DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0);
3220 1.83 augustss }
3221 1.83 augustss
3222 1.61 augustss sitd = opipe->tail.itd;
3223 1.254.2.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3224 1.83 augustss bp0 = OHCI_PAGE(buf);
3225 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3226 1.254.2.7 skrll nframes = xfer->ux_nframes;
3227 1.254.2.7 skrll xfer->ux_hcpriv = sitd;
3228 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3229 1.254.2.7 skrll noffs = offs + xfer->ux_frlengths[i];
3230 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3231 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3232 1.120 augustss
3233 1.83 augustss /* Allocate next ITD */
3234 1.224 mrg mutex_enter(&sc->sc_lock);
3235 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3236 1.224 mrg mutex_exit(&sc->sc_lock);
3237 1.61 augustss if (nsitd == NULL) {
3238 1.61 augustss /* XXX what now? */
3239 1.83 augustss printf("%s: isoc TD alloc failed\n",
3240 1.190 drochner device_xname(sc->sc_dev));
3241 1.61 augustss return;
3242 1.61 augustss }
3243 1.83 augustss
3244 1.83 augustss /* Fill current ITD */
3245 1.168 augustss sitd->itd.itd_flags = HTOO32(
3246 1.120 augustss OHCI_ITD_NOCC |
3247 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3248 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3249 1.83 augustss OHCI_ITD_SET_FC(ncur));
3250 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3251 1.83 augustss sitd->nextitd = nsitd;
3252 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3253 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3254 1.83 augustss sitd->xfer = xfer;
3255 1.83 augustss sitd->flags = 0;
3256 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3257 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3258 1.83 augustss
3259 1.61 augustss sitd = nsitd;
3260 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3261 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3262 1.61 augustss ncur = 0;
3263 1.61 augustss }
3264 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3265 1.83 augustss offs = noffs;
3266 1.61 augustss }
3267 1.224 mrg mutex_enter(&sc->sc_lock);
3268 1.61 augustss nsitd = ohci_alloc_sitd(sc);
3269 1.224 mrg mutex_exit(&sc->sc_lock);
3270 1.61 augustss if (nsitd == NULL) {
3271 1.61 augustss /* XXX what now? */
3272 1.120 augustss printf("%s: isoc TD alloc failed\n",
3273 1.190 drochner device_xname(sc->sc_dev));
3274 1.61 augustss return;
3275 1.61 augustss }
3276 1.83 augustss /* Fixup last used ITD */
3277 1.168 augustss sitd->itd.itd_flags = HTOO32(
3278 1.120 augustss OHCI_ITD_NOCC |
3279 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3280 1.61 augustss OHCI_ITD_SET_DI(0) |
3281 1.61 augustss OHCI_ITD_SET_FC(ncur));
3282 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3283 1.83 augustss sitd->nextitd = nsitd;
3284 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3285 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3286 1.83 augustss sitd->xfer = xfer;
3287 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3288 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3289 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3290 1.83 augustss
3291 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3292 1.254.2.21 skrll isoc->inuse += nframes;
3293 1.83 augustss
3294 1.254.2.7 skrll xfer->ux_actlen = offs; /* XXX pretend we did it all */
3295 1.83 augustss
3296 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3297 1.83 augustss
3298 1.83 augustss #ifdef OHCI_DEBUG
3299 1.83 augustss if (ohcidebug > 5) {
3300 1.254.2.18 skrll DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3301 1.254.2.18 skrll 0, 0, 0);
3302 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3303 1.168 augustss ohci_dump_ed(sc, sed);
3304 1.83 augustss }
3305 1.83 augustss #endif
3306 1.61 augustss
3307 1.224 mrg mutex_enter(&sc->sc_lock);
3308 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3309 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3310 1.168 augustss sed->ed.ed_tailp = HTOO32(nsitd->physaddr);
3311 1.61 augustss opipe->tail.itd = nsitd;
3312 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3313 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3314 1.195 bouyer sizeof(sed->ed.ed_flags),
3315 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3316 1.224 mrg mutex_exit(&sc->sc_lock);
3317 1.83 augustss
3318 1.83 augustss #ifdef OHCI_DEBUG
3319 1.83 augustss if (ohcidebug > 5) {
3320 1.83 augustss delay(150000);
3321 1.254.2.18 skrll DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3322 1.254.2.18 skrll 0, 0, 0);
3323 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3324 1.168 augustss ohci_dump_ed(sc, sed);
3325 1.83 augustss }
3326 1.83 augustss #endif
3327 1.60 augustss }
3328 1.60 augustss
3329 1.60 augustss usbd_status
3330 1.254.2.19 skrll ohci_device_isoc_start(struct usbd_xfer *xfer)
3331 1.60 augustss {
3332 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3333 1.83 augustss
3334 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3335 1.254.2.18 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3336 1.83 augustss
3337 1.224 mrg mutex_enter(&sc->sc_lock);
3338 1.224 mrg
3339 1.224 mrg if (sc->sc_dying) {
3340 1.224 mrg mutex_exit(&sc->sc_lock);
3341 1.254.2.13 skrll return USBD_IOERROR;
3342 1.224 mrg }
3343 1.83 augustss
3344 1.254.2.24 skrll
3345 1.83 augustss #ifdef DIAGNOSTIC
3346 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
3347 1.121 tsutsui printf("ohci_device_isoc_start: not in progress %p\n", xfer);
3348 1.83 augustss #endif
3349 1.83 augustss
3350 1.83 augustss /* XXX anything to do? */
3351 1.83 augustss
3352 1.224 mrg mutex_exit(&sc->sc_lock);
3353 1.224 mrg
3354 1.254.2.13 skrll return USBD_IN_PROGRESS;
3355 1.60 augustss }
3356 1.60 augustss
3357 1.60 augustss void
3358 1.254.2.19 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3359 1.60 augustss {
3360 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3361 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3362 1.83 augustss ohci_soft_ed_t *sed;
3363 1.83 augustss ohci_soft_itd_t *sitd;
3364 1.83 augustss
3365 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3366 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3367 1.83 augustss
3368 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3369 1.83 augustss
3370 1.83 augustss /* Transfer is already done. */
3371 1.254.2.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3372 1.254.2.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3373 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3374 1.224 mrg goto done;
3375 1.83 augustss }
3376 1.83 augustss
3377 1.83 augustss /* Give xfer the requested abort code. */
3378 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
3379 1.83 augustss
3380 1.83 augustss sed = opipe->sed;
3381 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3382 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3383 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3384 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3385 1.195 bouyer sizeof(sed->ed.ed_flags),
3386 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3387 1.83 augustss
3388 1.254.2.7 skrll sitd = xfer->ux_hcpriv;
3389 1.254.2.24 skrll KASSERT(sitd);
3390 1.254.2.24 skrll
3391 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3392 1.83 augustss #ifdef DIAGNOSTIC
3393 1.254.2.18 skrll DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0);
3394 1.83 augustss sitd->isdone = 1;
3395 1.83 augustss #endif
3396 1.83 augustss }
3397 1.83 augustss
3398 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3399 1.83 augustss
3400 1.83 augustss /* Run callback. */
3401 1.83 augustss usb_transfer_complete(xfer);
3402 1.83 augustss
3403 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3404 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3405 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3406 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3407 1.83 augustss
3408 1.224 mrg done:
3409 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3410 1.60 augustss }
3411 1.60 augustss
3412 1.60 augustss void
3413 1.254.2.19 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3414 1.60 augustss {
3415 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3416 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3417 1.60 augustss }
3418 1.60 augustss
3419 1.60 augustss usbd_status
3420 1.254.2.19 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3421 1.60 augustss {
3422 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3423 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3424 1.254.2.21 skrll struct isoc *isoc = &opipe->isoc;
3425 1.60 augustss
3426 1.254.2.21 skrll isoc->next = -1;
3427 1.254.2.21 skrll isoc->inuse = 0;
3428 1.60 augustss
3429 1.224 mrg mutex_enter(&sc->sc_lock);
3430 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3431 1.224 mrg mutex_exit(&sc->sc_lock);
3432 1.83 augustss
3433 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3434 1.60 augustss }
3435 1.60 augustss
3436 1.60 augustss void
3437 1.254.2.19 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3438 1.60 augustss {
3439 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3440 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3441 1.60 augustss
3442 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3443 1.224 mrg
3444 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3445 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3446 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3447 1.83 augustss #ifdef DIAGNOSTIC
3448 1.83 augustss opipe->tail.itd->isdone = 1;
3449 1.83 augustss #endif
3450 1.60 augustss ohci_free_sitd(sc, opipe->tail.itd);
3451 1.1 augustss }
3452