ohci.c revision 1.254.2.59 1 1.254.2.59 skrll /* $NetBSD: ohci.c,v 1.254.2.59 2016/03/17 09:04:53 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.254.2.59 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.59 2016/03/17 09:04:53 skrll Exp $");
45 1.254.2.18 skrll
46 1.254.2.18 skrll #include "opt_usb.h"
47 1.1 augustss
48 1.1 augustss #include <sys/param.h>
49 1.254.2.17 skrll
50 1.254.2.17 skrll #include <sys/cpu.h>
51 1.1 augustss #include <sys/device.h>
52 1.254.2.17 skrll #include <sys/kernel.h>
53 1.254.2.17 skrll #include <sys/kmem.h>
54 1.1 augustss #include <sys/proc.h>
55 1.1 augustss #include <sys/queue.h>
56 1.254.2.17 skrll #include <sys/select.h>
57 1.254.2.18 skrll #include <sys/sysctl.h>
58 1.254.2.17 skrll #include <sys/systm.h>
59 1.1 augustss
60 1.16 augustss #include <machine/endian.h>
61 1.4 augustss
62 1.1 augustss #include <dev/usb/usb.h>
63 1.1 augustss #include <dev/usb/usbdi.h>
64 1.1 augustss #include <dev/usb/usbdivar.h>
65 1.38 augustss #include <dev/usb/usb_mem.h>
66 1.1 augustss #include <dev/usb/usb_quirks.h>
67 1.1 augustss
68 1.1 augustss #include <dev/usb/ohcireg.h>
69 1.1 augustss #include <dev/usb/ohcivar.h>
70 1.254.2.11 skrll #include <dev/usb/usbroothub.h>
71 1.254.2.18 skrll #include <dev/usb/usbhist.h>
72 1.1 augustss
73 1.254.2.18 skrll #ifdef USB_DEBUG
74 1.254.2.18 skrll #ifndef OHCI_DEBUG
75 1.254.2.18 skrll #define ohcidebug 0
76 1.254.2.18 skrll #else
77 1.254.2.59 skrll static int ohcidebug = 10;
78 1.1 augustss
79 1.254.2.18 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
80 1.254.2.18 skrll {
81 1.254.2.18 skrll int err;
82 1.254.2.18 skrll const struct sysctlnode *rnode;
83 1.254.2.18 skrll const struct sysctlnode *cnode;
84 1.254.2.18 skrll
85 1.254.2.18 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
86 1.254.2.18 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
87 1.254.2.18 skrll SYSCTL_DESCR("ohci global controls"),
88 1.254.2.18 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
89 1.36 augustss
90 1.254.2.18 skrll if (err)
91 1.254.2.18 skrll goto fail;
92 1.254.2.18 skrll
93 1.254.2.18 skrll /* control debugging printfs */
94 1.254.2.18 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
95 1.254.2.18 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
96 1.254.2.18 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
97 1.254.2.18 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
98 1.254.2.18 skrll if (err)
99 1.254.2.18 skrll goto fail;
100 1.254.2.18 skrll
101 1.254.2.18 skrll return;
102 1.254.2.18 skrll fail:
103 1.254.2.18 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
104 1.254.2.18 skrll }
105 1.254.2.18 skrll
106 1.254.2.18 skrll #endif /* OHCI_DEBUG */
107 1.254.2.18 skrll #endif /* USB_DEBUG */
108 1.254.2.18 skrll
109 1.254.2.18 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
110 1.254.2.18 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
111 1.254.2.18 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
112 1.254.2.18 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
113 1.52 augustss
114 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
115 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
116 1.16 augustss #else
117 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
118 1.16 augustss #endif
119 1.16 augustss
120 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
121 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
122 1.169 tron #define HTOO16(val) O16TOH(val)
123 1.169 tron #define HTOO32(val) O32TOH(val)
124 1.168 augustss
125 1.1 augustss struct ohci_pipe;
126 1.1 augustss
127 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
128 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
129 1.1 augustss
130 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
131 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
132 1.254.2.35 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
133 1.1 augustss
134 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
135 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
136 1.254.2.35 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
137 1.254.2.35 skrll ohci_soft_itd_t *);
138 1.60 augustss
139 1.254.2.35 skrll Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
140 1.254.2.35 skrll int, int);
141 1.254.2.35 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
142 1.254.2.35 skrll
143 1.254.2.35 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
144 1.254.2.35 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
145 1.53 augustss
146 1.254.2.19 skrll Static usbd_status ohci_open(struct usbd_pipe *);
147 1.91 augustss Static void ohci_poll(struct usbd_bus *);
148 1.99 augustss Static void ohci_softintr(void *);
149 1.254.2.19 skrll Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *);
150 1.254.2.19 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
151 1.254.2.15 skrll Static void ohci_rhsc_softint(void *);
152 1.91 augustss
153 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
154 1.168 augustss ohci_soft_ed_t *);
155 1.168 augustss
156 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
157 1.224 mrg ohci_soft_ed_t *);
158 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
159 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
161 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
162 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
164 1.91 augustss
165 1.254.2.19 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
166 1.254.2.19 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
167 1.91 augustss
168 1.254.2.23 skrll Static struct usbd_xfer *
169 1.254.2.23 skrll ohci_allocx(struct usbd_bus *, unsigned int);
170 1.254.2.19 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
171 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
172 1.254.2.13 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
173 1.254.2.26 skrll usb_device_request_t *, void *, int);
174 1.91 augustss
175 1.254.2.19 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
176 1.254.2.19 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
177 1.254.2.19 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
178 1.254.2.19 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
179 1.254.2.19 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
180 1.254.2.19 skrll
181 1.254.2.35 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
182 1.254.2.35 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
183 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
184 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
185 1.254.2.19 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
186 1.254.2.19 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
187 1.254.2.19 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
188 1.254.2.19 skrll
189 1.254.2.35 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
190 1.254.2.35 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
191 1.254.2.19 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
192 1.254.2.19 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
193 1.254.2.19 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
194 1.254.2.19 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
195 1.254.2.19 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
196 1.254.2.19 skrll
197 1.254.2.35 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
198 1.254.2.35 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
199 1.254.2.19 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
200 1.254.2.19 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
201 1.254.2.19 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
202 1.254.2.19 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
203 1.254.2.19 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
204 1.254.2.19 skrll
205 1.254.2.35 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
206 1.254.2.35 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
207 1.254.2.19 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
208 1.254.2.19 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
209 1.254.2.19 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
210 1.254.2.19 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
211 1.91 augustss
212 1.254.2.15 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
213 1.254.2.15 skrll struct ohci_pipe *, int);
214 1.91 augustss
215 1.91 augustss Static void ohci_timeout(void *);
216 1.114 augustss Static void ohci_timeout_task(void *);
217 1.104 augustss Static void ohci_rhsc_enable(void *);
218 1.91 augustss
219 1.254.2.19 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
220 1.254.2.19 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
221 1.53 augustss
222 1.254.2.19 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
223 1.254.2.19 skrll Static void ohci_noop(struct usbd_pipe *);
224 1.37 augustss
225 1.52 augustss #ifdef OHCI_DEBUG
226 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
227 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
228 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
230 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
231 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
232 1.1 augustss #endif
233 1.1 augustss
234 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
235 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
236 1.88 augustss #define OWRITE1(sc, r, x) \
237 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
238 1.88 augustss #define OWRITE2(sc, r, x) \
239 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
240 1.88 augustss #define OWRITE4(sc, r, x) \
241 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
242 1.174 mrg
243 1.174 mrg static __inline uint32_t
244 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
245 1.174 mrg {
246 1.174 mrg
247 1.174 mrg OBARR(sc);
248 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
249 1.174 mrg }
250 1.1 augustss
251 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
252 1.254.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
253 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
254 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
255 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
256 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
257 1.1 augustss
258 1.1 augustss struct ohci_pipe {
259 1.1 augustss struct usbd_pipe pipe;
260 1.1 augustss ohci_soft_ed_t *sed;
261 1.60 augustss union {
262 1.60 augustss ohci_soft_td_t *td;
263 1.60 augustss ohci_soft_itd_t *itd;
264 1.60 augustss } tail;
265 1.1 augustss /* Info needed for different pipe kinds. */
266 1.1 augustss union {
267 1.1 augustss /* Control pipe */
268 1.1 augustss struct {
269 1.4 augustss usb_dma_t reqdma;
270 1.254.2.21 skrll } ctrl;
271 1.1 augustss /* Interrupt pipe */
272 1.1 augustss struct {
273 1.1 augustss int nslots;
274 1.1 augustss int pos;
275 1.1 augustss } intr;
276 1.254.2.21 skrll /* Isochronous pipe */
277 1.254.2.21 skrll struct isoc {
278 1.60 augustss int next, inuse;
279 1.254.2.21 skrll } isoc;
280 1.254.2.21 skrll };
281 1.1 augustss };
282 1.1 augustss
283 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
284 1.254.2.5 skrll .ubm_open = ohci_open,
285 1.254.2.5 skrll .ubm_softint = ohci_softintr,
286 1.254.2.5 skrll .ubm_dopoll = ohci_poll,
287 1.254.2.5 skrll .ubm_allocx = ohci_allocx,
288 1.254.2.5 skrll .ubm_freex = ohci_freex,
289 1.254.2.5 skrll .ubm_getlock = ohci_get_lock,
290 1.254.2.12 skrll .ubm_rhctrl = ohci_roothub_ctrl,
291 1.1 augustss };
292 1.1 augustss
293 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
294 1.254.2.5 skrll .upm_transfer = ohci_root_intr_transfer,
295 1.254.2.5 skrll .upm_start = ohci_root_intr_start,
296 1.254.2.5 skrll .upm_abort = ohci_root_intr_abort,
297 1.254.2.5 skrll .upm_close = ohci_root_intr_close,
298 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
299 1.254.2.5 skrll .upm_done = ohci_root_intr_done,
300 1.1 augustss };
301 1.1 augustss
302 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
303 1.254.2.35 skrll .upm_init = ohci_device_ctrl_init,
304 1.254.2.35 skrll .upm_fini = ohci_device_ctrl_fini,
305 1.254.2.5 skrll .upm_transfer = ohci_device_ctrl_transfer,
306 1.254.2.5 skrll .upm_start = ohci_device_ctrl_start,
307 1.254.2.5 skrll .upm_abort = ohci_device_ctrl_abort,
308 1.254.2.5 skrll .upm_close = ohci_device_ctrl_close,
309 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
310 1.254.2.5 skrll .upm_done = ohci_device_ctrl_done,
311 1.1 augustss };
312 1.1 augustss
313 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
314 1.254.2.35 skrll .upm_init = ohci_device_intr_init,
315 1.254.2.35 skrll .upm_fini = ohci_device_intr_fini,
316 1.254.2.5 skrll .upm_transfer = ohci_device_intr_transfer,
317 1.254.2.5 skrll .upm_start = ohci_device_intr_start,
318 1.254.2.5 skrll .upm_abort = ohci_device_intr_abort,
319 1.254.2.5 skrll .upm_close = ohci_device_intr_close,
320 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
321 1.254.2.5 skrll .upm_done = ohci_device_intr_done,
322 1.1 augustss };
323 1.1 augustss
324 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
325 1.254.2.35 skrll .upm_init = ohci_device_bulk_init,
326 1.254.2.35 skrll .upm_fini = ohci_device_bulk_fini,
327 1.254.2.5 skrll .upm_transfer = ohci_device_bulk_transfer,
328 1.254.2.5 skrll .upm_start = ohci_device_bulk_start,
329 1.254.2.5 skrll .upm_abort = ohci_device_bulk_abort,
330 1.254.2.5 skrll .upm_close = ohci_device_bulk_close,
331 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
332 1.254.2.5 skrll .upm_done = ohci_device_bulk_done,
333 1.3 augustss };
334 1.3 augustss
335 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
336 1.254.2.35 skrll .upm_init = ohci_device_isoc_init,
337 1.254.2.35 skrll .upm_fini = ohci_device_isoc_fini,
338 1.254.2.5 skrll .upm_transfer = ohci_device_isoc_transfer,
339 1.254.2.5 skrll .upm_abort = ohci_device_isoc_abort,
340 1.254.2.5 skrll .upm_close = ohci_device_isoc_close,
341 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
342 1.254.2.5 skrll .upm_done = ohci_device_isoc_done,
343 1.43 augustss };
344 1.43 augustss
345 1.47 augustss int
346 1.189 dyoung ohci_activate(device_t self, enum devact act)
347 1.47 augustss {
348 1.189 dyoung struct ohci_softc *sc = device_private(self);
349 1.47 augustss
350 1.47 augustss switch (act) {
351 1.47 augustss case DVACT_DEACTIVATE:
352 1.183 kiyohara sc->sc_dying = 1;
353 1.203 dyoung return 0;
354 1.203 dyoung default:
355 1.203 dyoung return EOPNOTSUPP;
356 1.47 augustss }
357 1.47 augustss }
358 1.47 augustss
359 1.187 dyoung void
360 1.187 dyoung ohci_childdet(device_t self, device_t child)
361 1.187 dyoung {
362 1.187 dyoung struct ohci_softc *sc = device_private(self);
363 1.187 dyoung
364 1.187 dyoung KASSERT(sc->sc_child == child);
365 1.187 dyoung sc->sc_child = NULL;
366 1.187 dyoung }
367 1.187 dyoung
368 1.47 augustss int
369 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
370 1.47 augustss {
371 1.47 augustss int rv = 0;
372 1.47 augustss
373 1.47 augustss if (sc->sc_child != NULL)
374 1.47 augustss rv = config_detach(sc->sc_child, flags);
375 1.120 augustss
376 1.47 augustss if (rv != 0)
377 1.254.2.13 skrll return rv;
378 1.47 augustss
379 1.254 ozaki callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
380 1.104 augustss
381 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
382 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
383 1.116 augustss
384 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
385 1.224 mrg
386 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
387 1.224 mrg
388 1.224 mrg mutex_destroy(&sc->sc_lock);
389 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
390 1.224 mrg
391 1.198 cegger if (sc->sc_hcca != NULL)
392 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
393 1.232 christos pool_cache_destroy(sc->sc_xferpool);
394 1.47 augustss
395 1.254.2.13 skrll return rv;
396 1.47 augustss }
397 1.47 augustss
398 1.1 augustss ohci_soft_ed_t *
399 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
400 1.1 augustss {
401 1.1 augustss ohci_soft_ed_t *sed;
402 1.53 augustss usbd_status err;
403 1.1 augustss int i, offs;
404 1.4 augustss usb_dma_t dma;
405 1.1 augustss
406 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
407 1.254.2.18 skrll
408 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
409 1.53 augustss if (sc->sc_freeeds == NULL) {
410 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
411 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
412 1.254.2.35 skrll
413 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
414 1.53 augustss OHCI_ED_ALIGN, &dma);
415 1.53 augustss if (err)
416 1.254.2.13 skrll return 0;
417 1.254.2.35 skrll
418 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
419 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
420 1.39 augustss offs = i * OHCI_SED_SIZE;
421 1.123 augustss sed = KERNADDR(&dma, offs);
422 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
423 1.195 bouyer sed->dma = dma;
424 1.195 bouyer sed->offs = offs;
425 1.1 augustss sed->next = sc->sc_freeeds;
426 1.1 augustss sc->sc_freeeds = sed;
427 1.1 augustss }
428 1.1 augustss }
429 1.1 augustss sed = sc->sc_freeeds;
430 1.1 augustss sc->sc_freeeds = sed->next;
431 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
432 1.254.2.35 skrll
433 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
434 1.1 augustss sed->next = 0;
435 1.254.2.13 skrll return sed;
436 1.1 augustss }
437 1.1 augustss
438 1.254.2.35 skrll static inline void
439 1.254.2.35 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
440 1.1 augustss {
441 1.254.2.35 skrll
442 1.254.2.35 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
443 1.254.2.35 skrll
444 1.1 augustss sed->next = sc->sc_freeeds;
445 1.1 augustss sc->sc_freeeds = sed;
446 1.1 augustss }
447 1.1 augustss
448 1.254.2.35 skrll void
449 1.254.2.35 skrll ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
450 1.254.2.35 skrll {
451 1.254.2.35 skrll
452 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
453 1.254.2.35 skrll ohci_free_sed_locked(sc, sed);
454 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
455 1.254.2.35 skrll }
456 1.254.2.35 skrll
457 1.1 augustss ohci_soft_td_t *
458 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
459 1.1 augustss {
460 1.1 augustss ohci_soft_td_t *std;
461 1.53 augustss usbd_status err;
462 1.1 augustss int i, offs;
463 1.4 augustss usb_dma_t dma;
464 1.1 augustss
465 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
466 1.254.2.18 skrll
467 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
468 1.53 augustss if (sc->sc_freetds == NULL) {
469 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
470 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
471 1.254.2.35 skrll
472 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
473 1.53 augustss OHCI_TD_ALIGN, &dma);
474 1.53 augustss if (err)
475 1.254.2.13 skrll return NULL;
476 1.254.2.35 skrll
477 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
478 1.254.2.58 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
479 1.39 augustss offs = i * OHCI_STD_SIZE;
480 1.123 augustss std = KERNADDR(&dma, offs);
481 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
482 1.195 bouyer std->dma = dma;
483 1.195 bouyer std->offs = offs;
484 1.1 augustss std->nexttd = sc->sc_freetds;
485 1.1 augustss sc->sc_freetds = std;
486 1.1 augustss }
487 1.1 augustss }
488 1.69 augustss
489 1.1 augustss std = sc->sc_freetds;
490 1.1 augustss sc->sc_freetds = std->nexttd;
491 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
492 1.254.2.35 skrll
493 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
494 1.83 augustss std->nexttd = NULL;
495 1.83 augustss std->xfer = NULL;
496 1.69 augustss
497 1.254.2.13 skrll return std;
498 1.1 augustss }
499 1.1 augustss
500 1.1 augustss void
501 1.254.2.35 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
502 1.1 augustss {
503 1.254.2.7 skrll
504 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
505 1.254.2.1 skrll
506 1.1 augustss std->nexttd = sc->sc_freetds;
507 1.1 augustss sc->sc_freetds = std;
508 1.1 augustss }
509 1.1 augustss
510 1.254.2.35 skrll void
511 1.254.2.35 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
512 1.254.2.35 skrll {
513 1.254.2.35 skrll
514 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
515 1.254.2.35 skrll ohci_free_std_locked(sc, std);
516 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
517 1.254.2.35 skrll }
518 1.254.2.35 skrll
519 1.254.2.35 skrll Static usbd_status
520 1.254.2.35 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int alen, int rd)
521 1.48 augustss {
522 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
523 1.254.2.35 skrll struct usbd_pipe *pipe = xfer->ux_pipe;
524 1.48 augustss ohci_soft_td_t *next, *cur;
525 1.48 augustss ohci_physaddr_t dataphys, dataphysend;
526 1.254.2.1 skrll uint32_t tdflags;
527 1.254.2.35 skrll int len = alen;
528 1.254.2.35 skrll int curlen;
529 1.254.2.7 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
530 1.254.2.7 skrll uint16_t flags = xfer->ux_flags;
531 1.48 augustss
532 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
533 1.224 mrg
534 1.254.2.18 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
535 1.254.2.35 skrll pipe->up_dev->ud_addr,
536 1.254.2.35 skrll UE_GET_ADDR(pipe->up_endpoint->ue_edesc->bEndpointAddress),
537 1.254.2.35 skrll alen, pipe->up_dev->ud_speed);
538 1.254.2.35 skrll
539 1.254.2.35 skrll ASSERT_SLEEPABLE();
540 1.254.2.35 skrll
541 1.254.2.35 skrll size_t nstd = (flags & USBD_FORCE_SHORT_XFER) ? 1 : 0;
542 1.254.2.35 skrll nstd += ((len + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
543 1.254.2.35 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
544 1.254.2.35 skrll KM_SLEEP);
545 1.254.2.35 skrll ox->ox_nstd = nstd;
546 1.254.2.35 skrll int mps = UGETW(pipe->up_endpoint->ue_edesc->wMaxPacketSize);
547 1.254.2.35 skrll
548 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d mps %d", xfer, nstd, mps, 0);
549 1.254.2.18 skrll
550 1.75 augustss len = alen;
551 1.254.2.35 skrll cur = ohci_alloc_std(sc);
552 1.254.2.35 skrll if (cur == NULL)
553 1.254.2.35 skrll goto nomem;
554 1.254.2.35 skrll
555 1.125 augustss dataphys = DMAADDR(dma, 0);
556 1.48 augustss dataphysend = OHCI_PAGE(dataphys + len - 1);
557 1.168 augustss tdflags = HTOO32(
558 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
559 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
560 1.61 augustss
561 1.254.2.35 skrll for (size_t j = 0;;) {
562 1.254.2.35 skrll ox->ox_stds[j++] = cur;
563 1.48 augustss next = ohci_alloc_std(sc);
564 1.75 augustss if (next == NULL)
565 1.61 augustss goto nomem;
566 1.48 augustss
567 1.48 augustss /* The OHCI hardware can handle at most one page crossing. */
568 1.48 augustss if (OHCI_PAGE(dataphys) == dataphysend ||
569 1.48 augustss OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
570 1.48 augustss /* we can handle it in this TD */
571 1.48 augustss curlen = len;
572 1.48 augustss } else {
573 1.48 augustss /* must use multiple TDs, fill as much as possible. */
574 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
575 1.48 augustss (dataphys & (OHCI_PAGE_SIZE-1));
576 1.78 augustss /* the length must be a multiple of the max size */
577 1.254.2.35 skrll curlen -= curlen % mps;
578 1.254.2.24 skrll KASSERT(curlen != 0);
579 1.48 augustss }
580 1.254.2.18 skrll DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x "
581 1.254.2.18 skrll "len=%d curlen=%d", dataphys, dataphysend, len, curlen);
582 1.48 augustss len -= curlen;
583 1.48 augustss
584 1.77 augustss cur->td.td_flags = tdflags;
585 1.168 augustss cur->td.td_cbp = HTOO32(dataphys);
586 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
587 1.168 augustss cur->td.td_be = HTOO32(dataphys + curlen - 1);
588 1.254.2.33 skrll cur->nexttd = next;
589 1.48 augustss cur->len = curlen;
590 1.48 augustss cur->flags = OHCI_ADD_LEN;
591 1.77 augustss cur->xfer = xfer;
592 1.254.2.35 skrll
593 1.254.2.18 skrll DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys,
594 1.254.2.18 skrll dataphys + curlen - 1, 0, 0);
595 1.48 augustss if (len == 0)
596 1.48 augustss break;
597 1.254.2.18 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
598 1.48 augustss dataphys += curlen;
599 1.48 augustss cur = next;
600 1.48 augustss }
601 1.164 augustss if (!rd && (flags & USBD_FORCE_SHORT_XFER) &&
602 1.254.2.35 skrll alen % mps == 0) {
603 1.61 augustss /* Force a 0 length transfer at the end. */
604 1.75 augustss
605 1.75 augustss cur = next;
606 1.61 augustss next = ohci_alloc_std(sc);
607 1.75 augustss if (next == NULL)
608 1.61 augustss goto nomem;
609 1.61 augustss
610 1.77 augustss cur->td.td_flags = tdflags;
611 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
612 1.168 augustss cur->td.td_nexttd = HTOO32(next->physaddr);
613 1.75 augustss cur->td.td_be = ~0;
614 1.254.2.33 skrll cur->nexttd = next;
615 1.61 augustss cur->len = 0;
616 1.61 augustss cur->flags = 0;
617 1.77 augustss cur->xfer = xfer;
618 1.254.2.35 skrll
619 1.254.2.18 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
620 1.61 augustss }
621 1.48 augustss
622 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
623 1.61 augustss
624 1.61 augustss nomem:
625 1.254.2.35 skrll ohci_free_stds(sc, ox);
626 1.236 skrll
627 1.254.2.13 skrll return USBD_NOMEM;
628 1.48 augustss }
629 1.48 augustss
630 1.82 augustss Static void
631 1.254.2.35 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
632 1.48 augustss {
633 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
634 1.254.2.35 skrll DPRINTF("ox=%p", ox, 0, 0, 0);
635 1.48 augustss
636 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
637 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
638 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
639 1.254.2.35 skrll if (std == NULL)
640 1.254.2.35 skrll break;
641 1.254.2.35 skrll ohci_free_std_locked(sc, std);
642 1.254.2.35 skrll }
643 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
644 1.254.2.35 skrll }
645 1.254.2.35 skrll
646 1.254.2.35 skrll void
647 1.254.2.35 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
648 1.254.2.35 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
649 1.254.2.35 skrll {
650 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
651 1.254.2.35 skrll ohci_soft_td_t *next, *cur;
652 1.254.2.35 skrll ohci_physaddr_t dataphys, dataphysend;
653 1.254.2.35 skrll uint32_t tdflags;
654 1.254.2.35 skrll int len, curlen;
655 1.254.2.35 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
656 1.254.2.35 skrll uint16_t flags = xfer->ux_flags;
657 1.254.2.35 skrll
658 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
659 1.254.2.35 skrll DPRINTF("start len=%d", alen, 0, 0, 0);
660 1.254.2.35 skrll
661 1.254.2.35 skrll KASSERT(mutex_owned(&sc->sc_lock));
662 1.254.2.35 skrll
663 1.254.2.35 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
664 1.254.2.35 skrll xfer->ux_pipe->up_dev->ud_addr,
665 1.254.2.35 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
666 1.254.2.35 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
667 1.254.2.35 skrll
668 1.254.2.35 skrll KASSERT(sp);
669 1.254.2.35 skrll
670 1.254.2.35 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
671 1.254.2.35 skrll
672 1.254.2.35 skrll len = alen;
673 1.254.2.35 skrll cur = sp;
674 1.254.2.35 skrll
675 1.254.2.35 skrll dataphys = DMAADDR(dma, 0);
676 1.254.2.35 skrll dataphysend = OHCI_PAGE(dataphys + len - 1);
677 1.254.2.35 skrll usb_syncmem(dma, 0, len,
678 1.254.2.35 skrll rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
679 1.254.2.35 skrll tdflags = HTOO32(
680 1.254.2.35 skrll (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
681 1.254.2.35 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
682 1.254.2.35 skrll
683 1.254.2.35 skrll for (size_t j = 1;;) {
684 1.254.2.35 skrll if (j == ox->ox_nstd)
685 1.254.2.35 skrll next = NULL;
686 1.254.2.35 skrll else
687 1.254.2.35 skrll next = ox->ox_stds[j++];
688 1.254.2.35 skrll KASSERT(next != cur);
689 1.254.2.35 skrll
690 1.254.2.35 skrll /* The OHCI hardware can handle at most one page crossing. */
691 1.254.2.35 skrll if (OHCI_PAGE(dataphys) == dataphysend ||
692 1.254.2.35 skrll OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) {
693 1.254.2.35 skrll /* we can handle it in this TD */
694 1.254.2.35 skrll curlen = len;
695 1.254.2.35 skrll } else {
696 1.254.2.35 skrll /* must use multiple TDs, fill as much as possible. */
697 1.254.2.35 skrll curlen = 2 * OHCI_PAGE_SIZE -
698 1.254.2.35 skrll (dataphys & (OHCI_PAGE_SIZE - 1));
699 1.254.2.35 skrll /* the length must be a multiple of the max size */
700 1.254.2.35 skrll curlen -= curlen % mps;
701 1.254.2.35 skrll KASSERT(curlen != 0);
702 1.254.2.35 skrll }
703 1.254.2.35 skrll DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x "
704 1.254.2.35 skrll "len=%d curlen=%d", dataphys, dataphysend, len, curlen);
705 1.254.2.35 skrll len -= curlen;
706 1.254.2.35 skrll
707 1.254.2.35 skrll cur->td.td_flags = tdflags;
708 1.254.2.35 skrll cur->td.td_cbp = HTOO32(dataphys);
709 1.254.2.35 skrll cur->td.td_be = HTOO32(dataphys + curlen - 1);
710 1.254.2.35 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
711 1.254.2.35 skrll cur->nexttd = next;
712 1.254.2.35 skrll cur->len = curlen;
713 1.254.2.35 skrll cur->flags = OHCI_ADD_LEN;
714 1.254.2.35 skrll cur->xfer = xfer;
715 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
716 1.254.2.35 skrll
717 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
718 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
719 1.254.2.35 skrll DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys,
720 1.254.2.35 skrll dataphys + curlen - 1, 0, 0);
721 1.254.2.35 skrll if (len == 0)
722 1.254.2.35 skrll break;
723 1.254.2.35 skrll KASSERT(next != NULL);
724 1.254.2.35 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
725 1.254.2.35 skrll dataphys += curlen;
726 1.254.2.35 skrll cur = next;
727 1.254.2.35 skrll }
728 1.254.2.44 skrll cur->td.td_flags |=
729 1.254.2.44 skrll (xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
730 1.254.2.44 skrll
731 1.254.2.35 skrll if (!rd &&
732 1.254.2.35 skrll (flags & USBD_FORCE_SHORT_XFER) &&
733 1.254.2.35 skrll alen % mps == 0) {
734 1.254.2.35 skrll /* Force a 0 length transfer at the end. */
735 1.254.2.35 skrll
736 1.254.2.35 skrll KASSERT(next != NULL);
737 1.254.2.35 skrll cur = next;
738 1.254.2.35 skrll
739 1.254.2.35 skrll cur->td.td_flags = tdflags;
740 1.254.2.35 skrll cur->td.td_cbp = 0; /* indicate 0 length packet */
741 1.254.2.35 skrll cur->td.td_nexttd = HTOO32(next->physaddr);
742 1.254.2.35 skrll cur->td.td_be = ~0;
743 1.254.2.35 skrll cur->nexttd = NULL;
744 1.254.2.35 skrll cur->len = 0;
745 1.254.2.35 skrll cur->flags = 0;
746 1.254.2.35 skrll cur->xfer = xfer;
747 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
748 1.254.2.35 skrll
749 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
750 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
751 1.254.2.35 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
752 1.48 augustss }
753 1.254.2.35 skrll *ep = cur;
754 1.48 augustss }
755 1.48 augustss
756 1.60 augustss ohci_soft_itd_t *
757 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
758 1.60 augustss {
759 1.60 augustss ohci_soft_itd_t *sitd;
760 1.60 augustss usbd_status err;
761 1.224 mrg int i, offs;
762 1.60 augustss usb_dma_t dma;
763 1.60 augustss
764 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
765 1.254.2.18 skrll
766 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
767 1.60 augustss if (sc->sc_freeitds == NULL) {
768 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
769 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
770 1.254.2.35 skrll
771 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
772 1.83 augustss OHCI_ITD_ALIGN, &dma);
773 1.60 augustss if (err)
774 1.254.2.13 skrll return NULL;
775 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
776 1.254.2.58 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
777 1.83 augustss offs = i * OHCI_SITD_SIZE;
778 1.123 augustss sitd = KERNADDR(&dma, offs);
779 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
780 1.195 bouyer sitd->dma = dma;
781 1.195 bouyer sitd->offs = offs;
782 1.60 augustss sitd->nextitd = sc->sc_freeitds;
783 1.60 augustss sc->sc_freeitds = sitd;
784 1.60 augustss }
785 1.60 augustss }
786 1.83 augustss
787 1.60 augustss sitd = sc->sc_freeitds;
788 1.60 augustss sc->sc_freeitds = sitd->nextitd;
789 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
790 1.254.2.35 skrll
791 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
792 1.83 augustss sitd->nextitd = NULL;
793 1.83 augustss sitd->xfer = NULL;
794 1.83 augustss
795 1.83 augustss #ifdef DIAGNOSTIC
796 1.254.2.52 skrll sitd->isdone = true;
797 1.83 augustss #endif
798 1.83 augustss
799 1.254.2.13 skrll return sitd;
800 1.60 augustss }
801 1.60 augustss
802 1.254.2.35 skrll Static void
803 1.254.2.35 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
804 1.60 augustss {
805 1.83 augustss
806 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
807 1.254.2.18 skrll DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
808 1.83 augustss
809 1.254.2.24 skrll KASSERT(sitd->isdone);
810 1.83 augustss #ifdef DIAGNOSTIC
811 1.134 toshii /* Warn double free */
812 1.254.2.31 skrll sitd->isdone = false;
813 1.83 augustss #endif
814 1.83 augustss
815 1.60 augustss sitd->nextitd = sc->sc_freeitds;
816 1.60 augustss sc->sc_freeitds = sitd;
817 1.60 augustss }
818 1.60 augustss
819 1.254.2.35 skrll void
820 1.254.2.35 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
821 1.254.2.35 skrll {
822 1.254.2.35 skrll
823 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
824 1.254.2.35 skrll
825 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
826 1.254.2.35 skrll ohci_free_sitd_locked(sc, sitd);
827 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
828 1.254.2.35 skrll }
829 1.254.2.35 skrll
830 1.254.2.14 skrll int
831 1.91 augustss ohci_init(ohci_softc_t *sc)
832 1.1 augustss {
833 1.1 augustss ohci_soft_ed_t *sed, *psed;
834 1.53 augustss usbd_status err;
835 1.1 augustss int i;
836 1.254.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
837 1.16 augustss
838 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
839 1.254.2.18 skrll
840 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
841 1.199 jmcneill
842 1.198 cegger sc->sc_hcca = NULL;
843 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
844 1.224 mrg
845 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
846 1.254.2.22 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
847 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
848 1.224 mrg
849 1.224 mrg sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
850 1.224 mrg ohci_rhsc_softint, sc);
851 1.198 cegger
852 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
853 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
854 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
855 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
856 1.198 cegger
857 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
858 1.254.2.37 skrll "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
859 1.198 cegger
860 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
861 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
862 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
863 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
864 1.55 augustss
865 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
866 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
867 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
868 1.254.2.14 skrll return -1;
869 1.1 augustss }
870 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_1_0;
871 1.254.2.7 skrll sc->sc_bus.ub_usedma = true;
872 1.153 fvdl
873 1.73 augustss /* XXX determine alignment by R/W */
874 1.1 augustss /* Allocate the HCCA area. */
875 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
876 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
877 1.198 cegger if (err) {
878 1.198 cegger sc->sc_hcca = NULL;
879 1.198 cegger return err;
880 1.198 cegger }
881 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
882 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
883 1.1 augustss
884 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
885 1.1 augustss
886 1.60 augustss /* Allocate dummy ED that starts the control list. */
887 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
888 1.53 augustss if (sc->sc_ctrl_head == NULL) {
889 1.254.2.14 skrll err = ENOMEM;
890 1.1 augustss goto bad1;
891 1.1 augustss }
892 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
893 1.34 augustss
894 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
895 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
896 1.53 augustss if (sc->sc_bulk_head == NULL) {
897 1.254.2.14 skrll err = ENOMEM;
898 1.1 augustss goto bad2;
899 1.1 augustss }
900 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
901 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
902 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
903 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
904 1.1 augustss
905 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
906 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
907 1.60 augustss if (sc->sc_isoc_head == NULL) {
908 1.254.2.14 skrll err = ENOMEM;
909 1.60 augustss goto bad3;
910 1.60 augustss }
911 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
912 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
913 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
914 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
915 1.60 augustss
916 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
917 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
918 1.1 augustss sed = ohci_alloc_sed(sc);
919 1.53 augustss if (sed == NULL) {
920 1.1 augustss while (--i >= 0)
921 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
922 1.254.2.14 skrll err = ENOMEM;
923 1.60 augustss goto bad4;
924 1.1 augustss }
925 1.1 augustss /* All ED fields are set to 0. */
926 1.1 augustss sc->sc_eds[i] = sed;
927 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
928 1.60 augustss if (i != 0)
929 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
930 1.60 augustss else
931 1.60 augustss psed= sc->sc_isoc_head;
932 1.60 augustss sed->next = psed;
933 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
934 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
935 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
936 1.1 augustss }
937 1.120 augustss /*
938 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
939 1.1 augustss * the tree set up properly to spread the interrupts.
940 1.1 augustss */
941 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
942 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
943 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
944 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
945 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
946 1.1 augustss
947 1.73 augustss #ifdef OHCI_DEBUG
948 1.254.2.18 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
949 1.254.2.39 skrll if (ohcidebug >= 15) {
950 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
951 1.254.2.18 skrll DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
952 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
953 1.73 augustss }
954 1.254.2.18 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
955 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
956 1.73 augustss }
957 1.254.2.18 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
958 1.73 augustss #endif
959 1.73 augustss
960 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
961 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
962 1.161 augustss rwc = ctl & OHCI_RWC;
963 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
964 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
965 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
966 1.161 augustss
967 1.1 augustss /* Determine in what context we are running. */
968 1.1 augustss if (ctl & OHCI_IR) {
969 1.1 augustss /* SMM active, request change */
970 1.254.2.18 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
971 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
972 1.160 augustss (OHCI_OC | OHCI_MIE))
973 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
974 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
975 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
976 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
977 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
978 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
979 1.1 augustss }
980 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
981 1.1 augustss if ((ctl & OHCI_IR) == 0) {
982 1.199 jmcneill aprint_error_dev(sc->sc_dev,
983 1.199 jmcneill "SMM does not respond, resetting\n");
984 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
985 1.1 augustss goto reset;
986 1.1 augustss }
987 1.103 augustss #if 0
988 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
989 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
990 1.1 augustss /* BIOS started controller. */
991 1.254.2.18 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
992 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
993 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
994 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
995 1.1 augustss }
996 1.103 augustss #endif
997 1.1 augustss } else {
998 1.254.2.18 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
999 1.1 augustss reset:
1000 1.1 augustss /* Controller was cold started. */
1001 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
1002 1.1 augustss }
1003 1.1 augustss
1004 1.16 augustss /*
1005 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
1006 1.25 augustss * without it some controllers do not start.
1007 1.16 augustss */
1008 1.254.2.18 skrll DPRINTF("sc %p: resetting", sc, 0, 0, 0);
1009 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
1010 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
1011 1.16 augustss
1012 1.1 augustss /* We now own the host controller and the bus has been reset. */
1013 1.1 augustss
1014 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
1015 1.1 augustss /* Nominal time for a reset is 10 us. */
1016 1.1 augustss for (i = 0; i < 10; i++) {
1017 1.1 augustss delay(10);
1018 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
1019 1.1 augustss if (!hcr)
1020 1.1 augustss break;
1021 1.1 augustss }
1022 1.1 augustss if (hcr) {
1023 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
1024 1.254.2.14 skrll err = EIO;
1025 1.60 augustss goto bad5;
1026 1.1 augustss }
1027 1.52 augustss #ifdef OHCI_DEBUG
1028 1.254.2.39 skrll if (ohcidebug >= 15)
1029 1.1 augustss ohci_dumpregs(sc);
1030 1.1 augustss #endif
1031 1.1 augustss
1032 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
1033 1.1 augustss
1034 1.1 augustss /* Set up HC registers. */
1035 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1036 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
1037 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
1038 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
1039 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
1040 1.55 augustss /* switch on desired functional features */
1041 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
1042 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
1043 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
1044 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
1045 1.1 augustss /* And finally start it! */
1046 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
1047 1.1 augustss
1048 1.1 augustss /*
1049 1.1 augustss * The controller is now OPERATIONAL. Set a some final
1050 1.1 augustss * registers that should be set earlier, but that the
1051 1.1 augustss * controller ignores when in the SUSPEND state.
1052 1.1 augustss */
1053 1.161 augustss ival = OHCI_GET_IVAL(fm);
1054 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
1055 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
1056 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
1057 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
1058 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
1059 1.1 augustss
1060 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
1061 1.249 skrll /* no overcurrent protection */
1062 1.249 skrll desca |= OHCI_NOCP;
1063 1.249 skrll /*
1064 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1065 1.249 skrll * that
1066 1.249 skrll * - ports are always power switched
1067 1.249 skrll * - don't wait for powered root hub port
1068 1.249 skrll */
1069 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1070 1.249 skrll }
1071 1.249 skrll
1072 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1073 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1074 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1075 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1076 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1077 1.1 augustss
1078 1.85 augustss /*
1079 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1080 1.85 augustss * otherwise it will occasionally report 0 ports.
1081 1.85 augustss */
1082 1.145 augustss sc->sc_noport = 0;
1083 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1084 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1085 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1086 1.145 augustss }
1087 1.1 augustss
1088 1.52 augustss #ifdef OHCI_DEBUG
1089 1.254.2.39 skrll if (ohcidebug >= 5)
1090 1.1 augustss ohci_dumpregs(sc);
1091 1.1 augustss #endif
1092 1.120 augustss
1093 1.1 augustss /* Set up the bus struct. */
1094 1.254.2.7 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1095 1.254.2.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1096 1.1 augustss
1097 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1098 1.59 augustss
1099 1.167 augustss /* Finally, turn on interrupts. */
1100 1.254.2.18 skrll DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1101 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1102 1.167 augustss
1103 1.254.2.14 skrll return 0;
1104 1.1 augustss
1105 1.60 augustss bad5:
1106 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1107 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1108 1.60 augustss bad4:
1109 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1110 1.1 augustss bad3:
1111 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1112 1.144 augustss bad2:
1113 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1114 1.1 augustss bad1:
1115 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1116 1.198 cegger sc->sc_hcca = NULL;
1117 1.254.2.13 skrll return err;
1118 1.1 augustss }
1119 1.1 augustss
1120 1.254.2.19 skrll struct usbd_xfer *
1121 1.254.2.23 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1122 1.62 augustss {
1123 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1124 1.254.2.19 skrll struct usbd_xfer *xfer;
1125 1.62 augustss
1126 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
1127 1.118 augustss if (xfer != NULL) {
1128 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1129 1.118 augustss #ifdef DIAGNOSTIC
1130 1.254.2.7 skrll xfer->ux_state = XFER_BUSY;
1131 1.118 augustss #endif
1132 1.118 augustss }
1133 1.254.2.13 skrll return xfer;
1134 1.62 augustss }
1135 1.62 augustss
1136 1.62 augustss void
1137 1.254.2.19 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1138 1.62 augustss {
1139 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1140 1.62 augustss
1141 1.254.2.24 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
1142 1.254.2.24 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1143 1.118 augustss #ifdef DIAGNOSTIC
1144 1.254.2.7 skrll xfer->ux_state = XFER_FREE;
1145 1.118 augustss #endif
1146 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1147 1.42 augustss }
1148 1.42 augustss
1149 1.224 mrg Static void
1150 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1151 1.224 mrg {
1152 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1153 1.224 mrg
1154 1.224 mrg *lock = &sc->sc_lock;
1155 1.224 mrg }
1156 1.224 mrg
1157 1.59 augustss /*
1158 1.59 augustss * Shut down the controller when the system is going down.
1159 1.59 augustss */
1160 1.188 dyoung bool
1161 1.188 dyoung ohci_shutdown(device_t self, int flags)
1162 1.59 augustss {
1163 1.188 dyoung ohci_softc_t *sc = device_private(self);
1164 1.59 augustss
1165 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1166 1.254.2.18 skrll
1167 1.254.2.18 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1168 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1169 1.188 dyoung return true;
1170 1.59 augustss }
1171 1.59 augustss
1172 1.185 jmcneill bool
1173 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1174 1.33 augustss {
1175 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1176 1.185 jmcneill uint32_t ctl;
1177 1.33 augustss
1178 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1179 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1180 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1181 1.224 mrg
1182 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1183 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1184 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1185 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1186 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1187 1.185 jmcneill sc->sc_bulk_head->physaddr);
1188 1.185 jmcneill if (sc->sc_intre)
1189 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1190 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1191 1.185 jmcneill if (sc->sc_control)
1192 1.185 jmcneill ctl = sc->sc_control;
1193 1.185 jmcneill else
1194 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1195 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1196 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1197 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1198 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1199 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1200 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1201 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1202 1.224 mrg
1203 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1204 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1205 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1206 1.185 jmcneill
1207 1.185 jmcneill return true;
1208 1.185 jmcneill }
1209 1.185 jmcneill
1210 1.185 jmcneill bool
1211 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1212 1.185 jmcneill {
1213 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1214 1.185 jmcneill uint32_t ctl;
1215 1.95 augustss
1216 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1217 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1218 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1219 1.224 mrg
1220 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1221 1.185 jmcneill if (sc->sc_control == 0) {
1222 1.185 jmcneill /*
1223 1.185 jmcneill * Preserve register values, in case that BIOS
1224 1.185 jmcneill * does not recover them.
1225 1.185 jmcneill */
1226 1.185 jmcneill sc->sc_control = ctl;
1227 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1228 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1229 1.95 augustss }
1230 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1231 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1232 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1233 1.224 mrg
1234 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1235 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1236 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1237 1.185 jmcneill
1238 1.185 jmcneill return true;
1239 1.33 augustss }
1240 1.33 augustss
1241 1.52 augustss #ifdef OHCI_DEBUG
1242 1.1 augustss void
1243 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1244 1.1 augustss {
1245 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1246 1.254.2.18 skrll
1247 1.254.2.18 skrll DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
1248 1.41 augustss OREAD4(sc, OHCI_REVISION),
1249 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1250 1.254.2.18 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1251 1.254.2.18 skrll DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x",
1252 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1253 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1254 1.254.2.18 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1255 1.254.2.18 skrll DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
1256 1.41 augustss OREAD4(sc, OHCI_HCCA),
1257 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1258 1.254.2.18 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1259 1.254.2.18 skrll DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
1260 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1261 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1262 1.254.2.18 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1263 1.254.2.18 skrll DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x",
1264 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1265 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1266 1.254.2.18 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1267 1.254.2.18 skrll DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
1268 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1269 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1270 1.254.2.18 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1271 1.254.2.18 skrll DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x",
1272 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1273 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1274 1.254.2.18 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1275 1.254.2.18 skrll DPRINTF(" port1=0x%08x port2=0x%08x",
1276 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1277 1.254.2.18 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1278 1.254.2.18 skrll DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x",
1279 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1280 1.254.2.18 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1281 1.1 augustss }
1282 1.1 augustss #endif
1283 1.1 augustss
1284 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1285 1.53 augustss
1286 1.1 augustss int
1287 1.91 augustss ohci_intr(void *p)
1288 1.1 augustss {
1289 1.1 augustss ohci_softc_t *sc = p;
1290 1.224 mrg int ret = 0;
1291 1.111 augustss
1292 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1293 1.254.2.18 skrll
1294 1.224 mrg if (sc == NULL)
1295 1.254.2.13 skrll return 0;
1296 1.53 augustss
1297 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1298 1.224 mrg
1299 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1300 1.224 mrg goto done;
1301 1.224 mrg
1302 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1303 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling) {
1304 1.254.2.18 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1305 1.154 joff /* for level triggered intrs, should do something to ack */
1306 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1307 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1308 1.155 perry
1309 1.224 mrg goto done;
1310 1.57 augustss }
1311 1.53 augustss
1312 1.224 mrg ret = ohci_intr1(sc);
1313 1.224 mrg
1314 1.224 mrg done:
1315 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1316 1.224 mrg return ret;
1317 1.53 augustss }
1318 1.53 augustss
1319 1.82 augustss Static int
1320 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1321 1.53 augustss {
1322 1.254.2.1 skrll uint32_t intrs, eintrs;
1323 1.1 augustss
1324 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1325 1.105 augustss
1326 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1327 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1328 1.15 augustss #ifdef DIAGNOSTIC
1329 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1330 1.15 augustss #endif
1331 1.254.2.13 skrll return 0;
1332 1.15 augustss }
1333 1.15 augustss
1334 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1335 1.224 mrg
1336 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1337 1.1 augustss if (!intrs)
1338 1.254.2.13 skrll return 0;
1339 1.55 augustss
1340 1.254.2.32 skrll /* Acknowledge */
1341 1.254.2.32 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1342 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1343 1.254.2.18 skrll DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
1344 1.254.2.18 skrll DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
1345 1.254.2.18 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1346 1.254.2.18 skrll sc->sc_eintrs);
1347 1.211 matt
1348 1.211 matt if (!eintrs) {
1349 1.254.2.13 skrll return 0;
1350 1.211 matt }
1351 1.1 augustss
1352 1.1 augustss if (eintrs & OHCI_SO) {
1353 1.100 augustss sc->sc_overrun_cnt++;
1354 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1355 1.100 augustss printf("%s: %u scheduling overruns\n",
1356 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1357 1.100 augustss sc->sc_overrun_cnt = 0;
1358 1.100 augustss }
1359 1.1 augustss /* XXX do what */
1360 1.106 augustss eintrs &= ~OHCI_SO;
1361 1.1 augustss }
1362 1.1 augustss if (eintrs & OHCI_WDH) {
1363 1.157 mycroft /*
1364 1.157 mycroft * We block the interrupt below, and reenable it later from
1365 1.157 mycroft * ohci_softintr().
1366 1.157 mycroft */
1367 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1368 1.1 augustss }
1369 1.1 augustss if (eintrs & OHCI_RD) {
1370 1.254.2.47 skrll DPRINTFN(5, "resume detect", sc, 0, 0, 0);
1371 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1372 1.1 augustss /* XXX process resume detect */
1373 1.1 augustss }
1374 1.1 augustss if (eintrs & OHCI_UE) {
1375 1.254.2.47 skrll DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0);
1376 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1377 1.190 drochner device_xname(sc->sc_dev));
1378 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1379 1.1 augustss /* XXX what else */
1380 1.1 augustss }
1381 1.1 augustss if (eintrs & OHCI_RHSC) {
1382 1.120 augustss /*
1383 1.157 mycroft * We block the interrupt below, and reenable it later from
1384 1.157 mycroft * a timeout.
1385 1.1 augustss */
1386 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1387 1.1 augustss }
1388 1.1 augustss
1389 1.106 augustss if (eintrs != 0) {
1390 1.157 mycroft /* Block unprocessed interrupts. */
1391 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1392 1.106 augustss sc->sc_eintrs &= ~eintrs;
1393 1.254.2.18 skrll DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0);
1394 1.106 augustss }
1395 1.1 augustss
1396 1.254.2.13 skrll return 1;
1397 1.1 augustss }
1398 1.1 augustss
1399 1.1 augustss void
1400 1.104 augustss ohci_rhsc_enable(void *v_sc)
1401 1.104 augustss {
1402 1.104 augustss ohci_softc_t *sc = v_sc;
1403 1.104 augustss
1404 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1405 1.254.2.18 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1406 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1407 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1408 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1409 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1410 1.1 augustss }
1411 1.1 augustss
1412 1.52 augustss #ifdef OHCI_DEBUG
1413 1.166 drochner const char *ohci_cc_strs[] = {
1414 1.13 augustss "NO_ERROR",
1415 1.13 augustss "CRC",
1416 1.13 augustss "BIT_STUFFING",
1417 1.13 augustss "DATA_TOGGLE_MISMATCH",
1418 1.13 augustss "STALL",
1419 1.13 augustss "DEVICE_NOT_RESPONDING",
1420 1.13 augustss "PID_CHECK_FAILURE",
1421 1.13 augustss "UNEXPECTED_PID",
1422 1.13 augustss "DATA_OVERRUN",
1423 1.13 augustss "DATA_UNDERRUN",
1424 1.13 augustss "BUFFER_OVERRUN",
1425 1.13 augustss "BUFFER_UNDERRUN",
1426 1.67 augustss "reserved",
1427 1.67 augustss "reserved",
1428 1.67 augustss "NOT_ACCESSED",
1429 1.13 augustss "NOT_ACCESSED",
1430 1.13 augustss };
1431 1.13 augustss #endif
1432 1.13 augustss
1433 1.1 augustss void
1434 1.157 mycroft ohci_softintr(void *v)
1435 1.83 augustss {
1436 1.190 drochner struct usbd_bus *bus = v;
1437 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1438 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1439 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1440 1.254.2.19 skrll struct usbd_xfer *xfer;
1441 1.157 mycroft struct ohci_pipe *opipe;
1442 1.224 mrg int len, cc;
1443 1.157 mycroft int i, j, actlen, iframes, uedir;
1444 1.157 mycroft ohci_physaddr_t done;
1445 1.157 mycroft
1446 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1447 1.224 mrg
1448 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1449 1.157 mycroft
1450 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1451 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1452 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1453 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1454 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1455 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1456 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1457 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1458 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1459 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1460 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1461 1.83 augustss
1462 1.83 augustss /* Reverse the done list. */
1463 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1464 1.83 augustss std = ohci_hash_find_td(sc, done);
1465 1.83 augustss if (std != NULL) {
1466 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1467 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1468 1.83 augustss std->dnext = sdone;
1469 1.168 augustss done = O32TOH(std->td.td_nexttd);
1470 1.83 augustss sdone = std;
1471 1.254.2.18 skrll DPRINTFN(10, "add TD %p", std, 0, 0, 0);
1472 1.83 augustss continue;
1473 1.83 augustss }
1474 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1475 1.83 augustss if (sitd != NULL) {
1476 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1477 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1478 1.83 augustss sitd->dnext = sidone;
1479 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1480 1.83 augustss sidone = sitd;
1481 1.254.2.18 skrll DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
1482 1.83 augustss continue;
1483 1.83 augustss }
1484 1.254.2.57 skrll DPRINTFN(10, "addr %p not found", done, 0, 0, 0);
1485 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1486 1.218 jmcneill (u_long)done);
1487 1.218 jmcneill break;
1488 1.83 augustss }
1489 1.83 augustss
1490 1.254.2.18 skrll DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
1491 1.254.2.41 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1492 1.52 augustss #ifdef OHCI_DEBUG
1493 1.254.2.39 skrll if (ohcidebug >= 10) {
1494 1.234 skrll for (std = sdone; std; std = std->dnext)
1495 1.254.2.1 skrll ohci_dump_td(sc, std);
1496 1.1 augustss }
1497 1.1 augustss #endif
1498 1.254.2.41 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1499 1.1 augustss
1500 1.48 augustss for (std = sdone; std; std = stdnext) {
1501 1.53 augustss xfer = std->xfer;
1502 1.48 augustss stdnext = std->dnext;
1503 1.254.2.18 skrll DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer,
1504 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1505 1.71 augustss if (xfer == NULL) {
1506 1.117 augustss /*
1507 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1508 1.71 augustss * with this TD. It is tailp that happened to end up on
1509 1.71 augustss * the done queue.
1510 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1511 1.71 augustss */
1512 1.71 augustss continue;
1513 1.71 augustss }
1514 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1515 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1516 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1517 1.38 augustss /* Handled by abort routine. */
1518 1.83 augustss continue;
1519 1.83 augustss }
1520 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
1521 1.141 mycroft
1522 1.141 mycroft len = std->len;
1523 1.141 mycroft if (std->td.td_cbp != 0)
1524 1.168 augustss len -= O32TOH(std->td.td_be) -
1525 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1526 1.254.2.18 skrll DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
1527 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1528 1.254.2.7 skrll xfer->ux_actlen += len;
1529 1.141 mycroft
1530 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1531 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1532 1.254.2.42 skrll ohci_hash_rem_td(sc, std);
1533 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1534 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1535 1.53 augustss usb_transfer_complete(xfer);
1536 1.21 augustss }
1537 1.1 augustss } else {
1538 1.48 augustss /*
1539 1.48 augustss * Endpoint is halted. First unlink all the TDs
1540 1.48 augustss * belonging to the failed transfer, and then restart
1541 1.48 augustss * the endpoint.
1542 1.48 augustss */
1543 1.1 augustss ohci_soft_td_t *p, *n;
1544 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1545 1.48 augustss
1546 1.254.2.43 skrll DPRINTFN(10, "error cc=%d", cc, 0, 0, 0);
1547 1.48 augustss
1548 1.254.2.35 skrll /* remove xfer's TDs from the hash */
1549 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1550 1.1 augustss n = p->nexttd;
1551 1.254.2.35 skrll ohci_hash_rem_td(sc, p);
1552 1.1 augustss }
1553 1.48 augustss
1554 1.254.2.44 skrll ohci_soft_ed_t *sed = opipe->sed;
1555 1.254.2.44 skrll
1556 1.254.2.44 skrll /* clear halt and TD chain */
1557 1.254.2.44 skrll sed->ed.ed_headp = HTOO32(p->physaddr);
1558 1.254.2.45 skrll usb_syncmem(&sed->dma,
1559 1.254.2.46 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1560 1.254.2.45 skrll sizeof(sed->ed.ed_headp),
1561 1.254.2.44 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1562 1.254.2.44 skrll
1563 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1564 1.48 augustss
1565 1.254.2.44 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1566 1.254.2.44 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1567 1.254.2.44 skrll else if (cc == OHCI_CC_STALL)
1568 1.254.2.7 skrll xfer->ux_status = USBD_STALLED;
1569 1.1 augustss else
1570 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1571 1.53 augustss usb_transfer_complete(xfer);
1572 1.1 augustss }
1573 1.1 augustss }
1574 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1575 1.83 augustss #ifdef OHCI_DEBUG
1576 1.254.2.39 skrll if (ohcidebug >= 10) {
1577 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1578 1.254.2.1 skrll ohci_dump_itd(sc, sitd);
1579 1.83 augustss }
1580 1.83 augustss #endif
1581 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1582 1.83 augustss
1583 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1584 1.83 augustss xfer = sitd->xfer;
1585 1.83 augustss sitdnext = sitd->dnext;
1586 1.254.2.18 skrll DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
1587 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1588 1.83 augustss if (xfer == NULL)
1589 1.83 augustss continue;
1590 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1591 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1592 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1593 1.83 augustss /* Handled by abort routine. */
1594 1.83 augustss continue;
1595 1.83 augustss }
1596 1.254.2.24 skrll KASSERT(!sitd->isdone);
1597 1.83 augustss #ifdef DIAGNOSTIC
1598 1.254.2.31 skrll sitd->isdone = true;
1599 1.83 augustss #endif
1600 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1601 1.134 toshii ohci_soft_itd_t *next;
1602 1.134 toshii
1603 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1604 1.254.2.21 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1605 1.254.2.7 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1606 1.134 toshii bEndpointAddress);
1607 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1608 1.134 toshii actlen = 0;
1609 1.254.2.7 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1610 1.134 toshii sitd = next) {
1611 1.134 toshii next = sitd->nextitd;
1612 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1613 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1614 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1615 1.134 toshii /* For input, update frlengths with actual */
1616 1.134 toshii /* XXX anything necessary for output? */
1617 1.134 toshii if (uedir == UE_DIR_IN &&
1618 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1619 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1620 1.135 toshii sitd->itd.itd_flags));
1621 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1622 1.168 augustss len = O16TOH(sitd->
1623 1.134 toshii itd.itd_offset[j]);
1624 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1625 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1626 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1627 1.158 toshii len = 0;
1628 1.158 toshii else
1629 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1630 1.254.2.7 skrll xfer->ux_frlengths[i] = len;
1631 1.134 toshii actlen += len;
1632 1.134 toshii }
1633 1.134 toshii }
1634 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1635 1.134 toshii break;
1636 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1637 1.254.2.35 skrll
1638 1.83 augustss }
1639 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1640 1.134 toshii if (uedir == UE_DIR_IN &&
1641 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1642 1.254.2.7 skrll xfer->ux_actlen = actlen;
1643 1.254.2.7 skrll xfer->ux_hcpriv = NULL;
1644 1.134 toshii
1645 1.83 augustss usb_transfer_complete(xfer);
1646 1.83 augustss }
1647 1.83 augustss }
1648 1.83 augustss
1649 1.119 augustss if (sc->sc_softwake) {
1650 1.119 augustss sc->sc_softwake = 0;
1651 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1652 1.119 augustss }
1653 1.119 augustss
1654 1.254.2.18 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1655 1.1 augustss }
1656 1.1 augustss
1657 1.1 augustss void
1658 1.254.2.19 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1659 1.1 augustss {
1660 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1661 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1662 1.254.2.7 skrll int len = UGETW(xfer->ux_request.wLength);
1663 1.254.2.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1664 1.195 bouyer
1665 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1666 1.254.2.18 skrll DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
1667 1.1 augustss
1668 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1669 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1670 1.224 mrg
1671 1.195 bouyer if (len)
1672 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1673 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1674 1.254.2.30 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1675 1.254.2.30 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1676 1.1 augustss }
1677 1.1 augustss
1678 1.1 augustss void
1679 1.254.2.19 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1680 1.1 augustss {
1681 1.254.2.54 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1682 1.195 bouyer int isread =
1683 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1684 1.1 augustss
1685 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1686 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1687 1.1 augustss
1688 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1689 1.224 mrg
1690 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1691 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1692 1.1 augustss }
1693 1.1 augustss
1694 1.1 augustss void
1695 1.254.2.19 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1696 1.3 augustss {
1697 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1698 1.254.2.25 skrll
1699 1.195 bouyer int isread =
1700 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1701 1.195 bouyer
1702 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1703 1.224 mrg
1704 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1705 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1706 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1707 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1708 1.3 augustss }
1709 1.3 augustss
1710 1.224 mrg Static void
1711 1.224 mrg ohci_rhsc_softint(void *arg)
1712 1.224 mrg {
1713 1.224 mrg ohci_softc_t *sc = arg;
1714 1.224 mrg
1715 1.224 mrg mutex_enter(&sc->sc_lock);
1716 1.224 mrg
1717 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1718 1.224 mrg
1719 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1720 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1721 1.224 mrg
1722 1.224 mrg mutex_exit(&sc->sc_lock);
1723 1.224 mrg }
1724 1.224 mrg
1725 1.3 augustss void
1726 1.254.2.19 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1727 1.1 augustss {
1728 1.1 augustss u_char *p;
1729 1.1 augustss int i, m;
1730 1.243 martin int hstatus __unused;
1731 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1732 1.1 augustss
1733 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1734 1.224 mrg
1735 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1736 1.254.2.18 skrll DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0);
1737 1.1 augustss
1738 1.53 augustss if (xfer == NULL) {
1739 1.1 augustss /* Just ignore the change. */
1740 1.1 augustss return;
1741 1.1 augustss }
1742 1.1 augustss
1743 1.254.2.7 skrll p = xfer->ux_buf;
1744 1.254.2.7 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1745 1.254.2.7 skrll memset(p, 0, xfer->ux_length);
1746 1.1 augustss for (i = 1; i <= m; i++) {
1747 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1748 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1749 1.1 augustss p[i/8] |= 1 << (i%8);
1750 1.1 augustss }
1751 1.254.2.18 skrll DPRINTF("change=0x%02x", *p, 0, 0, 0);
1752 1.254.2.7 skrll xfer->ux_actlen = xfer->ux_length;
1753 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1754 1.1 augustss
1755 1.53 augustss usb_transfer_complete(xfer);
1756 1.38 augustss }
1757 1.38 augustss
1758 1.38 augustss void
1759 1.254.2.19 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1760 1.65 augustss {
1761 1.254.2.54 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1762 1.254.2.54 skrll
1763 1.254.2.54 skrll KASSERT(mutex_owned(&sc->sc_lock));
1764 1.254.2.54 skrll
1765 1.254.2.54 skrll KASSERT(sc->sc_intrxfer == xfer);
1766 1.254.2.54 skrll sc->sc_intrxfer = NULL;
1767 1.65 augustss }
1768 1.65 augustss
1769 1.1 augustss /*
1770 1.1 augustss * Wait here until controller claims to have an interrupt.
1771 1.1 augustss * Then call ohci_intr and return. Use timeout to avoid waiting
1772 1.1 augustss * too long.
1773 1.1 augustss */
1774 1.1 augustss void
1775 1.254.2.19 skrll ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer)
1776 1.1 augustss {
1777 1.163 augustss int timo;
1778 1.254.2.1 skrll uint32_t intrs;
1779 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1780 1.1 augustss
1781 1.224 mrg mutex_enter(&sc->sc_lock);
1782 1.224 mrg
1783 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1784 1.254.2.7 skrll for (timo = xfer->ux_timeout; timo >= 0; timo--) {
1785 1.20 augustss usb_delay_ms(&sc->sc_bus, 1);
1786 1.116 augustss if (sc->sc_dying)
1787 1.116 augustss break;
1788 1.1 augustss intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
1789 1.254.2.18 skrll DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0);
1790 1.52 augustss #ifdef OHCI_DEBUG
1791 1.1 augustss if (ohcidebug > 15)
1792 1.1 augustss ohci_dumpregs(sc);
1793 1.1 augustss #endif
1794 1.1 augustss if (intrs) {
1795 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1796 1.53 augustss ohci_intr1(sc);
1797 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1798 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1799 1.230 jmcneill goto done;
1800 1.1 augustss }
1801 1.1 augustss }
1802 1.15 augustss
1803 1.15 augustss /* Timeout */
1804 1.254.2.18 skrll DPRINTF("timeout", 0, 0, 0, 0);
1805 1.254.2.7 skrll xfer->ux_status = USBD_TIMEOUT;
1806 1.53 augustss usb_transfer_complete(xfer);
1807 1.224 mrg
1808 1.230 jmcneill done:
1809 1.224 mrg mutex_exit(&sc->sc_lock);
1810 1.5 augustss }
1811 1.5 augustss
1812 1.5 augustss void
1813 1.91 augustss ohci_poll(struct usbd_bus *bus)
1814 1.5 augustss {
1815 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1816 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1817 1.254.2.18 skrll
1818 1.105 augustss #ifdef OHCI_DEBUG
1819 1.105 augustss static int last;
1820 1.105 augustss int new;
1821 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1822 1.105 augustss if (new != last) {
1823 1.254.2.18 skrll DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0);
1824 1.105 augustss last = new;
1825 1.105 augustss }
1826 1.105 augustss #endif
1827 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1828 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1829 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1830 1.53 augustss ohci_intr1(sc);
1831 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1832 1.224 mrg }
1833 1.1 augustss }
1834 1.1 augustss
1835 1.1 augustss /*
1836 1.224 mrg * Add an ED to the schedule. Called with USB lock held.
1837 1.1 augustss */
1838 1.224 mrg Static void
1839 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1840 1.1 augustss {
1841 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1842 1.254.2.18 skrll DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0);
1843 1.113 augustss
1844 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1845 1.224 mrg
1846 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1847 1.195 bouyer sizeof(head->ed.ed_nexted),
1848 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1849 1.1 augustss sed->next = head->next;
1850 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1851 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1852 1.195 bouyer sizeof(sed->ed.ed_nexted),
1853 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1854 1.1 augustss head->next = sed;
1855 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1856 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1857 1.195 bouyer sizeof(head->ed.ed_nexted),
1858 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1859 1.1 augustss }
1860 1.1 augustss
1861 1.1 augustss /*
1862 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1863 1.3 augustss */
1864 1.224 mrg Static void
1865 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1866 1.3 augustss {
1867 1.120 augustss ohci_soft_ed_t *p;
1868 1.3 augustss
1869 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1870 1.224 mrg
1871 1.3 augustss /* XXX */
1872 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1873 1.3 augustss ;
1874 1.254.2.20 skrll KASSERT(p != NULL);
1875 1.254.2.20 skrll
1876 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1877 1.195 bouyer sizeof(sed->ed.ed_nexted),
1878 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1879 1.3 augustss p->next = sed->next;
1880 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1881 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1882 1.195 bouyer sizeof(p->ed.ed_nexted),
1883 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1884 1.3 augustss }
1885 1.3 augustss
1886 1.3 augustss /*
1887 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1888 1.1 augustss * the host controller. This queue is the processed by software.
1889 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1890 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1891 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1892 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1893 1.1 augustss * hash value.
1894 1.1 augustss */
1895 1.1 augustss
1896 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1897 1.224 mrg /* Called with USB lock held. */
1898 1.1 augustss void
1899 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1900 1.1 augustss {
1901 1.1 augustss int h = HASH(std->physaddr);
1902 1.1 augustss
1903 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1904 1.224 mrg
1905 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1906 1.1 augustss }
1907 1.1 augustss
1908 1.224 mrg /* Called with USB lock held. */
1909 1.1 augustss void
1910 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1911 1.1 augustss {
1912 1.46 augustss
1913 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1914 1.224 mrg
1915 1.1 augustss LIST_REMOVE(std, hnext);
1916 1.1 augustss }
1917 1.1 augustss
1918 1.1 augustss ohci_soft_td_t *
1919 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1920 1.1 augustss {
1921 1.1 augustss int h = HASH(a);
1922 1.1 augustss ohci_soft_td_t *std;
1923 1.1 augustss
1924 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1925 1.53 augustss std != NULL;
1926 1.1 augustss std = LIST_NEXT(std, hnext))
1927 1.1 augustss if (std->physaddr == a)
1928 1.254.2.13 skrll return std;
1929 1.254.2.13 skrll return NULL;
1930 1.83 augustss }
1931 1.83 augustss
1932 1.224 mrg /* Called with USB lock held. */
1933 1.83 augustss void
1934 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1935 1.83 augustss {
1936 1.83 augustss int h = HASH(sitd->physaddr);
1937 1.83 augustss
1938 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1939 1.254.2.18 skrll
1940 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1941 1.224 mrg
1942 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1943 1.254.2.18 skrll 0, 0);
1944 1.83 augustss
1945 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1946 1.83 augustss }
1947 1.83 augustss
1948 1.224 mrg /* Called with USB lock held. */
1949 1.83 augustss void
1950 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1951 1.83 augustss {
1952 1.83 augustss
1953 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1954 1.254.2.18 skrll
1955 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1956 1.224 mrg
1957 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1958 1.254.2.18 skrll 0, 0);
1959 1.83 augustss
1960 1.83 augustss LIST_REMOVE(sitd, hnext);
1961 1.83 augustss }
1962 1.83 augustss
1963 1.83 augustss ohci_soft_itd_t *
1964 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1965 1.83 augustss {
1966 1.83 augustss int h = HASH(a);
1967 1.83 augustss ohci_soft_itd_t *sitd;
1968 1.83 augustss
1969 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1970 1.83 augustss sitd != NULL;
1971 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1972 1.83 augustss if (sitd->physaddr == a)
1973 1.254.2.13 skrll return sitd;
1974 1.254.2.13 skrll return NULL;
1975 1.1 augustss }
1976 1.1 augustss
1977 1.1 augustss void
1978 1.91 augustss ohci_timeout(void *addr)
1979 1.1 augustss {
1980 1.254.2.25 skrll struct usbd_xfer *xfer = addr;
1981 1.254.2.25 skrll struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer);
1982 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1983 1.114 augustss
1984 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1985 1.254.2.18 skrll DPRINTF("oxfer=%p", oxfer, 0, 0, 0);
1986 1.114 augustss
1987 1.116 augustss if (sc->sc_dying) {
1988 1.224 mrg mutex_enter(&sc->sc_lock);
1989 1.254.2.25 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1990 1.224 mrg mutex_exit(&sc->sc_lock);
1991 1.116 augustss return;
1992 1.116 augustss }
1993 1.116 augustss
1994 1.114 augustss /* Execute the abort in a process context. */
1995 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1996 1.231 jmcneill USB_TASKQ_MPSAFE);
1997 1.254.2.25 skrll usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task,
1998 1.178 joerg USB_TASKQ_HC);
1999 1.114 augustss }
2000 1.114 augustss
2001 1.114 augustss void
2002 1.114 augustss ohci_timeout_task(void *addr)
2003 1.114 augustss {
2004 1.254.2.19 skrll struct usbd_xfer *xfer = addr;
2005 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2006 1.1 augustss
2007 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2008 1.254.2.18 skrll
2009 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2010 1.45 augustss
2011 1.224 mrg mutex_enter(&sc->sc_lock);
2012 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
2013 1.224 mrg mutex_exit(&sc->sc_lock);
2014 1.1 augustss }
2015 1.1 augustss
2016 1.52 augustss #ifdef OHCI_DEBUG
2017 1.1 augustss void
2018 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
2019 1.1 augustss {
2020 1.254.2.34 skrll for (; std; std = std->nexttd) {
2021 1.168 augustss ohci_dump_td(sc, std);
2022 1.254.2.34 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
2023 1.254.2.34 skrll "std %p next %p", std, std->nexttd);
2024 1.254.2.34 skrll }
2025 1.1 augustss }
2026 1.1 augustss
2027 1.1 augustss void
2028 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
2029 1.1 augustss {
2030 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2031 1.92 tv
2032 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
2033 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2034 1.254.2.18 skrll
2035 1.254.2.18 skrll uint32_t flags = O32TOH(std->td.td_flags);
2036 1.254.2.40 skrll DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0);
2037 1.254.2.18 skrll DPRINTF(" round=%d DP=%x DI=%x T=%x",
2038 1.254.2.18 skrll !!(flags & OHCI_TD_R),
2039 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
2040 1.254.2.18 skrll OHCI_TD_GET_DI(flags),
2041 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
2042 1.254.2.18 skrll DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags),
2043 1.254.2.18 skrll 0, 0);
2044 1.254.2.47 skrll DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx",
2045 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
2046 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
2047 1.254.2.18 skrll (u_long)O32TOH(std->td.td_be), 0);
2048 1.1 augustss }
2049 1.1 augustss
2050 1.1 augustss void
2051 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2052 1.83 augustss {
2053 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2054 1.83 augustss
2055 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
2056 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2057 1.254.2.18 skrll
2058 1.254.2.18 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
2059 1.254.2.40 skrll DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0);
2060 1.254.2.18 skrll DPRINTF(" sf=%d di=%d fc=%d cc=%d",
2061 1.254.2.18 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
2062 1.254.2.18 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
2063 1.254.2.18 skrll DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x",
2064 1.254.2.18 skrll O32TOH(sitd->itd.itd_bp0),
2065 1.254.2.18 skrll O32TOH(sitd->itd.itd_nextitd),
2066 1.254.2.18 skrll O32TOH(sitd->itd.itd_be), 0);
2067 1.254.2.18 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
2068 1.254.2.18 skrll DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x "
2069 1.254.2.18 skrll "offs[2] = 0x%04x offs[3] = 0x%04x",
2070 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[0]),
2071 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[1]),
2072 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[2]),
2073 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[3]));
2074 1.254.2.18 skrll DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x "
2075 1.254.2.18 skrll "offs[6] = 0x%04x offs[7] = 0x%04x",
2076 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[4]),
2077 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[5]),
2078 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[6]),
2079 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[7]));
2080 1.83 augustss }
2081 1.83 augustss
2082 1.83 augustss void
2083 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2084 1.83 augustss {
2085 1.83 augustss for (; sitd; sitd = sitd->nextitd)
2086 1.168 augustss ohci_dump_itd(sc, sitd);
2087 1.83 augustss }
2088 1.83 augustss
2089 1.83 augustss void
2090 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2091 1.1 augustss {
2092 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2093 1.92 tv
2094 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2095 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2096 1.254.2.18 skrll
2097 1.254.2.18 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
2098 1.254.2.18 skrll DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0);
2099 1.254.2.18 skrll DPRINTF(" addr=%d endpt=%d maxp=%d",
2100 1.254.2.18 skrll OHCI_ED_GET_FA(flags),
2101 1.254.2.18 skrll OHCI_ED_GET_EN(flags),
2102 1.254.2.18 skrll OHCI_ED_GET_MAXP(flags),
2103 1.254.2.18 skrll 0);
2104 1.254.2.18 skrll DPRINTF(" dir=%d speed=%d skip=%d iso=%d",
2105 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
2106 1.254.2.18 skrll !!(flags & OHCI_ED_SPEED),
2107 1.254.2.18 skrll !!(flags & OHCI_ED_SKIP),
2108 1.254.2.18 skrll !!(flags & OHCI_ED_FORMAT_ISO));
2109 1.254.2.18 skrll DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp),
2110 1.254.2.18 skrll 0, 0, 0);
2111 1.254.2.18 skrll DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d",
2112 1.254.2.18 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
2113 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
2114 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2115 1.1 augustss }
2116 1.1 augustss #endif
2117 1.1 augustss
2118 1.1 augustss usbd_status
2119 1.254.2.19 skrll ohci_open(struct usbd_pipe *pipe)
2120 1.1 augustss {
2121 1.254.2.19 skrll struct usbd_device *dev = pipe->up_dev;
2122 1.254.2.12 skrll struct usbd_bus *bus = dev->ud_bus;
2123 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2124 1.254.2.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2125 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2126 1.254.2.7 skrll uint8_t addr = dev->ud_addr;
2127 1.254.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2128 1.1 augustss ohci_soft_ed_t *sed;
2129 1.1 augustss ohci_soft_td_t *std;
2130 1.60 augustss ohci_soft_itd_t *sitd;
2131 1.60 augustss ohci_physaddr_t tdphys;
2132 1.254.2.1 skrll uint32_t fmt;
2133 1.224 mrg usbd_status err = USBD_NOMEM;
2134 1.64 augustss int ival;
2135 1.1 augustss
2136 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2137 1.254.2.18 skrll DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr,
2138 1.254.2.18 skrll ed->bEndpointAddress, bus->ub_rhaddr);
2139 1.81 augustss
2140 1.224 mrg if (sc->sc_dying) {
2141 1.241 skrll return USBD_IOERROR;
2142 1.224 mrg }
2143 1.116 augustss
2144 1.90 thorpej std = NULL;
2145 1.90 thorpej sed = NULL;
2146 1.90 thorpej
2147 1.254.2.12 skrll if (addr == bus->ub_rhaddr) {
2148 1.1 augustss switch (ed->bEndpointAddress) {
2149 1.1 augustss case USB_CONTROL_ENDPOINT:
2150 1.254.2.12 skrll pipe->up_methods = &roothub_ctrl_methods;
2151 1.1 augustss break;
2152 1.254.2.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2153 1.254.2.7 skrll pipe->up_methods = &ohci_root_intr_methods;
2154 1.1 augustss break;
2155 1.1 augustss default:
2156 1.224 mrg err = USBD_INVAL;
2157 1.241 skrll goto bad;
2158 1.1 augustss }
2159 1.1 augustss } else {
2160 1.1 augustss sed = ohci_alloc_sed(sc);
2161 1.53 augustss if (sed == NULL)
2162 1.241 skrll goto bad;
2163 1.1 augustss opipe->sed = sed;
2164 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2165 1.60 augustss sitd = ohci_alloc_sitd(sc);
2166 1.127 augustss if (sitd == NULL)
2167 1.241 skrll goto bad;
2168 1.241 skrll
2169 1.60 augustss opipe->tail.itd = sitd;
2170 1.76 tsutsui tdphys = sitd->physaddr;
2171 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2172 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2173 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2174 1.83 augustss else
2175 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2176 1.60 augustss } else {
2177 1.60 augustss std = ohci_alloc_std(sc);
2178 1.127 augustss if (std == NULL)
2179 1.241 skrll goto bad;
2180 1.241 skrll
2181 1.60 augustss opipe->tail.td = std;
2182 1.76 tsutsui tdphys = std->physaddr;
2183 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2184 1.60 augustss }
2185 1.168 augustss sed->ed.ed_flags = HTOO32(
2186 1.120 augustss OHCI_ED_SET_FA(addr) |
2187 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2188 1.254.2.7 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2189 1.109 augustss fmt |
2190 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2191 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2192 1.254.2.7 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2193 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2194 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2195 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2196 1.1 augustss
2197 1.60 augustss switch (xfertype) {
2198 1.1 augustss case UE_CONTROL:
2199 1.254.2.7 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2200 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2201 1.120 augustss sizeof(usb_device_request_t),
2202 1.254.2.21 skrll 0, &opipe->ctrl.reqdma);
2203 1.53 augustss if (err)
2204 1.1 augustss goto bad;
2205 1.224 mrg mutex_enter(&sc->sc_lock);
2206 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2207 1.224 mrg mutex_exit(&sc->sc_lock);
2208 1.1 augustss break;
2209 1.1 augustss case UE_INTERRUPT:
2210 1.254.2.7 skrll pipe->up_methods = &ohci_device_intr_methods;
2211 1.254.2.7 skrll ival = pipe->up_interval;
2212 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2213 1.64 augustss ival = ed->bInterval;
2214 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2215 1.226 skrll if (err)
2216 1.226 skrll goto bad;
2217 1.226 skrll break;
2218 1.1 augustss case UE_ISOCHRONOUS:
2219 1.254.2.59 skrll pipe->up_serialise = false;
2220 1.254.2.7 skrll pipe->up_methods = &ohci_device_isoc_methods;
2221 1.254.2.13 skrll return ohci_setup_isoc(pipe);
2222 1.1 augustss case UE_BULK:
2223 1.254.2.7 skrll pipe->up_methods = &ohci_device_bulk_methods;
2224 1.224 mrg mutex_enter(&sc->sc_lock);
2225 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2226 1.224 mrg mutex_exit(&sc->sc_lock);
2227 1.3 augustss break;
2228 1.1 augustss }
2229 1.1 augustss }
2230 1.224 mrg
2231 1.224 mrg return USBD_NORMAL_COMPLETION;
2232 1.1 augustss
2233 1.1 augustss bad:
2234 1.241 skrll if (std != NULL) {
2235 1.90 thorpej ohci_free_std(sc, std);
2236 1.241 skrll }
2237 1.90 thorpej if (sed != NULL)
2238 1.90 thorpej ohci_free_sed(sc, sed);
2239 1.224 mrg return err;
2240 1.120 augustss
2241 1.1 augustss }
2242 1.1 augustss
2243 1.1 augustss /*
2244 1.34 augustss * Close a reqular pipe.
2245 1.34 augustss * Assumes that there are no pending transactions.
2246 1.34 augustss */
2247 1.34 augustss void
2248 1.254.2.19 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2249 1.34 augustss {
2250 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2251 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2252 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2253 1.34 augustss
2254 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2255 1.224 mrg
2256 1.34 augustss #ifdef DIAGNOSTIC
2257 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2258 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2259 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2260 1.34 augustss ohci_soft_td_t *std;
2261 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2262 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2263 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2264 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2265 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2266 1.34 augustss pipe, std);
2267 1.229 christos #ifdef OHCI_DEBUG
2268 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2269 1.168 augustss ohci_dump_ed(sc, sed);
2270 1.106 augustss if (std)
2271 1.168 augustss ohci_dump_td(sc, std);
2272 1.106 augustss #endif
2273 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2274 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2275 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2276 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2277 1.34 augustss }
2278 1.34 augustss #endif
2279 1.224 mrg ohci_rem_ed(sc, sed, head);
2280 1.133 toshii /* Make sure the host controller is not touching this ED */
2281 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2282 1.254.2.7 skrll pipe->up_endpoint->ue_toggle =
2283 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2284 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
2285 1.34 augustss }
2286 1.34 augustss
2287 1.120 augustss /*
2288 1.34 augustss * Abort a device request.
2289 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2290 1.34 augustss * will be removed from the hardware scheduling and that the callback
2291 1.34 augustss * for it will be called with USBD_CANCELLED status.
2292 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2293 1.34 augustss * have happened since the hardware runs concurrently.
2294 1.34 augustss * If the transaction has already happened we rely on the ordinary
2295 1.34 augustss * interrupt processing to process it.
2296 1.224 mrg * XXX This is most probably wrong.
2297 1.224 mrg * XXXMRG this doesn't make sense anymore.
2298 1.34 augustss */
2299 1.34 augustss void
2300 1.254.2.19 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2301 1.34 augustss {
2302 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2303 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2304 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2305 1.106 augustss ohci_soft_td_t *p, *n;
2306 1.106 augustss ohci_physaddr_t headp;
2307 1.224 mrg int hit;
2308 1.159 augustss int wake;
2309 1.34 augustss
2310 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2311 1.254.2.18 skrll DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0);
2312 1.34 augustss
2313 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2314 1.254.2.3 skrll ASSERT_SLEEPABLE();
2315 1.224 mrg
2316 1.116 augustss if (sc->sc_dying) {
2317 1.116 augustss /* If we're dying, just do the software part. */
2318 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2319 1.254.2.7 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2320 1.116 augustss usb_transfer_complete(xfer);
2321 1.170 christos return;
2322 1.116 augustss }
2323 1.116 augustss
2324 1.106 augustss /*
2325 1.159 augustss * If an abort is already in progress then just wait for it to
2326 1.159 augustss * complete and return.
2327 1.159 augustss */
2328 1.254.2.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2329 1.254.2.18 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2330 1.159 augustss #ifdef DIAGNOSTIC
2331 1.159 augustss if (status == USBD_TIMEOUT)
2332 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2333 1.159 augustss #endif
2334 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2335 1.254.2.7 skrll xfer->ux_status = status;
2336 1.254.2.18 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2337 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2338 1.254.2.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2339 1.254.2.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2340 1.224 mrg goto done;
2341 1.159 augustss }
2342 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2343 1.159 augustss
2344 1.159 augustss /*
2345 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2346 1.106 augustss */
2347 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2348 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
2349 1.254.2.18 skrll DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0);
2350 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2351 1.195 bouyer sizeof(sed->ed.ed_flags),
2352 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2353 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2354 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2355 1.195 bouyer sizeof(sed->ed.ed_flags),
2356 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2357 1.34 augustss
2358 1.120 augustss /*
2359 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2360 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2361 1.106 augustss * has run.
2362 1.106 augustss */
2363 1.224 mrg /* Hardware finishes in 1ms */
2364 1.254.2.7 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2365 1.119 augustss sc->sc_softwake = 1;
2366 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2367 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2368 1.119 augustss
2369 1.120 augustss /*
2370 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2371 1.106 augustss * The complication here is that the hardware may have executed
2372 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2373 1.106 augustss * the TDs of this xfer we check if the hardware points to
2374 1.106 augustss * any of them.
2375 1.106 augustss */
2376 1.254.2.7 skrll p = xfer->ux_hcpriv;
2377 1.254.2.24 skrll KASSERT(p);
2378 1.254.2.24 skrll
2379 1.106 augustss #ifdef OHCI_DEBUG
2380 1.254.2.18 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2381 1.254.2.18 skrll
2382 1.254.2.39 skrll if (ohcidebug >= 2) {
2383 1.254.2.18 skrll DPRINTF("sed:", 0, 0, 0, 0);
2384 1.168 augustss ohci_dump_ed(sc, sed);
2385 1.168 augustss ohci_dump_tds(sc, p);
2386 1.106 augustss }
2387 1.254.2.18 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2388 1.106 augustss #endif
2389 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2390 1.106 augustss hit = 0;
2391 1.53 augustss for (; p->xfer == xfer; p = n) {
2392 1.106 augustss hit |= headp == p->physaddr;
2393 1.38 augustss n = p->nexttd;
2394 1.254.2.35 skrll ohci_hash_rem_td(sc, p);
2395 1.34 augustss }
2396 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2397 1.106 augustss if (hit) {
2398 1.254.2.18 skrll DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr,
2399 1.254.2.18 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2400 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2401 1.195 bouyer usb_syncmem(&sed->dma,
2402 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2403 1.195 bouyer sizeof(sed->ed.ed_headp),
2404 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2405 1.106 augustss } else {
2406 1.254.2.18 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2407 1.106 augustss }
2408 1.34 augustss
2409 1.106 augustss /*
2410 1.106 augustss * Step 4: Turn on hardware again.
2411 1.106 augustss */
2412 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2413 1.195 bouyer sizeof(sed->ed.ed_flags),
2414 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2415 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2416 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2417 1.195 bouyer sizeof(sed->ed.ed_flags),
2418 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2419 1.38 augustss
2420 1.106 augustss /*
2421 1.106 augustss * Step 5: Execute callback.
2422 1.106 augustss */
2423 1.254.2.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2424 1.254.2.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2425 1.53 augustss usb_transfer_complete(xfer);
2426 1.159 augustss if (wake)
2427 1.254.2.7 skrll cv_broadcast(&xfer->ux_hccv);
2428 1.38 augustss
2429 1.224 mrg done:
2430 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2431 1.34 augustss }
2432 1.34 augustss
2433 1.34 augustss /*
2434 1.1 augustss * Data structures and routines to emulate the root hub.
2435 1.1 augustss */
2436 1.254.2.12 skrll Static int
2437 1.254.2.12 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2438 1.254.2.12 skrll void *buf, int buflen)
2439 1.17 augustss {
2440 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2441 1.1 augustss usb_port_status_t ps;
2442 1.254.2.12 skrll uint16_t len, value, index;
2443 1.254.2.12 skrll int l, totlen = 0;
2444 1.254.2.12 skrll int port, i;
2445 1.254.2.1 skrll uint32_t v;
2446 1.1 augustss
2447 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2448 1.254.2.18 skrll
2449 1.83 augustss if (sc->sc_dying)
2450 1.254.2.12 skrll return -1;
2451 1.1 augustss
2452 1.254.2.18 skrll DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType,
2453 1.254.2.18 skrll req->bRequest, 0, 0);
2454 1.1 augustss
2455 1.1 augustss len = UGETW(req->wLength);
2456 1.1 augustss value = UGETW(req->wValue);
2457 1.1 augustss index = UGETW(req->wIndex);
2458 1.43 augustss
2459 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2460 1.254.2.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
2461 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2462 1.254.2.18 skrll DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0);
2463 1.171 christos if (len == 0)
2464 1.171 christos break;
2465 1.254.2.12 skrll switch (value) {
2466 1.254.2.12 skrll case C(0, UDESC_DEVICE): {
2467 1.254.2.12 skrll usb_device_descriptor_t devd;
2468 1.254.2.12 skrll
2469 1.254.2.12 skrll totlen = min(buflen, sizeof(devd));
2470 1.254.2.12 skrll memcpy(&devd, buf, totlen);
2471 1.254.2.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2472 1.254.2.12 skrll memcpy(buf, &devd, totlen);
2473 1.1 augustss break;
2474 1.254.2.12 skrll }
2475 1.254.2.12 skrll case C(1, UDESC_STRING):
2476 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2477 1.254.2.12 skrll /* Vendor */
2478 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2479 1.254.2.12 skrll break;
2480 1.254.2.12 skrll case C(2, UDESC_STRING):
2481 1.254.2.12 skrll /* Product */
2482 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2483 1.1 augustss break;
2484 1.254.2.12 skrll #undef sd
2485 1.1 augustss default:
2486 1.254.2.12 skrll /* default from usbroothub */
2487 1.254.2.12 skrll return buflen;
2488 1.1 augustss }
2489 1.1 augustss break;
2490 1.254.2.12 skrll
2491 1.1 augustss /* Hub requests */
2492 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2493 1.1 augustss break;
2494 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2495 1.254.2.18 skrll DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2496 1.254.2.18 skrll index, value, 0, 0);
2497 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2498 1.254.2.12 skrll return -1;
2499 1.1 augustss }
2500 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2501 1.1 augustss switch(value) {
2502 1.1 augustss case UHF_PORT_ENABLE:
2503 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2504 1.1 augustss break;
2505 1.1 augustss case UHF_PORT_SUSPEND:
2506 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2507 1.1 augustss break;
2508 1.1 augustss case UHF_PORT_POWER:
2509 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2510 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2511 1.1 augustss break;
2512 1.1 augustss case UHF_C_PORT_CONNECTION:
2513 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2514 1.1 augustss break;
2515 1.1 augustss case UHF_C_PORT_ENABLE:
2516 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2517 1.1 augustss break;
2518 1.1 augustss case UHF_C_PORT_SUSPEND:
2519 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2520 1.1 augustss break;
2521 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2522 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2523 1.1 augustss break;
2524 1.1 augustss case UHF_C_PORT_RESET:
2525 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2526 1.1 augustss break;
2527 1.1 augustss default:
2528 1.254.2.12 skrll return -1;
2529 1.1 augustss }
2530 1.1 augustss switch(value) {
2531 1.1 augustss case UHF_C_PORT_CONNECTION:
2532 1.1 augustss case UHF_C_PORT_ENABLE:
2533 1.1 augustss case UHF_C_PORT_SUSPEND:
2534 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2535 1.1 augustss case UHF_C_PORT_RESET:
2536 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2537 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2538 1.157 mycroft ohci_rhsc_enable(sc);
2539 1.1 augustss break;
2540 1.1 augustss default:
2541 1.1 augustss break;
2542 1.1 augustss }
2543 1.1 augustss break;
2544 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2545 1.171 christos if (len == 0)
2546 1.171 christos break;
2547 1.146 toshii if ((value & 0xff) != 0) {
2548 1.254.2.12 skrll return -1;
2549 1.1 augustss }
2550 1.254.2.12 skrll usb_hub_descriptor_t hubd;
2551 1.254.2.12 skrll
2552 1.254.2.12 skrll totlen = min(buflen, sizeof(hubd));
2553 1.254.2.12 skrll memcpy(&hubd, buf, totlen);
2554 1.254.2.12 skrll
2555 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2556 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2557 1.15 augustss USETW(hubd.wHubCharacteristics,
2558 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2559 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2560 1.1 augustss /* XXX overcurrent */
2561 1.1 augustss );
2562 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2563 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2564 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2565 1.254.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2566 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2567 1.254.2.12 skrll totlen = min(totlen, hubd.bDescLength);
2568 1.254.2.12 skrll memcpy(buf, &hubd, totlen);
2569 1.1 augustss break;
2570 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2571 1.1 augustss if (len != 4) {
2572 1.254.2.12 skrll return -1;
2573 1.1 augustss }
2574 1.1 augustss memset(buf, 0, len); /* ? XXX */
2575 1.1 augustss totlen = len;
2576 1.1 augustss break;
2577 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2578 1.254.2.18 skrll DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
2579 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2580 1.254.2.12 skrll return -1;
2581 1.1 augustss }
2582 1.1 augustss if (len != 4) {
2583 1.254.2.12 skrll return -1;
2584 1.254.2.56 skrll }
2585 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2586 1.254.2.18 skrll DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0);
2587 1.1 augustss USETW(ps.wPortStatus, v);
2588 1.1 augustss USETW(ps.wPortChange, v >> 16);
2589 1.254.2.12 skrll totlen = min(len, sizeof(ps));
2590 1.254.2.12 skrll memcpy(buf, &ps, totlen);
2591 1.1 augustss break;
2592 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2593 1.254.2.12 skrll return -1;
2594 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2595 1.1 augustss break;
2596 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2597 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2598 1.254.2.12 skrll return -1;
2599 1.1 augustss }
2600 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2601 1.1 augustss switch(value) {
2602 1.1 augustss case UHF_PORT_ENABLE:
2603 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2604 1.1 augustss break;
2605 1.1 augustss case UHF_PORT_SUSPEND:
2606 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2607 1.1 augustss break;
2608 1.1 augustss case UHF_PORT_RESET:
2609 1.254.2.18 skrll DPRINTFN(5, "reset port %d", index, 0, 0, 0);
2610 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2611 1.110 augustss for (i = 0; i < 5; i++) {
2612 1.110 augustss usb_delay_ms(&sc->sc_bus,
2613 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2614 1.116 augustss if (sc->sc_dying) {
2615 1.254.2.12 skrll return -1;
2616 1.116 augustss }
2617 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2618 1.1 augustss break;
2619 1.1 augustss }
2620 1.254.2.18 skrll DPRINTFN(8, "port %d reset, status = 0x%04x", index,
2621 1.254.2.18 skrll OREAD4(sc, port), 0, 0);
2622 1.1 augustss break;
2623 1.1 augustss case UHF_PORT_POWER:
2624 1.254.2.18 skrll DPRINTFN(2, "set port power %d", index, 0, 0, 0);
2625 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2626 1.1 augustss break;
2627 1.1 augustss default:
2628 1.254.2.12 skrll return -1;
2629 1.1 augustss }
2630 1.1 augustss break;
2631 1.1 augustss default:
2632 1.254.2.12 skrll /* default from usbroothub */
2633 1.254.2.12 skrll return buflen;
2634 1.1 augustss }
2635 1.1 augustss
2636 1.254.2.12 skrll return totlen;
2637 1.1 augustss }
2638 1.1 augustss
2639 1.82 augustss Static usbd_status
2640 1.254.2.19 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2641 1.1 augustss {
2642 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2643 1.53 augustss usbd_status err;
2644 1.17 augustss
2645 1.46 augustss /* Insert last in queue. */
2646 1.224 mrg mutex_enter(&sc->sc_lock);
2647 1.53 augustss err = usb_insert_transfer(xfer);
2648 1.224 mrg mutex_exit(&sc->sc_lock);
2649 1.53 augustss if (err)
2650 1.254.2.13 skrll return err;
2651 1.46 augustss
2652 1.46 augustss /* Pipe isn't running, start first */
2653 1.254.2.13 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2654 1.17 augustss }
2655 1.17 augustss
2656 1.82 augustss Static usbd_status
2657 1.254.2.19 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2658 1.17 augustss {
2659 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2660 1.1 augustss
2661 1.83 augustss if (sc->sc_dying)
2662 1.254.2.13 skrll return USBD_IOERROR;
2663 1.83 augustss
2664 1.224 mrg mutex_enter(&sc->sc_lock);
2665 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2666 1.53 augustss sc->sc_intrxfer = xfer;
2667 1.224 mrg mutex_exit(&sc->sc_lock);
2668 1.1 augustss
2669 1.254.2.13 skrll return USBD_IN_PROGRESS;
2670 1.1 augustss }
2671 1.1 augustss
2672 1.3 augustss /* Abort a root interrupt request. */
2673 1.82 augustss Static void
2674 1.254.2.19 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2675 1.1 augustss {
2676 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2677 1.224 mrg
2678 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2679 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2680 1.53 augustss
2681 1.252 skrll sc->sc_intrxfer = NULL;
2682 1.252 skrll
2683 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
2684 1.53 augustss usb_transfer_complete(xfer);
2685 1.1 augustss }
2686 1.1 augustss
2687 1.1 augustss /* Close the root pipe. */
2688 1.82 augustss Static void
2689 1.254.2.19 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2690 1.1 augustss {
2691 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2692 1.120 augustss
2693 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2694 1.224 mrg
2695 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2696 1.34 augustss
2697 1.53 augustss sc->sc_intrxfer = NULL;
2698 1.1 augustss }
2699 1.1 augustss
2700 1.1 augustss /************************/
2701 1.1 augustss
2702 1.254.2.35 skrll int
2703 1.254.2.35 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2704 1.254.2.35 skrll {
2705 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2706 1.254.2.35 skrll usb_device_request_t *req = &xfer->ux_request;
2707 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2708 1.254.2.42 skrll ohci_soft_td_t *stat, *setup;
2709 1.254.2.35 skrll int isread = req->bmRequestType & UT_READ;
2710 1.254.2.35 skrll int len = xfer->ux_bufsize;
2711 1.254.2.35 skrll int err = ENOMEM;
2712 1.254.2.35 skrll
2713 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2714 1.254.2.35 skrll
2715 1.254.2.42 skrll setup = ohci_alloc_std(sc);
2716 1.254.2.42 skrll if (setup == NULL) {
2717 1.254.2.35 skrll goto bad1;
2718 1.254.2.35 skrll }
2719 1.254.2.42 skrll stat = ohci_alloc_std(sc);
2720 1.254.2.42 skrll if (stat == NULL) {
2721 1.254.2.35 skrll goto bad2;
2722 1.254.2.35 skrll }
2723 1.254.2.35 skrll
2724 1.254.2.42 skrll ox->ox_setup = setup;
2725 1.254.2.35 skrll ox->ox_stat = stat;
2726 1.254.2.35 skrll ox->ox_nstd = 0;
2727 1.254.2.35 skrll
2728 1.254.2.35 skrll /* Set up data transaction */
2729 1.254.2.35 skrll if (len != 0) {
2730 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2731 1.254.2.35 skrll if (err) {
2732 1.254.2.35 skrll goto bad3;
2733 1.254.2.35 skrll }
2734 1.254.2.35 skrll }
2735 1.254.2.35 skrll return 0;
2736 1.254.2.35 skrll
2737 1.254.2.35 skrll bad3:
2738 1.254.2.35 skrll ohci_free_std(sc, stat);
2739 1.254.2.42 skrll bad2:
2740 1.254.2.42 skrll ohci_free_std(sc, setup);
2741 1.254.2.35 skrll bad1:
2742 1.254.2.35 skrll return err;
2743 1.254.2.35 skrll }
2744 1.254.2.35 skrll
2745 1.254.2.35 skrll void
2746 1.254.2.35 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2747 1.254.2.35 skrll {
2748 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2749 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2750 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2751 1.254.2.35 skrll
2752 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2753 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2754 1.254.2.35 skrll
2755 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2756 1.254.2.42 skrll if (ox->ox_setup != opipe->tail.td) {
2757 1.254.2.42 skrll ohci_free_std_locked(sc, ox->ox_setup);
2758 1.254.2.35 skrll }
2759 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2760 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2761 1.254.2.35 skrll if (std == NULL)
2762 1.254.2.35 skrll break;
2763 1.254.2.35 skrll ohci_free_std_locked(sc, std);
2764 1.254.2.35 skrll }
2765 1.254.2.35 skrll ohci_free_std_locked(sc, ox->ox_stat);
2766 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
2767 1.254.2.35 skrll
2768 1.254.2.35 skrll if (ox->ox_nstd) {
2769 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2770 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
2771 1.254.2.35 skrll }
2772 1.254.2.35 skrll }
2773 1.254.2.35 skrll
2774 1.82 augustss Static usbd_status
2775 1.254.2.19 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2776 1.1 augustss {
2777 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2778 1.53 augustss usbd_status err;
2779 1.17 augustss
2780 1.46 augustss /* Insert last in queue. */
2781 1.224 mrg mutex_enter(&sc->sc_lock);
2782 1.53 augustss err = usb_insert_transfer(xfer);
2783 1.224 mrg mutex_exit(&sc->sc_lock);
2784 1.53 augustss if (err)
2785 1.254.2.13 skrll return err;
2786 1.46 augustss
2787 1.46 augustss /* Pipe isn't running, start first */
2788 1.254.2.13 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2789 1.17 augustss }
2790 1.17 augustss
2791 1.82 augustss Static usbd_status
2792 1.254.2.19 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2793 1.17 augustss {
2794 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2795 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2796 1.254.2.27 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2797 1.254.2.27 skrll usb_device_request_t *req = &xfer->ux_request;
2798 1.254.2.27 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2799 1.254.2.27 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2800 1.254.2.27 skrll ohci_soft_ed_t *sed;
2801 1.254.2.27 skrll int isread;
2802 1.254.2.27 skrll int len;
2803 1.254.2.27 skrll
2804 1.254.2.27 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2805 1.254.2.27 skrll
2806 1.83 augustss if (sc->sc_dying)
2807 1.254.2.13 skrll return USBD_IOERROR;
2808 1.83 augustss
2809 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2810 1.1 augustss
2811 1.254.2.27 skrll isread = req->bmRequestType & UT_READ;
2812 1.254.2.27 skrll len = UGETW(req->wLength);
2813 1.254.2.27 skrll
2814 1.254.2.40 skrll DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr,
2815 1.254.2.40 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2816 1.254.2.40 skrll DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x",
2817 1.254.2.27 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2818 1.254.2.27 skrll UGETW(req->wIndex));
2819 1.254.2.27 skrll
2820 1.254.2.35 skrll /* Need to take lock here for pipe->tail.td */
2821 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2822 1.254.2.35 skrll
2823 1.254.2.42 skrll /*
2824 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2825 1.254.2.42 skrll * next transfer
2826 1.254.2.42 skrll */
2827 1.254.2.27 skrll setup = opipe->tail.td;
2828 1.254.2.42 skrll opipe->tail.td = ox->ox_setup;
2829 1.254.2.42 skrll ox->ox_setup = setup;
2830 1.254.2.42 skrll
2831 1.254.2.35 skrll stat = ox->ox_stat;
2832 1.254.2.27 skrll
2833 1.254.2.50 skrll /* point at sentinel */
2834 1.254.2.50 skrll tail = opipe->tail.td;
2835 1.254.2.27 skrll sed = opipe->sed;
2836 1.254.2.27 skrll
2837 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2838 1.254.2.27 skrll "address ED %d pipe %d\n",
2839 1.254.2.27 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2840 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2841 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2842 1.254.2.27 skrll "MPL ED %d pipe %d\n",
2843 1.254.2.27 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2844 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2845 1.254.2.27 skrll
2846 1.254.2.35 skrll /* next will point to data if len != 0 */
2847 1.254.2.27 skrll next = stat;
2848 1.254.2.27 skrll
2849 1.254.2.27 skrll /* Set up data transaction */
2850 1.254.2.27 skrll if (len != 0) {
2851 1.254.2.35 skrll ohci_soft_td_t *std;
2852 1.254.2.35 skrll ohci_soft_td_t *end;
2853 1.254.2.27 skrll
2854 1.254.2.35 skrll next = ox->ox_stds[0];
2855 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2856 1.254.2.27 skrll
2857 1.254.2.35 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2858 1.254.2.35 skrll end->nexttd = stat;
2859 1.254.2.35 skrll
2860 1.254.2.35 skrll usb_syncmem(&end->dma,
2861 1.254.2.35 skrll end->offs + offsetof(ohci_td_t, td_nexttd),
2862 1.254.2.35 skrll sizeof(end->td.td_nexttd),
2863 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2864 1.254.2.35 skrll
2865 1.254.2.35 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2866 1.254.2.35 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2867 1.254.2.35 skrll std = ox->ox_stds[0];
2868 1.254.2.27 skrll /* Start toggle at 1 and then use the carried toggle. */
2869 1.254.2.27 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2870 1.254.2.27 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2871 1.254.2.27 skrll usb_syncmem(&std->dma,
2872 1.254.2.27 skrll std->offs + offsetof(ohci_td_t, td_flags),
2873 1.254.2.27 skrll sizeof(std->td.td_flags),
2874 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2875 1.254.2.27 skrll }
2876 1.254.2.27 skrll
2877 1.254.2.35 skrll DPRINTFN(8, "setup %p data %p stat %p tail %p", setup,
2878 1.254.2.35 skrll (len != 0 ? ox->ox_stds[0] : NULL), stat, tail);
2879 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
2880 1.254.2.35 skrll
2881 1.254.2.27 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2882 1.254.2.27 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2883 1.254.2.27 skrll
2884 1.254.2.27 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2885 1.254.2.27 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2886 1.254.2.27 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2887 1.254.2.27 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2888 1.254.2.27 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2889 1.254.2.33 skrll setup->nexttd = next;
2890 1.254.2.27 skrll setup->len = 0;
2891 1.254.2.27 skrll setup->xfer = xfer;
2892 1.254.2.27 skrll setup->flags = 0;
2893 1.254.2.35 skrll ohci_hash_add_td(sc, setup);
2894 1.254.2.35 skrll
2895 1.254.2.27 skrll xfer->ux_hcpriv = setup;
2896 1.254.2.27 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2897 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2898 1.254.2.27 skrll
2899 1.254.2.27 skrll stat->td.td_flags = HTOO32(
2900 1.254.2.27 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2901 1.254.2.27 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2902 1.254.2.27 skrll stat->td.td_cbp = 0;
2903 1.254.2.27 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2904 1.254.2.27 skrll stat->td.td_be = 0;
2905 1.254.2.33 skrll stat->nexttd = tail;
2906 1.254.2.27 skrll stat->flags = OHCI_CALL_DONE;
2907 1.254.2.27 skrll stat->len = 0;
2908 1.254.2.27 skrll stat->xfer = xfer;
2909 1.254.2.35 skrll ohci_hash_add_td(sc, stat);
2910 1.254.2.35 skrll
2911 1.254.2.27 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2912 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2913 1.254.2.27 skrll
2914 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
2915 1.254.2.35 skrll tail->nexttd = NULL;
2916 1.254.2.35 skrll tail->xfer = NULL;
2917 1.254.2.35 skrll
2918 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2919 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2920 1.254.2.35 skrll
2921 1.254.2.27 skrll #ifdef OHCI_DEBUG
2922 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2923 1.254.2.39 skrll if (ohcidebug >= 5) {
2924 1.254.2.27 skrll ohci_dump_ed(sc, sed);
2925 1.254.2.27 skrll ohci_dump_tds(sc, setup);
2926 1.254.2.27 skrll }
2927 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2928 1.254.2.27 skrll #endif
2929 1.254.2.27 skrll
2930 1.254.2.27 skrll /* Insert ED in schedule */
2931 1.254.2.27 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2932 1.254.2.27 skrll usb_syncmem(&sed->dma,
2933 1.254.2.27 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2934 1.254.2.27 skrll sizeof(sed->ed.ed_tailp),
2935 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2936 1.254.2.27 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2937 1.254.2.27 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2938 1.254.2.27 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2939 1.254.2.27 skrll ohci_timeout, xfer);
2940 1.254.2.27 skrll }
2941 1.254.2.27 skrll
2942 1.254.2.41 skrll DPRINTF("done", 0, 0, 0, 0);
2943 1.254.2.41 skrll
2944 1.224 mrg mutex_exit(&sc->sc_lock);
2945 1.1 augustss
2946 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling)
2947 1.53 augustss ohci_waitintr(sc, xfer);
2948 1.254.2.27 skrll
2949 1.254.2.13 skrll return USBD_IN_PROGRESS;
2950 1.1 augustss }
2951 1.1 augustss
2952 1.1 augustss /* Abort a device control request. */
2953 1.82 augustss Static void
2954 1.254.2.19 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2955 1.1 augustss {
2956 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2957 1.224 mrg
2958 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2959 1.224 mrg
2960 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2961 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2962 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2963 1.1 augustss }
2964 1.1 augustss
2965 1.1 augustss /* Close a device control pipe. */
2966 1.82 augustss Static void
2967 1.254.2.19 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2968 1.1 augustss {
2969 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2970 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2971 1.1 augustss
2972 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2973 1.224 mrg
2974 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2975 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2976 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2977 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
2978 1.3 augustss }
2979 1.3 augustss
2980 1.3 augustss /************************/
2981 1.37 augustss
2982 1.82 augustss Static void
2983 1.254.2.19 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2984 1.37 augustss {
2985 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2986 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2987 1.37 augustss
2988 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2989 1.37 augustss }
2990 1.37 augustss
2991 1.82 augustss Static void
2992 1.254.2.19 skrll ohci_noop(struct usbd_pipe *pipe)
2993 1.37 augustss {
2994 1.37 augustss }
2995 1.3 augustss
2996 1.254.2.35 skrll Static int
2997 1.254.2.35 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
2998 1.254.2.35 skrll {
2999 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3000 1.254.2.35 skrll int len = xfer->ux_bufsize;
3001 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3002 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3003 1.254.2.35 skrll int err;
3004 1.254.2.35 skrll
3005 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3006 1.254.2.35 skrll
3007 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3008 1.254.2.35 skrll
3009 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3010 1.254.2.35 skrll xfer->ux_flags);
3011 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3012 1.254.2.35 skrll
3013 1.254.2.35 skrll /* Allocate a chain of new TDs (including a new tail). */
3014 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3015 1.254.2.35 skrll if (err)
3016 1.254.2.35 skrll return err;
3017 1.254.2.35 skrll
3018 1.254.2.35 skrll return 0;
3019 1.254.2.35 skrll }
3020 1.254.2.35 skrll
3021 1.254.2.35 skrll Static void
3022 1.254.2.35 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
3023 1.254.2.35 skrll {
3024 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3025 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3026 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3027 1.254.2.35 skrll
3028 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3029 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3030 1.254.2.35 skrll
3031 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3032 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3033 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3034 1.254.2.35 skrll if (std == NULL)
3035 1.254.2.35 skrll break;
3036 1.254.2.35 skrll if (std != opipe->tail.td)
3037 1.254.2.35 skrll ohci_free_std_locked(sc, std);
3038 1.254.2.35 skrll }
3039 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3040 1.254.2.35 skrll
3041 1.254.2.35 skrll if (ox->ox_nstd) {
3042 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3043 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
3044 1.254.2.35 skrll }
3045 1.254.2.35 skrll }
3046 1.254.2.35 skrll
3047 1.82 augustss Static usbd_status
3048 1.254.2.19 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
3049 1.3 augustss {
3050 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3051 1.53 augustss usbd_status err;
3052 1.17 augustss
3053 1.46 augustss /* Insert last in queue. */
3054 1.224 mrg mutex_enter(&sc->sc_lock);
3055 1.53 augustss err = usb_insert_transfer(xfer);
3056 1.224 mrg mutex_exit(&sc->sc_lock);
3057 1.53 augustss if (err)
3058 1.254.2.13 skrll return err;
3059 1.46 augustss
3060 1.46 augustss /* Pipe isn't running, start first */
3061 1.254.2.13 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3062 1.17 augustss }
3063 1.17 augustss
3064 1.82 augustss Static usbd_status
3065 1.254.2.19 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
3066 1.17 augustss {
3067 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3068 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3069 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3070 1.254.2.35 skrll ohci_soft_td_t *last;
3071 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
3072 1.3 augustss ohci_soft_ed_t *sed;
3073 1.224 mrg int len, isread, endpt;
3074 1.3 augustss
3075 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3076 1.254.2.18 skrll
3077 1.83 augustss if (sc->sc_dying)
3078 1.254.2.13 skrll return USBD_IOERROR;
3079 1.83 augustss
3080 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3081 1.3 augustss
3082 1.254.2.7 skrll len = xfer->ux_length;
3083 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3084 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3085 1.3 augustss sed = opipe->sed;
3086 1.3 augustss
3087 1.254.2.18 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3088 1.254.2.18 skrll xfer->ux_flags);
3089 1.254.2.18 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3090 1.34 augustss
3091 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3092 1.3 augustss
3093 1.254.2.42 skrll /*
3094 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3095 1.254.2.42 skrll * next transfer
3096 1.254.2.42 skrll */
3097 1.60 augustss data = opipe->tail.td;
3098 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3099 1.254.2.35 skrll ox->ox_stds[0] = data;
3100 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3101 1.254.2.35 skrll
3102 1.254.2.50 skrll /* point at sentinel */
3103 1.254.2.50 skrll tail = opipe->tail.td;
3104 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3105 1.254.2.35 skrll tail->nexttd = NULL;
3106 1.254.2.35 skrll tail->xfer = NULL;
3107 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3108 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3109 1.254.2.35 skrll xfer->ux_hcpriv = data;
3110 1.254.2.35 skrll
3111 1.254.2.35 skrll DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0);
3112 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3113 1.254.2.1 skrll
3114 1.77 augustss /* We want interrupt at the end of the transfer. */
3115 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3116 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3117 1.48 augustss
3118 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3119 1.254.2.35 skrll last->nexttd = tail;
3120 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3121 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3122 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3123 1.3 augustss
3124 1.254.2.18 skrll DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x "
3125 1.254.2.18 skrll "td_cbp=0x%08x td_be=0x%08x",
3126 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3127 1.168 augustss (int)O32TOH(data->td.td_flags),
3128 1.168 augustss (int)O32TOH(data->td.td_cbp),
3129 1.254.2.18 skrll (int)O32TOH(data->td.td_be));
3130 1.34 augustss
3131 1.52 augustss #ifdef OHCI_DEBUG
3132 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3133 1.254.2.39 skrll if (ohcidebug >= 5) {
3134 1.168 augustss ohci_dump_ed(sc, sed);
3135 1.168 augustss ohci_dump_tds(sc, data);
3136 1.34 augustss }
3137 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3138 1.34 augustss #endif
3139 1.34 augustss
3140 1.3 augustss /* Insert ED in schedule */
3141 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3142 1.254.2.35 skrll KASSERT(tdp->xfer == xfer);
3143 1.48 augustss }
3144 1.254.2.35 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3145 1.254.2.35 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3146 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3147 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3148 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3149 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3150 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3151 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3152 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3153 1.80 augustss ohci_timeout, xfer);
3154 1.15 augustss }
3155 1.224 mrg mutex_exit(&sc->sc_lock);
3156 1.34 augustss
3157 1.254.2.13 skrll return USBD_IN_PROGRESS;
3158 1.3 augustss }
3159 1.3 augustss
3160 1.82 augustss Static void
3161 1.254.2.19 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3162 1.3 augustss {
3163 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3164 1.254.2.25 skrll
3165 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3166 1.224 mrg
3167 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3168 1.224 mrg
3169 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
3170 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3171 1.3 augustss }
3172 1.3 augustss
3173 1.120 augustss /*
3174 1.34 augustss * Close a device bulk pipe.
3175 1.34 augustss */
3176 1.82 augustss Static void
3177 1.254.2.19 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3178 1.3 augustss {
3179 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3180 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3181 1.3 augustss
3182 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3183 1.224 mrg
3184 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3185 1.254.2.18 skrll
3186 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3187 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3188 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3189 1.1 augustss }
3190 1.1 augustss
3191 1.1 augustss /************************/
3192 1.1 augustss
3193 1.254.2.35 skrll Static int
3194 1.254.2.35 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3195 1.254.2.35 skrll {
3196 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3197 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3198 1.254.2.35 skrll int len = xfer->ux_bufsize;
3199 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3200 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3201 1.254.2.35 skrll int err;
3202 1.254.2.35 skrll
3203 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3204 1.254.2.35 skrll
3205 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3206 1.254.2.35 skrll KASSERT(len != 0);
3207 1.254.2.35 skrll
3208 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3209 1.254.2.35 skrll xfer->ux_flags);
3210 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3211 1.254.2.35 skrll
3212 1.254.2.35 skrll ox->ox_nstd = 0;
3213 1.254.2.35 skrll
3214 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3215 1.254.2.35 skrll if (err) {
3216 1.254.2.35 skrll return err;
3217 1.254.2.35 skrll }
3218 1.254.2.35 skrll
3219 1.254.2.35 skrll return 0;
3220 1.254.2.35 skrll }
3221 1.254.2.35 skrll
3222 1.254.2.35 skrll Static void
3223 1.254.2.35 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3224 1.254.2.35 skrll {
3225 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3226 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3227 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3228 1.254.2.35 skrll
3229 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3230 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3231 1.254.2.35 skrll
3232 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3233 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3234 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3235 1.254.2.35 skrll if (std != NULL)
3236 1.254.2.35 skrll break;
3237 1.254.2.35 skrll if (std != opipe->tail.td)
3238 1.254.2.35 skrll ohci_free_std_locked(sc, std);
3239 1.254.2.35 skrll }
3240 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3241 1.254.2.35 skrll
3242 1.254.2.35 skrll if (ox->ox_nstd) {
3243 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3244 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
3245 1.254.2.35 skrll }
3246 1.254.2.35 skrll }
3247 1.254.2.35 skrll
3248 1.82 augustss Static usbd_status
3249 1.254.2.19 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3250 1.17 augustss {
3251 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3252 1.53 augustss usbd_status err;
3253 1.17 augustss
3254 1.46 augustss /* Insert last in queue. */
3255 1.224 mrg mutex_enter(&sc->sc_lock);
3256 1.53 augustss err = usb_insert_transfer(xfer);
3257 1.224 mrg mutex_exit(&sc->sc_lock);
3258 1.53 augustss if (err)
3259 1.254.2.13 skrll return err;
3260 1.46 augustss
3261 1.46 augustss /* Pipe isn't running, start first */
3262 1.254.2.13 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3263 1.17 augustss }
3264 1.17 augustss
3265 1.82 augustss Static usbd_status
3266 1.254.2.19 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3267 1.1 augustss {
3268 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3269 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3270 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3271 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3272 1.254.2.35 skrll ohci_soft_td_t *data, *last, *tail;
3273 1.224 mrg int len, isread, endpt;
3274 1.1 augustss
3275 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3276 1.254.2.18 skrll
3277 1.83 augustss if (sc->sc_dying)
3278 1.254.2.13 skrll return USBD_IOERROR;
3279 1.83 augustss
3280 1.254.2.18 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length,
3281 1.254.2.18 skrll xfer->ux_flags, xfer->ux_priv);
3282 1.1 augustss
3283 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3284 1.1 augustss
3285 1.254.2.7 skrll len = xfer->ux_length;
3286 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3287 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3288 1.1 augustss
3289 1.224 mrg mutex_enter(&sc->sc_lock);
3290 1.254.2.35 skrll
3291 1.254.2.42 skrll /*
3292 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3293 1.254.2.42 skrll * next transfer.
3294 1.254.2.42 skrll */
3295 1.254.2.35 skrll data = opipe->tail.td;
3296 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3297 1.254.2.35 skrll ox->ox_stds[0] = data;
3298 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3299 1.254.2.35 skrll
3300 1.254.2.50 skrll /* point at sentinel */
3301 1.254.2.50 skrll tail = opipe->tail.td;
3302 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3303 1.254.2.35 skrll tail->nexttd = NULL;
3304 1.53 augustss tail->xfer = NULL;
3305 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3306 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3307 1.254.2.35 skrll xfer->ux_hcpriv = data;
3308 1.254.2.35 skrll
3309 1.254.2.35 skrll DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0);
3310 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3311 1.1 augustss
3312 1.254.2.35 skrll /* We want interrupt at the end of the transfer. */
3313 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3314 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3315 1.254.2.35 skrll
3316 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3317 1.254.2.35 skrll last->nexttd = tail;
3318 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3319 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3320 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3321 1.1 augustss
3322 1.52 augustss #ifdef OHCI_DEBUG
3323 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3324 1.254.2.39 skrll if (ohcidebug >= 5) {
3325 1.168 augustss ohci_dump_ed(sc, sed);
3326 1.168 augustss ohci_dump_tds(sc, data);
3327 1.1 augustss }
3328 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3329 1.1 augustss #endif
3330 1.1 augustss
3331 1.1 augustss /* Insert ED in schedule */
3332 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3333 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3334 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3335 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3336 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3337 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3338 1.1 augustss
3339 1.224 mrg mutex_exit(&sc->sc_lock);
3340 1.1 augustss
3341 1.254.2.13 skrll return USBD_IN_PROGRESS;
3342 1.1 augustss }
3343 1.1 augustss
3344 1.227 skrll /* Abort a device interrupt request. */
3345 1.82 augustss Static void
3346 1.254.2.19 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3347 1.1 augustss {
3348 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3349 1.224 mrg
3350 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3351 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3352 1.224 mrg
3353 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3354 1.1 augustss }
3355 1.1 augustss
3356 1.1 augustss /* Close a device interrupt pipe. */
3357 1.82 augustss Static void
3358 1.254.2.19 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3359 1.1 augustss {
3360 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3361 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3362 1.254.2.21 skrll int nslots = opipe->intr.nslots;
3363 1.254.2.21 skrll int pos = opipe->intr.pos;
3364 1.1 augustss int j;
3365 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3366 1.224 mrg
3367 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3368 1.254.2.18 skrll
3369 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3370 1.1 augustss
3371 1.254.2.18 skrll DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0);
3372 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3373 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3374 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3375 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3376 1.195 bouyer sizeof(sed->ed.ed_flags),
3377 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3378 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3379 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3380 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3381 1.1 augustss
3382 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3383 1.172 christos continue;
3384 1.254.2.24 skrll KASSERT(p);
3385 1.173 christos p->next = sed->next;
3386 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3387 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3388 1.195 bouyer sizeof(p->ed.ed_nexted),
3389 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3390 1.1 augustss
3391 1.1 augustss for (j = 0; j < nslots; j++)
3392 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3393 1.1 augustss
3394 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3395 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
3396 1.1 augustss }
3397 1.1 augustss
3398 1.82 augustss Static usbd_status
3399 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3400 1.1 augustss {
3401 1.224 mrg int i, j, best;
3402 1.1 augustss u_int npoll, slow, shigh, nslots;
3403 1.1 augustss u_int bestbw, bw;
3404 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3405 1.1 augustss
3406 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3407 1.254.2.18 skrll
3408 1.254.2.18 skrll DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0);
3409 1.1 augustss if (ival == 0) {
3410 1.1 augustss printf("ohci_setintr: 0 interval\n");
3411 1.254.2.13 skrll return USBD_INVAL;
3412 1.1 augustss }
3413 1.1 augustss
3414 1.1 augustss npoll = OHCI_NO_INTRS;
3415 1.1 augustss while (npoll > ival)
3416 1.1 augustss npoll /= 2;
3417 1.254.2.18 skrll DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0);
3418 1.1 augustss
3419 1.1 augustss /*
3420 1.1 augustss * We now know which level in the tree the ED must go into.
3421 1.1 augustss * Figure out which slot has most bandwidth left over.
3422 1.1 augustss * Slots to examine:
3423 1.1 augustss * npoll
3424 1.1 augustss * 1 0
3425 1.1 augustss * 2 1 2
3426 1.1 augustss * 4 3 4 5 6
3427 1.1 augustss * 8 7 8 9 10 11 12 13 14
3428 1.1 augustss * N (N-1) .. (N-1+N-1)
3429 1.1 augustss */
3430 1.1 augustss slow = npoll-1;
3431 1.1 augustss shigh = slow + npoll;
3432 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3433 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3434 1.1 augustss bw = 0;
3435 1.1 augustss for (j = 0; j < nslots; j++)
3436 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3437 1.1 augustss if (bw < bestbw) {
3438 1.1 augustss best = i;
3439 1.1 augustss bestbw = bw;
3440 1.1 augustss }
3441 1.1 augustss }
3442 1.254.2.18 skrll DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw);
3443 1.1 augustss
3444 1.224 mrg mutex_enter(&sc->sc_lock);
3445 1.1 augustss hsed = sc->sc_eds[best];
3446 1.1 augustss sed->next = hsed->next;
3447 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3448 1.195 bouyer sizeof(hsed->ed.ed_flags),
3449 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3450 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3451 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3452 1.195 bouyer sizeof(sed->ed.ed_flags),
3453 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3454 1.1 augustss hsed->next = sed;
3455 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3456 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3457 1.195 bouyer sizeof(hsed->ed.ed_flags),
3458 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3459 1.224 mrg mutex_exit(&sc->sc_lock);
3460 1.1 augustss
3461 1.1 augustss for (j = 0; j < nslots; j++)
3462 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3463 1.254.2.21 skrll opipe->intr.nslots = nslots;
3464 1.254.2.21 skrll opipe->intr.pos = best;
3465 1.1 augustss
3466 1.254.2.18 skrll DPRINTFN(5, "returns %p", opipe, 0, 0, 0);
3467 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3468 1.60 augustss }
3469 1.60 augustss
3470 1.60 augustss /***********************/
3471 1.60 augustss
3472 1.254.2.35 skrll Static int
3473 1.254.2.35 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3474 1.254.2.35 skrll {
3475 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3476 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3477 1.254.2.35 skrll ohci_soft_itd_t *sitd;
3478 1.254.2.35 skrll size_t i;
3479 1.254.2.35 skrll int err;
3480 1.254.2.35 skrll
3481 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3482 1.254.2.35 skrll
3483 1.254.2.35 skrll DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length,
3484 1.254.2.35 skrll xfer->ux_flags, 0);
3485 1.254.2.35 skrll
3486 1.254.2.35 skrll const size_t nfsitd =
3487 1.254.2.35 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3488 1.254.2.35 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3489 1.254.2.35 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3490 1.254.2.35 skrll
3491 1.254.2.35 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3492 1.254.2.35 skrll KM_SLEEP);
3493 1.254.2.35 skrll ox->ox_nsitd = nsitd;
3494 1.254.2.35 skrll
3495 1.254.2.35 skrll for (i = 0; i < nsitd; i++) {
3496 1.254.2.35 skrll /* Allocate next ITD */
3497 1.254.2.35 skrll sitd = ohci_alloc_sitd(sc);
3498 1.254.2.35 skrll if (sitd == NULL) {
3499 1.254.2.35 skrll err = ENOMEM;
3500 1.254.2.35 skrll goto fail;
3501 1.254.2.35 skrll }
3502 1.254.2.35 skrll ox->ox_sitds[i] = sitd;
3503 1.254.2.35 skrll sitd->xfer = xfer;
3504 1.254.2.35 skrll sitd->flags = 0;
3505 1.254.2.35 skrll }
3506 1.254.2.35 skrll
3507 1.254.2.35 skrll return 0;
3508 1.254.2.35 skrll fail:
3509 1.254.2.35 skrll for (; i > 0;) {
3510 1.254.2.35 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3511 1.254.2.35 skrll }
3512 1.254.2.35 skrll return err;
3513 1.254.2.35 skrll }
3514 1.254.2.35 skrll
3515 1.254.2.35 skrll Static void
3516 1.254.2.35 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3517 1.254.2.35 skrll {
3518 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3519 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3520 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3521 1.254.2.35 skrll
3522 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3523 1.254.2.35 skrll
3524 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3525 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3526 1.254.2.35 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3527 1.254.2.35 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3528 1.254.2.35 skrll }
3529 1.254.2.35 skrll }
3530 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3531 1.254.2.35 skrll
3532 1.254.2.35 skrll if (ox->ox_nsitd) {
3533 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3534 1.254.2.35 skrll kmem_free(ox->ox_sitds, sz);
3535 1.254.2.35 skrll }
3536 1.254.2.35 skrll }
3537 1.254.2.35 skrll
3538 1.254.2.35 skrll
3539 1.60 augustss usbd_status
3540 1.254.2.19 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3541 1.60 augustss {
3542 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3543 1.254.2.59 skrll usbd_status __diagused err;
3544 1.60 augustss
3545 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3546 1.254.2.18 skrll
3547 1.254.2.18 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3548 1.60 augustss
3549 1.60 augustss /* Put it on our queue, */
3550 1.224 mrg mutex_enter(&sc->sc_lock);
3551 1.60 augustss err = usb_insert_transfer(xfer);
3552 1.224 mrg mutex_exit(&sc->sc_lock);
3553 1.60 augustss
3554 1.254.2.59 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3555 1.60 augustss
3556 1.60 augustss /* insert into schedule, */
3557 1.60 augustss ohci_device_isoc_enter(xfer);
3558 1.60 augustss
3559 1.83 augustss /* and start if the pipe wasn't running */
3560 1.254.2.59 skrll return USBD_IN_PROGRESS;
3561 1.60 augustss }
3562 1.60 augustss
3563 1.60 augustss void
3564 1.254.2.19 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3565 1.60 augustss {
3566 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3567 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3568 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3569 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3570 1.254.2.53 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3571 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3572 1.61 augustss int i, ncur, nframes;
3573 1.61 augustss
3574 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3575 1.254.2.53 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3576 1.254.2.18 skrll
3577 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3578 1.83 augustss
3579 1.254.2.35 skrll if (sc->sc_dying) {
3580 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3581 1.83 augustss return;
3582 1.254.2.35 skrll }
3583 1.254.2.35 skrll
3584 1.254.2.35 skrll struct isoc *isoc = &opipe->isoc;
3585 1.254.2.35 skrll
3586 1.254.2.35 skrll DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d",
3587 1.254.2.35 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3588 1.83 augustss
3589 1.254.2.21 skrll if (isoc->next == -1) {
3590 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3591 1.254.2.21 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3592 1.254.2.21 skrll DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0);
3593 1.83 augustss }
3594 1.83 augustss
3595 1.61 augustss sitd = opipe->tail.itd;
3596 1.254.2.35 skrll opipe->tail.itd = ox->ox_sitds[0];
3597 1.254.2.35 skrll ox->ox_sitds[0] = sitd;
3598 1.254.2.35 skrll
3599 1.254.2.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3600 1.83 augustss bp0 = OHCI_PAGE(buf);
3601 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3602 1.254.2.7 skrll nframes = xfer->ux_nframes;
3603 1.254.2.7 skrll xfer->ux_hcpriv = sitd;
3604 1.254.2.35 skrll size_t j = 1;
3605 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3606 1.254.2.7 skrll noffs = offs + xfer->ux_frlengths[i];
3607 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3608 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3609 1.120 augustss
3610 1.83 augustss /* Allocate next ITD */
3611 1.254.2.35 skrll nsitd = ox->ox_sitds[j++];
3612 1.254.2.35 skrll KASSERT(nsitd != NULL);
3613 1.254.2.35 skrll KASSERT(j < ox->ox_nsitd);
3614 1.83 augustss
3615 1.83 augustss /* Fill current ITD */
3616 1.168 augustss sitd->itd.itd_flags = HTOO32(
3617 1.120 augustss OHCI_ITD_NOCC |
3618 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3619 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3620 1.83 augustss OHCI_ITD_SET_FC(ncur));
3621 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3622 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3623 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3624 1.254.2.33 skrll sitd->nextitd = nsitd;
3625 1.83 augustss sitd->xfer = xfer;
3626 1.83 augustss sitd->flags = 0;
3627 1.254.2.35 skrll #ifdef DIAGNOSTIC
3628 1.254.2.35 skrll sitd->isdone = false;
3629 1.254.2.35 skrll #endif
3630 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3631 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3632 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3633 1.83 augustss
3634 1.61 augustss sitd = nsitd;
3635 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3636 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3637 1.61 augustss ncur = 0;
3638 1.61 augustss }
3639 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3640 1.83 augustss offs = noffs;
3641 1.61 augustss }
3642 1.254.2.35 skrll KASSERT(j <= ox->ox_nsitd);
3643 1.254.2.35 skrll
3644 1.254.2.53 skrll /* point at sentinel */
3645 1.254.2.53 skrll tail = opipe->tail.itd;
3646 1.254.2.53 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3647 1.254.2.53 skrll tail->nextitd = NULL;
3648 1.254.2.53 skrll tail->xfer = NULL;
3649 1.254.2.53 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3650 1.254.2.53 skrll BUS_DMASYNC_PREWRITE);
3651 1.254.2.53 skrll
3652 1.83 augustss /* Fixup last used ITD */
3653 1.168 augustss sitd->itd.itd_flags = HTOO32(
3654 1.120 augustss OHCI_ITD_NOCC |
3655 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3656 1.61 augustss OHCI_ITD_SET_DI(0) |
3657 1.61 augustss OHCI_ITD_SET_FC(ncur));
3658 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3659 1.254.2.53 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3660 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3661 1.254.2.53 skrll sitd->nextitd = tail;
3662 1.83 augustss sitd->xfer = xfer;
3663 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3664 1.254.2.35 skrll #ifdef DIAGNOSTIC
3665 1.254.2.35 skrll sitd->isdone = false;
3666 1.254.2.35 skrll #endif
3667 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3668 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3669 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3670 1.83 augustss
3671 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3672 1.254.2.21 skrll isoc->inuse += nframes;
3673 1.83 augustss
3674 1.254.2.48 skrll /* XXX pretend we did it all */
3675 1.254.2.48 skrll xfer->ux_actlen = offs;
3676 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3677 1.83 augustss
3678 1.83 augustss #ifdef OHCI_DEBUG
3679 1.254.2.39 skrll if (ohcidebug >= 5) {
3680 1.254.2.18 skrll DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3681 1.254.2.18 skrll 0, 0, 0);
3682 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3683 1.168 augustss ohci_dump_ed(sc, sed);
3684 1.83 augustss }
3685 1.83 augustss #endif
3686 1.61 augustss
3687 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3688 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3689 1.254.2.53 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3690 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3691 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3692 1.195 bouyer sizeof(sed->ed.ed_flags),
3693 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3694 1.224 mrg mutex_exit(&sc->sc_lock);
3695 1.60 augustss }
3696 1.60 augustss
3697 1.60 augustss void
3698 1.254.2.19 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3699 1.60 augustss {
3700 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3701 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3702 1.83 augustss ohci_soft_ed_t *sed;
3703 1.83 augustss ohci_soft_itd_t *sitd;
3704 1.83 augustss
3705 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3706 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3707 1.83 augustss
3708 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3709 1.83 augustss
3710 1.83 augustss /* Transfer is already done. */
3711 1.254.2.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3712 1.254.2.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3713 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3714 1.224 mrg goto done;
3715 1.83 augustss }
3716 1.83 augustss
3717 1.83 augustss /* Give xfer the requested abort code. */
3718 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
3719 1.83 augustss
3720 1.83 augustss sed = opipe->sed;
3721 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3722 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3723 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3724 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3725 1.195 bouyer sizeof(sed->ed.ed_flags),
3726 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3727 1.83 augustss
3728 1.254.2.7 skrll sitd = xfer->ux_hcpriv;
3729 1.254.2.24 skrll KASSERT(sitd);
3730 1.254.2.24 skrll
3731 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3732 1.254.2.55 skrll ohci_hash_rem_itd(sc, sitd);
3733 1.83 augustss #ifdef DIAGNOSTIC
3734 1.254.2.18 skrll DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0);
3735 1.254.2.31 skrll sitd->isdone = true;
3736 1.83 augustss #endif
3737 1.83 augustss }
3738 1.83 augustss
3739 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3740 1.83 augustss
3741 1.83 augustss /* Run callback. */
3742 1.83 augustss usb_transfer_complete(xfer);
3743 1.83 augustss
3744 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3745 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3746 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3747 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3748 1.83 augustss
3749 1.224 mrg done:
3750 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3751 1.60 augustss }
3752 1.60 augustss
3753 1.60 augustss void
3754 1.254.2.19 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3755 1.60 augustss {
3756 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3757 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3758 1.60 augustss }
3759 1.60 augustss
3760 1.60 augustss usbd_status
3761 1.254.2.19 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3762 1.60 augustss {
3763 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3764 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3765 1.254.2.21 skrll struct isoc *isoc = &opipe->isoc;
3766 1.60 augustss
3767 1.254.2.21 skrll isoc->next = -1;
3768 1.254.2.21 skrll isoc->inuse = 0;
3769 1.60 augustss
3770 1.224 mrg mutex_enter(&sc->sc_lock);
3771 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3772 1.224 mrg mutex_exit(&sc->sc_lock);
3773 1.83 augustss
3774 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3775 1.60 augustss }
3776 1.60 augustss
3777 1.60 augustss void
3778 1.254.2.19 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3779 1.60 augustss {
3780 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3781 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3782 1.60 augustss
3783 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3784 1.224 mrg
3785 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3786 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3787 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3788 1.83 augustss #ifdef DIAGNOSTIC
3789 1.254.2.31 skrll opipe->tail.itd->isdone = true;
3790 1.83 augustss #endif
3791 1.254.2.35 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3792 1.1 augustss }
3793