ohci.c revision 1.254.2.70 1 1.254.2.70 skrll /* $NetBSD: ohci.c,v 1.254.2.70 2016/04/04 07:43:12 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.254.2.70 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.70 2016/04/04 07:43:12 skrll Exp $");
45 1.254.2.18 skrll
46 1.254.2.18 skrll #include "opt_usb.h"
47 1.1 augustss
48 1.1 augustss #include <sys/param.h>
49 1.254.2.17 skrll
50 1.254.2.17 skrll #include <sys/cpu.h>
51 1.1 augustss #include <sys/device.h>
52 1.254.2.17 skrll #include <sys/kernel.h>
53 1.254.2.17 skrll #include <sys/kmem.h>
54 1.1 augustss #include <sys/proc.h>
55 1.1 augustss #include <sys/queue.h>
56 1.254.2.17 skrll #include <sys/select.h>
57 1.254.2.18 skrll #include <sys/sysctl.h>
58 1.254.2.17 skrll #include <sys/systm.h>
59 1.1 augustss
60 1.16 augustss #include <machine/endian.h>
61 1.4 augustss
62 1.1 augustss #include <dev/usb/usb.h>
63 1.1 augustss #include <dev/usb/usbdi.h>
64 1.1 augustss #include <dev/usb/usbdivar.h>
65 1.38 augustss #include <dev/usb/usb_mem.h>
66 1.1 augustss #include <dev/usb/usb_quirks.h>
67 1.1 augustss
68 1.1 augustss #include <dev/usb/ohcireg.h>
69 1.1 augustss #include <dev/usb/ohcivar.h>
70 1.254.2.11 skrll #include <dev/usb/usbroothub.h>
71 1.254.2.18 skrll #include <dev/usb/usbhist.h>
72 1.1 augustss
73 1.254.2.18 skrll #ifdef USB_DEBUG
74 1.254.2.18 skrll #ifndef OHCI_DEBUG
75 1.254.2.18 skrll #define ohcidebug 0
76 1.254.2.18 skrll #else
77 1.254.2.59 skrll static int ohcidebug = 10;
78 1.1 augustss
79 1.254.2.18 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
80 1.254.2.18 skrll {
81 1.254.2.18 skrll int err;
82 1.254.2.18 skrll const struct sysctlnode *rnode;
83 1.254.2.18 skrll const struct sysctlnode *cnode;
84 1.254.2.18 skrll
85 1.254.2.18 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
86 1.254.2.18 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
87 1.254.2.18 skrll SYSCTL_DESCR("ohci global controls"),
88 1.254.2.18 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
89 1.36 augustss
90 1.254.2.18 skrll if (err)
91 1.254.2.18 skrll goto fail;
92 1.254.2.18 skrll
93 1.254.2.18 skrll /* control debugging printfs */
94 1.254.2.18 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
95 1.254.2.18 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
96 1.254.2.18 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
97 1.254.2.18 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
98 1.254.2.18 skrll if (err)
99 1.254.2.18 skrll goto fail;
100 1.254.2.18 skrll
101 1.254.2.18 skrll return;
102 1.254.2.18 skrll fail:
103 1.254.2.18 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
104 1.254.2.18 skrll }
105 1.254.2.18 skrll
106 1.254.2.18 skrll #endif /* OHCI_DEBUG */
107 1.254.2.18 skrll #endif /* USB_DEBUG */
108 1.254.2.18 skrll
109 1.254.2.18 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
110 1.254.2.18 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
111 1.254.2.18 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
112 1.254.2.18 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
113 1.52 augustss
114 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
115 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
116 1.16 augustss #else
117 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
118 1.16 augustss #endif
119 1.16 augustss
120 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
121 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
122 1.169 tron #define HTOO16(val) O16TOH(val)
123 1.169 tron #define HTOO32(val) O32TOH(val)
124 1.168 augustss
125 1.1 augustss struct ohci_pipe;
126 1.1 augustss
127 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
128 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
129 1.1 augustss
130 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
131 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
132 1.254.2.35 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
133 1.1 augustss
134 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
135 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
136 1.254.2.35 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
137 1.254.2.35 skrll ohci_soft_itd_t *);
138 1.60 augustss
139 1.254.2.35 skrll Static usbd_status ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
140 1.254.2.35 skrll int, int);
141 1.254.2.35 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
142 1.254.2.35 skrll
143 1.254.2.35 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
144 1.254.2.35 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
145 1.53 augustss
146 1.254.2.19 skrll Static usbd_status ohci_open(struct usbd_pipe *);
147 1.91 augustss Static void ohci_poll(struct usbd_bus *);
148 1.99 augustss Static void ohci_softintr(void *);
149 1.254.2.19 skrll Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *);
150 1.254.2.19 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
151 1.254.2.15 skrll Static void ohci_rhsc_softint(void *);
152 1.91 augustss
153 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
154 1.168 augustss ohci_soft_ed_t *);
155 1.168 augustss
156 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
157 1.224 mrg ohci_soft_ed_t *);
158 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
159 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
161 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
162 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
164 1.91 augustss
165 1.254.2.19 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
166 1.254.2.19 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
167 1.91 augustss
168 1.254.2.23 skrll Static struct usbd_xfer *
169 1.254.2.23 skrll ohci_allocx(struct usbd_bus *, unsigned int);
170 1.254.2.19 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
171 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
172 1.254.2.13 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
173 1.254.2.26 skrll usb_device_request_t *, void *, int);
174 1.91 augustss
175 1.254.2.19 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
176 1.254.2.19 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
177 1.254.2.19 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
178 1.254.2.19 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
179 1.254.2.19 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
180 1.254.2.19 skrll
181 1.254.2.35 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
182 1.254.2.35 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
183 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
184 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
185 1.254.2.19 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
186 1.254.2.19 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
187 1.254.2.19 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
188 1.254.2.19 skrll
189 1.254.2.35 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
190 1.254.2.35 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
191 1.254.2.19 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
192 1.254.2.19 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
193 1.254.2.19 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
194 1.254.2.19 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
195 1.254.2.19 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
196 1.254.2.19 skrll
197 1.254.2.35 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
198 1.254.2.35 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
199 1.254.2.19 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
200 1.254.2.19 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
201 1.254.2.19 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
202 1.254.2.19 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
203 1.254.2.19 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
204 1.254.2.19 skrll
205 1.254.2.35 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
206 1.254.2.35 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
207 1.254.2.19 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
208 1.254.2.19 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
209 1.254.2.19 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
210 1.254.2.19 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
211 1.91 augustss
212 1.254.2.15 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
213 1.254.2.15 skrll struct ohci_pipe *, int);
214 1.91 augustss
215 1.91 augustss Static void ohci_timeout(void *);
216 1.114 augustss Static void ohci_timeout_task(void *);
217 1.104 augustss Static void ohci_rhsc_enable(void *);
218 1.91 augustss
219 1.254.2.19 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
220 1.254.2.19 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
221 1.53 augustss
222 1.254.2.19 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
223 1.254.2.19 skrll Static void ohci_noop(struct usbd_pipe *);
224 1.37 augustss
225 1.52 augustss #ifdef OHCI_DEBUG
226 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
227 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
228 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
230 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
231 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
232 1.1 augustss #endif
233 1.1 augustss
234 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
235 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
236 1.88 augustss #define OWRITE1(sc, r, x) \
237 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
238 1.88 augustss #define OWRITE2(sc, r, x) \
239 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
240 1.88 augustss #define OWRITE4(sc, r, x) \
241 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
242 1.174 mrg
243 1.174 mrg static __inline uint32_t
244 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
245 1.174 mrg {
246 1.174 mrg
247 1.174 mrg OBARR(sc);
248 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
249 1.174 mrg }
250 1.1 augustss
251 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
252 1.254.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
253 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
254 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
255 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
256 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
257 1.1 augustss
258 1.1 augustss struct ohci_pipe {
259 1.1 augustss struct usbd_pipe pipe;
260 1.1 augustss ohci_soft_ed_t *sed;
261 1.60 augustss union {
262 1.60 augustss ohci_soft_td_t *td;
263 1.60 augustss ohci_soft_itd_t *itd;
264 1.60 augustss } tail;
265 1.1 augustss /* Info needed for different pipe kinds. */
266 1.1 augustss union {
267 1.1 augustss /* Control pipe */
268 1.1 augustss struct {
269 1.4 augustss usb_dma_t reqdma;
270 1.254.2.21 skrll } ctrl;
271 1.1 augustss /* Interrupt pipe */
272 1.1 augustss struct {
273 1.1 augustss int nslots;
274 1.1 augustss int pos;
275 1.1 augustss } intr;
276 1.254.2.21 skrll /* Isochronous pipe */
277 1.254.2.21 skrll struct isoc {
278 1.60 augustss int next, inuse;
279 1.254.2.21 skrll } isoc;
280 1.254.2.21 skrll };
281 1.1 augustss };
282 1.1 augustss
283 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
284 1.254.2.5 skrll .ubm_open = ohci_open,
285 1.254.2.5 skrll .ubm_softint = ohci_softintr,
286 1.254.2.5 skrll .ubm_dopoll = ohci_poll,
287 1.254.2.5 skrll .ubm_allocx = ohci_allocx,
288 1.254.2.5 skrll .ubm_freex = ohci_freex,
289 1.254.2.5 skrll .ubm_getlock = ohci_get_lock,
290 1.254.2.12 skrll .ubm_rhctrl = ohci_roothub_ctrl,
291 1.1 augustss };
292 1.1 augustss
293 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
294 1.254.2.5 skrll .upm_transfer = ohci_root_intr_transfer,
295 1.254.2.5 skrll .upm_start = ohci_root_intr_start,
296 1.254.2.5 skrll .upm_abort = ohci_root_intr_abort,
297 1.254.2.5 skrll .upm_close = ohci_root_intr_close,
298 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
299 1.254.2.5 skrll .upm_done = ohci_root_intr_done,
300 1.1 augustss };
301 1.1 augustss
302 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
303 1.254.2.35 skrll .upm_init = ohci_device_ctrl_init,
304 1.254.2.35 skrll .upm_fini = ohci_device_ctrl_fini,
305 1.254.2.5 skrll .upm_transfer = ohci_device_ctrl_transfer,
306 1.254.2.5 skrll .upm_start = ohci_device_ctrl_start,
307 1.254.2.5 skrll .upm_abort = ohci_device_ctrl_abort,
308 1.254.2.5 skrll .upm_close = ohci_device_ctrl_close,
309 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
310 1.254.2.5 skrll .upm_done = ohci_device_ctrl_done,
311 1.1 augustss };
312 1.1 augustss
313 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
314 1.254.2.35 skrll .upm_init = ohci_device_intr_init,
315 1.254.2.35 skrll .upm_fini = ohci_device_intr_fini,
316 1.254.2.5 skrll .upm_transfer = ohci_device_intr_transfer,
317 1.254.2.5 skrll .upm_start = ohci_device_intr_start,
318 1.254.2.5 skrll .upm_abort = ohci_device_intr_abort,
319 1.254.2.5 skrll .upm_close = ohci_device_intr_close,
320 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
321 1.254.2.5 skrll .upm_done = ohci_device_intr_done,
322 1.1 augustss };
323 1.1 augustss
324 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
325 1.254.2.35 skrll .upm_init = ohci_device_bulk_init,
326 1.254.2.35 skrll .upm_fini = ohci_device_bulk_fini,
327 1.254.2.5 skrll .upm_transfer = ohci_device_bulk_transfer,
328 1.254.2.5 skrll .upm_start = ohci_device_bulk_start,
329 1.254.2.5 skrll .upm_abort = ohci_device_bulk_abort,
330 1.254.2.5 skrll .upm_close = ohci_device_bulk_close,
331 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
332 1.254.2.5 skrll .upm_done = ohci_device_bulk_done,
333 1.3 augustss };
334 1.3 augustss
335 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
336 1.254.2.35 skrll .upm_init = ohci_device_isoc_init,
337 1.254.2.35 skrll .upm_fini = ohci_device_isoc_fini,
338 1.254.2.5 skrll .upm_transfer = ohci_device_isoc_transfer,
339 1.254.2.5 skrll .upm_abort = ohci_device_isoc_abort,
340 1.254.2.5 skrll .upm_close = ohci_device_isoc_close,
341 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
342 1.254.2.5 skrll .upm_done = ohci_device_isoc_done,
343 1.43 augustss };
344 1.43 augustss
345 1.47 augustss int
346 1.189 dyoung ohci_activate(device_t self, enum devact act)
347 1.47 augustss {
348 1.189 dyoung struct ohci_softc *sc = device_private(self);
349 1.47 augustss
350 1.47 augustss switch (act) {
351 1.47 augustss case DVACT_DEACTIVATE:
352 1.183 kiyohara sc->sc_dying = 1;
353 1.203 dyoung return 0;
354 1.203 dyoung default:
355 1.203 dyoung return EOPNOTSUPP;
356 1.47 augustss }
357 1.47 augustss }
358 1.47 augustss
359 1.187 dyoung void
360 1.187 dyoung ohci_childdet(device_t self, device_t child)
361 1.187 dyoung {
362 1.187 dyoung struct ohci_softc *sc = device_private(self);
363 1.187 dyoung
364 1.187 dyoung KASSERT(sc->sc_child == child);
365 1.187 dyoung sc->sc_child = NULL;
366 1.187 dyoung }
367 1.187 dyoung
368 1.47 augustss int
369 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
370 1.47 augustss {
371 1.47 augustss int rv = 0;
372 1.47 augustss
373 1.47 augustss if (sc->sc_child != NULL)
374 1.47 augustss rv = config_detach(sc->sc_child, flags);
375 1.120 augustss
376 1.47 augustss if (rv != 0)
377 1.254.2.13 skrll return rv;
378 1.47 augustss
379 1.254 ozaki callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
380 1.104 augustss
381 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
382 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
383 1.116 augustss
384 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
385 1.224 mrg
386 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
387 1.224 mrg
388 1.224 mrg mutex_destroy(&sc->sc_lock);
389 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
390 1.224 mrg
391 1.198 cegger if (sc->sc_hcca != NULL)
392 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
393 1.232 christos pool_cache_destroy(sc->sc_xferpool);
394 1.47 augustss
395 1.254.2.13 skrll return rv;
396 1.47 augustss }
397 1.47 augustss
398 1.1 augustss ohci_soft_ed_t *
399 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
400 1.1 augustss {
401 1.1 augustss ohci_soft_ed_t *sed;
402 1.53 augustss usbd_status err;
403 1.1 augustss int i, offs;
404 1.4 augustss usb_dma_t dma;
405 1.1 augustss
406 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
407 1.254.2.18 skrll
408 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
409 1.53 augustss if (sc->sc_freeeds == NULL) {
410 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
411 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
412 1.254.2.35 skrll
413 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
414 1.53 augustss OHCI_ED_ALIGN, &dma);
415 1.53 augustss if (err)
416 1.254.2.13 skrll return 0;
417 1.254.2.35 skrll
418 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
419 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
420 1.39 augustss offs = i * OHCI_SED_SIZE;
421 1.123 augustss sed = KERNADDR(&dma, offs);
422 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
423 1.195 bouyer sed->dma = dma;
424 1.195 bouyer sed->offs = offs;
425 1.1 augustss sed->next = sc->sc_freeeds;
426 1.1 augustss sc->sc_freeeds = sed;
427 1.1 augustss }
428 1.1 augustss }
429 1.1 augustss sed = sc->sc_freeeds;
430 1.1 augustss sc->sc_freeeds = sed->next;
431 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
432 1.254.2.35 skrll
433 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
434 1.1 augustss sed->next = 0;
435 1.254.2.13 skrll return sed;
436 1.1 augustss }
437 1.1 augustss
438 1.254.2.35 skrll static inline void
439 1.254.2.35 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
440 1.1 augustss {
441 1.254.2.35 skrll
442 1.254.2.35 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
443 1.254.2.35 skrll
444 1.1 augustss sed->next = sc->sc_freeeds;
445 1.1 augustss sc->sc_freeeds = sed;
446 1.1 augustss }
447 1.1 augustss
448 1.254.2.35 skrll void
449 1.254.2.35 skrll ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
450 1.254.2.35 skrll {
451 1.254.2.35 skrll
452 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
453 1.254.2.35 skrll ohci_free_sed_locked(sc, sed);
454 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
455 1.254.2.35 skrll }
456 1.254.2.35 skrll
457 1.1 augustss ohci_soft_td_t *
458 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
459 1.1 augustss {
460 1.1 augustss ohci_soft_td_t *std;
461 1.53 augustss usbd_status err;
462 1.1 augustss int i, offs;
463 1.4 augustss usb_dma_t dma;
464 1.1 augustss
465 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
466 1.254.2.18 skrll
467 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
468 1.53 augustss if (sc->sc_freetds == NULL) {
469 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
470 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
471 1.254.2.35 skrll
472 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
473 1.53 augustss OHCI_TD_ALIGN, &dma);
474 1.53 augustss if (err)
475 1.254.2.13 skrll return NULL;
476 1.254.2.35 skrll
477 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
478 1.254.2.58 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
479 1.39 augustss offs = i * OHCI_STD_SIZE;
480 1.123 augustss std = KERNADDR(&dma, offs);
481 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
482 1.195 bouyer std->dma = dma;
483 1.195 bouyer std->offs = offs;
484 1.1 augustss std->nexttd = sc->sc_freetds;
485 1.1 augustss sc->sc_freetds = std;
486 1.1 augustss }
487 1.1 augustss }
488 1.69 augustss
489 1.1 augustss std = sc->sc_freetds;
490 1.1 augustss sc->sc_freetds = std->nexttd;
491 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
492 1.254.2.35 skrll
493 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
494 1.83 augustss std->nexttd = NULL;
495 1.83 augustss std->xfer = NULL;
496 1.69 augustss
497 1.254.2.13 skrll return std;
498 1.1 augustss }
499 1.1 augustss
500 1.1 augustss void
501 1.254.2.35 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
502 1.1 augustss {
503 1.254.2.7 skrll
504 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
505 1.254.2.1 skrll
506 1.1 augustss std->nexttd = sc->sc_freetds;
507 1.1 augustss sc->sc_freetds = std;
508 1.1 augustss }
509 1.1 augustss
510 1.254.2.35 skrll void
511 1.254.2.35 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
512 1.254.2.35 skrll {
513 1.254.2.35 skrll
514 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
515 1.254.2.35 skrll ohci_free_std_locked(sc, std);
516 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
517 1.254.2.35 skrll }
518 1.254.2.35 skrll
519 1.254.2.35 skrll Static usbd_status
520 1.254.2.70 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd)
521 1.48 augustss {
522 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
523 1.254.2.7 skrll uint16_t flags = xfer->ux_flags;
524 1.48 augustss
525 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
526 1.224 mrg
527 1.254.2.18 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
528 1.254.2.70 skrll xfer->ux_pipe->up_dev->ud_addr,
529 1.254.2.70 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
530 1.254.2.70 skrll length, xfer->ux_pipe->up_dev->ud_speed);
531 1.254.2.35 skrll
532 1.254.2.35 skrll ASSERT_SLEEPABLE();
533 1.254.2.70 skrll KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
534 1.254.2.35 skrll
535 1.254.2.70 skrll size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
536 1.254.2.70 skrll nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
537 1.254.2.35 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
538 1.254.2.35 skrll KM_SLEEP);
539 1.254.2.35 skrll ox->ox_nstd = nstd;
540 1.254.2.35 skrll
541 1.254.2.70 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0);
542 1.254.2.18 skrll
543 1.254.2.70 skrll for (size_t j = 0; j < ox->ox_nstd;) {
544 1.254.2.70 skrll ohci_soft_td_t *cur = ohci_alloc_std(sc);
545 1.254.2.70 skrll if (cur == NULL)
546 1.61 augustss goto nomem;
547 1.48 augustss
548 1.254.2.70 skrll ox->ox_stds[j++] = cur;
549 1.77 augustss cur->xfer = xfer;
550 1.61 augustss cur->flags = 0;
551 1.61 augustss }
552 1.48 augustss
553 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
554 1.61 augustss
555 1.61 augustss nomem:
556 1.254.2.35 skrll ohci_free_stds(sc, ox);
557 1.236 skrll
558 1.254.2.13 skrll return USBD_NOMEM;
559 1.48 augustss }
560 1.48 augustss
561 1.82 augustss Static void
562 1.254.2.35 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
563 1.48 augustss {
564 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
565 1.254.2.35 skrll DPRINTF("ox=%p", ox, 0, 0, 0);
566 1.48 augustss
567 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
568 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
569 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
570 1.254.2.35 skrll if (std == NULL)
571 1.254.2.35 skrll break;
572 1.254.2.35 skrll ohci_free_std_locked(sc, std);
573 1.254.2.35 skrll }
574 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
575 1.254.2.35 skrll }
576 1.254.2.35 skrll
577 1.254.2.35 skrll void
578 1.254.2.35 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
579 1.254.2.35 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
580 1.254.2.35 skrll {
581 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
582 1.254.2.35 skrll ohci_soft_td_t *next, *cur;
583 1.254.2.35 skrll int len, curlen;
584 1.254.2.35 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
585 1.254.2.35 skrll uint16_t flags = xfer->ux_flags;
586 1.254.2.35 skrll
587 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
588 1.254.2.35 skrll DPRINTF("start len=%d", alen, 0, 0, 0);
589 1.254.2.35 skrll
590 1.254.2.35 skrll KASSERT(mutex_owned(&sc->sc_lock));
591 1.254.2.35 skrll
592 1.254.2.35 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
593 1.254.2.35 skrll xfer->ux_pipe->up_dev->ud_addr,
594 1.254.2.35 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
595 1.254.2.35 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
596 1.254.2.35 skrll
597 1.254.2.35 skrll KASSERT(sp);
598 1.254.2.35 skrll
599 1.254.2.35 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
600 1.254.2.35 skrll
601 1.254.2.70 skrll /*
602 1.254.2.70 skrll * Assign next for the len == 0 case where we don't go through the
603 1.254.2.70 skrll * main loop.
604 1.254.2.70 skrll */
605 1.254.2.35 skrll len = alen;
606 1.254.2.70 skrll cur = next = sp;
607 1.254.2.35 skrll
608 1.254.2.35 skrll usb_syncmem(dma, 0, len,
609 1.254.2.35 skrll rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
610 1.254.2.61 skrll const uint32_t tdflags = HTOO32(
611 1.254.2.35 skrll (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
612 1.254.2.35 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
613 1.254.2.35 skrll
614 1.254.2.70 skrll size_t curoffs = 0;
615 1.254.2.70 skrll for (size_t j = 1; len != 0;) {
616 1.254.2.35 skrll if (j == ox->ox_nstd)
617 1.254.2.35 skrll next = NULL;
618 1.254.2.35 skrll else
619 1.254.2.35 skrll next = ox->ox_stds[j++];
620 1.254.2.35 skrll KASSERT(next != cur);
621 1.254.2.35 skrll
622 1.254.2.70 skrll curlen = 0;
623 1.254.2.70 skrll ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
624 1.254.2.70 skrll ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1);
625 1.254.2.70 skrll
626 1.254.2.70 skrll ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys);
627 1.254.2.70 skrll ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys);
628 1.254.2.70 skrll /*
629 1.254.2.70 skrll * The OHCI hardware can handle at most one page
630 1.254.2.70 skrll * crossing per TD
631 1.254.2.70 skrll */
632 1.254.2.70 skrll curlen = len;
633 1.254.2.70 skrll if (!(sphyspg == ephyspg || sphyspg + 1 == ephyspg)) {
634 1.254.2.35 skrll /* must use multiple TDs, fill as much as possible. */
635 1.254.2.35 skrll curlen = 2 * OHCI_PAGE_SIZE -
636 1.254.2.70 skrll (sdataphys & (OHCI_PAGE_SIZE - 1));
637 1.254.2.35 skrll /* the length must be a multiple of the max size */
638 1.254.2.35 skrll curlen -= curlen % mps;
639 1.254.2.35 skrll }
640 1.254.2.70 skrll KASSERT(curlen != 0);
641 1.254.2.70 skrll DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x "
642 1.254.2.70 skrll "len=%d curlen=%d", sdataphys, edataphys, len, curlen);
643 1.254.2.35 skrll
644 1.254.2.35 skrll cur->td.td_flags = tdflags;
645 1.254.2.70 skrll cur->td.td_cbp = HTOO32(sdataphys);
646 1.254.2.70 skrll cur->td.td_be = HTOO32(edataphys);
647 1.254.2.35 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
648 1.254.2.35 skrll cur->nexttd = next;
649 1.254.2.35 skrll cur->len = curlen;
650 1.254.2.35 skrll cur->flags = OHCI_ADD_LEN;
651 1.254.2.35 skrll cur->xfer = xfer;
652 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
653 1.254.2.35 skrll
654 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
655 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
656 1.254.2.70 skrll
657 1.254.2.70 skrll curoffs += curlen;
658 1.254.2.70 skrll len -= curlen;
659 1.254.2.70 skrll
660 1.254.2.70 skrll if (len != 0) {
661 1.254.2.70 skrll KASSERT(next != NULL);
662 1.254.2.70 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
663 1.254.2.70 skrll cur = next;
664 1.254.2.70 skrll }
665 1.254.2.35 skrll }
666 1.254.2.44 skrll cur->td.td_flags |=
667 1.254.2.44 skrll (xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
668 1.254.2.44 skrll
669 1.254.2.35 skrll if (!rd &&
670 1.254.2.35 skrll (flags & USBD_FORCE_SHORT_XFER) &&
671 1.254.2.35 skrll alen % mps == 0) {
672 1.254.2.35 skrll /* Force a 0 length transfer at the end. */
673 1.254.2.35 skrll
674 1.254.2.35 skrll KASSERT(next != NULL);
675 1.254.2.35 skrll cur = next;
676 1.254.2.35 skrll
677 1.254.2.35 skrll cur->td.td_flags = tdflags;
678 1.254.2.35 skrll cur->td.td_cbp = 0; /* indicate 0 length packet */
679 1.254.2.70 skrll cur->td.td_nexttd = 0;
680 1.254.2.35 skrll cur->td.td_be = ~0;
681 1.254.2.35 skrll cur->nexttd = NULL;
682 1.254.2.35 skrll cur->len = 0;
683 1.254.2.35 skrll cur->flags = 0;
684 1.254.2.35 skrll cur->xfer = xfer;
685 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
686 1.254.2.35 skrll
687 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
688 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
689 1.254.2.35 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
690 1.48 augustss }
691 1.254.2.35 skrll *ep = cur;
692 1.48 augustss }
693 1.48 augustss
694 1.60 augustss ohci_soft_itd_t *
695 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
696 1.60 augustss {
697 1.60 augustss ohci_soft_itd_t *sitd;
698 1.60 augustss usbd_status err;
699 1.224 mrg int i, offs;
700 1.60 augustss usb_dma_t dma;
701 1.60 augustss
702 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
703 1.254.2.18 skrll
704 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
705 1.60 augustss if (sc->sc_freeitds == NULL) {
706 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
707 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
708 1.254.2.35 skrll
709 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
710 1.83 augustss OHCI_ITD_ALIGN, &dma);
711 1.60 augustss if (err)
712 1.254.2.13 skrll return NULL;
713 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
714 1.254.2.58 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
715 1.83 augustss offs = i * OHCI_SITD_SIZE;
716 1.123 augustss sitd = KERNADDR(&dma, offs);
717 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
718 1.195 bouyer sitd->dma = dma;
719 1.195 bouyer sitd->offs = offs;
720 1.60 augustss sitd->nextitd = sc->sc_freeitds;
721 1.60 augustss sc->sc_freeitds = sitd;
722 1.60 augustss }
723 1.60 augustss }
724 1.83 augustss
725 1.60 augustss sitd = sc->sc_freeitds;
726 1.60 augustss sc->sc_freeitds = sitd->nextitd;
727 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
728 1.254.2.35 skrll
729 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
730 1.83 augustss sitd->nextitd = NULL;
731 1.83 augustss sitd->xfer = NULL;
732 1.83 augustss
733 1.83 augustss #ifdef DIAGNOSTIC
734 1.254.2.52 skrll sitd->isdone = true;
735 1.83 augustss #endif
736 1.83 augustss
737 1.254.2.13 skrll return sitd;
738 1.60 augustss }
739 1.60 augustss
740 1.254.2.35 skrll Static void
741 1.254.2.35 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
742 1.60 augustss {
743 1.83 augustss
744 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
745 1.254.2.18 skrll DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
746 1.83 augustss
747 1.254.2.24 skrll KASSERT(sitd->isdone);
748 1.83 augustss #ifdef DIAGNOSTIC
749 1.134 toshii /* Warn double free */
750 1.254.2.31 skrll sitd->isdone = false;
751 1.83 augustss #endif
752 1.83 augustss
753 1.60 augustss sitd->nextitd = sc->sc_freeitds;
754 1.60 augustss sc->sc_freeitds = sitd;
755 1.60 augustss }
756 1.60 augustss
757 1.254.2.35 skrll void
758 1.254.2.35 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
759 1.254.2.35 skrll {
760 1.254.2.35 skrll
761 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
762 1.254.2.35 skrll
763 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
764 1.254.2.35 skrll ohci_free_sitd_locked(sc, sitd);
765 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
766 1.254.2.35 skrll }
767 1.254.2.35 skrll
768 1.254.2.14 skrll int
769 1.91 augustss ohci_init(ohci_softc_t *sc)
770 1.1 augustss {
771 1.1 augustss ohci_soft_ed_t *sed, *psed;
772 1.53 augustss usbd_status err;
773 1.1 augustss int i;
774 1.254.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
775 1.16 augustss
776 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
777 1.254.2.18 skrll
778 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
779 1.199 jmcneill
780 1.198 cegger sc->sc_hcca = NULL;
781 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
782 1.224 mrg
783 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
784 1.254.2.22 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
785 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
786 1.224 mrg
787 1.224 mrg sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE,
788 1.224 mrg ohci_rhsc_softint, sc);
789 1.198 cegger
790 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
791 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
792 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
793 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
794 1.198 cegger
795 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
796 1.254.2.37 skrll "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
797 1.198 cegger
798 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
799 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
800 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
801 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
802 1.55 augustss
803 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
804 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
805 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
806 1.254.2.14 skrll return -1;
807 1.1 augustss }
808 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_1_0;
809 1.254.2.7 skrll sc->sc_bus.ub_usedma = true;
810 1.153 fvdl
811 1.73 augustss /* XXX determine alignment by R/W */
812 1.1 augustss /* Allocate the HCCA area. */
813 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
814 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
815 1.198 cegger if (err) {
816 1.198 cegger sc->sc_hcca = NULL;
817 1.198 cegger return err;
818 1.198 cegger }
819 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
820 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
821 1.1 augustss
822 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
823 1.1 augustss
824 1.60 augustss /* Allocate dummy ED that starts the control list. */
825 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
826 1.53 augustss if (sc->sc_ctrl_head == NULL) {
827 1.254.2.14 skrll err = ENOMEM;
828 1.1 augustss goto bad1;
829 1.1 augustss }
830 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
831 1.34 augustss
832 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
833 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
834 1.53 augustss if (sc->sc_bulk_head == NULL) {
835 1.254.2.14 skrll err = ENOMEM;
836 1.1 augustss goto bad2;
837 1.1 augustss }
838 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
839 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
840 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
841 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
842 1.1 augustss
843 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
844 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
845 1.60 augustss if (sc->sc_isoc_head == NULL) {
846 1.254.2.14 skrll err = ENOMEM;
847 1.60 augustss goto bad3;
848 1.60 augustss }
849 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
850 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
851 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
852 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
853 1.60 augustss
854 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
855 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
856 1.1 augustss sed = ohci_alloc_sed(sc);
857 1.53 augustss if (sed == NULL) {
858 1.1 augustss while (--i >= 0)
859 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
860 1.254.2.14 skrll err = ENOMEM;
861 1.60 augustss goto bad4;
862 1.1 augustss }
863 1.1 augustss /* All ED fields are set to 0. */
864 1.1 augustss sc->sc_eds[i] = sed;
865 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
866 1.60 augustss if (i != 0)
867 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
868 1.60 augustss else
869 1.60 augustss psed= sc->sc_isoc_head;
870 1.60 augustss sed->next = psed;
871 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
872 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
873 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
874 1.1 augustss }
875 1.120 augustss /*
876 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
877 1.1 augustss * the tree set up properly to spread the interrupts.
878 1.1 augustss */
879 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
880 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
881 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
882 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
883 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
884 1.1 augustss
885 1.73 augustss #ifdef OHCI_DEBUG
886 1.254.2.18 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
887 1.254.2.39 skrll if (ohcidebug >= 15) {
888 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
889 1.254.2.18 skrll DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
890 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
891 1.73 augustss }
892 1.254.2.18 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
893 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
894 1.73 augustss }
895 1.254.2.18 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
896 1.73 augustss #endif
897 1.73 augustss
898 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
899 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
900 1.161 augustss rwc = ctl & OHCI_RWC;
901 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
902 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
903 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
904 1.161 augustss
905 1.1 augustss /* Determine in what context we are running. */
906 1.1 augustss if (ctl & OHCI_IR) {
907 1.1 augustss /* SMM active, request change */
908 1.254.2.18 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
909 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
910 1.160 augustss (OHCI_OC | OHCI_MIE))
911 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
912 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
913 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
914 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
915 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
916 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
917 1.1 augustss }
918 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
919 1.1 augustss if ((ctl & OHCI_IR) == 0) {
920 1.199 jmcneill aprint_error_dev(sc->sc_dev,
921 1.199 jmcneill "SMM does not respond, resetting\n");
922 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
923 1.1 augustss goto reset;
924 1.1 augustss }
925 1.103 augustss #if 0
926 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
927 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
928 1.1 augustss /* BIOS started controller. */
929 1.254.2.18 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
930 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
931 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
932 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
933 1.1 augustss }
934 1.103 augustss #endif
935 1.1 augustss } else {
936 1.254.2.18 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
937 1.1 augustss reset:
938 1.1 augustss /* Controller was cold started. */
939 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
940 1.1 augustss }
941 1.1 augustss
942 1.16 augustss /*
943 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
944 1.25 augustss * without it some controllers do not start.
945 1.16 augustss */
946 1.254.2.18 skrll DPRINTF("sc %p: resetting", sc, 0, 0, 0);
947 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
948 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
949 1.16 augustss
950 1.1 augustss /* We now own the host controller and the bus has been reset. */
951 1.1 augustss
952 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
953 1.1 augustss /* Nominal time for a reset is 10 us. */
954 1.1 augustss for (i = 0; i < 10; i++) {
955 1.1 augustss delay(10);
956 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
957 1.1 augustss if (!hcr)
958 1.1 augustss break;
959 1.1 augustss }
960 1.1 augustss if (hcr) {
961 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
962 1.254.2.14 skrll err = EIO;
963 1.60 augustss goto bad5;
964 1.1 augustss }
965 1.52 augustss #ifdef OHCI_DEBUG
966 1.254.2.39 skrll if (ohcidebug >= 15)
967 1.1 augustss ohci_dumpregs(sc);
968 1.1 augustss #endif
969 1.1 augustss
970 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
971 1.1 augustss
972 1.1 augustss /* Set up HC registers. */
973 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
974 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
975 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
976 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
977 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
978 1.55 augustss /* switch on desired functional features */
979 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
980 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
981 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
982 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
983 1.1 augustss /* And finally start it! */
984 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
985 1.1 augustss
986 1.1 augustss /*
987 1.1 augustss * The controller is now OPERATIONAL. Set a some final
988 1.1 augustss * registers that should be set earlier, but that the
989 1.1 augustss * controller ignores when in the SUSPEND state.
990 1.1 augustss */
991 1.161 augustss ival = OHCI_GET_IVAL(fm);
992 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
993 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
994 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
995 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
996 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
997 1.1 augustss
998 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
999 1.249 skrll /* no overcurrent protection */
1000 1.249 skrll desca |= OHCI_NOCP;
1001 1.249 skrll /*
1002 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1003 1.249 skrll * that
1004 1.249 skrll * - ports are always power switched
1005 1.249 skrll * - don't wait for powered root hub port
1006 1.249 skrll */
1007 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1008 1.249 skrll }
1009 1.249 skrll
1010 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1011 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1012 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1013 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1014 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1015 1.1 augustss
1016 1.85 augustss /*
1017 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1018 1.85 augustss * otherwise it will occasionally report 0 ports.
1019 1.85 augustss */
1020 1.145 augustss sc->sc_noport = 0;
1021 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1022 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1023 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1024 1.145 augustss }
1025 1.1 augustss
1026 1.52 augustss #ifdef OHCI_DEBUG
1027 1.254.2.39 skrll if (ohcidebug >= 5)
1028 1.1 augustss ohci_dumpregs(sc);
1029 1.1 augustss #endif
1030 1.120 augustss
1031 1.1 augustss /* Set up the bus struct. */
1032 1.254.2.7 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1033 1.254.2.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1034 1.1 augustss
1035 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1036 1.59 augustss
1037 1.167 augustss /* Finally, turn on interrupts. */
1038 1.254.2.18 skrll DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1039 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1040 1.167 augustss
1041 1.254.2.14 skrll return 0;
1042 1.1 augustss
1043 1.60 augustss bad5:
1044 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1045 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1046 1.60 augustss bad4:
1047 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1048 1.1 augustss bad3:
1049 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1050 1.144 augustss bad2:
1051 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1052 1.1 augustss bad1:
1053 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1054 1.198 cegger sc->sc_hcca = NULL;
1055 1.254.2.13 skrll return err;
1056 1.1 augustss }
1057 1.1 augustss
1058 1.254.2.19 skrll struct usbd_xfer *
1059 1.254.2.23 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1060 1.62 augustss {
1061 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1062 1.254.2.19 skrll struct usbd_xfer *xfer;
1063 1.62 augustss
1064 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
1065 1.118 augustss if (xfer != NULL) {
1066 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1067 1.118 augustss #ifdef DIAGNOSTIC
1068 1.254.2.7 skrll xfer->ux_state = XFER_BUSY;
1069 1.118 augustss #endif
1070 1.118 augustss }
1071 1.254.2.13 skrll return xfer;
1072 1.62 augustss }
1073 1.62 augustss
1074 1.62 augustss void
1075 1.254.2.19 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1076 1.62 augustss {
1077 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1078 1.62 augustss
1079 1.254.2.24 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
1080 1.254.2.24 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1081 1.118 augustss #ifdef DIAGNOSTIC
1082 1.254.2.7 skrll xfer->ux_state = XFER_FREE;
1083 1.118 augustss #endif
1084 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1085 1.42 augustss }
1086 1.42 augustss
1087 1.224 mrg Static void
1088 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1089 1.224 mrg {
1090 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1091 1.224 mrg
1092 1.224 mrg *lock = &sc->sc_lock;
1093 1.224 mrg }
1094 1.224 mrg
1095 1.59 augustss /*
1096 1.59 augustss * Shut down the controller when the system is going down.
1097 1.59 augustss */
1098 1.188 dyoung bool
1099 1.188 dyoung ohci_shutdown(device_t self, int flags)
1100 1.59 augustss {
1101 1.188 dyoung ohci_softc_t *sc = device_private(self);
1102 1.59 augustss
1103 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1104 1.254.2.18 skrll
1105 1.254.2.18 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1106 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1107 1.188 dyoung return true;
1108 1.59 augustss }
1109 1.59 augustss
1110 1.185 jmcneill bool
1111 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1112 1.33 augustss {
1113 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1114 1.185 jmcneill uint32_t ctl;
1115 1.33 augustss
1116 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1117 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1118 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1119 1.224 mrg
1120 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1121 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1122 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1123 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1124 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1125 1.185 jmcneill sc->sc_bulk_head->physaddr);
1126 1.185 jmcneill if (sc->sc_intre)
1127 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1128 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1129 1.185 jmcneill if (sc->sc_control)
1130 1.185 jmcneill ctl = sc->sc_control;
1131 1.185 jmcneill else
1132 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1133 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1134 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1135 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1136 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1137 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1138 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1139 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1140 1.224 mrg
1141 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1142 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1143 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1144 1.185 jmcneill
1145 1.185 jmcneill return true;
1146 1.185 jmcneill }
1147 1.185 jmcneill
1148 1.185 jmcneill bool
1149 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1150 1.185 jmcneill {
1151 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1152 1.185 jmcneill uint32_t ctl;
1153 1.95 augustss
1154 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1155 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1156 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1157 1.224 mrg
1158 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1159 1.185 jmcneill if (sc->sc_control == 0) {
1160 1.185 jmcneill /*
1161 1.185 jmcneill * Preserve register values, in case that BIOS
1162 1.185 jmcneill * does not recover them.
1163 1.185 jmcneill */
1164 1.185 jmcneill sc->sc_control = ctl;
1165 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1166 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1167 1.95 augustss }
1168 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1169 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1170 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1171 1.224 mrg
1172 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1173 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1174 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1175 1.185 jmcneill
1176 1.185 jmcneill return true;
1177 1.33 augustss }
1178 1.33 augustss
1179 1.52 augustss #ifdef OHCI_DEBUG
1180 1.1 augustss void
1181 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1182 1.1 augustss {
1183 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1184 1.254.2.18 skrll
1185 1.254.2.18 skrll DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
1186 1.41 augustss OREAD4(sc, OHCI_REVISION),
1187 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1188 1.254.2.18 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1189 1.254.2.18 skrll DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x",
1190 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1191 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1192 1.254.2.18 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1193 1.254.2.18 skrll DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
1194 1.41 augustss OREAD4(sc, OHCI_HCCA),
1195 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1196 1.254.2.18 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1197 1.254.2.18 skrll DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
1198 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1199 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1200 1.254.2.18 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1201 1.254.2.18 skrll DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x",
1202 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1203 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1204 1.254.2.18 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1205 1.254.2.18 skrll DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
1206 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1207 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1208 1.254.2.18 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1209 1.254.2.18 skrll DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x",
1210 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1211 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1212 1.254.2.18 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1213 1.254.2.18 skrll DPRINTF(" port1=0x%08x port2=0x%08x",
1214 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1215 1.254.2.18 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1216 1.254.2.18 skrll DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x",
1217 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1218 1.254.2.18 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1219 1.1 augustss }
1220 1.1 augustss #endif
1221 1.1 augustss
1222 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1223 1.53 augustss
1224 1.1 augustss int
1225 1.91 augustss ohci_intr(void *p)
1226 1.1 augustss {
1227 1.1 augustss ohci_softc_t *sc = p;
1228 1.224 mrg int ret = 0;
1229 1.111 augustss
1230 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1231 1.254.2.18 skrll
1232 1.224 mrg if (sc == NULL)
1233 1.254.2.13 skrll return 0;
1234 1.53 augustss
1235 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1236 1.224 mrg
1237 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1238 1.224 mrg goto done;
1239 1.224 mrg
1240 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1241 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling) {
1242 1.254.2.18 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1243 1.154 joff /* for level triggered intrs, should do something to ack */
1244 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1245 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1246 1.155 perry
1247 1.224 mrg goto done;
1248 1.57 augustss }
1249 1.53 augustss
1250 1.224 mrg ret = ohci_intr1(sc);
1251 1.224 mrg
1252 1.224 mrg done:
1253 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1254 1.224 mrg return ret;
1255 1.53 augustss }
1256 1.53 augustss
1257 1.82 augustss Static int
1258 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1259 1.53 augustss {
1260 1.254.2.1 skrll uint32_t intrs, eintrs;
1261 1.1 augustss
1262 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1263 1.105 augustss
1264 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1265 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1266 1.15 augustss #ifdef DIAGNOSTIC
1267 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1268 1.15 augustss #endif
1269 1.254.2.13 skrll return 0;
1270 1.15 augustss }
1271 1.15 augustss
1272 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1273 1.224 mrg
1274 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1275 1.1 augustss if (!intrs)
1276 1.254.2.13 skrll return 0;
1277 1.55 augustss
1278 1.254.2.32 skrll /* Acknowledge */
1279 1.254.2.32 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1280 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1281 1.254.2.18 skrll DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
1282 1.254.2.18 skrll DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
1283 1.254.2.18 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1284 1.254.2.18 skrll sc->sc_eintrs);
1285 1.211 matt
1286 1.211 matt if (!eintrs) {
1287 1.254.2.13 skrll return 0;
1288 1.211 matt }
1289 1.1 augustss
1290 1.1 augustss if (eintrs & OHCI_SO) {
1291 1.100 augustss sc->sc_overrun_cnt++;
1292 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1293 1.100 augustss printf("%s: %u scheduling overruns\n",
1294 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1295 1.100 augustss sc->sc_overrun_cnt = 0;
1296 1.100 augustss }
1297 1.1 augustss /* XXX do what */
1298 1.106 augustss eintrs &= ~OHCI_SO;
1299 1.1 augustss }
1300 1.1 augustss if (eintrs & OHCI_WDH) {
1301 1.157 mycroft /*
1302 1.157 mycroft * We block the interrupt below, and reenable it later from
1303 1.157 mycroft * ohci_softintr().
1304 1.157 mycroft */
1305 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1306 1.1 augustss }
1307 1.1 augustss if (eintrs & OHCI_RD) {
1308 1.254.2.47 skrll DPRINTFN(5, "resume detect", sc, 0, 0, 0);
1309 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1310 1.1 augustss /* XXX process resume detect */
1311 1.1 augustss }
1312 1.1 augustss if (eintrs & OHCI_UE) {
1313 1.254.2.47 skrll DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0);
1314 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1315 1.190 drochner device_xname(sc->sc_dev));
1316 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1317 1.1 augustss /* XXX what else */
1318 1.1 augustss }
1319 1.1 augustss if (eintrs & OHCI_RHSC) {
1320 1.120 augustss /*
1321 1.157 mycroft * We block the interrupt below, and reenable it later from
1322 1.157 mycroft * a timeout.
1323 1.1 augustss */
1324 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1325 1.1 augustss }
1326 1.1 augustss
1327 1.106 augustss if (eintrs != 0) {
1328 1.157 mycroft /* Block unprocessed interrupts. */
1329 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1330 1.106 augustss sc->sc_eintrs &= ~eintrs;
1331 1.254.2.18 skrll DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0);
1332 1.106 augustss }
1333 1.1 augustss
1334 1.254.2.13 skrll return 1;
1335 1.1 augustss }
1336 1.1 augustss
1337 1.1 augustss void
1338 1.104 augustss ohci_rhsc_enable(void *v_sc)
1339 1.104 augustss {
1340 1.104 augustss ohci_softc_t *sc = v_sc;
1341 1.104 augustss
1342 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1343 1.254.2.18 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1344 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1345 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1346 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1347 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1348 1.1 augustss }
1349 1.1 augustss
1350 1.52 augustss #ifdef OHCI_DEBUG
1351 1.166 drochner const char *ohci_cc_strs[] = {
1352 1.13 augustss "NO_ERROR",
1353 1.13 augustss "CRC",
1354 1.13 augustss "BIT_STUFFING",
1355 1.13 augustss "DATA_TOGGLE_MISMATCH",
1356 1.13 augustss "STALL",
1357 1.13 augustss "DEVICE_NOT_RESPONDING",
1358 1.13 augustss "PID_CHECK_FAILURE",
1359 1.13 augustss "UNEXPECTED_PID",
1360 1.13 augustss "DATA_OVERRUN",
1361 1.13 augustss "DATA_UNDERRUN",
1362 1.13 augustss "BUFFER_OVERRUN",
1363 1.13 augustss "BUFFER_UNDERRUN",
1364 1.67 augustss "reserved",
1365 1.67 augustss "reserved",
1366 1.67 augustss "NOT_ACCESSED",
1367 1.13 augustss "NOT_ACCESSED",
1368 1.13 augustss };
1369 1.13 augustss #endif
1370 1.13 augustss
1371 1.1 augustss void
1372 1.157 mycroft ohci_softintr(void *v)
1373 1.83 augustss {
1374 1.190 drochner struct usbd_bus *bus = v;
1375 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1376 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1377 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1378 1.254.2.19 skrll struct usbd_xfer *xfer;
1379 1.157 mycroft struct ohci_pipe *opipe;
1380 1.224 mrg int len, cc;
1381 1.157 mycroft int i, j, actlen, iframes, uedir;
1382 1.157 mycroft ohci_physaddr_t done;
1383 1.157 mycroft
1384 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1385 1.224 mrg
1386 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1387 1.157 mycroft
1388 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1389 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1390 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1391 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1392 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1393 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1394 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1395 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1396 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1397 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1398 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1399 1.83 augustss
1400 1.83 augustss /* Reverse the done list. */
1401 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1402 1.83 augustss std = ohci_hash_find_td(sc, done);
1403 1.83 augustss if (std != NULL) {
1404 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1405 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1406 1.83 augustss std->dnext = sdone;
1407 1.168 augustss done = O32TOH(std->td.td_nexttd);
1408 1.83 augustss sdone = std;
1409 1.254.2.18 skrll DPRINTFN(10, "add TD %p", std, 0, 0, 0);
1410 1.83 augustss continue;
1411 1.83 augustss }
1412 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1413 1.83 augustss if (sitd != NULL) {
1414 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1415 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1416 1.83 augustss sitd->dnext = sidone;
1417 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1418 1.83 augustss sidone = sitd;
1419 1.254.2.18 skrll DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
1420 1.83 augustss continue;
1421 1.83 augustss }
1422 1.254.2.57 skrll DPRINTFN(10, "addr %p not found", done, 0, 0, 0);
1423 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1424 1.218 jmcneill (u_long)done);
1425 1.218 jmcneill break;
1426 1.83 augustss }
1427 1.83 augustss
1428 1.254.2.18 skrll DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
1429 1.254.2.41 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1430 1.52 augustss #ifdef OHCI_DEBUG
1431 1.254.2.39 skrll if (ohcidebug >= 10) {
1432 1.234 skrll for (std = sdone; std; std = std->dnext)
1433 1.254.2.1 skrll ohci_dump_td(sc, std);
1434 1.1 augustss }
1435 1.1 augustss #endif
1436 1.254.2.41 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1437 1.1 augustss
1438 1.48 augustss for (std = sdone; std; std = stdnext) {
1439 1.53 augustss xfer = std->xfer;
1440 1.48 augustss stdnext = std->dnext;
1441 1.254.2.18 skrll DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer,
1442 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1443 1.71 augustss if (xfer == NULL) {
1444 1.117 augustss /*
1445 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1446 1.71 augustss * with this TD. It is tailp that happened to end up on
1447 1.71 augustss * the done queue.
1448 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1449 1.71 augustss */
1450 1.71 augustss continue;
1451 1.71 augustss }
1452 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1453 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1454 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1455 1.38 augustss /* Handled by abort routine. */
1456 1.83 augustss continue;
1457 1.83 augustss }
1458 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
1459 1.141 mycroft
1460 1.141 mycroft len = std->len;
1461 1.141 mycroft if (std->td.td_cbp != 0)
1462 1.168 augustss len -= O32TOH(std->td.td_be) -
1463 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1464 1.254.2.18 skrll DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
1465 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1466 1.254.2.7 skrll xfer->ux_actlen += len;
1467 1.141 mycroft
1468 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1469 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1470 1.254.2.42 skrll ohci_hash_rem_td(sc, std);
1471 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1472 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1473 1.53 augustss usb_transfer_complete(xfer);
1474 1.21 augustss }
1475 1.1 augustss } else {
1476 1.48 augustss /*
1477 1.48 augustss * Endpoint is halted. First unlink all the TDs
1478 1.48 augustss * belonging to the failed transfer, and then restart
1479 1.48 augustss * the endpoint.
1480 1.48 augustss */
1481 1.1 augustss ohci_soft_td_t *p, *n;
1482 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1483 1.48 augustss
1484 1.254.2.43 skrll DPRINTFN(10, "error cc=%d", cc, 0, 0, 0);
1485 1.48 augustss
1486 1.254.2.35 skrll /* remove xfer's TDs from the hash */
1487 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1488 1.1 augustss n = p->nexttd;
1489 1.254.2.35 skrll ohci_hash_rem_td(sc, p);
1490 1.1 augustss }
1491 1.48 augustss
1492 1.254.2.44 skrll ohci_soft_ed_t *sed = opipe->sed;
1493 1.254.2.44 skrll
1494 1.254.2.44 skrll /* clear halt and TD chain */
1495 1.254.2.44 skrll sed->ed.ed_headp = HTOO32(p->physaddr);
1496 1.254.2.45 skrll usb_syncmem(&sed->dma,
1497 1.254.2.46 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1498 1.254.2.45 skrll sizeof(sed->ed.ed_headp),
1499 1.254.2.44 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1500 1.254.2.44 skrll
1501 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1502 1.48 augustss
1503 1.254.2.44 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1504 1.254.2.44 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1505 1.254.2.44 skrll else if (cc == OHCI_CC_STALL)
1506 1.254.2.7 skrll xfer->ux_status = USBD_STALLED;
1507 1.1 augustss else
1508 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1509 1.53 augustss usb_transfer_complete(xfer);
1510 1.1 augustss }
1511 1.1 augustss }
1512 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1513 1.83 augustss #ifdef OHCI_DEBUG
1514 1.254.2.39 skrll if (ohcidebug >= 10) {
1515 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1516 1.254.2.1 skrll ohci_dump_itd(sc, sitd);
1517 1.83 augustss }
1518 1.83 augustss #endif
1519 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1520 1.83 augustss
1521 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1522 1.83 augustss xfer = sitd->xfer;
1523 1.83 augustss sitdnext = sitd->dnext;
1524 1.254.2.18 skrll DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
1525 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1526 1.83 augustss if (xfer == NULL)
1527 1.83 augustss continue;
1528 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1529 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1530 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1531 1.83 augustss /* Handled by abort routine. */
1532 1.83 augustss continue;
1533 1.83 augustss }
1534 1.254.2.24 skrll KASSERT(!sitd->isdone);
1535 1.83 augustss #ifdef DIAGNOSTIC
1536 1.254.2.31 skrll sitd->isdone = true;
1537 1.83 augustss #endif
1538 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1539 1.134 toshii ohci_soft_itd_t *next;
1540 1.134 toshii
1541 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1542 1.254.2.21 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1543 1.254.2.7 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1544 1.134 toshii bEndpointAddress);
1545 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1546 1.134 toshii actlen = 0;
1547 1.254.2.7 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1548 1.134 toshii sitd = next) {
1549 1.134 toshii next = sitd->nextitd;
1550 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1551 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1552 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1553 1.134 toshii /* For input, update frlengths with actual */
1554 1.134 toshii /* XXX anything necessary for output? */
1555 1.134 toshii if (uedir == UE_DIR_IN &&
1556 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1557 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1558 1.135 toshii sitd->itd.itd_flags));
1559 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1560 1.168 augustss len = O16TOH(sitd->
1561 1.134 toshii itd.itd_offset[j]);
1562 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1563 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1564 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1565 1.158 toshii len = 0;
1566 1.158 toshii else
1567 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1568 1.254.2.7 skrll xfer->ux_frlengths[i] = len;
1569 1.134 toshii actlen += len;
1570 1.134 toshii }
1571 1.134 toshii }
1572 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1573 1.134 toshii break;
1574 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1575 1.254.2.35 skrll
1576 1.83 augustss }
1577 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1578 1.134 toshii if (uedir == UE_DIR_IN &&
1579 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1580 1.254.2.7 skrll xfer->ux_actlen = actlen;
1581 1.254.2.7 skrll xfer->ux_hcpriv = NULL;
1582 1.134 toshii
1583 1.83 augustss usb_transfer_complete(xfer);
1584 1.83 augustss }
1585 1.83 augustss }
1586 1.83 augustss
1587 1.119 augustss if (sc->sc_softwake) {
1588 1.119 augustss sc->sc_softwake = 0;
1589 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1590 1.119 augustss }
1591 1.119 augustss
1592 1.254.2.18 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1593 1.1 augustss }
1594 1.1 augustss
1595 1.1 augustss void
1596 1.254.2.19 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1597 1.1 augustss {
1598 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1599 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1600 1.254.2.7 skrll int len = UGETW(xfer->ux_request.wLength);
1601 1.254.2.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1602 1.195 bouyer
1603 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1604 1.254.2.18 skrll DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
1605 1.1 augustss
1606 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1607 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1608 1.224 mrg
1609 1.195 bouyer if (len)
1610 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1611 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1612 1.254.2.30 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1613 1.254.2.30 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1614 1.1 augustss }
1615 1.1 augustss
1616 1.1 augustss void
1617 1.254.2.19 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1618 1.1 augustss {
1619 1.254.2.54 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1620 1.195 bouyer int isread =
1621 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1622 1.1 augustss
1623 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1624 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1625 1.1 augustss
1626 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1627 1.224 mrg
1628 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1629 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1630 1.1 augustss }
1631 1.1 augustss
1632 1.1 augustss void
1633 1.254.2.19 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1634 1.3 augustss {
1635 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1636 1.254.2.25 skrll
1637 1.195 bouyer int isread =
1638 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1639 1.195 bouyer
1640 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1641 1.224 mrg
1642 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1643 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1644 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1645 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1646 1.3 augustss }
1647 1.3 augustss
1648 1.224 mrg Static void
1649 1.224 mrg ohci_rhsc_softint(void *arg)
1650 1.224 mrg {
1651 1.224 mrg ohci_softc_t *sc = arg;
1652 1.224 mrg
1653 1.224 mrg mutex_enter(&sc->sc_lock);
1654 1.224 mrg
1655 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1656 1.224 mrg
1657 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1658 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1659 1.224 mrg
1660 1.224 mrg mutex_exit(&sc->sc_lock);
1661 1.224 mrg }
1662 1.224 mrg
1663 1.3 augustss void
1664 1.254.2.19 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1665 1.1 augustss {
1666 1.1 augustss u_char *p;
1667 1.1 augustss int i, m;
1668 1.243 martin int hstatus __unused;
1669 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1670 1.1 augustss
1671 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1672 1.224 mrg
1673 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1674 1.254.2.18 skrll DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0);
1675 1.1 augustss
1676 1.53 augustss if (xfer == NULL) {
1677 1.1 augustss /* Just ignore the change. */
1678 1.1 augustss return;
1679 1.1 augustss }
1680 1.1 augustss
1681 1.254.2.7 skrll p = xfer->ux_buf;
1682 1.254.2.7 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1683 1.254.2.7 skrll memset(p, 0, xfer->ux_length);
1684 1.1 augustss for (i = 1; i <= m; i++) {
1685 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1686 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1687 1.1 augustss p[i/8] |= 1 << (i%8);
1688 1.1 augustss }
1689 1.254.2.18 skrll DPRINTF("change=0x%02x", *p, 0, 0, 0);
1690 1.254.2.7 skrll xfer->ux_actlen = xfer->ux_length;
1691 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1692 1.1 augustss
1693 1.53 augustss usb_transfer_complete(xfer);
1694 1.38 augustss }
1695 1.38 augustss
1696 1.38 augustss void
1697 1.254.2.19 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1698 1.65 augustss {
1699 1.254.2.54 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1700 1.254.2.54 skrll
1701 1.254.2.54 skrll KASSERT(mutex_owned(&sc->sc_lock));
1702 1.254.2.54 skrll
1703 1.254.2.54 skrll KASSERT(sc->sc_intrxfer == xfer);
1704 1.254.2.54 skrll sc->sc_intrxfer = NULL;
1705 1.65 augustss }
1706 1.65 augustss
1707 1.1 augustss /*
1708 1.1 augustss * Wait here until controller claims to have an interrupt.
1709 1.1 augustss * Then call ohci_intr and return. Use timeout to avoid waiting
1710 1.1 augustss * too long.
1711 1.1 augustss */
1712 1.1 augustss void
1713 1.254.2.19 skrll ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer)
1714 1.1 augustss {
1715 1.163 augustss int timo;
1716 1.254.2.1 skrll uint32_t intrs;
1717 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1718 1.1 augustss
1719 1.224 mrg mutex_enter(&sc->sc_lock);
1720 1.224 mrg
1721 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
1722 1.254.2.7 skrll for (timo = xfer->ux_timeout; timo >= 0; timo--) {
1723 1.20 augustss usb_delay_ms(&sc->sc_bus, 1);
1724 1.116 augustss if (sc->sc_dying)
1725 1.116 augustss break;
1726 1.1 augustss intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
1727 1.254.2.18 skrll DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0);
1728 1.52 augustss #ifdef OHCI_DEBUG
1729 1.1 augustss if (ohcidebug > 15)
1730 1.1 augustss ohci_dumpregs(sc);
1731 1.1 augustss #endif
1732 1.1 augustss if (intrs) {
1733 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1734 1.53 augustss ohci_intr1(sc);
1735 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1736 1.254.2.7 skrll if (xfer->ux_status != USBD_IN_PROGRESS)
1737 1.230 jmcneill goto done;
1738 1.1 augustss }
1739 1.1 augustss }
1740 1.15 augustss
1741 1.15 augustss /* Timeout */
1742 1.254.2.18 skrll DPRINTF("timeout", 0, 0, 0, 0);
1743 1.254.2.7 skrll xfer->ux_status = USBD_TIMEOUT;
1744 1.53 augustss usb_transfer_complete(xfer);
1745 1.224 mrg
1746 1.230 jmcneill done:
1747 1.224 mrg mutex_exit(&sc->sc_lock);
1748 1.5 augustss }
1749 1.5 augustss
1750 1.5 augustss void
1751 1.91 augustss ohci_poll(struct usbd_bus *bus)
1752 1.5 augustss {
1753 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1754 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1755 1.254.2.18 skrll
1756 1.105 augustss #ifdef OHCI_DEBUG
1757 1.105 augustss static int last;
1758 1.105 augustss int new;
1759 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1760 1.105 augustss if (new != last) {
1761 1.254.2.18 skrll DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0);
1762 1.105 augustss last = new;
1763 1.105 augustss }
1764 1.105 augustss #endif
1765 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1766 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1767 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1768 1.53 augustss ohci_intr1(sc);
1769 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1770 1.224 mrg }
1771 1.1 augustss }
1772 1.1 augustss
1773 1.1 augustss /*
1774 1.224 mrg * Add an ED to the schedule. Called with USB lock held.
1775 1.1 augustss */
1776 1.224 mrg Static void
1777 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1778 1.1 augustss {
1779 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1780 1.254.2.18 skrll DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0);
1781 1.113 augustss
1782 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1783 1.224 mrg
1784 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1785 1.195 bouyer sizeof(head->ed.ed_nexted),
1786 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1787 1.1 augustss sed->next = head->next;
1788 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1789 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1790 1.195 bouyer sizeof(sed->ed.ed_nexted),
1791 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1792 1.1 augustss head->next = sed;
1793 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1794 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1795 1.195 bouyer sizeof(head->ed.ed_nexted),
1796 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1797 1.1 augustss }
1798 1.1 augustss
1799 1.1 augustss /*
1800 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1801 1.3 augustss */
1802 1.224 mrg Static void
1803 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1804 1.3 augustss {
1805 1.120 augustss ohci_soft_ed_t *p;
1806 1.3 augustss
1807 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1808 1.224 mrg
1809 1.3 augustss /* XXX */
1810 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1811 1.3 augustss ;
1812 1.254.2.20 skrll KASSERT(p != NULL);
1813 1.254.2.20 skrll
1814 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1815 1.195 bouyer sizeof(sed->ed.ed_nexted),
1816 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1817 1.3 augustss p->next = sed->next;
1818 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1819 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1820 1.195 bouyer sizeof(p->ed.ed_nexted),
1821 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1822 1.3 augustss }
1823 1.3 augustss
1824 1.3 augustss /*
1825 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1826 1.1 augustss * the host controller. This queue is the processed by software.
1827 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1828 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1829 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1830 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1831 1.1 augustss * hash value.
1832 1.1 augustss */
1833 1.1 augustss
1834 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1835 1.224 mrg /* Called with USB lock held. */
1836 1.1 augustss void
1837 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1838 1.1 augustss {
1839 1.1 augustss int h = HASH(std->physaddr);
1840 1.1 augustss
1841 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1842 1.224 mrg
1843 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1844 1.1 augustss }
1845 1.1 augustss
1846 1.224 mrg /* Called with USB lock held. */
1847 1.1 augustss void
1848 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1849 1.1 augustss {
1850 1.46 augustss
1851 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1852 1.224 mrg
1853 1.1 augustss LIST_REMOVE(std, hnext);
1854 1.1 augustss }
1855 1.1 augustss
1856 1.1 augustss ohci_soft_td_t *
1857 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1858 1.1 augustss {
1859 1.1 augustss int h = HASH(a);
1860 1.1 augustss ohci_soft_td_t *std;
1861 1.1 augustss
1862 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1863 1.53 augustss std != NULL;
1864 1.1 augustss std = LIST_NEXT(std, hnext))
1865 1.1 augustss if (std->physaddr == a)
1866 1.254.2.13 skrll return std;
1867 1.254.2.13 skrll return NULL;
1868 1.83 augustss }
1869 1.83 augustss
1870 1.224 mrg /* Called with USB lock held. */
1871 1.83 augustss void
1872 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1873 1.83 augustss {
1874 1.83 augustss int h = HASH(sitd->physaddr);
1875 1.83 augustss
1876 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1877 1.254.2.18 skrll
1878 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1879 1.224 mrg
1880 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1881 1.254.2.18 skrll 0, 0);
1882 1.83 augustss
1883 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1884 1.83 augustss }
1885 1.83 augustss
1886 1.224 mrg /* Called with USB lock held. */
1887 1.83 augustss void
1888 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1889 1.83 augustss {
1890 1.83 augustss
1891 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1892 1.254.2.18 skrll
1893 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1894 1.224 mrg
1895 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1896 1.254.2.18 skrll 0, 0);
1897 1.83 augustss
1898 1.83 augustss LIST_REMOVE(sitd, hnext);
1899 1.83 augustss }
1900 1.83 augustss
1901 1.83 augustss ohci_soft_itd_t *
1902 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1903 1.83 augustss {
1904 1.83 augustss int h = HASH(a);
1905 1.83 augustss ohci_soft_itd_t *sitd;
1906 1.83 augustss
1907 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1908 1.83 augustss sitd != NULL;
1909 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1910 1.83 augustss if (sitd->physaddr == a)
1911 1.254.2.13 skrll return sitd;
1912 1.254.2.13 skrll return NULL;
1913 1.1 augustss }
1914 1.1 augustss
1915 1.1 augustss void
1916 1.91 augustss ohci_timeout(void *addr)
1917 1.1 augustss {
1918 1.254.2.25 skrll struct usbd_xfer *xfer = addr;
1919 1.254.2.25 skrll struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer);
1920 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1921 1.114 augustss
1922 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1923 1.254.2.18 skrll DPRINTF("oxfer=%p", oxfer, 0, 0, 0);
1924 1.114 augustss
1925 1.116 augustss if (sc->sc_dying) {
1926 1.224 mrg mutex_enter(&sc->sc_lock);
1927 1.254.2.25 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1928 1.224 mrg mutex_exit(&sc->sc_lock);
1929 1.116 augustss return;
1930 1.116 augustss }
1931 1.116 augustss
1932 1.114 augustss /* Execute the abort in a process context. */
1933 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1934 1.231 jmcneill USB_TASKQ_MPSAFE);
1935 1.254.2.25 skrll usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task,
1936 1.178 joerg USB_TASKQ_HC);
1937 1.114 augustss }
1938 1.114 augustss
1939 1.114 augustss void
1940 1.114 augustss ohci_timeout_task(void *addr)
1941 1.114 augustss {
1942 1.254.2.19 skrll struct usbd_xfer *xfer = addr;
1943 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1944 1.1 augustss
1945 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1946 1.254.2.18 skrll
1947 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1948 1.45 augustss
1949 1.224 mrg mutex_enter(&sc->sc_lock);
1950 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1951 1.224 mrg mutex_exit(&sc->sc_lock);
1952 1.1 augustss }
1953 1.1 augustss
1954 1.52 augustss #ifdef OHCI_DEBUG
1955 1.1 augustss void
1956 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1957 1.1 augustss {
1958 1.254.2.34 skrll for (; std; std = std->nexttd) {
1959 1.168 augustss ohci_dump_td(sc, std);
1960 1.254.2.34 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
1961 1.254.2.34 skrll "std %p next %p", std, std->nexttd);
1962 1.254.2.34 skrll }
1963 1.1 augustss }
1964 1.1 augustss
1965 1.1 augustss void
1966 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1967 1.1 augustss {
1968 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1969 1.92 tv
1970 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1971 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1972 1.254.2.18 skrll
1973 1.254.2.18 skrll uint32_t flags = O32TOH(std->td.td_flags);
1974 1.254.2.40 skrll DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0);
1975 1.254.2.18 skrll DPRINTF(" round=%d DP=%x DI=%x T=%x",
1976 1.254.2.18 skrll !!(flags & OHCI_TD_R),
1977 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1978 1.254.2.18 skrll OHCI_TD_GET_DI(flags),
1979 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1980 1.254.2.18 skrll DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags),
1981 1.254.2.18 skrll 0, 0);
1982 1.254.2.47 skrll DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx",
1983 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1984 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1985 1.254.2.18 skrll (u_long)O32TOH(std->td.td_be), 0);
1986 1.1 augustss }
1987 1.1 augustss
1988 1.1 augustss void
1989 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1990 1.83 augustss {
1991 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1992 1.83 augustss
1993 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1994 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1995 1.254.2.18 skrll
1996 1.254.2.18 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
1997 1.254.2.40 skrll DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0);
1998 1.254.2.18 skrll DPRINTF(" sf=%d di=%d fc=%d cc=%d",
1999 1.254.2.18 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
2000 1.254.2.18 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
2001 1.254.2.18 skrll DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x",
2002 1.254.2.18 skrll O32TOH(sitd->itd.itd_bp0),
2003 1.254.2.18 skrll O32TOH(sitd->itd.itd_nextitd),
2004 1.254.2.18 skrll O32TOH(sitd->itd.itd_be), 0);
2005 1.254.2.18 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
2006 1.254.2.18 skrll DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x "
2007 1.254.2.18 skrll "offs[2] = 0x%04x offs[3] = 0x%04x",
2008 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[0]),
2009 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[1]),
2010 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[2]),
2011 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[3]));
2012 1.254.2.18 skrll DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x "
2013 1.254.2.18 skrll "offs[6] = 0x%04x offs[7] = 0x%04x",
2014 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[4]),
2015 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[5]),
2016 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[6]),
2017 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[7]));
2018 1.83 augustss }
2019 1.83 augustss
2020 1.83 augustss void
2021 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2022 1.83 augustss {
2023 1.83 augustss for (; sitd; sitd = sitd->nextitd)
2024 1.168 augustss ohci_dump_itd(sc, sitd);
2025 1.83 augustss }
2026 1.83 augustss
2027 1.83 augustss void
2028 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2029 1.1 augustss {
2030 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2031 1.92 tv
2032 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2033 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2034 1.254.2.18 skrll
2035 1.254.2.18 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
2036 1.254.2.18 skrll DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0);
2037 1.254.2.18 skrll DPRINTF(" addr=%d endpt=%d maxp=%d",
2038 1.254.2.18 skrll OHCI_ED_GET_FA(flags),
2039 1.254.2.18 skrll OHCI_ED_GET_EN(flags),
2040 1.254.2.18 skrll OHCI_ED_GET_MAXP(flags),
2041 1.254.2.18 skrll 0);
2042 1.254.2.18 skrll DPRINTF(" dir=%d speed=%d skip=%d iso=%d",
2043 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
2044 1.254.2.18 skrll !!(flags & OHCI_ED_SPEED),
2045 1.254.2.18 skrll !!(flags & OHCI_ED_SKIP),
2046 1.254.2.18 skrll !!(flags & OHCI_ED_FORMAT_ISO));
2047 1.254.2.18 skrll DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp),
2048 1.254.2.18 skrll 0, 0, 0);
2049 1.254.2.18 skrll DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d",
2050 1.254.2.18 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
2051 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
2052 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2053 1.1 augustss }
2054 1.1 augustss #endif
2055 1.1 augustss
2056 1.1 augustss usbd_status
2057 1.254.2.19 skrll ohci_open(struct usbd_pipe *pipe)
2058 1.1 augustss {
2059 1.254.2.19 skrll struct usbd_device *dev = pipe->up_dev;
2060 1.254.2.12 skrll struct usbd_bus *bus = dev->ud_bus;
2061 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2062 1.254.2.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2063 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2064 1.254.2.7 skrll uint8_t addr = dev->ud_addr;
2065 1.254.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2066 1.1 augustss ohci_soft_ed_t *sed;
2067 1.1 augustss ohci_soft_td_t *std;
2068 1.60 augustss ohci_soft_itd_t *sitd;
2069 1.60 augustss ohci_physaddr_t tdphys;
2070 1.254.2.1 skrll uint32_t fmt;
2071 1.224 mrg usbd_status err = USBD_NOMEM;
2072 1.64 augustss int ival;
2073 1.1 augustss
2074 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2075 1.254.2.18 skrll DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr,
2076 1.254.2.18 skrll ed->bEndpointAddress, bus->ub_rhaddr);
2077 1.81 augustss
2078 1.224 mrg if (sc->sc_dying) {
2079 1.241 skrll return USBD_IOERROR;
2080 1.224 mrg }
2081 1.116 augustss
2082 1.90 thorpej std = NULL;
2083 1.90 thorpej sed = NULL;
2084 1.90 thorpej
2085 1.254.2.12 skrll if (addr == bus->ub_rhaddr) {
2086 1.1 augustss switch (ed->bEndpointAddress) {
2087 1.1 augustss case USB_CONTROL_ENDPOINT:
2088 1.254.2.12 skrll pipe->up_methods = &roothub_ctrl_methods;
2089 1.1 augustss break;
2090 1.254.2.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2091 1.254.2.7 skrll pipe->up_methods = &ohci_root_intr_methods;
2092 1.1 augustss break;
2093 1.1 augustss default:
2094 1.224 mrg err = USBD_INVAL;
2095 1.241 skrll goto bad;
2096 1.1 augustss }
2097 1.1 augustss } else {
2098 1.1 augustss sed = ohci_alloc_sed(sc);
2099 1.53 augustss if (sed == NULL)
2100 1.241 skrll goto bad;
2101 1.1 augustss opipe->sed = sed;
2102 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2103 1.60 augustss sitd = ohci_alloc_sitd(sc);
2104 1.127 augustss if (sitd == NULL)
2105 1.241 skrll goto bad;
2106 1.241 skrll
2107 1.60 augustss opipe->tail.itd = sitd;
2108 1.76 tsutsui tdphys = sitd->physaddr;
2109 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2110 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2111 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2112 1.83 augustss else
2113 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2114 1.60 augustss } else {
2115 1.60 augustss std = ohci_alloc_std(sc);
2116 1.127 augustss if (std == NULL)
2117 1.241 skrll goto bad;
2118 1.241 skrll
2119 1.60 augustss opipe->tail.td = std;
2120 1.76 tsutsui tdphys = std->physaddr;
2121 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2122 1.60 augustss }
2123 1.168 augustss sed->ed.ed_flags = HTOO32(
2124 1.120 augustss OHCI_ED_SET_FA(addr) |
2125 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2126 1.254.2.7 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2127 1.109 augustss fmt |
2128 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2129 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2130 1.254.2.7 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2131 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2132 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2133 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2134 1.1 augustss
2135 1.60 augustss switch (xfertype) {
2136 1.1 augustss case UE_CONTROL:
2137 1.254.2.7 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2138 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2139 1.120 augustss sizeof(usb_device_request_t),
2140 1.254.2.21 skrll 0, &opipe->ctrl.reqdma);
2141 1.53 augustss if (err)
2142 1.1 augustss goto bad;
2143 1.224 mrg mutex_enter(&sc->sc_lock);
2144 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2145 1.224 mrg mutex_exit(&sc->sc_lock);
2146 1.1 augustss break;
2147 1.1 augustss case UE_INTERRUPT:
2148 1.254.2.7 skrll pipe->up_methods = &ohci_device_intr_methods;
2149 1.254.2.7 skrll ival = pipe->up_interval;
2150 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2151 1.64 augustss ival = ed->bInterval;
2152 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2153 1.226 skrll if (err)
2154 1.226 skrll goto bad;
2155 1.226 skrll break;
2156 1.1 augustss case UE_ISOCHRONOUS:
2157 1.254.2.59 skrll pipe->up_serialise = false;
2158 1.254.2.7 skrll pipe->up_methods = &ohci_device_isoc_methods;
2159 1.254.2.13 skrll return ohci_setup_isoc(pipe);
2160 1.1 augustss case UE_BULK:
2161 1.254.2.7 skrll pipe->up_methods = &ohci_device_bulk_methods;
2162 1.224 mrg mutex_enter(&sc->sc_lock);
2163 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2164 1.224 mrg mutex_exit(&sc->sc_lock);
2165 1.3 augustss break;
2166 1.1 augustss }
2167 1.1 augustss }
2168 1.224 mrg
2169 1.224 mrg return USBD_NORMAL_COMPLETION;
2170 1.1 augustss
2171 1.1 augustss bad:
2172 1.241 skrll if (std != NULL) {
2173 1.90 thorpej ohci_free_std(sc, std);
2174 1.241 skrll }
2175 1.90 thorpej if (sed != NULL)
2176 1.90 thorpej ohci_free_sed(sc, sed);
2177 1.224 mrg return err;
2178 1.120 augustss
2179 1.1 augustss }
2180 1.1 augustss
2181 1.1 augustss /*
2182 1.34 augustss * Close a reqular pipe.
2183 1.34 augustss * Assumes that there are no pending transactions.
2184 1.34 augustss */
2185 1.34 augustss void
2186 1.254.2.19 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2187 1.34 augustss {
2188 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2189 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2190 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2191 1.34 augustss
2192 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2193 1.224 mrg
2194 1.34 augustss #ifdef DIAGNOSTIC
2195 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2196 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2197 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2198 1.34 augustss ohci_soft_td_t *std;
2199 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2200 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2201 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2202 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2203 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2204 1.34 augustss pipe, std);
2205 1.229 christos #ifdef OHCI_DEBUG
2206 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2207 1.168 augustss ohci_dump_ed(sc, sed);
2208 1.106 augustss if (std)
2209 1.168 augustss ohci_dump_td(sc, std);
2210 1.106 augustss #endif
2211 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2212 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2213 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2214 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2215 1.34 augustss }
2216 1.34 augustss #endif
2217 1.224 mrg ohci_rem_ed(sc, sed, head);
2218 1.133 toshii /* Make sure the host controller is not touching this ED */
2219 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2220 1.254.2.7 skrll pipe->up_endpoint->ue_toggle =
2221 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2222 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
2223 1.34 augustss }
2224 1.34 augustss
2225 1.120 augustss /*
2226 1.34 augustss * Abort a device request.
2227 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2228 1.34 augustss * will be removed from the hardware scheduling and that the callback
2229 1.34 augustss * for it will be called with USBD_CANCELLED status.
2230 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2231 1.34 augustss * have happened since the hardware runs concurrently.
2232 1.34 augustss * If the transaction has already happened we rely on the ordinary
2233 1.34 augustss * interrupt processing to process it.
2234 1.224 mrg * XXX This is most probably wrong.
2235 1.224 mrg * XXXMRG this doesn't make sense anymore.
2236 1.34 augustss */
2237 1.34 augustss void
2238 1.254.2.19 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2239 1.34 augustss {
2240 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2241 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2242 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2243 1.106 augustss ohci_soft_td_t *p, *n;
2244 1.106 augustss ohci_physaddr_t headp;
2245 1.224 mrg int hit;
2246 1.159 augustss int wake;
2247 1.34 augustss
2248 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2249 1.254.2.18 skrll DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0);
2250 1.34 augustss
2251 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2252 1.254.2.3 skrll ASSERT_SLEEPABLE();
2253 1.224 mrg
2254 1.116 augustss if (sc->sc_dying) {
2255 1.116 augustss /* If we're dying, just do the software part. */
2256 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2257 1.254.2.7 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2258 1.116 augustss usb_transfer_complete(xfer);
2259 1.170 christos return;
2260 1.116 augustss }
2261 1.116 augustss
2262 1.106 augustss /*
2263 1.159 augustss * If an abort is already in progress then just wait for it to
2264 1.159 augustss * complete and return.
2265 1.159 augustss */
2266 1.254.2.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2267 1.254.2.18 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2268 1.159 augustss #ifdef DIAGNOSTIC
2269 1.159 augustss if (status == USBD_TIMEOUT)
2270 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2271 1.159 augustss #endif
2272 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2273 1.254.2.7 skrll xfer->ux_status = status;
2274 1.254.2.18 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2275 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2276 1.254.2.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2277 1.254.2.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2278 1.224 mrg goto done;
2279 1.159 augustss }
2280 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2281 1.159 augustss
2282 1.159 augustss /*
2283 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2284 1.106 augustss */
2285 1.254.2.7 skrll xfer->ux_status = status; /* make software ignore it */
2286 1.254.2.7 skrll callout_stop(&xfer->ux_callout);
2287 1.254.2.18 skrll DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0);
2288 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2289 1.195 bouyer sizeof(sed->ed.ed_flags),
2290 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2291 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2292 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2293 1.195 bouyer sizeof(sed->ed.ed_flags),
2294 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2295 1.34 augustss
2296 1.120 augustss /*
2297 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2298 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2299 1.106 augustss * has run.
2300 1.106 augustss */
2301 1.224 mrg /* Hardware finishes in 1ms */
2302 1.254.2.7 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2303 1.119 augustss sc->sc_softwake = 1;
2304 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2305 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2306 1.119 augustss
2307 1.120 augustss /*
2308 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2309 1.106 augustss * The complication here is that the hardware may have executed
2310 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2311 1.106 augustss * the TDs of this xfer we check if the hardware points to
2312 1.106 augustss * any of them.
2313 1.106 augustss */
2314 1.254.2.7 skrll p = xfer->ux_hcpriv;
2315 1.254.2.24 skrll KASSERT(p);
2316 1.254.2.24 skrll
2317 1.106 augustss #ifdef OHCI_DEBUG
2318 1.254.2.18 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2319 1.254.2.18 skrll
2320 1.254.2.39 skrll if (ohcidebug >= 2) {
2321 1.254.2.18 skrll DPRINTF("sed:", 0, 0, 0, 0);
2322 1.168 augustss ohci_dump_ed(sc, sed);
2323 1.168 augustss ohci_dump_tds(sc, p);
2324 1.106 augustss }
2325 1.254.2.18 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2326 1.106 augustss #endif
2327 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2328 1.106 augustss hit = 0;
2329 1.53 augustss for (; p->xfer == xfer; p = n) {
2330 1.106 augustss hit |= headp == p->physaddr;
2331 1.38 augustss n = p->nexttd;
2332 1.254.2.35 skrll ohci_hash_rem_td(sc, p);
2333 1.34 augustss }
2334 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2335 1.106 augustss if (hit) {
2336 1.254.2.18 skrll DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr,
2337 1.254.2.18 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2338 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2339 1.195 bouyer usb_syncmem(&sed->dma,
2340 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2341 1.195 bouyer sizeof(sed->ed.ed_headp),
2342 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2343 1.106 augustss } else {
2344 1.254.2.18 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2345 1.106 augustss }
2346 1.34 augustss
2347 1.106 augustss /*
2348 1.106 augustss * Step 4: Turn on hardware again.
2349 1.106 augustss */
2350 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2351 1.195 bouyer sizeof(sed->ed.ed_flags),
2352 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2353 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2354 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2355 1.195 bouyer sizeof(sed->ed.ed_flags),
2356 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2357 1.38 augustss
2358 1.106 augustss /*
2359 1.106 augustss * Step 5: Execute callback.
2360 1.106 augustss */
2361 1.254.2.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2362 1.254.2.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2363 1.53 augustss usb_transfer_complete(xfer);
2364 1.159 augustss if (wake)
2365 1.254.2.7 skrll cv_broadcast(&xfer->ux_hccv);
2366 1.38 augustss
2367 1.224 mrg done:
2368 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2369 1.34 augustss }
2370 1.34 augustss
2371 1.34 augustss /*
2372 1.1 augustss * Data structures and routines to emulate the root hub.
2373 1.1 augustss */
2374 1.254.2.12 skrll Static int
2375 1.254.2.12 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2376 1.254.2.12 skrll void *buf, int buflen)
2377 1.17 augustss {
2378 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2379 1.1 augustss usb_port_status_t ps;
2380 1.254.2.12 skrll uint16_t len, value, index;
2381 1.254.2.12 skrll int l, totlen = 0;
2382 1.254.2.12 skrll int port, i;
2383 1.254.2.1 skrll uint32_t v;
2384 1.1 augustss
2385 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2386 1.254.2.18 skrll
2387 1.83 augustss if (sc->sc_dying)
2388 1.254.2.12 skrll return -1;
2389 1.1 augustss
2390 1.254.2.18 skrll DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType,
2391 1.254.2.18 skrll req->bRequest, 0, 0);
2392 1.1 augustss
2393 1.1 augustss len = UGETW(req->wLength);
2394 1.1 augustss value = UGETW(req->wValue);
2395 1.1 augustss index = UGETW(req->wIndex);
2396 1.43 augustss
2397 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2398 1.254.2.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
2399 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2400 1.254.2.18 skrll DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0);
2401 1.171 christos if (len == 0)
2402 1.171 christos break;
2403 1.254.2.12 skrll switch (value) {
2404 1.254.2.12 skrll case C(0, UDESC_DEVICE): {
2405 1.254.2.12 skrll usb_device_descriptor_t devd;
2406 1.254.2.12 skrll
2407 1.254.2.12 skrll totlen = min(buflen, sizeof(devd));
2408 1.254.2.12 skrll memcpy(&devd, buf, totlen);
2409 1.254.2.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2410 1.254.2.12 skrll memcpy(buf, &devd, totlen);
2411 1.1 augustss break;
2412 1.254.2.12 skrll }
2413 1.254.2.12 skrll case C(1, UDESC_STRING):
2414 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2415 1.254.2.12 skrll /* Vendor */
2416 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2417 1.254.2.12 skrll break;
2418 1.254.2.12 skrll case C(2, UDESC_STRING):
2419 1.254.2.12 skrll /* Product */
2420 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2421 1.1 augustss break;
2422 1.254.2.12 skrll #undef sd
2423 1.1 augustss default:
2424 1.254.2.12 skrll /* default from usbroothub */
2425 1.254.2.12 skrll return buflen;
2426 1.1 augustss }
2427 1.1 augustss break;
2428 1.254.2.12 skrll
2429 1.1 augustss /* Hub requests */
2430 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2431 1.1 augustss break;
2432 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2433 1.254.2.18 skrll DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2434 1.254.2.18 skrll index, value, 0, 0);
2435 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2436 1.254.2.12 skrll return -1;
2437 1.1 augustss }
2438 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2439 1.1 augustss switch(value) {
2440 1.1 augustss case UHF_PORT_ENABLE:
2441 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2442 1.1 augustss break;
2443 1.1 augustss case UHF_PORT_SUSPEND:
2444 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2445 1.1 augustss break;
2446 1.1 augustss case UHF_PORT_POWER:
2447 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2448 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2449 1.1 augustss break;
2450 1.1 augustss case UHF_C_PORT_CONNECTION:
2451 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2452 1.1 augustss break;
2453 1.1 augustss case UHF_C_PORT_ENABLE:
2454 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2455 1.1 augustss break;
2456 1.1 augustss case UHF_C_PORT_SUSPEND:
2457 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2458 1.1 augustss break;
2459 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2460 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2461 1.1 augustss break;
2462 1.1 augustss case UHF_C_PORT_RESET:
2463 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2464 1.1 augustss break;
2465 1.1 augustss default:
2466 1.254.2.12 skrll return -1;
2467 1.1 augustss }
2468 1.1 augustss switch(value) {
2469 1.1 augustss case UHF_C_PORT_CONNECTION:
2470 1.1 augustss case UHF_C_PORT_ENABLE:
2471 1.1 augustss case UHF_C_PORT_SUSPEND:
2472 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2473 1.1 augustss case UHF_C_PORT_RESET:
2474 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2475 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2476 1.157 mycroft ohci_rhsc_enable(sc);
2477 1.1 augustss break;
2478 1.1 augustss default:
2479 1.1 augustss break;
2480 1.1 augustss }
2481 1.1 augustss break;
2482 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2483 1.171 christos if (len == 0)
2484 1.171 christos break;
2485 1.146 toshii if ((value & 0xff) != 0) {
2486 1.254.2.12 skrll return -1;
2487 1.1 augustss }
2488 1.254.2.12 skrll usb_hub_descriptor_t hubd;
2489 1.254.2.12 skrll
2490 1.254.2.12 skrll totlen = min(buflen, sizeof(hubd));
2491 1.254.2.12 skrll memcpy(&hubd, buf, totlen);
2492 1.254.2.12 skrll
2493 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2494 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2495 1.15 augustss USETW(hubd.wHubCharacteristics,
2496 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2497 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2498 1.1 augustss /* XXX overcurrent */
2499 1.1 augustss );
2500 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2501 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2502 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2503 1.254.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2504 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2505 1.254.2.12 skrll totlen = min(totlen, hubd.bDescLength);
2506 1.254.2.12 skrll memcpy(buf, &hubd, totlen);
2507 1.1 augustss break;
2508 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2509 1.1 augustss if (len != 4) {
2510 1.254.2.12 skrll return -1;
2511 1.1 augustss }
2512 1.1 augustss memset(buf, 0, len); /* ? XXX */
2513 1.1 augustss totlen = len;
2514 1.1 augustss break;
2515 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2516 1.254.2.18 skrll DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
2517 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2518 1.254.2.12 skrll return -1;
2519 1.1 augustss }
2520 1.1 augustss if (len != 4) {
2521 1.254.2.12 skrll return -1;
2522 1.254.2.56 skrll }
2523 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2524 1.254.2.18 skrll DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0);
2525 1.1 augustss USETW(ps.wPortStatus, v);
2526 1.1 augustss USETW(ps.wPortChange, v >> 16);
2527 1.254.2.12 skrll totlen = min(len, sizeof(ps));
2528 1.254.2.12 skrll memcpy(buf, &ps, totlen);
2529 1.1 augustss break;
2530 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2531 1.254.2.12 skrll return -1;
2532 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2533 1.1 augustss break;
2534 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2535 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2536 1.254.2.12 skrll return -1;
2537 1.1 augustss }
2538 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2539 1.1 augustss switch(value) {
2540 1.1 augustss case UHF_PORT_ENABLE:
2541 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2542 1.1 augustss break;
2543 1.1 augustss case UHF_PORT_SUSPEND:
2544 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2545 1.1 augustss break;
2546 1.1 augustss case UHF_PORT_RESET:
2547 1.254.2.18 skrll DPRINTFN(5, "reset port %d", index, 0, 0, 0);
2548 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2549 1.110 augustss for (i = 0; i < 5; i++) {
2550 1.110 augustss usb_delay_ms(&sc->sc_bus,
2551 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2552 1.116 augustss if (sc->sc_dying) {
2553 1.254.2.12 skrll return -1;
2554 1.116 augustss }
2555 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2556 1.1 augustss break;
2557 1.1 augustss }
2558 1.254.2.18 skrll DPRINTFN(8, "port %d reset, status = 0x%04x", index,
2559 1.254.2.18 skrll OREAD4(sc, port), 0, 0);
2560 1.1 augustss break;
2561 1.1 augustss case UHF_PORT_POWER:
2562 1.254.2.18 skrll DPRINTFN(2, "set port power %d", index, 0, 0, 0);
2563 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2564 1.1 augustss break;
2565 1.1 augustss default:
2566 1.254.2.12 skrll return -1;
2567 1.1 augustss }
2568 1.1 augustss break;
2569 1.1 augustss default:
2570 1.254.2.12 skrll /* default from usbroothub */
2571 1.254.2.12 skrll return buflen;
2572 1.1 augustss }
2573 1.1 augustss
2574 1.254.2.12 skrll return totlen;
2575 1.1 augustss }
2576 1.1 augustss
2577 1.82 augustss Static usbd_status
2578 1.254.2.19 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2579 1.1 augustss {
2580 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2581 1.53 augustss usbd_status err;
2582 1.17 augustss
2583 1.46 augustss /* Insert last in queue. */
2584 1.224 mrg mutex_enter(&sc->sc_lock);
2585 1.53 augustss err = usb_insert_transfer(xfer);
2586 1.224 mrg mutex_exit(&sc->sc_lock);
2587 1.53 augustss if (err)
2588 1.254.2.13 skrll return err;
2589 1.46 augustss
2590 1.46 augustss /* Pipe isn't running, start first */
2591 1.254.2.13 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2592 1.17 augustss }
2593 1.17 augustss
2594 1.82 augustss Static usbd_status
2595 1.254.2.19 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2596 1.17 augustss {
2597 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2598 1.1 augustss
2599 1.83 augustss if (sc->sc_dying)
2600 1.254.2.13 skrll return USBD_IOERROR;
2601 1.83 augustss
2602 1.224 mrg mutex_enter(&sc->sc_lock);
2603 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2604 1.53 augustss sc->sc_intrxfer = xfer;
2605 1.224 mrg mutex_exit(&sc->sc_lock);
2606 1.1 augustss
2607 1.254.2.13 skrll return USBD_IN_PROGRESS;
2608 1.1 augustss }
2609 1.1 augustss
2610 1.3 augustss /* Abort a root interrupt request. */
2611 1.82 augustss Static void
2612 1.254.2.19 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2613 1.1 augustss {
2614 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2615 1.224 mrg
2616 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2617 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2618 1.53 augustss
2619 1.252 skrll sc->sc_intrxfer = NULL;
2620 1.252 skrll
2621 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
2622 1.53 augustss usb_transfer_complete(xfer);
2623 1.1 augustss }
2624 1.1 augustss
2625 1.1 augustss /* Close the root pipe. */
2626 1.82 augustss Static void
2627 1.254.2.19 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2628 1.1 augustss {
2629 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2630 1.120 augustss
2631 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2632 1.224 mrg
2633 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2634 1.34 augustss
2635 1.53 augustss sc->sc_intrxfer = NULL;
2636 1.1 augustss }
2637 1.1 augustss
2638 1.1 augustss /************************/
2639 1.1 augustss
2640 1.254.2.35 skrll int
2641 1.254.2.35 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2642 1.254.2.35 skrll {
2643 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2644 1.254.2.35 skrll usb_device_request_t *req = &xfer->ux_request;
2645 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2646 1.254.2.42 skrll ohci_soft_td_t *stat, *setup;
2647 1.254.2.35 skrll int isread = req->bmRequestType & UT_READ;
2648 1.254.2.35 skrll int len = xfer->ux_bufsize;
2649 1.254.2.35 skrll int err = ENOMEM;
2650 1.254.2.35 skrll
2651 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2652 1.254.2.35 skrll
2653 1.254.2.42 skrll setup = ohci_alloc_std(sc);
2654 1.254.2.42 skrll if (setup == NULL) {
2655 1.254.2.35 skrll goto bad1;
2656 1.254.2.35 skrll }
2657 1.254.2.42 skrll stat = ohci_alloc_std(sc);
2658 1.254.2.42 skrll if (stat == NULL) {
2659 1.254.2.35 skrll goto bad2;
2660 1.254.2.35 skrll }
2661 1.254.2.35 skrll
2662 1.254.2.42 skrll ox->ox_setup = setup;
2663 1.254.2.35 skrll ox->ox_stat = stat;
2664 1.254.2.35 skrll ox->ox_nstd = 0;
2665 1.254.2.35 skrll
2666 1.254.2.35 skrll /* Set up data transaction */
2667 1.254.2.35 skrll if (len != 0) {
2668 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2669 1.254.2.35 skrll if (err) {
2670 1.254.2.35 skrll goto bad3;
2671 1.254.2.35 skrll }
2672 1.254.2.35 skrll }
2673 1.254.2.35 skrll return 0;
2674 1.254.2.35 skrll
2675 1.254.2.35 skrll bad3:
2676 1.254.2.35 skrll ohci_free_std(sc, stat);
2677 1.254.2.42 skrll bad2:
2678 1.254.2.42 skrll ohci_free_std(sc, setup);
2679 1.254.2.35 skrll bad1:
2680 1.254.2.35 skrll return err;
2681 1.254.2.35 skrll }
2682 1.254.2.35 skrll
2683 1.254.2.35 skrll void
2684 1.254.2.35 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2685 1.254.2.35 skrll {
2686 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2687 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2688 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2689 1.254.2.35 skrll
2690 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2691 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2692 1.254.2.35 skrll
2693 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2694 1.254.2.42 skrll if (ox->ox_setup != opipe->tail.td) {
2695 1.254.2.42 skrll ohci_free_std_locked(sc, ox->ox_setup);
2696 1.254.2.35 skrll }
2697 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2698 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2699 1.254.2.35 skrll if (std == NULL)
2700 1.254.2.35 skrll break;
2701 1.254.2.35 skrll ohci_free_std_locked(sc, std);
2702 1.254.2.35 skrll }
2703 1.254.2.35 skrll ohci_free_std_locked(sc, ox->ox_stat);
2704 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
2705 1.254.2.35 skrll
2706 1.254.2.35 skrll if (ox->ox_nstd) {
2707 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2708 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
2709 1.254.2.35 skrll }
2710 1.254.2.35 skrll }
2711 1.254.2.35 skrll
2712 1.82 augustss Static usbd_status
2713 1.254.2.19 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2714 1.1 augustss {
2715 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2716 1.53 augustss usbd_status err;
2717 1.17 augustss
2718 1.46 augustss /* Insert last in queue. */
2719 1.224 mrg mutex_enter(&sc->sc_lock);
2720 1.53 augustss err = usb_insert_transfer(xfer);
2721 1.224 mrg mutex_exit(&sc->sc_lock);
2722 1.53 augustss if (err)
2723 1.254.2.13 skrll return err;
2724 1.46 augustss
2725 1.46 augustss /* Pipe isn't running, start first */
2726 1.254.2.13 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2727 1.17 augustss }
2728 1.17 augustss
2729 1.82 augustss Static usbd_status
2730 1.254.2.19 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2731 1.17 augustss {
2732 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2733 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2734 1.254.2.27 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2735 1.254.2.27 skrll usb_device_request_t *req = &xfer->ux_request;
2736 1.254.2.27 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2737 1.254.2.27 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2738 1.254.2.27 skrll ohci_soft_ed_t *sed;
2739 1.254.2.27 skrll int isread;
2740 1.254.2.27 skrll int len;
2741 1.254.2.27 skrll
2742 1.254.2.27 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2743 1.254.2.27 skrll
2744 1.83 augustss if (sc->sc_dying)
2745 1.254.2.13 skrll return USBD_IOERROR;
2746 1.83 augustss
2747 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2748 1.1 augustss
2749 1.254.2.27 skrll isread = req->bmRequestType & UT_READ;
2750 1.254.2.27 skrll len = UGETW(req->wLength);
2751 1.254.2.27 skrll
2752 1.254.2.40 skrll DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr,
2753 1.254.2.40 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2754 1.254.2.40 skrll DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x",
2755 1.254.2.27 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2756 1.254.2.27 skrll UGETW(req->wIndex));
2757 1.254.2.27 skrll
2758 1.254.2.35 skrll /* Need to take lock here for pipe->tail.td */
2759 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2760 1.254.2.35 skrll
2761 1.254.2.42 skrll /*
2762 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2763 1.254.2.42 skrll * next transfer
2764 1.254.2.42 skrll */
2765 1.254.2.27 skrll setup = opipe->tail.td;
2766 1.254.2.42 skrll opipe->tail.td = ox->ox_setup;
2767 1.254.2.42 skrll ox->ox_setup = setup;
2768 1.254.2.42 skrll
2769 1.254.2.35 skrll stat = ox->ox_stat;
2770 1.254.2.27 skrll
2771 1.254.2.50 skrll /* point at sentinel */
2772 1.254.2.50 skrll tail = opipe->tail.td;
2773 1.254.2.27 skrll sed = opipe->sed;
2774 1.254.2.27 skrll
2775 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2776 1.254.2.27 skrll "address ED %d pipe %d\n",
2777 1.254.2.27 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2778 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2779 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2780 1.254.2.27 skrll "MPL ED %d pipe %d\n",
2781 1.254.2.27 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2782 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2783 1.254.2.27 skrll
2784 1.254.2.35 skrll /* next will point to data if len != 0 */
2785 1.254.2.27 skrll next = stat;
2786 1.254.2.27 skrll
2787 1.254.2.27 skrll /* Set up data transaction */
2788 1.254.2.27 skrll if (len != 0) {
2789 1.254.2.35 skrll ohci_soft_td_t *std;
2790 1.254.2.35 skrll ohci_soft_td_t *end;
2791 1.254.2.27 skrll
2792 1.254.2.35 skrll next = ox->ox_stds[0];
2793 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2794 1.254.2.27 skrll
2795 1.254.2.35 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2796 1.254.2.35 skrll end->nexttd = stat;
2797 1.254.2.35 skrll
2798 1.254.2.35 skrll usb_syncmem(&end->dma,
2799 1.254.2.35 skrll end->offs + offsetof(ohci_td_t, td_nexttd),
2800 1.254.2.35 skrll sizeof(end->td.td_nexttd),
2801 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2802 1.254.2.35 skrll
2803 1.254.2.35 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2804 1.254.2.35 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2805 1.254.2.35 skrll std = ox->ox_stds[0];
2806 1.254.2.27 skrll /* Start toggle at 1 and then use the carried toggle. */
2807 1.254.2.27 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2808 1.254.2.27 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2809 1.254.2.27 skrll usb_syncmem(&std->dma,
2810 1.254.2.27 skrll std->offs + offsetof(ohci_td_t, td_flags),
2811 1.254.2.27 skrll sizeof(std->td.td_flags),
2812 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2813 1.254.2.27 skrll }
2814 1.254.2.27 skrll
2815 1.254.2.35 skrll DPRINTFN(8, "setup %p data %p stat %p tail %p", setup,
2816 1.254.2.35 skrll (len != 0 ? ox->ox_stds[0] : NULL), stat, tail);
2817 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
2818 1.254.2.35 skrll
2819 1.254.2.27 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2820 1.254.2.27 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2821 1.254.2.27 skrll
2822 1.254.2.27 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2823 1.254.2.27 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2824 1.254.2.27 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2825 1.254.2.27 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2826 1.254.2.27 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2827 1.254.2.33 skrll setup->nexttd = next;
2828 1.254.2.27 skrll setup->len = 0;
2829 1.254.2.27 skrll setup->xfer = xfer;
2830 1.254.2.27 skrll setup->flags = 0;
2831 1.254.2.35 skrll ohci_hash_add_td(sc, setup);
2832 1.254.2.35 skrll
2833 1.254.2.27 skrll xfer->ux_hcpriv = setup;
2834 1.254.2.27 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2835 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2836 1.254.2.27 skrll
2837 1.254.2.27 skrll stat->td.td_flags = HTOO32(
2838 1.254.2.27 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2839 1.254.2.27 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2840 1.254.2.27 skrll stat->td.td_cbp = 0;
2841 1.254.2.27 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2842 1.254.2.27 skrll stat->td.td_be = 0;
2843 1.254.2.33 skrll stat->nexttd = tail;
2844 1.254.2.27 skrll stat->flags = OHCI_CALL_DONE;
2845 1.254.2.27 skrll stat->len = 0;
2846 1.254.2.27 skrll stat->xfer = xfer;
2847 1.254.2.35 skrll ohci_hash_add_td(sc, stat);
2848 1.254.2.35 skrll
2849 1.254.2.27 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2850 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2851 1.254.2.27 skrll
2852 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
2853 1.254.2.35 skrll tail->nexttd = NULL;
2854 1.254.2.35 skrll tail->xfer = NULL;
2855 1.254.2.35 skrll
2856 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2857 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2858 1.254.2.35 skrll
2859 1.254.2.27 skrll #ifdef OHCI_DEBUG
2860 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2861 1.254.2.39 skrll if (ohcidebug >= 5) {
2862 1.254.2.27 skrll ohci_dump_ed(sc, sed);
2863 1.254.2.27 skrll ohci_dump_tds(sc, setup);
2864 1.254.2.27 skrll }
2865 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2866 1.254.2.27 skrll #endif
2867 1.254.2.27 skrll
2868 1.254.2.27 skrll /* Insert ED in schedule */
2869 1.254.2.27 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2870 1.254.2.27 skrll usb_syncmem(&sed->dma,
2871 1.254.2.27 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2872 1.254.2.27 skrll sizeof(sed->ed.ed_tailp),
2873 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2874 1.254.2.27 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2875 1.254.2.27 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2876 1.254.2.27 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2877 1.254.2.27 skrll ohci_timeout, xfer);
2878 1.254.2.27 skrll }
2879 1.254.2.27 skrll
2880 1.254.2.41 skrll DPRINTF("done", 0, 0, 0, 0);
2881 1.254.2.41 skrll
2882 1.224 mrg mutex_exit(&sc->sc_lock);
2883 1.1 augustss
2884 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling)
2885 1.53 augustss ohci_waitintr(sc, xfer);
2886 1.254.2.27 skrll
2887 1.254.2.13 skrll return USBD_IN_PROGRESS;
2888 1.1 augustss }
2889 1.1 augustss
2890 1.1 augustss /* Abort a device control request. */
2891 1.82 augustss Static void
2892 1.254.2.19 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2893 1.1 augustss {
2894 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2895 1.224 mrg
2896 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2897 1.224 mrg
2898 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2899 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2900 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2901 1.1 augustss }
2902 1.1 augustss
2903 1.1 augustss /* Close a device control pipe. */
2904 1.82 augustss Static void
2905 1.254.2.19 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2906 1.1 augustss {
2907 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2908 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2909 1.1 augustss
2910 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2911 1.224 mrg
2912 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2913 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2914 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2915 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
2916 1.3 augustss }
2917 1.3 augustss
2918 1.3 augustss /************************/
2919 1.37 augustss
2920 1.82 augustss Static void
2921 1.254.2.19 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2922 1.37 augustss {
2923 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2924 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2925 1.37 augustss
2926 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2927 1.37 augustss }
2928 1.37 augustss
2929 1.82 augustss Static void
2930 1.254.2.19 skrll ohci_noop(struct usbd_pipe *pipe)
2931 1.37 augustss {
2932 1.37 augustss }
2933 1.3 augustss
2934 1.254.2.35 skrll Static int
2935 1.254.2.35 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
2936 1.254.2.35 skrll {
2937 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2938 1.254.2.35 skrll int len = xfer->ux_bufsize;
2939 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
2940 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2941 1.254.2.35 skrll int err;
2942 1.254.2.35 skrll
2943 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2944 1.254.2.35 skrll
2945 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2946 1.254.2.35 skrll
2947 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
2948 1.254.2.35 skrll xfer->ux_flags);
2949 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
2950 1.254.2.35 skrll
2951 1.254.2.35 skrll /* Allocate a chain of new TDs (including a new tail). */
2952 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2953 1.254.2.35 skrll if (err)
2954 1.254.2.35 skrll return err;
2955 1.254.2.35 skrll
2956 1.254.2.35 skrll return 0;
2957 1.254.2.35 skrll }
2958 1.254.2.35 skrll
2959 1.254.2.35 skrll Static void
2960 1.254.2.35 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
2961 1.254.2.35 skrll {
2962 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2963 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2964 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2965 1.254.2.35 skrll
2966 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2967 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2968 1.254.2.35 skrll
2969 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2970 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2971 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2972 1.254.2.35 skrll if (std == NULL)
2973 1.254.2.35 skrll break;
2974 1.254.2.35 skrll if (std != opipe->tail.td)
2975 1.254.2.35 skrll ohci_free_std_locked(sc, std);
2976 1.254.2.35 skrll }
2977 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
2978 1.254.2.35 skrll
2979 1.254.2.35 skrll if (ox->ox_nstd) {
2980 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2981 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
2982 1.254.2.35 skrll }
2983 1.254.2.35 skrll }
2984 1.254.2.35 skrll
2985 1.82 augustss Static usbd_status
2986 1.254.2.19 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
2987 1.3 augustss {
2988 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2989 1.53 augustss usbd_status err;
2990 1.17 augustss
2991 1.46 augustss /* Insert last in queue. */
2992 1.224 mrg mutex_enter(&sc->sc_lock);
2993 1.53 augustss err = usb_insert_transfer(xfer);
2994 1.224 mrg mutex_exit(&sc->sc_lock);
2995 1.53 augustss if (err)
2996 1.254.2.13 skrll return err;
2997 1.46 augustss
2998 1.46 augustss /* Pipe isn't running, start first */
2999 1.254.2.13 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3000 1.17 augustss }
3001 1.17 augustss
3002 1.82 augustss Static usbd_status
3003 1.254.2.19 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
3004 1.17 augustss {
3005 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3006 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3007 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3008 1.254.2.35 skrll ohci_soft_td_t *last;
3009 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
3010 1.3 augustss ohci_soft_ed_t *sed;
3011 1.224 mrg int len, isread, endpt;
3012 1.3 augustss
3013 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3014 1.254.2.18 skrll
3015 1.83 augustss if (sc->sc_dying)
3016 1.254.2.13 skrll return USBD_IOERROR;
3017 1.83 augustss
3018 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3019 1.3 augustss
3020 1.254.2.7 skrll len = xfer->ux_length;
3021 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3022 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3023 1.3 augustss sed = opipe->sed;
3024 1.3 augustss
3025 1.254.2.18 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3026 1.254.2.18 skrll xfer->ux_flags);
3027 1.254.2.18 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3028 1.34 augustss
3029 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3030 1.3 augustss
3031 1.254.2.42 skrll /*
3032 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3033 1.254.2.42 skrll * next transfer
3034 1.254.2.42 skrll */
3035 1.60 augustss data = opipe->tail.td;
3036 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3037 1.254.2.35 skrll ox->ox_stds[0] = data;
3038 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3039 1.254.2.35 skrll
3040 1.254.2.50 skrll /* point at sentinel */
3041 1.254.2.50 skrll tail = opipe->tail.td;
3042 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3043 1.254.2.35 skrll tail->nexttd = NULL;
3044 1.254.2.35 skrll tail->xfer = NULL;
3045 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3046 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3047 1.254.2.35 skrll xfer->ux_hcpriv = data;
3048 1.254.2.35 skrll
3049 1.254.2.35 skrll DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0);
3050 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3051 1.254.2.1 skrll
3052 1.77 augustss /* We want interrupt at the end of the transfer. */
3053 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3054 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3055 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3056 1.254.2.35 skrll last->nexttd = tail;
3057 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3058 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3059 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3060 1.3 augustss
3061 1.254.2.18 skrll DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x "
3062 1.254.2.18 skrll "td_cbp=0x%08x td_be=0x%08x",
3063 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3064 1.168 augustss (int)O32TOH(data->td.td_flags),
3065 1.168 augustss (int)O32TOH(data->td.td_cbp),
3066 1.254.2.18 skrll (int)O32TOH(data->td.td_be));
3067 1.34 augustss
3068 1.52 augustss #ifdef OHCI_DEBUG
3069 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3070 1.254.2.39 skrll if (ohcidebug >= 5) {
3071 1.168 augustss ohci_dump_ed(sc, sed);
3072 1.168 augustss ohci_dump_tds(sc, data);
3073 1.34 augustss }
3074 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3075 1.34 augustss #endif
3076 1.34 augustss
3077 1.3 augustss /* Insert ED in schedule */
3078 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3079 1.254.2.35 skrll KASSERT(tdp->xfer == xfer);
3080 1.48 augustss }
3081 1.254.2.35 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3082 1.254.2.35 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3083 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3084 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3085 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3086 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3087 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3088 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3089 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3090 1.80 augustss ohci_timeout, xfer);
3091 1.15 augustss }
3092 1.224 mrg mutex_exit(&sc->sc_lock);
3093 1.34 augustss
3094 1.254.2.13 skrll return USBD_IN_PROGRESS;
3095 1.3 augustss }
3096 1.3 augustss
3097 1.82 augustss Static void
3098 1.254.2.19 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3099 1.3 augustss {
3100 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3101 1.254.2.25 skrll
3102 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3103 1.224 mrg
3104 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3105 1.224 mrg
3106 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
3107 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3108 1.3 augustss }
3109 1.3 augustss
3110 1.120 augustss /*
3111 1.34 augustss * Close a device bulk pipe.
3112 1.34 augustss */
3113 1.82 augustss Static void
3114 1.254.2.19 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3115 1.3 augustss {
3116 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3117 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3118 1.3 augustss
3119 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3120 1.224 mrg
3121 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3122 1.254.2.18 skrll
3123 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3124 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3125 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3126 1.1 augustss }
3127 1.1 augustss
3128 1.1 augustss /************************/
3129 1.1 augustss
3130 1.254.2.35 skrll Static int
3131 1.254.2.35 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3132 1.254.2.35 skrll {
3133 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3134 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3135 1.254.2.35 skrll int len = xfer->ux_bufsize;
3136 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3137 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3138 1.254.2.35 skrll int err;
3139 1.254.2.35 skrll
3140 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3141 1.254.2.35 skrll
3142 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3143 1.254.2.35 skrll KASSERT(len != 0);
3144 1.254.2.35 skrll
3145 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3146 1.254.2.35 skrll xfer->ux_flags);
3147 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3148 1.254.2.35 skrll
3149 1.254.2.35 skrll ox->ox_nstd = 0;
3150 1.254.2.35 skrll
3151 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3152 1.254.2.35 skrll if (err) {
3153 1.254.2.35 skrll return err;
3154 1.254.2.35 skrll }
3155 1.254.2.35 skrll
3156 1.254.2.35 skrll return 0;
3157 1.254.2.35 skrll }
3158 1.254.2.35 skrll
3159 1.254.2.35 skrll Static void
3160 1.254.2.35 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3161 1.254.2.35 skrll {
3162 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3163 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3164 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3165 1.254.2.35 skrll
3166 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3167 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3168 1.254.2.35 skrll
3169 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3170 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3171 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3172 1.254.2.35 skrll if (std != NULL)
3173 1.254.2.35 skrll break;
3174 1.254.2.35 skrll if (std != opipe->tail.td)
3175 1.254.2.35 skrll ohci_free_std_locked(sc, std);
3176 1.254.2.35 skrll }
3177 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3178 1.254.2.35 skrll
3179 1.254.2.35 skrll if (ox->ox_nstd) {
3180 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3181 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
3182 1.254.2.35 skrll }
3183 1.254.2.35 skrll }
3184 1.254.2.35 skrll
3185 1.82 augustss Static usbd_status
3186 1.254.2.19 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3187 1.17 augustss {
3188 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3189 1.53 augustss usbd_status err;
3190 1.17 augustss
3191 1.46 augustss /* Insert last in queue. */
3192 1.224 mrg mutex_enter(&sc->sc_lock);
3193 1.53 augustss err = usb_insert_transfer(xfer);
3194 1.224 mrg mutex_exit(&sc->sc_lock);
3195 1.53 augustss if (err)
3196 1.254.2.13 skrll return err;
3197 1.46 augustss
3198 1.46 augustss /* Pipe isn't running, start first */
3199 1.254.2.13 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3200 1.17 augustss }
3201 1.17 augustss
3202 1.82 augustss Static usbd_status
3203 1.254.2.19 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3204 1.1 augustss {
3205 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3206 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3207 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3208 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3209 1.254.2.35 skrll ohci_soft_td_t *data, *last, *tail;
3210 1.224 mrg int len, isread, endpt;
3211 1.1 augustss
3212 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3213 1.254.2.18 skrll
3214 1.83 augustss if (sc->sc_dying)
3215 1.254.2.13 skrll return USBD_IOERROR;
3216 1.83 augustss
3217 1.254.2.18 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length,
3218 1.254.2.18 skrll xfer->ux_flags, xfer->ux_priv);
3219 1.1 augustss
3220 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3221 1.1 augustss
3222 1.254.2.7 skrll len = xfer->ux_length;
3223 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3224 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3225 1.1 augustss
3226 1.224 mrg mutex_enter(&sc->sc_lock);
3227 1.254.2.35 skrll
3228 1.254.2.42 skrll /*
3229 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3230 1.254.2.42 skrll * next transfer.
3231 1.254.2.42 skrll */
3232 1.254.2.35 skrll data = opipe->tail.td;
3233 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3234 1.254.2.35 skrll ox->ox_stds[0] = data;
3235 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3236 1.254.2.35 skrll
3237 1.254.2.50 skrll /* point at sentinel */
3238 1.254.2.50 skrll tail = opipe->tail.td;
3239 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3240 1.254.2.35 skrll tail->nexttd = NULL;
3241 1.53 augustss tail->xfer = NULL;
3242 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3243 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3244 1.254.2.35 skrll xfer->ux_hcpriv = data;
3245 1.254.2.35 skrll
3246 1.254.2.35 skrll DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0);
3247 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3248 1.1 augustss
3249 1.254.2.35 skrll /* We want interrupt at the end of the transfer. */
3250 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3251 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3252 1.254.2.35 skrll
3253 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3254 1.254.2.35 skrll last->nexttd = tail;
3255 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3256 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3257 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3258 1.1 augustss
3259 1.52 augustss #ifdef OHCI_DEBUG
3260 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3261 1.254.2.39 skrll if (ohcidebug >= 5) {
3262 1.168 augustss ohci_dump_ed(sc, sed);
3263 1.168 augustss ohci_dump_tds(sc, data);
3264 1.1 augustss }
3265 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3266 1.1 augustss #endif
3267 1.1 augustss
3268 1.1 augustss /* Insert ED in schedule */
3269 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3270 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3271 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3272 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3273 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3274 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3275 1.1 augustss
3276 1.224 mrg mutex_exit(&sc->sc_lock);
3277 1.1 augustss
3278 1.254.2.13 skrll return USBD_IN_PROGRESS;
3279 1.1 augustss }
3280 1.1 augustss
3281 1.227 skrll /* Abort a device interrupt request. */
3282 1.82 augustss Static void
3283 1.254.2.19 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3284 1.1 augustss {
3285 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3286 1.224 mrg
3287 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3288 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3289 1.224 mrg
3290 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3291 1.1 augustss }
3292 1.1 augustss
3293 1.1 augustss /* Close a device interrupt pipe. */
3294 1.82 augustss Static void
3295 1.254.2.19 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3296 1.1 augustss {
3297 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3298 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3299 1.254.2.21 skrll int nslots = opipe->intr.nslots;
3300 1.254.2.21 skrll int pos = opipe->intr.pos;
3301 1.1 augustss int j;
3302 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3303 1.224 mrg
3304 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3305 1.254.2.18 skrll
3306 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3307 1.1 augustss
3308 1.254.2.18 skrll DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0);
3309 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3310 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3311 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3312 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3313 1.195 bouyer sizeof(sed->ed.ed_flags),
3314 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3315 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3316 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3317 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3318 1.1 augustss
3319 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3320 1.172 christos continue;
3321 1.254.2.24 skrll KASSERT(p);
3322 1.173 christos p->next = sed->next;
3323 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3324 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3325 1.195 bouyer sizeof(p->ed.ed_nexted),
3326 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3327 1.1 augustss
3328 1.1 augustss for (j = 0; j < nslots; j++)
3329 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3330 1.1 augustss
3331 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3332 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
3333 1.1 augustss }
3334 1.1 augustss
3335 1.82 augustss Static usbd_status
3336 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3337 1.1 augustss {
3338 1.224 mrg int i, j, best;
3339 1.1 augustss u_int npoll, slow, shigh, nslots;
3340 1.1 augustss u_int bestbw, bw;
3341 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3342 1.1 augustss
3343 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3344 1.254.2.18 skrll
3345 1.254.2.18 skrll DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0);
3346 1.1 augustss if (ival == 0) {
3347 1.1 augustss printf("ohci_setintr: 0 interval\n");
3348 1.254.2.13 skrll return USBD_INVAL;
3349 1.1 augustss }
3350 1.1 augustss
3351 1.1 augustss npoll = OHCI_NO_INTRS;
3352 1.1 augustss while (npoll > ival)
3353 1.1 augustss npoll /= 2;
3354 1.254.2.18 skrll DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0);
3355 1.1 augustss
3356 1.1 augustss /*
3357 1.1 augustss * We now know which level in the tree the ED must go into.
3358 1.1 augustss * Figure out which slot has most bandwidth left over.
3359 1.1 augustss * Slots to examine:
3360 1.1 augustss * npoll
3361 1.1 augustss * 1 0
3362 1.1 augustss * 2 1 2
3363 1.1 augustss * 4 3 4 5 6
3364 1.1 augustss * 8 7 8 9 10 11 12 13 14
3365 1.1 augustss * N (N-1) .. (N-1+N-1)
3366 1.1 augustss */
3367 1.1 augustss slow = npoll-1;
3368 1.1 augustss shigh = slow + npoll;
3369 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3370 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3371 1.1 augustss bw = 0;
3372 1.1 augustss for (j = 0; j < nslots; j++)
3373 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3374 1.1 augustss if (bw < bestbw) {
3375 1.1 augustss best = i;
3376 1.1 augustss bestbw = bw;
3377 1.1 augustss }
3378 1.1 augustss }
3379 1.254.2.18 skrll DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw);
3380 1.1 augustss
3381 1.224 mrg mutex_enter(&sc->sc_lock);
3382 1.1 augustss hsed = sc->sc_eds[best];
3383 1.1 augustss sed->next = hsed->next;
3384 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3385 1.195 bouyer sizeof(hsed->ed.ed_flags),
3386 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3387 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3388 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3389 1.195 bouyer sizeof(sed->ed.ed_flags),
3390 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3391 1.1 augustss hsed->next = sed;
3392 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3393 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3394 1.195 bouyer sizeof(hsed->ed.ed_flags),
3395 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3396 1.224 mrg mutex_exit(&sc->sc_lock);
3397 1.1 augustss
3398 1.1 augustss for (j = 0; j < nslots; j++)
3399 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3400 1.254.2.21 skrll opipe->intr.nslots = nslots;
3401 1.254.2.21 skrll opipe->intr.pos = best;
3402 1.1 augustss
3403 1.254.2.18 skrll DPRINTFN(5, "returns %p", opipe, 0, 0, 0);
3404 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3405 1.60 augustss }
3406 1.60 augustss
3407 1.60 augustss /***********************/
3408 1.60 augustss
3409 1.254.2.35 skrll Static int
3410 1.254.2.35 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3411 1.254.2.35 skrll {
3412 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3413 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3414 1.254.2.35 skrll ohci_soft_itd_t *sitd;
3415 1.254.2.35 skrll size_t i;
3416 1.254.2.35 skrll int err;
3417 1.254.2.35 skrll
3418 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3419 1.254.2.35 skrll
3420 1.254.2.35 skrll DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length,
3421 1.254.2.35 skrll xfer->ux_flags, 0);
3422 1.254.2.35 skrll
3423 1.254.2.35 skrll const size_t nfsitd =
3424 1.254.2.35 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3425 1.254.2.35 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3426 1.254.2.35 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3427 1.254.2.35 skrll
3428 1.254.2.35 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3429 1.254.2.35 skrll KM_SLEEP);
3430 1.254.2.35 skrll ox->ox_nsitd = nsitd;
3431 1.254.2.35 skrll
3432 1.254.2.35 skrll for (i = 0; i < nsitd; i++) {
3433 1.254.2.35 skrll /* Allocate next ITD */
3434 1.254.2.35 skrll sitd = ohci_alloc_sitd(sc);
3435 1.254.2.35 skrll if (sitd == NULL) {
3436 1.254.2.35 skrll err = ENOMEM;
3437 1.254.2.35 skrll goto fail;
3438 1.254.2.35 skrll }
3439 1.254.2.35 skrll ox->ox_sitds[i] = sitd;
3440 1.254.2.35 skrll sitd->xfer = xfer;
3441 1.254.2.35 skrll sitd->flags = 0;
3442 1.254.2.35 skrll }
3443 1.254.2.35 skrll
3444 1.254.2.35 skrll return 0;
3445 1.254.2.35 skrll fail:
3446 1.254.2.35 skrll for (; i > 0;) {
3447 1.254.2.35 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3448 1.254.2.35 skrll }
3449 1.254.2.35 skrll return err;
3450 1.254.2.35 skrll }
3451 1.254.2.35 skrll
3452 1.254.2.35 skrll Static void
3453 1.254.2.35 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3454 1.254.2.35 skrll {
3455 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3456 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3457 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3458 1.254.2.35 skrll
3459 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3460 1.254.2.35 skrll
3461 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3462 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3463 1.254.2.35 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3464 1.254.2.35 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3465 1.254.2.35 skrll }
3466 1.254.2.35 skrll }
3467 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3468 1.254.2.35 skrll
3469 1.254.2.35 skrll if (ox->ox_nsitd) {
3470 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3471 1.254.2.35 skrll kmem_free(ox->ox_sitds, sz);
3472 1.254.2.35 skrll }
3473 1.254.2.35 skrll }
3474 1.254.2.35 skrll
3475 1.254.2.35 skrll
3476 1.60 augustss usbd_status
3477 1.254.2.19 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3478 1.60 augustss {
3479 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3480 1.254.2.59 skrll usbd_status __diagused err;
3481 1.60 augustss
3482 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3483 1.254.2.18 skrll
3484 1.254.2.18 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3485 1.60 augustss
3486 1.60 augustss /* Put it on our queue, */
3487 1.224 mrg mutex_enter(&sc->sc_lock);
3488 1.60 augustss err = usb_insert_transfer(xfer);
3489 1.224 mrg mutex_exit(&sc->sc_lock);
3490 1.60 augustss
3491 1.254.2.59 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3492 1.60 augustss
3493 1.60 augustss /* insert into schedule, */
3494 1.60 augustss ohci_device_isoc_enter(xfer);
3495 1.60 augustss
3496 1.83 augustss /* and start if the pipe wasn't running */
3497 1.254.2.59 skrll return USBD_IN_PROGRESS;
3498 1.60 augustss }
3499 1.60 augustss
3500 1.60 augustss void
3501 1.254.2.19 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3502 1.60 augustss {
3503 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3504 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3505 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3506 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3507 1.254.2.53 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3508 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3509 1.61 augustss int i, ncur, nframes;
3510 1.61 augustss
3511 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3512 1.254.2.53 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3513 1.254.2.18 skrll
3514 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3515 1.83 augustss
3516 1.254.2.35 skrll if (sc->sc_dying) {
3517 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3518 1.83 augustss return;
3519 1.254.2.35 skrll }
3520 1.254.2.35 skrll
3521 1.254.2.35 skrll struct isoc *isoc = &opipe->isoc;
3522 1.254.2.35 skrll
3523 1.254.2.35 skrll DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d",
3524 1.254.2.35 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3525 1.83 augustss
3526 1.254.2.21 skrll if (isoc->next == -1) {
3527 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3528 1.254.2.21 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3529 1.254.2.21 skrll DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0);
3530 1.83 augustss }
3531 1.83 augustss
3532 1.61 augustss sitd = opipe->tail.itd;
3533 1.254.2.35 skrll opipe->tail.itd = ox->ox_sitds[0];
3534 1.254.2.35 skrll ox->ox_sitds[0] = sitd;
3535 1.254.2.35 skrll
3536 1.254.2.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3537 1.83 augustss bp0 = OHCI_PAGE(buf);
3538 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3539 1.254.2.7 skrll nframes = xfer->ux_nframes;
3540 1.254.2.7 skrll xfer->ux_hcpriv = sitd;
3541 1.254.2.35 skrll size_t j = 1;
3542 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3543 1.254.2.7 skrll noffs = offs + xfer->ux_frlengths[i];
3544 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3545 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3546 1.120 augustss
3547 1.83 augustss /* Allocate next ITD */
3548 1.254.2.35 skrll nsitd = ox->ox_sitds[j++];
3549 1.254.2.35 skrll KASSERT(nsitd != NULL);
3550 1.254.2.35 skrll KASSERT(j < ox->ox_nsitd);
3551 1.83 augustss
3552 1.83 augustss /* Fill current ITD */
3553 1.168 augustss sitd->itd.itd_flags = HTOO32(
3554 1.120 augustss OHCI_ITD_NOCC |
3555 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3556 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3557 1.83 augustss OHCI_ITD_SET_FC(ncur));
3558 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3559 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3560 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3561 1.254.2.33 skrll sitd->nextitd = nsitd;
3562 1.83 augustss sitd->xfer = xfer;
3563 1.83 augustss sitd->flags = 0;
3564 1.254.2.35 skrll #ifdef DIAGNOSTIC
3565 1.254.2.35 skrll sitd->isdone = false;
3566 1.254.2.35 skrll #endif
3567 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3568 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3569 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3570 1.83 augustss
3571 1.61 augustss sitd = nsitd;
3572 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3573 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3574 1.61 augustss ncur = 0;
3575 1.61 augustss }
3576 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3577 1.83 augustss offs = noffs;
3578 1.61 augustss }
3579 1.254.2.35 skrll KASSERT(j <= ox->ox_nsitd);
3580 1.254.2.35 skrll
3581 1.254.2.53 skrll /* point at sentinel */
3582 1.254.2.53 skrll tail = opipe->tail.itd;
3583 1.254.2.53 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3584 1.254.2.53 skrll tail->nextitd = NULL;
3585 1.254.2.53 skrll tail->xfer = NULL;
3586 1.254.2.53 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3587 1.254.2.53 skrll BUS_DMASYNC_PREWRITE);
3588 1.254.2.53 skrll
3589 1.83 augustss /* Fixup last used ITD */
3590 1.168 augustss sitd->itd.itd_flags = HTOO32(
3591 1.120 augustss OHCI_ITD_NOCC |
3592 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3593 1.61 augustss OHCI_ITD_SET_DI(0) |
3594 1.61 augustss OHCI_ITD_SET_FC(ncur));
3595 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3596 1.254.2.53 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3597 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3598 1.254.2.53 skrll sitd->nextitd = tail;
3599 1.83 augustss sitd->xfer = xfer;
3600 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3601 1.254.2.35 skrll #ifdef DIAGNOSTIC
3602 1.254.2.35 skrll sitd->isdone = false;
3603 1.254.2.35 skrll #endif
3604 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3605 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3606 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3607 1.83 augustss
3608 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3609 1.254.2.21 skrll isoc->inuse += nframes;
3610 1.83 augustss
3611 1.254.2.48 skrll /* XXX pretend we did it all */
3612 1.254.2.48 skrll xfer->ux_actlen = offs;
3613 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3614 1.83 augustss
3615 1.83 augustss #ifdef OHCI_DEBUG
3616 1.254.2.39 skrll if (ohcidebug >= 5) {
3617 1.254.2.18 skrll DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3618 1.254.2.18 skrll 0, 0, 0);
3619 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3620 1.168 augustss ohci_dump_ed(sc, sed);
3621 1.83 augustss }
3622 1.83 augustss #endif
3623 1.61 augustss
3624 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3625 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3626 1.254.2.53 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3627 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3628 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3629 1.195 bouyer sizeof(sed->ed.ed_flags),
3630 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3631 1.224 mrg mutex_exit(&sc->sc_lock);
3632 1.60 augustss }
3633 1.60 augustss
3634 1.60 augustss void
3635 1.254.2.19 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3636 1.60 augustss {
3637 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3638 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3639 1.83 augustss ohci_soft_ed_t *sed;
3640 1.83 augustss ohci_soft_itd_t *sitd;
3641 1.83 augustss
3642 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3643 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3644 1.83 augustss
3645 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3646 1.83 augustss
3647 1.83 augustss /* Transfer is already done. */
3648 1.254.2.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3649 1.254.2.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3650 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3651 1.224 mrg goto done;
3652 1.83 augustss }
3653 1.83 augustss
3654 1.83 augustss /* Give xfer the requested abort code. */
3655 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
3656 1.83 augustss
3657 1.83 augustss sed = opipe->sed;
3658 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3659 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3660 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3661 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3662 1.195 bouyer sizeof(sed->ed.ed_flags),
3663 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3664 1.83 augustss
3665 1.254.2.7 skrll sitd = xfer->ux_hcpriv;
3666 1.254.2.24 skrll KASSERT(sitd);
3667 1.254.2.24 skrll
3668 1.254.2.60 skrll usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3669 1.254.2.60 skrll
3670 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3671 1.254.2.55 skrll ohci_hash_rem_itd(sc, sitd);
3672 1.83 augustss #ifdef DIAGNOSTIC
3673 1.254.2.18 skrll DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0);
3674 1.254.2.31 skrll sitd->isdone = true;
3675 1.83 augustss #endif
3676 1.83 augustss }
3677 1.83 augustss
3678 1.83 augustss /* Run callback. */
3679 1.83 augustss usb_transfer_complete(xfer);
3680 1.83 augustss
3681 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3682 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3683 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3684 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3685 1.83 augustss
3686 1.224 mrg done:
3687 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3688 1.60 augustss }
3689 1.60 augustss
3690 1.60 augustss void
3691 1.254.2.19 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3692 1.60 augustss {
3693 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3694 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3695 1.60 augustss }
3696 1.60 augustss
3697 1.60 augustss usbd_status
3698 1.254.2.19 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3699 1.60 augustss {
3700 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3701 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3702 1.254.2.21 skrll struct isoc *isoc = &opipe->isoc;
3703 1.60 augustss
3704 1.254.2.21 skrll isoc->next = -1;
3705 1.254.2.21 skrll isoc->inuse = 0;
3706 1.60 augustss
3707 1.224 mrg mutex_enter(&sc->sc_lock);
3708 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3709 1.224 mrg mutex_exit(&sc->sc_lock);
3710 1.83 augustss
3711 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3712 1.60 augustss }
3713 1.60 augustss
3714 1.60 augustss void
3715 1.254.2.19 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3716 1.60 augustss {
3717 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3718 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3719 1.60 augustss
3720 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3721 1.224 mrg
3722 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3723 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3724 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3725 1.83 augustss #ifdef DIAGNOSTIC
3726 1.254.2.31 skrll opipe->tail.itd->isdone = true;
3727 1.83 augustss #endif
3728 1.254.2.35 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3729 1.1 augustss }
3730