ohci.c revision 1.254.2.85 1 1.254.2.85 skrll /* $NetBSD: ohci.c,v 1.254.2.85 2017/01/31 07:25:34 skrll Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.254.2.85 skrll __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.85 2017/01/31 07:25:34 skrll Exp $");
45 1.254.2.18 skrll
46 1.254.2.75 skrll #ifdef _KERNEL_OPT
47 1.254.2.18 skrll #include "opt_usb.h"
48 1.254.2.75 skrll #endif
49 1.1 augustss
50 1.1 augustss #include <sys/param.h>
51 1.254.2.17 skrll
52 1.254.2.17 skrll #include <sys/cpu.h>
53 1.1 augustss #include <sys/device.h>
54 1.254.2.17 skrll #include <sys/kernel.h>
55 1.254.2.17 skrll #include <sys/kmem.h>
56 1.1 augustss #include <sys/proc.h>
57 1.1 augustss #include <sys/queue.h>
58 1.254.2.17 skrll #include <sys/select.h>
59 1.254.2.18 skrll #include <sys/sysctl.h>
60 1.254.2.17 skrll #include <sys/systm.h>
61 1.1 augustss
62 1.16 augustss #include <machine/endian.h>
63 1.4 augustss
64 1.1 augustss #include <dev/usb/usb.h>
65 1.1 augustss #include <dev/usb/usbdi.h>
66 1.1 augustss #include <dev/usb/usbdivar.h>
67 1.38 augustss #include <dev/usb/usb_mem.h>
68 1.1 augustss #include <dev/usb/usb_quirks.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/ohcireg.h>
71 1.1 augustss #include <dev/usb/ohcivar.h>
72 1.254.2.11 skrll #include <dev/usb/usbroothub.h>
73 1.254.2.18 skrll #include <dev/usb/usbhist.h>
74 1.1 augustss
75 1.254.2.18 skrll #ifdef USB_DEBUG
76 1.254.2.18 skrll #ifndef OHCI_DEBUG
77 1.254.2.18 skrll #define ohcidebug 0
78 1.254.2.18 skrll #else
79 1.254.2.59 skrll static int ohcidebug = 10;
80 1.1 augustss
81 1.254.2.18 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
82 1.254.2.18 skrll {
83 1.254.2.18 skrll int err;
84 1.254.2.18 skrll const struct sysctlnode *rnode;
85 1.254.2.18 skrll const struct sysctlnode *cnode;
86 1.254.2.18 skrll
87 1.254.2.18 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
88 1.254.2.18 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
89 1.254.2.18 skrll SYSCTL_DESCR("ohci global controls"),
90 1.254.2.18 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
91 1.36 augustss
92 1.254.2.18 skrll if (err)
93 1.254.2.18 skrll goto fail;
94 1.254.2.18 skrll
95 1.254.2.18 skrll /* control debugging printfs */
96 1.254.2.18 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
97 1.254.2.18 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
98 1.254.2.18 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
99 1.254.2.18 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
100 1.254.2.18 skrll if (err)
101 1.254.2.18 skrll goto fail;
102 1.254.2.18 skrll
103 1.254.2.18 skrll return;
104 1.254.2.18 skrll fail:
105 1.254.2.18 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
106 1.254.2.18 skrll }
107 1.254.2.18 skrll
108 1.254.2.18 skrll #endif /* OHCI_DEBUG */
109 1.254.2.18 skrll #endif /* USB_DEBUG */
110 1.254.2.18 skrll
111 1.254.2.18 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
112 1.254.2.18 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
113 1.254.2.18 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
114 1.254.2.18 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
115 1.52 augustss
116 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
117 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
118 1.16 augustss #else
119 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
120 1.16 augustss #endif
121 1.16 augustss
122 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
123 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
124 1.169 tron #define HTOO16(val) O16TOH(val)
125 1.169 tron #define HTOO32(val) O32TOH(val)
126 1.168 augustss
127 1.1 augustss struct ohci_pipe;
128 1.1 augustss
129 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
130 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
131 1.1 augustss
132 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
133 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
134 1.254.2.35 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
135 1.1 augustss
136 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
137 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
138 1.254.2.35 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
139 1.254.2.35 skrll ohci_soft_itd_t *);
140 1.60 augustss
141 1.254.2.72 skrll Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
142 1.254.2.35 skrll int, int);
143 1.254.2.35 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
144 1.254.2.35 skrll
145 1.254.2.35 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
146 1.254.2.35 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
147 1.53 augustss
148 1.254.2.19 skrll Static usbd_status ohci_open(struct usbd_pipe *);
149 1.91 augustss Static void ohci_poll(struct usbd_bus *);
150 1.99 augustss Static void ohci_softintr(void *);
151 1.254.2.19 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
152 1.254.2.15 skrll Static void ohci_rhsc_softint(void *);
153 1.91 augustss
154 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
155 1.168 augustss ohci_soft_ed_t *);
156 1.168 augustss
157 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
158 1.224 mrg ohci_soft_ed_t *);
159 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
161 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
162 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
164 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
165 1.91 augustss
166 1.254.2.19 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
167 1.254.2.19 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
168 1.91 augustss
169 1.254.2.23 skrll Static struct usbd_xfer *
170 1.254.2.23 skrll ohci_allocx(struct usbd_bus *, unsigned int);
171 1.254.2.19 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
172 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
173 1.254.2.13 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
174 1.254.2.26 skrll usb_device_request_t *, void *, int);
175 1.91 augustss
176 1.254.2.19 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
177 1.254.2.19 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
178 1.254.2.19 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
179 1.254.2.19 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
180 1.254.2.19 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
181 1.254.2.19 skrll
182 1.254.2.35 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
183 1.254.2.35 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
184 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
185 1.254.2.19 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
186 1.254.2.19 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
187 1.254.2.19 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
188 1.254.2.19 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
189 1.254.2.19 skrll
190 1.254.2.35 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
191 1.254.2.35 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
192 1.254.2.19 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
193 1.254.2.19 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
194 1.254.2.19 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
195 1.254.2.19 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
196 1.254.2.19 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
197 1.254.2.19 skrll
198 1.254.2.35 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
199 1.254.2.35 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
200 1.254.2.19 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
201 1.254.2.19 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
202 1.254.2.19 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
203 1.254.2.19 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
204 1.254.2.19 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
205 1.254.2.19 skrll
206 1.254.2.35 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
207 1.254.2.35 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
208 1.254.2.19 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
209 1.254.2.19 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
210 1.254.2.19 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
211 1.254.2.19 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
212 1.91 augustss
213 1.254.2.15 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
214 1.254.2.15 skrll struct ohci_pipe *, int);
215 1.91 augustss
216 1.91 augustss Static void ohci_timeout(void *);
217 1.114 augustss Static void ohci_timeout_task(void *);
218 1.104 augustss Static void ohci_rhsc_enable(void *);
219 1.91 augustss
220 1.254.2.19 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
221 1.254.2.19 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
222 1.53 augustss
223 1.254.2.19 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
224 1.254.2.19 skrll Static void ohci_noop(struct usbd_pipe *);
225 1.37 augustss
226 1.52 augustss #ifdef OHCI_DEBUG
227 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
228 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
230 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
231 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
232 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
233 1.1 augustss #endif
234 1.1 augustss
235 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
236 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
237 1.88 augustss #define OWRITE1(sc, r, x) \
238 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
239 1.88 augustss #define OWRITE2(sc, r, x) \
240 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
241 1.88 augustss #define OWRITE4(sc, r, x) \
242 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
243 1.174 mrg
244 1.174 mrg static __inline uint32_t
245 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
246 1.174 mrg {
247 1.174 mrg
248 1.174 mrg OBARR(sc);
249 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
250 1.174 mrg }
251 1.1 augustss
252 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
253 1.254.2.1 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
254 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
255 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
256 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
257 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
258 1.1 augustss
259 1.1 augustss struct ohci_pipe {
260 1.1 augustss struct usbd_pipe pipe;
261 1.1 augustss ohci_soft_ed_t *sed;
262 1.60 augustss union {
263 1.60 augustss ohci_soft_td_t *td;
264 1.60 augustss ohci_soft_itd_t *itd;
265 1.60 augustss } tail;
266 1.1 augustss /* Info needed for different pipe kinds. */
267 1.1 augustss union {
268 1.1 augustss /* Control pipe */
269 1.1 augustss struct {
270 1.4 augustss usb_dma_t reqdma;
271 1.254.2.21 skrll } ctrl;
272 1.1 augustss /* Interrupt pipe */
273 1.1 augustss struct {
274 1.1 augustss int nslots;
275 1.1 augustss int pos;
276 1.1 augustss } intr;
277 1.254.2.21 skrll /* Isochronous pipe */
278 1.254.2.21 skrll struct isoc {
279 1.60 augustss int next, inuse;
280 1.254.2.21 skrll } isoc;
281 1.254.2.21 skrll };
282 1.1 augustss };
283 1.1 augustss
284 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
285 1.254.2.5 skrll .ubm_open = ohci_open,
286 1.254.2.5 skrll .ubm_softint = ohci_softintr,
287 1.254.2.5 skrll .ubm_dopoll = ohci_poll,
288 1.254.2.5 skrll .ubm_allocx = ohci_allocx,
289 1.254.2.5 skrll .ubm_freex = ohci_freex,
290 1.254.2.5 skrll .ubm_getlock = ohci_get_lock,
291 1.254.2.12 skrll .ubm_rhctrl = ohci_roothub_ctrl,
292 1.1 augustss };
293 1.1 augustss
294 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
295 1.254.2.5 skrll .upm_transfer = ohci_root_intr_transfer,
296 1.254.2.5 skrll .upm_start = ohci_root_intr_start,
297 1.254.2.5 skrll .upm_abort = ohci_root_intr_abort,
298 1.254.2.5 skrll .upm_close = ohci_root_intr_close,
299 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
300 1.254.2.5 skrll .upm_done = ohci_root_intr_done,
301 1.1 augustss };
302 1.1 augustss
303 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
304 1.254.2.35 skrll .upm_init = ohci_device_ctrl_init,
305 1.254.2.35 skrll .upm_fini = ohci_device_ctrl_fini,
306 1.254.2.5 skrll .upm_transfer = ohci_device_ctrl_transfer,
307 1.254.2.5 skrll .upm_start = ohci_device_ctrl_start,
308 1.254.2.5 skrll .upm_abort = ohci_device_ctrl_abort,
309 1.254.2.5 skrll .upm_close = ohci_device_ctrl_close,
310 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
311 1.254.2.5 skrll .upm_done = ohci_device_ctrl_done,
312 1.1 augustss };
313 1.1 augustss
314 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
315 1.254.2.35 skrll .upm_init = ohci_device_intr_init,
316 1.254.2.35 skrll .upm_fini = ohci_device_intr_fini,
317 1.254.2.5 skrll .upm_transfer = ohci_device_intr_transfer,
318 1.254.2.5 skrll .upm_start = ohci_device_intr_start,
319 1.254.2.5 skrll .upm_abort = ohci_device_intr_abort,
320 1.254.2.5 skrll .upm_close = ohci_device_intr_close,
321 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
322 1.254.2.5 skrll .upm_done = ohci_device_intr_done,
323 1.1 augustss };
324 1.1 augustss
325 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
326 1.254.2.35 skrll .upm_init = ohci_device_bulk_init,
327 1.254.2.35 skrll .upm_fini = ohci_device_bulk_fini,
328 1.254.2.5 skrll .upm_transfer = ohci_device_bulk_transfer,
329 1.254.2.5 skrll .upm_start = ohci_device_bulk_start,
330 1.254.2.5 skrll .upm_abort = ohci_device_bulk_abort,
331 1.254.2.5 skrll .upm_close = ohci_device_bulk_close,
332 1.254.2.5 skrll .upm_cleartoggle = ohci_device_clear_toggle,
333 1.254.2.5 skrll .upm_done = ohci_device_bulk_done,
334 1.3 augustss };
335 1.3 augustss
336 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
337 1.254.2.35 skrll .upm_init = ohci_device_isoc_init,
338 1.254.2.35 skrll .upm_fini = ohci_device_isoc_fini,
339 1.254.2.5 skrll .upm_transfer = ohci_device_isoc_transfer,
340 1.254.2.5 skrll .upm_abort = ohci_device_isoc_abort,
341 1.254.2.5 skrll .upm_close = ohci_device_isoc_close,
342 1.254.2.5 skrll .upm_cleartoggle = ohci_noop,
343 1.254.2.5 skrll .upm_done = ohci_device_isoc_done,
344 1.43 augustss };
345 1.43 augustss
346 1.47 augustss int
347 1.189 dyoung ohci_activate(device_t self, enum devact act)
348 1.47 augustss {
349 1.189 dyoung struct ohci_softc *sc = device_private(self);
350 1.47 augustss
351 1.47 augustss switch (act) {
352 1.47 augustss case DVACT_DEACTIVATE:
353 1.183 kiyohara sc->sc_dying = 1;
354 1.203 dyoung return 0;
355 1.203 dyoung default:
356 1.203 dyoung return EOPNOTSUPP;
357 1.47 augustss }
358 1.47 augustss }
359 1.47 augustss
360 1.187 dyoung void
361 1.187 dyoung ohci_childdet(device_t self, device_t child)
362 1.187 dyoung {
363 1.187 dyoung struct ohci_softc *sc = device_private(self);
364 1.187 dyoung
365 1.187 dyoung KASSERT(sc->sc_child == child);
366 1.187 dyoung sc->sc_child = NULL;
367 1.187 dyoung }
368 1.187 dyoung
369 1.47 augustss int
370 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
371 1.47 augustss {
372 1.47 augustss int rv = 0;
373 1.47 augustss
374 1.47 augustss if (sc->sc_child != NULL)
375 1.47 augustss rv = config_detach(sc->sc_child, flags);
376 1.120 augustss
377 1.47 augustss if (rv != 0)
378 1.254.2.13 skrll return rv;
379 1.47 augustss
380 1.254 ozaki callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock);
381 1.104 augustss
382 1.116 augustss usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
383 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
384 1.116 augustss
385 1.224 mrg softint_disestablish(sc->sc_rhsc_si);
386 1.224 mrg
387 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
388 1.224 mrg
389 1.224 mrg mutex_destroy(&sc->sc_lock);
390 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
391 1.224 mrg
392 1.198 cegger if (sc->sc_hcca != NULL)
393 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
394 1.232 christos pool_cache_destroy(sc->sc_xferpool);
395 1.47 augustss
396 1.254.2.13 skrll return rv;
397 1.47 augustss }
398 1.47 augustss
399 1.1 augustss ohci_soft_ed_t *
400 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
401 1.1 augustss {
402 1.1 augustss ohci_soft_ed_t *sed;
403 1.53 augustss usbd_status err;
404 1.1 augustss int i, offs;
405 1.4 augustss usb_dma_t dma;
406 1.1 augustss
407 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
408 1.254.2.18 skrll
409 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
410 1.53 augustss if (sc->sc_freeeds == NULL) {
411 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
412 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
413 1.254.2.35 skrll
414 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
415 1.53 augustss OHCI_ED_ALIGN, &dma);
416 1.53 augustss if (err)
417 1.254.2.13 skrll return 0;
418 1.254.2.35 skrll
419 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
420 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
421 1.39 augustss offs = i * OHCI_SED_SIZE;
422 1.123 augustss sed = KERNADDR(&dma, offs);
423 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
424 1.195 bouyer sed->dma = dma;
425 1.195 bouyer sed->offs = offs;
426 1.1 augustss sed->next = sc->sc_freeeds;
427 1.1 augustss sc->sc_freeeds = sed;
428 1.1 augustss }
429 1.1 augustss }
430 1.1 augustss sed = sc->sc_freeeds;
431 1.1 augustss sc->sc_freeeds = sed->next;
432 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
433 1.254.2.35 skrll
434 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
435 1.1 augustss sed->next = 0;
436 1.254.2.13 skrll return sed;
437 1.1 augustss }
438 1.1 augustss
439 1.254.2.35 skrll static inline void
440 1.254.2.35 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
441 1.1 augustss {
442 1.254.2.35 skrll
443 1.254.2.35 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
444 1.254.2.35 skrll
445 1.1 augustss sed->next = sc->sc_freeeds;
446 1.1 augustss sc->sc_freeeds = sed;
447 1.1 augustss }
448 1.1 augustss
449 1.254.2.35 skrll void
450 1.254.2.35 skrll ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
451 1.254.2.35 skrll {
452 1.254.2.35 skrll
453 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
454 1.254.2.35 skrll ohci_free_sed_locked(sc, sed);
455 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
456 1.254.2.35 skrll }
457 1.254.2.35 skrll
458 1.1 augustss ohci_soft_td_t *
459 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
460 1.1 augustss {
461 1.1 augustss ohci_soft_td_t *std;
462 1.53 augustss usbd_status err;
463 1.1 augustss int i, offs;
464 1.4 augustss usb_dma_t dma;
465 1.1 augustss
466 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
467 1.254.2.18 skrll
468 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
469 1.53 augustss if (sc->sc_freetds == NULL) {
470 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
471 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
472 1.254.2.35 skrll
473 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
474 1.53 augustss OHCI_TD_ALIGN, &dma);
475 1.53 augustss if (err)
476 1.254.2.13 skrll return NULL;
477 1.254.2.35 skrll
478 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
479 1.254.2.58 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
480 1.39 augustss offs = i * OHCI_STD_SIZE;
481 1.123 augustss std = KERNADDR(&dma, offs);
482 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
483 1.195 bouyer std->dma = dma;
484 1.195 bouyer std->offs = offs;
485 1.1 augustss std->nexttd = sc->sc_freetds;
486 1.1 augustss sc->sc_freetds = std;
487 1.1 augustss }
488 1.1 augustss }
489 1.69 augustss
490 1.1 augustss std = sc->sc_freetds;
491 1.1 augustss sc->sc_freetds = std->nexttd;
492 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
493 1.254.2.35 skrll
494 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
495 1.83 augustss std->nexttd = NULL;
496 1.83 augustss std->xfer = NULL;
497 1.254.2.76 skrll std->held = NULL;
498 1.69 augustss
499 1.254.2.13 skrll return std;
500 1.1 augustss }
501 1.1 augustss
502 1.1 augustss void
503 1.254.2.35 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
504 1.1 augustss {
505 1.254.2.7 skrll
506 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
507 1.254.2.1 skrll
508 1.1 augustss std->nexttd = sc->sc_freetds;
509 1.1 augustss sc->sc_freetds = std;
510 1.1 augustss }
511 1.1 augustss
512 1.254.2.35 skrll void
513 1.254.2.35 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
514 1.254.2.35 skrll {
515 1.254.2.35 skrll
516 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
517 1.254.2.35 skrll ohci_free_std_locked(sc, std);
518 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
519 1.254.2.35 skrll }
520 1.254.2.35 skrll
521 1.254.2.72 skrll Static int
522 1.254.2.70 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd)
523 1.48 augustss {
524 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
525 1.254.2.7 skrll uint16_t flags = xfer->ux_flags;
526 1.48 augustss
527 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
528 1.224 mrg
529 1.254.2.18 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
530 1.254.2.70 skrll xfer->ux_pipe->up_dev->ud_addr,
531 1.254.2.70 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
532 1.254.2.70 skrll length, xfer->ux_pipe->up_dev->ud_speed);
533 1.254.2.35 skrll
534 1.254.2.35 skrll ASSERT_SLEEPABLE();
535 1.254.2.70 skrll KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
536 1.254.2.35 skrll
537 1.254.2.70 skrll size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
538 1.254.2.70 skrll nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
539 1.254.2.35 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
540 1.254.2.35 skrll KM_SLEEP);
541 1.254.2.35 skrll ox->ox_nstd = nstd;
542 1.254.2.35 skrll
543 1.254.2.70 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, nstd, 0, 0);
544 1.254.2.18 skrll
545 1.254.2.76 skrll for (size_t j = 0; j < ox->ox_nstd; j++) {
546 1.254.2.70 skrll ohci_soft_td_t *cur = ohci_alloc_std(sc);
547 1.254.2.70 skrll if (cur == NULL)
548 1.61 augustss goto nomem;
549 1.48 augustss
550 1.254.2.76 skrll ox->ox_stds[j] = cur;
551 1.254.2.76 skrll cur->held = &ox->ox_stds[j];
552 1.77 augustss cur->xfer = xfer;
553 1.61 augustss cur->flags = 0;
554 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new std=%p held at %p", ox, cur,
555 1.254.2.76 skrll cur->held, 0);
556 1.61 augustss }
557 1.48 augustss
558 1.254.2.72 skrll return 0;
559 1.61 augustss
560 1.61 augustss nomem:
561 1.254.2.35 skrll ohci_free_stds(sc, ox);
562 1.254.2.71 skrll kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd);
563 1.236 skrll
564 1.254.2.72 skrll return ENOMEM;
565 1.48 augustss }
566 1.48 augustss
567 1.82 augustss Static void
568 1.254.2.35 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
569 1.48 augustss {
570 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
571 1.254.2.35 skrll DPRINTF("ox=%p", ox, 0, 0, 0);
572 1.48 augustss
573 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
574 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
575 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
576 1.254.2.35 skrll if (std == NULL)
577 1.254.2.35 skrll break;
578 1.254.2.35 skrll ohci_free_std_locked(sc, std);
579 1.254.2.35 skrll }
580 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
581 1.254.2.35 skrll }
582 1.254.2.35 skrll
583 1.254.2.35 skrll void
584 1.254.2.35 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
585 1.254.2.35 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
586 1.254.2.35 skrll {
587 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
588 1.254.2.35 skrll ohci_soft_td_t *next, *cur;
589 1.254.2.35 skrll int len, curlen;
590 1.254.2.35 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
591 1.254.2.35 skrll uint16_t flags = xfer->ux_flags;
592 1.254.2.35 skrll
593 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
594 1.254.2.35 skrll DPRINTF("start len=%d", alen, 0, 0, 0);
595 1.254.2.35 skrll
596 1.254.2.35 skrll KASSERT(mutex_owned(&sc->sc_lock));
597 1.254.2.35 skrll
598 1.254.2.35 skrll DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d",
599 1.254.2.35 skrll xfer->ux_pipe->up_dev->ud_addr,
600 1.254.2.35 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
601 1.254.2.35 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
602 1.254.2.35 skrll
603 1.254.2.35 skrll KASSERT(sp);
604 1.254.2.35 skrll
605 1.254.2.35 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
606 1.254.2.35 skrll
607 1.254.2.70 skrll /*
608 1.254.2.70 skrll * Assign next for the len == 0 case where we don't go through the
609 1.254.2.70 skrll * main loop.
610 1.254.2.70 skrll */
611 1.254.2.35 skrll len = alen;
612 1.254.2.70 skrll cur = next = sp;
613 1.254.2.35 skrll
614 1.254.2.35 skrll usb_syncmem(dma, 0, len,
615 1.254.2.35 skrll rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
616 1.254.2.61 skrll const uint32_t tdflags = HTOO32(
617 1.254.2.35 skrll (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
618 1.254.2.35 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
619 1.254.2.35 skrll
620 1.254.2.70 skrll size_t curoffs = 0;
621 1.254.2.70 skrll for (size_t j = 1; len != 0;) {
622 1.254.2.35 skrll if (j == ox->ox_nstd)
623 1.254.2.35 skrll next = NULL;
624 1.254.2.35 skrll else
625 1.254.2.35 skrll next = ox->ox_stds[j++];
626 1.254.2.35 skrll KASSERT(next != cur);
627 1.254.2.35 skrll
628 1.254.2.70 skrll curlen = 0;
629 1.254.2.85 skrll const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
630 1.254.2.70 skrll ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1);
631 1.254.2.70 skrll
632 1.254.2.85 skrll const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys);
633 1.254.2.70 skrll ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys);
634 1.254.2.70 skrll /*
635 1.254.2.70 skrll * The OHCI hardware can handle at most one page
636 1.254.2.70 skrll * crossing per TD
637 1.254.2.70 skrll */
638 1.254.2.70 skrll curlen = len;
639 1.254.2.85 skrll if (sphyspg != ephyspg &&
640 1.254.2.85 skrll sphyspg + OHCI_PAGE_SIZE != ephyspg) {
641 1.254.2.35 skrll /* must use multiple TDs, fill as much as possible. */
642 1.254.2.35 skrll curlen = 2 * OHCI_PAGE_SIZE -
643 1.254.2.85 skrll OHCI_PAGE_OFFSET(sdataphys);
644 1.254.2.35 skrll /* the length must be a multiple of the max size */
645 1.254.2.35 skrll curlen -= curlen % mps;
646 1.254.2.85 skrll edataphys = DMAADDR(dma, curoffs + curlen - 1);
647 1.254.2.35 skrll }
648 1.254.2.70 skrll KASSERT(curlen != 0);
649 1.254.2.70 skrll DPRINTFN(4, "sdataphys=0x%08x edataphys=0x%08x "
650 1.254.2.70 skrll "len=%d curlen=%d", sdataphys, edataphys, len, curlen);
651 1.254.2.35 skrll
652 1.254.2.35 skrll cur->td.td_flags = tdflags;
653 1.254.2.70 skrll cur->td.td_cbp = HTOO32(sdataphys);
654 1.254.2.70 skrll cur->td.td_be = HTOO32(edataphys);
655 1.254.2.35 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
656 1.254.2.35 skrll cur->nexttd = next;
657 1.254.2.35 skrll cur->len = curlen;
658 1.254.2.35 skrll cur->flags = OHCI_ADD_LEN;
659 1.254.2.35 skrll cur->xfer = xfer;
660 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
661 1.254.2.35 skrll
662 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
663 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
664 1.254.2.70 skrll
665 1.254.2.70 skrll curoffs += curlen;
666 1.254.2.70 skrll len -= curlen;
667 1.254.2.70 skrll
668 1.254.2.70 skrll if (len != 0) {
669 1.254.2.70 skrll KASSERT(next != NULL);
670 1.254.2.70 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
671 1.254.2.70 skrll cur = next;
672 1.254.2.70 skrll }
673 1.254.2.35 skrll }
674 1.254.2.44 skrll cur->td.td_flags |=
675 1.254.2.74 skrll HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
676 1.254.2.44 skrll
677 1.254.2.35 skrll if (!rd &&
678 1.254.2.35 skrll (flags & USBD_FORCE_SHORT_XFER) &&
679 1.254.2.35 skrll alen % mps == 0) {
680 1.254.2.35 skrll /* Force a 0 length transfer at the end. */
681 1.254.2.35 skrll
682 1.254.2.35 skrll KASSERT(next != NULL);
683 1.254.2.35 skrll cur = next;
684 1.254.2.35 skrll
685 1.254.2.35 skrll cur->td.td_flags = tdflags;
686 1.254.2.35 skrll cur->td.td_cbp = 0; /* indicate 0 length packet */
687 1.254.2.70 skrll cur->td.td_nexttd = 0;
688 1.254.2.35 skrll cur->td.td_be = ~0;
689 1.254.2.35 skrll cur->nexttd = NULL;
690 1.254.2.35 skrll cur->len = 0;
691 1.254.2.35 skrll cur->flags = 0;
692 1.254.2.35 skrll cur->xfer = xfer;
693 1.254.2.35 skrll ohci_hash_add_td(sc, cur);
694 1.254.2.35 skrll
695 1.254.2.35 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
696 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
697 1.254.2.35 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
698 1.48 augustss }
699 1.254.2.35 skrll *ep = cur;
700 1.48 augustss }
701 1.48 augustss
702 1.60 augustss ohci_soft_itd_t *
703 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
704 1.60 augustss {
705 1.60 augustss ohci_soft_itd_t *sitd;
706 1.60 augustss usbd_status err;
707 1.224 mrg int i, offs;
708 1.60 augustss usb_dma_t dma;
709 1.60 augustss
710 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
711 1.254.2.18 skrll
712 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
713 1.60 augustss if (sc->sc_freeitds == NULL) {
714 1.254.2.18 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
715 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
716 1.254.2.35 skrll
717 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
718 1.83 augustss OHCI_ITD_ALIGN, &dma);
719 1.60 augustss if (err)
720 1.254.2.13 skrll return NULL;
721 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
722 1.254.2.58 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
723 1.83 augustss offs = i * OHCI_SITD_SIZE;
724 1.123 augustss sitd = KERNADDR(&dma, offs);
725 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
726 1.195 bouyer sitd->dma = dma;
727 1.195 bouyer sitd->offs = offs;
728 1.60 augustss sitd->nextitd = sc->sc_freeitds;
729 1.60 augustss sc->sc_freeitds = sitd;
730 1.60 augustss }
731 1.60 augustss }
732 1.83 augustss
733 1.60 augustss sitd = sc->sc_freeitds;
734 1.60 augustss sc->sc_freeitds = sitd->nextitd;
735 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
736 1.254.2.35 skrll
737 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
738 1.83 augustss sitd->nextitd = NULL;
739 1.83 augustss sitd->xfer = NULL;
740 1.83 augustss
741 1.83 augustss #ifdef DIAGNOSTIC
742 1.254.2.52 skrll sitd->isdone = true;
743 1.83 augustss #endif
744 1.83 augustss
745 1.254.2.13 skrll return sitd;
746 1.60 augustss }
747 1.60 augustss
748 1.254.2.35 skrll Static void
749 1.254.2.35 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
750 1.60 augustss {
751 1.83 augustss
752 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
753 1.254.2.18 skrll DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0);
754 1.83 augustss
755 1.254.2.24 skrll KASSERT(sitd->isdone);
756 1.83 augustss #ifdef DIAGNOSTIC
757 1.134 toshii /* Warn double free */
758 1.254.2.31 skrll sitd->isdone = false;
759 1.83 augustss #endif
760 1.83 augustss
761 1.60 augustss sitd->nextitd = sc->sc_freeitds;
762 1.60 augustss sc->sc_freeitds = sitd;
763 1.60 augustss }
764 1.60 augustss
765 1.254.2.35 skrll void
766 1.254.2.35 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
767 1.254.2.35 skrll {
768 1.254.2.35 skrll
769 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
770 1.254.2.35 skrll
771 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
772 1.254.2.35 skrll ohci_free_sitd_locked(sc, sitd);
773 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
774 1.254.2.35 skrll }
775 1.254.2.35 skrll
776 1.254.2.14 skrll int
777 1.91 augustss ohci_init(ohci_softc_t *sc)
778 1.1 augustss {
779 1.1 augustss ohci_soft_ed_t *sed, *psed;
780 1.53 augustss usbd_status err;
781 1.1 augustss int i;
782 1.254.2.1 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
783 1.16 augustss
784 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
785 1.254.2.18 skrll
786 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
787 1.199 jmcneill
788 1.198 cegger sc->sc_hcca = NULL;
789 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
790 1.224 mrg
791 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
792 1.254.2.22 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
793 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
794 1.224 mrg
795 1.254.2.77 skrll sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
796 1.224 mrg ohci_rhsc_softint, sc);
797 1.198 cegger
798 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
799 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
800 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
801 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
802 1.198 cegger
803 1.254.2.76 skrll TAILQ_INIT(&sc->sc_abortingxfers);
804 1.254.2.76 skrll
805 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
806 1.254.2.37 skrll "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
807 1.198 cegger
808 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
809 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
810 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
811 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
812 1.55 augustss
813 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
814 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
815 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
816 1.254.2.14 skrll return -1;
817 1.1 augustss }
818 1.254.2.7 skrll sc->sc_bus.ub_revision = USBREV_1_0;
819 1.254.2.7 skrll sc->sc_bus.ub_usedma = true;
820 1.153 fvdl
821 1.73 augustss /* XXX determine alignment by R/W */
822 1.1 augustss /* Allocate the HCCA area. */
823 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
824 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
825 1.198 cegger if (err) {
826 1.198 cegger sc->sc_hcca = NULL;
827 1.198 cegger return err;
828 1.198 cegger }
829 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
830 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
831 1.1 augustss
832 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
833 1.1 augustss
834 1.60 augustss /* Allocate dummy ED that starts the control list. */
835 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
836 1.53 augustss if (sc->sc_ctrl_head == NULL) {
837 1.254.2.14 skrll err = ENOMEM;
838 1.1 augustss goto bad1;
839 1.1 augustss }
840 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
841 1.34 augustss
842 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
843 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
844 1.53 augustss if (sc->sc_bulk_head == NULL) {
845 1.254.2.14 skrll err = ENOMEM;
846 1.1 augustss goto bad2;
847 1.1 augustss }
848 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
849 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
850 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
851 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
852 1.1 augustss
853 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
854 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
855 1.60 augustss if (sc->sc_isoc_head == NULL) {
856 1.254.2.14 skrll err = ENOMEM;
857 1.60 augustss goto bad3;
858 1.60 augustss }
859 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
860 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
861 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
862 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
863 1.60 augustss
864 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
865 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
866 1.1 augustss sed = ohci_alloc_sed(sc);
867 1.53 augustss if (sed == NULL) {
868 1.1 augustss while (--i >= 0)
869 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
870 1.254.2.14 skrll err = ENOMEM;
871 1.60 augustss goto bad4;
872 1.1 augustss }
873 1.1 augustss /* All ED fields are set to 0. */
874 1.1 augustss sc->sc_eds[i] = sed;
875 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
876 1.60 augustss if (i != 0)
877 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
878 1.60 augustss else
879 1.60 augustss psed= sc->sc_isoc_head;
880 1.60 augustss sed->next = psed;
881 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
882 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
883 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
884 1.1 augustss }
885 1.120 augustss /*
886 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
887 1.1 augustss * the tree set up properly to spread the interrupts.
888 1.1 augustss */
889 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
890 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
891 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
892 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
893 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
894 1.1 augustss
895 1.73 augustss #ifdef OHCI_DEBUG
896 1.254.2.18 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
897 1.254.2.39 skrll if (ohcidebug >= 15) {
898 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
899 1.254.2.18 skrll DPRINTFN(15, "ed#%d ", i, 0, 0, 0);
900 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
901 1.73 augustss }
902 1.254.2.18 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
903 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
904 1.73 augustss }
905 1.254.2.18 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
906 1.73 augustss #endif
907 1.73 augustss
908 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
909 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
910 1.161 augustss rwc = ctl & OHCI_RWC;
911 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
912 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
913 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
914 1.161 augustss
915 1.1 augustss /* Determine in what context we are running. */
916 1.1 augustss if (ctl & OHCI_IR) {
917 1.1 augustss /* SMM active, request change */
918 1.254.2.18 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
919 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
920 1.160 augustss (OHCI_OC | OHCI_MIE))
921 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
922 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
923 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
924 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
925 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
926 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
927 1.1 augustss }
928 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
929 1.1 augustss if ((ctl & OHCI_IR) == 0) {
930 1.199 jmcneill aprint_error_dev(sc->sc_dev,
931 1.199 jmcneill "SMM does not respond, resetting\n");
932 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
933 1.1 augustss goto reset;
934 1.1 augustss }
935 1.103 augustss #if 0
936 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
937 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
938 1.1 augustss /* BIOS started controller. */
939 1.254.2.18 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
940 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
941 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
942 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
943 1.1 augustss }
944 1.103 augustss #endif
945 1.1 augustss } else {
946 1.254.2.18 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
947 1.1 augustss reset:
948 1.1 augustss /* Controller was cold started. */
949 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
950 1.1 augustss }
951 1.1 augustss
952 1.16 augustss /*
953 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
954 1.25 augustss * without it some controllers do not start.
955 1.16 augustss */
956 1.254.2.18 skrll DPRINTF("sc %p: resetting", sc, 0, 0, 0);
957 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
958 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
959 1.16 augustss
960 1.1 augustss /* We now own the host controller and the bus has been reset. */
961 1.1 augustss
962 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
963 1.1 augustss /* Nominal time for a reset is 10 us. */
964 1.1 augustss for (i = 0; i < 10; i++) {
965 1.1 augustss delay(10);
966 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
967 1.1 augustss if (!hcr)
968 1.1 augustss break;
969 1.1 augustss }
970 1.1 augustss if (hcr) {
971 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
972 1.254.2.14 skrll err = EIO;
973 1.60 augustss goto bad5;
974 1.1 augustss }
975 1.52 augustss #ifdef OHCI_DEBUG
976 1.254.2.39 skrll if (ohcidebug >= 15)
977 1.1 augustss ohci_dumpregs(sc);
978 1.1 augustss #endif
979 1.1 augustss
980 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
981 1.1 augustss
982 1.1 augustss /* Set up HC registers. */
983 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
984 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
985 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
986 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
987 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
988 1.55 augustss /* switch on desired functional features */
989 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
990 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
991 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
992 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
993 1.1 augustss /* And finally start it! */
994 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
995 1.1 augustss
996 1.1 augustss /*
997 1.1 augustss * The controller is now OPERATIONAL. Set a some final
998 1.1 augustss * registers that should be set earlier, but that the
999 1.1 augustss * controller ignores when in the SUSPEND state.
1000 1.1 augustss */
1001 1.161 augustss ival = OHCI_GET_IVAL(fm);
1002 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
1003 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
1004 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
1005 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
1006 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
1007 1.1 augustss
1008 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
1009 1.249 skrll /* no overcurrent protection */
1010 1.249 skrll desca |= OHCI_NOCP;
1011 1.249 skrll /*
1012 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1013 1.249 skrll * that
1014 1.249 skrll * - ports are always power switched
1015 1.249 skrll * - don't wait for powered root hub port
1016 1.249 skrll */
1017 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1018 1.249 skrll }
1019 1.249 skrll
1020 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1021 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1022 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1023 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1024 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1025 1.1 augustss
1026 1.85 augustss /*
1027 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1028 1.85 augustss * otherwise it will occasionally report 0 ports.
1029 1.85 augustss */
1030 1.145 augustss sc->sc_noport = 0;
1031 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1032 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1033 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1034 1.145 augustss }
1035 1.1 augustss
1036 1.52 augustss #ifdef OHCI_DEBUG
1037 1.254.2.39 skrll if (ohcidebug >= 5)
1038 1.1 augustss ohci_dumpregs(sc);
1039 1.1 augustss #endif
1040 1.120 augustss
1041 1.1 augustss /* Set up the bus struct. */
1042 1.254.2.7 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1043 1.254.2.7 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1044 1.1 augustss
1045 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1046 1.59 augustss
1047 1.167 augustss /* Finally, turn on interrupts. */
1048 1.254.2.18 skrll DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1049 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1050 1.167 augustss
1051 1.254.2.14 skrll return 0;
1052 1.1 augustss
1053 1.60 augustss bad5:
1054 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1055 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1056 1.60 augustss bad4:
1057 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1058 1.1 augustss bad3:
1059 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1060 1.144 augustss bad2:
1061 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1062 1.1 augustss bad1:
1063 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1064 1.198 cegger sc->sc_hcca = NULL;
1065 1.254.2.13 skrll return err;
1066 1.1 augustss }
1067 1.1 augustss
1068 1.254.2.19 skrll struct usbd_xfer *
1069 1.254.2.23 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1070 1.62 augustss {
1071 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1072 1.254.2.19 skrll struct usbd_xfer *xfer;
1073 1.62 augustss
1074 1.232 christos xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT);
1075 1.118 augustss if (xfer != NULL) {
1076 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1077 1.118 augustss #ifdef DIAGNOSTIC
1078 1.254.2.7 skrll xfer->ux_state = XFER_BUSY;
1079 1.118 augustss #endif
1080 1.118 augustss }
1081 1.254.2.13 skrll return xfer;
1082 1.62 augustss }
1083 1.62 augustss
1084 1.62 augustss void
1085 1.254.2.19 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1086 1.62 augustss {
1087 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1088 1.62 augustss
1089 1.254.2.24 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
1090 1.254.2.24 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1091 1.118 augustss #ifdef DIAGNOSTIC
1092 1.254.2.7 skrll xfer->ux_state = XFER_FREE;
1093 1.118 augustss #endif
1094 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1095 1.42 augustss }
1096 1.42 augustss
1097 1.224 mrg Static void
1098 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1099 1.224 mrg {
1100 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1101 1.224 mrg
1102 1.224 mrg *lock = &sc->sc_lock;
1103 1.224 mrg }
1104 1.224 mrg
1105 1.59 augustss /*
1106 1.59 augustss * Shut down the controller when the system is going down.
1107 1.59 augustss */
1108 1.188 dyoung bool
1109 1.188 dyoung ohci_shutdown(device_t self, int flags)
1110 1.59 augustss {
1111 1.188 dyoung ohci_softc_t *sc = device_private(self);
1112 1.59 augustss
1113 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1114 1.254.2.18 skrll
1115 1.254.2.18 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1116 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1117 1.188 dyoung return true;
1118 1.59 augustss }
1119 1.59 augustss
1120 1.185 jmcneill bool
1121 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1122 1.33 augustss {
1123 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1124 1.185 jmcneill uint32_t ctl;
1125 1.33 augustss
1126 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1127 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1128 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1129 1.224 mrg
1130 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1131 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1132 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1133 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1134 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1135 1.185 jmcneill sc->sc_bulk_head->physaddr);
1136 1.185 jmcneill if (sc->sc_intre)
1137 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1138 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1139 1.185 jmcneill if (sc->sc_control)
1140 1.185 jmcneill ctl = sc->sc_control;
1141 1.185 jmcneill else
1142 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1143 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1144 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1145 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1146 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1147 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1148 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1149 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1150 1.224 mrg
1151 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1152 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1153 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1154 1.185 jmcneill
1155 1.185 jmcneill return true;
1156 1.185 jmcneill }
1157 1.185 jmcneill
1158 1.185 jmcneill bool
1159 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1160 1.185 jmcneill {
1161 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1162 1.185 jmcneill uint32_t ctl;
1163 1.95 augustss
1164 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1165 1.254.2.7 skrll sc->sc_bus.ub_usepolling++;
1166 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1167 1.224 mrg
1168 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1169 1.185 jmcneill if (sc->sc_control == 0) {
1170 1.185 jmcneill /*
1171 1.185 jmcneill * Preserve register values, in case that BIOS
1172 1.185 jmcneill * does not recover them.
1173 1.185 jmcneill */
1174 1.185 jmcneill sc->sc_control = ctl;
1175 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1176 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1177 1.95 augustss }
1178 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1179 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1180 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1181 1.224 mrg
1182 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1183 1.254.2.7 skrll sc->sc_bus.ub_usepolling--;
1184 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1185 1.185 jmcneill
1186 1.185 jmcneill return true;
1187 1.33 augustss }
1188 1.33 augustss
1189 1.52 augustss #ifdef OHCI_DEBUG
1190 1.1 augustss void
1191 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1192 1.1 augustss {
1193 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1194 1.254.2.18 skrll
1195 1.254.2.18 skrll DPRINTF("rev=0x%08x control=0x%08x command=0x%08x",
1196 1.41 augustss OREAD4(sc, OHCI_REVISION),
1197 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1198 1.254.2.18 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1199 1.254.2.18 skrll DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x",
1200 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1201 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1202 1.254.2.18 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1203 1.254.2.18 skrll DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x",
1204 1.41 augustss OREAD4(sc, OHCI_HCCA),
1205 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1206 1.254.2.18 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1207 1.254.2.18 skrll DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x",
1208 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1209 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1210 1.254.2.18 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1211 1.254.2.18 skrll DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x",
1212 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1213 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1214 1.254.2.18 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1215 1.254.2.18 skrll DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x",
1216 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1217 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1218 1.254.2.18 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1219 1.254.2.18 skrll DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x",
1220 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1221 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1222 1.254.2.18 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1223 1.254.2.18 skrll DPRINTF(" port1=0x%08x port2=0x%08x",
1224 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1225 1.254.2.18 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1226 1.254.2.18 skrll DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x",
1227 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1228 1.254.2.18 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1229 1.1 augustss }
1230 1.1 augustss #endif
1231 1.1 augustss
1232 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1233 1.53 augustss
1234 1.1 augustss int
1235 1.91 augustss ohci_intr(void *p)
1236 1.1 augustss {
1237 1.1 augustss ohci_softc_t *sc = p;
1238 1.224 mrg int ret = 0;
1239 1.111 augustss
1240 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1241 1.254.2.18 skrll
1242 1.224 mrg if (sc == NULL)
1243 1.254.2.13 skrll return 0;
1244 1.53 augustss
1245 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1246 1.224 mrg
1247 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1248 1.224 mrg goto done;
1249 1.224 mrg
1250 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1251 1.254.2.7 skrll if (sc->sc_bus.ub_usepolling) {
1252 1.254.2.18 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1253 1.154 joff /* for level triggered intrs, should do something to ack */
1254 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1255 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1256 1.155 perry
1257 1.224 mrg goto done;
1258 1.57 augustss }
1259 1.53 augustss
1260 1.224 mrg ret = ohci_intr1(sc);
1261 1.224 mrg
1262 1.224 mrg done:
1263 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1264 1.224 mrg return ret;
1265 1.53 augustss }
1266 1.53 augustss
1267 1.82 augustss Static int
1268 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1269 1.53 augustss {
1270 1.254.2.1 skrll uint32_t intrs, eintrs;
1271 1.1 augustss
1272 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1273 1.105 augustss
1274 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1275 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1276 1.15 augustss #ifdef DIAGNOSTIC
1277 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1278 1.15 augustss #endif
1279 1.254.2.13 skrll return 0;
1280 1.15 augustss }
1281 1.15 augustss
1282 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1283 1.224 mrg
1284 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1285 1.1 augustss if (!intrs)
1286 1.254.2.13 skrll return 0;
1287 1.55 augustss
1288 1.254.2.32 skrll /* Acknowledge */
1289 1.254.2.32 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1290 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1291 1.254.2.18 skrll DPRINTFN(7, "sc=%p", sc, 0, 0, 0);
1292 1.254.2.18 skrll DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)",
1293 1.254.2.18 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1294 1.254.2.18 skrll sc->sc_eintrs);
1295 1.211 matt
1296 1.211 matt if (!eintrs) {
1297 1.254.2.13 skrll return 0;
1298 1.211 matt }
1299 1.1 augustss
1300 1.1 augustss if (eintrs & OHCI_SO) {
1301 1.100 augustss sc->sc_overrun_cnt++;
1302 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1303 1.100 augustss printf("%s: %u scheduling overruns\n",
1304 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1305 1.100 augustss sc->sc_overrun_cnt = 0;
1306 1.100 augustss }
1307 1.1 augustss /* XXX do what */
1308 1.106 augustss eintrs &= ~OHCI_SO;
1309 1.1 augustss }
1310 1.1 augustss if (eintrs & OHCI_WDH) {
1311 1.157 mycroft /*
1312 1.157 mycroft * We block the interrupt below, and reenable it later from
1313 1.157 mycroft * ohci_softintr().
1314 1.157 mycroft */
1315 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1316 1.1 augustss }
1317 1.1 augustss if (eintrs & OHCI_RD) {
1318 1.254.2.47 skrll DPRINTFN(5, "resume detect", sc, 0, 0, 0);
1319 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1320 1.1 augustss /* XXX process resume detect */
1321 1.1 augustss }
1322 1.1 augustss if (eintrs & OHCI_UE) {
1323 1.254.2.47 skrll DPRINTFN(5, "unrecoverable error", sc, 0, 0, 0);
1324 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1325 1.190 drochner device_xname(sc->sc_dev));
1326 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1327 1.1 augustss /* XXX what else */
1328 1.1 augustss }
1329 1.1 augustss if (eintrs & OHCI_RHSC) {
1330 1.120 augustss /*
1331 1.157 mycroft * We block the interrupt below, and reenable it later from
1332 1.157 mycroft * a timeout.
1333 1.1 augustss */
1334 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1335 1.1 augustss }
1336 1.254.2.76 skrll if (eintrs & OHCI_SF) {
1337 1.254.2.76 skrll struct ohci_xfer *ox, *tmp;
1338 1.254.2.76 skrll TAILQ_FOREACH_SAFE(ox, &sc->sc_abortingxfers, ox_abnext, tmp) {
1339 1.254.2.76 skrll DPRINTFN(10, "SF %p xfer %p", sc, ox, 0, 0);
1340 1.254.2.76 skrll ox->ox_abintrs &= ~OHCI_SF;
1341 1.254.2.76 skrll KASSERT(ox->ox_abintrs == 0);
1342 1.254.2.76 skrll TAILQ_REMOVE(&sc->sc_abortingxfers, ox, ox_abnext);
1343 1.254.2.76 skrll }
1344 1.254.2.76 skrll cv_broadcast(&sc->sc_softwake_cv);
1345 1.254.2.76 skrll
1346 1.254.2.76 skrll KASSERT(TAILQ_EMPTY(&sc->sc_abortingxfers));
1347 1.254.2.76 skrll DPRINTFN(10, "end SOF %p", sc, 0, 0, 0);
1348 1.254.2.76 skrll /* Don't remove OHIC_SF from eintrs so it is blocked below */
1349 1.254.2.76 skrll }
1350 1.1 augustss
1351 1.106 augustss if (eintrs != 0) {
1352 1.157 mycroft /* Block unprocessed interrupts. */
1353 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1354 1.106 augustss sc->sc_eintrs &= ~eintrs;
1355 1.254.2.76 skrll DPRINTF("sc %p blocking/removing intrs 0x%x", sc, eintrs, 0, 0);
1356 1.106 augustss }
1357 1.1 augustss
1358 1.254.2.13 skrll return 1;
1359 1.1 augustss }
1360 1.1 augustss
1361 1.1 augustss void
1362 1.104 augustss ohci_rhsc_enable(void *v_sc)
1363 1.104 augustss {
1364 1.104 augustss ohci_softc_t *sc = v_sc;
1365 1.104 augustss
1366 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1367 1.254.2.18 skrll DPRINTF("sc %p", sc, 0, 0, 0);
1368 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1369 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1370 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1371 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1372 1.1 augustss }
1373 1.1 augustss
1374 1.52 augustss #ifdef OHCI_DEBUG
1375 1.166 drochner const char *ohci_cc_strs[] = {
1376 1.13 augustss "NO_ERROR",
1377 1.13 augustss "CRC",
1378 1.13 augustss "BIT_STUFFING",
1379 1.13 augustss "DATA_TOGGLE_MISMATCH",
1380 1.13 augustss "STALL",
1381 1.13 augustss "DEVICE_NOT_RESPONDING",
1382 1.13 augustss "PID_CHECK_FAILURE",
1383 1.13 augustss "UNEXPECTED_PID",
1384 1.13 augustss "DATA_OVERRUN",
1385 1.13 augustss "DATA_UNDERRUN",
1386 1.13 augustss "BUFFER_OVERRUN",
1387 1.13 augustss "BUFFER_UNDERRUN",
1388 1.67 augustss "reserved",
1389 1.67 augustss "reserved",
1390 1.67 augustss "NOT_ACCESSED",
1391 1.13 augustss "NOT_ACCESSED",
1392 1.13 augustss };
1393 1.13 augustss #endif
1394 1.13 augustss
1395 1.1 augustss void
1396 1.157 mycroft ohci_softintr(void *v)
1397 1.83 augustss {
1398 1.190 drochner struct usbd_bus *bus = v;
1399 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1400 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1401 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1402 1.254.2.19 skrll struct usbd_xfer *xfer;
1403 1.157 mycroft struct ohci_pipe *opipe;
1404 1.224 mrg int len, cc;
1405 1.157 mycroft int i, j, actlen, iframes, uedir;
1406 1.254.2.76 skrll ohci_physaddr_t done = 0;
1407 1.254.2.82 skrll bool polling = sc->sc_bus.ub_usepolling;
1408 1.157 mycroft
1409 1.254.2.82 skrll KASSERT(polling || mutex_owned(&sc->sc_lock));
1410 1.224 mrg
1411 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1412 1.157 mycroft
1413 1.254.2.76 skrll /*
1414 1.254.2.76 skrll * Only read hccadone if WDH is set - we might get here from places
1415 1.254.2.76 skrll * other than an interrupt
1416 1.254.2.76 skrll */
1417 1.254.2.76 skrll if (!(OREAD4(sc, OHCI_INTERRUPT_STATUS) & OHCI_WDH)) {
1418 1.254.2.76 skrll DPRINTFN(10, "no WDH %p", sc, 0, 0, 0);
1419 1.254.2.76 skrll return;
1420 1.254.2.76 skrll }
1421 1.254.2.76 skrll
1422 1.254.2.76 skrll DPRINTFN(10, "WDH %p", sc, 0, 0, 0);
1423 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1424 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1425 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1426 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1427 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1428 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1429 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1430 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1431 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1432 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1433 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1434 1.83 augustss
1435 1.83 augustss /* Reverse the done list. */
1436 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1437 1.83 augustss std = ohci_hash_find_td(sc, done);
1438 1.83 augustss if (std != NULL) {
1439 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1440 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1441 1.83 augustss std->dnext = sdone;
1442 1.168 augustss done = O32TOH(std->td.td_nexttd);
1443 1.83 augustss sdone = std;
1444 1.254.2.18 skrll DPRINTFN(10, "add TD %p", std, 0, 0, 0);
1445 1.83 augustss continue;
1446 1.83 augustss }
1447 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1448 1.83 augustss if (sitd != NULL) {
1449 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1450 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1451 1.83 augustss sitd->dnext = sidone;
1452 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1453 1.83 augustss sidone = sitd;
1454 1.254.2.18 skrll DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0);
1455 1.83 augustss continue;
1456 1.83 augustss }
1457 1.254.2.57 skrll DPRINTFN(10, "addr %p not found", done, 0, 0, 0);
1458 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1459 1.218 jmcneill (u_long)done);
1460 1.218 jmcneill break;
1461 1.83 augustss }
1462 1.83 augustss
1463 1.254.2.18 skrll DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0);
1464 1.254.2.41 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1465 1.52 augustss #ifdef OHCI_DEBUG
1466 1.254.2.39 skrll if (ohcidebug >= 10) {
1467 1.234 skrll for (std = sdone; std; std = std->dnext)
1468 1.254.2.1 skrll ohci_dump_td(sc, std);
1469 1.1 augustss }
1470 1.1 augustss #endif
1471 1.254.2.41 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1472 1.1 augustss
1473 1.48 augustss for (std = sdone; std; std = stdnext) {
1474 1.53 augustss xfer = std->xfer;
1475 1.48 augustss stdnext = std->dnext;
1476 1.254.2.76 skrll DPRINTFN(10, "std=%p xfer=%p hcpriv=%p dnext=%p", std, xfer,
1477 1.254.2.76 skrll xfer ? xfer->ux_hcpriv : 0, stdnext);
1478 1.71 augustss if (xfer == NULL) {
1479 1.117 augustss /*
1480 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1481 1.71 augustss * with this TD. It is tailp that happened to end up on
1482 1.71 augustss * the done queue.
1483 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1484 1.71 augustss */
1485 1.71 augustss continue;
1486 1.71 augustss }
1487 1.254.2.76 skrll if (std->held == NULL) {
1488 1.254.2.76 skrll DPRINTFN(10, "std=%p held is null", std, 0, 0, 0);
1489 1.254.2.76 skrll ohci_hash_rem_td(sc, std);
1490 1.254.2.76 skrll ohci_free_std_locked(sc, std);
1491 1.254.2.76 skrll continue;
1492 1.254.2.76 skrll }
1493 1.254.2.76 skrll /*
1494 1.254.2.76 skrll * Make sure the timeout handler didn't run or ran to the end
1495 1.254.2.76 skrll * and set the transfer status.
1496 1.254.2.76 skrll */
1497 1.254.2.82 skrll callout_halt(&xfer->ux_callout, polling ? NULL : &sc->sc_lock);
1498 1.254.2.76 skrll
1499 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1500 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1501 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1502 1.254.2.76 skrll
1503 1.38 augustss /* Handled by abort routine. */
1504 1.83 augustss continue;
1505 1.83 augustss }
1506 1.141 mycroft
1507 1.141 mycroft len = std->len;
1508 1.141 mycroft if (std->td.td_cbp != 0)
1509 1.168 augustss len -= O32TOH(std->td.td_be) -
1510 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1511 1.254.2.18 skrll DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0);
1512 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1513 1.254.2.7 skrll xfer->ux_actlen += len;
1514 1.141 mycroft
1515 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1516 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1517 1.254.2.42 skrll ohci_hash_rem_td(sc, std);
1518 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1519 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1520 1.53 augustss usb_transfer_complete(xfer);
1521 1.21 augustss }
1522 1.1 augustss } else {
1523 1.48 augustss /*
1524 1.48 augustss * Endpoint is halted. First unlink all the TDs
1525 1.48 augustss * belonging to the failed transfer, and then restart
1526 1.48 augustss * the endpoint.
1527 1.48 augustss */
1528 1.1 augustss ohci_soft_td_t *p, *n;
1529 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1530 1.48 augustss
1531 1.254.2.43 skrll DPRINTFN(10, "error cc=%d", cc, 0, 0, 0);
1532 1.48 augustss
1533 1.254.2.35 skrll /* remove xfer's TDs from the hash */
1534 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1535 1.1 augustss n = p->nexttd;
1536 1.254.2.35 skrll ohci_hash_rem_td(sc, p);
1537 1.1 augustss }
1538 1.48 augustss
1539 1.254.2.44 skrll ohci_soft_ed_t *sed = opipe->sed;
1540 1.254.2.44 skrll
1541 1.254.2.44 skrll /* clear halt and TD chain */
1542 1.254.2.44 skrll sed->ed.ed_headp = HTOO32(p->physaddr);
1543 1.254.2.45 skrll usb_syncmem(&sed->dma,
1544 1.254.2.46 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1545 1.254.2.45 skrll sizeof(sed->ed.ed_headp),
1546 1.254.2.44 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1547 1.254.2.44 skrll
1548 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1549 1.48 augustss
1550 1.254.2.44 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1551 1.254.2.44 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1552 1.254.2.44 skrll else if (cc == OHCI_CC_STALL)
1553 1.254.2.7 skrll xfer->ux_status = USBD_STALLED;
1554 1.1 augustss else
1555 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1556 1.53 augustss usb_transfer_complete(xfer);
1557 1.1 augustss }
1558 1.1 augustss }
1559 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1560 1.83 augustss #ifdef OHCI_DEBUG
1561 1.254.2.39 skrll if (ohcidebug >= 10) {
1562 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1563 1.254.2.1 skrll ohci_dump_itd(sc, sitd);
1564 1.83 augustss }
1565 1.83 augustss #endif
1566 1.254.2.41 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1567 1.83 augustss
1568 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1569 1.83 augustss xfer = sitd->xfer;
1570 1.83 augustss sitdnext = sitd->dnext;
1571 1.254.2.18 skrll DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer,
1572 1.254.2.18 skrll xfer ? xfer->ux_hcpriv : 0, 0);
1573 1.83 augustss if (xfer == NULL)
1574 1.83 augustss continue;
1575 1.254.2.7 skrll if (xfer->ux_status == USBD_CANCELLED ||
1576 1.254.2.7 skrll xfer->ux_status == USBD_TIMEOUT) {
1577 1.254.2.18 skrll DPRINTF("cancel/timeout %p", xfer, 0, 0, 0);
1578 1.83 augustss /* Handled by abort routine. */
1579 1.83 augustss continue;
1580 1.83 augustss }
1581 1.254.2.24 skrll KASSERT(!sitd->isdone);
1582 1.83 augustss #ifdef DIAGNOSTIC
1583 1.254.2.31 skrll sitd->isdone = true;
1584 1.83 augustss #endif
1585 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1586 1.134 toshii ohci_soft_itd_t *next;
1587 1.134 toshii
1588 1.254.2.25 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1589 1.254.2.21 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1590 1.254.2.7 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1591 1.134 toshii bEndpointAddress);
1592 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1593 1.134 toshii actlen = 0;
1594 1.254.2.7 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1595 1.134 toshii sitd = next) {
1596 1.134 toshii next = sitd->nextitd;
1597 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1598 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1599 1.254.2.7 skrll xfer->ux_status = USBD_IOERROR;
1600 1.134 toshii /* For input, update frlengths with actual */
1601 1.134 toshii /* XXX anything necessary for output? */
1602 1.134 toshii if (uedir == UE_DIR_IN &&
1603 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1604 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1605 1.135 toshii sitd->itd.itd_flags));
1606 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1607 1.168 augustss len = O16TOH(sitd->
1608 1.134 toshii itd.itd_offset[j]);
1609 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1610 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1611 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1612 1.158 toshii len = 0;
1613 1.158 toshii else
1614 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1615 1.254.2.7 skrll xfer->ux_frlengths[i] = len;
1616 1.134 toshii actlen += len;
1617 1.134 toshii }
1618 1.134 toshii }
1619 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1620 1.134 toshii break;
1621 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1622 1.254.2.35 skrll
1623 1.83 augustss }
1624 1.254.2.35 skrll ohci_hash_rem_itd(sc, sitd);
1625 1.134 toshii if (uedir == UE_DIR_IN &&
1626 1.254.2.7 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1627 1.254.2.7 skrll xfer->ux_actlen = actlen;
1628 1.254.2.7 skrll xfer->ux_hcpriv = NULL;
1629 1.134 toshii
1630 1.83 augustss usb_transfer_complete(xfer);
1631 1.83 augustss }
1632 1.83 augustss }
1633 1.83 augustss
1634 1.254.2.18 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1635 1.1 augustss }
1636 1.1 augustss
1637 1.1 augustss void
1638 1.254.2.19 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1639 1.1 augustss {
1640 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1641 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1642 1.254.2.7 skrll int len = UGETW(xfer->ux_request.wLength);
1643 1.254.2.7 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1644 1.195 bouyer
1645 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1646 1.254.2.18 skrll DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0);
1647 1.1 augustss
1648 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1649 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1650 1.224 mrg
1651 1.195 bouyer if (len)
1652 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1653 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1654 1.254.2.30 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1655 1.254.2.30 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1656 1.1 augustss }
1657 1.1 augustss
1658 1.1 augustss void
1659 1.254.2.19 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1660 1.1 augustss {
1661 1.254.2.54 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1662 1.195 bouyer int isread =
1663 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1664 1.1 augustss
1665 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1666 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1667 1.1 augustss
1668 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1669 1.224 mrg
1670 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1671 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1672 1.1 augustss }
1673 1.1 augustss
1674 1.1 augustss void
1675 1.254.2.19 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1676 1.3 augustss {
1677 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1678 1.254.2.25 skrll
1679 1.195 bouyer int isread =
1680 1.254.2.7 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1681 1.195 bouyer
1682 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1683 1.224 mrg
1684 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1685 1.254.2.18 skrll DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0);
1686 1.254.2.7 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1687 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1688 1.3 augustss }
1689 1.3 augustss
1690 1.224 mrg Static void
1691 1.224 mrg ohci_rhsc_softint(void *arg)
1692 1.224 mrg {
1693 1.224 mrg ohci_softc_t *sc = arg;
1694 1.224 mrg
1695 1.224 mrg mutex_enter(&sc->sc_lock);
1696 1.224 mrg
1697 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1698 1.224 mrg
1699 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1700 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1701 1.224 mrg
1702 1.224 mrg mutex_exit(&sc->sc_lock);
1703 1.224 mrg }
1704 1.224 mrg
1705 1.3 augustss void
1706 1.254.2.19 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1707 1.1 augustss {
1708 1.1 augustss u_char *p;
1709 1.1 augustss int i, m;
1710 1.243 martin int hstatus __unused;
1711 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1712 1.1 augustss
1713 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1714 1.224 mrg
1715 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1716 1.254.2.18 skrll DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0);
1717 1.1 augustss
1718 1.53 augustss if (xfer == NULL) {
1719 1.1 augustss /* Just ignore the change. */
1720 1.1 augustss return;
1721 1.1 augustss }
1722 1.1 augustss
1723 1.254.2.7 skrll p = xfer->ux_buf;
1724 1.254.2.7 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1725 1.254.2.7 skrll memset(p, 0, xfer->ux_length);
1726 1.1 augustss for (i = 1; i <= m; i++) {
1727 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1728 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1729 1.1 augustss p[i/8] |= 1 << (i%8);
1730 1.1 augustss }
1731 1.254.2.18 skrll DPRINTF("change=0x%02x", *p, 0, 0, 0);
1732 1.254.2.7 skrll xfer->ux_actlen = xfer->ux_length;
1733 1.254.2.7 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1734 1.1 augustss
1735 1.53 augustss usb_transfer_complete(xfer);
1736 1.38 augustss }
1737 1.38 augustss
1738 1.38 augustss void
1739 1.254.2.19 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1740 1.65 augustss {
1741 1.254.2.54 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1742 1.254.2.54 skrll
1743 1.254.2.54 skrll KASSERT(mutex_owned(&sc->sc_lock));
1744 1.254.2.54 skrll
1745 1.254.2.54 skrll KASSERT(sc->sc_intrxfer == xfer);
1746 1.254.2.54 skrll sc->sc_intrxfer = NULL;
1747 1.65 augustss }
1748 1.65 augustss
1749 1.5 augustss void
1750 1.91 augustss ohci_poll(struct usbd_bus *bus)
1751 1.5 augustss {
1752 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1753 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1754 1.254.2.18 skrll
1755 1.105 augustss #ifdef OHCI_DEBUG
1756 1.105 augustss static int last;
1757 1.105 augustss int new;
1758 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1759 1.105 augustss if (new != last) {
1760 1.254.2.18 skrll DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0);
1761 1.105 augustss last = new;
1762 1.105 augustss }
1763 1.105 augustss #endif
1764 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1765 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1766 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1767 1.53 augustss ohci_intr1(sc);
1768 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1769 1.224 mrg }
1770 1.1 augustss }
1771 1.1 augustss
1772 1.1 augustss /*
1773 1.224 mrg * Add an ED to the schedule. Called with USB lock held.
1774 1.1 augustss */
1775 1.224 mrg Static void
1776 1.168 augustss ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1777 1.1 augustss {
1778 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1779 1.254.2.18 skrll DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0);
1780 1.113 augustss
1781 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1782 1.224 mrg
1783 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1784 1.195 bouyer sizeof(head->ed.ed_nexted),
1785 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1786 1.1 augustss sed->next = head->next;
1787 1.39 augustss sed->ed.ed_nexted = head->ed.ed_nexted;
1788 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1789 1.195 bouyer sizeof(sed->ed.ed_nexted),
1790 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1791 1.1 augustss head->next = sed;
1792 1.168 augustss head->ed.ed_nexted = HTOO32(sed->physaddr);
1793 1.195 bouyer usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1794 1.195 bouyer sizeof(head->ed.ed_nexted),
1795 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1796 1.1 augustss }
1797 1.1 augustss
1798 1.1 augustss /*
1799 1.224 mrg * Remove an ED from the schedule. Called with USB lock held.
1800 1.3 augustss */
1801 1.224 mrg Static void
1802 1.224 mrg ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1803 1.3 augustss {
1804 1.120 augustss ohci_soft_ed_t *p;
1805 1.3 augustss
1806 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1807 1.224 mrg
1808 1.3 augustss /* XXX */
1809 1.133 toshii for (p = head; p != NULL && p->next != sed; p = p->next)
1810 1.3 augustss ;
1811 1.254.2.20 skrll KASSERT(p != NULL);
1812 1.254.2.20 skrll
1813 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1814 1.195 bouyer sizeof(sed->ed.ed_nexted),
1815 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1816 1.3 augustss p->next = sed->next;
1817 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1818 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1819 1.195 bouyer sizeof(p->ed.ed_nexted),
1820 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1821 1.3 augustss }
1822 1.3 augustss
1823 1.3 augustss /*
1824 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1825 1.1 augustss * the host controller. This queue is the processed by software.
1826 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1827 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1828 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1829 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1830 1.1 augustss * hash value.
1831 1.1 augustss */
1832 1.1 augustss
1833 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1834 1.224 mrg /* Called with USB lock held. */
1835 1.1 augustss void
1836 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1837 1.1 augustss {
1838 1.1 augustss int h = HASH(std->physaddr);
1839 1.1 augustss
1840 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1841 1.224 mrg
1842 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1843 1.1 augustss }
1844 1.1 augustss
1845 1.224 mrg /* Called with USB lock held. */
1846 1.1 augustss void
1847 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1848 1.1 augustss {
1849 1.46 augustss
1850 1.254.2.7 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1851 1.224 mrg
1852 1.1 augustss LIST_REMOVE(std, hnext);
1853 1.1 augustss }
1854 1.1 augustss
1855 1.1 augustss ohci_soft_td_t *
1856 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1857 1.1 augustss {
1858 1.1 augustss int h = HASH(a);
1859 1.1 augustss ohci_soft_td_t *std;
1860 1.1 augustss
1861 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1862 1.53 augustss std != NULL;
1863 1.1 augustss std = LIST_NEXT(std, hnext))
1864 1.1 augustss if (std->physaddr == a)
1865 1.254.2.13 skrll return std;
1866 1.254.2.13 skrll return NULL;
1867 1.83 augustss }
1868 1.83 augustss
1869 1.224 mrg /* Called with USB lock held. */
1870 1.83 augustss void
1871 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1872 1.83 augustss {
1873 1.83 augustss int h = HASH(sitd->physaddr);
1874 1.83 augustss
1875 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1876 1.254.2.18 skrll
1877 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1878 1.224 mrg
1879 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1880 1.254.2.18 skrll 0, 0);
1881 1.83 augustss
1882 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1883 1.83 augustss }
1884 1.83 augustss
1885 1.224 mrg /* Called with USB lock held. */
1886 1.83 augustss void
1887 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1888 1.83 augustss {
1889 1.83 augustss
1890 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1891 1.254.2.18 skrll
1892 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1893 1.224 mrg
1894 1.254.2.18 skrll DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr,
1895 1.254.2.18 skrll 0, 0);
1896 1.83 augustss
1897 1.83 augustss LIST_REMOVE(sitd, hnext);
1898 1.83 augustss }
1899 1.83 augustss
1900 1.83 augustss ohci_soft_itd_t *
1901 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1902 1.83 augustss {
1903 1.83 augustss int h = HASH(a);
1904 1.83 augustss ohci_soft_itd_t *sitd;
1905 1.83 augustss
1906 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1907 1.83 augustss sitd != NULL;
1908 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1909 1.83 augustss if (sitd->physaddr == a)
1910 1.254.2.13 skrll return sitd;
1911 1.254.2.13 skrll return NULL;
1912 1.1 augustss }
1913 1.1 augustss
1914 1.1 augustss void
1915 1.91 augustss ohci_timeout(void *addr)
1916 1.1 augustss {
1917 1.254.2.25 skrll struct usbd_xfer *xfer = addr;
1918 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1919 1.254.2.76 skrll bool timeout = false;
1920 1.114 augustss
1921 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1922 1.254.2.73 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1923 1.114 augustss
1924 1.254.2.76 skrll mutex_enter(&sc->sc_lock);
1925 1.116 augustss if (sc->sc_dying) {
1926 1.254.2.25 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1927 1.224 mrg mutex_exit(&sc->sc_lock);
1928 1.116 augustss return;
1929 1.116 augustss }
1930 1.116 augustss
1931 1.254.2.76 skrll if (xfer->ux_status != USBD_CANCELLED) {
1932 1.254.2.76 skrll xfer->ux_status = USBD_TIMEOUT;
1933 1.254.2.76 skrll timeout = true;
1934 1.254.2.76 skrll }
1935 1.254.2.76 skrll mutex_exit(&sc->sc_lock);
1936 1.254.2.78 skrll
1937 1.254.2.76 skrll if (timeout) {
1938 1.254.2.76 skrll /* Execute the abort in a process context. */
1939 1.254.2.76 skrll usb_init_task(&xfer->ux_aborttask, ohci_timeout_task, addr,
1940 1.254.2.76 skrll USB_TASKQ_MPSAFE);
1941 1.254.2.76 skrll usb_add_task(xfer->ux_pipe->up_dev, &xfer->ux_aborttask,
1942 1.254.2.76 skrll USB_TASKQ_HC);
1943 1.254.2.76 skrll }
1944 1.114 augustss }
1945 1.114 augustss
1946 1.114 augustss void
1947 1.114 augustss ohci_timeout_task(void *addr)
1948 1.114 augustss {
1949 1.254.2.19 skrll struct usbd_xfer *xfer = addr;
1950 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1951 1.1 augustss
1952 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1953 1.254.2.18 skrll
1954 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
1955 1.45 augustss
1956 1.224 mrg mutex_enter(&sc->sc_lock);
1957 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1958 1.224 mrg mutex_exit(&sc->sc_lock);
1959 1.1 augustss }
1960 1.1 augustss
1961 1.52 augustss #ifdef OHCI_DEBUG
1962 1.1 augustss void
1963 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1964 1.1 augustss {
1965 1.254.2.34 skrll for (; std; std = std->nexttd) {
1966 1.168 augustss ohci_dump_td(sc, std);
1967 1.254.2.34 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
1968 1.254.2.34 skrll "std %p next %p", std, std->nexttd);
1969 1.254.2.34 skrll }
1970 1.1 augustss }
1971 1.1 augustss
1972 1.1 augustss void
1973 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1974 1.1 augustss {
1975 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1976 1.92 tv
1977 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1978 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1979 1.254.2.18 skrll
1980 1.254.2.18 skrll uint32_t flags = O32TOH(std->td.td_flags);
1981 1.254.2.40 skrll DPRINTF("TD(%p) at 0x%08lx:", std, (u_long)std->physaddr, 0, 0);
1982 1.254.2.18 skrll DPRINTF(" round=%d DP=%x DI=%x T=%x",
1983 1.254.2.18 skrll !!(flags & OHCI_TD_R),
1984 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1985 1.254.2.18 skrll OHCI_TD_GET_DI(flags),
1986 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1987 1.254.2.18 skrll DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags),
1988 1.254.2.18 skrll 0, 0);
1989 1.254.2.47 skrll DPRINTF(" td_cbp=0x%08lx td_nexttd=0x%08lx td_be=0x%08lx",
1990 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1991 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1992 1.254.2.18 skrll (u_long)O32TOH(std->td.td_be), 0);
1993 1.1 augustss }
1994 1.1 augustss
1995 1.1 augustss void
1996 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1997 1.83 augustss {
1998 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1999 1.83 augustss
2000 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
2001 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2002 1.254.2.18 skrll
2003 1.254.2.18 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
2004 1.254.2.40 skrll DPRINTF("ITD(%p) at 0x%08lx", sitd, (u_long)sitd->physaddr, 0, 0);
2005 1.254.2.18 skrll DPRINTF(" sf=%d di=%d fc=%d cc=%d",
2006 1.254.2.18 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
2007 1.254.2.18 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
2008 1.254.2.18 skrll DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x",
2009 1.254.2.18 skrll O32TOH(sitd->itd.itd_bp0),
2010 1.254.2.18 skrll O32TOH(sitd->itd.itd_nextitd),
2011 1.254.2.18 skrll O32TOH(sitd->itd.itd_be), 0);
2012 1.254.2.18 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
2013 1.254.2.18 skrll DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x "
2014 1.254.2.18 skrll "offs[2] = 0x%04x offs[3] = 0x%04x",
2015 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[0]),
2016 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[1]),
2017 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[2]),
2018 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[3]));
2019 1.254.2.18 skrll DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x "
2020 1.254.2.18 skrll "offs[6] = 0x%04x offs[7] = 0x%04x",
2021 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[4]),
2022 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[5]),
2023 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[6]),
2024 1.254.2.18 skrll O16TOH(sitd->itd.itd_offset[7]));
2025 1.83 augustss }
2026 1.83 augustss
2027 1.83 augustss void
2028 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
2029 1.83 augustss {
2030 1.83 augustss for (; sitd; sitd = sitd->nextitd)
2031 1.168 augustss ohci_dump_itd(sc, sitd);
2032 1.83 augustss }
2033 1.83 augustss
2034 1.83 augustss void
2035 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2036 1.1 augustss {
2037 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2038 1.92 tv
2039 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2040 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2041 1.254.2.18 skrll
2042 1.254.2.18 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
2043 1.254.2.18 skrll DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0);
2044 1.254.2.18 skrll DPRINTF(" addr=%d endpt=%d maxp=%d",
2045 1.254.2.18 skrll OHCI_ED_GET_FA(flags),
2046 1.254.2.18 skrll OHCI_ED_GET_EN(flags),
2047 1.254.2.18 skrll OHCI_ED_GET_MAXP(flags),
2048 1.254.2.18 skrll 0);
2049 1.254.2.18 skrll DPRINTF(" dir=%d speed=%d skip=%d iso=%d",
2050 1.254.2.18 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
2051 1.254.2.18 skrll !!(flags & OHCI_ED_SPEED),
2052 1.254.2.18 skrll !!(flags & OHCI_ED_SKIP),
2053 1.254.2.18 skrll !!(flags & OHCI_ED_FORMAT_ISO));
2054 1.254.2.18 skrll DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp),
2055 1.254.2.18 skrll 0, 0, 0);
2056 1.254.2.18 skrll DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d",
2057 1.254.2.18 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
2058 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
2059 1.254.2.18 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2060 1.1 augustss }
2061 1.1 augustss #endif
2062 1.1 augustss
2063 1.1 augustss usbd_status
2064 1.254.2.19 skrll ohci_open(struct usbd_pipe *pipe)
2065 1.1 augustss {
2066 1.254.2.19 skrll struct usbd_device *dev = pipe->up_dev;
2067 1.254.2.12 skrll struct usbd_bus *bus = dev->ud_bus;
2068 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2069 1.254.2.7 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2070 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2071 1.254.2.7 skrll uint8_t addr = dev->ud_addr;
2072 1.254.2.1 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2073 1.1 augustss ohci_soft_ed_t *sed;
2074 1.1 augustss ohci_soft_td_t *std;
2075 1.60 augustss ohci_soft_itd_t *sitd;
2076 1.60 augustss ohci_physaddr_t tdphys;
2077 1.254.2.1 skrll uint32_t fmt;
2078 1.224 mrg usbd_status err = USBD_NOMEM;
2079 1.64 augustss int ival;
2080 1.1 augustss
2081 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2082 1.254.2.18 skrll DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr,
2083 1.254.2.18 skrll ed->bEndpointAddress, bus->ub_rhaddr);
2084 1.81 augustss
2085 1.224 mrg if (sc->sc_dying) {
2086 1.241 skrll return USBD_IOERROR;
2087 1.224 mrg }
2088 1.116 augustss
2089 1.90 thorpej std = NULL;
2090 1.90 thorpej sed = NULL;
2091 1.90 thorpej
2092 1.254.2.12 skrll if (addr == bus->ub_rhaddr) {
2093 1.1 augustss switch (ed->bEndpointAddress) {
2094 1.1 augustss case USB_CONTROL_ENDPOINT:
2095 1.254.2.12 skrll pipe->up_methods = &roothub_ctrl_methods;
2096 1.1 augustss break;
2097 1.254.2.12 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2098 1.254.2.7 skrll pipe->up_methods = &ohci_root_intr_methods;
2099 1.1 augustss break;
2100 1.1 augustss default:
2101 1.224 mrg err = USBD_INVAL;
2102 1.241 skrll goto bad;
2103 1.1 augustss }
2104 1.1 augustss } else {
2105 1.1 augustss sed = ohci_alloc_sed(sc);
2106 1.53 augustss if (sed == NULL)
2107 1.241 skrll goto bad;
2108 1.1 augustss opipe->sed = sed;
2109 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2110 1.60 augustss sitd = ohci_alloc_sitd(sc);
2111 1.127 augustss if (sitd == NULL)
2112 1.241 skrll goto bad;
2113 1.241 skrll
2114 1.60 augustss opipe->tail.itd = sitd;
2115 1.254.2.76 skrll sitd->held = &opipe->tail.itd;
2116 1.76 tsutsui tdphys = sitd->physaddr;
2117 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2118 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2119 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2120 1.83 augustss else
2121 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2122 1.60 augustss } else {
2123 1.60 augustss std = ohci_alloc_std(sc);
2124 1.127 augustss if (std == NULL)
2125 1.241 skrll goto bad;
2126 1.241 skrll
2127 1.60 augustss opipe->tail.td = std;
2128 1.254.2.76 skrll std->held = &opipe->tail.td;
2129 1.76 tsutsui tdphys = std->physaddr;
2130 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2131 1.60 augustss }
2132 1.168 augustss sed->ed.ed_flags = HTOO32(
2133 1.120 augustss OHCI_ED_SET_FA(addr) |
2134 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2135 1.254.2.7 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2136 1.109 augustss fmt |
2137 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2138 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2139 1.254.2.7 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2140 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2141 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2142 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2143 1.1 augustss
2144 1.60 augustss switch (xfertype) {
2145 1.1 augustss case UE_CONTROL:
2146 1.254.2.7 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2147 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2148 1.120 augustss sizeof(usb_device_request_t),
2149 1.254.2.21 skrll 0, &opipe->ctrl.reqdma);
2150 1.53 augustss if (err)
2151 1.1 augustss goto bad;
2152 1.224 mrg mutex_enter(&sc->sc_lock);
2153 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2154 1.224 mrg mutex_exit(&sc->sc_lock);
2155 1.1 augustss break;
2156 1.1 augustss case UE_INTERRUPT:
2157 1.254.2.7 skrll pipe->up_methods = &ohci_device_intr_methods;
2158 1.254.2.7 skrll ival = pipe->up_interval;
2159 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2160 1.64 augustss ival = ed->bInterval;
2161 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2162 1.226 skrll if (err)
2163 1.226 skrll goto bad;
2164 1.226 skrll break;
2165 1.1 augustss case UE_ISOCHRONOUS:
2166 1.254.2.59 skrll pipe->up_serialise = false;
2167 1.254.2.7 skrll pipe->up_methods = &ohci_device_isoc_methods;
2168 1.254.2.13 skrll return ohci_setup_isoc(pipe);
2169 1.1 augustss case UE_BULK:
2170 1.254.2.7 skrll pipe->up_methods = &ohci_device_bulk_methods;
2171 1.224 mrg mutex_enter(&sc->sc_lock);
2172 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2173 1.224 mrg mutex_exit(&sc->sc_lock);
2174 1.3 augustss break;
2175 1.1 augustss }
2176 1.1 augustss }
2177 1.224 mrg
2178 1.224 mrg return USBD_NORMAL_COMPLETION;
2179 1.1 augustss
2180 1.1 augustss bad:
2181 1.241 skrll if (std != NULL) {
2182 1.90 thorpej ohci_free_std(sc, std);
2183 1.241 skrll }
2184 1.90 thorpej if (sed != NULL)
2185 1.90 thorpej ohci_free_sed(sc, sed);
2186 1.224 mrg return err;
2187 1.120 augustss
2188 1.1 augustss }
2189 1.1 augustss
2190 1.1 augustss /*
2191 1.34 augustss * Close a reqular pipe.
2192 1.34 augustss * Assumes that there are no pending transactions.
2193 1.34 augustss */
2194 1.34 augustss void
2195 1.254.2.19 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2196 1.34 augustss {
2197 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2198 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2199 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2200 1.34 augustss
2201 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2202 1.224 mrg
2203 1.34 augustss #ifdef DIAGNOSTIC
2204 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2205 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2206 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2207 1.34 augustss ohci_soft_td_t *std;
2208 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2209 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2210 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2211 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2212 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2213 1.34 augustss pipe, std);
2214 1.229 christos #ifdef OHCI_DEBUG
2215 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2216 1.168 augustss ohci_dump_ed(sc, sed);
2217 1.106 augustss if (std)
2218 1.168 augustss ohci_dump_td(sc, std);
2219 1.106 augustss #endif
2220 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2221 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2222 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2223 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2224 1.34 augustss }
2225 1.34 augustss #endif
2226 1.224 mrg ohci_rem_ed(sc, sed, head);
2227 1.133 toshii /* Make sure the host controller is not touching this ED */
2228 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2229 1.254.2.7 skrll pipe->up_endpoint->ue_toggle =
2230 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2231 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
2232 1.34 augustss }
2233 1.34 augustss
2234 1.120 augustss /*
2235 1.254.2.80 skrll * Cancel or timeout a device request. We have two cases to deal with
2236 1.254.2.76 skrll *
2237 1.254.2.76 skrll * 1) A driver wants to stop scheduled or inflight transfers
2238 1.254.2.76 skrll * 2) A transfer has timed out
2239 1.254.2.76 skrll *
2240 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2241 1.254.2.76 skrll * have (partially) happened since the hardware runs concurrently.
2242 1.254.2.76 skrll *
2243 1.254.2.76 skrll * Transfer state is protected by the bus lock and we set the transfer status
2244 1.254.2.76 skrll * as soon as either of the above happens (with bus lock held).
2245 1.254.2.76 skrll *
2246 1.254.2.76 skrll * Then we arrange for the hardware to tells us that it is not still
2247 1.254.2.76 skrll * processing the TDs by setting the sKip bit and requesting a SOF interrupt
2248 1.254.2.76 skrll *
2249 1.254.2.76 skrll * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if
2250 1.254.2.76 skrll * they've been processed and either
2251 1.254.2.76 skrll * a) if they're unused recover them for later use, or
2252 1.254.2.76 skrll * b) if they've been used allocate new TD/iTDs to replace those
2253 1.254.2.76 skrll * used. The softint handler will free the old ones.
2254 1.34 augustss */
2255 1.34 augustss void
2256 1.254.2.19 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2257 1.34 augustss {
2258 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2259 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2260 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2261 1.106 augustss ohci_soft_td_t *p, *n;
2262 1.106 augustss ohci_physaddr_t headp;
2263 1.224 mrg int hit;
2264 1.159 augustss int wake;
2265 1.34 augustss
2266 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2267 1.254.2.18 skrll DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0);
2268 1.34 augustss
2269 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2270 1.254.2.3 skrll ASSERT_SLEEPABLE();
2271 1.224 mrg
2272 1.116 augustss if (sc->sc_dying) {
2273 1.116 augustss /* If we're dying, just do the software part. */
2274 1.254.2.83 skrll xfer->ux_status = status;
2275 1.254.2.7 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2276 1.116 augustss usb_transfer_complete(xfer);
2277 1.170 christos return;
2278 1.116 augustss }
2279 1.116 augustss
2280 1.106 augustss /*
2281 1.159 augustss * If an abort is already in progress then just wait for it to
2282 1.159 augustss * complete and return.
2283 1.159 augustss */
2284 1.254.2.7 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2285 1.254.2.18 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2286 1.159 augustss #ifdef DIAGNOSTIC
2287 1.159 augustss if (status == USBD_TIMEOUT)
2288 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2289 1.159 augustss #endif
2290 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2291 1.254.2.7 skrll xfer->ux_status = status;
2292 1.254.2.18 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2293 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2294 1.254.2.7 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2295 1.254.2.7 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2296 1.224 mrg goto done;
2297 1.159 augustss }
2298 1.254.2.7 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2299 1.159 augustss
2300 1.159 augustss /*
2301 1.254.2.76 skrll * Step 1: When cancelling a transfer make sure the timeout handler
2302 1.254.2.76 skrll * didn't run or ran to the end and saw the USBD_CANCELLED status.
2303 1.254.2.76 skrll * Otherwise we must have got here via a timeout.
2304 1.254.2.76 skrll */
2305 1.254.2.76 skrll if (status == USBD_CANCELLED) {
2306 1.254.2.76 skrll xfer->ux_status = status;
2307 1.254.2.76 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2308 1.254.2.76 skrll } else {
2309 1.254.2.76 skrll KASSERT(xfer->ux_status == USBD_TIMEOUT);
2310 1.254.2.76 skrll }
2311 1.254.2.76 skrll
2312 1.254.2.76 skrll /*
2313 1.254.2.76 skrll * Step 2: Unless the endpoint is already halted, we set the endpoint
2314 1.254.2.76 skrll * descriptor sKip bit and wait for hardware to complete processing.
2315 1.254.2.76 skrll *
2316 1.254.2.76 skrll * This includes ensuring that any TDs of the transfer that got onto
2317 1.254.2.76 skrll * the done list are also removed. We ensure this by waiting for
2318 1.254.2.76 skrll * both a WDH and SOF interrupt.
2319 1.106 augustss */
2320 1.254.2.18 skrll DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0);
2321 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2322 1.195 bouyer sizeof(sed->ed.ed_flags),
2323 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2324 1.254.2.76 skrll if (!(sed->ed.ed_flags & OHCI_HALTED)) {
2325 1.254.2.76 skrll /* force hardware skip */
2326 1.254.2.76 skrll DPRINTFN(1, "pausing ed=%p", sed, 0, 0, 0);
2327 1.254.2.76 skrll sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2328 1.254.2.76 skrll usb_syncmem(&sed->dma,
2329 1.254.2.76 skrll sed->offs + offsetof(ohci_ed_t, ed_flags),
2330 1.254.2.76 skrll sizeof(sed->ed.ed_flags),
2331 1.254.2.76 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2332 1.34 augustss
2333 1.254.2.76 skrll DPRINTFN(10, "WDH %p xfer %p", sc, xfer, 0, 0);
2334 1.254.2.76 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2335 1.254.2.76 skrll ox->ox_abintrs = OHCI_SF;
2336 1.254.2.76 skrll TAILQ_INSERT_TAIL(&sc->sc_abortingxfers, ox, ox_abnext);
2337 1.254.2.76 skrll
2338 1.254.2.76 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_SF);
2339 1.254.2.76 skrll sc->sc_eintrs |= OHCI_SF;
2340 1.254.2.76 skrll OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_SF);
2341 1.254.2.76 skrll /*
2342 1.254.2.76 skrll * Step 2: Wait until we know hardware has finished any possible
2343 1.254.2.76 skrll * use of the xfer.
2344 1.254.2.76 skrll */
2345 1.254.2.76 skrll while (ox->ox_abintrs != 0) {
2346 1.254.2.76 skrll DPRINTFN(10, "WDH %p xfer %p intrs %#x", sc, xfer,
2347 1.254.2.76 skrll ox->ox_abintrs, 0);
2348 1.254.2.76 skrll cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2349 1.254.2.76 skrll }
2350 1.254.2.76 skrll } else {
2351 1.254.2.76 skrll DPRINTFN(1, "halted ed=%p", sed, 0, 0, 0);
2352 1.254.2.76 skrll }
2353 1.119 augustss
2354 1.120 augustss /*
2355 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2356 1.106 augustss * The complication here is that the hardware may have executed
2357 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2358 1.106 augustss * the TDs of this xfer we check if the hardware points to
2359 1.106 augustss * any of them.
2360 1.106 augustss */
2361 1.254.2.7 skrll p = xfer->ux_hcpriv;
2362 1.254.2.24 skrll KASSERT(p);
2363 1.254.2.24 skrll
2364 1.106 augustss #ifdef OHCI_DEBUG
2365 1.254.2.18 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2366 1.254.2.18 skrll
2367 1.254.2.39 skrll if (ohcidebug >= 2) {
2368 1.254.2.18 skrll DPRINTF("sed:", 0, 0, 0, 0);
2369 1.168 augustss ohci_dump_ed(sc, sed);
2370 1.168 augustss ohci_dump_tds(sc, p);
2371 1.106 augustss }
2372 1.254.2.18 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2373 1.106 augustss #endif
2374 1.254.2.76 skrll
2375 1.254.2.81 skrll #define OHCI_CC_ACCESSED_P(x) \
2376 1.254.2.81 skrll (((x) & OHCI_CC_NOT_ACCESSED_MASK) != OHCI_CC_NOT_ACCESSED)
2377 1.254.2.81 skrll
2378 1.254.2.81 skrll
2379 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2380 1.106 augustss hit = 0;
2381 1.53 augustss for (; p->xfer == xfer; p = n) {
2382 1.106 augustss hit |= headp == p->physaddr;
2383 1.38 augustss n = p->nexttd;
2384 1.254.2.76 skrll
2385 1.254.2.76 skrll int cc = OHCI_TD_GET_CC(O32TOH(p->td.td_flags));
2386 1.254.2.76 skrll if (!OHCI_CC_ACCESSED_P(cc)) {
2387 1.254.2.76 skrll ohci_hash_rem_td(sc, p);
2388 1.254.2.76 skrll continue;
2389 1.254.2.76 skrll }
2390 1.254.2.76 skrll DPRINTFN(10, "std=%p has been touched by HC", p, 0, 0, 0);
2391 1.254.2.76 skrll
2392 1.254.2.76 skrll mutex_exit(&sc->sc_lock);
2393 1.254.2.76 skrll ohci_soft_td_t *std = ohci_alloc_std(sc);
2394 1.254.2.76 skrll if (std == NULL) {
2395 1.254.2.76 skrll /* XXX What to do??? */
2396 1.254.2.76 skrll panic("hmm");
2397 1.254.2.76 skrll }
2398 1.254.2.76 skrll mutex_enter(&sc->sc_lock);
2399 1.254.2.76 skrll
2400 1.254.2.76 skrll DPRINTFN(10, "new std=%p now held at %p", std, p->held, 0, 0);
2401 1.254.2.76 skrll *(p->held) = std;
2402 1.254.2.76 skrll std->held = p->held;
2403 1.254.2.76 skrll std->xfer = xfer;
2404 1.254.2.76 skrll p->held = NULL;
2405 1.34 augustss }
2406 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2407 1.106 augustss if (hit) {
2408 1.254.2.18 skrll DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr,
2409 1.254.2.18 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2410 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2411 1.195 bouyer usb_syncmem(&sed->dma,
2412 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2413 1.195 bouyer sizeof(sed->ed.ed_headp),
2414 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2415 1.106 augustss } else {
2416 1.254.2.18 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2417 1.106 augustss }
2418 1.34 augustss
2419 1.106 augustss /*
2420 1.106 augustss * Step 4: Turn on hardware again.
2421 1.106 augustss */
2422 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2423 1.195 bouyer sizeof(sed->ed.ed_flags),
2424 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2425 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2426 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2427 1.195 bouyer sizeof(sed->ed.ed_flags),
2428 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2429 1.38 augustss
2430 1.106 augustss /*
2431 1.106 augustss * Step 5: Execute callback.
2432 1.106 augustss */
2433 1.254.2.7 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2434 1.254.2.7 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2435 1.53 augustss usb_transfer_complete(xfer);
2436 1.159 augustss if (wake)
2437 1.254.2.7 skrll cv_broadcast(&xfer->ux_hccv);
2438 1.38 augustss
2439 1.224 mrg done:
2440 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2441 1.34 augustss }
2442 1.34 augustss
2443 1.34 augustss /*
2444 1.1 augustss * Data structures and routines to emulate the root hub.
2445 1.1 augustss */
2446 1.254.2.12 skrll Static int
2447 1.254.2.12 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2448 1.254.2.12 skrll void *buf, int buflen)
2449 1.17 augustss {
2450 1.254.2.25 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2451 1.1 augustss usb_port_status_t ps;
2452 1.254.2.12 skrll uint16_t len, value, index;
2453 1.254.2.12 skrll int l, totlen = 0;
2454 1.254.2.12 skrll int port, i;
2455 1.254.2.1 skrll uint32_t v;
2456 1.1 augustss
2457 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2458 1.254.2.18 skrll
2459 1.83 augustss if (sc->sc_dying)
2460 1.254.2.12 skrll return -1;
2461 1.1 augustss
2462 1.254.2.18 skrll DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType,
2463 1.254.2.18 skrll req->bRequest, 0, 0);
2464 1.1 augustss
2465 1.1 augustss len = UGETW(req->wLength);
2466 1.1 augustss value = UGETW(req->wValue);
2467 1.1 augustss index = UGETW(req->wIndex);
2468 1.43 augustss
2469 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2470 1.254.2.12 skrll switch (C(req->bRequest, req->bmRequestType)) {
2471 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2472 1.254.2.18 skrll DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0);
2473 1.171 christos if (len == 0)
2474 1.171 christos break;
2475 1.254.2.12 skrll switch (value) {
2476 1.254.2.12 skrll case C(0, UDESC_DEVICE): {
2477 1.254.2.12 skrll usb_device_descriptor_t devd;
2478 1.254.2.12 skrll
2479 1.254.2.12 skrll totlen = min(buflen, sizeof(devd));
2480 1.254.2.12 skrll memcpy(&devd, buf, totlen);
2481 1.254.2.12 skrll USETW(devd.idVendor, sc->sc_id_vendor);
2482 1.254.2.12 skrll memcpy(buf, &devd, totlen);
2483 1.1 augustss break;
2484 1.254.2.12 skrll }
2485 1.254.2.12 skrll case C(1, UDESC_STRING):
2486 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2487 1.254.2.12 skrll /* Vendor */
2488 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, sc->sc_vendor);
2489 1.254.2.12 skrll break;
2490 1.254.2.12 skrll case C(2, UDESC_STRING):
2491 1.254.2.12 skrll /* Product */
2492 1.254.2.12 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2493 1.1 augustss break;
2494 1.254.2.12 skrll #undef sd
2495 1.1 augustss default:
2496 1.254.2.12 skrll /* default from usbroothub */
2497 1.254.2.12 skrll return buflen;
2498 1.1 augustss }
2499 1.1 augustss break;
2500 1.254.2.12 skrll
2501 1.1 augustss /* Hub requests */
2502 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2503 1.1 augustss break;
2504 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2505 1.254.2.18 skrll DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d",
2506 1.254.2.18 skrll index, value, 0, 0);
2507 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2508 1.254.2.12 skrll return -1;
2509 1.1 augustss }
2510 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2511 1.1 augustss switch(value) {
2512 1.1 augustss case UHF_PORT_ENABLE:
2513 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2514 1.1 augustss break;
2515 1.1 augustss case UHF_PORT_SUSPEND:
2516 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2517 1.1 augustss break;
2518 1.1 augustss case UHF_PORT_POWER:
2519 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2520 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2521 1.1 augustss break;
2522 1.1 augustss case UHF_C_PORT_CONNECTION:
2523 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2524 1.1 augustss break;
2525 1.1 augustss case UHF_C_PORT_ENABLE:
2526 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2527 1.1 augustss break;
2528 1.1 augustss case UHF_C_PORT_SUSPEND:
2529 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2530 1.1 augustss break;
2531 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2532 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2533 1.1 augustss break;
2534 1.1 augustss case UHF_C_PORT_RESET:
2535 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2536 1.1 augustss break;
2537 1.1 augustss default:
2538 1.254.2.12 skrll return -1;
2539 1.1 augustss }
2540 1.1 augustss switch(value) {
2541 1.1 augustss case UHF_C_PORT_CONNECTION:
2542 1.1 augustss case UHF_C_PORT_ENABLE:
2543 1.1 augustss case UHF_C_PORT_SUSPEND:
2544 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2545 1.1 augustss case UHF_C_PORT_RESET:
2546 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2547 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2548 1.157 mycroft ohci_rhsc_enable(sc);
2549 1.1 augustss break;
2550 1.1 augustss default:
2551 1.1 augustss break;
2552 1.1 augustss }
2553 1.1 augustss break;
2554 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2555 1.171 christos if (len == 0)
2556 1.171 christos break;
2557 1.146 toshii if ((value & 0xff) != 0) {
2558 1.254.2.12 skrll return -1;
2559 1.1 augustss }
2560 1.254.2.12 skrll usb_hub_descriptor_t hubd;
2561 1.254.2.12 skrll
2562 1.254.2.12 skrll totlen = min(buflen, sizeof(hubd));
2563 1.254.2.12 skrll memcpy(&hubd, buf, totlen);
2564 1.254.2.12 skrll
2565 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2566 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2567 1.15 augustss USETW(hubd.wHubCharacteristics,
2568 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2569 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2570 1.1 augustss /* XXX overcurrent */
2571 1.1 augustss );
2572 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2573 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2574 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2575 1.254.2.1 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2576 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2577 1.254.2.12 skrll totlen = min(totlen, hubd.bDescLength);
2578 1.254.2.12 skrll memcpy(buf, &hubd, totlen);
2579 1.1 augustss break;
2580 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2581 1.1 augustss if (len != 4) {
2582 1.254.2.12 skrll return -1;
2583 1.1 augustss }
2584 1.1 augustss memset(buf, 0, len); /* ? XXX */
2585 1.1 augustss totlen = len;
2586 1.1 augustss break;
2587 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2588 1.254.2.18 skrll DPRINTFN(8, "get port status i=%d", index, 0, 0, 0);
2589 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2590 1.254.2.12 skrll return -1;
2591 1.1 augustss }
2592 1.1 augustss if (len != 4) {
2593 1.254.2.12 skrll return -1;
2594 1.254.2.56 skrll }
2595 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2596 1.254.2.18 skrll DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0);
2597 1.1 augustss USETW(ps.wPortStatus, v);
2598 1.1 augustss USETW(ps.wPortChange, v >> 16);
2599 1.254.2.12 skrll totlen = min(len, sizeof(ps));
2600 1.254.2.12 skrll memcpy(buf, &ps, totlen);
2601 1.1 augustss break;
2602 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2603 1.254.2.12 skrll return -1;
2604 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2605 1.1 augustss break;
2606 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2607 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2608 1.254.2.12 skrll return -1;
2609 1.1 augustss }
2610 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2611 1.1 augustss switch(value) {
2612 1.1 augustss case UHF_PORT_ENABLE:
2613 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2614 1.1 augustss break;
2615 1.1 augustss case UHF_PORT_SUSPEND:
2616 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2617 1.1 augustss break;
2618 1.1 augustss case UHF_PORT_RESET:
2619 1.254.2.18 skrll DPRINTFN(5, "reset port %d", index, 0, 0, 0);
2620 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2621 1.110 augustss for (i = 0; i < 5; i++) {
2622 1.110 augustss usb_delay_ms(&sc->sc_bus,
2623 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2624 1.116 augustss if (sc->sc_dying) {
2625 1.254.2.12 skrll return -1;
2626 1.116 augustss }
2627 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2628 1.1 augustss break;
2629 1.1 augustss }
2630 1.254.2.18 skrll DPRINTFN(8, "port %d reset, status = 0x%04x", index,
2631 1.254.2.18 skrll OREAD4(sc, port), 0, 0);
2632 1.1 augustss break;
2633 1.1 augustss case UHF_PORT_POWER:
2634 1.254.2.18 skrll DPRINTFN(2, "set port power %d", index, 0, 0, 0);
2635 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2636 1.1 augustss break;
2637 1.1 augustss default:
2638 1.254.2.12 skrll return -1;
2639 1.1 augustss }
2640 1.1 augustss break;
2641 1.1 augustss default:
2642 1.254.2.12 skrll /* default from usbroothub */
2643 1.254.2.12 skrll return buflen;
2644 1.1 augustss }
2645 1.1 augustss
2646 1.254.2.12 skrll return totlen;
2647 1.1 augustss }
2648 1.1 augustss
2649 1.82 augustss Static usbd_status
2650 1.254.2.19 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2651 1.1 augustss {
2652 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2653 1.53 augustss usbd_status err;
2654 1.17 augustss
2655 1.46 augustss /* Insert last in queue. */
2656 1.224 mrg mutex_enter(&sc->sc_lock);
2657 1.53 augustss err = usb_insert_transfer(xfer);
2658 1.224 mrg mutex_exit(&sc->sc_lock);
2659 1.53 augustss if (err)
2660 1.254.2.13 skrll return err;
2661 1.46 augustss
2662 1.46 augustss /* Pipe isn't running, start first */
2663 1.254.2.13 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2664 1.17 augustss }
2665 1.17 augustss
2666 1.82 augustss Static usbd_status
2667 1.254.2.19 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2668 1.17 augustss {
2669 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2670 1.1 augustss
2671 1.83 augustss if (sc->sc_dying)
2672 1.254.2.13 skrll return USBD_IOERROR;
2673 1.83 augustss
2674 1.224 mrg mutex_enter(&sc->sc_lock);
2675 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2676 1.53 augustss sc->sc_intrxfer = xfer;
2677 1.224 mrg mutex_exit(&sc->sc_lock);
2678 1.1 augustss
2679 1.254.2.13 skrll return USBD_IN_PROGRESS;
2680 1.1 augustss }
2681 1.1 augustss
2682 1.3 augustss /* Abort a root interrupt request. */
2683 1.82 augustss Static void
2684 1.254.2.19 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2685 1.1 augustss {
2686 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2687 1.224 mrg
2688 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2689 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2690 1.53 augustss
2691 1.252 skrll sc->sc_intrxfer = NULL;
2692 1.252 skrll
2693 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
2694 1.53 augustss usb_transfer_complete(xfer);
2695 1.1 augustss }
2696 1.1 augustss
2697 1.1 augustss /* Close the root pipe. */
2698 1.82 augustss Static void
2699 1.254.2.19 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2700 1.1 augustss {
2701 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2702 1.120 augustss
2703 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2704 1.224 mrg
2705 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2706 1.34 augustss
2707 1.53 augustss sc->sc_intrxfer = NULL;
2708 1.1 augustss }
2709 1.1 augustss
2710 1.1 augustss /************************/
2711 1.1 augustss
2712 1.254.2.35 skrll int
2713 1.254.2.35 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2714 1.254.2.35 skrll {
2715 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2716 1.254.2.35 skrll usb_device_request_t *req = &xfer->ux_request;
2717 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2718 1.254.2.42 skrll ohci_soft_td_t *stat, *setup;
2719 1.254.2.35 skrll int isread = req->bmRequestType & UT_READ;
2720 1.254.2.35 skrll int len = xfer->ux_bufsize;
2721 1.254.2.35 skrll int err = ENOMEM;
2722 1.254.2.35 skrll
2723 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2724 1.254.2.35 skrll
2725 1.254.2.42 skrll setup = ohci_alloc_std(sc);
2726 1.254.2.42 skrll if (setup == NULL) {
2727 1.254.2.35 skrll goto bad1;
2728 1.254.2.35 skrll }
2729 1.254.2.42 skrll stat = ohci_alloc_std(sc);
2730 1.254.2.42 skrll if (stat == NULL) {
2731 1.254.2.35 skrll goto bad2;
2732 1.254.2.35 skrll }
2733 1.254.2.35 skrll
2734 1.254.2.42 skrll ox->ox_setup = setup;
2735 1.254.2.35 skrll ox->ox_stat = stat;
2736 1.254.2.35 skrll ox->ox_nstd = 0;
2737 1.254.2.76 skrll setup->held = &ox->ox_setup;
2738 1.254.2.76 skrll stat->held = &ox->ox_stat;
2739 1.254.2.76 skrll
2740 1.254.2.76 skrll DPRINTFN(10, "xfer=%p setup=%p held at %p", ox, setup, setup->held, 0);
2741 1.254.2.76 skrll DPRINTFN(10, "xfer=%p stat= %p held at %p", ox, stat, stat->held, 0);
2742 1.254.2.35 skrll
2743 1.254.2.35 skrll /* Set up data transaction */
2744 1.254.2.35 skrll if (len != 0) {
2745 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2746 1.254.2.35 skrll if (err) {
2747 1.254.2.35 skrll goto bad3;
2748 1.254.2.35 skrll }
2749 1.254.2.35 skrll }
2750 1.254.2.35 skrll return 0;
2751 1.254.2.35 skrll
2752 1.254.2.35 skrll bad3:
2753 1.254.2.35 skrll ohci_free_std(sc, stat);
2754 1.254.2.42 skrll bad2:
2755 1.254.2.42 skrll ohci_free_std(sc, setup);
2756 1.254.2.35 skrll bad1:
2757 1.254.2.35 skrll return err;
2758 1.254.2.35 skrll }
2759 1.254.2.35 skrll
2760 1.254.2.35 skrll void
2761 1.254.2.35 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2762 1.254.2.35 skrll {
2763 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2764 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2765 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2766 1.254.2.35 skrll
2767 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2768 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
2769 1.254.2.35 skrll
2770 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2771 1.254.2.42 skrll if (ox->ox_setup != opipe->tail.td) {
2772 1.254.2.42 skrll ohci_free_std_locked(sc, ox->ox_setup);
2773 1.254.2.35 skrll }
2774 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2775 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2776 1.254.2.35 skrll if (std == NULL)
2777 1.254.2.35 skrll break;
2778 1.254.2.35 skrll ohci_free_std_locked(sc, std);
2779 1.254.2.35 skrll }
2780 1.254.2.35 skrll ohci_free_std_locked(sc, ox->ox_stat);
2781 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
2782 1.254.2.35 skrll
2783 1.254.2.35 skrll if (ox->ox_nstd) {
2784 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2785 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
2786 1.254.2.35 skrll }
2787 1.254.2.35 skrll }
2788 1.254.2.35 skrll
2789 1.82 augustss Static usbd_status
2790 1.254.2.19 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2791 1.1 augustss {
2792 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2793 1.53 augustss usbd_status err;
2794 1.17 augustss
2795 1.46 augustss /* Insert last in queue. */
2796 1.224 mrg mutex_enter(&sc->sc_lock);
2797 1.53 augustss err = usb_insert_transfer(xfer);
2798 1.224 mrg mutex_exit(&sc->sc_lock);
2799 1.53 augustss if (err)
2800 1.254.2.13 skrll return err;
2801 1.46 augustss
2802 1.46 augustss /* Pipe isn't running, start first */
2803 1.254.2.13 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2804 1.17 augustss }
2805 1.17 augustss
2806 1.82 augustss Static usbd_status
2807 1.254.2.19 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2808 1.17 augustss {
2809 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2810 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2811 1.254.2.27 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2812 1.254.2.27 skrll usb_device_request_t *req = &xfer->ux_request;
2813 1.254.2.27 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2814 1.254.2.27 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2815 1.254.2.27 skrll ohci_soft_ed_t *sed;
2816 1.254.2.27 skrll int isread;
2817 1.254.2.27 skrll int len;
2818 1.254.2.27 skrll
2819 1.254.2.27 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2820 1.254.2.27 skrll
2821 1.83 augustss if (sc->sc_dying)
2822 1.254.2.13 skrll return USBD_IOERROR;
2823 1.83 augustss
2824 1.254.2.24 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2825 1.1 augustss
2826 1.254.2.27 skrll isread = req->bmRequestType & UT_READ;
2827 1.254.2.27 skrll len = UGETW(req->wLength);
2828 1.254.2.27 skrll
2829 1.254.2.40 skrll DPRINTF("xfer=%p len=%d, addr=%d, endpt=%d", xfer, len, dev->ud_addr,
2830 1.254.2.40 skrll opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2831 1.254.2.40 skrll DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x",
2832 1.254.2.27 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2833 1.254.2.27 skrll UGETW(req->wIndex));
2834 1.254.2.27 skrll
2835 1.254.2.35 skrll /* Need to take lock here for pipe->tail.td */
2836 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
2837 1.254.2.35 skrll
2838 1.254.2.42 skrll /*
2839 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2840 1.254.2.42 skrll * next transfer
2841 1.254.2.42 skrll */
2842 1.254.2.27 skrll setup = opipe->tail.td;
2843 1.254.2.42 skrll opipe->tail.td = ox->ox_setup;
2844 1.254.2.42 skrll ox->ox_setup = setup;
2845 1.254.2.76 skrll setup->held = &ox->ox_setup;
2846 1.254.2.76 skrll
2847 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new setup=%p held at %p", ox, setup, setup->held, 0);
2848 1.254.2.42 skrll
2849 1.254.2.35 skrll stat = ox->ox_stat;
2850 1.254.2.27 skrll
2851 1.254.2.50 skrll /* point at sentinel */
2852 1.254.2.50 skrll tail = opipe->tail.td;
2853 1.254.2.76 skrll tail->held = &opipe->tail.td;
2854 1.254.2.27 skrll sed = opipe->sed;
2855 1.254.2.27 skrll
2856 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0);
2857 1.254.2.76 skrll
2858 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2859 1.254.2.27 skrll "address ED %d pipe %d\n",
2860 1.254.2.27 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2861 1.254.2.27 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2862 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2863 1.254.2.27 skrll "MPL ED %d pipe %d\n",
2864 1.254.2.27 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2865 1.254.2.27 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2866 1.254.2.27 skrll
2867 1.254.2.35 skrll /* next will point to data if len != 0 */
2868 1.254.2.27 skrll next = stat;
2869 1.254.2.27 skrll
2870 1.254.2.27 skrll /* Set up data transaction */
2871 1.254.2.27 skrll if (len != 0) {
2872 1.254.2.35 skrll ohci_soft_td_t *std;
2873 1.254.2.35 skrll ohci_soft_td_t *end;
2874 1.254.2.27 skrll
2875 1.254.2.35 skrll next = ox->ox_stds[0];
2876 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2877 1.254.2.27 skrll
2878 1.254.2.35 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2879 1.254.2.35 skrll end->nexttd = stat;
2880 1.254.2.35 skrll
2881 1.254.2.35 skrll usb_syncmem(&end->dma,
2882 1.254.2.35 skrll end->offs + offsetof(ohci_td_t, td_nexttd),
2883 1.254.2.35 skrll sizeof(end->td.td_nexttd),
2884 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2885 1.254.2.35 skrll
2886 1.254.2.35 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2887 1.254.2.35 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2888 1.254.2.35 skrll std = ox->ox_stds[0];
2889 1.254.2.27 skrll /* Start toggle at 1 and then use the carried toggle. */
2890 1.254.2.27 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2891 1.254.2.27 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2892 1.254.2.27 skrll usb_syncmem(&std->dma,
2893 1.254.2.27 skrll std->offs + offsetof(ohci_td_t, td_flags),
2894 1.254.2.27 skrll sizeof(std->td.td_flags),
2895 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2896 1.254.2.27 skrll }
2897 1.254.2.27 skrll
2898 1.254.2.35 skrll DPRINTFN(8, "setup %p data %p stat %p tail %p", setup,
2899 1.254.2.35 skrll (len != 0 ? ox->ox_stds[0] : NULL), stat, tail);
2900 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
2901 1.254.2.35 skrll
2902 1.254.2.27 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2903 1.254.2.27 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2904 1.254.2.27 skrll
2905 1.254.2.27 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2906 1.254.2.27 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2907 1.254.2.27 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2908 1.254.2.27 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2909 1.254.2.27 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2910 1.254.2.33 skrll setup->nexttd = next;
2911 1.254.2.27 skrll setup->len = 0;
2912 1.254.2.27 skrll setup->xfer = xfer;
2913 1.254.2.27 skrll setup->flags = 0;
2914 1.254.2.35 skrll ohci_hash_add_td(sc, setup);
2915 1.254.2.35 skrll
2916 1.254.2.27 skrll xfer->ux_hcpriv = setup;
2917 1.254.2.27 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2918 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2919 1.254.2.27 skrll
2920 1.254.2.27 skrll stat->td.td_flags = HTOO32(
2921 1.254.2.27 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2922 1.254.2.27 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2923 1.254.2.27 skrll stat->td.td_cbp = 0;
2924 1.254.2.27 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2925 1.254.2.27 skrll stat->td.td_be = 0;
2926 1.254.2.33 skrll stat->nexttd = tail;
2927 1.254.2.27 skrll stat->flags = OHCI_CALL_DONE;
2928 1.254.2.27 skrll stat->len = 0;
2929 1.254.2.27 skrll stat->xfer = xfer;
2930 1.254.2.35 skrll ohci_hash_add_td(sc, stat);
2931 1.254.2.35 skrll
2932 1.254.2.27 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2933 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2934 1.254.2.27 skrll
2935 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
2936 1.254.2.35 skrll tail->nexttd = NULL;
2937 1.254.2.35 skrll tail->xfer = NULL;
2938 1.254.2.35 skrll
2939 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2940 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2941 1.254.2.35 skrll
2942 1.254.2.27 skrll #ifdef OHCI_DEBUG
2943 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2944 1.254.2.39 skrll if (ohcidebug >= 5) {
2945 1.254.2.27 skrll ohci_dump_ed(sc, sed);
2946 1.254.2.27 skrll ohci_dump_tds(sc, setup);
2947 1.254.2.27 skrll }
2948 1.254.2.27 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2949 1.254.2.27 skrll #endif
2950 1.254.2.27 skrll
2951 1.254.2.27 skrll /* Insert ED in schedule */
2952 1.254.2.27 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2953 1.254.2.27 skrll usb_syncmem(&sed->dma,
2954 1.254.2.27 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2955 1.254.2.27 skrll sizeof(sed->ed.ed_tailp),
2956 1.254.2.27 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2957 1.254.2.27 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2958 1.254.2.27 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2959 1.254.2.27 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2960 1.254.2.27 skrll ohci_timeout, xfer);
2961 1.254.2.27 skrll }
2962 1.254.2.27 skrll
2963 1.254.2.41 skrll DPRINTF("done", 0, 0, 0, 0);
2964 1.254.2.41 skrll
2965 1.254.2.84 skrll xfer->ux_status = USBD_IN_PROGRESS;
2966 1.224 mrg mutex_exit(&sc->sc_lock);
2967 1.1 augustss
2968 1.254.2.13 skrll return USBD_IN_PROGRESS;
2969 1.1 augustss }
2970 1.1 augustss
2971 1.1 augustss /* Abort a device control request. */
2972 1.82 augustss Static void
2973 1.254.2.19 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2974 1.1 augustss {
2975 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2976 1.224 mrg
2977 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2978 1.224 mrg
2979 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2980 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
2981 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2982 1.1 augustss }
2983 1.1 augustss
2984 1.1 augustss /* Close a device control pipe. */
2985 1.82 augustss Static void
2986 1.254.2.19 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2987 1.1 augustss {
2988 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2989 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2990 1.1 augustss
2991 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2992 1.224 mrg
2993 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2994 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
2995 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2996 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
2997 1.3 augustss }
2998 1.3 augustss
2999 1.3 augustss /************************/
3000 1.37 augustss
3001 1.82 augustss Static void
3002 1.254.2.19 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
3003 1.37 augustss {
3004 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3005 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3006 1.37 augustss
3007 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
3008 1.37 augustss }
3009 1.37 augustss
3010 1.82 augustss Static void
3011 1.254.2.19 skrll ohci_noop(struct usbd_pipe *pipe)
3012 1.37 augustss {
3013 1.37 augustss }
3014 1.3 augustss
3015 1.254.2.35 skrll Static int
3016 1.254.2.35 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
3017 1.254.2.35 skrll {
3018 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3019 1.254.2.35 skrll int len = xfer->ux_bufsize;
3020 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3021 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3022 1.254.2.35 skrll int err;
3023 1.254.2.35 skrll
3024 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3025 1.254.2.35 skrll
3026 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3027 1.254.2.35 skrll
3028 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3029 1.254.2.35 skrll xfer->ux_flags);
3030 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3031 1.254.2.35 skrll
3032 1.254.2.35 skrll /* Allocate a chain of new TDs (including a new tail). */
3033 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3034 1.254.2.35 skrll if (err)
3035 1.254.2.35 skrll return err;
3036 1.254.2.35 skrll
3037 1.254.2.35 skrll return 0;
3038 1.254.2.35 skrll }
3039 1.254.2.35 skrll
3040 1.254.2.35 skrll Static void
3041 1.254.2.35 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
3042 1.254.2.35 skrll {
3043 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3044 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3045 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3046 1.254.2.35 skrll
3047 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3048 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3049 1.254.2.35 skrll
3050 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3051 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3052 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3053 1.254.2.35 skrll if (std == NULL)
3054 1.254.2.35 skrll break;
3055 1.254.2.35 skrll if (std != opipe->tail.td)
3056 1.254.2.35 skrll ohci_free_std_locked(sc, std);
3057 1.254.2.35 skrll }
3058 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3059 1.254.2.35 skrll
3060 1.254.2.35 skrll if (ox->ox_nstd) {
3061 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3062 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
3063 1.254.2.35 skrll }
3064 1.254.2.35 skrll }
3065 1.254.2.35 skrll
3066 1.82 augustss Static usbd_status
3067 1.254.2.19 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
3068 1.3 augustss {
3069 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3070 1.53 augustss usbd_status err;
3071 1.17 augustss
3072 1.46 augustss /* Insert last in queue. */
3073 1.224 mrg mutex_enter(&sc->sc_lock);
3074 1.53 augustss err = usb_insert_transfer(xfer);
3075 1.224 mrg mutex_exit(&sc->sc_lock);
3076 1.53 augustss if (err)
3077 1.254.2.13 skrll return err;
3078 1.46 augustss
3079 1.46 augustss /* Pipe isn't running, start first */
3080 1.254.2.13 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3081 1.17 augustss }
3082 1.17 augustss
3083 1.82 augustss Static usbd_status
3084 1.254.2.19 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
3085 1.17 augustss {
3086 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3087 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3088 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3089 1.254.2.35 skrll ohci_soft_td_t *last;
3090 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
3091 1.3 augustss ohci_soft_ed_t *sed;
3092 1.224 mrg int len, isread, endpt;
3093 1.3 augustss
3094 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3095 1.254.2.18 skrll
3096 1.83 augustss if (sc->sc_dying)
3097 1.254.2.13 skrll return USBD_IOERROR;
3098 1.83 augustss
3099 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3100 1.3 augustss
3101 1.254.2.7 skrll len = xfer->ux_length;
3102 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3103 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3104 1.3 augustss sed = opipe->sed;
3105 1.3 augustss
3106 1.254.2.18 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3107 1.254.2.18 skrll xfer->ux_flags);
3108 1.254.2.18 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3109 1.34 augustss
3110 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3111 1.3 augustss
3112 1.254.2.42 skrll /*
3113 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3114 1.254.2.42 skrll * next transfer
3115 1.254.2.42 skrll */
3116 1.60 augustss data = opipe->tail.td;
3117 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3118 1.254.2.35 skrll ox->ox_stds[0] = data;
3119 1.254.2.76 skrll data->held = &ox->ox_stds[0];
3120 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3121 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0);
3122 1.254.2.35 skrll
3123 1.254.2.50 skrll /* point at sentinel */
3124 1.254.2.50 skrll tail = opipe->tail.td;
3125 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3126 1.254.2.76 skrll tail->held = &opipe->tail.td;
3127 1.254.2.35 skrll tail->nexttd = NULL;
3128 1.254.2.35 skrll tail->xfer = NULL;
3129 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0);
3130 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3131 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3132 1.254.2.35 skrll xfer->ux_hcpriv = data;
3133 1.254.2.35 skrll
3134 1.254.2.35 skrll DPRINTFN(8, "xfer %p data %p tail %p", xfer, ox->ox_stds[0], tail, 0);
3135 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3136 1.254.2.1 skrll
3137 1.77 augustss /* We want interrupt at the end of the transfer. */
3138 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3139 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3140 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3141 1.254.2.35 skrll last->nexttd = tail;
3142 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3143 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3144 1.254.2.35 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3145 1.3 augustss
3146 1.254.2.18 skrll DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x "
3147 1.254.2.18 skrll "td_cbp=0x%08x td_be=0x%08x",
3148 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3149 1.168 augustss (int)O32TOH(data->td.td_flags),
3150 1.168 augustss (int)O32TOH(data->td.td_cbp),
3151 1.254.2.18 skrll (int)O32TOH(data->td.td_be));
3152 1.34 augustss
3153 1.52 augustss #ifdef OHCI_DEBUG
3154 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3155 1.254.2.39 skrll if (ohcidebug >= 5) {
3156 1.168 augustss ohci_dump_ed(sc, sed);
3157 1.168 augustss ohci_dump_tds(sc, data);
3158 1.34 augustss }
3159 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3160 1.34 augustss #endif
3161 1.34 augustss
3162 1.3 augustss /* Insert ED in schedule */
3163 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3164 1.254.2.35 skrll KASSERT(tdp->xfer == xfer);
3165 1.48 augustss }
3166 1.254.2.35 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3167 1.254.2.35 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3168 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3169 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3170 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3171 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3172 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3173 1.254.2.7 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3174 1.254.2.7 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3175 1.80 augustss ohci_timeout, xfer);
3176 1.15 augustss }
3177 1.254.2.84 skrll
3178 1.254.2.84 skrll xfer->ux_status = USBD_IN_PROGRESS;
3179 1.224 mrg mutex_exit(&sc->sc_lock);
3180 1.34 augustss
3181 1.254.2.13 skrll return USBD_IN_PROGRESS;
3182 1.3 augustss }
3183 1.3 augustss
3184 1.82 augustss Static void
3185 1.254.2.19 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3186 1.3 augustss {
3187 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3188 1.254.2.25 skrll
3189 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3190 1.224 mrg
3191 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3192 1.224 mrg
3193 1.254.2.18 skrll DPRINTF("xfer=%p", xfer, 0, 0, 0);
3194 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3195 1.3 augustss }
3196 1.3 augustss
3197 1.120 augustss /*
3198 1.34 augustss * Close a device bulk pipe.
3199 1.34 augustss */
3200 1.82 augustss Static void
3201 1.254.2.19 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3202 1.3 augustss {
3203 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3204 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3205 1.3 augustss
3206 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3207 1.224 mrg
3208 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3209 1.254.2.18 skrll
3210 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3211 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3212 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3213 1.1 augustss }
3214 1.1 augustss
3215 1.1 augustss /************************/
3216 1.1 augustss
3217 1.254.2.35 skrll Static int
3218 1.254.2.35 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3219 1.254.2.35 skrll {
3220 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3221 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3222 1.254.2.35 skrll int len = xfer->ux_bufsize;
3223 1.254.2.35 skrll int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;;
3224 1.254.2.35 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3225 1.254.2.35 skrll int err;
3226 1.254.2.35 skrll
3227 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3228 1.254.2.35 skrll
3229 1.254.2.35 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3230 1.254.2.35 skrll KASSERT(len != 0);
3231 1.254.2.35 skrll
3232 1.254.2.35 skrll DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread,
3233 1.254.2.35 skrll xfer->ux_flags);
3234 1.254.2.35 skrll DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0);
3235 1.254.2.35 skrll
3236 1.254.2.35 skrll ox->ox_nstd = 0;
3237 1.254.2.35 skrll
3238 1.254.2.35 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3239 1.254.2.35 skrll if (err) {
3240 1.254.2.35 skrll return err;
3241 1.254.2.35 skrll }
3242 1.254.2.35 skrll
3243 1.254.2.35 skrll return 0;
3244 1.254.2.35 skrll }
3245 1.254.2.35 skrll
3246 1.254.2.35 skrll Static void
3247 1.254.2.35 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3248 1.254.2.35 skrll {
3249 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3250 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3251 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3252 1.254.2.35 skrll
3253 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3254 1.254.2.35 skrll DPRINTFN(8, "xfer %p nstd %d", xfer, ox->ox_nstd, 0, 0);
3255 1.254.2.35 skrll
3256 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3257 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3258 1.254.2.35 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3259 1.254.2.35 skrll if (std != NULL)
3260 1.254.2.35 skrll break;
3261 1.254.2.35 skrll if (std != opipe->tail.td)
3262 1.254.2.35 skrll ohci_free_std_locked(sc, std);
3263 1.254.2.35 skrll }
3264 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3265 1.254.2.35 skrll
3266 1.254.2.35 skrll if (ox->ox_nstd) {
3267 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3268 1.254.2.35 skrll kmem_free(ox->ox_stds, sz);
3269 1.254.2.35 skrll }
3270 1.254.2.35 skrll }
3271 1.254.2.35 skrll
3272 1.82 augustss Static usbd_status
3273 1.254.2.19 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3274 1.17 augustss {
3275 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3276 1.53 augustss usbd_status err;
3277 1.17 augustss
3278 1.46 augustss /* Insert last in queue. */
3279 1.224 mrg mutex_enter(&sc->sc_lock);
3280 1.53 augustss err = usb_insert_transfer(xfer);
3281 1.224 mrg mutex_exit(&sc->sc_lock);
3282 1.53 augustss if (err)
3283 1.254.2.13 skrll return err;
3284 1.46 augustss
3285 1.46 augustss /* Pipe isn't running, start first */
3286 1.254.2.13 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3287 1.17 augustss }
3288 1.17 augustss
3289 1.82 augustss Static usbd_status
3290 1.254.2.19 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3291 1.1 augustss {
3292 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3293 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3294 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3295 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3296 1.254.2.35 skrll ohci_soft_td_t *data, *last, *tail;
3297 1.224 mrg int len, isread, endpt;
3298 1.1 augustss
3299 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3300 1.254.2.18 skrll
3301 1.83 augustss if (sc->sc_dying)
3302 1.254.2.13 skrll return USBD_IOERROR;
3303 1.83 augustss
3304 1.254.2.18 skrll DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length,
3305 1.254.2.18 skrll xfer->ux_flags, xfer->ux_priv);
3306 1.1 augustss
3307 1.254.2.24 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3308 1.1 augustss
3309 1.254.2.7 skrll len = xfer->ux_length;
3310 1.254.2.7 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3311 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3312 1.1 augustss
3313 1.224 mrg mutex_enter(&sc->sc_lock);
3314 1.254.2.35 skrll
3315 1.254.2.42 skrll /*
3316 1.254.2.42 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3317 1.254.2.42 skrll * next transfer.
3318 1.254.2.42 skrll */
3319 1.254.2.35 skrll data = opipe->tail.td;
3320 1.254.2.35 skrll opipe->tail.td = ox->ox_stds[0];
3321 1.254.2.35 skrll ox->ox_stds[0] = data;
3322 1.254.2.76 skrll data->held = &ox->ox_stds[0];
3323 1.254.2.35 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3324 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new data=%p held at %p", ox, data, data->held, 0);
3325 1.254.2.35 skrll
3326 1.254.2.50 skrll /* point at sentinel */
3327 1.254.2.50 skrll tail = opipe->tail.td;
3328 1.254.2.35 skrll memset(&tail->td, 0, sizeof(tail->td));
3329 1.254.2.76 skrll tail->held = &opipe->tail.td;
3330 1.254.2.35 skrll tail->nexttd = NULL;
3331 1.53 augustss tail->xfer = NULL;
3332 1.254.2.76 skrll DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0);
3333 1.254.2.35 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3334 1.254.2.35 skrll BUS_DMASYNC_PREWRITE);
3335 1.254.2.35 skrll xfer->ux_hcpriv = data;
3336 1.254.2.35 skrll
3337 1.254.2.35 skrll DPRINTFN(8, "data %p tail %p", ox->ox_stds[0], tail, 0, 0);
3338 1.254.2.35 skrll KASSERT(opipe->tail.td == tail);
3339 1.1 augustss
3340 1.254.2.35 skrll /* We want interrupt at the end of the transfer. */
3341 1.254.2.35 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3342 1.254.2.35 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3343 1.254.2.35 skrll
3344 1.254.2.35 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3345 1.254.2.35 skrll last->nexttd = tail;
3346 1.254.2.35 skrll last->flags |= OHCI_CALL_DONE;
3347 1.254.2.35 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3348 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3349 1.1 augustss
3350 1.52 augustss #ifdef OHCI_DEBUG
3351 1.254.2.18 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3352 1.254.2.39 skrll if (ohcidebug >= 5) {
3353 1.168 augustss ohci_dump_ed(sc, sed);
3354 1.168 augustss ohci_dump_tds(sc, data);
3355 1.1 augustss }
3356 1.254.2.18 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3357 1.1 augustss #endif
3358 1.1 augustss
3359 1.1 augustss /* Insert ED in schedule */
3360 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3361 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3362 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3363 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3364 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3365 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3366 1.1 augustss
3367 1.254.2.84 skrll xfer->ux_status = USBD_IN_PROGRESS;
3368 1.224 mrg mutex_exit(&sc->sc_lock);
3369 1.1 augustss
3370 1.254.2.13 skrll return USBD_IN_PROGRESS;
3371 1.1 augustss }
3372 1.1 augustss
3373 1.227 skrll /* Abort a device interrupt request. */
3374 1.82 augustss Static void
3375 1.254.2.19 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3376 1.1 augustss {
3377 1.254.2.25 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3378 1.224 mrg
3379 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3380 1.254.2.7 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3381 1.224 mrg
3382 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3383 1.1 augustss }
3384 1.1 augustss
3385 1.1 augustss /* Close a device interrupt pipe. */
3386 1.82 augustss Static void
3387 1.254.2.19 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3388 1.1 augustss {
3389 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3390 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3391 1.254.2.21 skrll int nslots = opipe->intr.nslots;
3392 1.254.2.21 skrll int pos = opipe->intr.pos;
3393 1.1 augustss int j;
3394 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3395 1.224 mrg
3396 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3397 1.254.2.18 skrll
3398 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3399 1.1 augustss
3400 1.254.2.18 skrll DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0);
3401 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3402 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3403 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3404 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3405 1.195 bouyer sizeof(sed->ed.ed_flags),
3406 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3407 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3408 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3409 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3410 1.1 augustss
3411 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3412 1.172 christos continue;
3413 1.254.2.24 skrll KASSERT(p);
3414 1.173 christos p->next = sed->next;
3415 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3416 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3417 1.195 bouyer sizeof(p->ed.ed_nexted),
3418 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3419 1.1 augustss
3420 1.1 augustss for (j = 0; j < nslots; j++)
3421 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3422 1.1 augustss
3423 1.254.2.35 skrll ohci_free_std_locked(sc, opipe->tail.td);
3424 1.254.2.35 skrll ohci_free_sed_locked(sc, opipe->sed);
3425 1.1 augustss }
3426 1.1 augustss
3427 1.82 augustss Static usbd_status
3428 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3429 1.1 augustss {
3430 1.224 mrg int i, j, best;
3431 1.1 augustss u_int npoll, slow, shigh, nslots;
3432 1.1 augustss u_int bestbw, bw;
3433 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3434 1.1 augustss
3435 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3436 1.254.2.18 skrll
3437 1.254.2.18 skrll DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0);
3438 1.1 augustss if (ival == 0) {
3439 1.1 augustss printf("ohci_setintr: 0 interval\n");
3440 1.254.2.13 skrll return USBD_INVAL;
3441 1.1 augustss }
3442 1.1 augustss
3443 1.1 augustss npoll = OHCI_NO_INTRS;
3444 1.1 augustss while (npoll > ival)
3445 1.1 augustss npoll /= 2;
3446 1.254.2.18 skrll DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0);
3447 1.1 augustss
3448 1.1 augustss /*
3449 1.1 augustss * We now know which level in the tree the ED must go into.
3450 1.1 augustss * Figure out which slot has most bandwidth left over.
3451 1.1 augustss * Slots to examine:
3452 1.1 augustss * npoll
3453 1.1 augustss * 1 0
3454 1.1 augustss * 2 1 2
3455 1.1 augustss * 4 3 4 5 6
3456 1.1 augustss * 8 7 8 9 10 11 12 13 14
3457 1.1 augustss * N (N-1) .. (N-1+N-1)
3458 1.1 augustss */
3459 1.1 augustss slow = npoll-1;
3460 1.1 augustss shigh = slow + npoll;
3461 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3462 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3463 1.1 augustss bw = 0;
3464 1.1 augustss for (j = 0; j < nslots; j++)
3465 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3466 1.1 augustss if (bw < bestbw) {
3467 1.1 augustss best = i;
3468 1.1 augustss bestbw = bw;
3469 1.1 augustss }
3470 1.1 augustss }
3471 1.254.2.18 skrll DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw);
3472 1.1 augustss
3473 1.224 mrg mutex_enter(&sc->sc_lock);
3474 1.1 augustss hsed = sc->sc_eds[best];
3475 1.1 augustss sed->next = hsed->next;
3476 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3477 1.195 bouyer sizeof(hsed->ed.ed_flags),
3478 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3479 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3480 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3481 1.195 bouyer sizeof(sed->ed.ed_flags),
3482 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3483 1.1 augustss hsed->next = sed;
3484 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3485 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3486 1.195 bouyer sizeof(hsed->ed.ed_flags),
3487 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3488 1.224 mrg mutex_exit(&sc->sc_lock);
3489 1.1 augustss
3490 1.1 augustss for (j = 0; j < nslots; j++)
3491 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3492 1.254.2.21 skrll opipe->intr.nslots = nslots;
3493 1.254.2.21 skrll opipe->intr.pos = best;
3494 1.1 augustss
3495 1.254.2.18 skrll DPRINTFN(5, "returns %p", opipe, 0, 0, 0);
3496 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3497 1.60 augustss }
3498 1.60 augustss
3499 1.60 augustss /***********************/
3500 1.60 augustss
3501 1.254.2.35 skrll Static int
3502 1.254.2.35 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3503 1.254.2.35 skrll {
3504 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3505 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3506 1.254.2.35 skrll ohci_soft_itd_t *sitd;
3507 1.254.2.35 skrll size_t i;
3508 1.254.2.35 skrll int err;
3509 1.254.2.35 skrll
3510 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3511 1.254.2.35 skrll
3512 1.254.2.35 skrll DPRINTFN(1, "xfer %p len %d flags %d", xfer, xfer->ux_length,
3513 1.254.2.35 skrll xfer->ux_flags, 0);
3514 1.254.2.35 skrll
3515 1.254.2.35 skrll const size_t nfsitd =
3516 1.254.2.35 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3517 1.254.2.35 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3518 1.254.2.35 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3519 1.254.2.35 skrll
3520 1.254.2.35 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3521 1.254.2.35 skrll KM_SLEEP);
3522 1.254.2.35 skrll ox->ox_nsitd = nsitd;
3523 1.254.2.35 skrll
3524 1.254.2.35 skrll for (i = 0; i < nsitd; i++) {
3525 1.254.2.35 skrll /* Allocate next ITD */
3526 1.254.2.35 skrll sitd = ohci_alloc_sitd(sc);
3527 1.254.2.35 skrll if (sitd == NULL) {
3528 1.254.2.35 skrll err = ENOMEM;
3529 1.254.2.35 skrll goto fail;
3530 1.254.2.35 skrll }
3531 1.254.2.35 skrll ox->ox_sitds[i] = sitd;
3532 1.254.2.76 skrll sitd->held = &ox->ox_sitds[i];
3533 1.254.2.35 skrll sitd->xfer = xfer;
3534 1.254.2.35 skrll sitd->flags = 0;
3535 1.254.2.76 skrll // DPRINTFN(10, "xfer=%p new tail=%p held at %p", ox, tail, tail->held, 0);
3536 1.254.2.35 skrll }
3537 1.254.2.35 skrll
3538 1.254.2.35 skrll return 0;
3539 1.254.2.35 skrll fail:
3540 1.254.2.35 skrll for (; i > 0;) {
3541 1.254.2.35 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3542 1.254.2.35 skrll }
3543 1.254.2.35 skrll return err;
3544 1.254.2.35 skrll }
3545 1.254.2.35 skrll
3546 1.254.2.35 skrll Static void
3547 1.254.2.35 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3548 1.254.2.35 skrll {
3549 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3550 1.254.2.35 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3551 1.254.2.35 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3552 1.254.2.35 skrll
3553 1.254.2.35 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3554 1.254.2.35 skrll
3555 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3556 1.254.2.35 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3557 1.254.2.35 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3558 1.254.2.35 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3559 1.254.2.35 skrll }
3560 1.254.2.35 skrll }
3561 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3562 1.254.2.35 skrll
3563 1.254.2.35 skrll if (ox->ox_nsitd) {
3564 1.254.2.35 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3565 1.254.2.35 skrll kmem_free(ox->ox_sitds, sz);
3566 1.254.2.35 skrll }
3567 1.254.2.35 skrll }
3568 1.254.2.35 skrll
3569 1.254.2.35 skrll
3570 1.60 augustss usbd_status
3571 1.254.2.19 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3572 1.60 augustss {
3573 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3574 1.254.2.59 skrll usbd_status __diagused err;
3575 1.60 augustss
3576 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3577 1.254.2.18 skrll
3578 1.254.2.18 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3579 1.60 augustss
3580 1.60 augustss /* Put it on our queue, */
3581 1.224 mrg mutex_enter(&sc->sc_lock);
3582 1.60 augustss err = usb_insert_transfer(xfer);
3583 1.224 mrg mutex_exit(&sc->sc_lock);
3584 1.60 augustss
3585 1.254.2.59 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3586 1.60 augustss
3587 1.60 augustss /* insert into schedule, */
3588 1.60 augustss ohci_device_isoc_enter(xfer);
3589 1.60 augustss
3590 1.83 augustss /* and start if the pipe wasn't running */
3591 1.254.2.59 skrll return USBD_IN_PROGRESS;
3592 1.60 augustss }
3593 1.60 augustss
3594 1.60 augustss void
3595 1.254.2.19 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3596 1.60 augustss {
3597 1.254.2.35 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3598 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3599 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3600 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3601 1.254.2.53 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3602 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3603 1.61 augustss int i, ncur, nframes;
3604 1.61 augustss
3605 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3606 1.254.2.53 skrll DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0);
3607 1.254.2.18 skrll
3608 1.254.2.35 skrll mutex_enter(&sc->sc_lock);
3609 1.83 augustss
3610 1.254.2.35 skrll if (sc->sc_dying) {
3611 1.254.2.35 skrll mutex_exit(&sc->sc_lock);
3612 1.83 augustss return;
3613 1.254.2.35 skrll }
3614 1.254.2.35 skrll
3615 1.254.2.35 skrll struct isoc *isoc = &opipe->isoc;
3616 1.254.2.35 skrll
3617 1.254.2.35 skrll DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d",
3618 1.254.2.35 skrll isoc->inuse, isoc->next, xfer, xfer->ux_nframes);
3619 1.83 augustss
3620 1.254.2.21 skrll if (isoc->next == -1) {
3621 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3622 1.254.2.21 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3623 1.254.2.21 skrll DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0);
3624 1.83 augustss }
3625 1.83 augustss
3626 1.61 augustss sitd = opipe->tail.itd;
3627 1.254.2.35 skrll opipe->tail.itd = ox->ox_sitds[0];
3628 1.254.2.35 skrll ox->ox_sitds[0] = sitd;
3629 1.254.2.76 skrll sitd->held = &ox->ox_sitds[0];
3630 1.254.2.35 skrll
3631 1.254.2.7 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3632 1.83 augustss bp0 = OHCI_PAGE(buf);
3633 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3634 1.254.2.7 skrll nframes = xfer->ux_nframes;
3635 1.254.2.7 skrll xfer->ux_hcpriv = sitd;
3636 1.254.2.35 skrll size_t j = 1;
3637 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3638 1.254.2.7 skrll noffs = offs + xfer->ux_frlengths[i];
3639 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3640 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3641 1.120 augustss
3642 1.83 augustss /* Allocate next ITD */
3643 1.254.2.35 skrll nsitd = ox->ox_sitds[j++];
3644 1.254.2.35 skrll KASSERT(nsitd != NULL);
3645 1.254.2.35 skrll KASSERT(j < ox->ox_nsitd);
3646 1.83 augustss
3647 1.83 augustss /* Fill current ITD */
3648 1.168 augustss sitd->itd.itd_flags = HTOO32(
3649 1.120 augustss OHCI_ITD_NOCC |
3650 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3651 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3652 1.83 augustss OHCI_ITD_SET_FC(ncur));
3653 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3654 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3655 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3656 1.254.2.33 skrll sitd->nextitd = nsitd;
3657 1.83 augustss sitd->xfer = xfer;
3658 1.83 augustss sitd->flags = 0;
3659 1.254.2.35 skrll #ifdef DIAGNOSTIC
3660 1.254.2.35 skrll sitd->isdone = false;
3661 1.254.2.35 skrll #endif
3662 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3663 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3664 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3665 1.83 augustss
3666 1.61 augustss sitd = nsitd;
3667 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3668 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3669 1.61 augustss ncur = 0;
3670 1.61 augustss }
3671 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3672 1.83 augustss offs = noffs;
3673 1.61 augustss }
3674 1.254.2.35 skrll KASSERT(j <= ox->ox_nsitd);
3675 1.254.2.35 skrll
3676 1.254.2.53 skrll /* point at sentinel */
3677 1.254.2.53 skrll tail = opipe->tail.itd;
3678 1.254.2.53 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3679 1.254.2.76 skrll tail->held = &opipe->tail.itd;
3680 1.254.2.53 skrll tail->nextitd = NULL;
3681 1.254.2.79 skrll tail->xfer = NULL;
3682 1.254.2.53 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3683 1.254.2.53 skrll BUS_DMASYNC_PREWRITE);
3684 1.254.2.53 skrll
3685 1.83 augustss /* Fixup last used ITD */
3686 1.168 augustss sitd->itd.itd_flags = HTOO32(
3687 1.120 augustss OHCI_ITD_NOCC |
3688 1.254.2.21 skrll OHCI_ITD_SET_SF(isoc->next) |
3689 1.61 augustss OHCI_ITD_SET_DI(0) |
3690 1.61 augustss OHCI_ITD_SET_FC(ncur));
3691 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3692 1.254.2.53 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3693 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3694 1.254.2.53 skrll sitd->nextitd = tail;
3695 1.83 augustss sitd->xfer = xfer;
3696 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3697 1.254.2.35 skrll #ifdef DIAGNOSTIC
3698 1.254.2.35 skrll sitd->isdone = false;
3699 1.254.2.35 skrll #endif
3700 1.254.2.35 skrll ohci_hash_add_itd(sc, sitd);
3701 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3702 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3703 1.83 augustss
3704 1.254.2.21 skrll isoc->next = isoc->next + ncur;
3705 1.254.2.21 skrll isoc->inuse += nframes;
3706 1.83 augustss
3707 1.254.2.48 skrll /* XXX pretend we did it all */
3708 1.254.2.48 skrll xfer->ux_actlen = offs;
3709 1.254.2.7 skrll xfer->ux_status = USBD_IN_PROGRESS;
3710 1.83 augustss
3711 1.83 augustss #ifdef OHCI_DEBUG
3712 1.254.2.39 skrll if (ohcidebug >= 5) {
3713 1.254.2.18 skrll DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number),
3714 1.254.2.18 skrll 0, 0, 0);
3715 1.254.2.7 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3716 1.168 augustss ohci_dump_ed(sc, sed);
3717 1.83 augustss }
3718 1.83 augustss #endif
3719 1.61 augustss
3720 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3721 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3722 1.254.2.53 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3723 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3724 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3725 1.195 bouyer sizeof(sed->ed.ed_flags),
3726 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3727 1.224 mrg mutex_exit(&sc->sc_lock);
3728 1.60 augustss }
3729 1.60 augustss
3730 1.60 augustss void
3731 1.254.2.19 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3732 1.60 augustss {
3733 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3734 1.254.2.25 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3735 1.83 augustss ohci_soft_ed_t *sed;
3736 1.83 augustss ohci_soft_itd_t *sitd;
3737 1.83 augustss
3738 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3739 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3740 1.83 augustss
3741 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3742 1.83 augustss
3743 1.83 augustss /* Transfer is already done. */
3744 1.254.2.7 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3745 1.254.2.7 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3746 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3747 1.224 mrg goto done;
3748 1.83 augustss }
3749 1.83 augustss
3750 1.83 augustss /* Give xfer the requested abort code. */
3751 1.254.2.7 skrll xfer->ux_status = USBD_CANCELLED;
3752 1.83 augustss
3753 1.83 augustss sed = opipe->sed;
3754 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3755 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3756 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3757 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3758 1.195 bouyer sizeof(sed->ed.ed_flags),
3759 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3760 1.83 augustss
3761 1.254.2.7 skrll sitd = xfer->ux_hcpriv;
3762 1.254.2.24 skrll KASSERT(sitd);
3763 1.254.2.24 skrll
3764 1.254.2.60 skrll usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3765 1.254.2.60 skrll
3766 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3767 1.254.2.55 skrll ohci_hash_rem_itd(sc, sitd);
3768 1.83 augustss #ifdef DIAGNOSTIC
3769 1.254.2.18 skrll DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0);
3770 1.254.2.31 skrll sitd->isdone = true;
3771 1.83 augustss #endif
3772 1.83 augustss }
3773 1.83 augustss
3774 1.83 augustss /* Run callback. */
3775 1.83 augustss usb_transfer_complete(xfer);
3776 1.83 augustss
3777 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3778 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3779 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3780 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3781 1.83 augustss
3782 1.224 mrg done:
3783 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3784 1.60 augustss }
3785 1.60 augustss
3786 1.60 augustss void
3787 1.254.2.19 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3788 1.60 augustss {
3789 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3790 1.254.2.18 skrll DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0);
3791 1.60 augustss }
3792 1.60 augustss
3793 1.60 augustss usbd_status
3794 1.254.2.19 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3795 1.60 augustss {
3796 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3797 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3798 1.254.2.21 skrll struct isoc *isoc = &opipe->isoc;
3799 1.60 augustss
3800 1.254.2.21 skrll isoc->next = -1;
3801 1.254.2.21 skrll isoc->inuse = 0;
3802 1.60 augustss
3803 1.224 mrg mutex_enter(&sc->sc_lock);
3804 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3805 1.224 mrg mutex_exit(&sc->sc_lock);
3806 1.83 augustss
3807 1.254.2.13 skrll return USBD_NORMAL_COMPLETION;
3808 1.60 augustss }
3809 1.60 augustss
3810 1.60 augustss void
3811 1.254.2.19 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3812 1.60 augustss {
3813 1.254.2.25 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3814 1.254.2.25 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3815 1.60 augustss
3816 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3817 1.224 mrg
3818 1.254.2.18 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3819 1.254.2.18 skrll DPRINTF("pipe=%p", pipe, 0, 0, 0);
3820 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3821 1.83 augustss #ifdef DIAGNOSTIC
3822 1.254.2.31 skrll opipe->tail.itd->isdone = true;
3823 1.83 augustss #endif
3824 1.254.2.35 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3825 1.1 augustss }
3826