ohci.c revision 1.281 1 1.281 maya /* $NetBSD: ohci.c,v 1.281 2018/06/06 01:49:09 maya Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.281 maya __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.281 2018/06/06 01:49:09 maya Exp $");
45 1.260 skrll
46 1.263 pooka #ifdef _KERNEL_OPT
47 1.260 skrll #include "opt_usb.h"
48 1.263 pooka #endif
49 1.1 augustss
50 1.1 augustss #include <sys/param.h>
51 1.260 skrll
52 1.260 skrll #include <sys/cpu.h>
53 1.260 skrll #include <sys/device.h>
54 1.260 skrll #include <sys/kernel.h>
55 1.224 mrg #include <sys/kmem.h>
56 1.1 augustss #include <sys/proc.h>
57 1.1 augustss #include <sys/queue.h>
58 1.260 skrll #include <sys/select.h>
59 1.260 skrll #include <sys/sysctl.h>
60 1.260 skrll #include <sys/systm.h>
61 1.1 augustss
62 1.16 augustss #include <machine/endian.h>
63 1.4 augustss
64 1.1 augustss #include <dev/usb/usb.h>
65 1.1 augustss #include <dev/usb/usbdi.h>
66 1.1 augustss #include <dev/usb/usbdivar.h>
67 1.38 augustss #include <dev/usb/usb_mem.h>
68 1.1 augustss #include <dev/usb/usb_quirks.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/ohcireg.h>
71 1.1 augustss #include <dev/usb/ohcivar.h>
72 1.260 skrll #include <dev/usb/usbroothub.h>
73 1.260 skrll #include <dev/usb/usbhist.h>
74 1.260 skrll
75 1.260 skrll #ifdef USB_DEBUG
76 1.260 skrll #ifndef OHCI_DEBUG
77 1.260 skrll #define ohcidebug 0
78 1.260 skrll #else
79 1.260 skrll static int ohcidebug = 10;
80 1.260 skrll
81 1.260 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
82 1.260 skrll {
83 1.260 skrll int err;
84 1.260 skrll const struct sysctlnode *rnode;
85 1.260 skrll const struct sysctlnode *cnode;
86 1.260 skrll
87 1.260 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
88 1.260 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
89 1.260 skrll SYSCTL_DESCR("ohci global controls"),
90 1.260 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
91 1.1 augustss
92 1.260 skrll if (err)
93 1.260 skrll goto fail;
94 1.260 skrll
95 1.260 skrll /* control debugging printfs */
96 1.260 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
97 1.260 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
98 1.260 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
99 1.260 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
100 1.260 skrll if (err)
101 1.260 skrll goto fail;
102 1.260 skrll
103 1.260 skrll return;
104 1.260 skrll fail:
105 1.260 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
106 1.260 skrll }
107 1.1 augustss
108 1.260 skrll #endif /* OHCI_DEBUG */
109 1.260 skrll #endif /* USB_DEBUG */
110 1.36 augustss
111 1.260 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
112 1.260 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
113 1.260 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
114 1.260 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
115 1.52 augustss
116 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
117 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
118 1.16 augustss #else
119 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
120 1.16 augustss #endif
121 1.16 augustss
122 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
123 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
124 1.169 tron #define HTOO16(val) O16TOH(val)
125 1.169 tron #define HTOO32(val) O32TOH(val)
126 1.168 augustss
127 1.1 augustss struct ohci_pipe;
128 1.1 augustss
129 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
130 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
131 1.1 augustss
132 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
133 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
134 1.260 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
135 1.1 augustss
136 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
137 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
138 1.260 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
139 1.260 skrll ohci_soft_itd_t *);
140 1.60 augustss
141 1.260 skrll Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
142 1.260 skrll int, int);
143 1.260 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
144 1.53 augustss
145 1.260 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
146 1.260 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
147 1.260 skrll
148 1.260 skrll Static usbd_status ohci_open(struct usbd_pipe *);
149 1.91 augustss Static void ohci_poll(struct usbd_bus *);
150 1.99 augustss Static void ohci_softintr(void *);
151 1.260 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
152 1.260 skrll Static void ohci_rhsc_softint(void *);
153 1.91 augustss
154 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
155 1.168 augustss ohci_soft_ed_t *);
156 1.168 augustss
157 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
158 1.224 mrg ohci_soft_ed_t *);
159 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
161 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
162 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
164 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
165 1.91 augustss
166 1.260 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
167 1.260 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
168 1.91 augustss
169 1.260 skrll Static struct usbd_xfer *
170 1.260 skrll ohci_allocx(struct usbd_bus *, unsigned int);
171 1.260 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
172 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
173 1.260 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
174 1.260 skrll usb_device_request_t *, void *, int);
175 1.91 augustss
176 1.260 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
177 1.260 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
178 1.260 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
179 1.260 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
180 1.260 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
181 1.260 skrll
182 1.260 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
183 1.260 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
184 1.260 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
185 1.260 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
186 1.260 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
187 1.260 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
188 1.260 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
189 1.260 skrll
190 1.260 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
191 1.260 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
192 1.260 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
193 1.260 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
194 1.260 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
195 1.260 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
196 1.260 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
197 1.260 skrll
198 1.260 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
199 1.260 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
200 1.260 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
201 1.260 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
202 1.260 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
203 1.260 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
204 1.260 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
205 1.260 skrll
206 1.260 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
207 1.260 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
208 1.260 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
209 1.260 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
210 1.260 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
211 1.260 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
212 1.91 augustss
213 1.260 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
214 1.260 skrll struct ohci_pipe *, int);
215 1.91 augustss
216 1.91 augustss Static void ohci_timeout(void *);
217 1.114 augustss Static void ohci_timeout_task(void *);
218 1.104 augustss Static void ohci_rhsc_enable(void *);
219 1.91 augustss
220 1.260 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
221 1.260 skrll Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status);
222 1.53 augustss
223 1.260 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
224 1.260 skrll Static void ohci_noop(struct usbd_pipe *);
225 1.37 augustss
226 1.52 augustss #ifdef OHCI_DEBUG
227 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
228 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
230 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
231 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
232 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
233 1.1 augustss #endif
234 1.1 augustss
235 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
236 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
237 1.88 augustss #define OWRITE1(sc, r, x) \
238 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
239 1.88 augustss #define OWRITE2(sc, r, x) \
240 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
241 1.88 augustss #define OWRITE4(sc, r, x) \
242 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
243 1.174 mrg
244 1.174 mrg static __inline uint32_t
245 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
246 1.174 mrg {
247 1.174 mrg
248 1.174 mrg OBARR(sc);
249 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
250 1.174 mrg }
251 1.1 augustss
252 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
253 1.260 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
254 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
255 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
256 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
257 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
258 1.1 augustss
259 1.1 augustss struct ohci_pipe {
260 1.1 augustss struct usbd_pipe pipe;
261 1.1 augustss ohci_soft_ed_t *sed;
262 1.60 augustss union {
263 1.60 augustss ohci_soft_td_t *td;
264 1.60 augustss ohci_soft_itd_t *itd;
265 1.60 augustss } tail;
266 1.1 augustss /* Info needed for different pipe kinds. */
267 1.1 augustss union {
268 1.1 augustss /* Control pipe */
269 1.1 augustss struct {
270 1.4 augustss usb_dma_t reqdma;
271 1.260 skrll } ctrl;
272 1.1 augustss /* Interrupt pipe */
273 1.1 augustss struct {
274 1.1 augustss int nslots;
275 1.1 augustss int pos;
276 1.1 augustss } intr;
277 1.260 skrll /* Isochronous pipe */
278 1.260 skrll struct isoc {
279 1.60 augustss int next, inuse;
280 1.260 skrll } isoc;
281 1.260 skrll };
282 1.1 augustss };
283 1.1 augustss
284 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
285 1.260 skrll .ubm_open = ohci_open,
286 1.260 skrll .ubm_softint = ohci_softintr,
287 1.260 skrll .ubm_dopoll = ohci_poll,
288 1.260 skrll .ubm_allocx = ohci_allocx,
289 1.260 skrll .ubm_freex = ohci_freex,
290 1.260 skrll .ubm_getlock = ohci_get_lock,
291 1.260 skrll .ubm_rhctrl = ohci_roothub_ctrl,
292 1.1 augustss };
293 1.1 augustss
294 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
295 1.260 skrll .upm_transfer = ohci_root_intr_transfer,
296 1.260 skrll .upm_start = ohci_root_intr_start,
297 1.260 skrll .upm_abort = ohci_root_intr_abort,
298 1.260 skrll .upm_close = ohci_root_intr_close,
299 1.260 skrll .upm_cleartoggle = ohci_noop,
300 1.260 skrll .upm_done = ohci_root_intr_done,
301 1.1 augustss };
302 1.1 augustss
303 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
304 1.260 skrll .upm_init = ohci_device_ctrl_init,
305 1.260 skrll .upm_fini = ohci_device_ctrl_fini,
306 1.260 skrll .upm_transfer = ohci_device_ctrl_transfer,
307 1.260 skrll .upm_start = ohci_device_ctrl_start,
308 1.260 skrll .upm_abort = ohci_device_ctrl_abort,
309 1.260 skrll .upm_close = ohci_device_ctrl_close,
310 1.260 skrll .upm_cleartoggle = ohci_noop,
311 1.260 skrll .upm_done = ohci_device_ctrl_done,
312 1.1 augustss };
313 1.1 augustss
314 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
315 1.260 skrll .upm_init = ohci_device_intr_init,
316 1.260 skrll .upm_fini = ohci_device_intr_fini,
317 1.260 skrll .upm_transfer = ohci_device_intr_transfer,
318 1.260 skrll .upm_start = ohci_device_intr_start,
319 1.260 skrll .upm_abort = ohci_device_intr_abort,
320 1.260 skrll .upm_close = ohci_device_intr_close,
321 1.260 skrll .upm_cleartoggle = ohci_device_clear_toggle,
322 1.260 skrll .upm_done = ohci_device_intr_done,
323 1.1 augustss };
324 1.1 augustss
325 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
326 1.260 skrll .upm_init = ohci_device_bulk_init,
327 1.260 skrll .upm_fini = ohci_device_bulk_fini,
328 1.260 skrll .upm_transfer = ohci_device_bulk_transfer,
329 1.260 skrll .upm_start = ohci_device_bulk_start,
330 1.260 skrll .upm_abort = ohci_device_bulk_abort,
331 1.260 skrll .upm_close = ohci_device_bulk_close,
332 1.260 skrll .upm_cleartoggle = ohci_device_clear_toggle,
333 1.260 skrll .upm_done = ohci_device_bulk_done,
334 1.3 augustss };
335 1.3 augustss
336 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
337 1.260 skrll .upm_init = ohci_device_isoc_init,
338 1.260 skrll .upm_fini = ohci_device_isoc_fini,
339 1.260 skrll .upm_transfer = ohci_device_isoc_transfer,
340 1.260 skrll .upm_abort = ohci_device_isoc_abort,
341 1.260 skrll .upm_close = ohci_device_isoc_close,
342 1.260 skrll .upm_cleartoggle = ohci_noop,
343 1.260 skrll .upm_done = ohci_device_isoc_done,
344 1.43 augustss };
345 1.43 augustss
346 1.47 augustss int
347 1.189 dyoung ohci_activate(device_t self, enum devact act)
348 1.47 augustss {
349 1.189 dyoung struct ohci_softc *sc = device_private(self);
350 1.47 augustss
351 1.47 augustss switch (act) {
352 1.47 augustss case DVACT_DEACTIVATE:
353 1.183 kiyohara sc->sc_dying = 1;
354 1.203 dyoung return 0;
355 1.203 dyoung default:
356 1.203 dyoung return EOPNOTSUPP;
357 1.47 augustss }
358 1.47 augustss }
359 1.47 augustss
360 1.187 dyoung void
361 1.187 dyoung ohci_childdet(device_t self, device_t child)
362 1.187 dyoung {
363 1.187 dyoung struct ohci_softc *sc = device_private(self);
364 1.187 dyoung
365 1.187 dyoung KASSERT(sc->sc_child == child);
366 1.187 dyoung sc->sc_child = NULL;
367 1.187 dyoung }
368 1.187 dyoung
369 1.47 augustss int
370 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
371 1.47 augustss {
372 1.47 augustss int rv = 0;
373 1.47 augustss
374 1.47 augustss if (sc->sc_child != NULL)
375 1.47 augustss rv = config_detach(sc->sc_child, flags);
376 1.120 augustss
377 1.47 augustss if (rv != 0)
378 1.260 skrll return rv;
379 1.47 augustss
380 1.277 msaitoh softint_disestablish(sc->sc_rhsc_si);
381 1.104 augustss
382 1.277 msaitoh callout_halt(&sc->sc_tmo_rhsc, NULL);
383 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
384 1.116 augustss
385 1.224 mrg cv_destroy(&sc->sc_softwake_cv);
386 1.224 mrg
387 1.224 mrg mutex_destroy(&sc->sc_lock);
388 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
389 1.224 mrg
390 1.198 cegger if (sc->sc_hcca != NULL)
391 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
392 1.232 christos pool_cache_destroy(sc->sc_xferpool);
393 1.47 augustss
394 1.260 skrll return rv;
395 1.47 augustss }
396 1.47 augustss
397 1.1 augustss ohci_soft_ed_t *
398 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
399 1.1 augustss {
400 1.1 augustss ohci_soft_ed_t *sed;
401 1.53 augustss usbd_status err;
402 1.1 augustss int i, offs;
403 1.4 augustss usb_dma_t dma;
404 1.1 augustss
405 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
406 1.260 skrll
407 1.260 skrll mutex_enter(&sc->sc_lock);
408 1.53 augustss if (sc->sc_freeeds == NULL) {
409 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
410 1.260 skrll mutex_exit(&sc->sc_lock);
411 1.260 skrll
412 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
413 1.53 augustss OHCI_ED_ALIGN, &dma);
414 1.53 augustss if (err)
415 1.260 skrll return 0;
416 1.260 skrll
417 1.260 skrll mutex_enter(&sc->sc_lock);
418 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
419 1.39 augustss offs = i * OHCI_SED_SIZE;
420 1.123 augustss sed = KERNADDR(&dma, offs);
421 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
422 1.195 bouyer sed->dma = dma;
423 1.195 bouyer sed->offs = offs;
424 1.1 augustss sed->next = sc->sc_freeeds;
425 1.1 augustss sc->sc_freeeds = sed;
426 1.1 augustss }
427 1.1 augustss }
428 1.1 augustss sed = sc->sc_freeeds;
429 1.1 augustss sc->sc_freeeds = sed->next;
430 1.260 skrll mutex_exit(&sc->sc_lock);
431 1.260 skrll
432 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
433 1.1 augustss sed->next = 0;
434 1.260 skrll return sed;
435 1.260 skrll }
436 1.260 skrll
437 1.260 skrll static inline void
438 1.260 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
439 1.260 skrll {
440 1.260 skrll
441 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
442 1.260 skrll
443 1.260 skrll sed->next = sc->sc_freeeds;
444 1.260 skrll sc->sc_freeeds = sed;
445 1.1 augustss }
446 1.1 augustss
447 1.1 augustss void
448 1.91 augustss ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
449 1.1 augustss {
450 1.260 skrll
451 1.260 skrll mutex_enter(&sc->sc_lock);
452 1.260 skrll ohci_free_sed_locked(sc, sed);
453 1.260 skrll mutex_exit(&sc->sc_lock);
454 1.1 augustss }
455 1.1 augustss
456 1.1 augustss ohci_soft_td_t *
457 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
458 1.1 augustss {
459 1.1 augustss ohci_soft_td_t *std;
460 1.53 augustss usbd_status err;
461 1.1 augustss int i, offs;
462 1.4 augustss usb_dma_t dma;
463 1.1 augustss
464 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
465 1.240 skrll
466 1.260 skrll mutex_enter(&sc->sc_lock);
467 1.53 augustss if (sc->sc_freetds == NULL) {
468 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
469 1.260 skrll mutex_exit(&sc->sc_lock);
470 1.260 skrll
471 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
472 1.53 augustss OHCI_TD_ALIGN, &dma);
473 1.53 augustss if (err)
474 1.260 skrll return NULL;
475 1.260 skrll
476 1.260 skrll mutex_enter(&sc->sc_lock);
477 1.259 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
478 1.39 augustss offs = i * OHCI_STD_SIZE;
479 1.123 augustss std = KERNADDR(&dma, offs);
480 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
481 1.195 bouyer std->dma = dma;
482 1.195 bouyer std->offs = offs;
483 1.1 augustss std->nexttd = sc->sc_freetds;
484 1.1 augustss sc->sc_freetds = std;
485 1.1 augustss }
486 1.1 augustss }
487 1.69 augustss
488 1.1 augustss std = sc->sc_freetds;
489 1.1 augustss sc->sc_freetds = std->nexttd;
490 1.260 skrll mutex_exit(&sc->sc_lock);
491 1.260 skrll
492 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
493 1.83 augustss std->nexttd = NULL;
494 1.83 augustss std->xfer = NULL;
495 1.69 augustss
496 1.260 skrll return std;
497 1.1 augustss }
498 1.1 augustss
499 1.1 augustss void
500 1.260 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
501 1.1 augustss {
502 1.258 skrll
503 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
504 1.260 skrll
505 1.1 augustss std->nexttd = sc->sc_freetds;
506 1.1 augustss sc->sc_freetds = std;
507 1.1 augustss }
508 1.1 augustss
509 1.260 skrll void
510 1.260 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
511 1.260 skrll {
512 1.260 skrll
513 1.260 skrll mutex_enter(&sc->sc_lock);
514 1.260 skrll ohci_free_std_locked(sc, std);
515 1.260 skrll mutex_exit(&sc->sc_lock);
516 1.260 skrll }
517 1.260 skrll
518 1.260 skrll Static int
519 1.260 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd)
520 1.260 skrll {
521 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
522 1.260 skrll uint16_t flags = xfer->ux_flags;
523 1.260 skrll
524 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
525 1.260 skrll
526 1.274 pgoyette DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd",
527 1.260 skrll xfer->ux_pipe->up_dev->ud_addr,
528 1.260 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
529 1.260 skrll length, xfer->ux_pipe->up_dev->ud_speed);
530 1.260 skrll
531 1.260 skrll ASSERT_SLEEPABLE();
532 1.260 skrll KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
533 1.260 skrll
534 1.260 skrll size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
535 1.260 skrll nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
536 1.260 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
537 1.260 skrll KM_SLEEP);
538 1.260 skrll ox->ox_nstd = nstd;
539 1.260 skrll
540 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0);
541 1.260 skrll
542 1.260 skrll for (size_t j = 0; j < ox->ox_nstd;) {
543 1.260 skrll ohci_soft_td_t *cur = ohci_alloc_std(sc);
544 1.260 skrll if (cur == NULL)
545 1.260 skrll goto nomem;
546 1.260 skrll
547 1.260 skrll ox->ox_stds[j++] = cur;
548 1.260 skrll cur->xfer = xfer;
549 1.260 skrll cur->flags = 0;
550 1.260 skrll }
551 1.260 skrll
552 1.260 skrll return 0;
553 1.260 skrll
554 1.260 skrll nomem:
555 1.260 skrll ohci_free_stds(sc, ox);
556 1.260 skrll kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd);
557 1.260 skrll
558 1.260 skrll return ENOMEM;
559 1.260 skrll }
560 1.260 skrll
561 1.260 skrll Static void
562 1.260 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
563 1.260 skrll {
564 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
565 1.274 pgoyette DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0);
566 1.260 skrll
567 1.260 skrll mutex_enter(&sc->sc_lock);
568 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
569 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
570 1.260 skrll if (std == NULL)
571 1.260 skrll break;
572 1.260 skrll ohci_free_std_locked(sc, std);
573 1.260 skrll }
574 1.260 skrll mutex_exit(&sc->sc_lock);
575 1.260 skrll }
576 1.260 skrll
577 1.260 skrll void
578 1.260 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
579 1.260 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
580 1.48 augustss {
581 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
582 1.48 augustss ohci_soft_td_t *next, *cur;
583 1.75 augustss int len, curlen;
584 1.260 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
585 1.260 skrll uint16_t flags = xfer->ux_flags;
586 1.48 augustss
587 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
588 1.274 pgoyette DPRINTF("start len=%jd", alen, 0, 0, 0);
589 1.75 augustss
590 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
591 1.224 mrg
592 1.274 pgoyette DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd",
593 1.260 skrll xfer->ux_pipe->up_dev->ud_addr,
594 1.260 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
595 1.260 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
596 1.260 skrll
597 1.260 skrll KASSERT(sp);
598 1.260 skrll
599 1.260 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
600 1.260 skrll
601 1.260 skrll /*
602 1.260 skrll * Assign next for the len == 0 case where we don't go through the
603 1.260 skrll * main loop.
604 1.260 skrll */
605 1.75 augustss len = alen;
606 1.260 skrll cur = next = sp;
607 1.260 skrll
608 1.195 bouyer usb_syncmem(dma, 0, len,
609 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
610 1.260 skrll const uint32_t tdflags = HTOO32(
611 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
612 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
613 1.61 augustss
614 1.260 skrll size_t curoffs = 0;
615 1.260 skrll for (size_t j = 1; len != 0;) {
616 1.260 skrll if (j == ox->ox_nstd)
617 1.260 skrll next = NULL;
618 1.260 skrll else
619 1.260 skrll next = ox->ox_stds[j++];
620 1.260 skrll KASSERT(next != cur);
621 1.260 skrll
622 1.260 skrll curlen = 0;
623 1.270 skrll const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
624 1.260 skrll ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1);
625 1.48 augustss
626 1.270 skrll const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys);
627 1.260 skrll ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys);
628 1.260 skrll /*
629 1.260 skrll * The OHCI hardware can handle at most one page
630 1.260 skrll * crossing per TD
631 1.260 skrll */
632 1.260 skrll curlen = len;
633 1.267 skrll if (sphyspg != ephyspg &&
634 1.268 skrll sphyspg + OHCI_PAGE_SIZE != ephyspg) {
635 1.48 augustss /* must use multiple TDs, fill as much as possible. */
636 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
637 1.269 skrll OHCI_PAGE_OFFSET(sdataphys);
638 1.78 augustss /* the length must be a multiple of the max size */
639 1.260 skrll curlen -= curlen % mps;
640 1.271 skrll edataphys = DMAADDR(dma, curoffs + curlen - 1);
641 1.48 augustss }
642 1.260 skrll KASSERT(curlen != 0);
643 1.274 pgoyette DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx "
644 1.274 pgoyette "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen);
645 1.48 augustss
646 1.77 augustss cur->td.td_flags = tdflags;
647 1.260 skrll cur->td.td_cbp = HTOO32(sdataphys);
648 1.260 skrll cur->td.td_be = HTOO32(edataphys);
649 1.260 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
650 1.48 augustss cur->nexttd = next;
651 1.48 augustss cur->len = curlen;
652 1.48 augustss cur->flags = OHCI_ADD_LEN;
653 1.77 augustss cur->xfer = xfer;
654 1.260 skrll ohci_hash_add_td(sc, cur);
655 1.260 skrll
656 1.260 skrll curoffs += curlen;
657 1.260 skrll len -= curlen;
658 1.260 skrll
659 1.260 skrll if (len != 0) {
660 1.260 skrll KASSERT(next != NULL);
661 1.260 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
662 1.272 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
663 1.272 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
664 1.272 skrll
665 1.260 skrll cur = next;
666 1.260 skrll }
667 1.48 augustss }
668 1.260 skrll cur->td.td_flags |=
669 1.262 skrll HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
670 1.260 skrll
671 1.260 skrll if (!rd &&
672 1.260 skrll (flags & USBD_FORCE_SHORT_XFER) &&
673 1.260 skrll alen % mps == 0) {
674 1.272 skrll /* We're adding a ZLP so sync the previous TD */
675 1.272 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
676 1.272 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
677 1.272 skrll
678 1.61 augustss /* Force a 0 length transfer at the end. */
679 1.75 augustss
680 1.260 skrll KASSERT(next != NULL);
681 1.75 augustss cur = next;
682 1.61 augustss
683 1.77 augustss cur->td.td_flags = tdflags;
684 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
685 1.260 skrll cur->td.td_nexttd = 0;
686 1.75 augustss cur->td.td_be = ~0;
687 1.260 skrll cur->nexttd = NULL;
688 1.61 augustss cur->len = 0;
689 1.61 augustss cur->flags = 0;
690 1.77 augustss cur->xfer = xfer;
691 1.260 skrll ohci_hash_add_td(sc, cur);
692 1.260 skrll
693 1.260 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
694 1.61 augustss }
695 1.272 skrll
696 1.272 skrll /* Last TD gets usb_syncmem'ed by caller */
697 1.77 augustss *ep = cur;
698 1.48 augustss }
699 1.48 augustss
700 1.60 augustss ohci_soft_itd_t *
701 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
702 1.60 augustss {
703 1.60 augustss ohci_soft_itd_t *sitd;
704 1.60 augustss usbd_status err;
705 1.224 mrg int i, offs;
706 1.60 augustss usb_dma_t dma;
707 1.60 augustss
708 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
709 1.260 skrll
710 1.260 skrll mutex_enter(&sc->sc_lock);
711 1.60 augustss if (sc->sc_freeitds == NULL) {
712 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
713 1.260 skrll mutex_exit(&sc->sc_lock);
714 1.260 skrll
715 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
716 1.83 augustss OHCI_ITD_ALIGN, &dma);
717 1.60 augustss if (err)
718 1.260 skrll return NULL;
719 1.260 skrll mutex_enter(&sc->sc_lock);
720 1.259 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
721 1.83 augustss offs = i * OHCI_SITD_SIZE;
722 1.123 augustss sitd = KERNADDR(&dma, offs);
723 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
724 1.195 bouyer sitd->dma = dma;
725 1.195 bouyer sitd->offs = offs;
726 1.60 augustss sitd->nextitd = sc->sc_freeitds;
727 1.60 augustss sc->sc_freeitds = sitd;
728 1.60 augustss }
729 1.60 augustss }
730 1.83 augustss
731 1.60 augustss sitd = sc->sc_freeitds;
732 1.60 augustss sc->sc_freeitds = sitd->nextitd;
733 1.260 skrll mutex_exit(&sc->sc_lock);
734 1.260 skrll
735 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
736 1.83 augustss sitd->nextitd = NULL;
737 1.83 augustss sitd->xfer = NULL;
738 1.83 augustss
739 1.83 augustss #ifdef DIAGNOSTIC
740 1.260 skrll sitd->isdone = true;
741 1.83 augustss #endif
742 1.83 augustss
743 1.260 skrll return sitd;
744 1.60 augustss }
745 1.60 augustss
746 1.260 skrll Static void
747 1.260 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
748 1.60 augustss {
749 1.83 augustss
750 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
751 1.274 pgoyette DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0);
752 1.83 augustss
753 1.260 skrll KASSERT(sitd->isdone);
754 1.83 augustss #ifdef DIAGNOSTIC
755 1.134 toshii /* Warn double free */
756 1.260 skrll sitd->isdone = false;
757 1.83 augustss #endif
758 1.83 augustss
759 1.60 augustss sitd->nextitd = sc->sc_freeitds;
760 1.60 augustss sc->sc_freeitds = sitd;
761 1.60 augustss }
762 1.60 augustss
763 1.260 skrll void
764 1.260 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
765 1.260 skrll {
766 1.260 skrll
767 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
768 1.260 skrll
769 1.260 skrll mutex_enter(&sc->sc_lock);
770 1.260 skrll ohci_free_sitd_locked(sc, sitd);
771 1.260 skrll mutex_exit(&sc->sc_lock);
772 1.260 skrll }
773 1.260 skrll
774 1.260 skrll int
775 1.91 augustss ohci_init(ohci_softc_t *sc)
776 1.1 augustss {
777 1.1 augustss ohci_soft_ed_t *sed, *psed;
778 1.53 augustss usbd_status err;
779 1.1 augustss int i;
780 1.260 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
781 1.260 skrll
782 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
783 1.16 augustss
784 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
785 1.199 jmcneill
786 1.198 cegger sc->sc_hcca = NULL;
787 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
788 1.224 mrg
789 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
790 1.256 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
791 1.224 mrg cv_init(&sc->sc_softwake_cv, "ohciab");
792 1.224 mrg
793 1.264 skrll sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
794 1.224 mrg ohci_rhsc_softint, sc);
795 1.198 cegger
796 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
797 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
798 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
799 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
800 1.198 cegger
801 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
802 1.232 christos "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
803 1.198 cegger
804 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
805 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
806 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
807 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
808 1.55 augustss
809 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
810 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
811 1.260 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
812 1.260 skrll return -1;
813 1.1 augustss }
814 1.260 skrll sc->sc_bus.ub_revision = USBREV_1_0;
815 1.260 skrll sc->sc_bus.ub_usedma = true;
816 1.153 fvdl
817 1.73 augustss /* XXX determine alignment by R/W */
818 1.1 augustss /* Allocate the HCCA area. */
819 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
820 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
821 1.198 cegger if (err) {
822 1.198 cegger sc->sc_hcca = NULL;
823 1.198 cegger return err;
824 1.198 cegger }
825 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
826 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
827 1.1 augustss
828 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
829 1.1 augustss
830 1.60 augustss /* Allocate dummy ED that starts the control list. */
831 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
832 1.53 augustss if (sc->sc_ctrl_head == NULL) {
833 1.260 skrll err = ENOMEM;
834 1.1 augustss goto bad1;
835 1.1 augustss }
836 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
837 1.34 augustss
838 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
839 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
840 1.53 augustss if (sc->sc_bulk_head == NULL) {
841 1.260 skrll err = ENOMEM;
842 1.1 augustss goto bad2;
843 1.1 augustss }
844 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
845 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
846 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
847 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
848 1.1 augustss
849 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
850 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
851 1.60 augustss if (sc->sc_isoc_head == NULL) {
852 1.260 skrll err = ENOMEM;
853 1.60 augustss goto bad3;
854 1.60 augustss }
855 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
856 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
857 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
858 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
859 1.60 augustss
860 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
861 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
862 1.1 augustss sed = ohci_alloc_sed(sc);
863 1.53 augustss if (sed == NULL) {
864 1.1 augustss while (--i >= 0)
865 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
866 1.260 skrll err = ENOMEM;
867 1.60 augustss goto bad4;
868 1.1 augustss }
869 1.1 augustss /* All ED fields are set to 0. */
870 1.1 augustss sc->sc_eds[i] = sed;
871 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
872 1.60 augustss if (i != 0)
873 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
874 1.60 augustss else
875 1.60 augustss psed= sc->sc_isoc_head;
876 1.60 augustss sed->next = psed;
877 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
878 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
879 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
880 1.1 augustss }
881 1.120 augustss /*
882 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
883 1.1 augustss * the tree set up properly to spread the interrupts.
884 1.1 augustss */
885 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
886 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
887 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
888 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
889 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
890 1.1 augustss
891 1.73 augustss #ifdef OHCI_DEBUG
892 1.260 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
893 1.260 skrll if (ohcidebug >= 15) {
894 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
895 1.274 pgoyette DPRINTFN(15, "ed#%jd ", i, 0, 0, 0);
896 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
897 1.73 augustss }
898 1.260 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
899 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
900 1.73 augustss }
901 1.260 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
902 1.73 augustss #endif
903 1.73 augustss
904 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
905 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
906 1.161 augustss rwc = ctl & OHCI_RWC;
907 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
908 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
909 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
910 1.161 augustss
911 1.1 augustss /* Determine in what context we are running. */
912 1.1 augustss if (ctl & OHCI_IR) {
913 1.1 augustss /* SMM active, request change */
914 1.260 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
915 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
916 1.160 augustss (OHCI_OC | OHCI_MIE))
917 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
918 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
919 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
920 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
921 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
922 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
923 1.1 augustss }
924 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
925 1.1 augustss if ((ctl & OHCI_IR) == 0) {
926 1.199 jmcneill aprint_error_dev(sc->sc_dev,
927 1.199 jmcneill "SMM does not respond, resetting\n");
928 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
929 1.1 augustss goto reset;
930 1.1 augustss }
931 1.103 augustss #if 0
932 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
933 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
934 1.1 augustss /* BIOS started controller. */
935 1.260 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
936 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
937 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
938 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
939 1.1 augustss }
940 1.103 augustss #endif
941 1.1 augustss } else {
942 1.260 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
943 1.1 augustss reset:
944 1.1 augustss /* Controller was cold started. */
945 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
946 1.1 augustss }
947 1.1 augustss
948 1.16 augustss /*
949 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
950 1.25 augustss * without it some controllers do not start.
951 1.16 augustss */
952 1.274 pgoyette DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0);
953 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
954 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
955 1.16 augustss
956 1.1 augustss /* We now own the host controller and the bus has been reset. */
957 1.1 augustss
958 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
959 1.1 augustss /* Nominal time for a reset is 10 us. */
960 1.1 augustss for (i = 0; i < 10; i++) {
961 1.1 augustss delay(10);
962 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
963 1.1 augustss if (!hcr)
964 1.1 augustss break;
965 1.1 augustss }
966 1.1 augustss if (hcr) {
967 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
968 1.260 skrll err = EIO;
969 1.60 augustss goto bad5;
970 1.1 augustss }
971 1.52 augustss #ifdef OHCI_DEBUG
972 1.260 skrll if (ohcidebug >= 15)
973 1.1 augustss ohci_dumpregs(sc);
974 1.1 augustss #endif
975 1.1 augustss
976 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
977 1.1 augustss
978 1.1 augustss /* Set up HC registers. */
979 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
980 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
981 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
982 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
983 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
984 1.55 augustss /* switch on desired functional features */
985 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
986 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
987 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
988 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
989 1.1 augustss /* And finally start it! */
990 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
991 1.1 augustss
992 1.1 augustss /*
993 1.1 augustss * The controller is now OPERATIONAL. Set a some final
994 1.1 augustss * registers that should be set earlier, but that the
995 1.1 augustss * controller ignores when in the SUSPEND state.
996 1.1 augustss */
997 1.161 augustss ival = OHCI_GET_IVAL(fm);
998 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
999 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
1000 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
1001 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
1002 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
1003 1.1 augustss
1004 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
1005 1.249 skrll /* no overcurrent protection */
1006 1.249 skrll desca |= OHCI_NOCP;
1007 1.249 skrll /*
1008 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1009 1.249 skrll * that
1010 1.249 skrll * - ports are always power switched
1011 1.249 skrll * - don't wait for powered root hub port
1012 1.249 skrll */
1013 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1014 1.249 skrll }
1015 1.249 skrll
1016 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1017 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1018 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1019 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1020 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1021 1.1 augustss
1022 1.85 augustss /*
1023 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1024 1.85 augustss * otherwise it will occasionally report 0 ports.
1025 1.85 augustss */
1026 1.145 augustss sc->sc_noport = 0;
1027 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1028 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1029 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1030 1.145 augustss }
1031 1.1 augustss
1032 1.52 augustss #ifdef OHCI_DEBUG
1033 1.260 skrll if (ohcidebug >= 5)
1034 1.1 augustss ohci_dumpregs(sc);
1035 1.1 augustss #endif
1036 1.120 augustss
1037 1.1 augustss /* Set up the bus struct. */
1038 1.260 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1039 1.260 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1040 1.1 augustss
1041 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1042 1.59 augustss
1043 1.167 augustss /* Finally, turn on interrupts. */
1044 1.274 pgoyette DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1045 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1046 1.167 augustss
1047 1.260 skrll return 0;
1048 1.1 augustss
1049 1.60 augustss bad5:
1050 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1051 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1052 1.60 augustss bad4:
1053 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1054 1.1 augustss bad3:
1055 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1056 1.144 augustss bad2:
1057 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1058 1.1 augustss bad1:
1059 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1060 1.198 cegger sc->sc_hcca = NULL;
1061 1.260 skrll return err;
1062 1.62 augustss }
1063 1.62 augustss
1064 1.260 skrll struct usbd_xfer *
1065 1.260 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1066 1.62 augustss {
1067 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1068 1.260 skrll struct usbd_xfer *xfer;
1069 1.62 augustss
1070 1.276 skrll xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1071 1.118 augustss if (xfer != NULL) {
1072 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1073 1.118 augustss #ifdef DIAGNOSTIC
1074 1.260 skrll xfer->ux_state = XFER_BUSY;
1075 1.118 augustss #endif
1076 1.118 augustss }
1077 1.260 skrll return xfer;
1078 1.62 augustss }
1079 1.62 augustss
1080 1.62 augustss void
1081 1.260 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1082 1.62 augustss {
1083 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1084 1.62 augustss
1085 1.260 skrll KASSERTMSG(xfer->ux_state == XFER_BUSY,
1086 1.260 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1087 1.118 augustss #ifdef DIAGNOSTIC
1088 1.260 skrll xfer->ux_state = XFER_FREE;
1089 1.118 augustss #endif
1090 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1091 1.42 augustss }
1092 1.42 augustss
1093 1.224 mrg Static void
1094 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1095 1.224 mrg {
1096 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1097 1.224 mrg
1098 1.224 mrg *lock = &sc->sc_lock;
1099 1.224 mrg }
1100 1.224 mrg
1101 1.59 augustss /*
1102 1.59 augustss * Shut down the controller when the system is going down.
1103 1.59 augustss */
1104 1.188 dyoung bool
1105 1.188 dyoung ohci_shutdown(device_t self, int flags)
1106 1.59 augustss {
1107 1.188 dyoung ohci_softc_t *sc = device_private(self);
1108 1.59 augustss
1109 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1110 1.260 skrll
1111 1.260 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1112 1.277 msaitoh OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
1113 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1114 1.188 dyoung return true;
1115 1.59 augustss }
1116 1.59 augustss
1117 1.185 jmcneill bool
1118 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1119 1.33 augustss {
1120 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1121 1.185 jmcneill uint32_t ctl;
1122 1.33 augustss
1123 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1124 1.260 skrll sc->sc_bus.ub_usepolling++;
1125 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1126 1.224 mrg
1127 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1128 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1129 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1130 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1131 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1132 1.185 jmcneill sc->sc_bulk_head->physaddr);
1133 1.185 jmcneill if (sc->sc_intre)
1134 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1135 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1136 1.185 jmcneill if (sc->sc_control)
1137 1.185 jmcneill ctl = sc->sc_control;
1138 1.185 jmcneill else
1139 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1140 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1141 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1142 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1143 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1144 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1145 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1146 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1147 1.224 mrg
1148 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1149 1.260 skrll sc->sc_bus.ub_usepolling--;
1150 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1151 1.185 jmcneill
1152 1.185 jmcneill return true;
1153 1.185 jmcneill }
1154 1.185 jmcneill
1155 1.185 jmcneill bool
1156 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1157 1.185 jmcneill {
1158 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1159 1.185 jmcneill uint32_t ctl;
1160 1.95 augustss
1161 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1162 1.260 skrll sc->sc_bus.ub_usepolling++;
1163 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1164 1.224 mrg
1165 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1166 1.185 jmcneill if (sc->sc_control == 0) {
1167 1.185 jmcneill /*
1168 1.185 jmcneill * Preserve register values, in case that BIOS
1169 1.185 jmcneill * does not recover them.
1170 1.185 jmcneill */
1171 1.185 jmcneill sc->sc_control = ctl;
1172 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1173 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1174 1.95 augustss }
1175 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1176 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1177 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1178 1.224 mrg
1179 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1180 1.260 skrll sc->sc_bus.ub_usepolling--;
1181 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1182 1.185 jmcneill
1183 1.185 jmcneill return true;
1184 1.33 augustss }
1185 1.33 augustss
1186 1.52 augustss #ifdef OHCI_DEBUG
1187 1.1 augustss void
1188 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1189 1.1 augustss {
1190 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1191 1.260 skrll
1192 1.274 pgoyette DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx",
1193 1.41 augustss OREAD4(sc, OHCI_REVISION),
1194 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1195 1.260 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1196 1.274 pgoyette DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx",
1197 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1198 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1199 1.260 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1200 1.274 pgoyette DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx",
1201 1.41 augustss OREAD4(sc, OHCI_HCCA),
1202 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1203 1.260 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1204 1.274 pgoyette DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx",
1205 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1206 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1207 1.260 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1208 1.274 pgoyette DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx",
1209 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1210 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1211 1.260 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1212 1.274 pgoyette DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx",
1213 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1214 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1215 1.260 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1216 1.274 pgoyette DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx",
1217 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1218 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1219 1.260 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1220 1.274 pgoyette DPRINTF(" port1=0x%08jx port2=0x%08jx",
1221 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1222 1.260 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1223 1.274 pgoyette DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx",
1224 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1225 1.260 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1226 1.1 augustss }
1227 1.1 augustss #endif
1228 1.1 augustss
1229 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1230 1.53 augustss
1231 1.1 augustss int
1232 1.91 augustss ohci_intr(void *p)
1233 1.1 augustss {
1234 1.1 augustss ohci_softc_t *sc = p;
1235 1.224 mrg int ret = 0;
1236 1.111 augustss
1237 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1238 1.260 skrll
1239 1.224 mrg if (sc == NULL)
1240 1.260 skrll return 0;
1241 1.53 augustss
1242 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1243 1.224 mrg
1244 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1245 1.224 mrg goto done;
1246 1.224 mrg
1247 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1248 1.260 skrll if (sc->sc_bus.ub_usepolling) {
1249 1.260 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1250 1.154 joff /* for level triggered intrs, should do something to ack */
1251 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1252 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1253 1.155 perry
1254 1.224 mrg goto done;
1255 1.57 augustss }
1256 1.53 augustss
1257 1.224 mrg ret = ohci_intr1(sc);
1258 1.224 mrg
1259 1.224 mrg done:
1260 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1261 1.224 mrg return ret;
1262 1.53 augustss }
1263 1.53 augustss
1264 1.82 augustss Static int
1265 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1266 1.53 augustss {
1267 1.260 skrll uint32_t intrs, eintrs;
1268 1.1 augustss
1269 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1270 1.105 augustss
1271 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1272 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1273 1.15 augustss #ifdef DIAGNOSTIC
1274 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1275 1.15 augustss #endif
1276 1.260 skrll return 0;
1277 1.15 augustss }
1278 1.15 augustss
1279 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1280 1.224 mrg
1281 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1282 1.1 augustss if (!intrs)
1283 1.260 skrll return 0;
1284 1.55 augustss
1285 1.260 skrll /* Acknowledge */
1286 1.260 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1287 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1288 1.274 pgoyette DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1289 1.274 pgoyette DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)",
1290 1.260 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1291 1.260 skrll sc->sc_eintrs);
1292 1.211 matt
1293 1.211 matt if (!eintrs) {
1294 1.260 skrll return 0;
1295 1.211 matt }
1296 1.1 augustss
1297 1.1 augustss if (eintrs & OHCI_SO) {
1298 1.100 augustss sc->sc_overrun_cnt++;
1299 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1300 1.100 augustss printf("%s: %u scheduling overruns\n",
1301 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1302 1.100 augustss sc->sc_overrun_cnt = 0;
1303 1.100 augustss }
1304 1.1 augustss /* XXX do what */
1305 1.106 augustss eintrs &= ~OHCI_SO;
1306 1.1 augustss }
1307 1.1 augustss if (eintrs & OHCI_WDH) {
1308 1.157 mycroft /*
1309 1.157 mycroft * We block the interrupt below, and reenable it later from
1310 1.157 mycroft * ohci_softintr().
1311 1.157 mycroft */
1312 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1313 1.1 augustss }
1314 1.1 augustss if (eintrs & OHCI_RD) {
1315 1.275 skrll DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1316 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1317 1.1 augustss /* XXX process resume detect */
1318 1.1 augustss }
1319 1.1 augustss if (eintrs & OHCI_UE) {
1320 1.275 skrll DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1321 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1322 1.190 drochner device_xname(sc->sc_dev));
1323 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1324 1.1 augustss /* XXX what else */
1325 1.1 augustss }
1326 1.1 augustss if (eintrs & OHCI_RHSC) {
1327 1.120 augustss /*
1328 1.157 mycroft * We block the interrupt below, and reenable it later from
1329 1.157 mycroft * a timeout.
1330 1.1 augustss */
1331 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1332 1.1 augustss }
1333 1.1 augustss
1334 1.106 augustss if (eintrs != 0) {
1335 1.157 mycroft /* Block unprocessed interrupts. */
1336 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1337 1.106 augustss sc->sc_eintrs &= ~eintrs;
1338 1.274 pgoyette DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc,
1339 1.274 pgoyette eintrs, 0, 0);
1340 1.106 augustss }
1341 1.1 augustss
1342 1.260 skrll return 1;
1343 1.1 augustss }
1344 1.1 augustss
1345 1.1 augustss void
1346 1.104 augustss ohci_rhsc_enable(void *v_sc)
1347 1.104 augustss {
1348 1.104 augustss ohci_softc_t *sc = v_sc;
1349 1.104 augustss
1350 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1351 1.274 pgoyette DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0);
1352 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1353 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1354 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1355 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1356 1.1 augustss }
1357 1.1 augustss
1358 1.52 augustss #ifdef OHCI_DEBUG
1359 1.166 drochner const char *ohci_cc_strs[] = {
1360 1.13 augustss "NO_ERROR",
1361 1.13 augustss "CRC",
1362 1.13 augustss "BIT_STUFFING",
1363 1.13 augustss "DATA_TOGGLE_MISMATCH",
1364 1.13 augustss "STALL",
1365 1.13 augustss "DEVICE_NOT_RESPONDING",
1366 1.13 augustss "PID_CHECK_FAILURE",
1367 1.13 augustss "UNEXPECTED_PID",
1368 1.13 augustss "DATA_OVERRUN",
1369 1.13 augustss "DATA_UNDERRUN",
1370 1.13 augustss "BUFFER_OVERRUN",
1371 1.13 augustss "BUFFER_UNDERRUN",
1372 1.67 augustss "reserved",
1373 1.67 augustss "reserved",
1374 1.67 augustss "NOT_ACCESSED",
1375 1.13 augustss "NOT_ACCESSED",
1376 1.13 augustss };
1377 1.13 augustss #endif
1378 1.13 augustss
1379 1.1 augustss void
1380 1.157 mycroft ohci_softintr(void *v)
1381 1.83 augustss {
1382 1.190 drochner struct usbd_bus *bus = v;
1383 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1384 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1385 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1386 1.260 skrll struct usbd_xfer *xfer;
1387 1.157 mycroft struct ohci_pipe *opipe;
1388 1.224 mrg int len, cc;
1389 1.157 mycroft int i, j, actlen, iframes, uedir;
1390 1.157 mycroft ohci_physaddr_t done;
1391 1.157 mycroft
1392 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1393 1.224 mrg
1394 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1395 1.157 mycroft
1396 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1397 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1398 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1399 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1400 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1401 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1402 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1403 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1404 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1405 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1406 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1407 1.83 augustss
1408 1.83 augustss /* Reverse the done list. */
1409 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1410 1.83 augustss std = ohci_hash_find_td(sc, done);
1411 1.83 augustss if (std != NULL) {
1412 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1413 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1414 1.83 augustss std->dnext = sdone;
1415 1.168 augustss done = O32TOH(std->td.td_nexttd);
1416 1.83 augustss sdone = std;
1417 1.274 pgoyette DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0);
1418 1.83 augustss continue;
1419 1.83 augustss }
1420 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1421 1.83 augustss if (sitd != NULL) {
1422 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1423 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1424 1.83 augustss sitd->dnext = sidone;
1425 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1426 1.83 augustss sidone = sitd;
1427 1.274 pgoyette DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0);
1428 1.83 augustss continue;
1429 1.83 augustss }
1430 1.274 pgoyette DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0);
1431 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1432 1.218 jmcneill (u_long)done);
1433 1.218 jmcneill break;
1434 1.83 augustss }
1435 1.83 augustss
1436 1.274 pgoyette DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone,
1437 1.274 pgoyette (uintptr_t)sidone, 0, 0);
1438 1.260 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1439 1.52 augustss #ifdef OHCI_DEBUG
1440 1.260 skrll if (ohcidebug >= 10) {
1441 1.234 skrll for (std = sdone; std; std = std->dnext)
1442 1.258 skrll ohci_dump_td(sc, std);
1443 1.1 augustss }
1444 1.1 augustss #endif
1445 1.260 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1446 1.1 augustss
1447 1.48 augustss for (std = sdone; std; std = stdnext) {
1448 1.53 augustss xfer = std->xfer;
1449 1.48 augustss stdnext = std->dnext;
1450 1.274 pgoyette DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std,
1451 1.274 pgoyette (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0),
1452 1.274 pgoyette 0);
1453 1.71 augustss if (xfer == NULL) {
1454 1.117 augustss /*
1455 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1456 1.71 augustss * with this TD. It is tailp that happened to end up on
1457 1.71 augustss * the done queue.
1458 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1459 1.71 augustss */
1460 1.71 augustss continue;
1461 1.71 augustss }
1462 1.260 skrll if (xfer->ux_status == USBD_CANCELLED ||
1463 1.260 skrll xfer->ux_status == USBD_TIMEOUT) {
1464 1.274 pgoyette DPRINTF("cancel/timeout %#jx", (uintptr_t)xfer, 0, 0,
1465 1.274 pgoyette 0);
1466 1.38 augustss /* Handled by abort routine. */
1467 1.83 augustss continue;
1468 1.83 augustss }
1469 1.260 skrll callout_stop(&xfer->ux_callout);
1470 1.141 mycroft
1471 1.141 mycroft len = std->len;
1472 1.141 mycroft if (std->td.td_cbp != 0)
1473 1.168 augustss len -= O32TOH(std->td.td_be) -
1474 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1475 1.274 pgoyette DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0);
1476 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1477 1.260 skrll xfer->ux_actlen += len;
1478 1.141 mycroft
1479 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1480 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1481 1.260 skrll ohci_hash_rem_td(sc, std);
1482 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1483 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1484 1.53 augustss usb_transfer_complete(xfer);
1485 1.21 augustss }
1486 1.1 augustss } else {
1487 1.48 augustss /*
1488 1.48 augustss * Endpoint is halted. First unlink all the TDs
1489 1.48 augustss * belonging to the failed transfer, and then restart
1490 1.48 augustss * the endpoint.
1491 1.48 augustss */
1492 1.1 augustss ohci_soft_td_t *p, *n;
1493 1.260 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1494 1.48 augustss
1495 1.274 pgoyette DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0);
1496 1.48 augustss
1497 1.260 skrll /* remove xfer's TDs from the hash */
1498 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1499 1.1 augustss n = p->nexttd;
1500 1.260 skrll ohci_hash_rem_td(sc, p);
1501 1.1 augustss }
1502 1.48 augustss
1503 1.260 skrll ohci_soft_ed_t *sed = opipe->sed;
1504 1.260 skrll
1505 1.260 skrll /* clear halt and TD chain */
1506 1.260 skrll sed->ed.ed_headp = HTOO32(p->physaddr);
1507 1.260 skrll usb_syncmem(&sed->dma,
1508 1.260 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1509 1.260 skrll sizeof(sed->ed.ed_headp),
1510 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1511 1.260 skrll
1512 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1513 1.48 augustss
1514 1.260 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1515 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1516 1.260 skrll else if (cc == OHCI_CC_STALL)
1517 1.260 skrll xfer->ux_status = USBD_STALLED;
1518 1.1 augustss else
1519 1.260 skrll xfer->ux_status = USBD_IOERROR;
1520 1.53 augustss usb_transfer_complete(xfer);
1521 1.1 augustss }
1522 1.1 augustss }
1523 1.260 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1524 1.83 augustss #ifdef OHCI_DEBUG
1525 1.260 skrll if (ohcidebug >= 10) {
1526 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1527 1.258 skrll ohci_dump_itd(sc, sitd);
1528 1.83 augustss }
1529 1.83 augustss #endif
1530 1.260 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1531 1.83 augustss
1532 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1533 1.83 augustss xfer = sitd->xfer;
1534 1.83 augustss sitdnext = sitd->dnext;
1535 1.274 pgoyette DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd,
1536 1.274 pgoyette (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0),
1537 1.274 pgoyette 0);
1538 1.83 augustss if (xfer == NULL)
1539 1.83 augustss continue;
1540 1.260 skrll if (xfer->ux_status == USBD_CANCELLED ||
1541 1.260 skrll xfer->ux_status == USBD_TIMEOUT) {
1542 1.274 pgoyette DPRINTF("cancel/timeout %#jx",
1543 1.274 pgoyette (uintptr_t)xfer, 0, 0, 0);
1544 1.83 augustss /* Handled by abort routine. */
1545 1.83 augustss continue;
1546 1.83 augustss }
1547 1.260 skrll KASSERT(!sitd->isdone);
1548 1.83 augustss #ifdef DIAGNOSTIC
1549 1.260 skrll sitd->isdone = true;
1550 1.83 augustss #endif
1551 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1552 1.134 toshii ohci_soft_itd_t *next;
1553 1.134 toshii
1554 1.260 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1555 1.260 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1556 1.260 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1557 1.134 toshii bEndpointAddress);
1558 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1559 1.134 toshii actlen = 0;
1560 1.260 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1561 1.134 toshii sitd = next) {
1562 1.134 toshii next = sitd->nextitd;
1563 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1564 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1565 1.260 skrll xfer->ux_status = USBD_IOERROR;
1566 1.134 toshii /* For input, update frlengths with actual */
1567 1.134 toshii /* XXX anything necessary for output? */
1568 1.134 toshii if (uedir == UE_DIR_IN &&
1569 1.260 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1570 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1571 1.135 toshii sitd->itd.itd_flags));
1572 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1573 1.168 augustss len = O16TOH(sitd->
1574 1.134 toshii itd.itd_offset[j]);
1575 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1576 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1577 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1578 1.158 toshii len = 0;
1579 1.158 toshii else
1580 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1581 1.260 skrll xfer->ux_frlengths[i] = len;
1582 1.134 toshii actlen += len;
1583 1.134 toshii }
1584 1.134 toshii }
1585 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1586 1.134 toshii break;
1587 1.260 skrll ohci_hash_rem_itd(sc, sitd);
1588 1.260 skrll
1589 1.83 augustss }
1590 1.260 skrll ohci_hash_rem_itd(sc, sitd);
1591 1.134 toshii if (uedir == UE_DIR_IN &&
1592 1.260 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1593 1.260 skrll xfer->ux_actlen = actlen;
1594 1.260 skrll xfer->ux_hcpriv = NULL;
1595 1.134 toshii
1596 1.83 augustss usb_transfer_complete(xfer);
1597 1.83 augustss }
1598 1.83 augustss }
1599 1.83 augustss
1600 1.119 augustss if (sc->sc_softwake) {
1601 1.119 augustss sc->sc_softwake = 0;
1602 1.224 mrg cv_broadcast(&sc->sc_softwake_cv);
1603 1.119 augustss }
1604 1.119 augustss
1605 1.260 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1606 1.1 augustss }
1607 1.1 augustss
1608 1.1 augustss void
1609 1.260 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1610 1.1 augustss {
1611 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1612 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1613 1.260 skrll int len = UGETW(xfer->ux_request.wLength);
1614 1.260 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1615 1.195 bouyer
1616 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1617 1.274 pgoyette DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
1618 1.1 augustss
1619 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1620 1.260 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1621 1.224 mrg
1622 1.195 bouyer if (len)
1623 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1624 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1625 1.260 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1626 1.260 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1627 1.1 augustss }
1628 1.1 augustss
1629 1.1 augustss void
1630 1.260 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1631 1.1 augustss {
1632 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1633 1.195 bouyer int isread =
1634 1.260 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1635 1.1 augustss
1636 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1637 1.274 pgoyette DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer,
1638 1.274 pgoyette xfer->ux_actlen, 0, 0);
1639 1.1 augustss
1640 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1641 1.224 mrg
1642 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1643 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1644 1.1 augustss }
1645 1.1 augustss
1646 1.1 augustss void
1647 1.260 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1648 1.3 augustss {
1649 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1650 1.260 skrll
1651 1.195 bouyer int isread =
1652 1.260 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1653 1.195 bouyer
1654 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1655 1.224 mrg
1656 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1657 1.274 pgoyette DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen,
1658 1.274 pgoyette 0, 0);
1659 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1660 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1661 1.3 augustss }
1662 1.3 augustss
1663 1.224 mrg Static void
1664 1.224 mrg ohci_rhsc_softint(void *arg)
1665 1.224 mrg {
1666 1.224 mrg ohci_softc_t *sc = arg;
1667 1.224 mrg
1668 1.224 mrg mutex_enter(&sc->sc_lock);
1669 1.224 mrg
1670 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1671 1.224 mrg
1672 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1673 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1674 1.224 mrg
1675 1.224 mrg mutex_exit(&sc->sc_lock);
1676 1.224 mrg }
1677 1.224 mrg
1678 1.3 augustss void
1679 1.260 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1680 1.1 augustss {
1681 1.1 augustss u_char *p;
1682 1.1 augustss int i, m;
1683 1.243 martin int hstatus __unused;
1684 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1685 1.1 augustss
1686 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1687 1.224 mrg
1688 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1689 1.274 pgoyette DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc,
1690 1.274 pgoyette (uintptr_t)xfer, hstatus, 0);
1691 1.1 augustss
1692 1.53 augustss if (xfer == NULL) {
1693 1.1 augustss /* Just ignore the change. */
1694 1.1 augustss return;
1695 1.1 augustss }
1696 1.1 augustss
1697 1.260 skrll p = xfer->ux_buf;
1698 1.260 skrll m = min(sc->sc_noport, xfer->ux_length * 8 - 1);
1699 1.260 skrll memset(p, 0, xfer->ux_length);
1700 1.1 augustss for (i = 1; i <= m; i++) {
1701 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1702 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1703 1.1 augustss p[i/8] |= 1 << (i%8);
1704 1.1 augustss }
1705 1.274 pgoyette DPRINTF("change=0x%02jx", *p, 0, 0, 0);
1706 1.260 skrll xfer->ux_actlen = xfer->ux_length;
1707 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1708 1.1 augustss
1709 1.53 augustss usb_transfer_complete(xfer);
1710 1.38 augustss }
1711 1.38 augustss
1712 1.38 augustss void
1713 1.260 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1714 1.65 augustss {
1715 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1716 1.260 skrll
1717 1.260 skrll KASSERT(mutex_owned(&sc->sc_lock));
1718 1.65 augustss
1719 1.260 skrll KASSERT(sc->sc_intrxfer == xfer);
1720 1.260 skrll sc->sc_intrxfer = NULL;
1721 1.1 augustss }
1722 1.1 augustss
1723 1.5 augustss void
1724 1.91 augustss ohci_poll(struct usbd_bus *bus)
1725 1.5 augustss {
1726 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1727 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1728 1.260 skrll
1729 1.105 augustss #ifdef OHCI_DEBUG
1730 1.105 augustss static int last;
1731 1.105 augustss int new;
1732 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1733 1.105 augustss if (new != last) {
1734 1.274 pgoyette DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0);
1735 1.105 augustss last = new;
1736 1.105 augustss }
1737 1.105 augustss #endif
1738 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1739 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1740 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1741 1.53 augustss ohci_intr1(sc);
1742 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1743 1.224 mrg }
1744 1.1 augustss }
1745 1.1 augustss
1746 1.260 skrll /*
1747 1.260 skrll * Add an ED to the schedule. Called with USB lock held.
1748 1.260 skrll */
1749 1.260 skrll Static void
1750 1.260 skrll ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1751 1.1 augustss {
1752 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1753 1.274 pgoyette DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0,
1754 1.274 pgoyette 0);
1755 1.224 mrg
1756 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1757 1.1 augustss
1758 1.260 skrll usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1759 1.260 skrll sizeof(head->ed.ed_nexted),
1760 1.260 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1761 1.260 skrll sed->next = head->next;
1762 1.260 skrll sed->ed.ed_nexted = head->ed.ed_nexted;
1763 1.260 skrll usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1764 1.260 skrll sizeof(sed->ed.ed_nexted),
1765 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1766 1.260 skrll head->next = sed;
1767 1.260 skrll head->ed.ed_nexted = HTOO32(sed->physaddr);
1768 1.260 skrll usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1769 1.260 skrll sizeof(head->ed.ed_nexted),
1770 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1771 1.260 skrll }
1772 1.1 augustss
1773 1.260 skrll /*
1774 1.260 skrll * Remove an ED from the schedule. Called with USB lock held.
1775 1.260 skrll */
1776 1.260 skrll Static void
1777 1.260 skrll ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1778 1.260 skrll {
1779 1.260 skrll ohci_soft_ed_t *p;
1780 1.1 augustss
1781 1.260 skrll KASSERT(mutex_owned(&sc->sc_lock));
1782 1.1 augustss
1783 1.260 skrll /* XXX */
1784 1.260 skrll for (p = head; p != NULL && p->next != sed; p = p->next)
1785 1.3 augustss ;
1786 1.255 skrll KASSERT(p != NULL);
1787 1.255 skrll
1788 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1789 1.195 bouyer sizeof(sed->ed.ed_nexted),
1790 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1791 1.3 augustss p->next = sed->next;
1792 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1793 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1794 1.195 bouyer sizeof(p->ed.ed_nexted),
1795 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1796 1.3 augustss }
1797 1.3 augustss
1798 1.3 augustss /*
1799 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1800 1.1 augustss * the host controller. This queue is the processed by software.
1801 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1802 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1803 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1804 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1805 1.1 augustss * hash value.
1806 1.1 augustss */
1807 1.1 augustss
1808 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1809 1.224 mrg /* Called with USB lock held. */
1810 1.1 augustss void
1811 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1812 1.1 augustss {
1813 1.1 augustss int h = HASH(std->physaddr);
1814 1.1 augustss
1815 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1816 1.224 mrg
1817 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1818 1.1 augustss }
1819 1.1 augustss
1820 1.224 mrg /* Called with USB lock held. */
1821 1.1 augustss void
1822 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1823 1.1 augustss {
1824 1.46 augustss
1825 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1826 1.224 mrg
1827 1.1 augustss LIST_REMOVE(std, hnext);
1828 1.1 augustss }
1829 1.1 augustss
1830 1.1 augustss ohci_soft_td_t *
1831 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1832 1.1 augustss {
1833 1.1 augustss int h = HASH(a);
1834 1.1 augustss ohci_soft_td_t *std;
1835 1.1 augustss
1836 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1837 1.53 augustss std != NULL;
1838 1.1 augustss std = LIST_NEXT(std, hnext))
1839 1.1 augustss if (std->physaddr == a)
1840 1.260 skrll return std;
1841 1.260 skrll return NULL;
1842 1.83 augustss }
1843 1.83 augustss
1844 1.224 mrg /* Called with USB lock held. */
1845 1.83 augustss void
1846 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1847 1.83 augustss {
1848 1.83 augustss int h = HASH(sitd->physaddr);
1849 1.83 augustss
1850 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1851 1.260 skrll
1852 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1853 1.224 mrg
1854 1.274 pgoyette DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx",
1855 1.274 pgoyette (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0);
1856 1.83 augustss
1857 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1858 1.83 augustss }
1859 1.83 augustss
1860 1.224 mrg /* Called with USB lock held. */
1861 1.83 augustss void
1862 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1863 1.83 augustss {
1864 1.83 augustss
1865 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1866 1.260 skrll
1867 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1868 1.224 mrg
1869 1.274 pgoyette DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd,
1870 1.274 pgoyette sitd->physaddr, 0, 0);
1871 1.83 augustss
1872 1.83 augustss LIST_REMOVE(sitd, hnext);
1873 1.83 augustss }
1874 1.83 augustss
1875 1.83 augustss ohci_soft_itd_t *
1876 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1877 1.83 augustss {
1878 1.83 augustss int h = HASH(a);
1879 1.83 augustss ohci_soft_itd_t *sitd;
1880 1.83 augustss
1881 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1882 1.83 augustss sitd != NULL;
1883 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1884 1.83 augustss if (sitd->physaddr == a)
1885 1.260 skrll return sitd;
1886 1.260 skrll return NULL;
1887 1.1 augustss }
1888 1.1 augustss
1889 1.1 augustss void
1890 1.91 augustss ohci_timeout(void *addr)
1891 1.1 augustss {
1892 1.260 skrll struct usbd_xfer *xfer = addr;
1893 1.260 skrll struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer);
1894 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1895 1.114 augustss
1896 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1897 1.274 pgoyette DPRINTF("oxfer=%#jx", (uintptr_t)oxfer, 0, 0, 0);
1898 1.114 augustss
1899 1.116 augustss if (sc->sc_dying) {
1900 1.224 mrg mutex_enter(&sc->sc_lock);
1901 1.260 skrll ohci_abort_xfer(xfer, USBD_TIMEOUT);
1902 1.224 mrg mutex_exit(&sc->sc_lock);
1903 1.116 augustss return;
1904 1.116 augustss }
1905 1.116 augustss
1906 1.114 augustss /* Execute the abort in a process context. */
1907 1.231 jmcneill usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr,
1908 1.231 jmcneill USB_TASKQ_MPSAFE);
1909 1.260 skrll usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task,
1910 1.178 joerg USB_TASKQ_HC);
1911 1.114 augustss }
1912 1.114 augustss
1913 1.114 augustss void
1914 1.114 augustss ohci_timeout_task(void *addr)
1915 1.114 augustss {
1916 1.260 skrll struct usbd_xfer *xfer = addr;
1917 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1918 1.1 augustss
1919 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1920 1.260 skrll
1921 1.274 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
1922 1.45 augustss
1923 1.224 mrg mutex_enter(&sc->sc_lock);
1924 1.54 augustss ohci_abort_xfer(xfer, USBD_TIMEOUT);
1925 1.224 mrg mutex_exit(&sc->sc_lock);
1926 1.1 augustss }
1927 1.1 augustss
1928 1.52 augustss #ifdef OHCI_DEBUG
1929 1.1 augustss void
1930 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1931 1.1 augustss {
1932 1.260 skrll for (; std; std = std->nexttd) {
1933 1.168 augustss ohci_dump_td(sc, std);
1934 1.260 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
1935 1.260 skrll "std %p next %p", std, std->nexttd);
1936 1.260 skrll }
1937 1.1 augustss }
1938 1.1 augustss
1939 1.1 augustss void
1940 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1941 1.1 augustss {
1942 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1943 1.92 tv
1944 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1945 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1946 1.260 skrll
1947 1.260 skrll uint32_t flags = O32TOH(std->td.td_flags);
1948 1.274 pgoyette DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0);
1949 1.274 pgoyette DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx",
1950 1.260 skrll !!(flags & OHCI_TD_R),
1951 1.260 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1952 1.260 skrll OHCI_TD_GET_DI(flags),
1953 1.260 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1954 1.274 pgoyette DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags),
1955 1.274 pgoyette OHCI_TD_GET_CC(flags), 0, 0);
1956 1.274 pgoyette DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx",
1957 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1958 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1959 1.260 skrll (u_long)O32TOH(std->td.td_be), 0);
1960 1.1 augustss }
1961 1.1 augustss
1962 1.1 augustss void
1963 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1964 1.83 augustss {
1965 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1966 1.83 augustss
1967 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1968 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1969 1.260 skrll
1970 1.260 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
1971 1.274 pgoyette DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0);
1972 1.274 pgoyette DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd",
1973 1.260 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
1974 1.260 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
1975 1.274 pgoyette DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx",
1976 1.260 skrll O32TOH(sitd->itd.itd_bp0),
1977 1.260 skrll O32TOH(sitd->itd.itd_nextitd),
1978 1.260 skrll O32TOH(sitd->itd.itd_be), 0);
1979 1.260 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
1980 1.274 pgoyette DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx "
1981 1.274 pgoyette "offs[2] = 0x%04jx offs[3] = 0x%04jx",
1982 1.260 skrll O16TOH(sitd->itd.itd_offset[0]),
1983 1.260 skrll O16TOH(sitd->itd.itd_offset[1]),
1984 1.260 skrll O16TOH(sitd->itd.itd_offset[2]),
1985 1.260 skrll O16TOH(sitd->itd.itd_offset[3]));
1986 1.274 pgoyette DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx "
1987 1.274 pgoyette "offs[6] = 0x%04jx offs[7] = 0x%04jx",
1988 1.260 skrll O16TOH(sitd->itd.itd_offset[4]),
1989 1.260 skrll O16TOH(sitd->itd.itd_offset[5]),
1990 1.260 skrll O16TOH(sitd->itd.itd_offset[6]),
1991 1.260 skrll O16TOH(sitd->itd.itd_offset[7]));
1992 1.83 augustss }
1993 1.83 augustss
1994 1.83 augustss void
1995 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1996 1.83 augustss {
1997 1.83 augustss for (; sitd; sitd = sitd->nextitd)
1998 1.168 augustss ohci_dump_itd(sc, sitd);
1999 1.83 augustss }
2000 1.83 augustss
2001 1.83 augustss void
2002 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
2003 1.1 augustss {
2004 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2005 1.92 tv
2006 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2007 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2008 1.260 skrll
2009 1.260 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
2010 1.274 pgoyette DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0);
2011 1.274 pgoyette DPRINTF(" addr=%jd endpt=%jd maxp=%jd",
2012 1.260 skrll OHCI_ED_GET_FA(flags),
2013 1.260 skrll OHCI_ED_GET_EN(flags),
2014 1.260 skrll OHCI_ED_GET_MAXP(flags),
2015 1.260 skrll 0);
2016 1.274 pgoyette DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd",
2017 1.260 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
2018 1.260 skrll !!(flags & OHCI_ED_SPEED),
2019 1.260 skrll !!(flags & OHCI_ED_SKIP),
2020 1.260 skrll !!(flags & OHCI_ED_FORMAT_ISO));
2021 1.274 pgoyette DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp),
2022 1.260 skrll 0, 0, 0);
2023 1.274 pgoyette DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd",
2024 1.260 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
2025 1.260 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
2026 1.260 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2027 1.1 augustss }
2028 1.1 augustss #endif
2029 1.1 augustss
2030 1.1 augustss usbd_status
2031 1.260 skrll ohci_open(struct usbd_pipe *pipe)
2032 1.1 augustss {
2033 1.260 skrll struct usbd_device *dev = pipe->up_dev;
2034 1.260 skrll struct usbd_bus *bus = dev->ud_bus;
2035 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2036 1.260 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2037 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2038 1.260 skrll uint8_t addr = dev->ud_addr;
2039 1.260 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2040 1.1 augustss ohci_soft_ed_t *sed;
2041 1.1 augustss ohci_soft_td_t *std;
2042 1.60 augustss ohci_soft_itd_t *sitd;
2043 1.60 augustss ohci_physaddr_t tdphys;
2044 1.260 skrll uint32_t fmt;
2045 1.224 mrg usbd_status err = USBD_NOMEM;
2046 1.64 augustss int ival;
2047 1.1 augustss
2048 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2049 1.274 pgoyette DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe,
2050 1.274 pgoyette addr, ed->bEndpointAddress, bus->ub_rhaddr);
2051 1.81 augustss
2052 1.224 mrg if (sc->sc_dying) {
2053 1.241 skrll return USBD_IOERROR;
2054 1.224 mrg }
2055 1.116 augustss
2056 1.90 thorpej std = NULL;
2057 1.90 thorpej sed = NULL;
2058 1.90 thorpej
2059 1.260 skrll if (addr == bus->ub_rhaddr) {
2060 1.1 augustss switch (ed->bEndpointAddress) {
2061 1.1 augustss case USB_CONTROL_ENDPOINT:
2062 1.260 skrll pipe->up_methods = &roothub_ctrl_methods;
2063 1.1 augustss break;
2064 1.260 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2065 1.260 skrll pipe->up_methods = &ohci_root_intr_methods;
2066 1.1 augustss break;
2067 1.1 augustss default:
2068 1.224 mrg err = USBD_INVAL;
2069 1.241 skrll goto bad;
2070 1.1 augustss }
2071 1.1 augustss } else {
2072 1.1 augustss sed = ohci_alloc_sed(sc);
2073 1.53 augustss if (sed == NULL)
2074 1.241 skrll goto bad;
2075 1.1 augustss opipe->sed = sed;
2076 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2077 1.60 augustss sitd = ohci_alloc_sitd(sc);
2078 1.127 augustss if (sitd == NULL)
2079 1.241 skrll goto bad;
2080 1.241 skrll
2081 1.60 augustss opipe->tail.itd = sitd;
2082 1.76 tsutsui tdphys = sitd->physaddr;
2083 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2084 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2085 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2086 1.83 augustss else
2087 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2088 1.60 augustss } else {
2089 1.60 augustss std = ohci_alloc_std(sc);
2090 1.127 augustss if (std == NULL)
2091 1.241 skrll goto bad;
2092 1.241 skrll
2093 1.60 augustss opipe->tail.td = std;
2094 1.76 tsutsui tdphys = std->physaddr;
2095 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2096 1.60 augustss }
2097 1.168 augustss sed->ed.ed_flags = HTOO32(
2098 1.120 augustss OHCI_ED_SET_FA(addr) |
2099 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2100 1.260 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2101 1.109 augustss fmt |
2102 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2103 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2104 1.260 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2105 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2106 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2107 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2108 1.1 augustss
2109 1.60 augustss switch (xfertype) {
2110 1.1 augustss case UE_CONTROL:
2111 1.260 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2112 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2113 1.120 augustss sizeof(usb_device_request_t),
2114 1.260 skrll 0, &opipe->ctrl.reqdma);
2115 1.53 augustss if (err)
2116 1.1 augustss goto bad;
2117 1.224 mrg mutex_enter(&sc->sc_lock);
2118 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2119 1.224 mrg mutex_exit(&sc->sc_lock);
2120 1.1 augustss break;
2121 1.1 augustss case UE_INTERRUPT:
2122 1.260 skrll pipe->up_methods = &ohci_device_intr_methods;
2123 1.260 skrll ival = pipe->up_interval;
2124 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2125 1.64 augustss ival = ed->bInterval;
2126 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2127 1.226 skrll if (err)
2128 1.226 skrll goto bad;
2129 1.226 skrll break;
2130 1.1 augustss case UE_ISOCHRONOUS:
2131 1.260 skrll pipe->up_serialise = false;
2132 1.260 skrll pipe->up_methods = &ohci_device_isoc_methods;
2133 1.260 skrll return ohci_setup_isoc(pipe);
2134 1.1 augustss case UE_BULK:
2135 1.260 skrll pipe->up_methods = &ohci_device_bulk_methods;
2136 1.224 mrg mutex_enter(&sc->sc_lock);
2137 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2138 1.224 mrg mutex_exit(&sc->sc_lock);
2139 1.3 augustss break;
2140 1.1 augustss }
2141 1.1 augustss }
2142 1.224 mrg
2143 1.224 mrg return USBD_NORMAL_COMPLETION;
2144 1.1 augustss
2145 1.1 augustss bad:
2146 1.241 skrll if (std != NULL) {
2147 1.90 thorpej ohci_free_std(sc, std);
2148 1.241 skrll }
2149 1.90 thorpej if (sed != NULL)
2150 1.90 thorpej ohci_free_sed(sc, sed);
2151 1.224 mrg return err;
2152 1.120 augustss
2153 1.1 augustss }
2154 1.1 augustss
2155 1.1 augustss /*
2156 1.34 augustss * Close a reqular pipe.
2157 1.34 augustss * Assumes that there are no pending transactions.
2158 1.34 augustss */
2159 1.34 augustss void
2160 1.260 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2161 1.34 augustss {
2162 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2163 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2164 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2165 1.34 augustss
2166 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2167 1.224 mrg
2168 1.34 augustss #ifdef DIAGNOSTIC
2169 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2170 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2171 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2172 1.34 augustss ohci_soft_td_t *std;
2173 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2174 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2175 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2176 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2177 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2178 1.34 augustss pipe, std);
2179 1.229 christos #ifdef OHCI_DEBUG
2180 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2181 1.168 augustss ohci_dump_ed(sc, sed);
2182 1.106 augustss if (std)
2183 1.168 augustss ohci_dump_td(sc, std);
2184 1.106 augustss #endif
2185 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2186 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2187 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2188 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2189 1.34 augustss }
2190 1.34 augustss #endif
2191 1.224 mrg ohci_rem_ed(sc, sed, head);
2192 1.133 toshii /* Make sure the host controller is not touching this ED */
2193 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2194 1.260 skrll pipe->up_endpoint->ue_toggle =
2195 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2196 1.260 skrll ohci_free_sed_locked(sc, opipe->sed);
2197 1.34 augustss }
2198 1.34 augustss
2199 1.120 augustss /*
2200 1.34 augustss * Abort a device request.
2201 1.34 augustss * If this routine is called at splusb() it guarantees that the request
2202 1.34 augustss * will be removed from the hardware scheduling and that the callback
2203 1.34 augustss * for it will be called with USBD_CANCELLED status.
2204 1.34 augustss * It's impossible to guarantee that the requested transfer will not
2205 1.34 augustss * have happened since the hardware runs concurrently.
2206 1.34 augustss * If the transaction has already happened we rely on the ordinary
2207 1.34 augustss * interrupt processing to process it.
2208 1.224 mrg * XXX This is most probably wrong.
2209 1.224 mrg * XXXMRG this doesn't make sense anymore.
2210 1.34 augustss */
2211 1.34 augustss void
2212 1.260 skrll ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status)
2213 1.34 augustss {
2214 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2215 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2216 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2217 1.106 augustss ohci_soft_td_t *p, *n;
2218 1.106 augustss ohci_physaddr_t headp;
2219 1.224 mrg int hit;
2220 1.159 augustss int wake;
2221 1.34 augustss
2222 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2223 1.274 pgoyette DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer,
2224 1.274 pgoyette (uintptr_t)opipe, (uintptr_t)sed, 0);
2225 1.34 augustss
2226 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2227 1.260 skrll ASSERT_SLEEPABLE();
2228 1.224 mrg
2229 1.116 augustss if (sc->sc_dying) {
2230 1.116 augustss /* If we're dying, just do the software part. */
2231 1.260 skrll xfer->ux_status = status; /* make software ignore it */
2232 1.260 skrll callout_halt(&xfer->ux_callout, &sc->sc_lock);
2233 1.116 augustss usb_transfer_complete(xfer);
2234 1.170 christos return;
2235 1.116 augustss }
2236 1.116 augustss
2237 1.106 augustss /*
2238 1.159 augustss * If an abort is already in progress then just wait for it to
2239 1.159 augustss * complete and return.
2240 1.159 augustss */
2241 1.260 skrll if (xfer->ux_hcflags & UXFER_ABORTING) {
2242 1.260 skrll DPRINTFN(2, "already aborting", 0, 0, 0, 0);
2243 1.159 augustss #ifdef DIAGNOSTIC
2244 1.159 augustss if (status == USBD_TIMEOUT)
2245 1.235 skrll printf("%s: TIMEOUT while aborting\n", __func__);
2246 1.159 augustss #endif
2247 1.159 augustss /* Override the status which might be USBD_TIMEOUT. */
2248 1.260 skrll xfer->ux_status = status;
2249 1.260 skrll DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0);
2250 1.260 skrll xfer->ux_hcflags |= UXFER_ABORTWAIT;
2251 1.260 skrll while (xfer->ux_hcflags & UXFER_ABORTING)
2252 1.260 skrll cv_wait(&xfer->ux_hccv, &sc->sc_lock);
2253 1.224 mrg goto done;
2254 1.159 augustss }
2255 1.260 skrll xfer->ux_hcflags |= UXFER_ABORTING;
2256 1.159 augustss
2257 1.159 augustss /*
2258 1.106 augustss * Step 1: Make interrupt routine and hardware ignore xfer.
2259 1.106 augustss */
2260 1.260 skrll xfer->ux_status = status; /* make software ignore it */
2261 1.260 skrll callout_stop(&xfer->ux_callout);
2262 1.274 pgoyette DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0);
2263 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2264 1.195 bouyer sizeof(sed->ed.ed_flags),
2265 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2266 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2267 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2268 1.195 bouyer sizeof(sed->ed.ed_flags),
2269 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2270 1.34 augustss
2271 1.120 augustss /*
2272 1.106 augustss * Step 2: Wait until we know hardware has finished any possible
2273 1.106 augustss * use of the xfer. Also make sure the soft interrupt routine
2274 1.106 augustss * has run.
2275 1.106 augustss */
2276 1.224 mrg /* Hardware finishes in 1ms */
2277 1.260 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2278 1.119 augustss sc->sc_softwake = 1;
2279 1.119 augustss usb_schedsoftintr(&sc->sc_bus);
2280 1.224 mrg cv_wait(&sc->sc_softwake_cv, &sc->sc_lock);
2281 1.119 augustss
2282 1.120 augustss /*
2283 1.106 augustss * Step 3: Remove any vestiges of the xfer from the hardware.
2284 1.106 augustss * The complication here is that the hardware may have executed
2285 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2286 1.106 augustss * the TDs of this xfer we check if the hardware points to
2287 1.106 augustss * any of them.
2288 1.106 augustss */
2289 1.260 skrll p = xfer->ux_hcpriv;
2290 1.260 skrll KASSERT(p);
2291 1.260 skrll
2292 1.106 augustss #ifdef OHCI_DEBUG
2293 1.260 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2294 1.260 skrll
2295 1.260 skrll if (ohcidebug >= 2) {
2296 1.260 skrll DPRINTF("sed:", 0, 0, 0, 0);
2297 1.168 augustss ohci_dump_ed(sc, sed);
2298 1.168 augustss ohci_dump_tds(sc, p);
2299 1.106 augustss }
2300 1.260 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2301 1.106 augustss #endif
2302 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2303 1.106 augustss hit = 0;
2304 1.53 augustss for (; p->xfer == xfer; p = n) {
2305 1.106 augustss hit |= headp == p->physaddr;
2306 1.38 augustss n = p->nexttd;
2307 1.260 skrll ohci_hash_rem_td(sc, p);
2308 1.34 augustss }
2309 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2310 1.106 augustss if (hit) {
2311 1.274 pgoyette DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr,
2312 1.260 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2313 1.168 augustss sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */
2314 1.195 bouyer usb_syncmem(&sed->dma,
2315 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2316 1.195 bouyer sizeof(sed->ed.ed_headp),
2317 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2318 1.106 augustss } else {
2319 1.260 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2320 1.106 augustss }
2321 1.34 augustss
2322 1.106 augustss /*
2323 1.106 augustss * Step 4: Turn on hardware again.
2324 1.106 augustss */
2325 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2326 1.195 bouyer sizeof(sed->ed.ed_flags),
2327 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2328 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2329 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2330 1.195 bouyer sizeof(sed->ed.ed_flags),
2331 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2332 1.38 augustss
2333 1.106 augustss /*
2334 1.106 augustss * Step 5: Execute callback.
2335 1.106 augustss */
2336 1.260 skrll wake = xfer->ux_hcflags & UXFER_ABORTWAIT;
2337 1.260 skrll xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT);
2338 1.53 augustss usb_transfer_complete(xfer);
2339 1.159 augustss if (wake)
2340 1.260 skrll cv_broadcast(&xfer->ux_hccv);
2341 1.38 augustss
2342 1.224 mrg done:
2343 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2344 1.34 augustss }
2345 1.34 augustss
2346 1.34 augustss /*
2347 1.1 augustss * Data structures and routines to emulate the root hub.
2348 1.1 augustss */
2349 1.260 skrll Static int
2350 1.260 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2351 1.260 skrll void *buf, int buflen)
2352 1.1 augustss {
2353 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2354 1.260 skrll usb_port_status_t ps;
2355 1.260 skrll uint16_t len, value, index;
2356 1.260 skrll int l, totlen = 0;
2357 1.260 skrll int port, i;
2358 1.260 skrll uint32_t v;
2359 1.17 augustss
2360 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2361 1.1 augustss
2362 1.83 augustss if (sc->sc_dying)
2363 1.260 skrll return -1;
2364 1.1 augustss
2365 1.274 pgoyette DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType,
2366 1.260 skrll req->bRequest, 0, 0);
2367 1.1 augustss
2368 1.1 augustss len = UGETW(req->wLength);
2369 1.1 augustss value = UGETW(req->wValue);
2370 1.1 augustss index = UGETW(req->wIndex);
2371 1.43 augustss
2372 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2373 1.260 skrll switch (C(req->bRequest, req->bmRequestType)) {
2374 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2375 1.274 pgoyette DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0);
2376 1.171 christos if (len == 0)
2377 1.171 christos break;
2378 1.260 skrll switch (value) {
2379 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2380 1.260 skrll case C(2, UDESC_STRING):
2381 1.260 skrll /* Product */
2382 1.260 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2383 1.260 skrll break;
2384 1.186 drochner #undef sd
2385 1.1 augustss default:
2386 1.260 skrll /* default from usbroothub */
2387 1.260 skrll return buflen;
2388 1.1 augustss }
2389 1.1 augustss break;
2390 1.260 skrll
2391 1.1 augustss /* Hub requests */
2392 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2393 1.1 augustss break;
2394 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2395 1.274 pgoyette DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd",
2396 1.260 skrll index, value, 0, 0);
2397 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2398 1.260 skrll return -1;
2399 1.1 augustss }
2400 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2401 1.1 augustss switch(value) {
2402 1.1 augustss case UHF_PORT_ENABLE:
2403 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2404 1.1 augustss break;
2405 1.1 augustss case UHF_PORT_SUSPEND:
2406 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2407 1.1 augustss break;
2408 1.1 augustss case UHF_PORT_POWER:
2409 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2410 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2411 1.1 augustss break;
2412 1.1 augustss case UHF_C_PORT_CONNECTION:
2413 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2414 1.1 augustss break;
2415 1.1 augustss case UHF_C_PORT_ENABLE:
2416 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2417 1.1 augustss break;
2418 1.1 augustss case UHF_C_PORT_SUSPEND:
2419 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2420 1.1 augustss break;
2421 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2422 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2423 1.1 augustss break;
2424 1.1 augustss case UHF_C_PORT_RESET:
2425 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2426 1.1 augustss break;
2427 1.1 augustss default:
2428 1.260 skrll return -1;
2429 1.1 augustss }
2430 1.1 augustss switch(value) {
2431 1.1 augustss case UHF_C_PORT_CONNECTION:
2432 1.1 augustss case UHF_C_PORT_ENABLE:
2433 1.1 augustss case UHF_C_PORT_SUSPEND:
2434 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2435 1.1 augustss case UHF_C_PORT_RESET:
2436 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2437 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2438 1.157 mycroft ohci_rhsc_enable(sc);
2439 1.1 augustss break;
2440 1.1 augustss default:
2441 1.1 augustss break;
2442 1.1 augustss }
2443 1.1 augustss break;
2444 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2445 1.171 christos if (len == 0)
2446 1.171 christos break;
2447 1.146 toshii if ((value & 0xff) != 0) {
2448 1.260 skrll return -1;
2449 1.1 augustss }
2450 1.260 skrll usb_hub_descriptor_t hubd;
2451 1.260 skrll
2452 1.260 skrll totlen = min(buflen, sizeof(hubd));
2453 1.260 skrll memcpy(&hubd, buf, totlen);
2454 1.260 skrll
2455 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2456 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2457 1.15 augustss USETW(hubd.wHubCharacteristics,
2458 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2459 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2460 1.1 augustss /* XXX overcurrent */
2461 1.1 augustss );
2462 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2463 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2464 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2465 1.260 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2466 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2467 1.260 skrll totlen = min(totlen, hubd.bDescLength);
2468 1.260 skrll memcpy(buf, &hubd, totlen);
2469 1.1 augustss break;
2470 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2471 1.1 augustss if (len != 4) {
2472 1.260 skrll return -1;
2473 1.1 augustss }
2474 1.1 augustss memset(buf, 0, len); /* ? XXX */
2475 1.1 augustss totlen = len;
2476 1.1 augustss break;
2477 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2478 1.274 pgoyette DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0);
2479 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2480 1.260 skrll return -1;
2481 1.1 augustss }
2482 1.1 augustss if (len != 4) {
2483 1.260 skrll return -1;
2484 1.1 augustss }
2485 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2486 1.274 pgoyette DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0);
2487 1.1 augustss USETW(ps.wPortStatus, v);
2488 1.1 augustss USETW(ps.wPortChange, v >> 16);
2489 1.260 skrll totlen = min(len, sizeof(ps));
2490 1.260 skrll memcpy(buf, &ps, totlen);
2491 1.1 augustss break;
2492 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2493 1.260 skrll return -1;
2494 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2495 1.1 augustss break;
2496 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2497 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2498 1.260 skrll return -1;
2499 1.1 augustss }
2500 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2501 1.1 augustss switch(value) {
2502 1.1 augustss case UHF_PORT_ENABLE:
2503 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2504 1.1 augustss break;
2505 1.1 augustss case UHF_PORT_SUSPEND:
2506 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2507 1.1 augustss break;
2508 1.1 augustss case UHF_PORT_RESET:
2509 1.274 pgoyette DPRINTFN(5, "reset port %jd", index, 0, 0, 0);
2510 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2511 1.110 augustss for (i = 0; i < 5; i++) {
2512 1.110 augustss usb_delay_ms(&sc->sc_bus,
2513 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2514 1.116 augustss if (sc->sc_dying) {
2515 1.260 skrll return -1;
2516 1.116 augustss }
2517 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2518 1.1 augustss break;
2519 1.1 augustss }
2520 1.274 pgoyette DPRINTFN(8, "port %jd reset, status = 0x%04jx", index,
2521 1.260 skrll OREAD4(sc, port), 0, 0);
2522 1.1 augustss break;
2523 1.1 augustss case UHF_PORT_POWER:
2524 1.274 pgoyette DPRINTFN(2, "set port power %jd", index, 0, 0, 0);
2525 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2526 1.1 augustss break;
2527 1.1 augustss default:
2528 1.260 skrll return -1;
2529 1.1 augustss }
2530 1.1 augustss break;
2531 1.1 augustss default:
2532 1.260 skrll /* default from usbroothub */
2533 1.260 skrll return buflen;
2534 1.1 augustss }
2535 1.1 augustss
2536 1.260 skrll return totlen;
2537 1.1 augustss }
2538 1.1 augustss
2539 1.82 augustss Static usbd_status
2540 1.260 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2541 1.1 augustss {
2542 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2543 1.53 augustss usbd_status err;
2544 1.17 augustss
2545 1.46 augustss /* Insert last in queue. */
2546 1.224 mrg mutex_enter(&sc->sc_lock);
2547 1.53 augustss err = usb_insert_transfer(xfer);
2548 1.224 mrg mutex_exit(&sc->sc_lock);
2549 1.53 augustss if (err)
2550 1.260 skrll return err;
2551 1.46 augustss
2552 1.46 augustss /* Pipe isn't running, start first */
2553 1.260 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2554 1.17 augustss }
2555 1.17 augustss
2556 1.82 augustss Static usbd_status
2557 1.260 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2558 1.17 augustss {
2559 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2560 1.1 augustss
2561 1.83 augustss if (sc->sc_dying)
2562 1.260 skrll return USBD_IOERROR;
2563 1.83 augustss
2564 1.224 mrg mutex_enter(&sc->sc_lock);
2565 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2566 1.53 augustss sc->sc_intrxfer = xfer;
2567 1.224 mrg mutex_exit(&sc->sc_lock);
2568 1.1 augustss
2569 1.260 skrll return USBD_IN_PROGRESS;
2570 1.1 augustss }
2571 1.1 augustss
2572 1.3 augustss /* Abort a root interrupt request. */
2573 1.82 augustss Static void
2574 1.260 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2575 1.1 augustss {
2576 1.279 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2577 1.224 mrg
2578 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2579 1.260 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2580 1.53 augustss
2581 1.260 skrll xfer->ux_status = USBD_CANCELLED;
2582 1.53 augustss usb_transfer_complete(xfer);
2583 1.1 augustss }
2584 1.1 augustss
2585 1.1 augustss /* Close the root pipe. */
2586 1.82 augustss Static void
2587 1.260 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2588 1.1 augustss {
2589 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2590 1.120 augustss
2591 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2592 1.224 mrg
2593 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2594 1.34 augustss
2595 1.53 augustss sc->sc_intrxfer = NULL;
2596 1.1 augustss }
2597 1.1 augustss
2598 1.1 augustss /************************/
2599 1.1 augustss
2600 1.260 skrll int
2601 1.260 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2602 1.260 skrll {
2603 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2604 1.260 skrll usb_device_request_t *req = &xfer->ux_request;
2605 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2606 1.260 skrll ohci_soft_td_t *stat, *setup;
2607 1.260 skrll int isread = req->bmRequestType & UT_READ;
2608 1.260 skrll int len = xfer->ux_bufsize;
2609 1.260 skrll int err = ENOMEM;
2610 1.260 skrll
2611 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2612 1.260 skrll
2613 1.260 skrll setup = ohci_alloc_std(sc);
2614 1.260 skrll if (setup == NULL) {
2615 1.260 skrll goto bad1;
2616 1.260 skrll }
2617 1.260 skrll stat = ohci_alloc_std(sc);
2618 1.260 skrll if (stat == NULL) {
2619 1.260 skrll goto bad2;
2620 1.260 skrll }
2621 1.260 skrll
2622 1.260 skrll ox->ox_setup = setup;
2623 1.260 skrll ox->ox_stat = stat;
2624 1.260 skrll ox->ox_nstd = 0;
2625 1.260 skrll
2626 1.260 skrll /* Set up data transaction */
2627 1.260 skrll if (len != 0) {
2628 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2629 1.260 skrll if (err) {
2630 1.260 skrll goto bad3;
2631 1.260 skrll }
2632 1.260 skrll }
2633 1.260 skrll return 0;
2634 1.260 skrll
2635 1.260 skrll bad3:
2636 1.260 skrll ohci_free_std(sc, stat);
2637 1.260 skrll bad2:
2638 1.260 skrll ohci_free_std(sc, setup);
2639 1.260 skrll bad1:
2640 1.260 skrll return err;
2641 1.260 skrll }
2642 1.260 skrll
2643 1.260 skrll void
2644 1.260 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2645 1.260 skrll {
2646 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2647 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2648 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2649 1.260 skrll
2650 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2651 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
2652 1.260 skrll
2653 1.260 skrll mutex_enter(&sc->sc_lock);
2654 1.260 skrll if (ox->ox_setup != opipe->tail.td) {
2655 1.260 skrll ohci_free_std_locked(sc, ox->ox_setup);
2656 1.260 skrll }
2657 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2658 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2659 1.260 skrll if (std == NULL)
2660 1.260 skrll break;
2661 1.260 skrll ohci_free_std_locked(sc, std);
2662 1.260 skrll }
2663 1.260 skrll ohci_free_std_locked(sc, ox->ox_stat);
2664 1.260 skrll mutex_exit(&sc->sc_lock);
2665 1.260 skrll
2666 1.260 skrll if (ox->ox_nstd) {
2667 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2668 1.260 skrll kmem_free(ox->ox_stds, sz);
2669 1.260 skrll }
2670 1.260 skrll }
2671 1.260 skrll
2672 1.82 augustss Static usbd_status
2673 1.260 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2674 1.1 augustss {
2675 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2676 1.53 augustss usbd_status err;
2677 1.17 augustss
2678 1.46 augustss /* Insert last in queue. */
2679 1.224 mrg mutex_enter(&sc->sc_lock);
2680 1.53 augustss err = usb_insert_transfer(xfer);
2681 1.224 mrg mutex_exit(&sc->sc_lock);
2682 1.53 augustss if (err)
2683 1.260 skrll return err;
2684 1.46 augustss
2685 1.46 augustss /* Pipe isn't running, start first */
2686 1.260 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2687 1.17 augustss }
2688 1.17 augustss
2689 1.82 augustss Static usbd_status
2690 1.260 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2691 1.17 augustss {
2692 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2693 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2694 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2695 1.260 skrll usb_device_request_t *req = &xfer->ux_request;
2696 1.260 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2697 1.260 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2698 1.260 skrll ohci_soft_ed_t *sed;
2699 1.260 skrll int isread;
2700 1.260 skrll int len;
2701 1.260 skrll
2702 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2703 1.1 augustss
2704 1.83 augustss if (sc->sc_dying)
2705 1.260 skrll return USBD_IOERROR;
2706 1.260 skrll
2707 1.260 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2708 1.260 skrll
2709 1.260 skrll isread = req->bmRequestType & UT_READ;
2710 1.260 skrll len = UGETW(req->wLength);
2711 1.260 skrll
2712 1.274 pgoyette DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len,
2713 1.274 pgoyette dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2714 1.274 pgoyette DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx",
2715 1.260 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2716 1.260 skrll UGETW(req->wIndex));
2717 1.260 skrll
2718 1.260 skrll /* Need to take lock here for pipe->tail.td */
2719 1.260 skrll mutex_enter(&sc->sc_lock);
2720 1.260 skrll
2721 1.260 skrll /*
2722 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2723 1.260 skrll * next transfer
2724 1.260 skrll */
2725 1.260 skrll setup = opipe->tail.td;
2726 1.260 skrll opipe->tail.td = ox->ox_setup;
2727 1.260 skrll ox->ox_setup = setup;
2728 1.260 skrll
2729 1.260 skrll stat = ox->ox_stat;
2730 1.260 skrll
2731 1.260 skrll /* point at sentinel */
2732 1.260 skrll tail = opipe->tail.td;
2733 1.260 skrll sed = opipe->sed;
2734 1.260 skrll
2735 1.260 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2736 1.260 skrll "address ED %d pipe %d\n",
2737 1.260 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2738 1.260 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2739 1.260 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2740 1.260 skrll "MPL ED %d pipe %d\n",
2741 1.260 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2742 1.260 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2743 1.260 skrll
2744 1.260 skrll /* next will point to data if len != 0 */
2745 1.260 skrll next = stat;
2746 1.260 skrll
2747 1.260 skrll /* Set up data transaction */
2748 1.260 skrll if (len != 0) {
2749 1.260 skrll ohci_soft_td_t *std;
2750 1.260 skrll ohci_soft_td_t *end;
2751 1.260 skrll
2752 1.260 skrll next = ox->ox_stds[0];
2753 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2754 1.260 skrll
2755 1.260 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2756 1.260 skrll end->nexttd = stat;
2757 1.260 skrll
2758 1.273 skrll usb_syncmem(&end->dma, end->offs, sizeof(end->td),
2759 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2760 1.260 skrll
2761 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2762 1.260 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2763 1.260 skrll std = ox->ox_stds[0];
2764 1.260 skrll /* Start toggle at 1 and then use the carried toggle. */
2765 1.260 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2766 1.260 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2767 1.260 skrll usb_syncmem(&std->dma,
2768 1.260 skrll std->offs + offsetof(ohci_td_t, td_flags),
2769 1.260 skrll sizeof(std->td.td_flags),
2770 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2771 1.260 skrll }
2772 1.260 skrll
2773 1.274 pgoyette DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx",
2774 1.274 pgoyette (uintptr_t)setup,
2775 1.274 pgoyette (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat,
2776 1.274 pgoyette (uintptr_t)tail);
2777 1.260 skrll KASSERT(opipe->tail.td == tail);
2778 1.260 skrll
2779 1.260 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2780 1.260 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2781 1.83 augustss
2782 1.260 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2783 1.260 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2784 1.260 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2785 1.260 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2786 1.260 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2787 1.260 skrll setup->nexttd = next;
2788 1.260 skrll setup->len = 0;
2789 1.260 skrll setup->xfer = xfer;
2790 1.260 skrll setup->flags = 0;
2791 1.260 skrll ohci_hash_add_td(sc, setup);
2792 1.260 skrll
2793 1.260 skrll xfer->ux_hcpriv = setup;
2794 1.260 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2795 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2796 1.260 skrll
2797 1.260 skrll stat->td.td_flags = HTOO32(
2798 1.260 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2799 1.260 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2800 1.260 skrll stat->td.td_cbp = 0;
2801 1.260 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2802 1.260 skrll stat->td.td_be = 0;
2803 1.260 skrll stat->nexttd = tail;
2804 1.260 skrll stat->flags = OHCI_CALL_DONE;
2805 1.260 skrll stat->len = 0;
2806 1.260 skrll stat->xfer = xfer;
2807 1.260 skrll ohci_hash_add_td(sc, stat);
2808 1.260 skrll
2809 1.260 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2810 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2811 1.260 skrll
2812 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
2813 1.260 skrll tail->nexttd = NULL;
2814 1.260 skrll tail->xfer = NULL;
2815 1.260 skrll
2816 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2817 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2818 1.260 skrll
2819 1.260 skrll #ifdef OHCI_DEBUG
2820 1.260 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2821 1.260 skrll if (ohcidebug >= 5) {
2822 1.260 skrll ohci_dump_ed(sc, sed);
2823 1.260 skrll ohci_dump_tds(sc, setup);
2824 1.1 augustss }
2825 1.260 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2826 1.42 augustss #endif
2827 1.1 augustss
2828 1.260 skrll /* Insert ED in schedule */
2829 1.260 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2830 1.260 skrll usb_syncmem(&sed->dma,
2831 1.260 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2832 1.260 skrll sizeof(sed->ed.ed_tailp),
2833 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2834 1.260 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2835 1.260 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
2836 1.260 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
2837 1.260 skrll ohci_timeout, xfer);
2838 1.260 skrll }
2839 1.260 skrll
2840 1.260 skrll DPRINTF("done", 0, 0, 0, 0);
2841 1.260 skrll
2842 1.224 mrg mutex_exit(&sc->sc_lock);
2843 1.1 augustss
2844 1.260 skrll return USBD_IN_PROGRESS;
2845 1.1 augustss }
2846 1.1 augustss
2847 1.1 augustss /* Abort a device control request. */
2848 1.82 augustss Static void
2849 1.260 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2850 1.1 augustss {
2851 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2852 1.224 mrg
2853 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2854 1.224 mrg
2855 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2856 1.274 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
2857 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
2858 1.1 augustss }
2859 1.1 augustss
2860 1.1 augustss /* Close a device control pipe. */
2861 1.82 augustss Static void
2862 1.260 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2863 1.1 augustss {
2864 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2865 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2866 1.1 augustss
2867 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2868 1.224 mrg
2869 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2870 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
2871 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2872 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
2873 1.3 augustss }
2874 1.3 augustss
2875 1.3 augustss /************************/
2876 1.37 augustss
2877 1.82 augustss Static void
2878 1.260 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2879 1.37 augustss {
2880 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2881 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2882 1.37 augustss
2883 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2884 1.37 augustss }
2885 1.37 augustss
2886 1.82 augustss Static void
2887 1.260 skrll ohci_noop(struct usbd_pipe *pipe)
2888 1.37 augustss {
2889 1.37 augustss }
2890 1.3 augustss
2891 1.260 skrll Static int
2892 1.260 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
2893 1.260 skrll {
2894 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2895 1.260 skrll int len = xfer->ux_bufsize;
2896 1.281 maya int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2897 1.260 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2898 1.260 skrll int err;
2899 1.260 skrll
2900 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2901 1.260 skrll
2902 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2903 1.260 skrll
2904 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
2905 1.274 pgoyette len, isread, xfer->ux_flags);
2906 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
2907 1.260 skrll
2908 1.260 skrll /* Allocate a chain of new TDs (including a new tail). */
2909 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2910 1.260 skrll if (err)
2911 1.260 skrll return err;
2912 1.260 skrll
2913 1.260 skrll return 0;
2914 1.260 skrll }
2915 1.260 skrll
2916 1.260 skrll Static void
2917 1.260 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
2918 1.260 skrll {
2919 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2920 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2921 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2922 1.260 skrll
2923 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2924 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
2925 1.260 skrll
2926 1.260 skrll mutex_enter(&sc->sc_lock);
2927 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2928 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2929 1.260 skrll if (std == NULL)
2930 1.260 skrll break;
2931 1.260 skrll if (std != opipe->tail.td)
2932 1.260 skrll ohci_free_std_locked(sc, std);
2933 1.260 skrll }
2934 1.260 skrll mutex_exit(&sc->sc_lock);
2935 1.260 skrll
2936 1.260 skrll if (ox->ox_nstd) {
2937 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2938 1.260 skrll kmem_free(ox->ox_stds, sz);
2939 1.260 skrll }
2940 1.260 skrll }
2941 1.260 skrll
2942 1.82 augustss Static usbd_status
2943 1.260 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
2944 1.3 augustss {
2945 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2946 1.53 augustss usbd_status err;
2947 1.17 augustss
2948 1.46 augustss /* Insert last in queue. */
2949 1.224 mrg mutex_enter(&sc->sc_lock);
2950 1.53 augustss err = usb_insert_transfer(xfer);
2951 1.224 mrg mutex_exit(&sc->sc_lock);
2952 1.53 augustss if (err)
2953 1.260 skrll return err;
2954 1.46 augustss
2955 1.46 augustss /* Pipe isn't running, start first */
2956 1.260 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2957 1.17 augustss }
2958 1.17 augustss
2959 1.82 augustss Static usbd_status
2960 1.260 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
2961 1.17 augustss {
2962 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2963 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2964 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2965 1.260 skrll ohci_soft_td_t *last;
2966 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
2967 1.3 augustss ohci_soft_ed_t *sed;
2968 1.224 mrg int len, isread, endpt;
2969 1.260 skrll
2970 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2971 1.3 augustss
2972 1.83 augustss if (sc->sc_dying)
2973 1.260 skrll return USBD_IOERROR;
2974 1.83 augustss
2975 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2976 1.224 mrg
2977 1.260 skrll len = xfer->ux_length;
2978 1.260 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2979 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2980 1.3 augustss sed = opipe->sed;
2981 1.3 augustss
2982 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
2983 1.274 pgoyette len, isread, xfer->ux_flags);
2984 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
2985 1.34 augustss
2986 1.260 skrll mutex_enter(&sc->sc_lock);
2987 1.3 augustss
2988 1.260 skrll /*
2989 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2990 1.260 skrll * next transfer
2991 1.260 skrll */
2992 1.260 skrll data = opipe->tail.td;
2993 1.260 skrll opipe->tail.td = ox->ox_stds[0];
2994 1.260 skrll ox->ox_stds[0] = data;
2995 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
2996 1.260 skrll
2997 1.260 skrll /* point at sentinel */
2998 1.260 skrll tail = opipe->tail.td;
2999 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
3000 1.260 skrll tail->nexttd = NULL;
3001 1.260 skrll tail->xfer = NULL;
3002 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3003 1.273 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3004 1.260 skrll xfer->ux_hcpriv = data;
3005 1.3 augustss
3006 1.274 pgoyette DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer,
3007 1.274 pgoyette (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0);
3008 1.260 skrll KASSERT(opipe->tail.td == tail);
3009 1.258 skrll
3010 1.77 augustss /* We want interrupt at the end of the transfer. */
3011 1.260 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3012 1.260 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3013 1.260 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3014 1.260 skrll last->nexttd = tail;
3015 1.260 skrll last->flags |= OHCI_CALL_DONE;
3016 1.260 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3017 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3018 1.3 augustss
3019 1.274 pgoyette DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx "
3020 1.274 pgoyette "td_cbp=0x%08jx td_be=0x%08jx",
3021 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
3022 1.168 augustss (int)O32TOH(data->td.td_flags),
3023 1.168 augustss (int)O32TOH(data->td.td_cbp),
3024 1.260 skrll (int)O32TOH(data->td.td_be));
3025 1.34 augustss
3026 1.52 augustss #ifdef OHCI_DEBUG
3027 1.260 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3028 1.260 skrll if (ohcidebug >= 5) {
3029 1.168 augustss ohci_dump_ed(sc, sed);
3030 1.168 augustss ohci_dump_tds(sc, data);
3031 1.34 augustss }
3032 1.260 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3033 1.34 augustss #endif
3034 1.34 augustss
3035 1.3 augustss /* Insert ED in schedule */
3036 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
3037 1.260 skrll KASSERT(tdp->xfer == xfer);
3038 1.48 augustss }
3039 1.260 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3040 1.260 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3041 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3042 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3043 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3044 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3045 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
3046 1.260 skrll if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) {
3047 1.260 skrll callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout),
3048 1.80 augustss ohci_timeout, xfer);
3049 1.15 augustss }
3050 1.224 mrg mutex_exit(&sc->sc_lock);
3051 1.34 augustss
3052 1.260 skrll return USBD_IN_PROGRESS;
3053 1.3 augustss }
3054 1.3 augustss
3055 1.82 augustss Static void
3056 1.260 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3057 1.3 augustss {
3058 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3059 1.260 skrll
3060 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3061 1.224 mrg
3062 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3063 1.224 mrg
3064 1.274 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3065 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3066 1.3 augustss }
3067 1.3 augustss
3068 1.120 augustss /*
3069 1.34 augustss * Close a device bulk pipe.
3070 1.34 augustss */
3071 1.82 augustss Static void
3072 1.260 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3073 1.3 augustss {
3074 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3075 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3076 1.3 augustss
3077 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3078 1.224 mrg
3079 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3080 1.260 skrll
3081 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3082 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3083 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
3084 1.1 augustss }
3085 1.1 augustss
3086 1.1 augustss /************************/
3087 1.1 augustss
3088 1.260 skrll Static int
3089 1.260 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3090 1.260 skrll {
3091 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3092 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3093 1.260 skrll int len = xfer->ux_bufsize;
3094 1.281 maya int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3095 1.260 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3096 1.260 skrll int err;
3097 1.260 skrll
3098 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3099 1.260 skrll
3100 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3101 1.260 skrll KASSERT(len != 0);
3102 1.260 skrll
3103 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
3104 1.274 pgoyette len, isread, xfer->ux_flags);
3105 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
3106 1.260 skrll
3107 1.260 skrll ox->ox_nstd = 0;
3108 1.260 skrll
3109 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3110 1.260 skrll if (err) {
3111 1.260 skrll return err;
3112 1.260 skrll }
3113 1.260 skrll
3114 1.260 skrll return 0;
3115 1.260 skrll }
3116 1.260 skrll
3117 1.260 skrll Static void
3118 1.260 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3119 1.260 skrll {
3120 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3121 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3122 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3123 1.260 skrll
3124 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3125 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
3126 1.260 skrll
3127 1.260 skrll mutex_enter(&sc->sc_lock);
3128 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3129 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3130 1.260 skrll if (std != NULL)
3131 1.260 skrll break;
3132 1.260 skrll if (std != opipe->tail.td)
3133 1.260 skrll ohci_free_std_locked(sc, std);
3134 1.260 skrll }
3135 1.260 skrll mutex_exit(&sc->sc_lock);
3136 1.260 skrll
3137 1.260 skrll if (ox->ox_nstd) {
3138 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3139 1.260 skrll kmem_free(ox->ox_stds, sz);
3140 1.260 skrll }
3141 1.260 skrll }
3142 1.260 skrll
3143 1.82 augustss Static usbd_status
3144 1.260 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3145 1.17 augustss {
3146 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3147 1.53 augustss usbd_status err;
3148 1.17 augustss
3149 1.46 augustss /* Insert last in queue. */
3150 1.224 mrg mutex_enter(&sc->sc_lock);
3151 1.53 augustss err = usb_insert_transfer(xfer);
3152 1.224 mrg mutex_exit(&sc->sc_lock);
3153 1.53 augustss if (err)
3154 1.260 skrll return err;
3155 1.46 augustss
3156 1.46 augustss /* Pipe isn't running, start first */
3157 1.260 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3158 1.17 augustss }
3159 1.17 augustss
3160 1.82 augustss Static usbd_status
3161 1.260 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3162 1.1 augustss {
3163 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3164 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3165 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3166 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3167 1.260 skrll ohci_soft_td_t *data, *last, *tail;
3168 1.224 mrg int len, isread, endpt;
3169 1.1 augustss
3170 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3171 1.260 skrll
3172 1.83 augustss if (sc->sc_dying)
3173 1.260 skrll return USBD_IOERROR;
3174 1.83 augustss
3175 1.274 pgoyette DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer,
3176 1.274 pgoyette xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv);
3177 1.1 augustss
3178 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3179 1.1 augustss
3180 1.260 skrll len = xfer->ux_length;
3181 1.260 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3182 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3183 1.1 augustss
3184 1.260 skrll mutex_enter(&sc->sc_lock);
3185 1.260 skrll
3186 1.260 skrll /*
3187 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3188 1.260 skrll * next transfer.
3189 1.260 skrll */
3190 1.60 augustss data = opipe->tail.td;
3191 1.260 skrll opipe->tail.td = ox->ox_stds[0];
3192 1.260 skrll ox->ox_stds[0] = data;
3193 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3194 1.260 skrll
3195 1.260 skrll /* point at sentinel */
3196 1.260 skrll tail = opipe->tail.td;
3197 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
3198 1.260 skrll tail->nexttd = NULL;
3199 1.53 augustss tail->xfer = NULL;
3200 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3201 1.273 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3202 1.260 skrll xfer->ux_hcpriv = data;
3203 1.260 skrll
3204 1.274 pgoyette DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0],
3205 1.274 pgoyette (uintptr_t)tail, 0, 0);
3206 1.260 skrll KASSERT(opipe->tail.td == tail);
3207 1.260 skrll
3208 1.260 skrll /* We want interrupt at the end of the transfer. */
3209 1.260 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3210 1.260 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3211 1.1 augustss
3212 1.260 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3213 1.260 skrll last->nexttd = tail;
3214 1.260 skrll last->flags |= OHCI_CALL_DONE;
3215 1.260 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3216 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3217 1.1 augustss
3218 1.52 augustss #ifdef OHCI_DEBUG
3219 1.260 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3220 1.260 skrll if (ohcidebug >= 5) {
3221 1.168 augustss ohci_dump_ed(sc, sed);
3222 1.168 augustss ohci_dump_tds(sc, data);
3223 1.1 augustss }
3224 1.260 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3225 1.1 augustss #endif
3226 1.1 augustss
3227 1.1 augustss /* Insert ED in schedule */
3228 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3229 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3230 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3231 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3232 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3233 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3234 1.1 augustss
3235 1.224 mrg mutex_exit(&sc->sc_lock);
3236 1.1 augustss
3237 1.260 skrll return USBD_IN_PROGRESS;
3238 1.1 augustss }
3239 1.1 augustss
3240 1.227 skrll /* Abort a device interrupt request. */
3241 1.82 augustss Static void
3242 1.260 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3243 1.1 augustss {
3244 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3245 1.224 mrg
3246 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3247 1.260 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3248 1.224 mrg
3249 1.54 augustss ohci_abort_xfer(xfer, USBD_CANCELLED);
3250 1.1 augustss }
3251 1.1 augustss
3252 1.1 augustss /* Close a device interrupt pipe. */
3253 1.82 augustss Static void
3254 1.260 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3255 1.1 augustss {
3256 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3257 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3258 1.260 skrll int nslots = opipe->intr.nslots;
3259 1.260 skrll int pos = opipe->intr.pos;
3260 1.1 augustss int j;
3261 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3262 1.224 mrg
3263 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3264 1.260 skrll
3265 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3266 1.1 augustss
3267 1.274 pgoyette DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots,
3268 1.274 pgoyette pos, 0);
3269 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3270 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3271 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3272 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3273 1.195 bouyer sizeof(sed->ed.ed_flags),
3274 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3275 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3276 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3277 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3278 1.1 augustss
3279 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3280 1.172 christos continue;
3281 1.260 skrll KASSERT(p);
3282 1.173 christos p->next = sed->next;
3283 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3284 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3285 1.195 bouyer sizeof(p->ed.ed_nexted),
3286 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3287 1.1 augustss
3288 1.1 augustss for (j = 0; j < nslots; j++)
3289 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3290 1.1 augustss
3291 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
3292 1.260 skrll ohci_free_sed_locked(sc, opipe->sed);
3293 1.1 augustss }
3294 1.1 augustss
3295 1.82 augustss Static usbd_status
3296 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3297 1.1 augustss {
3298 1.224 mrg int i, j, best;
3299 1.1 augustss u_int npoll, slow, shigh, nslots;
3300 1.1 augustss u_int bestbw, bw;
3301 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3302 1.1 augustss
3303 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3304 1.260 skrll
3305 1.274 pgoyette DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0);
3306 1.1 augustss if (ival == 0) {
3307 1.1 augustss printf("ohci_setintr: 0 interval\n");
3308 1.260 skrll return USBD_INVAL;
3309 1.1 augustss }
3310 1.1 augustss
3311 1.1 augustss npoll = OHCI_NO_INTRS;
3312 1.1 augustss while (npoll > ival)
3313 1.1 augustss npoll /= 2;
3314 1.274 pgoyette DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0);
3315 1.1 augustss
3316 1.1 augustss /*
3317 1.1 augustss * We now know which level in the tree the ED must go into.
3318 1.1 augustss * Figure out which slot has most bandwidth left over.
3319 1.1 augustss * Slots to examine:
3320 1.1 augustss * npoll
3321 1.1 augustss * 1 0
3322 1.1 augustss * 2 1 2
3323 1.1 augustss * 4 3 4 5 6
3324 1.1 augustss * 8 7 8 9 10 11 12 13 14
3325 1.1 augustss * N (N-1) .. (N-1+N-1)
3326 1.1 augustss */
3327 1.1 augustss slow = npoll-1;
3328 1.1 augustss shigh = slow + npoll;
3329 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3330 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3331 1.1 augustss bw = 0;
3332 1.1 augustss for (j = 0; j < nslots; j++)
3333 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3334 1.1 augustss if (bw < bestbw) {
3335 1.1 augustss best = i;
3336 1.1 augustss bestbw = bw;
3337 1.1 augustss }
3338 1.1 augustss }
3339 1.274 pgoyette DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw);
3340 1.1 augustss
3341 1.224 mrg mutex_enter(&sc->sc_lock);
3342 1.1 augustss hsed = sc->sc_eds[best];
3343 1.1 augustss sed->next = hsed->next;
3344 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3345 1.195 bouyer sizeof(hsed->ed.ed_flags),
3346 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3347 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3348 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3349 1.195 bouyer sizeof(sed->ed.ed_flags),
3350 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3351 1.1 augustss hsed->next = sed;
3352 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3353 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3354 1.195 bouyer sizeof(hsed->ed.ed_flags),
3355 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3356 1.224 mrg mutex_exit(&sc->sc_lock);
3357 1.1 augustss
3358 1.1 augustss for (j = 0; j < nslots; j++)
3359 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3360 1.260 skrll opipe->intr.nslots = nslots;
3361 1.260 skrll opipe->intr.pos = best;
3362 1.1 augustss
3363 1.274 pgoyette DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0);
3364 1.260 skrll return USBD_NORMAL_COMPLETION;
3365 1.60 augustss }
3366 1.60 augustss
3367 1.60 augustss /***********************/
3368 1.60 augustss
3369 1.260 skrll Static int
3370 1.260 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3371 1.260 skrll {
3372 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3373 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3374 1.260 skrll ohci_soft_itd_t *sitd;
3375 1.260 skrll size_t i;
3376 1.260 skrll int err;
3377 1.260 skrll
3378 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3379 1.260 skrll
3380 1.274 pgoyette DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer,
3381 1.274 pgoyette xfer->ux_length, xfer->ux_flags, 0);
3382 1.260 skrll
3383 1.260 skrll const size_t nfsitd =
3384 1.260 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3385 1.260 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3386 1.260 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3387 1.260 skrll
3388 1.260 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3389 1.260 skrll KM_SLEEP);
3390 1.260 skrll ox->ox_nsitd = nsitd;
3391 1.260 skrll
3392 1.260 skrll for (i = 0; i < nsitd; i++) {
3393 1.260 skrll /* Allocate next ITD */
3394 1.260 skrll sitd = ohci_alloc_sitd(sc);
3395 1.260 skrll if (sitd == NULL) {
3396 1.260 skrll err = ENOMEM;
3397 1.260 skrll goto fail;
3398 1.260 skrll }
3399 1.260 skrll ox->ox_sitds[i] = sitd;
3400 1.260 skrll sitd->xfer = xfer;
3401 1.260 skrll sitd->flags = 0;
3402 1.260 skrll }
3403 1.260 skrll
3404 1.260 skrll return 0;
3405 1.260 skrll fail:
3406 1.260 skrll for (; i > 0;) {
3407 1.260 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3408 1.260 skrll }
3409 1.260 skrll return err;
3410 1.260 skrll }
3411 1.260 skrll
3412 1.260 skrll Static void
3413 1.260 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3414 1.260 skrll {
3415 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3416 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3417 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3418 1.260 skrll
3419 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3420 1.260 skrll
3421 1.260 skrll mutex_enter(&sc->sc_lock);
3422 1.260 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3423 1.260 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3424 1.260 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3425 1.260 skrll }
3426 1.260 skrll }
3427 1.260 skrll mutex_exit(&sc->sc_lock);
3428 1.260 skrll
3429 1.260 skrll if (ox->ox_nsitd) {
3430 1.260 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3431 1.260 skrll kmem_free(ox->ox_sitds, sz);
3432 1.260 skrll }
3433 1.260 skrll }
3434 1.260 skrll
3435 1.260 skrll
3436 1.60 augustss usbd_status
3437 1.260 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3438 1.60 augustss {
3439 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3440 1.260 skrll usbd_status __diagused err;
3441 1.260 skrll
3442 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3443 1.60 augustss
3444 1.274 pgoyette DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3445 1.60 augustss
3446 1.60 augustss /* Put it on our queue, */
3447 1.224 mrg mutex_enter(&sc->sc_lock);
3448 1.60 augustss err = usb_insert_transfer(xfer);
3449 1.224 mrg mutex_exit(&sc->sc_lock);
3450 1.60 augustss
3451 1.260 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3452 1.60 augustss
3453 1.60 augustss /* insert into schedule, */
3454 1.60 augustss ohci_device_isoc_enter(xfer);
3455 1.60 augustss
3456 1.83 augustss /* and start if the pipe wasn't running */
3457 1.260 skrll return USBD_IN_PROGRESS;
3458 1.60 augustss }
3459 1.60 augustss
3460 1.60 augustss void
3461 1.260 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3462 1.60 augustss {
3463 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3464 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3465 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3466 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3467 1.260 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3468 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3469 1.61 augustss int i, ncur, nframes;
3470 1.61 augustss
3471 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3472 1.274 pgoyette DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3473 1.260 skrll
3474 1.260 skrll mutex_enter(&sc->sc_lock);
3475 1.83 augustss
3476 1.260 skrll if (sc->sc_dying) {
3477 1.260 skrll mutex_exit(&sc->sc_lock);
3478 1.83 augustss return;
3479 1.260 skrll }
3480 1.260 skrll
3481 1.260 skrll struct isoc *isoc = &opipe->isoc;
3482 1.260 skrll
3483 1.274 pgoyette DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd",
3484 1.274 pgoyette isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes);
3485 1.83 augustss
3486 1.260 skrll if (isoc->next == -1) {
3487 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3488 1.260 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3489 1.274 pgoyette DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0);
3490 1.83 augustss }
3491 1.83 augustss
3492 1.61 augustss sitd = opipe->tail.itd;
3493 1.260 skrll opipe->tail.itd = ox->ox_sitds[0];
3494 1.260 skrll ox->ox_sitds[0] = sitd;
3495 1.260 skrll
3496 1.260 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3497 1.83 augustss bp0 = OHCI_PAGE(buf);
3498 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3499 1.260 skrll nframes = xfer->ux_nframes;
3500 1.260 skrll xfer->ux_hcpriv = sitd;
3501 1.260 skrll size_t j = 1;
3502 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3503 1.260 skrll noffs = offs + xfer->ux_frlengths[i];
3504 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3505 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3506 1.120 augustss
3507 1.83 augustss /* Allocate next ITD */
3508 1.260 skrll nsitd = ox->ox_sitds[j++];
3509 1.260 skrll KASSERT(nsitd != NULL);
3510 1.260 skrll KASSERT(j < ox->ox_nsitd);
3511 1.83 augustss
3512 1.83 augustss /* Fill current ITD */
3513 1.168 augustss sitd->itd.itd_flags = HTOO32(
3514 1.120 augustss OHCI_ITD_NOCC |
3515 1.260 skrll OHCI_ITD_SET_SF(isoc->next) |
3516 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3517 1.83 augustss OHCI_ITD_SET_FC(ncur));
3518 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3519 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3520 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3521 1.260 skrll sitd->nextitd = nsitd;
3522 1.83 augustss sitd->xfer = xfer;
3523 1.83 augustss sitd->flags = 0;
3524 1.260 skrll #ifdef DIAGNOSTIC
3525 1.260 skrll sitd->isdone = false;
3526 1.260 skrll #endif
3527 1.260 skrll ohci_hash_add_itd(sc, sitd);
3528 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3529 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3530 1.83 augustss
3531 1.61 augustss sitd = nsitd;
3532 1.260 skrll isoc->next = isoc->next + ncur;
3533 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3534 1.61 augustss ncur = 0;
3535 1.61 augustss }
3536 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3537 1.273 skrll /* XXX Sync */
3538 1.83 augustss offs = noffs;
3539 1.61 augustss }
3540 1.260 skrll KASSERT(j <= ox->ox_nsitd);
3541 1.260 skrll
3542 1.260 skrll /* point at sentinel */
3543 1.260 skrll tail = opipe->tail.itd;
3544 1.260 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3545 1.260 skrll tail->nextitd = NULL;
3546 1.265 skrll tail->xfer = NULL;
3547 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3548 1.260 skrll BUS_DMASYNC_PREWRITE);
3549 1.260 skrll
3550 1.83 augustss /* Fixup last used ITD */
3551 1.168 augustss sitd->itd.itd_flags = HTOO32(
3552 1.120 augustss OHCI_ITD_NOCC |
3553 1.260 skrll OHCI_ITD_SET_SF(isoc->next) |
3554 1.61 augustss OHCI_ITD_SET_DI(0) |
3555 1.61 augustss OHCI_ITD_SET_FC(ncur));
3556 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3557 1.260 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3558 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3559 1.260 skrll sitd->nextitd = tail;
3560 1.83 augustss sitd->xfer = xfer;
3561 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3562 1.260 skrll #ifdef DIAGNOSTIC
3563 1.260 skrll sitd->isdone = false;
3564 1.260 skrll #endif
3565 1.260 skrll ohci_hash_add_itd(sc, sitd);
3566 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3567 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3568 1.83 augustss
3569 1.260 skrll isoc->next = isoc->next + ncur;
3570 1.260 skrll isoc->inuse += nframes;
3571 1.83 augustss
3572 1.260 skrll /* XXX pretend we did it all */
3573 1.260 skrll xfer->ux_actlen = offs;
3574 1.260 skrll xfer->ux_status = USBD_IN_PROGRESS;
3575 1.83 augustss
3576 1.83 augustss #ifdef OHCI_DEBUG
3577 1.260 skrll if (ohcidebug >= 5) {
3578 1.274 pgoyette DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number),
3579 1.260 skrll 0, 0, 0);
3580 1.260 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3581 1.168 augustss ohci_dump_ed(sc, sed);
3582 1.83 augustss }
3583 1.83 augustss #endif
3584 1.61 augustss
3585 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3586 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3587 1.260 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3588 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3589 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3590 1.195 bouyer sizeof(sed->ed.ed_flags),
3591 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3592 1.224 mrg mutex_exit(&sc->sc_lock);
3593 1.60 augustss }
3594 1.60 augustss
3595 1.60 augustss void
3596 1.260 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3597 1.60 augustss {
3598 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3599 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3600 1.83 augustss ohci_soft_ed_t *sed;
3601 1.83 augustss ohci_soft_itd_t *sitd;
3602 1.83 augustss
3603 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3604 1.274 pgoyette DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3605 1.83 augustss
3606 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3607 1.83 augustss
3608 1.83 augustss /* Transfer is already done. */
3609 1.260 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3610 1.260 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3611 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3612 1.224 mrg goto done;
3613 1.83 augustss }
3614 1.83 augustss
3615 1.83 augustss /* Give xfer the requested abort code. */
3616 1.260 skrll xfer->ux_status = USBD_CANCELLED;
3617 1.83 augustss
3618 1.83 augustss sed = opipe->sed;
3619 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3620 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3621 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3622 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3623 1.195 bouyer sizeof(sed->ed.ed_flags),
3624 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3625 1.83 augustss
3626 1.260 skrll sitd = xfer->ux_hcpriv;
3627 1.260 skrll KASSERT(sitd);
3628 1.260 skrll
3629 1.260 skrll usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3630 1.260 skrll
3631 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3632 1.260 skrll ohci_hash_rem_itd(sc, sitd);
3633 1.83 augustss #ifdef DIAGNOSTIC
3634 1.274 pgoyette DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd,
3635 1.274 pgoyette 0, 0, 0);
3636 1.260 skrll sitd->isdone = true;
3637 1.83 augustss #endif
3638 1.83 augustss }
3639 1.83 augustss
3640 1.83 augustss /* Run callback. */
3641 1.83 augustss usb_transfer_complete(xfer);
3642 1.83 augustss
3643 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3644 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3645 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3646 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3647 1.83 augustss
3648 1.224 mrg done:
3649 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3650 1.60 augustss }
3651 1.60 augustss
3652 1.60 augustss void
3653 1.260 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3654 1.60 augustss {
3655 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3656 1.274 pgoyette DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3657 1.60 augustss }
3658 1.60 augustss
3659 1.60 augustss usbd_status
3660 1.260 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3661 1.60 augustss {
3662 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3663 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3664 1.260 skrll struct isoc *isoc = &opipe->isoc;
3665 1.60 augustss
3666 1.260 skrll isoc->next = -1;
3667 1.260 skrll isoc->inuse = 0;
3668 1.60 augustss
3669 1.224 mrg mutex_enter(&sc->sc_lock);
3670 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3671 1.224 mrg mutex_exit(&sc->sc_lock);
3672 1.83 augustss
3673 1.260 skrll return USBD_NORMAL_COMPLETION;
3674 1.60 augustss }
3675 1.60 augustss
3676 1.60 augustss void
3677 1.260 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3678 1.60 augustss {
3679 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3680 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3681 1.60 augustss
3682 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3683 1.224 mrg
3684 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3685 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3686 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3687 1.83 augustss #ifdef DIAGNOSTIC
3688 1.260 skrll opipe->tail.itd->isdone = true;
3689 1.83 augustss #endif
3690 1.260 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3691 1.1 augustss }
3692