ohci.c revision 1.293 1 1.293 riastrad /* $NetBSD: ohci.c,v 1.293 2020/02/12 16:01:00 riastradh Exp $ */
2 1.1 augustss
3 1.1 augustss /*
4 1.224 mrg * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc.
5 1.1 augustss * All rights reserved.
6 1.1 augustss *
7 1.11 augustss * This code is derived from software contributed to The NetBSD Foundation
8 1.89 augustss * by Lennart Augustsson (lennart (at) augustsson.net) at
9 1.224 mrg * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca)
10 1.224 mrg * and Matthew R. Green (mrg (at) eterna.com.au).
11 1.157 mycroft * This code is derived from software contributed to The NetBSD Foundation
12 1.157 mycroft * by Charles M. Hannum.
13 1.1 augustss *
14 1.1 augustss * Redistribution and use in source and binary forms, with or without
15 1.1 augustss * modification, are permitted provided that the following conditions
16 1.1 augustss * are met:
17 1.1 augustss * 1. Redistributions of source code must retain the above copyright
18 1.1 augustss * notice, this list of conditions and the following disclaimer.
19 1.1 augustss * 2. Redistributions in binary form must reproduce the above copyright
20 1.1 augustss * notice, this list of conditions and the following disclaimer in the
21 1.1 augustss * documentation and/or other materials provided with the distribution.
22 1.1 augustss *
23 1.1 augustss * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24 1.1 augustss * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 1.1 augustss * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 1.1 augustss * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27 1.1 augustss * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 1.1 augustss * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 1.1 augustss * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 1.1 augustss * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 1.1 augustss * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 1.1 augustss * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 1.1 augustss * POSSIBILITY OF SUCH DAMAGE.
34 1.1 augustss */
35 1.1 augustss
36 1.1 augustss /*
37 1.1 augustss * USB Open Host Controller driver.
38 1.1 augustss *
39 1.96 augustss * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html
40 1.201 uebayasi * USB spec: http://www.usb.org/developers/docs/
41 1.1 augustss */
42 1.108 lukem
43 1.108 lukem #include <sys/cdefs.h>
44 1.293 riastrad __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.293 2020/02/12 16:01:00 riastradh Exp $");
45 1.260 skrll
46 1.263 pooka #ifdef _KERNEL_OPT
47 1.260 skrll #include "opt_usb.h"
48 1.263 pooka #endif
49 1.1 augustss
50 1.1 augustss #include <sys/param.h>
51 1.260 skrll
52 1.260 skrll #include <sys/cpu.h>
53 1.260 skrll #include <sys/device.h>
54 1.260 skrll #include <sys/kernel.h>
55 1.224 mrg #include <sys/kmem.h>
56 1.1 augustss #include <sys/proc.h>
57 1.1 augustss #include <sys/queue.h>
58 1.260 skrll #include <sys/select.h>
59 1.260 skrll #include <sys/sysctl.h>
60 1.260 skrll #include <sys/systm.h>
61 1.1 augustss
62 1.16 augustss #include <machine/endian.h>
63 1.4 augustss
64 1.1 augustss #include <dev/usb/usb.h>
65 1.1 augustss #include <dev/usb/usbdi.h>
66 1.1 augustss #include <dev/usb/usbdivar.h>
67 1.38 augustss #include <dev/usb/usb_mem.h>
68 1.1 augustss #include <dev/usb/usb_quirks.h>
69 1.1 augustss
70 1.1 augustss #include <dev/usb/ohcireg.h>
71 1.1 augustss #include <dev/usb/ohcivar.h>
72 1.260 skrll #include <dev/usb/usbroothub.h>
73 1.260 skrll #include <dev/usb/usbhist.h>
74 1.260 skrll
75 1.260 skrll #ifdef USB_DEBUG
76 1.260 skrll #ifndef OHCI_DEBUG
77 1.260 skrll #define ohcidebug 0
78 1.260 skrll #else
79 1.260 skrll static int ohcidebug = 10;
80 1.260 skrll
81 1.260 skrll SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup")
82 1.260 skrll {
83 1.260 skrll int err;
84 1.260 skrll const struct sysctlnode *rnode;
85 1.260 skrll const struct sysctlnode *cnode;
86 1.260 skrll
87 1.260 skrll err = sysctl_createv(clog, 0, NULL, &rnode,
88 1.260 skrll CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci",
89 1.260 skrll SYSCTL_DESCR("ohci global controls"),
90 1.260 skrll NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL);
91 1.1 augustss
92 1.260 skrll if (err)
93 1.260 skrll goto fail;
94 1.260 skrll
95 1.260 skrll /* control debugging printfs */
96 1.260 skrll err = sysctl_createv(clog, 0, &rnode, &cnode,
97 1.260 skrll CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT,
98 1.260 skrll "debug", SYSCTL_DESCR("Enable debugging output"),
99 1.260 skrll NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL);
100 1.260 skrll if (err)
101 1.260 skrll goto fail;
102 1.260 skrll
103 1.260 skrll return;
104 1.260 skrll fail:
105 1.260 skrll aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err);
106 1.260 skrll }
107 1.1 augustss
108 1.260 skrll #endif /* OHCI_DEBUG */
109 1.260 skrll #endif /* USB_DEBUG */
110 1.36 augustss
111 1.260 skrll #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D)
112 1.260 skrll #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D)
113 1.260 skrll #define OHCIHIST_FUNC() USBHIST_FUNC()
114 1.260 skrll #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug)
115 1.52 augustss
116 1.16 augustss #if BYTE_ORDER == BIG_ENDIAN
117 1.169 tron #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN
118 1.16 augustss #else
119 1.169 tron #define SWAP_ENDIAN OHCI_BIG_ENDIAN
120 1.16 augustss #endif
121 1.16 augustss
122 1.169 tron #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val)
123 1.169 tron #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val)
124 1.169 tron #define HTOO16(val) O16TOH(val)
125 1.169 tron #define HTOO32(val) O32TOH(val)
126 1.168 augustss
127 1.1 augustss struct ohci_pipe;
128 1.1 augustss
129 1.91 augustss Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *);
130 1.91 augustss Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *);
131 1.1 augustss
132 1.91 augustss Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *);
133 1.91 augustss Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *);
134 1.260 skrll Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *);
135 1.1 augustss
136 1.91 augustss Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *);
137 1.91 augustss Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *);
138 1.260 skrll Static void ohci_free_sitd_locked(ohci_softc_t *,
139 1.260 skrll ohci_soft_itd_t *);
140 1.60 augustss
141 1.260 skrll Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *,
142 1.260 skrll int, int);
143 1.260 skrll Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *);
144 1.53 augustss
145 1.260 skrll Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *,
146 1.260 skrll int, int, ohci_soft_td_t *, ohci_soft_td_t **);
147 1.260 skrll
148 1.260 skrll Static usbd_status ohci_open(struct usbd_pipe *);
149 1.91 augustss Static void ohci_poll(struct usbd_bus *);
150 1.99 augustss Static void ohci_softintr(void *);
151 1.260 skrll Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *);
152 1.260 skrll Static void ohci_rhsc_softint(void *);
153 1.91 augustss
154 1.168 augustss Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *,
155 1.168 augustss ohci_soft_ed_t *);
156 1.168 augustss
157 1.224 mrg Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *,
158 1.224 mrg ohci_soft_ed_t *);
159 1.91 augustss Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *);
160 1.91 augustss Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *);
161 1.91 augustss Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t);
162 1.91 augustss Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *);
163 1.91 augustss Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *);
164 1.91 augustss Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t);
165 1.91 augustss
166 1.260 skrll Static usbd_status ohci_setup_isoc(struct usbd_pipe *);
167 1.260 skrll Static void ohci_device_isoc_enter(struct usbd_xfer *);
168 1.91 augustss
169 1.260 skrll Static struct usbd_xfer *
170 1.260 skrll ohci_allocx(struct usbd_bus *, unsigned int);
171 1.260 skrll Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *);
172 1.293 riastrad Static bool ohci_dying(struct usbd_bus *);
173 1.224 mrg Static void ohci_get_lock(struct usbd_bus *, kmutex_t **);
174 1.260 skrll Static int ohci_roothub_ctrl(struct usbd_bus *,
175 1.260 skrll usb_device_request_t *, void *, int);
176 1.91 augustss
177 1.260 skrll Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *);
178 1.260 skrll Static usbd_status ohci_root_intr_start(struct usbd_xfer *);
179 1.260 skrll Static void ohci_root_intr_abort(struct usbd_xfer *);
180 1.260 skrll Static void ohci_root_intr_close(struct usbd_pipe *);
181 1.260 skrll Static void ohci_root_intr_done(struct usbd_xfer *);
182 1.260 skrll
183 1.260 skrll Static int ohci_device_ctrl_init(struct usbd_xfer *);
184 1.260 skrll Static void ohci_device_ctrl_fini(struct usbd_xfer *);
185 1.260 skrll Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *);
186 1.260 skrll Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *);
187 1.260 skrll Static void ohci_device_ctrl_abort(struct usbd_xfer *);
188 1.260 skrll Static void ohci_device_ctrl_close(struct usbd_pipe *);
189 1.260 skrll Static void ohci_device_ctrl_done(struct usbd_xfer *);
190 1.260 skrll
191 1.260 skrll Static int ohci_device_bulk_init(struct usbd_xfer *);
192 1.260 skrll Static void ohci_device_bulk_fini(struct usbd_xfer *);
193 1.260 skrll Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *);
194 1.260 skrll Static usbd_status ohci_device_bulk_start(struct usbd_xfer *);
195 1.260 skrll Static void ohci_device_bulk_abort(struct usbd_xfer *);
196 1.260 skrll Static void ohci_device_bulk_close(struct usbd_pipe *);
197 1.260 skrll Static void ohci_device_bulk_done(struct usbd_xfer *);
198 1.260 skrll
199 1.260 skrll Static int ohci_device_intr_init(struct usbd_xfer *);
200 1.260 skrll Static void ohci_device_intr_fini(struct usbd_xfer *);
201 1.260 skrll Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *);
202 1.260 skrll Static usbd_status ohci_device_intr_start(struct usbd_xfer *);
203 1.260 skrll Static void ohci_device_intr_abort(struct usbd_xfer *);
204 1.260 skrll Static void ohci_device_intr_close(struct usbd_pipe *);
205 1.260 skrll Static void ohci_device_intr_done(struct usbd_xfer *);
206 1.260 skrll
207 1.260 skrll Static int ohci_device_isoc_init(struct usbd_xfer *);
208 1.260 skrll Static void ohci_device_isoc_fini(struct usbd_xfer *);
209 1.260 skrll Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *);
210 1.260 skrll Static void ohci_device_isoc_abort(struct usbd_xfer *);
211 1.260 skrll Static void ohci_device_isoc_close(struct usbd_pipe *);
212 1.260 skrll Static void ohci_device_isoc_done(struct usbd_xfer *);
213 1.91 augustss
214 1.260 skrll Static usbd_status ohci_device_setintr(ohci_softc_t *,
215 1.260 skrll struct ohci_pipe *, int);
216 1.91 augustss
217 1.104 augustss Static void ohci_rhsc_enable(void *);
218 1.91 augustss
219 1.260 skrll Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *);
220 1.293 riastrad Static void ohci_abortx(struct usbd_xfer *);
221 1.53 augustss
222 1.260 skrll Static void ohci_device_clear_toggle(struct usbd_pipe *);
223 1.260 skrll Static void ohci_noop(struct usbd_pipe *);
224 1.37 augustss
225 1.52 augustss #ifdef OHCI_DEBUG
226 1.91 augustss Static void ohci_dumpregs(ohci_softc_t *);
227 1.168 augustss Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *);
228 1.168 augustss Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *);
229 1.168 augustss Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *);
230 1.168 augustss Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *);
231 1.168 augustss Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *);
232 1.1 augustss #endif
233 1.1 augustss
234 1.88 augustss #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \
235 1.88 augustss BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
236 1.88 augustss #define OWRITE1(sc, r, x) \
237 1.88 augustss do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
238 1.88 augustss #define OWRITE2(sc, r, x) \
239 1.88 augustss do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
240 1.88 augustss #define OWRITE4(sc, r, x) \
241 1.88 augustss do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0)
242 1.174 mrg
243 1.174 mrg static __inline uint32_t
244 1.174 mrg OREAD4(ohci_softc_t *sc, bus_size_t r)
245 1.174 mrg {
246 1.174 mrg
247 1.174 mrg OBARR(sc);
248 1.174 mrg return bus_space_read_4(sc->iot, sc->ioh, r);
249 1.174 mrg }
250 1.1 augustss
251 1.1 augustss /* Reverse the bits in a value 0 .. 31 */
252 1.260 skrll Static uint8_t revbits[OHCI_NO_INTRS] =
253 1.1 augustss { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
254 1.1 augustss 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
255 1.1 augustss 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
256 1.1 augustss 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
257 1.1 augustss
258 1.1 augustss struct ohci_pipe {
259 1.1 augustss struct usbd_pipe pipe;
260 1.1 augustss ohci_soft_ed_t *sed;
261 1.60 augustss union {
262 1.60 augustss ohci_soft_td_t *td;
263 1.60 augustss ohci_soft_itd_t *itd;
264 1.60 augustss } tail;
265 1.1 augustss /* Info needed for different pipe kinds. */
266 1.1 augustss union {
267 1.1 augustss /* Control pipe */
268 1.1 augustss struct {
269 1.4 augustss usb_dma_t reqdma;
270 1.260 skrll } ctrl;
271 1.1 augustss /* Interrupt pipe */
272 1.1 augustss struct {
273 1.1 augustss int nslots;
274 1.1 augustss int pos;
275 1.1 augustss } intr;
276 1.260 skrll /* Isochronous pipe */
277 1.260 skrll struct isoc {
278 1.60 augustss int next, inuse;
279 1.260 skrll } isoc;
280 1.260 skrll };
281 1.1 augustss };
282 1.1 augustss
283 1.182 drochner Static const struct usbd_bus_methods ohci_bus_methods = {
284 1.260 skrll .ubm_open = ohci_open,
285 1.260 skrll .ubm_softint = ohci_softintr,
286 1.260 skrll .ubm_dopoll = ohci_poll,
287 1.260 skrll .ubm_allocx = ohci_allocx,
288 1.260 skrll .ubm_freex = ohci_freex,
289 1.293 riastrad .ubm_abortx = ohci_abortx,
290 1.293 riastrad .ubm_dying = ohci_dying,
291 1.260 skrll .ubm_getlock = ohci_get_lock,
292 1.260 skrll .ubm_rhctrl = ohci_roothub_ctrl,
293 1.1 augustss };
294 1.1 augustss
295 1.182 drochner Static const struct usbd_pipe_methods ohci_root_intr_methods = {
296 1.260 skrll .upm_transfer = ohci_root_intr_transfer,
297 1.260 skrll .upm_start = ohci_root_intr_start,
298 1.260 skrll .upm_abort = ohci_root_intr_abort,
299 1.260 skrll .upm_close = ohci_root_intr_close,
300 1.260 skrll .upm_cleartoggle = ohci_noop,
301 1.260 skrll .upm_done = ohci_root_intr_done,
302 1.1 augustss };
303 1.1 augustss
304 1.182 drochner Static const struct usbd_pipe_methods ohci_device_ctrl_methods = {
305 1.260 skrll .upm_init = ohci_device_ctrl_init,
306 1.260 skrll .upm_fini = ohci_device_ctrl_fini,
307 1.260 skrll .upm_transfer = ohci_device_ctrl_transfer,
308 1.260 skrll .upm_start = ohci_device_ctrl_start,
309 1.260 skrll .upm_abort = ohci_device_ctrl_abort,
310 1.260 skrll .upm_close = ohci_device_ctrl_close,
311 1.260 skrll .upm_cleartoggle = ohci_noop,
312 1.260 skrll .upm_done = ohci_device_ctrl_done,
313 1.1 augustss };
314 1.1 augustss
315 1.182 drochner Static const struct usbd_pipe_methods ohci_device_intr_methods = {
316 1.260 skrll .upm_init = ohci_device_intr_init,
317 1.260 skrll .upm_fini = ohci_device_intr_fini,
318 1.260 skrll .upm_transfer = ohci_device_intr_transfer,
319 1.260 skrll .upm_start = ohci_device_intr_start,
320 1.260 skrll .upm_abort = ohci_device_intr_abort,
321 1.260 skrll .upm_close = ohci_device_intr_close,
322 1.260 skrll .upm_cleartoggle = ohci_device_clear_toggle,
323 1.260 skrll .upm_done = ohci_device_intr_done,
324 1.1 augustss };
325 1.1 augustss
326 1.182 drochner Static const struct usbd_pipe_methods ohci_device_bulk_methods = {
327 1.260 skrll .upm_init = ohci_device_bulk_init,
328 1.260 skrll .upm_fini = ohci_device_bulk_fini,
329 1.260 skrll .upm_transfer = ohci_device_bulk_transfer,
330 1.260 skrll .upm_start = ohci_device_bulk_start,
331 1.260 skrll .upm_abort = ohci_device_bulk_abort,
332 1.260 skrll .upm_close = ohci_device_bulk_close,
333 1.260 skrll .upm_cleartoggle = ohci_device_clear_toggle,
334 1.260 skrll .upm_done = ohci_device_bulk_done,
335 1.3 augustss };
336 1.3 augustss
337 1.182 drochner Static const struct usbd_pipe_methods ohci_device_isoc_methods = {
338 1.260 skrll .upm_init = ohci_device_isoc_init,
339 1.260 skrll .upm_fini = ohci_device_isoc_fini,
340 1.260 skrll .upm_transfer = ohci_device_isoc_transfer,
341 1.260 skrll .upm_abort = ohci_device_isoc_abort,
342 1.260 skrll .upm_close = ohci_device_isoc_close,
343 1.260 skrll .upm_cleartoggle = ohci_noop,
344 1.260 skrll .upm_done = ohci_device_isoc_done,
345 1.43 augustss };
346 1.43 augustss
347 1.47 augustss int
348 1.189 dyoung ohci_activate(device_t self, enum devact act)
349 1.47 augustss {
350 1.189 dyoung struct ohci_softc *sc = device_private(self);
351 1.47 augustss
352 1.47 augustss switch (act) {
353 1.47 augustss case DVACT_DEACTIVATE:
354 1.183 kiyohara sc->sc_dying = 1;
355 1.203 dyoung return 0;
356 1.203 dyoung default:
357 1.203 dyoung return EOPNOTSUPP;
358 1.47 augustss }
359 1.47 augustss }
360 1.47 augustss
361 1.187 dyoung void
362 1.187 dyoung ohci_childdet(device_t self, device_t child)
363 1.187 dyoung {
364 1.187 dyoung struct ohci_softc *sc = device_private(self);
365 1.187 dyoung
366 1.187 dyoung KASSERT(sc->sc_child == child);
367 1.187 dyoung sc->sc_child = NULL;
368 1.187 dyoung }
369 1.187 dyoung
370 1.47 augustss int
371 1.91 augustss ohci_detach(struct ohci_softc *sc, int flags)
372 1.47 augustss {
373 1.47 augustss int rv = 0;
374 1.47 augustss
375 1.47 augustss if (sc->sc_child != NULL)
376 1.47 augustss rv = config_detach(sc->sc_child, flags);
377 1.120 augustss
378 1.47 augustss if (rv != 0)
379 1.260 skrll return rv;
380 1.47 augustss
381 1.277 msaitoh softint_disestablish(sc->sc_rhsc_si);
382 1.104 augustss
383 1.277 msaitoh callout_halt(&sc->sc_tmo_rhsc, NULL);
384 1.209 dyoung callout_destroy(&sc->sc_tmo_rhsc);
385 1.116 augustss
386 1.224 mrg mutex_destroy(&sc->sc_lock);
387 1.224 mrg mutex_destroy(&sc->sc_intr_lock);
388 1.224 mrg
389 1.198 cegger if (sc->sc_hcca != NULL)
390 1.198 cegger usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
391 1.232 christos pool_cache_destroy(sc->sc_xferpool);
392 1.47 augustss
393 1.260 skrll return rv;
394 1.47 augustss }
395 1.47 augustss
396 1.1 augustss ohci_soft_ed_t *
397 1.91 augustss ohci_alloc_sed(ohci_softc_t *sc)
398 1.1 augustss {
399 1.1 augustss ohci_soft_ed_t *sed;
400 1.53 augustss usbd_status err;
401 1.1 augustss int i, offs;
402 1.4 augustss usb_dma_t dma;
403 1.1 augustss
404 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
405 1.260 skrll
406 1.260 skrll mutex_enter(&sc->sc_lock);
407 1.53 augustss if (sc->sc_freeeds == NULL) {
408 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
409 1.260 skrll mutex_exit(&sc->sc_lock);
410 1.260 skrll
411 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK,
412 1.53 augustss OHCI_ED_ALIGN, &dma);
413 1.53 augustss if (err)
414 1.260 skrll return 0;
415 1.260 skrll
416 1.260 skrll mutex_enter(&sc->sc_lock);
417 1.225 skrll for (i = 0; i < OHCI_SED_CHUNK; i++) {
418 1.39 augustss offs = i * OHCI_SED_SIZE;
419 1.123 augustss sed = KERNADDR(&dma, offs);
420 1.125 augustss sed->physaddr = DMAADDR(&dma, offs);
421 1.195 bouyer sed->dma = dma;
422 1.195 bouyer sed->offs = offs;
423 1.1 augustss sed->next = sc->sc_freeeds;
424 1.1 augustss sc->sc_freeeds = sed;
425 1.1 augustss }
426 1.1 augustss }
427 1.1 augustss sed = sc->sc_freeeds;
428 1.1 augustss sc->sc_freeeds = sed->next;
429 1.260 skrll mutex_exit(&sc->sc_lock);
430 1.260 skrll
431 1.39 augustss memset(&sed->ed, 0, sizeof(ohci_ed_t));
432 1.1 augustss sed->next = 0;
433 1.260 skrll return sed;
434 1.260 skrll }
435 1.260 skrll
436 1.260 skrll static inline void
437 1.260 skrll ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed)
438 1.260 skrll {
439 1.260 skrll
440 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
441 1.260 skrll
442 1.260 skrll sed->next = sc->sc_freeeds;
443 1.260 skrll sc->sc_freeeds = sed;
444 1.1 augustss }
445 1.1 augustss
446 1.1 augustss void
447 1.91 augustss ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
448 1.1 augustss {
449 1.260 skrll
450 1.260 skrll mutex_enter(&sc->sc_lock);
451 1.260 skrll ohci_free_sed_locked(sc, sed);
452 1.260 skrll mutex_exit(&sc->sc_lock);
453 1.1 augustss }
454 1.1 augustss
455 1.1 augustss ohci_soft_td_t *
456 1.91 augustss ohci_alloc_std(ohci_softc_t *sc)
457 1.1 augustss {
458 1.1 augustss ohci_soft_td_t *std;
459 1.53 augustss usbd_status err;
460 1.1 augustss int i, offs;
461 1.4 augustss usb_dma_t dma;
462 1.1 augustss
463 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
464 1.240 skrll
465 1.260 skrll mutex_enter(&sc->sc_lock);
466 1.53 augustss if (sc->sc_freetds == NULL) {
467 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
468 1.260 skrll mutex_exit(&sc->sc_lock);
469 1.260 skrll
470 1.53 augustss err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK,
471 1.53 augustss OHCI_TD_ALIGN, &dma);
472 1.53 augustss if (err)
473 1.260 skrll return NULL;
474 1.260 skrll
475 1.260 skrll mutex_enter(&sc->sc_lock);
476 1.259 skrll for (i = 0; i < OHCI_STD_CHUNK; i++) {
477 1.39 augustss offs = i * OHCI_STD_SIZE;
478 1.123 augustss std = KERNADDR(&dma, offs);
479 1.125 augustss std->physaddr = DMAADDR(&dma, offs);
480 1.195 bouyer std->dma = dma;
481 1.195 bouyer std->offs = offs;
482 1.1 augustss std->nexttd = sc->sc_freetds;
483 1.1 augustss sc->sc_freetds = std;
484 1.1 augustss }
485 1.1 augustss }
486 1.69 augustss
487 1.1 augustss std = sc->sc_freetds;
488 1.1 augustss sc->sc_freetds = std->nexttd;
489 1.260 skrll mutex_exit(&sc->sc_lock);
490 1.260 skrll
491 1.39 augustss memset(&std->td, 0, sizeof(ohci_td_t));
492 1.83 augustss std->nexttd = NULL;
493 1.83 augustss std->xfer = NULL;
494 1.69 augustss
495 1.260 skrll return std;
496 1.1 augustss }
497 1.1 augustss
498 1.1 augustss void
499 1.260 skrll ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std)
500 1.1 augustss {
501 1.258 skrll
502 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
503 1.260 skrll
504 1.1 augustss std->nexttd = sc->sc_freetds;
505 1.1 augustss sc->sc_freetds = std;
506 1.1 augustss }
507 1.1 augustss
508 1.260 skrll void
509 1.260 skrll ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std)
510 1.260 skrll {
511 1.260 skrll
512 1.260 skrll mutex_enter(&sc->sc_lock);
513 1.260 skrll ohci_free_std_locked(sc, std);
514 1.260 skrll mutex_exit(&sc->sc_lock);
515 1.260 skrll }
516 1.260 skrll
517 1.260 skrll Static int
518 1.260 skrll ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd)
519 1.260 skrll {
520 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
521 1.260 skrll uint16_t flags = xfer->ux_flags;
522 1.260 skrll
523 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
524 1.260 skrll
525 1.274 pgoyette DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd",
526 1.260 skrll xfer->ux_pipe->up_dev->ud_addr,
527 1.260 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
528 1.260 skrll length, xfer->ux_pipe->up_dev->ud_speed);
529 1.260 skrll
530 1.260 skrll ASSERT_SLEEPABLE();
531 1.260 skrll KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER)));
532 1.260 skrll
533 1.260 skrll size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0;
534 1.260 skrll nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE);
535 1.260 skrll ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd,
536 1.260 skrll KM_SLEEP);
537 1.260 skrll ox->ox_nstd = nstd;
538 1.260 skrll
539 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0);
540 1.260 skrll
541 1.260 skrll for (size_t j = 0; j < ox->ox_nstd;) {
542 1.260 skrll ohci_soft_td_t *cur = ohci_alloc_std(sc);
543 1.260 skrll if (cur == NULL)
544 1.260 skrll goto nomem;
545 1.260 skrll
546 1.260 skrll ox->ox_stds[j++] = cur;
547 1.260 skrll cur->xfer = xfer;
548 1.260 skrll cur->flags = 0;
549 1.260 skrll }
550 1.260 skrll
551 1.260 skrll return 0;
552 1.260 skrll
553 1.260 skrll nomem:
554 1.260 skrll ohci_free_stds(sc, ox);
555 1.260 skrll kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd);
556 1.260 skrll
557 1.260 skrll return ENOMEM;
558 1.260 skrll }
559 1.260 skrll
560 1.260 skrll Static void
561 1.260 skrll ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox)
562 1.260 skrll {
563 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
564 1.274 pgoyette DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0);
565 1.260 skrll
566 1.260 skrll mutex_enter(&sc->sc_lock);
567 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
568 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
569 1.260 skrll if (std == NULL)
570 1.260 skrll break;
571 1.260 skrll ohci_free_std_locked(sc, std);
572 1.260 skrll }
573 1.260 skrll mutex_exit(&sc->sc_lock);
574 1.260 skrll }
575 1.260 skrll
576 1.260 skrll void
577 1.260 skrll ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer,
578 1.260 skrll int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep)
579 1.48 augustss {
580 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
581 1.48 augustss ohci_soft_td_t *next, *cur;
582 1.75 augustss int len, curlen;
583 1.260 skrll usb_dma_t *dma = &xfer->ux_dmabuf;
584 1.260 skrll uint16_t flags = xfer->ux_flags;
585 1.48 augustss
586 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
587 1.274 pgoyette DPRINTF("start len=%jd", alen, 0, 0, 0);
588 1.75 augustss
589 1.289 mrg KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
590 1.224 mrg
591 1.274 pgoyette DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd",
592 1.260 skrll xfer->ux_pipe->up_dev->ud_addr,
593 1.260 skrll UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress),
594 1.260 skrll alen, xfer->ux_pipe->up_dev->ud_speed);
595 1.260 skrll
596 1.260 skrll KASSERT(sp);
597 1.260 skrll
598 1.260 skrll int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize);
599 1.260 skrll
600 1.260 skrll /*
601 1.260 skrll * Assign next for the len == 0 case where we don't go through the
602 1.260 skrll * main loop.
603 1.260 skrll */
604 1.75 augustss len = alen;
605 1.260 skrll cur = next = sp;
606 1.260 skrll
607 1.195 bouyer usb_syncmem(dma, 0, len,
608 1.195 bouyer rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
609 1.260 skrll const uint32_t tdflags = HTOO32(
610 1.120 augustss (rd ? OHCI_TD_IN : OHCI_TD_OUT) |
611 1.77 augustss OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR);
612 1.61 augustss
613 1.260 skrll size_t curoffs = 0;
614 1.260 skrll for (size_t j = 1; len != 0;) {
615 1.260 skrll if (j == ox->ox_nstd)
616 1.260 skrll next = NULL;
617 1.260 skrll else
618 1.260 skrll next = ox->ox_stds[j++];
619 1.260 skrll KASSERT(next != cur);
620 1.260 skrll
621 1.260 skrll curlen = 0;
622 1.270 skrll const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs);
623 1.260 skrll ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1);
624 1.48 augustss
625 1.270 skrll const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys);
626 1.260 skrll ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys);
627 1.260 skrll /*
628 1.260 skrll * The OHCI hardware can handle at most one page
629 1.260 skrll * crossing per TD
630 1.260 skrll */
631 1.260 skrll curlen = len;
632 1.267 skrll if (sphyspg != ephyspg &&
633 1.268 skrll sphyspg + OHCI_PAGE_SIZE != ephyspg) {
634 1.48 augustss /* must use multiple TDs, fill as much as possible. */
635 1.120 augustss curlen = 2 * OHCI_PAGE_SIZE -
636 1.269 skrll OHCI_PAGE_OFFSET(sdataphys);
637 1.78 augustss /* the length must be a multiple of the max size */
638 1.260 skrll curlen -= curlen % mps;
639 1.271 skrll edataphys = DMAADDR(dma, curoffs + curlen - 1);
640 1.48 augustss }
641 1.260 skrll KASSERT(curlen != 0);
642 1.274 pgoyette DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx "
643 1.274 pgoyette "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen);
644 1.48 augustss
645 1.77 augustss cur->td.td_flags = tdflags;
646 1.260 skrll cur->td.td_cbp = HTOO32(sdataphys);
647 1.260 skrll cur->td.td_be = HTOO32(edataphys);
648 1.260 skrll cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0;
649 1.48 augustss cur->nexttd = next;
650 1.48 augustss cur->len = curlen;
651 1.48 augustss cur->flags = OHCI_ADD_LEN;
652 1.77 augustss cur->xfer = xfer;
653 1.260 skrll ohci_hash_add_td(sc, cur);
654 1.260 skrll
655 1.260 skrll curoffs += curlen;
656 1.260 skrll len -= curlen;
657 1.260 skrll
658 1.260 skrll if (len != 0) {
659 1.260 skrll KASSERT(next != NULL);
660 1.260 skrll DPRINTFN(10, "extend chain", 0, 0, 0, 0);
661 1.272 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
662 1.272 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
663 1.272 skrll
664 1.260 skrll cur = next;
665 1.260 skrll }
666 1.48 augustss }
667 1.260 skrll cur->td.td_flags |=
668 1.262 skrll HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0);
669 1.260 skrll
670 1.260 skrll if (!rd &&
671 1.260 skrll (flags & USBD_FORCE_SHORT_XFER) &&
672 1.260 skrll alen % mps == 0) {
673 1.272 skrll /* We're adding a ZLP so sync the previous TD */
674 1.272 skrll usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td),
675 1.272 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
676 1.272 skrll
677 1.61 augustss /* Force a 0 length transfer at the end. */
678 1.75 augustss
679 1.260 skrll KASSERT(next != NULL);
680 1.75 augustss cur = next;
681 1.61 augustss
682 1.77 augustss cur->td.td_flags = tdflags;
683 1.61 augustss cur->td.td_cbp = 0; /* indicate 0 length packet */
684 1.260 skrll cur->td.td_nexttd = 0;
685 1.75 augustss cur->td.td_be = ~0;
686 1.260 skrll cur->nexttd = NULL;
687 1.61 augustss cur->len = 0;
688 1.61 augustss cur->flags = 0;
689 1.77 augustss cur->xfer = xfer;
690 1.260 skrll ohci_hash_add_td(sc, cur);
691 1.260 skrll
692 1.260 skrll DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0);
693 1.61 augustss }
694 1.272 skrll
695 1.272 skrll /* Last TD gets usb_syncmem'ed by caller */
696 1.77 augustss *ep = cur;
697 1.48 augustss }
698 1.48 augustss
699 1.60 augustss ohci_soft_itd_t *
700 1.91 augustss ohci_alloc_sitd(ohci_softc_t *sc)
701 1.60 augustss {
702 1.60 augustss ohci_soft_itd_t *sitd;
703 1.60 augustss usbd_status err;
704 1.224 mrg int i, offs;
705 1.60 augustss usb_dma_t dma;
706 1.60 augustss
707 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
708 1.260 skrll
709 1.260 skrll mutex_enter(&sc->sc_lock);
710 1.60 augustss if (sc->sc_freeitds == NULL) {
711 1.260 skrll DPRINTFN(2, "allocating chunk", 0, 0, 0, 0);
712 1.260 skrll mutex_exit(&sc->sc_lock);
713 1.260 skrll
714 1.83 augustss err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK,
715 1.83 augustss OHCI_ITD_ALIGN, &dma);
716 1.60 augustss if (err)
717 1.260 skrll return NULL;
718 1.260 skrll mutex_enter(&sc->sc_lock);
719 1.259 skrll for (i = 0; i < OHCI_SITD_CHUNK; i++) {
720 1.83 augustss offs = i * OHCI_SITD_SIZE;
721 1.123 augustss sitd = KERNADDR(&dma, offs);
722 1.125 augustss sitd->physaddr = DMAADDR(&dma, offs);
723 1.195 bouyer sitd->dma = dma;
724 1.195 bouyer sitd->offs = offs;
725 1.60 augustss sitd->nextitd = sc->sc_freeitds;
726 1.60 augustss sc->sc_freeitds = sitd;
727 1.60 augustss }
728 1.60 augustss }
729 1.83 augustss
730 1.60 augustss sitd = sc->sc_freeitds;
731 1.60 augustss sc->sc_freeitds = sitd->nextitd;
732 1.260 skrll mutex_exit(&sc->sc_lock);
733 1.260 skrll
734 1.60 augustss memset(&sitd->itd, 0, sizeof(ohci_itd_t));
735 1.83 augustss sitd->nextitd = NULL;
736 1.83 augustss sitd->xfer = NULL;
737 1.83 augustss
738 1.83 augustss #ifdef DIAGNOSTIC
739 1.260 skrll sitd->isdone = true;
740 1.83 augustss #endif
741 1.83 augustss
742 1.260 skrll return sitd;
743 1.60 augustss }
744 1.60 augustss
745 1.260 skrll Static void
746 1.260 skrll ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
747 1.60 augustss {
748 1.83 augustss
749 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
750 1.274 pgoyette DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0);
751 1.83 augustss
752 1.260 skrll KASSERT(sitd->isdone);
753 1.83 augustss #ifdef DIAGNOSTIC
754 1.134 toshii /* Warn double free */
755 1.260 skrll sitd->isdone = false;
756 1.83 augustss #endif
757 1.83 augustss
758 1.60 augustss sitd->nextitd = sc->sc_freeitds;
759 1.60 augustss sc->sc_freeitds = sitd;
760 1.60 augustss }
761 1.60 augustss
762 1.260 skrll void
763 1.260 skrll ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
764 1.260 skrll {
765 1.260 skrll
766 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
767 1.260 skrll
768 1.260 skrll mutex_enter(&sc->sc_lock);
769 1.260 skrll ohci_free_sitd_locked(sc, sitd);
770 1.260 skrll mutex_exit(&sc->sc_lock);
771 1.260 skrll }
772 1.260 skrll
773 1.260 skrll int
774 1.91 augustss ohci_init(ohci_softc_t *sc)
775 1.1 augustss {
776 1.1 augustss ohci_soft_ed_t *sed, *psed;
777 1.53 augustss usbd_status err;
778 1.1 augustss int i;
779 1.260 skrll uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */;
780 1.260 skrll
781 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
782 1.16 augustss
783 1.199 jmcneill aprint_normal_dev(sc->sc_dev, "");
784 1.199 jmcneill
785 1.198 cegger sc->sc_hcca = NULL;
786 1.224 mrg callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE);
787 1.224 mrg
788 1.224 mrg mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB);
789 1.256 skrll mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB);
790 1.224 mrg
791 1.264 skrll sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE,
792 1.224 mrg ohci_rhsc_softint, sc);
793 1.198 cegger
794 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
795 1.198 cegger LIST_INIT(&sc->sc_hash_tds[i]);
796 1.198 cegger for (i = 0; i < OHCI_HASH_SIZE; i++)
797 1.198 cegger LIST_INIT(&sc->sc_hash_itds[i]);
798 1.198 cegger
799 1.232 christos sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0,
800 1.232 christos "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL);
801 1.198 cegger
802 1.56 augustss rev = OREAD4(sc, OHCI_REVISION);
803 1.200 enami aprint_normal("OHCI version %d.%d%s\n",
804 1.199 jmcneill OHCI_REV_HI(rev), OHCI_REV_LO(rev),
805 1.199 jmcneill OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
806 1.55 augustss
807 1.1 augustss if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
808 1.199 jmcneill aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n");
809 1.260 skrll sc->sc_bus.ub_revision = USBREV_UNKNOWN;
810 1.260 skrll return -1;
811 1.1 augustss }
812 1.260 skrll sc->sc_bus.ub_revision = USBREV_1_0;
813 1.260 skrll sc->sc_bus.ub_usedma = true;
814 1.153 fvdl
815 1.73 augustss /* XXX determine alignment by R/W */
816 1.1 augustss /* Allocate the HCCA area. */
817 1.120 augustss err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE,
818 1.4 augustss OHCI_HCCA_ALIGN, &sc->sc_hccadma);
819 1.198 cegger if (err) {
820 1.198 cegger sc->sc_hcca = NULL;
821 1.198 cegger return err;
822 1.198 cegger }
823 1.123 augustss sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0);
824 1.1 augustss memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
825 1.1 augustss
826 1.1 augustss sc->sc_eintrs = OHCI_NORMAL_INTRS;
827 1.1 augustss
828 1.60 augustss /* Allocate dummy ED that starts the control list. */
829 1.1 augustss sc->sc_ctrl_head = ohci_alloc_sed(sc);
830 1.53 augustss if (sc->sc_ctrl_head == NULL) {
831 1.260 skrll err = ENOMEM;
832 1.1 augustss goto bad1;
833 1.1 augustss }
834 1.168 augustss sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
835 1.34 augustss
836 1.60 augustss /* Allocate dummy ED that starts the bulk list. */
837 1.1 augustss sc->sc_bulk_head = ohci_alloc_sed(sc);
838 1.53 augustss if (sc->sc_bulk_head == NULL) {
839 1.260 skrll err = ENOMEM;
840 1.1 augustss goto bad2;
841 1.1 augustss }
842 1.168 augustss sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
843 1.195 bouyer usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs,
844 1.195 bouyer sizeof(sc->sc_bulk_head->ed),
845 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
846 1.1 augustss
847 1.60 augustss /* Allocate dummy ED that starts the isochronous list. */
848 1.60 augustss sc->sc_isoc_head = ohci_alloc_sed(sc);
849 1.60 augustss if (sc->sc_isoc_head == NULL) {
850 1.260 skrll err = ENOMEM;
851 1.60 augustss goto bad3;
852 1.60 augustss }
853 1.168 augustss sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
854 1.195 bouyer usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs,
855 1.195 bouyer sizeof(sc->sc_isoc_head->ed),
856 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
857 1.60 augustss
858 1.1 augustss /* Allocate all the dummy EDs that make up the interrupt tree. */
859 1.1 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
860 1.1 augustss sed = ohci_alloc_sed(sc);
861 1.53 augustss if (sed == NULL) {
862 1.1 augustss while (--i >= 0)
863 1.1 augustss ohci_free_sed(sc, sc->sc_eds[i]);
864 1.260 skrll err = ENOMEM;
865 1.60 augustss goto bad4;
866 1.1 augustss }
867 1.1 augustss /* All ED fields are set to 0. */
868 1.1 augustss sc->sc_eds[i] = sed;
869 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
870 1.60 augustss if (i != 0)
871 1.1 augustss psed = sc->sc_eds[(i-1) / 2];
872 1.60 augustss else
873 1.60 augustss psed= sc->sc_isoc_head;
874 1.60 augustss sed->next = psed;
875 1.168 augustss sed->ed.ed_nexted = HTOO32(psed->physaddr);
876 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
877 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
878 1.1 augustss }
879 1.120 augustss /*
880 1.1 augustss * Fill HCCA interrupt table. The bit reversal is to get
881 1.1 augustss * the tree set up properly to spread the interrupts.
882 1.1 augustss */
883 1.1 augustss for (i = 0; i < OHCI_NO_INTRS; i++)
884 1.120 augustss sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
885 1.168 augustss HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
886 1.195 bouyer usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE,
887 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
888 1.1 augustss
889 1.73 augustss #ifdef OHCI_DEBUG
890 1.260 skrll DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0);
891 1.260 skrll if (ohcidebug >= 15) {
892 1.73 augustss for (i = 0; i < OHCI_NO_EDS; i++) {
893 1.274 pgoyette DPRINTFN(15, "ed#%jd ", i, 0, 0, 0);
894 1.168 augustss ohci_dump_ed(sc, sc->sc_eds[i]);
895 1.73 augustss }
896 1.260 skrll DPRINTFN(15, "iso", 0, 0, 0 ,0);
897 1.168 augustss ohci_dump_ed(sc, sc->sc_isoc_head);
898 1.73 augustss }
899 1.260 skrll DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0);
900 1.73 augustss #endif
901 1.73 augustss
902 1.161 augustss /* Preserve values programmed by SMM/BIOS but lost over reset. */
903 1.161 augustss ctl = OREAD4(sc, OHCI_CONTROL);
904 1.161 augustss rwc = ctl & OHCI_RWC;
905 1.161 augustss fm = OREAD4(sc, OHCI_FM_INTERVAL);
906 1.161 augustss desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
907 1.243 martin /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */
908 1.161 augustss
909 1.1 augustss /* Determine in what context we are running. */
910 1.1 augustss if (ctl & OHCI_IR) {
911 1.1 augustss /* SMM active, request change */
912 1.260 skrll DPRINTF("SMM active, request owner change", 0, 0, 0, 0);
913 1.160 augustss if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) ==
914 1.160 augustss (OHCI_OC | OHCI_MIE))
915 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE);
916 1.1 augustss s = OREAD4(sc, OHCI_COMMAND_STATUS);
917 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
918 1.1 augustss for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
919 1.53 augustss usb_delay_ms(&sc->sc_bus, 1);
920 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
921 1.1 augustss }
922 1.160 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE);
923 1.1 augustss if ((ctl & OHCI_IR) == 0) {
924 1.199 jmcneill aprint_error_dev(sc->sc_dev,
925 1.199 jmcneill "SMM does not respond, resetting\n");
926 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
927 1.1 augustss goto reset;
928 1.1 augustss }
929 1.103 augustss #if 0
930 1.103 augustss /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */
931 1.1 augustss } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
932 1.1 augustss /* BIOS started controller. */
933 1.260 skrll DPRINTF("BIOS active", 0, 0, 0, 0);
934 1.1 augustss if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
935 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc);
936 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
937 1.1 augustss }
938 1.103 augustss #endif
939 1.1 augustss } else {
940 1.260 skrll DPRINTF("cold started", 0 ,0 ,0 ,0);
941 1.1 augustss reset:
942 1.1 augustss /* Controller was cold started. */
943 1.53 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
944 1.1 augustss }
945 1.1 augustss
946 1.16 augustss /*
947 1.25 augustss * This reset should not be necessary according to the OHCI spec, but
948 1.25 augustss * without it some controllers do not start.
949 1.16 augustss */
950 1.274 pgoyette DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0);
951 1.161 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc);
952 1.55 augustss usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY);
953 1.16 augustss
954 1.1 augustss /* We now own the host controller and the bus has been reset. */
955 1.1 augustss
956 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
957 1.1 augustss /* Nominal time for a reset is 10 us. */
958 1.1 augustss for (i = 0; i < 10; i++) {
959 1.1 augustss delay(10);
960 1.1 augustss hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
961 1.1 augustss if (!hcr)
962 1.1 augustss break;
963 1.1 augustss }
964 1.1 augustss if (hcr) {
965 1.199 jmcneill aprint_error_dev(sc->sc_dev, "reset timeout\n");
966 1.260 skrll err = EIO;
967 1.60 augustss goto bad5;
968 1.1 augustss }
969 1.52 augustss #ifdef OHCI_DEBUG
970 1.260 skrll if (ohcidebug >= 15)
971 1.1 augustss ohci_dumpregs(sc);
972 1.1 augustss #endif
973 1.1 augustss
974 1.60 augustss /* The controller is now in SUSPEND state, we have 2ms to finish. */
975 1.1 augustss
976 1.1 augustss /* Set up HC registers. */
977 1.125 augustss OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
978 1.1 augustss OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
979 1.1 augustss OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
980 1.55 augustss /* disable all interrupts and then switch on all desired interrupts */
981 1.1 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
982 1.55 augustss /* switch on desired functional features */
983 1.1 augustss ctl = OREAD4(sc, OHCI_CONTROL);
984 1.1 augustss ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
985 1.1 augustss ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
986 1.161 augustss OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc;
987 1.1 augustss /* And finally start it! */
988 1.1 augustss OWRITE4(sc, OHCI_CONTROL, ctl);
989 1.1 augustss
990 1.1 augustss /*
991 1.1 augustss * The controller is now OPERATIONAL. Set a some final
992 1.1 augustss * registers that should be set earlier, but that the
993 1.1 augustss * controller ignores when in the SUSPEND state.
994 1.1 augustss */
995 1.161 augustss ival = OHCI_GET_IVAL(fm);
996 1.1 augustss fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
997 1.1 augustss fm |= OHCI_FSMPS(ival) | ival;
998 1.1 augustss OWRITE4(sc, OHCI_FM_INTERVAL, fm);
999 1.1 augustss per = OHCI_PERIODIC(ival); /* 90% periodic */
1000 1.1 augustss OWRITE4(sc, OHCI_PERIODIC_START, per);
1001 1.1 augustss
1002 1.249 skrll if (sc->sc_flags & OHCIF_SUPERIO) {
1003 1.249 skrll /* no overcurrent protection */
1004 1.249 skrll desca |= OHCI_NOCP;
1005 1.249 skrll /*
1006 1.249 skrll * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning
1007 1.249 skrll * that
1008 1.249 skrll * - ports are always power switched
1009 1.249 skrll * - don't wait for powered root hub port
1010 1.249 skrll */
1011 1.249 skrll desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS);
1012 1.249 skrll }
1013 1.249 skrll
1014 1.68 augustss /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */
1015 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP);
1016 1.68 augustss OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
1017 1.85 augustss usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY);
1018 1.68 augustss OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca);
1019 1.1 augustss
1020 1.85 augustss /*
1021 1.85 augustss * The AMD756 requires a delay before re-reading the register,
1022 1.85 augustss * otherwise it will occasionally report 0 ports.
1023 1.85 augustss */
1024 1.145 augustss sc->sc_noport = 0;
1025 1.145 augustss for (i = 0; i < 10 && sc->sc_noport == 0; i++) {
1026 1.145 augustss usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY);
1027 1.145 augustss sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
1028 1.145 augustss }
1029 1.1 augustss
1030 1.52 augustss #ifdef OHCI_DEBUG
1031 1.260 skrll if (ohcidebug >= 5)
1032 1.1 augustss ohci_dumpregs(sc);
1033 1.1 augustss #endif
1034 1.120 augustss
1035 1.1 augustss /* Set up the bus struct. */
1036 1.260 skrll sc->sc_bus.ub_methods = &ohci_bus_methods;
1037 1.260 skrll sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe);
1038 1.1 augustss
1039 1.101 minoura sc->sc_control = sc->sc_intre = 0;
1040 1.59 augustss
1041 1.167 augustss /* Finally, turn on interrupts. */
1042 1.274 pgoyette DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0);
1043 1.167 augustss OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
1044 1.167 augustss
1045 1.260 skrll return 0;
1046 1.1 augustss
1047 1.60 augustss bad5:
1048 1.60 augustss for (i = 0; i < OHCI_NO_EDS; i++)
1049 1.60 augustss ohci_free_sed(sc, sc->sc_eds[i]);
1050 1.60 augustss bad4:
1051 1.60 augustss ohci_free_sed(sc, sc->sc_isoc_head);
1052 1.1 augustss bad3:
1053 1.144 augustss ohci_free_sed(sc, sc->sc_bulk_head);
1054 1.144 augustss bad2:
1055 1.1 augustss ohci_free_sed(sc, sc->sc_ctrl_head);
1056 1.1 augustss bad1:
1057 1.44 augustss usb_freemem(&sc->sc_bus, &sc->sc_hccadma);
1058 1.198 cegger sc->sc_hcca = NULL;
1059 1.260 skrll return err;
1060 1.62 augustss }
1061 1.62 augustss
1062 1.260 skrll struct usbd_xfer *
1063 1.260 skrll ohci_allocx(struct usbd_bus *bus, unsigned int nframes)
1064 1.62 augustss {
1065 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1066 1.260 skrll struct usbd_xfer *xfer;
1067 1.62 augustss
1068 1.276 skrll xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK);
1069 1.118 augustss if (xfer != NULL) {
1070 1.232 christos memset(xfer, 0, sizeof(struct ohci_xfer));
1071 1.282 mrg
1072 1.118 augustss #ifdef DIAGNOSTIC
1073 1.260 skrll xfer->ux_state = XFER_BUSY;
1074 1.118 augustss #endif
1075 1.118 augustss }
1076 1.260 skrll return xfer;
1077 1.62 augustss }
1078 1.62 augustss
1079 1.62 augustss void
1080 1.260 skrll ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer)
1081 1.62 augustss {
1082 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1083 1.62 augustss
1084 1.288 rin KASSERTMSG(xfer->ux_state == XFER_BUSY ||
1085 1.288 rin xfer->ux_status == USBD_NOT_STARTED,
1086 1.260 skrll "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state);
1087 1.118 augustss #ifdef DIAGNOSTIC
1088 1.260 skrll xfer->ux_state = XFER_FREE;
1089 1.118 augustss #endif
1090 1.232 christos pool_cache_put(sc->sc_xferpool, xfer);
1091 1.42 augustss }
1092 1.42 augustss
1093 1.293 riastrad Static bool
1094 1.293 riastrad ohci_dying(struct usbd_bus *bus)
1095 1.293 riastrad {
1096 1.293 riastrad ohci_softc_t *sc = OHCI_BUS2SC(bus);
1097 1.293 riastrad
1098 1.293 riastrad return sc->sc_dying;
1099 1.293 riastrad }
1100 1.293 riastrad
1101 1.224 mrg Static void
1102 1.224 mrg ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock)
1103 1.224 mrg {
1104 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1105 1.224 mrg
1106 1.224 mrg *lock = &sc->sc_lock;
1107 1.224 mrg }
1108 1.224 mrg
1109 1.59 augustss /*
1110 1.59 augustss * Shut down the controller when the system is going down.
1111 1.59 augustss */
1112 1.188 dyoung bool
1113 1.188 dyoung ohci_shutdown(device_t self, int flags)
1114 1.59 augustss {
1115 1.188 dyoung ohci_softc_t *sc = device_private(self);
1116 1.59 augustss
1117 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1118 1.260 skrll
1119 1.260 skrll DPRINTF("stopping the HC", 0, 0, 0, 0);
1120 1.277 msaitoh OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
1121 1.59 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1122 1.188 dyoung return true;
1123 1.59 augustss }
1124 1.59 augustss
1125 1.185 jmcneill bool
1126 1.206 dyoung ohci_resume(device_t dv, const pmf_qual_t *qual)
1127 1.33 augustss {
1128 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1129 1.185 jmcneill uint32_t ctl;
1130 1.33 augustss
1131 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1132 1.260 skrll sc->sc_bus.ub_usepolling++;
1133 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1134 1.224 mrg
1135 1.185 jmcneill /* Some broken BIOSes do not recover these values */
1136 1.185 jmcneill OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0));
1137 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL_HEAD_ED,
1138 1.185 jmcneill sc->sc_ctrl_head->physaddr);
1139 1.185 jmcneill OWRITE4(sc, OHCI_BULK_HEAD_ED,
1140 1.185 jmcneill sc->sc_bulk_head->physaddr);
1141 1.185 jmcneill if (sc->sc_intre)
1142 1.185 jmcneill OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre &
1143 1.185 jmcneill (OHCI_ALL_INTRS | OHCI_MIE));
1144 1.185 jmcneill if (sc->sc_control)
1145 1.185 jmcneill ctl = sc->sc_control;
1146 1.185 jmcneill else
1147 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL);
1148 1.185 jmcneill ctl |= OHCI_HCFS_RESUME;
1149 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1150 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
1151 1.185 jmcneill ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL;
1152 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1153 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
1154 1.185 jmcneill sc->sc_control = sc->sc_intre = 0;
1155 1.224 mrg
1156 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1157 1.260 skrll sc->sc_bus.ub_usepolling--;
1158 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1159 1.185 jmcneill
1160 1.185 jmcneill return true;
1161 1.185 jmcneill }
1162 1.185 jmcneill
1163 1.185 jmcneill bool
1164 1.206 dyoung ohci_suspend(device_t dv, const pmf_qual_t *qual)
1165 1.185 jmcneill {
1166 1.185 jmcneill ohci_softc_t *sc = device_private(dv);
1167 1.185 jmcneill uint32_t ctl;
1168 1.95 augustss
1169 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1170 1.260 skrll sc->sc_bus.ub_usepolling++;
1171 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1172 1.224 mrg
1173 1.185 jmcneill ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK;
1174 1.185 jmcneill if (sc->sc_control == 0) {
1175 1.185 jmcneill /*
1176 1.185 jmcneill * Preserve register values, in case that BIOS
1177 1.185 jmcneill * does not recover them.
1178 1.185 jmcneill */
1179 1.185 jmcneill sc->sc_control = ctl;
1180 1.185 jmcneill sc->sc_intre = OREAD4(sc,
1181 1.185 jmcneill OHCI_INTERRUPT_ENABLE);
1182 1.95 augustss }
1183 1.185 jmcneill ctl |= OHCI_HCFS_SUSPEND;
1184 1.185 jmcneill OWRITE4(sc, OHCI_CONTROL, ctl);
1185 1.185 jmcneill usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1186 1.224 mrg
1187 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1188 1.260 skrll sc->sc_bus.ub_usepolling--;
1189 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1190 1.185 jmcneill
1191 1.185 jmcneill return true;
1192 1.33 augustss }
1193 1.33 augustss
1194 1.52 augustss #ifdef OHCI_DEBUG
1195 1.1 augustss void
1196 1.91 augustss ohci_dumpregs(ohci_softc_t *sc)
1197 1.1 augustss {
1198 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1199 1.260 skrll
1200 1.274 pgoyette DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx",
1201 1.41 augustss OREAD4(sc, OHCI_REVISION),
1202 1.41 augustss OREAD4(sc, OHCI_CONTROL),
1203 1.260 skrll OREAD4(sc, OHCI_COMMAND_STATUS), 0);
1204 1.274 pgoyette DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx",
1205 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_STATUS),
1206 1.41 augustss OREAD4(sc, OHCI_INTERRUPT_ENABLE),
1207 1.260 skrll OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0);
1208 1.274 pgoyette DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx",
1209 1.41 augustss OREAD4(sc, OHCI_HCCA),
1210 1.41 augustss OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
1211 1.260 skrll OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0);
1212 1.274 pgoyette DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx",
1213 1.41 augustss OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
1214 1.41 augustss OREAD4(sc, OHCI_BULK_HEAD_ED),
1215 1.260 skrll OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0);
1216 1.274 pgoyette DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx",
1217 1.41 augustss OREAD4(sc, OHCI_DONE_HEAD),
1218 1.41 augustss OREAD4(sc, OHCI_FM_INTERVAL),
1219 1.260 skrll OREAD4(sc, OHCI_FM_REMAINING), 0);
1220 1.274 pgoyette DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx",
1221 1.41 augustss OREAD4(sc, OHCI_FM_NUMBER),
1222 1.41 augustss OREAD4(sc, OHCI_PERIODIC_START),
1223 1.260 skrll OREAD4(sc, OHCI_LS_THRESHOLD), 0);
1224 1.274 pgoyette DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx",
1225 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
1226 1.41 augustss OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
1227 1.260 skrll OREAD4(sc, OHCI_RH_STATUS), 0);
1228 1.274 pgoyette DPRINTF(" port1=0x%08jx port2=0x%08jx",
1229 1.41 augustss OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
1230 1.260 skrll OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0);
1231 1.274 pgoyette DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx",
1232 1.168 augustss O32TOH(sc->sc_hcca->hcca_frame_number),
1233 1.260 skrll O32TOH(sc->sc_hcca->hcca_done_head), 0, 0);
1234 1.1 augustss }
1235 1.1 augustss #endif
1236 1.1 augustss
1237 1.91 augustss Static int ohci_intr1(ohci_softc_t *);
1238 1.53 augustss
1239 1.1 augustss int
1240 1.91 augustss ohci_intr(void *p)
1241 1.1 augustss {
1242 1.1 augustss ohci_softc_t *sc = p;
1243 1.224 mrg int ret = 0;
1244 1.111 augustss
1245 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1246 1.260 skrll
1247 1.224 mrg if (sc == NULL)
1248 1.260 skrll return 0;
1249 1.53 augustss
1250 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1251 1.224 mrg
1252 1.224 mrg if (sc->sc_dying || !device_has_power(sc->sc_dev))
1253 1.224 mrg goto done;
1254 1.224 mrg
1255 1.53 augustss /* If we get an interrupt while polling, then just ignore it. */
1256 1.260 skrll if (sc->sc_bus.ub_usepolling) {
1257 1.260 skrll DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0);
1258 1.154 joff /* for level triggered intrs, should do something to ack */
1259 1.155 perry OWRITE4(sc, OHCI_INTERRUPT_STATUS,
1260 1.154 joff OREAD4(sc, OHCI_INTERRUPT_STATUS));
1261 1.155 perry
1262 1.224 mrg goto done;
1263 1.57 augustss }
1264 1.53 augustss
1265 1.224 mrg ret = ohci_intr1(sc);
1266 1.224 mrg
1267 1.224 mrg done:
1268 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1269 1.224 mrg return ret;
1270 1.53 augustss }
1271 1.53 augustss
1272 1.82 augustss Static int
1273 1.91 augustss ohci_intr1(ohci_softc_t *sc)
1274 1.53 augustss {
1275 1.260 skrll uint32_t intrs, eintrs;
1276 1.1 augustss
1277 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1278 1.105 augustss
1279 1.15 augustss /* In case the interrupt occurs before initialization has completed. */
1280 1.34 augustss if (sc == NULL || sc->sc_hcca == NULL) {
1281 1.15 augustss #ifdef DIAGNOSTIC
1282 1.15 augustss printf("ohci_intr: sc->sc_hcca == NULL\n");
1283 1.15 augustss #endif
1284 1.260 skrll return 0;
1285 1.15 augustss }
1286 1.15 augustss
1287 1.224 mrg KASSERT(mutex_owned(&sc->sc_intr_lock));
1288 1.224 mrg
1289 1.157 mycroft intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1290 1.1 augustss if (!intrs)
1291 1.260 skrll return 0;
1292 1.55 augustss
1293 1.260 skrll /* Acknowledge */
1294 1.260 skrll OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH));
1295 1.1 augustss eintrs = intrs & sc->sc_eintrs;
1296 1.274 pgoyette DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1297 1.274 pgoyette DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)",
1298 1.260 skrll intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs,
1299 1.260 skrll sc->sc_eintrs);
1300 1.211 matt
1301 1.211 matt if (!eintrs) {
1302 1.260 skrll return 0;
1303 1.211 matt }
1304 1.1 augustss
1305 1.1 augustss if (eintrs & OHCI_SO) {
1306 1.100 augustss sc->sc_overrun_cnt++;
1307 1.100 augustss if (usbd_ratecheck(&sc->sc_overrun_ntc)) {
1308 1.100 augustss printf("%s: %u scheduling overruns\n",
1309 1.190 drochner device_xname(sc->sc_dev), sc->sc_overrun_cnt);
1310 1.100 augustss sc->sc_overrun_cnt = 0;
1311 1.100 augustss }
1312 1.1 augustss /* XXX do what */
1313 1.106 augustss eintrs &= ~OHCI_SO;
1314 1.1 augustss }
1315 1.1 augustss if (eintrs & OHCI_WDH) {
1316 1.157 mycroft /*
1317 1.157 mycroft * We block the interrupt below, and reenable it later from
1318 1.157 mycroft * ohci_softintr().
1319 1.157 mycroft */
1320 1.72 augustss usb_schedsoftintr(&sc->sc_bus);
1321 1.1 augustss }
1322 1.1 augustss if (eintrs & OHCI_RD) {
1323 1.275 skrll DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1324 1.190 drochner printf("%s: resume detect\n", device_xname(sc->sc_dev));
1325 1.1 augustss /* XXX process resume detect */
1326 1.1 augustss }
1327 1.1 augustss if (eintrs & OHCI_UE) {
1328 1.275 skrll DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0);
1329 1.15 augustss printf("%s: unrecoverable error, controller halted\n",
1330 1.190 drochner device_xname(sc->sc_dev));
1331 1.1 augustss OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
1332 1.1 augustss /* XXX what else */
1333 1.1 augustss }
1334 1.1 augustss if (eintrs & OHCI_RHSC) {
1335 1.120 augustss /*
1336 1.157 mycroft * We block the interrupt below, and reenable it later from
1337 1.157 mycroft * a timeout.
1338 1.1 augustss */
1339 1.224 mrg softint_schedule(sc->sc_rhsc_si);
1340 1.1 augustss }
1341 1.1 augustss
1342 1.106 augustss if (eintrs != 0) {
1343 1.157 mycroft /* Block unprocessed interrupts. */
1344 1.106 augustss OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs);
1345 1.106 augustss sc->sc_eintrs &= ~eintrs;
1346 1.274 pgoyette DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc,
1347 1.274 pgoyette eintrs, 0, 0);
1348 1.106 augustss }
1349 1.1 augustss
1350 1.260 skrll return 1;
1351 1.1 augustss }
1352 1.1 augustss
1353 1.1 augustss void
1354 1.104 augustss ohci_rhsc_enable(void *v_sc)
1355 1.104 augustss {
1356 1.104 augustss ohci_softc_t *sc = v_sc;
1357 1.104 augustss
1358 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1359 1.274 pgoyette DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0);
1360 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1361 1.157 mycroft sc->sc_eintrs |= OHCI_RHSC;
1362 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
1363 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1364 1.1 augustss }
1365 1.1 augustss
1366 1.52 augustss #ifdef OHCI_DEBUG
1367 1.166 drochner const char *ohci_cc_strs[] = {
1368 1.13 augustss "NO_ERROR",
1369 1.13 augustss "CRC",
1370 1.13 augustss "BIT_STUFFING",
1371 1.13 augustss "DATA_TOGGLE_MISMATCH",
1372 1.13 augustss "STALL",
1373 1.13 augustss "DEVICE_NOT_RESPONDING",
1374 1.13 augustss "PID_CHECK_FAILURE",
1375 1.13 augustss "UNEXPECTED_PID",
1376 1.13 augustss "DATA_OVERRUN",
1377 1.13 augustss "DATA_UNDERRUN",
1378 1.13 augustss "BUFFER_OVERRUN",
1379 1.13 augustss "BUFFER_UNDERRUN",
1380 1.67 augustss "reserved",
1381 1.67 augustss "reserved",
1382 1.67 augustss "NOT_ACCESSED",
1383 1.13 augustss "NOT_ACCESSED",
1384 1.13 augustss };
1385 1.13 augustss #endif
1386 1.13 augustss
1387 1.1 augustss void
1388 1.157 mycroft ohci_softintr(void *v)
1389 1.83 augustss {
1390 1.190 drochner struct usbd_bus *bus = v;
1391 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1392 1.157 mycroft ohci_soft_itd_t *sitd, *sidone, *sitdnext;
1393 1.157 mycroft ohci_soft_td_t *std, *sdone, *stdnext;
1394 1.260 skrll struct usbd_xfer *xfer;
1395 1.157 mycroft struct ohci_pipe *opipe;
1396 1.224 mrg int len, cc;
1397 1.157 mycroft int i, j, actlen, iframes, uedir;
1398 1.157 mycroft ohci_physaddr_t done;
1399 1.157 mycroft
1400 1.286 mrg KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1401 1.224 mrg
1402 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1403 1.157 mycroft
1404 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1405 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1406 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1407 1.168 augustss done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS;
1408 1.157 mycroft sc->sc_hcca->hcca_done_head = 0;
1409 1.195 bouyer usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head),
1410 1.195 bouyer sizeof(sc->sc_hcca->hcca_done_head),
1411 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1412 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH);
1413 1.157 mycroft sc->sc_eintrs |= OHCI_WDH;
1414 1.157 mycroft OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH);
1415 1.83 augustss
1416 1.83 augustss /* Reverse the done list. */
1417 1.83 augustss for (sdone = NULL, sidone = NULL; done != 0; ) {
1418 1.83 augustss std = ohci_hash_find_td(sc, done);
1419 1.83 augustss if (std != NULL) {
1420 1.195 bouyer usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1421 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1422 1.83 augustss std->dnext = sdone;
1423 1.168 augustss done = O32TOH(std->td.td_nexttd);
1424 1.83 augustss sdone = std;
1425 1.274 pgoyette DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0);
1426 1.83 augustss continue;
1427 1.83 augustss }
1428 1.83 augustss sitd = ohci_hash_find_itd(sc, done);
1429 1.83 augustss if (sitd != NULL) {
1430 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1431 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1432 1.83 augustss sitd->dnext = sidone;
1433 1.168 augustss done = O32TOH(sitd->itd.itd_nextitd);
1434 1.83 augustss sidone = sitd;
1435 1.274 pgoyette DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0);
1436 1.83 augustss continue;
1437 1.83 augustss }
1438 1.274 pgoyette DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0);
1439 1.218 jmcneill device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n",
1440 1.218 jmcneill (u_long)done);
1441 1.218 jmcneill break;
1442 1.83 augustss }
1443 1.83 augustss
1444 1.274 pgoyette DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone,
1445 1.274 pgoyette (uintptr_t)sidone, 0, 0);
1446 1.260 skrll DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0);
1447 1.52 augustss #ifdef OHCI_DEBUG
1448 1.260 skrll if (ohcidebug >= 10) {
1449 1.234 skrll for (std = sdone; std; std = std->dnext)
1450 1.258 skrll ohci_dump_td(sc, std);
1451 1.1 augustss }
1452 1.1 augustss #endif
1453 1.260 skrll DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0);
1454 1.1 augustss
1455 1.48 augustss for (std = sdone; std; std = stdnext) {
1456 1.53 augustss xfer = std->xfer;
1457 1.48 augustss stdnext = std->dnext;
1458 1.274 pgoyette DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std,
1459 1.274 pgoyette (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0),
1460 1.274 pgoyette 0);
1461 1.71 augustss if (xfer == NULL) {
1462 1.117 augustss /*
1463 1.117 augustss * xfer == NULL: There seems to be no xfer associated
1464 1.71 augustss * with this TD. It is tailp that happened to end up on
1465 1.71 augustss * the done queue.
1466 1.117 augustss * Shouldn't happen, but some chips are broken(?).
1467 1.71 augustss */
1468 1.71 augustss continue;
1469 1.71 augustss }
1470 1.282 mrg
1471 1.282 mrg /*
1472 1.293 riastrad * Try to claim this xfer for completion. If it has
1473 1.293 riastrad * already completed or aborted, drop it on the floor.
1474 1.282 mrg */
1475 1.293 riastrad if (!usbd_xfer_trycomplete(xfer))
1476 1.83 augustss continue;
1477 1.141 mycroft
1478 1.141 mycroft len = std->len;
1479 1.141 mycroft if (std->td.td_cbp != 0)
1480 1.168 augustss len -= O32TOH(std->td.td_be) -
1481 1.168 augustss O32TOH(std->td.td_cbp) + 1;
1482 1.274 pgoyette DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0);
1483 1.141 mycroft if (std->flags & OHCI_ADD_LEN)
1484 1.260 skrll xfer->ux_actlen += len;
1485 1.141 mycroft
1486 1.168 augustss cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags));
1487 1.83 augustss if (cc == OHCI_CC_NO_ERROR) {
1488 1.260 skrll ohci_hash_rem_td(sc, std);
1489 1.34 augustss if (std->flags & OHCI_CALL_DONE) {
1490 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1491 1.53 augustss usb_transfer_complete(xfer);
1492 1.21 augustss }
1493 1.1 augustss } else {
1494 1.48 augustss /*
1495 1.48 augustss * Endpoint is halted. First unlink all the TDs
1496 1.48 augustss * belonging to the failed transfer, and then restart
1497 1.48 augustss * the endpoint.
1498 1.48 augustss */
1499 1.1 augustss ohci_soft_td_t *p, *n;
1500 1.260 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1501 1.48 augustss
1502 1.274 pgoyette DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0);
1503 1.48 augustss
1504 1.260 skrll /* remove xfer's TDs from the hash */
1505 1.53 augustss for (p = std; p->xfer == xfer; p = n) {
1506 1.1 augustss n = p->nexttd;
1507 1.260 skrll ohci_hash_rem_td(sc, p);
1508 1.1 augustss }
1509 1.48 augustss
1510 1.260 skrll ohci_soft_ed_t *sed = opipe->sed;
1511 1.260 skrll
1512 1.291 gson /* clear halt and TD chain, preserving toggle carry */
1513 1.291 gson sed->ed.ed_headp = HTOO32(p->physaddr |
1514 1.291 gson (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
1515 1.260 skrll usb_syncmem(&sed->dma,
1516 1.260 skrll sed->offs + offsetof(ohci_ed_t, ed_headp),
1517 1.260 skrll sizeof(sed->ed.ed_headp),
1518 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1519 1.260 skrll
1520 1.1 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1521 1.48 augustss
1522 1.260 skrll if (cc == OHCI_CC_DATA_UNDERRUN)
1523 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1524 1.260 skrll else if (cc == OHCI_CC_STALL)
1525 1.260 skrll xfer->ux_status = USBD_STALLED;
1526 1.1 augustss else
1527 1.260 skrll xfer->ux_status = USBD_IOERROR;
1528 1.53 augustss usb_transfer_complete(xfer);
1529 1.1 augustss }
1530 1.1 augustss }
1531 1.260 skrll DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0);
1532 1.83 augustss #ifdef OHCI_DEBUG
1533 1.260 skrll if (ohcidebug >= 10) {
1534 1.234 skrll for (sitd = sidone; sitd; sitd = sitd->dnext)
1535 1.258 skrll ohci_dump_itd(sc, sitd);
1536 1.83 augustss }
1537 1.83 augustss #endif
1538 1.260 skrll DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0);
1539 1.83 augustss
1540 1.83 augustss for (sitd = sidone; sitd != NULL; sitd = sitdnext) {
1541 1.83 augustss xfer = sitd->xfer;
1542 1.83 augustss sitdnext = sitd->dnext;
1543 1.274 pgoyette DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd,
1544 1.274 pgoyette (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0),
1545 1.274 pgoyette 0);
1546 1.83 augustss if (xfer == NULL)
1547 1.83 augustss continue;
1548 1.282 mrg
1549 1.282 mrg /*
1550 1.293 riastrad * Try to claim this xfer for completion. If it has
1551 1.293 riastrad * already completed or aborted, drop it on the floor.
1552 1.282 mrg */
1553 1.293 riastrad if (!usbd_xfer_trycomplete(xfer))
1554 1.83 augustss continue;
1555 1.282 mrg
1556 1.260 skrll KASSERT(!sitd->isdone);
1557 1.83 augustss #ifdef DIAGNOSTIC
1558 1.260 skrll sitd->isdone = true;
1559 1.83 augustss #endif
1560 1.134 toshii if (sitd->flags & OHCI_CALL_DONE) {
1561 1.134 toshii ohci_soft_itd_t *next;
1562 1.134 toshii
1563 1.260 skrll opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1564 1.260 skrll opipe->isoc.inuse -= xfer->ux_nframes;
1565 1.260 skrll uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->
1566 1.134 toshii bEndpointAddress);
1567 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1568 1.134 toshii actlen = 0;
1569 1.260 skrll for (i = 0, sitd = xfer->ux_hcpriv;;
1570 1.134 toshii sitd = next) {
1571 1.134 toshii next = sitd->nextitd;
1572 1.168 augustss if (OHCI_ITD_GET_CC(O32TOH(sitd->
1573 1.135 toshii itd.itd_flags)) != OHCI_CC_NO_ERROR)
1574 1.260 skrll xfer->ux_status = USBD_IOERROR;
1575 1.134 toshii /* For input, update frlengths with actual */
1576 1.134 toshii /* XXX anything necessary for output? */
1577 1.134 toshii if (uedir == UE_DIR_IN &&
1578 1.260 skrll xfer->ux_status == USBD_NORMAL_COMPLETION) {
1579 1.168 augustss iframes = OHCI_ITD_GET_FC(O32TOH(
1580 1.135 toshii sitd->itd.itd_flags));
1581 1.134 toshii for (j = 0; j < iframes; i++, j++) {
1582 1.168 augustss len = O16TOH(sitd->
1583 1.134 toshii itd.itd_offset[j]);
1584 1.158 toshii if ((OHCI_ITD_PSW_GET_CC(len) &
1585 1.158 toshii OHCI_CC_NOT_ACCESSED_MASK)
1586 1.158 toshii == OHCI_CC_NOT_ACCESSED)
1587 1.158 toshii len = 0;
1588 1.158 toshii else
1589 1.158 toshii len = OHCI_ITD_PSW_LENGTH(len);
1590 1.260 skrll xfer->ux_frlengths[i] = len;
1591 1.134 toshii actlen += len;
1592 1.134 toshii }
1593 1.134 toshii }
1594 1.134 toshii if (sitd->flags & OHCI_CALL_DONE)
1595 1.134 toshii break;
1596 1.260 skrll ohci_hash_rem_itd(sc, sitd);
1597 1.260 skrll
1598 1.83 augustss }
1599 1.260 skrll ohci_hash_rem_itd(sc, sitd);
1600 1.134 toshii if (uedir == UE_DIR_IN &&
1601 1.260 skrll xfer->ux_status == USBD_NORMAL_COMPLETION)
1602 1.260 skrll xfer->ux_actlen = actlen;
1603 1.260 skrll xfer->ux_hcpriv = NULL;
1604 1.134 toshii
1605 1.83 augustss usb_transfer_complete(xfer);
1606 1.83 augustss }
1607 1.83 augustss }
1608 1.83 augustss
1609 1.260 skrll DPRINTFN(10, "done", 0, 0, 0, 0);
1610 1.286 mrg KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1611 1.1 augustss }
1612 1.1 augustss
1613 1.1 augustss void
1614 1.260 skrll ohci_device_ctrl_done(struct usbd_xfer *xfer)
1615 1.1 augustss {
1616 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
1617 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1618 1.260 skrll int len = UGETW(xfer->ux_request.wLength);
1619 1.260 skrll int isread = (xfer->ux_request.bmRequestType & UT_READ);
1620 1.195 bouyer
1621 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1622 1.274 pgoyette DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
1623 1.1 augustss
1624 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1625 1.260 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
1626 1.224 mrg
1627 1.195 bouyer if (len)
1628 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
1629 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1630 1.260 skrll usb_syncmem(&opipe->ctrl.reqdma, 0,
1631 1.260 skrll sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE);
1632 1.1 augustss }
1633 1.1 augustss
1634 1.1 augustss void
1635 1.260 skrll ohci_device_intr_done(struct usbd_xfer *xfer)
1636 1.1 augustss {
1637 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1638 1.195 bouyer int isread =
1639 1.260 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1640 1.1 augustss
1641 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1642 1.274 pgoyette DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer,
1643 1.274 pgoyette xfer->ux_actlen, 0, 0);
1644 1.1 augustss
1645 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1646 1.224 mrg
1647 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1648 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1649 1.1 augustss }
1650 1.1 augustss
1651 1.1 augustss void
1652 1.260 skrll ohci_device_bulk_done(struct usbd_xfer *xfer)
1653 1.3 augustss {
1654 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
1655 1.260 skrll
1656 1.195 bouyer int isread =
1657 1.260 skrll (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN);
1658 1.195 bouyer
1659 1.290 mrg KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1660 1.224 mrg
1661 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1662 1.274 pgoyette DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen,
1663 1.274 pgoyette 0, 0);
1664 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length,
1665 1.195 bouyer isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1666 1.3 augustss }
1667 1.3 augustss
1668 1.224 mrg Static void
1669 1.224 mrg ohci_rhsc_softint(void *arg)
1670 1.224 mrg {
1671 1.224 mrg ohci_softc_t *sc = arg;
1672 1.224 mrg
1673 1.224 mrg mutex_enter(&sc->sc_lock);
1674 1.224 mrg
1675 1.224 mrg ohci_rhsc(sc, sc->sc_intrxfer);
1676 1.224 mrg
1677 1.224 mrg /* Do not allow RHSC interrupts > 1 per second */
1678 1.224 mrg callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc);
1679 1.224 mrg
1680 1.224 mrg mutex_exit(&sc->sc_lock);
1681 1.224 mrg }
1682 1.224 mrg
1683 1.3 augustss void
1684 1.260 skrll ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer)
1685 1.1 augustss {
1686 1.1 augustss u_char *p;
1687 1.1 augustss int i, m;
1688 1.243 martin int hstatus __unused;
1689 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1690 1.1 augustss
1691 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1692 1.224 mrg
1693 1.1 augustss hstatus = OREAD4(sc, OHCI_RH_STATUS);
1694 1.274 pgoyette DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc,
1695 1.274 pgoyette (uintptr_t)xfer, hstatus, 0);
1696 1.1 augustss
1697 1.53 augustss if (xfer == NULL) {
1698 1.1 augustss /* Just ignore the change. */
1699 1.1 augustss return;
1700 1.1 augustss }
1701 1.1 augustss
1702 1.260 skrll p = xfer->ux_buf;
1703 1.285 riastrad m = uimin(sc->sc_noport, xfer->ux_length * 8 - 1);
1704 1.260 skrll memset(p, 0, xfer->ux_length);
1705 1.1 augustss for (i = 1; i <= m; i++) {
1706 1.87 augustss /* Pick out CHANGE bits from the status reg. */
1707 1.1 augustss if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
1708 1.1 augustss p[i/8] |= 1 << (i%8);
1709 1.1 augustss }
1710 1.274 pgoyette DPRINTF("change=0x%02jx", *p, 0, 0, 0);
1711 1.260 skrll xfer->ux_actlen = xfer->ux_length;
1712 1.260 skrll xfer->ux_status = USBD_NORMAL_COMPLETION;
1713 1.1 augustss
1714 1.53 augustss usb_transfer_complete(xfer);
1715 1.38 augustss }
1716 1.38 augustss
1717 1.38 augustss void
1718 1.260 skrll ohci_root_intr_done(struct usbd_xfer *xfer)
1719 1.65 augustss {
1720 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
1721 1.260 skrll
1722 1.260 skrll KASSERT(mutex_owned(&sc->sc_lock));
1723 1.65 augustss
1724 1.260 skrll KASSERT(sc->sc_intrxfer == xfer);
1725 1.260 skrll sc->sc_intrxfer = NULL;
1726 1.1 augustss }
1727 1.1 augustss
1728 1.5 augustss void
1729 1.91 augustss ohci_poll(struct usbd_bus *bus)
1730 1.5 augustss {
1731 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
1732 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1733 1.260 skrll
1734 1.105 augustss #ifdef OHCI_DEBUG
1735 1.105 augustss static int last;
1736 1.105 augustss int new;
1737 1.105 augustss new = OREAD4(sc, OHCI_INTERRUPT_STATUS);
1738 1.105 augustss if (new != last) {
1739 1.274 pgoyette DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0);
1740 1.105 augustss last = new;
1741 1.105 augustss }
1742 1.105 augustss #endif
1743 1.217 jmcneill sc->sc_eintrs |= OHCI_WDH;
1744 1.224 mrg if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) {
1745 1.224 mrg mutex_spin_enter(&sc->sc_intr_lock);
1746 1.53 augustss ohci_intr1(sc);
1747 1.224 mrg mutex_spin_exit(&sc->sc_intr_lock);
1748 1.224 mrg }
1749 1.1 augustss }
1750 1.1 augustss
1751 1.260 skrll /*
1752 1.260 skrll * Add an ED to the schedule. Called with USB lock held.
1753 1.260 skrll */
1754 1.260 skrll Static void
1755 1.260 skrll ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1756 1.1 augustss {
1757 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1758 1.274 pgoyette DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0,
1759 1.274 pgoyette 0);
1760 1.224 mrg
1761 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1762 1.1 augustss
1763 1.260 skrll usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1764 1.260 skrll sizeof(head->ed.ed_nexted),
1765 1.260 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1766 1.260 skrll sed->next = head->next;
1767 1.260 skrll sed->ed.ed_nexted = head->ed.ed_nexted;
1768 1.260 skrll usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1769 1.260 skrll sizeof(sed->ed.ed_nexted),
1770 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1771 1.260 skrll head->next = sed;
1772 1.260 skrll head->ed.ed_nexted = HTOO32(sed->physaddr);
1773 1.260 skrll usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted),
1774 1.260 skrll sizeof(head->ed.ed_nexted),
1775 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1776 1.260 skrll }
1777 1.1 augustss
1778 1.260 skrll /*
1779 1.260 skrll * Remove an ED from the schedule. Called with USB lock held.
1780 1.260 skrll */
1781 1.260 skrll Static void
1782 1.260 skrll ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head)
1783 1.260 skrll {
1784 1.260 skrll ohci_soft_ed_t *p;
1785 1.1 augustss
1786 1.260 skrll KASSERT(mutex_owned(&sc->sc_lock));
1787 1.1 augustss
1788 1.260 skrll /* XXX */
1789 1.260 skrll for (p = head; p != NULL && p->next != sed; p = p->next)
1790 1.3 augustss ;
1791 1.255 skrll KASSERT(p != NULL);
1792 1.255 skrll
1793 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted),
1794 1.195 bouyer sizeof(sed->ed.ed_nexted),
1795 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1796 1.3 augustss p->next = sed->next;
1797 1.39 augustss p->ed.ed_nexted = sed->ed.ed_nexted;
1798 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
1799 1.195 bouyer sizeof(p->ed.ed_nexted),
1800 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1801 1.3 augustss }
1802 1.3 augustss
1803 1.3 augustss /*
1804 1.1 augustss * When a transfer is completed the TD is added to the done queue by
1805 1.1 augustss * the host controller. This queue is the processed by software.
1806 1.1 augustss * Unfortunately the queue contains the physical address of the TD
1807 1.9 augustss * and we have no simple way to translate this back to a kernel address.
1808 1.1 augustss * To make the translation possible (and fast) we use a hash table of
1809 1.1 augustss * TDs currently in the schedule. The physical address is used as the
1810 1.1 augustss * hash value.
1811 1.1 augustss */
1812 1.1 augustss
1813 1.1 augustss #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1814 1.224 mrg /* Called with USB lock held. */
1815 1.1 augustss void
1816 1.91 augustss ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1817 1.1 augustss {
1818 1.1 augustss int h = HASH(std->physaddr);
1819 1.1 augustss
1820 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1821 1.224 mrg
1822 1.1 augustss LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1823 1.1 augustss }
1824 1.1 augustss
1825 1.224 mrg /* Called with USB lock held. */
1826 1.1 augustss void
1827 1.179 christos ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1828 1.1 augustss {
1829 1.46 augustss
1830 1.260 skrll KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock));
1831 1.224 mrg
1832 1.1 augustss LIST_REMOVE(std, hnext);
1833 1.1 augustss }
1834 1.1 augustss
1835 1.1 augustss ohci_soft_td_t *
1836 1.91 augustss ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a)
1837 1.1 augustss {
1838 1.1 augustss int h = HASH(a);
1839 1.1 augustss ohci_soft_td_t *std;
1840 1.1 augustss
1841 1.120 augustss for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1842 1.53 augustss std != NULL;
1843 1.1 augustss std = LIST_NEXT(std, hnext))
1844 1.1 augustss if (std->physaddr == a)
1845 1.260 skrll return std;
1846 1.260 skrll return NULL;
1847 1.83 augustss }
1848 1.83 augustss
1849 1.224 mrg /* Called with USB lock held. */
1850 1.83 augustss void
1851 1.91 augustss ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1852 1.83 augustss {
1853 1.83 augustss int h = HASH(sitd->physaddr);
1854 1.83 augustss
1855 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1856 1.260 skrll
1857 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1858 1.224 mrg
1859 1.274 pgoyette DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx",
1860 1.274 pgoyette (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0);
1861 1.83 augustss
1862 1.83 augustss LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext);
1863 1.83 augustss }
1864 1.83 augustss
1865 1.224 mrg /* Called with USB lock held. */
1866 1.83 augustss void
1867 1.179 christos ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1868 1.83 augustss {
1869 1.83 augustss
1870 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1871 1.260 skrll
1872 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
1873 1.224 mrg
1874 1.274 pgoyette DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd,
1875 1.274 pgoyette sitd->physaddr, 0, 0);
1876 1.83 augustss
1877 1.83 augustss LIST_REMOVE(sitd, hnext);
1878 1.83 augustss }
1879 1.83 augustss
1880 1.83 augustss ohci_soft_itd_t *
1881 1.91 augustss ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a)
1882 1.83 augustss {
1883 1.83 augustss int h = HASH(a);
1884 1.83 augustss ohci_soft_itd_t *sitd;
1885 1.83 augustss
1886 1.120 augustss for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]);
1887 1.83 augustss sitd != NULL;
1888 1.83 augustss sitd = LIST_NEXT(sitd, hnext))
1889 1.83 augustss if (sitd->physaddr == a)
1890 1.260 skrll return sitd;
1891 1.260 skrll return NULL;
1892 1.1 augustss }
1893 1.1 augustss
1894 1.52 augustss #ifdef OHCI_DEBUG
1895 1.1 augustss void
1896 1.168 augustss ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std)
1897 1.1 augustss {
1898 1.260 skrll for (; std; std = std->nexttd) {
1899 1.168 augustss ohci_dump_td(sc, std);
1900 1.260 skrll KASSERTMSG(std->nexttd == NULL || std != std->nexttd,
1901 1.260 skrll "std %p next %p", std, std->nexttd);
1902 1.260 skrll }
1903 1.1 augustss }
1904 1.1 augustss
1905 1.1 augustss void
1906 1.168 augustss ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std)
1907 1.1 augustss {
1908 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1909 1.92 tv
1910 1.204 martin usb_syncmem(&std->dma, std->offs, sizeof(std->td),
1911 1.204 martin BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1912 1.260 skrll
1913 1.260 skrll uint32_t flags = O32TOH(std->td.td_flags);
1914 1.274 pgoyette DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0);
1915 1.274 pgoyette DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx",
1916 1.260 skrll !!(flags & OHCI_TD_R),
1917 1.260 skrll __SHIFTOUT(flags, OHCI_TD_DP_MASK),
1918 1.260 skrll OHCI_TD_GET_DI(flags),
1919 1.260 skrll __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK));
1920 1.274 pgoyette DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags),
1921 1.274 pgoyette OHCI_TD_GET_CC(flags), 0, 0);
1922 1.274 pgoyette DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx",
1923 1.168 augustss (u_long)O32TOH(std->td.td_cbp),
1924 1.168 augustss (u_long)O32TOH(std->td.td_nexttd),
1925 1.260 skrll (u_long)O32TOH(std->td.td_be), 0);
1926 1.1 augustss }
1927 1.1 augustss
1928 1.1 augustss void
1929 1.168 augustss ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1930 1.83 augustss {
1931 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1932 1.83 augustss
1933 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
1934 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1935 1.260 skrll
1936 1.260 skrll uint32_t flags = O32TOH(sitd->itd.itd_flags);
1937 1.274 pgoyette DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0);
1938 1.274 pgoyette DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd",
1939 1.260 skrll OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags),
1940 1.260 skrll OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags));
1941 1.274 pgoyette DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx",
1942 1.260 skrll O32TOH(sitd->itd.itd_bp0),
1943 1.260 skrll O32TOH(sitd->itd.itd_nextitd),
1944 1.260 skrll O32TOH(sitd->itd.itd_be), 0);
1945 1.260 skrll CTASSERT(OHCI_ITD_NOFFSET == 8);
1946 1.274 pgoyette DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx "
1947 1.274 pgoyette "offs[2] = 0x%04jx offs[3] = 0x%04jx",
1948 1.260 skrll O16TOH(sitd->itd.itd_offset[0]),
1949 1.260 skrll O16TOH(sitd->itd.itd_offset[1]),
1950 1.260 skrll O16TOH(sitd->itd.itd_offset[2]),
1951 1.260 skrll O16TOH(sitd->itd.itd_offset[3]));
1952 1.274 pgoyette DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx "
1953 1.274 pgoyette "offs[6] = 0x%04jx offs[7] = 0x%04jx",
1954 1.260 skrll O16TOH(sitd->itd.itd_offset[4]),
1955 1.260 skrll O16TOH(sitd->itd.itd_offset[5]),
1956 1.260 skrll O16TOH(sitd->itd.itd_offset[6]),
1957 1.260 skrll O16TOH(sitd->itd.itd_offset[7]));
1958 1.83 augustss }
1959 1.83 augustss
1960 1.83 augustss void
1961 1.168 augustss ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd)
1962 1.83 augustss {
1963 1.83 augustss for (; sitd; sitd = sitd->nextitd)
1964 1.168 augustss ohci_dump_itd(sc, sitd);
1965 1.83 augustss }
1966 1.83 augustss
1967 1.83 augustss void
1968 1.168 augustss ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed)
1969 1.1 augustss {
1970 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
1971 1.92 tv
1972 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
1973 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
1974 1.260 skrll
1975 1.260 skrll uint32_t flags = O32TOH(sed->ed.ed_flags);
1976 1.274 pgoyette DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0);
1977 1.274 pgoyette DPRINTF(" addr=%jd endpt=%jd maxp=%jd",
1978 1.260 skrll OHCI_ED_GET_FA(flags),
1979 1.260 skrll OHCI_ED_GET_EN(flags),
1980 1.260 skrll OHCI_ED_GET_MAXP(flags),
1981 1.260 skrll 0);
1982 1.274 pgoyette DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd",
1983 1.260 skrll __SHIFTOUT(flags, OHCI_ED_DIR_MASK),
1984 1.260 skrll !!(flags & OHCI_ED_SPEED),
1985 1.260 skrll !!(flags & OHCI_ED_SKIP),
1986 1.260 skrll !!(flags & OHCI_ED_FORMAT_ISO));
1987 1.274 pgoyette DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp),
1988 1.260 skrll 0, 0, 0);
1989 1.274 pgoyette DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd",
1990 1.260 skrll O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted),
1991 1.260 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED),
1992 1.260 skrll !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
1993 1.1 augustss }
1994 1.1 augustss #endif
1995 1.1 augustss
1996 1.1 augustss usbd_status
1997 1.260 skrll ohci_open(struct usbd_pipe *pipe)
1998 1.1 augustss {
1999 1.260 skrll struct usbd_device *dev = pipe->up_dev;
2000 1.260 skrll struct usbd_bus *bus = dev->ud_bus;
2001 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2002 1.260 skrll usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc;
2003 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2004 1.260 skrll uint8_t addr = dev->ud_addr;
2005 1.260 skrll uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
2006 1.1 augustss ohci_soft_ed_t *sed;
2007 1.1 augustss ohci_soft_td_t *std;
2008 1.60 augustss ohci_soft_itd_t *sitd;
2009 1.60 augustss ohci_physaddr_t tdphys;
2010 1.260 skrll uint32_t fmt;
2011 1.224 mrg usbd_status err = USBD_NOMEM;
2012 1.64 augustss int ival;
2013 1.1 augustss
2014 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2015 1.274 pgoyette DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe,
2016 1.274 pgoyette addr, ed->bEndpointAddress, bus->ub_rhaddr);
2017 1.81 augustss
2018 1.224 mrg if (sc->sc_dying) {
2019 1.241 skrll return USBD_IOERROR;
2020 1.224 mrg }
2021 1.116 augustss
2022 1.90 thorpej std = NULL;
2023 1.90 thorpej sed = NULL;
2024 1.90 thorpej
2025 1.260 skrll if (addr == bus->ub_rhaddr) {
2026 1.1 augustss switch (ed->bEndpointAddress) {
2027 1.1 augustss case USB_CONTROL_ENDPOINT:
2028 1.260 skrll pipe->up_methods = &roothub_ctrl_methods;
2029 1.1 augustss break;
2030 1.260 skrll case UE_DIR_IN | USBROOTHUB_INTR_ENDPT:
2031 1.260 skrll pipe->up_methods = &ohci_root_intr_methods;
2032 1.1 augustss break;
2033 1.1 augustss default:
2034 1.224 mrg err = USBD_INVAL;
2035 1.241 skrll goto bad;
2036 1.1 augustss }
2037 1.1 augustss } else {
2038 1.1 augustss sed = ohci_alloc_sed(sc);
2039 1.53 augustss if (sed == NULL)
2040 1.241 skrll goto bad;
2041 1.1 augustss opipe->sed = sed;
2042 1.60 augustss if (xfertype == UE_ISOCHRONOUS) {
2043 1.60 augustss sitd = ohci_alloc_sitd(sc);
2044 1.127 augustss if (sitd == NULL)
2045 1.241 skrll goto bad;
2046 1.241 skrll
2047 1.60 augustss opipe->tail.itd = sitd;
2048 1.76 tsutsui tdphys = sitd->physaddr;
2049 1.60 augustss fmt = OHCI_ED_FORMAT_ISO;
2050 1.83 augustss if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN)
2051 1.83 augustss fmt |= OHCI_ED_DIR_IN;
2052 1.83 augustss else
2053 1.83 augustss fmt |= OHCI_ED_DIR_OUT;
2054 1.60 augustss } else {
2055 1.60 augustss std = ohci_alloc_std(sc);
2056 1.127 augustss if (std == NULL)
2057 1.241 skrll goto bad;
2058 1.241 skrll
2059 1.60 augustss opipe->tail.td = std;
2060 1.76 tsutsui tdphys = std->physaddr;
2061 1.83 augustss fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD;
2062 1.60 augustss }
2063 1.168 augustss sed->ed.ed_flags = HTOO32(
2064 1.120 augustss OHCI_ED_SET_FA(addr) |
2065 1.147 mycroft OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) |
2066 1.260 skrll (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) |
2067 1.109 augustss fmt |
2068 1.16 augustss OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
2069 1.214 jakllsch sed->ed.ed_headp = HTOO32(tdphys |
2070 1.260 skrll (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0));
2071 1.214 jakllsch sed->ed.ed_tailp = HTOO32(tdphys);
2072 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2073 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2074 1.1 augustss
2075 1.60 augustss switch (xfertype) {
2076 1.1 augustss case UE_CONTROL:
2077 1.260 skrll pipe->up_methods = &ohci_device_ctrl_methods;
2078 1.120 augustss err = usb_allocmem(&sc->sc_bus,
2079 1.120 augustss sizeof(usb_device_request_t),
2080 1.260 skrll 0, &opipe->ctrl.reqdma);
2081 1.53 augustss if (err)
2082 1.1 augustss goto bad;
2083 1.224 mrg mutex_enter(&sc->sc_lock);
2084 1.168 augustss ohci_add_ed(sc, sed, sc->sc_ctrl_head);
2085 1.224 mrg mutex_exit(&sc->sc_lock);
2086 1.1 augustss break;
2087 1.1 augustss case UE_INTERRUPT:
2088 1.260 skrll pipe->up_methods = &ohci_device_intr_methods;
2089 1.260 skrll ival = pipe->up_interval;
2090 1.64 augustss if (ival == USBD_DEFAULT_INTERVAL)
2091 1.64 augustss ival = ed->bInterval;
2092 1.226 skrll err = ohci_device_setintr(sc, opipe, ival);
2093 1.226 skrll if (err)
2094 1.226 skrll goto bad;
2095 1.226 skrll break;
2096 1.1 augustss case UE_ISOCHRONOUS:
2097 1.260 skrll pipe->up_serialise = false;
2098 1.260 skrll pipe->up_methods = &ohci_device_isoc_methods;
2099 1.260 skrll return ohci_setup_isoc(pipe);
2100 1.1 augustss case UE_BULK:
2101 1.260 skrll pipe->up_methods = &ohci_device_bulk_methods;
2102 1.224 mrg mutex_enter(&sc->sc_lock);
2103 1.168 augustss ohci_add_ed(sc, sed, sc->sc_bulk_head);
2104 1.224 mrg mutex_exit(&sc->sc_lock);
2105 1.3 augustss break;
2106 1.1 augustss }
2107 1.1 augustss }
2108 1.224 mrg
2109 1.224 mrg return USBD_NORMAL_COMPLETION;
2110 1.1 augustss
2111 1.1 augustss bad:
2112 1.241 skrll if (std != NULL) {
2113 1.90 thorpej ohci_free_std(sc, std);
2114 1.241 skrll }
2115 1.90 thorpej if (sed != NULL)
2116 1.90 thorpej ohci_free_sed(sc, sed);
2117 1.224 mrg return err;
2118 1.120 augustss
2119 1.1 augustss }
2120 1.1 augustss
2121 1.1 augustss /*
2122 1.34 augustss * Close a reqular pipe.
2123 1.34 augustss * Assumes that there are no pending transactions.
2124 1.34 augustss */
2125 1.34 augustss void
2126 1.260 skrll ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head)
2127 1.34 augustss {
2128 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2129 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2130 1.34 augustss ohci_soft_ed_t *sed = opipe->sed;
2131 1.34 augustss
2132 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2133 1.224 mrg
2134 1.34 augustss #ifdef DIAGNOSTIC
2135 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
2136 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2137 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) {
2138 1.34 augustss ohci_soft_td_t *std;
2139 1.168 augustss std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp));
2140 1.34 augustss printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x "
2141 1.34 augustss "tl=0x%x pipe=%p, std=%p\n", sed,
2142 1.168 augustss (int)O32TOH(sed->ed.ed_headp),
2143 1.168 augustss (int)O32TOH(sed->ed.ed_tailp),
2144 1.34 augustss pipe, std);
2145 1.229 christos #ifdef OHCI_DEBUG
2146 1.107 augustss usbd_dump_pipe(&opipe->pipe);
2147 1.168 augustss ohci_dump_ed(sc, sed);
2148 1.106 augustss if (std)
2149 1.168 augustss ohci_dump_td(sc, std);
2150 1.106 augustss #endif
2151 1.34 augustss usb_delay_ms(&sc->sc_bus, 2);
2152 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
2153 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
2154 1.34 augustss printf("ohci_close_pipe: pipe still not empty\n");
2155 1.34 augustss }
2156 1.34 augustss #endif
2157 1.224 mrg ohci_rem_ed(sc, sed, head);
2158 1.133 toshii /* Make sure the host controller is not touching this ED */
2159 1.133 toshii usb_delay_ms(&sc->sc_bus, 1);
2160 1.260 skrll pipe->up_endpoint->ue_toggle =
2161 1.214 jakllsch (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0;
2162 1.260 skrll ohci_free_sed_locked(sc, opipe->sed);
2163 1.34 augustss }
2164 1.34 augustss
2165 1.120 augustss /*
2166 1.293 riastrad * Arrange for the hardware to tells us that it is not still processing
2167 1.293 riastrad * the TDs by setting the sKip bit and requesting a SOF interrupt
2168 1.282 mrg *
2169 1.282 mrg * Once we see the SOF interrupt we can check the transfer TDs/iTDs to see if
2170 1.282 mrg * they've been processed and either
2171 1.282 mrg * a) if they're unused recover them for later use, or
2172 1.282 mrg * b) if they've been used allocate new TD/iTDs to replace those
2173 1.282 mrg * used. The softint handler will free the old ones.
2174 1.34 augustss */
2175 1.34 augustss void
2176 1.293 riastrad ohci_abortx(struct usbd_xfer *xfer)
2177 1.34 augustss {
2178 1.282 mrg OHCIHIST_FUNC(); OHCIHIST_CALLED();
2179 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2180 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2181 1.106 augustss ohci_soft_ed_t *sed = opipe->sed;
2182 1.106 augustss ohci_soft_td_t *p, *n;
2183 1.106 augustss ohci_physaddr_t headp;
2184 1.224 mrg int hit;
2185 1.34 augustss
2186 1.274 pgoyette DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer,
2187 1.274 pgoyette (uintptr_t)opipe, (uintptr_t)sed, 0);
2188 1.34 augustss
2189 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2190 1.260 skrll ASSERT_SLEEPABLE();
2191 1.224 mrg
2192 1.293 riastrad KASSERTMSG((xfer->ux_status == USBD_CANCELLED ||
2193 1.293 riastrad xfer->ux_status == USBD_TIMEOUT),
2194 1.293 riastrad "bad abort status: %d", xfer->ux_status);
2195 1.116 augustss
2196 1.106 augustss /*
2197 1.282 mrg * If we're dying, skip the hardware action and just notify the
2198 1.282 mrg * software that we're done.
2199 1.159 augustss */
2200 1.282 mrg if (sc->sc_dying) {
2201 1.282 mrg DPRINTFN(4, "xfer %#jx dying %ju", (uintptr_t)xfer,
2202 1.282 mrg xfer->ux_status, 0, 0);
2203 1.282 mrg goto dying;
2204 1.159 augustss }
2205 1.159 augustss
2206 1.159 augustss /*
2207 1.282 mrg * HC Step 1: Unless the endpoint is already halted, we set the endpoint
2208 1.282 mrg * descriptor sKip bit and wait for hardware to complete processing.
2209 1.282 mrg *
2210 1.282 mrg * This includes ensuring that any TDs of the transfer that got onto
2211 1.282 mrg * the done list are also removed. We ensure this by waiting for
2212 1.282 mrg * both a WDH and SOF interrupt.
2213 1.106 augustss */
2214 1.274 pgoyette DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0);
2215 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2216 1.195 bouyer sizeof(sed->ed.ed_flags),
2217 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2218 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
2219 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2220 1.195 bouyer sizeof(sed->ed.ed_flags),
2221 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2222 1.34 augustss
2223 1.120 augustss /*
2224 1.282 mrg * HC Step 2: Wait until we know hardware has finished any possible
2225 1.282 mrg * use of the xfer.
2226 1.106 augustss */
2227 1.224 mrg /* Hardware finishes in 1ms */
2228 1.260 skrll usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock);
2229 1.119 augustss
2230 1.120 augustss /*
2231 1.282 mrg * HC Step 3: Remove any vestiges of the xfer from the hardware.
2232 1.106 augustss * The complication here is that the hardware may have executed
2233 1.106 augustss * beyond the xfer we're trying to abort. So as we're scanning
2234 1.106 augustss * the TDs of this xfer we check if the hardware points to
2235 1.106 augustss * any of them.
2236 1.106 augustss */
2237 1.260 skrll p = xfer->ux_hcpriv;
2238 1.260 skrll KASSERT(p);
2239 1.260 skrll
2240 1.106 augustss #ifdef OHCI_DEBUG
2241 1.260 skrll DPRINTF("--- dump start ---", 0, 0, 0, 0);
2242 1.260 skrll
2243 1.260 skrll if (ohcidebug >= 2) {
2244 1.260 skrll DPRINTF("sed:", 0, 0, 0, 0);
2245 1.168 augustss ohci_dump_ed(sc, sed);
2246 1.168 augustss ohci_dump_tds(sc, p);
2247 1.106 augustss }
2248 1.260 skrll DPRINTF("--- dump end ---", 0, 0, 0, 0);
2249 1.106 augustss #endif
2250 1.168 augustss headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK;
2251 1.106 augustss hit = 0;
2252 1.53 augustss for (; p->xfer == xfer; p = n) {
2253 1.106 augustss hit |= headp == p->physaddr;
2254 1.38 augustss n = p->nexttd;
2255 1.260 skrll ohci_hash_rem_td(sc, p);
2256 1.34 augustss }
2257 1.106 augustss /* Zap headp register if hardware pointed inside the xfer. */
2258 1.106 augustss if (hit) {
2259 1.274 pgoyette DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr,
2260 1.260 skrll (int)O32TOH(sed->ed.ed_tailp), 0, 0);
2261 1.292 gson /* unlink TDs, preserving toggle carry */
2262 1.292 gson sed->ed.ed_headp = HTOO32(p->physaddr |
2263 1.292 gson (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY));
2264 1.195 bouyer usb_syncmem(&sed->dma,
2265 1.195 bouyer sed->offs + offsetof(ohci_ed_t, ed_headp),
2266 1.195 bouyer sizeof(sed->ed.ed_headp),
2267 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2268 1.106 augustss } else {
2269 1.260 skrll DPRINTFN(1, "no hit", 0, 0, 0, 0);
2270 1.106 augustss }
2271 1.34 augustss
2272 1.106 augustss /*
2273 1.282 mrg * HC Step 4: Turn on hardware again.
2274 1.106 augustss */
2275 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2276 1.195 bouyer sizeof(sed->ed.ed_flags),
2277 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2278 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
2279 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
2280 1.195 bouyer sizeof(sed->ed.ed_flags),
2281 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2282 1.38 augustss
2283 1.106 augustss /*
2284 1.282 mrg * Final step: Notify completion to waiting xfers.
2285 1.106 augustss */
2286 1.282 mrg dying:
2287 1.53 augustss usb_transfer_complete(xfer);
2288 1.282 mrg DPRINTFN(14, "end", 0, 0, 0, 0);
2289 1.38 augustss
2290 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2291 1.34 augustss }
2292 1.34 augustss
2293 1.34 augustss /*
2294 1.1 augustss * Data structures and routines to emulate the root hub.
2295 1.1 augustss */
2296 1.260 skrll Static int
2297 1.260 skrll ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req,
2298 1.260 skrll void *buf, int buflen)
2299 1.1 augustss {
2300 1.260 skrll ohci_softc_t *sc = OHCI_BUS2SC(bus);
2301 1.260 skrll usb_port_status_t ps;
2302 1.260 skrll uint16_t len, value, index;
2303 1.260 skrll int l, totlen = 0;
2304 1.260 skrll int port, i;
2305 1.260 skrll uint32_t v;
2306 1.17 augustss
2307 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2308 1.1 augustss
2309 1.83 augustss if (sc->sc_dying)
2310 1.260 skrll return -1;
2311 1.1 augustss
2312 1.274 pgoyette DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType,
2313 1.260 skrll req->bRequest, 0, 0);
2314 1.1 augustss
2315 1.1 augustss len = UGETW(req->wLength);
2316 1.1 augustss value = UGETW(req->wValue);
2317 1.1 augustss index = UGETW(req->wIndex);
2318 1.43 augustss
2319 1.1 augustss #define C(x,y) ((x) | ((y) << 8))
2320 1.260 skrll switch (C(req->bRequest, req->bmRequestType)) {
2321 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
2322 1.274 pgoyette DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0);
2323 1.171 christos if (len == 0)
2324 1.171 christos break;
2325 1.260 skrll switch (value) {
2326 1.186 drochner #define sd ((usb_string_descriptor_t *)buf)
2327 1.260 skrll case C(2, UDESC_STRING):
2328 1.260 skrll /* Product */
2329 1.260 skrll totlen = usb_makestrdesc(sd, len, "OHCI root hub");
2330 1.260 skrll break;
2331 1.186 drochner #undef sd
2332 1.1 augustss default:
2333 1.260 skrll /* default from usbroothub */
2334 1.260 skrll return buflen;
2335 1.1 augustss }
2336 1.1 augustss break;
2337 1.260 skrll
2338 1.1 augustss /* Hub requests */
2339 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
2340 1.1 augustss break;
2341 1.1 augustss case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
2342 1.274 pgoyette DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd",
2343 1.260 skrll index, value, 0, 0);
2344 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2345 1.260 skrll return -1;
2346 1.1 augustss }
2347 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2348 1.1 augustss switch(value) {
2349 1.1 augustss case UHF_PORT_ENABLE:
2350 1.1 augustss OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
2351 1.1 augustss break;
2352 1.1 augustss case UHF_PORT_SUSPEND:
2353 1.1 augustss OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
2354 1.1 augustss break;
2355 1.1 augustss case UHF_PORT_POWER:
2356 1.86 augustss /* Yes, writing to the LOW_SPEED bit clears power. */
2357 1.1 augustss OWRITE4(sc, port, UPS_LOW_SPEED);
2358 1.1 augustss break;
2359 1.1 augustss case UHF_C_PORT_CONNECTION:
2360 1.1 augustss OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
2361 1.1 augustss break;
2362 1.1 augustss case UHF_C_PORT_ENABLE:
2363 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
2364 1.1 augustss break;
2365 1.1 augustss case UHF_C_PORT_SUSPEND:
2366 1.1 augustss OWRITE4(sc, port, UPS_C_SUSPEND << 16);
2367 1.1 augustss break;
2368 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2369 1.1 augustss OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
2370 1.1 augustss break;
2371 1.1 augustss case UHF_C_PORT_RESET:
2372 1.1 augustss OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
2373 1.1 augustss break;
2374 1.1 augustss default:
2375 1.260 skrll return -1;
2376 1.1 augustss }
2377 1.1 augustss switch(value) {
2378 1.1 augustss case UHF_C_PORT_CONNECTION:
2379 1.1 augustss case UHF_C_PORT_ENABLE:
2380 1.1 augustss case UHF_C_PORT_SUSPEND:
2381 1.1 augustss case UHF_C_PORT_OVER_CURRENT:
2382 1.1 augustss case UHF_C_PORT_RESET:
2383 1.1 augustss /* Enable RHSC interrupt if condition is cleared. */
2384 1.1 augustss if ((OREAD4(sc, port) >> 16) == 0)
2385 1.157 mycroft ohci_rhsc_enable(sc);
2386 1.1 augustss break;
2387 1.1 augustss default:
2388 1.1 augustss break;
2389 1.1 augustss }
2390 1.1 augustss break;
2391 1.1 augustss case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
2392 1.171 christos if (len == 0)
2393 1.171 christos break;
2394 1.146 toshii if ((value & 0xff) != 0) {
2395 1.260 skrll return -1;
2396 1.1 augustss }
2397 1.260 skrll usb_hub_descriptor_t hubd;
2398 1.260 skrll
2399 1.285 riastrad totlen = uimin(buflen, sizeof(hubd));
2400 1.260 skrll memcpy(&hubd, buf, totlen);
2401 1.260 skrll
2402 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
2403 1.1 augustss hubd.bNbrPorts = sc->sc_noport;
2404 1.15 augustss USETW(hubd.wHubCharacteristics,
2405 1.120 augustss (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
2406 1.1 augustss v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
2407 1.1 augustss /* XXX overcurrent */
2408 1.1 augustss );
2409 1.1 augustss hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
2410 1.1 augustss v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
2411 1.120 augustss for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
2412 1.260 skrll hubd.DeviceRemovable[i++] = (uint8_t)v;
2413 1.15 augustss hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
2414 1.285 riastrad totlen = uimin(totlen, hubd.bDescLength);
2415 1.260 skrll memcpy(buf, &hubd, totlen);
2416 1.1 augustss break;
2417 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
2418 1.1 augustss if (len != 4) {
2419 1.260 skrll return -1;
2420 1.1 augustss }
2421 1.1 augustss memset(buf, 0, len); /* ? XXX */
2422 1.1 augustss totlen = len;
2423 1.1 augustss break;
2424 1.1 augustss case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
2425 1.274 pgoyette DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0);
2426 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2427 1.260 skrll return -1;
2428 1.1 augustss }
2429 1.1 augustss if (len != 4) {
2430 1.260 skrll return -1;
2431 1.1 augustss }
2432 1.1 augustss v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
2433 1.274 pgoyette DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0);
2434 1.1 augustss USETW(ps.wPortStatus, v);
2435 1.1 augustss USETW(ps.wPortChange, v >> 16);
2436 1.285 riastrad totlen = uimin(len, sizeof(ps));
2437 1.260 skrll memcpy(buf, &ps, totlen);
2438 1.1 augustss break;
2439 1.1 augustss case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
2440 1.260 skrll return -1;
2441 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
2442 1.1 augustss break;
2443 1.1 augustss case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
2444 1.1 augustss if (index < 1 || index > sc->sc_noport) {
2445 1.260 skrll return -1;
2446 1.1 augustss }
2447 1.1 augustss port = OHCI_RH_PORT_STATUS(index);
2448 1.1 augustss switch(value) {
2449 1.1 augustss case UHF_PORT_ENABLE:
2450 1.1 augustss OWRITE4(sc, port, UPS_PORT_ENABLED);
2451 1.1 augustss break;
2452 1.1 augustss case UHF_PORT_SUSPEND:
2453 1.1 augustss OWRITE4(sc, port, UPS_SUSPEND);
2454 1.1 augustss break;
2455 1.1 augustss case UHF_PORT_RESET:
2456 1.274 pgoyette DPRINTFN(5, "reset port %jd", index, 0, 0, 0);
2457 1.1 augustss OWRITE4(sc, port, UPS_RESET);
2458 1.110 augustss for (i = 0; i < 5; i++) {
2459 1.110 augustss usb_delay_ms(&sc->sc_bus,
2460 1.110 augustss USB_PORT_ROOT_RESET_DELAY);
2461 1.116 augustss if (sc->sc_dying) {
2462 1.260 skrll return -1;
2463 1.116 augustss }
2464 1.1 augustss if ((OREAD4(sc, port) & UPS_RESET) == 0)
2465 1.1 augustss break;
2466 1.1 augustss }
2467 1.274 pgoyette DPRINTFN(8, "port %jd reset, status = 0x%04jx", index,
2468 1.260 skrll OREAD4(sc, port), 0, 0);
2469 1.1 augustss break;
2470 1.1 augustss case UHF_PORT_POWER:
2471 1.274 pgoyette DPRINTFN(2, "set port power %jd", index, 0, 0, 0);
2472 1.1 augustss OWRITE4(sc, port, UPS_PORT_POWER);
2473 1.1 augustss break;
2474 1.1 augustss default:
2475 1.260 skrll return -1;
2476 1.1 augustss }
2477 1.1 augustss break;
2478 1.1 augustss default:
2479 1.260 skrll /* default from usbroothub */
2480 1.260 skrll return buflen;
2481 1.1 augustss }
2482 1.1 augustss
2483 1.260 skrll return totlen;
2484 1.1 augustss }
2485 1.1 augustss
2486 1.82 augustss Static usbd_status
2487 1.260 skrll ohci_root_intr_transfer(struct usbd_xfer *xfer)
2488 1.1 augustss {
2489 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2490 1.53 augustss usbd_status err;
2491 1.17 augustss
2492 1.46 augustss /* Insert last in queue. */
2493 1.224 mrg mutex_enter(&sc->sc_lock);
2494 1.53 augustss err = usb_insert_transfer(xfer);
2495 1.224 mrg mutex_exit(&sc->sc_lock);
2496 1.53 augustss if (err)
2497 1.260 skrll return err;
2498 1.46 augustss
2499 1.46 augustss /* Pipe isn't running, start first */
2500 1.260 skrll return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2501 1.17 augustss }
2502 1.17 augustss
2503 1.82 augustss Static usbd_status
2504 1.260 skrll ohci_root_intr_start(struct usbd_xfer *xfer)
2505 1.17 augustss {
2506 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2507 1.287 mrg const bool polling = sc->sc_bus.ub_usepolling;
2508 1.1 augustss
2509 1.83 augustss if (sc->sc_dying)
2510 1.260 skrll return USBD_IOERROR;
2511 1.83 augustss
2512 1.287 mrg if (!polling)
2513 1.287 mrg mutex_enter(&sc->sc_lock);
2514 1.224 mrg KASSERT(sc->sc_intrxfer == NULL);
2515 1.53 augustss sc->sc_intrxfer = xfer;
2516 1.287 mrg if (!polling)
2517 1.287 mrg mutex_exit(&sc->sc_lock);
2518 1.1 augustss
2519 1.260 skrll return USBD_IN_PROGRESS;
2520 1.1 augustss }
2521 1.1 augustss
2522 1.3 augustss /* Abort a root interrupt request. */
2523 1.82 augustss Static void
2524 1.260 skrll ohci_root_intr_abort(struct usbd_xfer *xfer)
2525 1.1 augustss {
2526 1.279 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2527 1.224 mrg
2528 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2529 1.260 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
2530 1.53 augustss
2531 1.260 skrll xfer->ux_status = USBD_CANCELLED;
2532 1.53 augustss usb_transfer_complete(xfer);
2533 1.1 augustss }
2534 1.1 augustss
2535 1.1 augustss /* Close the root pipe. */
2536 1.82 augustss Static void
2537 1.260 skrll ohci_root_intr_close(struct usbd_pipe *pipe)
2538 1.1 augustss {
2539 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2540 1.120 augustss
2541 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2542 1.224 mrg
2543 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2544 1.34 augustss
2545 1.53 augustss sc->sc_intrxfer = NULL;
2546 1.1 augustss }
2547 1.1 augustss
2548 1.1 augustss /************************/
2549 1.1 augustss
2550 1.260 skrll int
2551 1.260 skrll ohci_device_ctrl_init(struct usbd_xfer *xfer)
2552 1.260 skrll {
2553 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2554 1.260 skrll usb_device_request_t *req = &xfer->ux_request;
2555 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2556 1.260 skrll ohci_soft_td_t *stat, *setup;
2557 1.260 skrll int isread = req->bmRequestType & UT_READ;
2558 1.260 skrll int len = xfer->ux_bufsize;
2559 1.260 skrll int err = ENOMEM;
2560 1.260 skrll
2561 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2562 1.260 skrll
2563 1.260 skrll setup = ohci_alloc_std(sc);
2564 1.260 skrll if (setup == NULL) {
2565 1.260 skrll goto bad1;
2566 1.260 skrll }
2567 1.260 skrll stat = ohci_alloc_std(sc);
2568 1.260 skrll if (stat == NULL) {
2569 1.260 skrll goto bad2;
2570 1.260 skrll }
2571 1.260 skrll
2572 1.260 skrll ox->ox_setup = setup;
2573 1.260 skrll ox->ox_stat = stat;
2574 1.260 skrll ox->ox_nstd = 0;
2575 1.260 skrll
2576 1.260 skrll /* Set up data transaction */
2577 1.260 skrll if (len != 0) {
2578 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2579 1.260 skrll if (err) {
2580 1.260 skrll goto bad3;
2581 1.260 skrll }
2582 1.260 skrll }
2583 1.260 skrll return 0;
2584 1.260 skrll
2585 1.260 skrll bad3:
2586 1.260 skrll ohci_free_std(sc, stat);
2587 1.260 skrll bad2:
2588 1.260 skrll ohci_free_std(sc, setup);
2589 1.260 skrll bad1:
2590 1.260 skrll return err;
2591 1.260 skrll }
2592 1.260 skrll
2593 1.260 skrll void
2594 1.260 skrll ohci_device_ctrl_fini(struct usbd_xfer *xfer)
2595 1.260 skrll {
2596 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2597 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2598 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2599 1.260 skrll
2600 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2601 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
2602 1.260 skrll
2603 1.260 skrll mutex_enter(&sc->sc_lock);
2604 1.260 skrll if (ox->ox_setup != opipe->tail.td) {
2605 1.260 skrll ohci_free_std_locked(sc, ox->ox_setup);
2606 1.260 skrll }
2607 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2608 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2609 1.260 skrll if (std == NULL)
2610 1.260 skrll break;
2611 1.260 skrll ohci_free_std_locked(sc, std);
2612 1.260 skrll }
2613 1.260 skrll ohci_free_std_locked(sc, ox->ox_stat);
2614 1.260 skrll mutex_exit(&sc->sc_lock);
2615 1.260 skrll
2616 1.260 skrll if (ox->ox_nstd) {
2617 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2618 1.260 skrll kmem_free(ox->ox_stds, sz);
2619 1.260 skrll }
2620 1.260 skrll }
2621 1.260 skrll
2622 1.82 augustss Static usbd_status
2623 1.260 skrll ohci_device_ctrl_transfer(struct usbd_xfer *xfer)
2624 1.1 augustss {
2625 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2626 1.53 augustss usbd_status err;
2627 1.17 augustss
2628 1.46 augustss /* Insert last in queue. */
2629 1.224 mrg mutex_enter(&sc->sc_lock);
2630 1.53 augustss err = usb_insert_transfer(xfer);
2631 1.224 mrg mutex_exit(&sc->sc_lock);
2632 1.53 augustss if (err)
2633 1.260 skrll return err;
2634 1.46 augustss
2635 1.46 augustss /* Pipe isn't running, start first */
2636 1.260 skrll return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2637 1.17 augustss }
2638 1.17 augustss
2639 1.82 augustss Static usbd_status
2640 1.260 skrll ohci_device_ctrl_start(struct usbd_xfer *xfer)
2641 1.17 augustss {
2642 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2643 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2644 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2645 1.260 skrll usb_device_request_t *req = &xfer->ux_request;
2646 1.260 skrll struct usbd_device *dev __diagused = opipe->pipe.up_dev;
2647 1.260 skrll ohci_soft_td_t *setup, *stat, *next, *tail;
2648 1.260 skrll ohci_soft_ed_t *sed;
2649 1.260 skrll int isread;
2650 1.260 skrll int len;
2651 1.287 mrg const bool polling = sc->sc_bus.ub_usepolling;
2652 1.260 skrll
2653 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2654 1.1 augustss
2655 1.83 augustss if (sc->sc_dying)
2656 1.260 skrll return USBD_IOERROR;
2657 1.260 skrll
2658 1.260 skrll KASSERT(xfer->ux_rqflags & URQ_REQUEST);
2659 1.260 skrll
2660 1.260 skrll isread = req->bmRequestType & UT_READ;
2661 1.260 skrll len = UGETW(req->wLength);
2662 1.260 skrll
2663 1.274 pgoyette DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len,
2664 1.274 pgoyette dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress);
2665 1.274 pgoyette DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx",
2666 1.260 skrll req->bmRequestType, req->bRequest, UGETW(req->wValue),
2667 1.260 skrll UGETW(req->wIndex));
2668 1.260 skrll
2669 1.260 skrll /* Need to take lock here for pipe->tail.td */
2670 1.287 mrg if (!polling)
2671 1.287 mrg mutex_enter(&sc->sc_lock);
2672 1.260 skrll
2673 1.260 skrll /*
2674 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2675 1.260 skrll * next transfer
2676 1.260 skrll */
2677 1.260 skrll setup = opipe->tail.td;
2678 1.260 skrll opipe->tail.td = ox->ox_setup;
2679 1.260 skrll ox->ox_setup = setup;
2680 1.260 skrll
2681 1.260 skrll stat = ox->ox_stat;
2682 1.260 skrll
2683 1.260 skrll /* point at sentinel */
2684 1.260 skrll tail = opipe->tail.td;
2685 1.260 skrll sed = opipe->sed;
2686 1.260 skrll
2687 1.260 skrll KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr,
2688 1.260 skrll "address ED %d pipe %d\n",
2689 1.260 skrll OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr);
2690 1.260 skrll KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) ==
2691 1.260 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize),
2692 1.260 skrll "MPL ED %d pipe %d\n",
2693 1.260 skrll OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)),
2694 1.260 skrll UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize));
2695 1.260 skrll
2696 1.260 skrll /* next will point to data if len != 0 */
2697 1.260 skrll next = stat;
2698 1.260 skrll
2699 1.260 skrll /* Set up data transaction */
2700 1.260 skrll if (len != 0) {
2701 1.260 skrll ohci_soft_td_t *std;
2702 1.260 skrll ohci_soft_td_t *end;
2703 1.260 skrll
2704 1.260 skrll next = ox->ox_stds[0];
2705 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, next, &end);
2706 1.260 skrll
2707 1.260 skrll end->td.td_nexttd = HTOO32(stat->physaddr);
2708 1.260 skrll end->nexttd = stat;
2709 1.260 skrll
2710 1.273 skrll usb_syncmem(&end->dma, end->offs, sizeof(end->td),
2711 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2712 1.260 skrll
2713 1.260 skrll usb_syncmem(&xfer->ux_dmabuf, 0, len,
2714 1.260 skrll isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
2715 1.260 skrll std = ox->ox_stds[0];
2716 1.260 skrll /* Start toggle at 1 and then use the carried toggle. */
2717 1.260 skrll std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK);
2718 1.260 skrll std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1);
2719 1.260 skrll usb_syncmem(&std->dma,
2720 1.260 skrll std->offs + offsetof(ohci_td_t, td_flags),
2721 1.260 skrll sizeof(std->td.td_flags),
2722 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2723 1.260 skrll }
2724 1.260 skrll
2725 1.274 pgoyette DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx",
2726 1.274 pgoyette (uintptr_t)setup,
2727 1.274 pgoyette (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat,
2728 1.274 pgoyette (uintptr_t)tail);
2729 1.260 skrll KASSERT(opipe->tail.td == tail);
2730 1.260 skrll
2731 1.260 skrll memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req));
2732 1.260 skrll usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE);
2733 1.83 augustss
2734 1.260 skrll setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC |
2735 1.260 skrll OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
2736 1.260 skrll setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0));
2737 1.260 skrll setup->td.td_nexttd = HTOO32(next->physaddr);
2738 1.260 skrll setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1);
2739 1.260 skrll setup->nexttd = next;
2740 1.260 skrll setup->len = 0;
2741 1.260 skrll setup->xfer = xfer;
2742 1.260 skrll setup->flags = 0;
2743 1.260 skrll ohci_hash_add_td(sc, setup);
2744 1.260 skrll
2745 1.260 skrll xfer->ux_hcpriv = setup;
2746 1.260 skrll usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td),
2747 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2748 1.260 skrll
2749 1.260 skrll stat->td.td_flags = HTOO32(
2750 1.260 skrll (isread ? OHCI_TD_OUT : OHCI_TD_IN) |
2751 1.260 skrll OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
2752 1.260 skrll stat->td.td_cbp = 0;
2753 1.260 skrll stat->td.td_nexttd = HTOO32(tail->physaddr);
2754 1.260 skrll stat->td.td_be = 0;
2755 1.260 skrll stat->nexttd = tail;
2756 1.260 skrll stat->flags = OHCI_CALL_DONE;
2757 1.260 skrll stat->len = 0;
2758 1.260 skrll stat->xfer = xfer;
2759 1.260 skrll ohci_hash_add_td(sc, stat);
2760 1.260 skrll
2761 1.260 skrll usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td),
2762 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2763 1.260 skrll
2764 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
2765 1.260 skrll tail->nexttd = NULL;
2766 1.260 skrll tail->xfer = NULL;
2767 1.260 skrll
2768 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2769 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2770 1.260 skrll
2771 1.260 skrll #ifdef OHCI_DEBUG
2772 1.260 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0);
2773 1.260 skrll if (ohcidebug >= 5) {
2774 1.260 skrll ohci_dump_ed(sc, sed);
2775 1.260 skrll ohci_dump_tds(sc, setup);
2776 1.1 augustss }
2777 1.260 skrll USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0);
2778 1.42 augustss #endif
2779 1.1 augustss
2780 1.260 skrll /* Insert ED in schedule */
2781 1.260 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
2782 1.260 skrll usb_syncmem(&sed->dma,
2783 1.260 skrll sed->offs + offsetof(ohci_ed_t, ed_tailp),
2784 1.260 skrll sizeof(sed->ed.ed_tailp),
2785 1.260 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2786 1.260 skrll OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
2787 1.293 riastrad usbd_xfer_schedule_timeout(xfer);
2788 1.260 skrll
2789 1.260 skrll DPRINTF("done", 0, 0, 0, 0);
2790 1.260 skrll
2791 1.282 mrg xfer->ux_status = USBD_IN_PROGRESS;
2792 1.287 mrg if (!polling)
2793 1.287 mrg mutex_exit(&sc->sc_lock);
2794 1.1 augustss
2795 1.260 skrll return USBD_IN_PROGRESS;
2796 1.1 augustss }
2797 1.1 augustss
2798 1.1 augustss /* Abort a device control request. */
2799 1.82 augustss Static void
2800 1.260 skrll ohci_device_ctrl_abort(struct usbd_xfer *xfer)
2801 1.1 augustss {
2802 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
2803 1.224 mrg
2804 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2805 1.224 mrg
2806 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2807 1.274 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
2808 1.293 riastrad usbd_xfer_abort(xfer);
2809 1.1 augustss }
2810 1.1 augustss
2811 1.1 augustss /* Close a device control pipe. */
2812 1.82 augustss Static void
2813 1.260 skrll ohci_device_ctrl_close(struct usbd_pipe *pipe)
2814 1.1 augustss {
2815 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2816 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2817 1.1 augustss
2818 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
2819 1.224 mrg
2820 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2821 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
2822 1.34 augustss ohci_close_pipe(pipe, sc->sc_ctrl_head);
2823 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
2824 1.3 augustss }
2825 1.3 augustss
2826 1.3 augustss /************************/
2827 1.37 augustss
2828 1.82 augustss Static void
2829 1.260 skrll ohci_device_clear_toggle(struct usbd_pipe *pipe)
2830 1.37 augustss {
2831 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
2832 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
2833 1.37 augustss
2834 1.168 augustss opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY);
2835 1.37 augustss }
2836 1.37 augustss
2837 1.82 augustss Static void
2838 1.260 skrll ohci_noop(struct usbd_pipe *pipe)
2839 1.37 augustss {
2840 1.37 augustss }
2841 1.3 augustss
2842 1.260 skrll Static int
2843 1.260 skrll ohci_device_bulk_init(struct usbd_xfer *xfer)
2844 1.260 skrll {
2845 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2846 1.260 skrll int len = xfer->ux_bufsize;
2847 1.281 maya int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2848 1.260 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2849 1.260 skrll int err;
2850 1.260 skrll
2851 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2852 1.260 skrll
2853 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2854 1.260 skrll
2855 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
2856 1.274 pgoyette len, isread, xfer->ux_flags);
2857 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
2858 1.260 skrll
2859 1.260 skrll /* Allocate a chain of new TDs (including a new tail). */
2860 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
2861 1.260 skrll if (err)
2862 1.260 skrll return err;
2863 1.260 skrll
2864 1.260 skrll return 0;
2865 1.260 skrll }
2866 1.260 skrll
2867 1.260 skrll Static void
2868 1.260 skrll ohci_device_bulk_fini(struct usbd_xfer *xfer)
2869 1.260 skrll {
2870 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2871 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2872 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2873 1.260 skrll
2874 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2875 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
2876 1.260 skrll
2877 1.260 skrll mutex_enter(&sc->sc_lock);
2878 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
2879 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
2880 1.260 skrll if (std == NULL)
2881 1.260 skrll break;
2882 1.260 skrll if (std != opipe->tail.td)
2883 1.260 skrll ohci_free_std_locked(sc, std);
2884 1.260 skrll }
2885 1.260 skrll mutex_exit(&sc->sc_lock);
2886 1.260 skrll
2887 1.260 skrll if (ox->ox_nstd) {
2888 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
2889 1.260 skrll kmem_free(ox->ox_stds, sz);
2890 1.260 skrll }
2891 1.260 skrll }
2892 1.260 skrll
2893 1.82 augustss Static usbd_status
2894 1.260 skrll ohci_device_bulk_transfer(struct usbd_xfer *xfer)
2895 1.3 augustss {
2896 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2897 1.53 augustss usbd_status err;
2898 1.17 augustss
2899 1.46 augustss /* Insert last in queue. */
2900 1.224 mrg mutex_enter(&sc->sc_lock);
2901 1.53 augustss err = usb_insert_transfer(xfer);
2902 1.224 mrg mutex_exit(&sc->sc_lock);
2903 1.53 augustss if (err)
2904 1.260 skrll return err;
2905 1.46 augustss
2906 1.46 augustss /* Pipe isn't running, start first */
2907 1.260 skrll return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
2908 1.17 augustss }
2909 1.17 augustss
2910 1.82 augustss Static usbd_status
2911 1.260 skrll ohci_device_bulk_start(struct usbd_xfer *xfer)
2912 1.17 augustss {
2913 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
2914 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
2915 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
2916 1.260 skrll ohci_soft_td_t *last;
2917 1.48 augustss ohci_soft_td_t *data, *tail, *tdp;
2918 1.3 augustss ohci_soft_ed_t *sed;
2919 1.224 mrg int len, isread, endpt;
2920 1.287 mrg const bool polling = sc->sc_bus.ub_usepolling;
2921 1.260 skrll
2922 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
2923 1.3 augustss
2924 1.83 augustss if (sc->sc_dying)
2925 1.260 skrll return USBD_IOERROR;
2926 1.83 augustss
2927 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
2928 1.224 mrg
2929 1.260 skrll len = xfer->ux_length;
2930 1.260 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
2931 1.40 augustss isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2932 1.3 augustss sed = opipe->sed;
2933 1.3 augustss
2934 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
2935 1.274 pgoyette len, isread, xfer->ux_flags);
2936 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
2937 1.34 augustss
2938 1.287 mrg if (!polling)
2939 1.287 mrg mutex_enter(&sc->sc_lock);
2940 1.3 augustss
2941 1.260 skrll /*
2942 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
2943 1.260 skrll * next transfer
2944 1.260 skrll */
2945 1.260 skrll data = opipe->tail.td;
2946 1.260 skrll opipe->tail.td = ox->ox_stds[0];
2947 1.260 skrll ox->ox_stds[0] = data;
2948 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
2949 1.260 skrll
2950 1.260 skrll /* point at sentinel */
2951 1.260 skrll tail = opipe->tail.td;
2952 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
2953 1.260 skrll tail->nexttd = NULL;
2954 1.260 skrll tail->xfer = NULL;
2955 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
2956 1.273 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2957 1.260 skrll xfer->ux_hcpriv = data;
2958 1.3 augustss
2959 1.274 pgoyette DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer,
2960 1.274 pgoyette (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0);
2961 1.260 skrll KASSERT(opipe->tail.td == tail);
2962 1.258 skrll
2963 1.77 augustss /* We want interrupt at the end of the transfer. */
2964 1.260 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
2965 1.260 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
2966 1.260 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
2967 1.260 skrll last->nexttd = tail;
2968 1.260 skrll last->flags |= OHCI_CALL_DONE;
2969 1.260 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
2970 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2971 1.3 augustss
2972 1.274 pgoyette DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx "
2973 1.274 pgoyette "td_cbp=0x%08jx td_be=0x%08jx",
2974 1.168 augustss (int)O32TOH(sed->ed.ed_flags),
2975 1.168 augustss (int)O32TOH(data->td.td_flags),
2976 1.168 augustss (int)O32TOH(data->td.td_cbp),
2977 1.260 skrll (int)O32TOH(data->td.td_be));
2978 1.34 augustss
2979 1.52 augustss #ifdef OHCI_DEBUG
2980 1.260 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
2981 1.260 skrll if (ohcidebug >= 5) {
2982 1.168 augustss ohci_dump_ed(sc, sed);
2983 1.168 augustss ohci_dump_tds(sc, data);
2984 1.34 augustss }
2985 1.260 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
2986 1.34 augustss #endif
2987 1.34 augustss
2988 1.3 augustss /* Insert ED in schedule */
2989 1.48 augustss for (tdp = data; tdp != tail; tdp = tdp->nexttd) {
2990 1.260 skrll KASSERT(tdp->xfer == xfer);
2991 1.48 augustss }
2992 1.260 skrll usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2993 1.260 skrll BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2994 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
2995 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
2996 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
2997 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2998 1.3 augustss OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
2999 1.293 riastrad usbd_xfer_schedule_timeout(xfer);
3000 1.282 mrg xfer->ux_status = USBD_IN_PROGRESS;
3001 1.287 mrg if (!polling)
3002 1.287 mrg mutex_exit(&sc->sc_lock);
3003 1.34 augustss
3004 1.260 skrll return USBD_IN_PROGRESS;
3005 1.3 augustss }
3006 1.3 augustss
3007 1.82 augustss Static void
3008 1.260 skrll ohci_device_bulk_abort(struct usbd_xfer *xfer)
3009 1.3 augustss {
3010 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3011 1.260 skrll
3012 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3013 1.224 mrg
3014 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3015 1.224 mrg
3016 1.274 pgoyette DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3017 1.293 riastrad usbd_xfer_abort(xfer);
3018 1.3 augustss }
3019 1.3 augustss
3020 1.120 augustss /*
3021 1.34 augustss * Close a device bulk pipe.
3022 1.34 augustss */
3023 1.82 augustss Static void
3024 1.260 skrll ohci_device_bulk_close(struct usbd_pipe *pipe)
3025 1.3 augustss {
3026 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3027 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3028 1.3 augustss
3029 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3030 1.224 mrg
3031 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3032 1.260 skrll
3033 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3034 1.34 augustss ohci_close_pipe(pipe, sc->sc_bulk_head);
3035 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
3036 1.1 augustss }
3037 1.1 augustss
3038 1.1 augustss /************************/
3039 1.1 augustss
3040 1.260 skrll Static int
3041 1.260 skrll ohci_device_intr_init(struct usbd_xfer *xfer)
3042 1.260 skrll {
3043 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3044 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3045 1.260 skrll int len = xfer->ux_bufsize;
3046 1.281 maya int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3047 1.260 skrll int isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3048 1.260 skrll int err;
3049 1.260 skrll
3050 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3051 1.260 skrll
3052 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3053 1.260 skrll KASSERT(len != 0);
3054 1.260 skrll
3055 1.274 pgoyette DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer,
3056 1.274 pgoyette len, isread, xfer->ux_flags);
3057 1.274 pgoyette DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0);
3058 1.260 skrll
3059 1.260 skrll ox->ox_nstd = 0;
3060 1.260 skrll
3061 1.260 skrll err = ohci_alloc_std_chain(sc, xfer, len, isread);
3062 1.260 skrll if (err) {
3063 1.260 skrll return err;
3064 1.260 skrll }
3065 1.260 skrll
3066 1.260 skrll return 0;
3067 1.260 skrll }
3068 1.260 skrll
3069 1.260 skrll Static void
3070 1.260 skrll ohci_device_intr_fini(struct usbd_xfer *xfer)
3071 1.260 skrll {
3072 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3073 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3074 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3075 1.260 skrll
3076 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3077 1.274 pgoyette DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0);
3078 1.260 skrll
3079 1.260 skrll mutex_enter(&sc->sc_lock);
3080 1.260 skrll for (size_t i = 0; i < ox->ox_nstd; i++) {
3081 1.260 skrll ohci_soft_td_t *std = ox->ox_stds[i];
3082 1.260 skrll if (std != NULL)
3083 1.260 skrll break;
3084 1.260 skrll if (std != opipe->tail.td)
3085 1.260 skrll ohci_free_std_locked(sc, std);
3086 1.260 skrll }
3087 1.260 skrll mutex_exit(&sc->sc_lock);
3088 1.260 skrll
3089 1.260 skrll if (ox->ox_nstd) {
3090 1.260 skrll const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd;
3091 1.260 skrll kmem_free(ox->ox_stds, sz);
3092 1.260 skrll }
3093 1.260 skrll }
3094 1.260 skrll
3095 1.82 augustss Static usbd_status
3096 1.260 skrll ohci_device_intr_transfer(struct usbd_xfer *xfer)
3097 1.17 augustss {
3098 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3099 1.53 augustss usbd_status err;
3100 1.17 augustss
3101 1.46 augustss /* Insert last in queue. */
3102 1.224 mrg mutex_enter(&sc->sc_lock);
3103 1.53 augustss err = usb_insert_transfer(xfer);
3104 1.224 mrg mutex_exit(&sc->sc_lock);
3105 1.53 augustss if (err)
3106 1.260 skrll return err;
3107 1.46 augustss
3108 1.46 augustss /* Pipe isn't running, start first */
3109 1.260 skrll return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue));
3110 1.17 augustss }
3111 1.17 augustss
3112 1.82 augustss Static usbd_status
3113 1.260 skrll ohci_device_intr_start(struct usbd_xfer *xfer)
3114 1.1 augustss {
3115 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3116 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3117 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3118 1.1 augustss ohci_soft_ed_t *sed = opipe->sed;
3119 1.260 skrll ohci_soft_td_t *data, *last, *tail;
3120 1.224 mrg int len, isread, endpt;
3121 1.287 mrg const bool polling = sc->sc_bus.ub_usepolling;
3122 1.1 augustss
3123 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3124 1.260 skrll
3125 1.83 augustss if (sc->sc_dying)
3126 1.260 skrll return USBD_IOERROR;
3127 1.83 augustss
3128 1.274 pgoyette DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer,
3129 1.274 pgoyette xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv);
3130 1.1 augustss
3131 1.260 skrll KASSERT(!(xfer->ux_rqflags & URQ_REQUEST));
3132 1.1 augustss
3133 1.260 skrll len = xfer->ux_length;
3134 1.260 skrll endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;
3135 1.165 skrll isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3136 1.1 augustss
3137 1.287 mrg if (!polling)
3138 1.287 mrg mutex_enter(&sc->sc_lock);
3139 1.260 skrll
3140 1.260 skrll /*
3141 1.260 skrll * Use the pipe "tail" TD as our first and loan our first TD to the
3142 1.260 skrll * next transfer.
3143 1.260 skrll */
3144 1.60 augustss data = opipe->tail.td;
3145 1.260 skrll opipe->tail.td = ox->ox_stds[0];
3146 1.260 skrll ox->ox_stds[0] = data;
3147 1.260 skrll ohci_reset_std_chain(sc, xfer, len, isread, data, &last);
3148 1.260 skrll
3149 1.260 skrll /* point at sentinel */
3150 1.260 skrll tail = opipe->tail.td;
3151 1.260 skrll memset(&tail->td, 0, sizeof(tail->td));
3152 1.260 skrll tail->nexttd = NULL;
3153 1.53 augustss tail->xfer = NULL;
3154 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td),
3155 1.273 skrll BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3156 1.260 skrll xfer->ux_hcpriv = data;
3157 1.260 skrll
3158 1.274 pgoyette DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0],
3159 1.274 pgoyette (uintptr_t)tail, 0, 0);
3160 1.260 skrll KASSERT(opipe->tail.td == tail);
3161 1.260 skrll
3162 1.260 skrll /* We want interrupt at the end of the transfer. */
3163 1.260 skrll last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK);
3164 1.260 skrll last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1));
3165 1.1 augustss
3166 1.260 skrll last->td.td_nexttd = HTOO32(tail->physaddr);
3167 1.260 skrll last->nexttd = tail;
3168 1.260 skrll last->flags |= OHCI_CALL_DONE;
3169 1.260 skrll usb_syncmem(&last->dma, last->offs, sizeof(last->td),
3170 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3171 1.1 augustss
3172 1.52 augustss #ifdef OHCI_DEBUG
3173 1.260 skrll DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0);
3174 1.260 skrll if (ohcidebug >= 5) {
3175 1.168 augustss ohci_dump_ed(sc, sed);
3176 1.168 augustss ohci_dump_tds(sc, data);
3177 1.1 augustss }
3178 1.260 skrll DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0);
3179 1.1 augustss #endif
3180 1.1 augustss
3181 1.1 augustss /* Insert ED in schedule */
3182 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3183 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3184 1.168 augustss sed->ed.ed_tailp = HTOO32(tail->physaddr);
3185 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3186 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3187 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3188 1.1 augustss
3189 1.282 mrg xfer->ux_status = USBD_IN_PROGRESS;
3190 1.287 mrg if (!polling)
3191 1.287 mrg mutex_exit(&sc->sc_lock);
3192 1.1 augustss
3193 1.260 skrll return USBD_IN_PROGRESS;
3194 1.1 augustss }
3195 1.1 augustss
3196 1.227 skrll /* Abort a device interrupt request. */
3197 1.82 augustss Static void
3198 1.260 skrll ohci_device_intr_abort(struct usbd_xfer *xfer)
3199 1.1 augustss {
3200 1.260 skrll ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer);
3201 1.224 mrg
3202 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3203 1.260 skrll KASSERT(xfer->ux_pipe->up_intrxfer == xfer);
3204 1.224 mrg
3205 1.293 riastrad usbd_xfer_abort(xfer);
3206 1.1 augustss }
3207 1.1 augustss
3208 1.1 augustss /* Close a device interrupt pipe. */
3209 1.82 augustss Static void
3210 1.260 skrll ohci_device_intr_close(struct usbd_pipe *pipe)
3211 1.1 augustss {
3212 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3213 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3214 1.260 skrll int nslots = opipe->intr.nslots;
3215 1.260 skrll int pos = opipe->intr.pos;
3216 1.1 augustss int j;
3217 1.1 augustss ohci_soft_ed_t *p, *sed = opipe->sed;
3218 1.224 mrg
3219 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3220 1.260 skrll
3221 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3222 1.1 augustss
3223 1.274 pgoyette DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots,
3224 1.274 pgoyette pos, 0);
3225 1.195 bouyer usb_syncmem(&sed->dma, sed->offs,
3226 1.195 bouyer sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3227 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP);
3228 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3229 1.195 bouyer sizeof(sed->ed.ed_flags),
3230 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3231 1.168 augustss if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) !=
3232 1.168 augustss (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK))
3233 1.224 mrg usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock);
3234 1.1 augustss
3235 1.1 augustss for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
3236 1.172 christos continue;
3237 1.260 skrll KASSERT(p);
3238 1.173 christos p->next = sed->next;
3239 1.173 christos p->ed.ed_nexted = sed->ed.ed_nexted;
3240 1.195 bouyer usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted),
3241 1.195 bouyer sizeof(p->ed.ed_nexted),
3242 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3243 1.1 augustss
3244 1.1 augustss for (j = 0; j < nslots; j++)
3245 1.31 wrstuden --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS];
3246 1.1 augustss
3247 1.260 skrll ohci_free_std_locked(sc, opipe->tail.td);
3248 1.260 skrll ohci_free_sed_locked(sc, opipe->sed);
3249 1.1 augustss }
3250 1.1 augustss
3251 1.82 augustss Static usbd_status
3252 1.91 augustss ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival)
3253 1.1 augustss {
3254 1.224 mrg int i, j, best;
3255 1.1 augustss u_int npoll, slow, shigh, nslots;
3256 1.1 augustss u_int bestbw, bw;
3257 1.1 augustss ohci_soft_ed_t *hsed, *sed = opipe->sed;
3258 1.1 augustss
3259 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3260 1.260 skrll
3261 1.274 pgoyette DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0);
3262 1.1 augustss if (ival == 0) {
3263 1.1 augustss printf("ohci_setintr: 0 interval\n");
3264 1.260 skrll return USBD_INVAL;
3265 1.1 augustss }
3266 1.1 augustss
3267 1.1 augustss npoll = OHCI_NO_INTRS;
3268 1.1 augustss while (npoll > ival)
3269 1.1 augustss npoll /= 2;
3270 1.274 pgoyette DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0);
3271 1.1 augustss
3272 1.1 augustss /*
3273 1.1 augustss * We now know which level in the tree the ED must go into.
3274 1.1 augustss * Figure out which slot has most bandwidth left over.
3275 1.1 augustss * Slots to examine:
3276 1.1 augustss * npoll
3277 1.1 augustss * 1 0
3278 1.1 augustss * 2 1 2
3279 1.1 augustss * 4 3 4 5 6
3280 1.1 augustss * 8 7 8 9 10 11 12 13 14
3281 1.1 augustss * N (N-1) .. (N-1+N-1)
3282 1.1 augustss */
3283 1.1 augustss slow = npoll-1;
3284 1.1 augustss shigh = slow + npoll;
3285 1.1 augustss nslots = OHCI_NO_INTRS / npoll;
3286 1.1 augustss for (best = i = slow, bestbw = ~0; i < shigh; i++) {
3287 1.1 augustss bw = 0;
3288 1.1 augustss for (j = 0; j < nslots; j++)
3289 1.28 augustss bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS];
3290 1.1 augustss if (bw < bestbw) {
3291 1.1 augustss best = i;
3292 1.1 augustss bestbw = bw;
3293 1.1 augustss }
3294 1.1 augustss }
3295 1.274 pgoyette DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw);
3296 1.1 augustss
3297 1.224 mrg mutex_enter(&sc->sc_lock);
3298 1.1 augustss hsed = sc->sc_eds[best];
3299 1.1 augustss sed->next = hsed->next;
3300 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3301 1.195 bouyer sizeof(hsed->ed.ed_flags),
3302 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3303 1.39 augustss sed->ed.ed_nexted = hsed->ed.ed_nexted;
3304 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3305 1.195 bouyer sizeof(sed->ed.ed_flags),
3306 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3307 1.1 augustss hsed->next = sed;
3308 1.168 augustss hsed->ed.ed_nexted = HTOO32(sed->physaddr);
3309 1.195 bouyer usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags),
3310 1.195 bouyer sizeof(hsed->ed.ed_flags),
3311 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3312 1.224 mrg mutex_exit(&sc->sc_lock);
3313 1.1 augustss
3314 1.1 augustss for (j = 0; j < nslots; j++)
3315 1.28 augustss ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS];
3316 1.260 skrll opipe->intr.nslots = nslots;
3317 1.260 skrll opipe->intr.pos = best;
3318 1.1 augustss
3319 1.274 pgoyette DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0);
3320 1.260 skrll return USBD_NORMAL_COMPLETION;
3321 1.60 augustss }
3322 1.60 augustss
3323 1.60 augustss /***********************/
3324 1.60 augustss
3325 1.260 skrll Static int
3326 1.260 skrll ohci_device_isoc_init(struct usbd_xfer *xfer)
3327 1.260 skrll {
3328 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3329 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3330 1.260 skrll ohci_soft_itd_t *sitd;
3331 1.260 skrll size_t i;
3332 1.260 skrll int err;
3333 1.260 skrll
3334 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3335 1.260 skrll
3336 1.274 pgoyette DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer,
3337 1.274 pgoyette xfer->ux_length, xfer->ux_flags, 0);
3338 1.260 skrll
3339 1.260 skrll const size_t nfsitd =
3340 1.260 skrll (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET;
3341 1.260 skrll const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE;
3342 1.260 skrll const size_t nsitd = MAX(nfsitd, nbsitd) + 1;
3343 1.260 skrll
3344 1.260 skrll ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd,
3345 1.260 skrll KM_SLEEP);
3346 1.260 skrll ox->ox_nsitd = nsitd;
3347 1.260 skrll
3348 1.260 skrll for (i = 0; i < nsitd; i++) {
3349 1.260 skrll /* Allocate next ITD */
3350 1.260 skrll sitd = ohci_alloc_sitd(sc);
3351 1.260 skrll if (sitd == NULL) {
3352 1.260 skrll err = ENOMEM;
3353 1.260 skrll goto fail;
3354 1.260 skrll }
3355 1.260 skrll ox->ox_sitds[i] = sitd;
3356 1.260 skrll sitd->xfer = xfer;
3357 1.260 skrll sitd->flags = 0;
3358 1.260 skrll }
3359 1.260 skrll
3360 1.260 skrll return 0;
3361 1.260 skrll fail:
3362 1.260 skrll for (; i > 0;) {
3363 1.260 skrll ohci_free_sitd(sc, ox->ox_sitds[--i]);
3364 1.260 skrll }
3365 1.260 skrll return err;
3366 1.260 skrll }
3367 1.260 skrll
3368 1.260 skrll Static void
3369 1.260 skrll ohci_device_isoc_fini(struct usbd_xfer *xfer)
3370 1.260 skrll {
3371 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3372 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3373 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3374 1.260 skrll
3375 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3376 1.260 skrll
3377 1.260 skrll mutex_enter(&sc->sc_lock);
3378 1.260 skrll for (size_t i = 0; i < ox->ox_nsitd; i++) {
3379 1.260 skrll if (ox->ox_sitds[i] != opipe->tail.itd) {
3380 1.260 skrll ohci_free_sitd_locked(sc, ox->ox_sitds[i]);
3381 1.260 skrll }
3382 1.260 skrll }
3383 1.260 skrll mutex_exit(&sc->sc_lock);
3384 1.260 skrll
3385 1.260 skrll if (ox->ox_nsitd) {
3386 1.260 skrll const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd;
3387 1.260 skrll kmem_free(ox->ox_sitds, sz);
3388 1.260 skrll }
3389 1.260 skrll }
3390 1.260 skrll
3391 1.260 skrll
3392 1.60 augustss usbd_status
3393 1.260 skrll ohci_device_isoc_transfer(struct usbd_xfer *xfer)
3394 1.60 augustss {
3395 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3396 1.260 skrll usbd_status __diagused err;
3397 1.260 skrll
3398 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3399 1.60 augustss
3400 1.274 pgoyette DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3401 1.60 augustss
3402 1.60 augustss /* Put it on our queue, */
3403 1.224 mrg mutex_enter(&sc->sc_lock);
3404 1.60 augustss err = usb_insert_transfer(xfer);
3405 1.224 mrg mutex_exit(&sc->sc_lock);
3406 1.60 augustss
3407 1.260 skrll KASSERT(err == USBD_NORMAL_COMPLETION);
3408 1.60 augustss
3409 1.60 augustss /* insert into schedule, */
3410 1.60 augustss ohci_device_isoc_enter(xfer);
3411 1.60 augustss
3412 1.83 augustss /* and start if the pipe wasn't running */
3413 1.260 skrll return USBD_IN_PROGRESS;
3414 1.60 augustss }
3415 1.60 augustss
3416 1.60 augustss void
3417 1.260 skrll ohci_device_isoc_enter(struct usbd_xfer *xfer)
3418 1.60 augustss {
3419 1.260 skrll struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer);
3420 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3421 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3422 1.61 augustss ohci_soft_ed_t *sed = opipe->sed;
3423 1.260 skrll ohci_soft_itd_t *sitd, *nsitd, *tail;
3424 1.83 augustss ohci_physaddr_t buf, offs, noffs, bp0;
3425 1.61 augustss int i, ncur, nframes;
3426 1.61 augustss
3427 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3428 1.274 pgoyette DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3429 1.260 skrll
3430 1.260 skrll mutex_enter(&sc->sc_lock);
3431 1.83 augustss
3432 1.260 skrll if (sc->sc_dying) {
3433 1.260 skrll mutex_exit(&sc->sc_lock);
3434 1.83 augustss return;
3435 1.260 skrll }
3436 1.260 skrll
3437 1.260 skrll struct isoc *isoc = &opipe->isoc;
3438 1.260 skrll
3439 1.274 pgoyette DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd",
3440 1.274 pgoyette isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes);
3441 1.83 augustss
3442 1.260 skrll if (isoc->next == -1) {
3443 1.83 augustss /* Not in use yet, schedule it a few frames ahead. */
3444 1.260 skrll isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5;
3445 1.274 pgoyette DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0);
3446 1.83 augustss }
3447 1.83 augustss
3448 1.61 augustss sitd = opipe->tail.itd;
3449 1.260 skrll opipe->tail.itd = ox->ox_sitds[0];
3450 1.260 skrll ox->ox_sitds[0] = sitd;
3451 1.260 skrll
3452 1.260 skrll buf = DMAADDR(&xfer->ux_dmabuf, 0);
3453 1.83 augustss bp0 = OHCI_PAGE(buf);
3454 1.83 augustss offs = OHCI_PAGE_OFFSET(buf);
3455 1.260 skrll nframes = xfer->ux_nframes;
3456 1.260 skrll xfer->ux_hcpriv = sitd;
3457 1.260 skrll size_t j = 1;
3458 1.61 augustss for (i = ncur = 0; i < nframes; i++, ncur++) {
3459 1.260 skrll noffs = offs + xfer->ux_frlengths[i];
3460 1.61 augustss if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */
3461 1.83 augustss OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */
3462 1.120 augustss
3463 1.83 augustss /* Allocate next ITD */
3464 1.260 skrll nsitd = ox->ox_sitds[j++];
3465 1.260 skrll KASSERT(nsitd != NULL);
3466 1.260 skrll KASSERT(j < ox->ox_nsitd);
3467 1.83 augustss
3468 1.83 augustss /* Fill current ITD */
3469 1.168 augustss sitd->itd.itd_flags = HTOO32(
3470 1.120 augustss OHCI_ITD_NOCC |
3471 1.260 skrll OHCI_ITD_SET_SF(isoc->next) |
3472 1.83 augustss OHCI_ITD_SET_DI(6) | /* delay intr a little */
3473 1.83 augustss OHCI_ITD_SET_FC(ncur));
3474 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3475 1.168 augustss sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr);
3476 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3477 1.260 skrll sitd->nextitd = nsitd;
3478 1.83 augustss sitd->xfer = xfer;
3479 1.83 augustss sitd->flags = 0;
3480 1.260 skrll #ifdef DIAGNOSTIC
3481 1.260 skrll sitd->isdone = false;
3482 1.260 skrll #endif
3483 1.260 skrll ohci_hash_add_itd(sc, sitd);
3484 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3485 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3486 1.83 augustss
3487 1.61 augustss sitd = nsitd;
3488 1.260 skrll isoc->next = isoc->next + ncur;
3489 1.83 augustss bp0 = OHCI_PAGE(buf + offs);
3490 1.61 augustss ncur = 0;
3491 1.61 augustss }
3492 1.168 augustss sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs));
3493 1.273 skrll /* XXX Sync */
3494 1.83 augustss offs = noffs;
3495 1.61 augustss }
3496 1.260 skrll KASSERT(j <= ox->ox_nsitd);
3497 1.260 skrll
3498 1.260 skrll /* point at sentinel */
3499 1.260 skrll tail = opipe->tail.itd;
3500 1.260 skrll memset(&tail->itd, 0, sizeof(tail->itd));
3501 1.260 skrll tail->nextitd = NULL;
3502 1.265 skrll tail->xfer = NULL;
3503 1.260 skrll usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd),
3504 1.260 skrll BUS_DMASYNC_PREWRITE);
3505 1.260 skrll
3506 1.83 augustss /* Fixup last used ITD */
3507 1.168 augustss sitd->itd.itd_flags = HTOO32(
3508 1.120 augustss OHCI_ITD_NOCC |
3509 1.260 skrll OHCI_ITD_SET_SF(isoc->next) |
3510 1.61 augustss OHCI_ITD_SET_DI(0) |
3511 1.61 augustss OHCI_ITD_SET_FC(ncur));
3512 1.168 augustss sitd->itd.itd_bp0 = HTOO32(bp0);
3513 1.260 skrll sitd->itd.itd_nextitd = HTOO32(tail->physaddr);
3514 1.168 augustss sitd->itd.itd_be = HTOO32(bp0 + offs - 1);
3515 1.260 skrll sitd->nextitd = tail;
3516 1.83 augustss sitd->xfer = xfer;
3517 1.83 augustss sitd->flags = OHCI_CALL_DONE;
3518 1.260 skrll #ifdef DIAGNOSTIC
3519 1.260 skrll sitd->isdone = false;
3520 1.260 skrll #endif
3521 1.260 skrll ohci_hash_add_itd(sc, sitd);
3522 1.195 bouyer usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd),
3523 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3524 1.83 augustss
3525 1.260 skrll isoc->next = isoc->next + ncur;
3526 1.260 skrll isoc->inuse += nframes;
3527 1.83 augustss
3528 1.260 skrll /* XXX pretend we did it all */
3529 1.260 skrll xfer->ux_actlen = offs;
3530 1.260 skrll xfer->ux_status = USBD_IN_PROGRESS;
3531 1.83 augustss
3532 1.83 augustss #ifdef OHCI_DEBUG
3533 1.260 skrll if (ohcidebug >= 5) {
3534 1.274 pgoyette DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number),
3535 1.260 skrll 0, 0, 0);
3536 1.260 skrll ohci_dump_itds(sc, xfer->ux_hcpriv);
3537 1.168 augustss ohci_dump_ed(sc, sed);
3538 1.83 augustss }
3539 1.83 augustss #endif
3540 1.61 augustss
3541 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3542 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3543 1.260 skrll sed->ed.ed_tailp = HTOO32(tail->physaddr);
3544 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP);
3545 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3546 1.195 bouyer sizeof(sed->ed.ed_flags),
3547 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3548 1.224 mrg mutex_exit(&sc->sc_lock);
3549 1.60 augustss }
3550 1.60 augustss
3551 1.60 augustss void
3552 1.260 skrll ohci_device_isoc_abort(struct usbd_xfer *xfer)
3553 1.60 augustss {
3554 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe);
3555 1.260 skrll ohci_softc_t *sc = OHCI_XFER2SC(xfer);
3556 1.83 augustss ohci_soft_ed_t *sed;
3557 1.83 augustss ohci_soft_itd_t *sitd;
3558 1.83 augustss
3559 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3560 1.274 pgoyette DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3561 1.83 augustss
3562 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3563 1.83 augustss
3564 1.83 augustss /* Transfer is already done. */
3565 1.260 skrll if (xfer->ux_status != USBD_NOT_STARTED &&
3566 1.260 skrll xfer->ux_status != USBD_IN_PROGRESS) {
3567 1.83 augustss printf("ohci_device_isoc_abort: early return\n");
3568 1.224 mrg goto done;
3569 1.83 augustss }
3570 1.83 augustss
3571 1.83 augustss /* Give xfer the requested abort code. */
3572 1.260 skrll xfer->ux_status = USBD_CANCELLED;
3573 1.83 augustss
3574 1.83 augustss sed = opipe->sed;
3575 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3576 1.195 bouyer BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
3577 1.168 augustss sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */
3578 1.195 bouyer usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags),
3579 1.195 bouyer sizeof(sed->ed.ed_flags),
3580 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3581 1.83 augustss
3582 1.260 skrll sitd = xfer->ux_hcpriv;
3583 1.260 skrll KASSERT(sitd);
3584 1.260 skrll
3585 1.260 skrll usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock);
3586 1.260 skrll
3587 1.83 augustss for (; sitd->xfer == xfer; sitd = sitd->nextitd) {
3588 1.260 skrll ohci_hash_rem_itd(sc, sitd);
3589 1.83 augustss #ifdef DIAGNOSTIC
3590 1.274 pgoyette DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd,
3591 1.274 pgoyette 0, 0, 0);
3592 1.260 skrll sitd->isdone = true;
3593 1.83 augustss #endif
3594 1.83 augustss }
3595 1.83 augustss
3596 1.83 augustss /* Run callback. */
3597 1.83 augustss usb_transfer_complete(xfer);
3598 1.83 augustss
3599 1.168 augustss sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */
3600 1.168 augustss sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */
3601 1.195 bouyer usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed),
3602 1.195 bouyer BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
3603 1.83 augustss
3604 1.224 mrg done:
3605 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3606 1.60 augustss }
3607 1.60 augustss
3608 1.60 augustss void
3609 1.260 skrll ohci_device_isoc_done(struct usbd_xfer *xfer)
3610 1.60 augustss {
3611 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3612 1.274 pgoyette DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0);
3613 1.60 augustss }
3614 1.60 augustss
3615 1.60 augustss usbd_status
3616 1.260 skrll ohci_setup_isoc(struct usbd_pipe *pipe)
3617 1.60 augustss {
3618 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3619 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3620 1.260 skrll struct isoc *isoc = &opipe->isoc;
3621 1.60 augustss
3622 1.260 skrll isoc->next = -1;
3623 1.260 skrll isoc->inuse = 0;
3624 1.60 augustss
3625 1.224 mrg mutex_enter(&sc->sc_lock);
3626 1.168 augustss ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head);
3627 1.224 mrg mutex_exit(&sc->sc_lock);
3628 1.83 augustss
3629 1.260 skrll return USBD_NORMAL_COMPLETION;
3630 1.60 augustss }
3631 1.60 augustss
3632 1.60 augustss void
3633 1.260 skrll ohci_device_isoc_close(struct usbd_pipe *pipe)
3634 1.60 augustss {
3635 1.260 skrll struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe);
3636 1.260 skrll ohci_softc_t *sc = OHCI_PIPE2SC(pipe);
3637 1.60 augustss
3638 1.224 mrg KASSERT(mutex_owned(&sc->sc_lock));
3639 1.224 mrg
3640 1.260 skrll OHCIHIST_FUNC(); OHCIHIST_CALLED();
3641 1.274 pgoyette DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0);
3642 1.60 augustss ohci_close_pipe(pipe, sc->sc_isoc_head);
3643 1.83 augustss #ifdef DIAGNOSTIC
3644 1.260 skrll opipe->tail.itd->isdone = true;
3645 1.83 augustss #endif
3646 1.260 skrll ohci_free_sitd_locked(sc, opipe->tail.itd);
3647 1.1 augustss }
3648