ohci.c revision 1.10 1 /* $NetBSD: ohci.c,v 1.10 1998/11/22 20:21:22 augustss Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Author: Lennart Augustsson <augustss (at) carlstedt.se>
8 * Carlstedt Research & Technology
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * USB Open Host Controller driver.
41 *
42 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf
43 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/device.h>
51 #include <sys/proc.h>
52 #include <sys/queue.h>
53 #include <sys/select.h>
54
55 #include <machine/bus.h>
56
57 #include <dev/usb/usb.h>
58 #include <dev/usb/usbdi.h>
59 #include <dev/usb/usbdivar.h>
60 #include <dev/usb/usb_quirks.h>
61 #include <dev/usb/usb_mem.h>
62
63 #include <dev/usb/ohcireg.h>
64 #include <dev/usb/ohcivar.h>
65
66 int ohcidebug = 0;
67
68 struct ohci_pipe;
69
70 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *));
71 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *));
72
73 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *));
74 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *));
75
76 usbd_status ohci_open __P((usbd_pipe_handle));
77 void ohci_poll __P((struct usbd_bus *));
78 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle));
79 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle));
80 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t));
81 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle));
82 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle));
83 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle));
84
85 usbd_status ohci_device_request __P((usbd_request_handle reqh));
86 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
87 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
88 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *));
89 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *));
90 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t));
91
92 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle));
93 void ohci_root_ctrl_abort __P((usbd_request_handle));
94 void ohci_root_ctrl_close __P((usbd_pipe_handle));
95
96 usbd_status ohci_root_intr_transfer __P((usbd_request_handle));
97 void ohci_root_intr_abort __P((usbd_request_handle));
98 void ohci_root_intr_close __P((usbd_pipe_handle));
99
100 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle));
101 void ohci_device_ctrl_abort __P((usbd_request_handle));
102 void ohci_device_ctrl_close __P((usbd_pipe_handle));
103
104 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle));
105 void ohci_device_bulk_abort __P((usbd_request_handle));
106 void ohci_device_bulk_close __P((usbd_pipe_handle));
107
108 usbd_status ohci_device_intr_transfer __P((usbd_request_handle));
109 void ohci_device_intr_abort __P((usbd_request_handle));
110 void ohci_device_intr_close __P((usbd_pipe_handle));
111 usbd_status ohci_device_setintr __P((ohci_softc_t *sc,
112 struct ohci_pipe *pipe, int ival));
113
114 int ohci_str __P((usb_string_descriptor_t *, int, char *));
115
116 void ohci_timeout __P((void *));
117 void ohci_rhsc_able __P((ohci_softc_t *, int));
118
119 #ifdef USB_DEBUG
120 ohci_softc_t *thesc;
121 void ohci_dumpregs __P((ohci_softc_t *));
122 void ohci_dump_tds __P((ohci_soft_td_t *));
123 void ohci_dump_td __P((ohci_soft_td_t *));
124 void ohci_dump_ed __P((ohci_soft_ed_t *));
125 #endif
126
127 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x))
128 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r))
129 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r))
130
131 /* Reverse the bits in a value 0 .. 31 */
132 static u_int8_t revbits[OHCI_NO_INTRS] =
133 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
134 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
135 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
136 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
137
138 struct ohci_pipe {
139 struct usbd_pipe pipe;
140 ohci_soft_ed_t *sed;
141 ohci_soft_td_t *tail;
142 /* Info needed for different pipe kinds. */
143 union {
144 /* Control pipe */
145 struct {
146 usb_dma_t datadma;
147 usb_dma_t reqdma;
148 u_int length;
149 ohci_soft_td_t *setup, *xfer, *stat;
150 } ctl;
151 /* Interrupt pipe */
152 struct {
153 usb_dma_t datadma;
154 int nslots;
155 int pos;
156 } intr;
157 /* Bulk pipe */
158 struct {
159 usb_dma_t datadma;
160 u_int length;
161 } bulk;
162 } u;
163 };
164
165 #define OHCI_INTR_ENDPT 1
166
167 struct usbd_methods ohci_root_ctrl_methods = {
168 ohci_root_ctrl_transfer,
169 ohci_root_ctrl_abort,
170 ohci_root_ctrl_close,
171 0,
172 };
173
174 struct usbd_methods ohci_root_intr_methods = {
175 ohci_root_intr_transfer,
176 ohci_root_intr_abort,
177 ohci_root_intr_close,
178 0,
179 };
180
181 struct usbd_methods ohci_device_ctrl_methods = {
182 ohci_device_ctrl_transfer,
183 ohci_device_ctrl_abort,
184 ohci_device_ctrl_close,
185 0,
186 };
187
188 struct usbd_methods ohci_device_intr_methods = {
189 ohci_device_intr_transfer,
190 ohci_device_intr_abort,
191 ohci_device_intr_close,
192 };
193
194 struct usbd_methods ohci_device_bulk_methods = {
195 ohci_device_bulk_transfer,
196 ohci_device_bulk_abort,
197 ohci_device_bulk_close,
198 0,
199 };
200
201 ohci_soft_ed_t *
202 ohci_alloc_sed(sc)
203 ohci_softc_t *sc;
204 {
205 ohci_soft_ed_t *sed;
206 usbd_status r;
207 int i, offs;
208 usb_dma_t dma;
209
210 if (!sc->sc_freeeds) {
211 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
212 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK,
213 M_USBDEV, M_NOWAIT);
214 if (!sed)
215 return 0;
216 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK,
217 OHCI_ED_ALIGN, &dma);
218 if (r != USBD_NORMAL_COMPLETION) {
219 free(sed, M_USBDEV);
220 return 0;
221 }
222 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) {
223 offs = i * OHCI_ED_SIZE;
224 sed->physaddr = DMAADDR(&dma) + offs;
225 sed->ed = (ohci_ed_t *)
226 ((char *)KERNADDR(&dma) + offs);
227 sed->next = sc->sc_freeeds;
228 sc->sc_freeeds = sed;
229 }
230 }
231 sed = sc->sc_freeeds;
232 sc->sc_freeeds = sed->next;
233 memset(sed->ed, 0, OHCI_ED_SIZE);
234 sed->next = 0;
235 return sed;
236 }
237
238 void
239 ohci_free_sed(sc, sed)
240 ohci_softc_t *sc;
241 ohci_soft_ed_t *sed;
242 {
243 sed->next = sc->sc_freeeds;
244 sc->sc_freeeds = sed;
245 }
246
247 ohci_soft_td_t *
248 ohci_alloc_std(sc)
249 ohci_softc_t *sc;
250 {
251 ohci_soft_td_t *std;
252 usbd_status r;
253 int i, offs;
254 usb_dma_t dma;
255
256 if (!sc->sc_freetds) {
257 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
258 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK,
259 M_USBDEV, M_NOWAIT);
260 if (!std)
261 return 0;
262 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK,
263 OHCI_TD_ALIGN, &dma);
264 if (r != USBD_NORMAL_COMPLETION) {
265 free(std, M_USBDEV);
266 return 0;
267 }
268 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) {
269 offs = i * OHCI_TD_SIZE;
270 std->physaddr = DMAADDR(&dma) + offs;
271 std->td = (ohci_td_t *)
272 ((char *)KERNADDR(&dma) + offs);
273 std->nexttd = sc->sc_freetds;
274 sc->sc_freetds = std;
275 }
276 }
277 std = sc->sc_freetds;
278 sc->sc_freetds = std->nexttd;
279 memset(std->td, 0, OHCI_TD_SIZE);
280 std->nexttd = 0;
281 return (std);
282 }
283
284 void
285 ohci_free_std(sc, std)
286 ohci_softc_t *sc;
287 ohci_soft_td_t *std;
288 {
289 std->nexttd = sc->sc_freetds;
290 sc->sc_freetds = std;
291 }
292
293 usbd_status
294 ohci_init(sc)
295 ohci_softc_t *sc;
296 {
297 ohci_soft_ed_t *sed, *psed;
298 usbd_status r;
299 int rev;
300 int i;
301 u_int32_t s, ctl, ival, hcr, fm, per;
302
303 DPRINTF(("ohci_init: start\n"));
304 rev = OREAD4(sc, OHCI_REVISION);
305 printf("%s: OHCI version %d.%d%s\n", sc->sc_bus.bdev.dv_xname,
306 OHCI_REV_HI(rev), OHCI_REV_LO(rev),
307 OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
308 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
309 printf("%s: unsupported OHCI revision\n",
310 sc->sc_bus.bdev.dv_xname);
311 return (USBD_INVAL);
312 }
313
314 for (i = 0; i < OHCI_HASH_SIZE; i++)
315 LIST_INIT(&sc->sc_hash_tds[i]);
316
317 /* Allocate the HCCA area. */
318 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE,
319 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
320 if (r != USBD_NORMAL_COMPLETION)
321 return (r);
322 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
323 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
324
325 sc->sc_eintrs = OHCI_NORMAL_INTRS;
326
327 sc->sc_ctrl_head = ohci_alloc_sed(sc);
328 if (!sc->sc_ctrl_head) {
329 r = USBD_NOMEM;
330 goto bad1;
331 }
332 sc->sc_ctrl_head->ed->ed_flags |= OHCI_ED_SKIP;
333 sc->sc_bulk_head = ohci_alloc_sed(sc);
334 if (!sc->sc_bulk_head) {
335 r = USBD_NOMEM;
336 goto bad2;
337 }
338 sc->sc_bulk_head->ed->ed_flags |= OHCI_ED_SKIP;
339
340 /* Allocate all the dummy EDs that make up the interrupt tree. */
341 for (i = 0; i < OHCI_NO_EDS; i++) {
342 sed = ohci_alloc_sed(sc);
343 if (!sed) {
344 while (--i >= 0)
345 ohci_free_sed(sc, sc->sc_eds[i]);
346 r = USBD_NOMEM;
347 goto bad3;
348 }
349 /* All ED fields are set to 0. */
350 sc->sc_eds[i] = sed;
351 sed->ed->ed_flags |= OHCI_ED_SKIP;
352 if (i != 0) {
353 psed = sc->sc_eds[(i-1) / 2];
354 sed->next = psed;
355 sed->ed->ed_nexted = psed->physaddr;
356 }
357 }
358 /*
359 * Fill HCCA interrupt table. The bit reversal is to get
360 * the tree set up properly to spread the interrupts.
361 */
362 for (i = 0; i < OHCI_NO_INTRS; i++)
363 sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
364 sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr;
365
366 /* Determine in what context we are running. */
367 ctl = OREAD4(sc, OHCI_CONTROL);
368 if (ctl & OHCI_IR) {
369 /* SMM active, request change */
370 DPRINTF(("ohci_init: SMM active, request owner change\n"));
371 s = OREAD4(sc, OHCI_COMMAND_STATUS);
372 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
373 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
374 delay(1000);
375 ctl = OREAD4(sc, OHCI_CONTROL);
376 }
377 if ((ctl & OHCI_IR) == 0) {
378 printf("%s: SMM does not respond, resetting\n",
379 sc->sc_bus.bdev.dv_xname);
380 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
381 goto reset;
382 }
383 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
384 /* BIOS started controller. */
385 DPRINTF(("ohci_init: BIOS active\n"));
386 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
387 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL);
388 delay(USB_RESUME_DELAY * 1000);
389 }
390 } else {
391 DPRINTF(("ohci_init: cold started\n"));
392 reset:
393 /* Controller was cold started. */
394 delay(USB_RESET_DELAY * 1000);
395 }
396
397 /* We now own the host controller and the bus has been reset. */
398 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
399
400 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
401 /* Nominal time for a reset is 10 us. */
402 for (i = 0; i < 10; i++) {
403 delay(10);
404 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
405 if (!hcr)
406 break;
407 }
408 if (hcr) {
409 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname);
410 r = USBD_IOERROR;
411 goto bad3;
412 }
413 #ifdef USB_DEBUG
414 thesc = sc;
415 if (ohcidebug > 15)
416 ohci_dumpregs(sc);
417 #endif
418
419 /* The controller is now in suspend state, we have 2ms to finish. */
420
421 /* Set up HC registers. */
422 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma));
423 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
424 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
425 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
426 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
427 ctl = OREAD4(sc, OHCI_CONTROL);
428 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
429 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
430 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
431 /* And finally start it! */
432 OWRITE4(sc, OHCI_CONTROL, ctl);
433
434 /*
435 * The controller is now OPERATIONAL. Set a some final
436 * registers that should be set earlier, but that the
437 * controller ignores when in the SUSPEND state.
438 */
439 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
440 fm |= OHCI_FSMPS(ival) | ival;
441 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
442 per = OHCI_PERIODIC(ival); /* 90% periodic */
443 OWRITE4(sc, OHCI_PERIODIC_START, per);
444
445 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
446
447 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
448 printf("%s: %d downstream port%s\n",
449 sc->sc_bus.bdev.dv_xname, sc->sc_noport,
450 sc->sc_noport != 1 ? "s" : "");
451
452 #ifdef USB_DEBUG
453 if (ohcidebug > 5)
454 ohci_dumpregs(sc);
455 #endif
456
457 /* Set up the bus struct. */
458 sc->sc_bus.open_pipe = ohci_open;
459 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
460 sc->sc_bus.do_poll = ohci_poll;
461
462 return (USBD_NORMAL_COMPLETION);
463
464 bad3:
465 ohci_free_sed(sc, sc->sc_ctrl_head);
466 bad2:
467 ohci_free_sed(sc, sc->sc_bulk_head);
468 bad1:
469 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma);
470 return (r);
471 }
472
473 #ifdef USB_DEBUG
474 void ohcidump(void);
475 void ohcidump(void) { ohci_dumpregs(thesc); }
476
477 void
478 ohci_dumpregs(sc)
479 ohci_softc_t *sc;
480 {
481 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
482 OREAD4(sc, OHCI_REVISION),
483 OREAD4(sc, OHCI_CONTROL),
484 OREAD4(sc, OHCI_COMMAND_STATUS));
485 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
486 OREAD4(sc, OHCI_INTERRUPT_STATUS),
487 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
488 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
489 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
490 OREAD4(sc, OHCI_HCCA),
491 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
492 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
493 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
494 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
495 OREAD4(sc, OHCI_BULK_HEAD_ED),
496 OREAD4(sc, OHCI_BULK_CURRENT_ED));
497 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
498 OREAD4(sc, OHCI_DONE_HEAD),
499 OREAD4(sc, OHCI_FM_INTERVAL),
500 OREAD4(sc, OHCI_FM_REMAINING));
501 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
502 OREAD4(sc, OHCI_FM_NUMBER),
503 OREAD4(sc, OHCI_PERIODIC_START),
504 OREAD4(sc, OHCI_LS_THRESHOLD));
505 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
506 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
507 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
508 OREAD4(sc, OHCI_RH_STATUS));
509 printf(" port1=0x%08x port2=0x%08x\n",
510 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
511 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
512 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
513 sc->sc_hcca->hcca_frame_number,
514 sc->sc_hcca->hcca_done_head);
515 }
516 #endif
517
518 int
519 ohci_intr(p)
520 void *p;
521 {
522 ohci_softc_t *sc = p;
523 u_int32_t intrs, eintrs;
524 ohci_physaddr_t done;
525
526 done = sc->sc_hcca->hcca_done_head;
527 if (done != 0) {
528 intrs = OHCI_WDH;
529 if (done & OHCI_DONE_INTRS)
530 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
531 } else
532 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
533 if (!intrs)
534 return (0);
535 intrs &= ~OHCI_MIE;
536 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */
537 eintrs = intrs & sc->sc_eintrs;
538 if (!eintrs)
539 return (0);
540
541 sc->sc_intrs++;
542 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n",
543 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
544 (u_int)eintrs));
545
546 if (eintrs & OHCI_SO) {
547 printf("%s: scheduling overrun\n", sc->sc_bus.bdev.dv_xname);
548 /* XXX do what */
549 intrs &= ~OHCI_SO;
550 }
551 if (eintrs & OHCI_WDH) {
552 ohci_process_done(sc, done &~ OHCI_DONE_INTRS);
553 sc->sc_hcca->hcca_done_head = 0;
554 intrs &= ~OHCI_WDH;
555 }
556 if (eintrs & OHCI_RD) {
557 /* XXX process resume detect */
558 }
559 if (eintrs & OHCI_UE) {
560 printf("%s: unrecoverable error, controller halted\n",
561 sc->sc_bus.bdev.dv_xname);
562 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
563 /* XXX what else */
564 }
565 if (eintrs & OHCI_RHSC) {
566 ohci_rhsc(sc, sc->sc_intrreqh);
567 intrs &= ~OHCI_RHSC;
568
569 /*
570 * Disable RHSC interrupt for now, because it will be
571 * on until the port has been reset.
572 */
573 ohci_rhsc_able(sc, 0);
574 }
575
576 /* Block unprocessed interrupts. XXX */
577 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs);
578 sc->sc_eintrs &= ~intrs;
579
580 return (1);
581 }
582
583 void
584 ohci_rhsc_able(sc, on)
585 ohci_softc_t *sc;
586 int on;
587 {
588 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on));
589 if (on) {
590 sc->sc_eintrs |= OHCI_RHSC;
591 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
592 } else {
593 sc->sc_eintrs &= ~OHCI_RHSC;
594 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
595 }
596 }
597
598 void
599 ohci_process_done(sc, done)
600 ohci_softc_t *sc;
601 ohci_physaddr_t done;
602 {
603 ohci_soft_td_t *std, *sdone;
604 usbd_request_handle reqh;
605 int len, cc;
606
607 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done));
608
609 /* Reverse the done list. */
610 for (sdone = 0; done; done = std->td->td_nexttd) {
611 std = ohci_hash_find_td(sc, done);
612 std->dnext = sdone;
613 sdone = std;
614 }
615
616 #ifdef USB_DEBUG
617 if (ohcidebug > 10) {
618 printf("ohci_process_done: TD done:\n");
619 ohci_dump_tds(sdone);
620 }
621 #endif
622
623 for (std = sdone; std; std = std->dnext) {
624 reqh = std->reqh;
625 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh));
626 cc = OHCI_TD_GET_CC(std->td->td_flags);
627 if (cc == OHCI_CC_NO_ERROR) {
628 if (std->td->td_cbp == 0)
629 len = std->len;
630 else
631 len = std->td->td_be - std->td->td_cbp + 1;
632 reqh->actlen += len;
633 if (reqh->hcpriv == std) {
634 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
635 case UE_CONTROL:
636 ohci_ctrl_done(sc, reqh);
637 break;
638 case UE_INTERRUPT:
639 ohci_intr_done(sc, reqh);
640 break;
641 case UE_BULK:
642 ohci_bulk_done(sc, reqh);
643 break;
644 case UE_ISOCHRONOUS:
645 printf("ohci_process_done: ISO done?\n");
646 break;
647 }
648 /* And finally execute callback. */
649 reqh->status = USBD_NORMAL_COMPLETION;
650 reqh->xfercb(reqh);
651 }
652 } else {
653 ohci_soft_td_t *p, *n;
654 struct ohci_pipe *opipe =
655 (struct ohci_pipe *)reqh->pipe;
656 DPRINTFN(-1,("ohci_process_done: error cc=%d\n",
657 OHCI_TD_GET_CC(std->td->td_flags)));
658 /*
659 * Endpoint is halted. First unlink all the TDs
660 * belonging to the failed transfer, and then restart
661 * the endpoint.
662 */
663 for (p = std->nexttd; p->reqh == reqh; p = n) {
664 n = p->nexttd;
665 ohci_hash_rem_td(sc, p);
666 ohci_free_std(sc, p);
667 }
668 opipe->sed->ed->ed_headp = p->physaddr;/* clear halt */
669 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
670
671 if (cc == OHCI_CC_STALL)
672 reqh->status = USBD_STALLED;
673 else
674 reqh->status = USBD_IOERROR;
675 reqh->xfercb(reqh);
676 }
677 ohci_hash_rem_td(sc, std);
678 ohci_free_std(sc, std);
679 }
680 }
681
682 void
683 ohci_ctrl_done(sc, reqh)
684 ohci_softc_t *sc;
685 usbd_request_handle reqh;
686 {
687 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
688 u_int len = opipe->u.ctl.length;
689 usb_dma_t *dma;
690
691 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh));
692
693 if (!reqh->isreq) {
694 panic("ohci_ctrl_done: not a request\n");
695 return;
696 }
697
698 if (len != 0) {
699 dma = &opipe->u.ctl.datadma;
700 if (reqh->request.bmRequestType & UT_READ)
701 memcpy(reqh->buffer, KERNADDR(dma), len);
702 usb_freemem(sc->sc_dmatag, dma);
703 }
704 }
705
706 void
707 ohci_intr_done(sc, reqh)
708 ohci_softc_t *sc;
709 usbd_request_handle reqh;
710 {
711 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
712 usb_dma_t *dma;
713 ohci_soft_ed_t *sed = opipe->sed;
714 ohci_soft_td_t *xfer, *tail;
715
716
717 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n",
718 reqh, reqh->actlen));
719
720 dma = &opipe->u.intr.datadma;
721 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
722
723 if (reqh->pipe->intrreqh == reqh) {
724 xfer = opipe->tail;
725 tail = ohci_alloc_std(sc); /* XXX should reuse TD */
726 if (!tail) {
727 reqh->status = USBD_NOMEM;
728 return;
729 }
730 tail->reqh = 0;
731
732 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC |
733 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
734 xfer->td->td_cbp = DMAADDR(dma);
735 xfer->nexttd = tail;
736 xfer->td->td_nexttd = tail->physaddr;
737 xfer->td->td_be = xfer->td->td_cbp + reqh->length - 1;
738 xfer->len = reqh->length;
739 xfer->reqh = reqh;
740
741 reqh->actlen = 0;
742 reqh->hcpriv = xfer;
743
744 ohci_hash_add_td(sc, xfer);
745 sed->ed->ed_tailp = tail->physaddr;
746 opipe->tail = tail;
747 } else {
748 usb_freemem(sc->sc_dmatag, dma);
749 }
750 }
751
752 void
753 ohci_bulk_done(sc, reqh)
754 ohci_softc_t *sc;
755 usbd_request_handle reqh;
756 {
757 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
758 usb_dma_t *dma;
759
760
761 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n",
762 reqh, reqh->actlen));
763
764 dma = &opipe->u.bulk.datadma;
765 if (reqh->request.bmRequestType & UT_READ)
766 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
767 usb_freemem(sc->sc_dmatag, dma);
768 }
769
770 void
771 ohci_rhsc(sc, reqh)
772 ohci_softc_t *sc;
773 usbd_request_handle reqh;
774 {
775 usbd_pipe_handle pipe;
776 struct ohci_pipe *opipe;
777 u_char *p;
778 int i, m;
779 int hstatus;
780
781 hstatus = OREAD4(sc, OHCI_RH_STATUS);
782 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n",
783 sc, reqh, hstatus));
784
785 if (reqh == 0) {
786 /* Just ignore the change. */
787 return;
788 }
789
790 pipe = reqh->pipe;
791 opipe = (struct ohci_pipe *)pipe;
792
793 p = KERNADDR(&opipe->u.intr.datadma);
794 m = min(sc->sc_noport, reqh->length * 8 - 1);
795 memset(p, 0, reqh->length);
796 for (i = 1; i <= m; i++) {
797 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
798 p[i/8] |= 1 << (i%8);
799 }
800 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
801 reqh->actlen = reqh->length;
802 reqh->status = USBD_NORMAL_COMPLETION;
803 reqh->xfercb(reqh);
804
805 if (reqh->pipe->intrreqh != reqh) {
806 sc->sc_intrreqh = 0;
807 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma);
808 }
809 }
810
811 /*
812 * Wait here until controller claims to have an interrupt.
813 * Then call ohci_intr and return. Use timeout to avoid waiting
814 * too long.
815 */
816 void
817 ohci_waitintr(sc, reqh)
818 ohci_softc_t *sc;
819 usbd_request_handle reqh;
820 {
821 int timo = reqh->timeout;
822 int usecs;
823 u_int32_t intrs;
824
825 reqh->status = USBD_IN_PROGRESS;
826 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
827 delay(1000);
828 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
829 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs));
830 #ifdef USB_DEBUG
831 if (ohcidebug > 15)
832 ohci_dumpregs(sc);
833 #endif
834 if (intrs) {
835 ohci_intr(sc);
836 if (reqh->status != USBD_IN_PROGRESS)
837 return;
838 }
839 }
840 DPRINTF(("ohci_waitintr: timeout\n"));
841 reqh->status = USBD_TIMEOUT;
842 reqh->xfercb(reqh);
843 }
844
845 void
846 ohci_poll(bus)
847 struct usbd_bus *bus;
848 {
849 ohci_softc_t *sc = (ohci_softc_t *)bus;
850
851 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs)
852 ohci_intr(sc);
853 }
854
855 usbd_status
856 ohci_device_request(reqh)
857 usbd_request_handle reqh;
858 {
859 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
860 usb_device_request_t *req = &reqh->request;
861 usbd_device_handle dev = opipe->pipe.device;
862 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
863 int addr = dev->address;
864 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail;
865 ohci_soft_ed_t *sed;
866 usb_dma_t *dmap;
867 int isread;
868 int len;
869 usbd_status r;
870 int s;
871
872 isread = req->bmRequestType & UT_READ;
873 len = UGETW(req->wLength);
874
875 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
876 req->bmRequestType, req->bRequest, UGETW(req->wValue),
877 UGETW(req->wIndex), len, addr,
878 opipe->pipe.endpoint->edesc->bEndpointAddress));
879
880 setup = opipe->tail;
881 stat = ohci_alloc_std(sc);
882 if (!stat) {
883 r = USBD_NOMEM;
884 goto bad1;
885 }
886 tail = ohci_alloc_std(sc);
887 if (!tail) {
888 r = USBD_NOMEM;
889 goto bad2;
890 }
891 tail->reqh = 0;
892
893 sed = opipe->sed;
894 dmap = &opipe->u.ctl.datadma;
895 opipe->u.ctl.length = len;
896
897 /* Update device address and length since they may have changed. */
898 /* XXX This only needs to be done once, but it's too early in open. */
899 sed->ed->ed_flags =
900 (sed->ed->ed_flags & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
901 OHCI_ED_SET_FA(addr) |
902 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize));
903
904 /* Set up data transaction */
905 if (len != 0) {
906 xfer = ohci_alloc_std(sc);
907 if (!xfer) {
908 r = USBD_NOMEM;
909 goto bad3;
910 }
911 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
912 if (r != USBD_NORMAL_COMPLETION)
913 goto bad4;
914 xfer->td->td_flags =
915 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
916 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR;
917 xfer->td->td_cbp = DMAADDR(dmap);
918 xfer->nexttd = stat;
919 xfer->td->td_nexttd = stat->physaddr;
920 xfer->td->td_be = xfer->td->td_cbp + len - 1;
921 xfer->len = len;
922 xfer->reqh = reqh;
923
924 next = xfer;
925 } else
926 next = stat;
927
928 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req);
929 if (!isread && len != 0)
930 memcpy(KERNADDR(dmap), reqh->buffer, len);
931
932 setup->td->td_flags = OHCI_TD_SETUP | OHCI_TD_NOCC |
933 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR;
934 setup->td->td_cbp = DMAADDR(&opipe->u.ctl.reqdma);
935 setup->nexttd = next;
936 setup->td->td_nexttd = next->physaddr;
937 setup->td->td_be = setup->td->td_cbp + sizeof *req - 1;
938 setup->len = 0; /* XXX The number of byte we count */
939 setup->reqh = reqh;
940
941 stat->td->td_flags =
942 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC |
943 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1);
944 stat->td->td_cbp = 0;
945 stat->nexttd = tail;
946 stat->td->td_nexttd = tail->physaddr;
947 stat->td->td_be = 0;
948 stat->len = 0;
949 stat->reqh = reqh;
950
951 reqh->actlen = 0;
952 reqh->hcpriv = stat;
953
954 #if USB_DEBUG
955 if (ohcidebug > 5) {
956 printf("ohci_device_request:\n");
957 ohci_dump_ed(sed);
958 ohci_dump_tds(setup);
959 }
960 #endif
961
962 /* Insert ED in schedule */
963 s = splusb();
964 ohci_hash_add_td(sc, setup);
965 if (len != 0)
966 ohci_hash_add_td(sc, xfer);
967 ohci_hash_add_td(sc, stat);
968 sed->ed->ed_tailp = tail->physaddr;
969 opipe->tail = tail;
970 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
971 if (reqh->timeout && !sc->sc_bus.use_polling)
972 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
973 splx(s);
974
975 #if USB_DEBUG
976 if (ohcidebug > 5) {
977 delay(5000);
978 printf("ohci_device_request: status=%x\n",
979 OREAD4(sc, OHCI_COMMAND_STATUS));
980 ohci_dump_ed(sed);
981 ohci_dump_tds(setup);
982 }
983 #endif
984
985 return (USBD_NORMAL_COMPLETION);
986
987 bad4:
988 ohci_free_std(sc, xfer);
989 bad3:
990 ohci_free_std(sc, tail);
991 bad2:
992 ohci_free_std(sc, stat);
993 bad1:
994 return (r);
995 }
996
997 /*
998 * Add an ED to the schedule. Called at splusb().
999 */
1000 void
1001 ohci_add_ed(sed, head)
1002 ohci_soft_ed_t *sed;
1003 ohci_soft_ed_t *head;
1004 {
1005 sed->next = head->next;
1006 sed->ed->ed_nexted = head->ed->ed_nexted;
1007 head->next = sed;
1008 head->ed->ed_nexted = sed->physaddr;
1009 }
1010
1011 /*
1012 * Remove an ED from the schedule. Called at splusb().
1013 */
1014 void
1015 ohci_rem_ed(sed, head)
1016 ohci_soft_ed_t *sed;
1017 ohci_soft_ed_t *head;
1018 {
1019 ohci_soft_ed_t *p;
1020
1021 /* XXX */
1022 for (p = head; p && p->next != sed; p = p->next)
1023 ;
1024 if (!p)
1025 panic("ohci_rem_ed: ED not found\n");
1026 p->next = sed->next;
1027 p->ed->ed_nexted = sed->ed->ed_nexted;
1028 }
1029
1030 /*
1031 * When a transfer is completed the TD is added to the done queue by
1032 * the host controller. This queue is the processed by software.
1033 * Unfortunately the queue contains the physical address of the TD
1034 * and we have no simple way to translate this back to a kernel address.
1035 * To make the translation possible (and fast) we use a hash table of
1036 * TDs currently in the schedule. The physical address is used as the
1037 * hash value.
1038 */
1039
1040 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1041 /* Called at splusb() */
1042 void
1043 ohci_hash_add_td(sc, std)
1044 ohci_softc_t *sc;
1045 ohci_soft_td_t *std;
1046 {
1047 int h = HASH(std->physaddr);
1048
1049 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1050 }
1051
1052 /* Called at splusb() */
1053 void
1054 ohci_hash_rem_td(sc, std)
1055 ohci_softc_t *sc;
1056 ohci_soft_td_t *std;
1057 {
1058 LIST_REMOVE(std, hnext);
1059 }
1060
1061 ohci_soft_td_t *
1062 ohci_hash_find_td(sc, a)
1063 ohci_softc_t *sc;
1064 ohci_physaddr_t a;
1065 {
1066 int h = HASH(a);
1067 ohci_soft_td_t *std;
1068
1069 for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1070 std != 0;
1071 std = LIST_NEXT(std, hnext))
1072 if (std->physaddr == a)
1073 return (std);
1074 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a);
1075 }
1076
1077 void
1078 ohci_timeout(addr)
1079 void *addr;
1080 {
1081 #if 0
1082 usbd_request_handle *reqh = addr;
1083 int s;
1084
1085 DPRINTF(("ohci_timeout: reqh=%p\n", reqh));
1086 s = splusb();
1087 /* XXX need to inactivate TD before calling interrupt routine */
1088 ohci_XXX_done(reqh);
1089 splx(s);
1090 #endif
1091 }
1092
1093 #ifdef USB_DEBUG
1094 void
1095 ohci_dump_tds(std)
1096 ohci_soft_td_t *std;
1097 {
1098 for (; std; std = std->nexttd)
1099 ohci_dump_td(std);
1100 }
1101
1102 void
1103 ohci_dump_td(std)
1104 ohci_soft_td_t *std;
1105 {
1106 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n",
1107 std, (u_long)std->physaddr,
1108 (u_long)std->td->td_flags,
1109 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
1110 OHCI_TD_GET_DI(std->td->td_flags),
1111 OHCI_TD_GET_EC(std->td->td_flags),
1112 OHCI_TD_GET_CC(std->td->td_flags),
1113 (u_long)std->td->td_cbp,
1114 (u_long)std->td->td_nexttd, (u_long)std->td->td_be);
1115 }
1116
1117 void
1118 ohci_dump_ed(sed)
1119 ohci_soft_ed_t *sed;
1120 {
1121 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx headp=%b nexted=0x%08lx\n",
1122 sed, (u_long)sed->physaddr,
1123 OHCI_ED_GET_FA(sed->ed->ed_flags),
1124 OHCI_ED_GET_EN(sed->ed->ed_flags),
1125 OHCI_ED_GET_MAXP(sed->ed->ed_flags),
1126 (u_long)sed->ed->ed_flags,
1127 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO",
1128 (u_long)sed->ed->ed_tailp,
1129 (u_long)sed->ed->ed_headp, "\20\1HALT\2CARRY",
1130 (u_long)sed->ed->ed_nexted);
1131 }
1132 #endif
1133
1134 usbd_status
1135 ohci_open(pipe)
1136 usbd_pipe_handle pipe;
1137 {
1138 usbd_device_handle dev = pipe->device;
1139 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1140 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1141 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1142 u_int8_t addr = dev->address;
1143 ohci_soft_ed_t *sed;
1144 ohci_soft_td_t *std;
1145 usbd_status r;
1146 int s;
1147
1148 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1149 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1150 if (addr == sc->sc_addr) {
1151 switch (ed->bEndpointAddress) {
1152 case USB_CONTROL_ENDPOINT:
1153 pipe->methods = &ohci_root_ctrl_methods;
1154 break;
1155 case UE_IN | OHCI_INTR_ENDPT:
1156 pipe->methods = &ohci_root_intr_methods;
1157 break;
1158 default:
1159 return (USBD_INVAL);
1160 }
1161 } else {
1162 sed = ohci_alloc_sed(sc);
1163 if (sed == 0)
1164 goto bad0;
1165 std = ohci_alloc_std(sc);
1166 if (std == 0)
1167 goto bad1;
1168 opipe->sed = sed;
1169 opipe->tail = std;
1170 sed->ed->ed_flags =
1171 OHCI_ED_SET_FA(addr) |
1172 OHCI_ED_SET_EN(ed->bEndpointAddress) |
1173 OHCI_ED_DIR_TD |
1174 (dev->lowspeed ? OHCI_ED_SPEED : 0) |
1175 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ?
1176 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) |
1177 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize));
1178 sed->ed->ed_headp = sed->ed->ed_tailp = std->physaddr;
1179
1180 switch (ed->bmAttributes & UE_XFERTYPE) {
1181 case UE_CONTROL:
1182 pipe->methods = &ohci_device_ctrl_methods;
1183 r = usb_allocmem(sc->sc_dmatag,
1184 sizeof(usb_device_request_t),
1185 0, &opipe->u.ctl.reqdma);
1186 if (r != USBD_NORMAL_COMPLETION)
1187 goto bad;
1188 s = splusb();
1189 ohci_add_ed(sed, sc->sc_ctrl_head);
1190 splx(s);
1191 break;
1192 case UE_INTERRUPT:
1193 pipe->methods = &ohci_device_intr_methods;
1194 return (ohci_device_setintr(sc, opipe, ed->bInterval));
1195 case UE_ISOCHRONOUS:
1196 printf("ohci_open: open iso unimplemented\n");
1197 return (USBD_XXX);
1198 case UE_BULK:
1199 pipe->methods = &ohci_device_bulk_methods;
1200 s = splusb();
1201 ohci_add_ed(sed, sc->sc_bulk_head);
1202 splx(s);
1203 break;
1204 }
1205 }
1206 return (USBD_NORMAL_COMPLETION);
1207
1208 bad:
1209 ohci_free_std(sc, std);
1210 bad1:
1211 ohci_free_sed(sc, sed);
1212 bad0:
1213 return (USBD_NOMEM);
1214
1215 }
1216
1217 /*
1218 * Data structures and routines to emulate the root hub.
1219 */
1220 usb_device_descriptor_t ohci_devd = {
1221 USB_DEVICE_DESCRIPTOR_SIZE,
1222 UDESC_DEVICE, /* type */
1223 {0x00, 0x01}, /* USB version */
1224 UCLASS_HUB, /* class */
1225 USUBCLASS_HUB, /* subclass */
1226 0, /* protocol */
1227 64, /* max packet */
1228 {0},{0},{0x00,0x01}, /* device id */
1229 1,2,0, /* string indicies */
1230 1 /* # of configurations */
1231 };
1232
1233 usb_config_descriptor_t ohci_confd = {
1234 USB_CONFIG_DESCRIPTOR_SIZE,
1235 UDESC_CONFIG,
1236 {USB_CONFIG_DESCRIPTOR_SIZE +
1237 USB_INTERFACE_DESCRIPTOR_SIZE +
1238 USB_ENDPOINT_DESCRIPTOR_SIZE},
1239 1,
1240 1,
1241 0,
1242 UC_SELF_POWERED,
1243 0 /* max power */
1244 };
1245
1246 usb_interface_descriptor_t ohci_ifcd = {
1247 USB_INTERFACE_DESCRIPTOR_SIZE,
1248 UDESC_INTERFACE,
1249 0,
1250 0,
1251 1,
1252 UCLASS_HUB,
1253 USUBCLASS_HUB,
1254 0,
1255 0
1256 };
1257
1258 usb_endpoint_descriptor_t ohci_endpd = {
1259 USB_ENDPOINT_DESCRIPTOR_SIZE,
1260 UDESC_ENDPOINT,
1261 UE_IN | OHCI_INTR_ENDPT,
1262 UE_INTERRUPT,
1263 {8, 0}, /* max packet */
1264 255
1265 };
1266
1267 usb_hub_descriptor_t ohci_hubd = {
1268 USB_HUB_DESCRIPTOR_SIZE,
1269 UDESC_HUB,
1270 0,
1271 {0,0},
1272 0,
1273 0,
1274 {0},
1275 {0},
1276 };
1277
1278 int
1279 ohci_str(p, l, s)
1280 usb_string_descriptor_t *p;
1281 int l;
1282 char *s;
1283 {
1284 int i;
1285
1286 if (l == 0)
1287 return (0);
1288 p->bLength = 2 * strlen(s) + 2;
1289 if (l == 1)
1290 return (1);
1291 p->bDescriptorType = UDESC_STRING;
1292 l -= 2;
1293 for (i = 0; s[i] && l > 1; i++, l -= 2)
1294 USETW2(p->bString[i], 0, s[i]);
1295 return (2*i+2);
1296 }
1297
1298 /*
1299 * Simulate a hardware hub by handling all the necessary requests.
1300 */
1301 usbd_status
1302 ohci_root_ctrl_transfer(reqh)
1303 usbd_request_handle reqh;
1304 {
1305 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1306 usb_device_request_t *req;
1307 void *buf;
1308 int port, i;
1309 int len, value, index, l, totlen = 0;
1310 usb_port_status_t ps;
1311 usb_hub_descriptor_t hubd;
1312 usbd_status r;
1313 u_int32_t v;
1314
1315 if (!reqh->isreq)
1316 /* XXX panic */
1317 return (USBD_INVAL);
1318 req = &reqh->request;
1319 buf = reqh->buffer;
1320
1321 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
1322 req->bmRequestType, req->bRequest));
1323
1324 len = UGETW(req->wLength);
1325 value = UGETW(req->wValue);
1326 index = UGETW(req->wIndex);
1327 #define C(x,y) ((x) | ((y) << 8))
1328 switch(C(req->bRequest, req->bmRequestType)) {
1329 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1330 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1331 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1332 /*
1333 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops
1334 * for the integrated root hub.
1335 */
1336 break;
1337 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1338 if (len > 0) {
1339 *(u_int8_t *)buf = sc->sc_conf;
1340 totlen = 1;
1341 }
1342 break;
1343 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1344 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
1345 switch(value >> 8) {
1346 case UDESC_DEVICE:
1347 if ((value & 0xff) != 0) {
1348 r = USBD_IOERROR;
1349 goto ret;
1350 }
1351 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1352 memcpy(buf, &ohci_devd, l);
1353 break;
1354 case UDESC_CONFIG:
1355 if ((value & 0xff) != 0) {
1356 r = USBD_IOERROR;
1357 goto ret;
1358 }
1359 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1360 memcpy(buf, &ohci_confd, l);
1361 buf = (char *)buf + l;
1362 len -= l;
1363 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1364 totlen += l;
1365 memcpy(buf, &ohci_ifcd, l);
1366 buf = (char *)buf + l;
1367 len -= l;
1368 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1369 totlen += l;
1370 memcpy(buf, &ohci_endpd, l);
1371 break;
1372 case UDESC_STRING:
1373 if (len == 0)
1374 break;
1375 *(u_int8_t *)buf = 0;
1376 totlen = 1;
1377 switch (value & 0xff) {
1378 case 1: /* Vendor */
1379 totlen = ohci_str(buf, len, sc->sc_vendor);
1380 break;
1381 case 2: /* Product */
1382 totlen = ohci_str(buf, len, "OHCI root hub");
1383 break;
1384 }
1385 break;
1386 default:
1387 r = USBD_IOERROR;
1388 goto ret;
1389 }
1390 break;
1391 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1392 if (len > 0) {
1393 *(u_int8_t *)buf = 0;
1394 totlen = 1;
1395 }
1396 break;
1397 case C(UR_GET_STATUS, UT_READ_DEVICE):
1398 if (len > 1) {
1399 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1400 totlen = 2;
1401 }
1402 break;
1403 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1404 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1405 if (len > 1) {
1406 USETW(((usb_status_t *)buf)->wStatus, 0);
1407 totlen = 2;
1408 }
1409 break;
1410 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1411 if (value >= USB_MAX_DEVICES) {
1412 r = USBD_IOERROR;
1413 goto ret;
1414 }
1415 sc->sc_addr = value;
1416 break;
1417 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1418 if (value != 0 && value != 1) {
1419 r = USBD_IOERROR;
1420 goto ret;
1421 }
1422 sc->sc_conf = value;
1423 break;
1424 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1425 break;
1426 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1427 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1428 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1429 r = USBD_IOERROR;
1430 goto ret;
1431 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1432 break;
1433 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1434 break;
1435 /* Hub requests */
1436 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1437 break;
1438 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1439 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n",
1440 index, value));
1441 if (index < 1 || index > sc->sc_noport) {
1442 r = USBD_IOERROR;
1443 goto ret;
1444 }
1445 port = OHCI_RH_PORT_STATUS(index);
1446 switch(value) {
1447 case UHF_PORT_ENABLE:
1448 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
1449 break;
1450 case UHF_PORT_SUSPEND:
1451 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
1452 break;
1453 case UHF_PORT_POWER:
1454 OWRITE4(sc, port, UPS_LOW_SPEED);
1455 break;
1456 case UHF_C_PORT_CONNECTION:
1457 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
1458 break;
1459 case UHF_C_PORT_ENABLE:
1460 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
1461 break;
1462 case UHF_C_PORT_SUSPEND:
1463 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
1464 break;
1465 case UHF_C_PORT_OVER_CURRENT:
1466 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
1467 break;
1468 case UHF_C_PORT_RESET:
1469 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
1470 break;
1471 default:
1472 r = USBD_IOERROR;
1473 goto ret;
1474 }
1475 switch(value) {
1476 case UHF_C_PORT_CONNECTION:
1477 case UHF_C_PORT_ENABLE:
1478 case UHF_C_PORT_SUSPEND:
1479 case UHF_C_PORT_OVER_CURRENT:
1480 case UHF_C_PORT_RESET:
1481 /* Enable RHSC interrupt if condition is cleared. */
1482 if ((OREAD4(sc, port) >> 16) == 0)
1483 ohci_rhsc_able(sc, 1);
1484 break;
1485 default:
1486 break;
1487 }
1488 break;
1489 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1490 if (value != 0) {
1491 r = USBD_IOERROR;
1492 goto ret;
1493 }
1494 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
1495 hubd = ohci_hubd;
1496 hubd.bNbrPorts = sc->sc_noport;
1497 USETW(hubd.bHubCharacteristics,
1498 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
1499 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
1500 /* XXX overcurrent */
1501 );
1502 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
1503 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
1504 if (sc->sc_noport < 8) {
1505 hubd.DeviceRemovable[0] = (u_int8_t)v;
1506 hubd.PortPowerCtrlMask[0] = (u_int8_t)(v >> 16);
1507 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE;
1508 } else {
1509 hubd.DeviceRemovable[0] = (u_int8_t)v;
1510 hubd.DeviceRemovable[1] = (u_int8_t)(v>>8);
1511 hubd.PortPowerCtrlMask[1] = (u_int8_t)(v >> 16);
1512 hubd.PortPowerCtrlMask[2] = (u_int8_t)(v >> 24);
1513 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + 2;
1514 }
1515 l = min(len, hubd.bDescLength);
1516 totlen = l;
1517 memcpy(buf, &hubd, l);
1518 break;
1519 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1520 if (len != 4) {
1521 r = USBD_IOERROR;
1522 goto ret;
1523 }
1524 memset(buf, 0, len); /* ? XXX */
1525 totlen = len;
1526 break;
1527 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1528 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
1529 index));
1530 if (index < 1 || index > sc->sc_noport) {
1531 r = USBD_IOERROR;
1532 goto ret;
1533 }
1534 if (len != 4) {
1535 r = USBD_IOERROR;
1536 goto ret;
1537 }
1538 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
1539 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
1540 v));
1541 USETW(ps.wPortStatus, v);
1542 USETW(ps.wPortChange, v >> 16);
1543 l = min(len, sizeof ps);
1544 memcpy(buf, &ps, l);
1545 totlen = l;
1546 break;
1547 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1548 r = USBD_IOERROR;
1549 goto ret;
1550 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1551 break;
1552 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1553 if (index < 1 || index > sc->sc_noport) {
1554 r = USBD_IOERROR;
1555 goto ret;
1556 }
1557 port = OHCI_RH_PORT_STATUS(index);
1558 switch(value) {
1559 case UHF_PORT_ENABLE:
1560 OWRITE4(sc, port, UPS_PORT_ENABLED);
1561 break;
1562 case UHF_PORT_SUSPEND:
1563 OWRITE4(sc, port, UPS_SUSPEND);
1564 break;
1565 case UHF_PORT_RESET:
1566 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", index));
1567 OWRITE4(sc, port, UPS_RESET);
1568 for (i = 0; i < 10; i++) {
1569 usbd_delay_ms(&sc->sc_bus, 10);
1570 if ((OREAD4(sc, port) & UPS_RESET) == 0)
1571 break;
1572 }
1573 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
1574 index, OREAD4(sc, port)));
1575 break;
1576 case UHF_PORT_POWER:
1577 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power %d\n", index));
1578 OWRITE4(sc, port, UPS_PORT_POWER);
1579 break;
1580 default:
1581 r = USBD_IOERROR;
1582 goto ret;
1583 }
1584 break;
1585 default:
1586 r = USBD_IOERROR;
1587 goto ret;
1588 }
1589 reqh->actlen = totlen;
1590 r = USBD_NORMAL_COMPLETION;
1591 ret:
1592 reqh->status = r;
1593 reqh->xfercb(reqh);
1594 return (USBD_IN_PROGRESS);
1595 }
1596
1597 /* Abort a root control request. */
1598 void
1599 ohci_root_ctrl_abort(reqh)
1600 usbd_request_handle reqh;
1601 {
1602 /* Nothing to do, all transfers are synchronous. */
1603 }
1604
1605 /* Close the root pipe. */
1606 void
1607 ohci_root_ctrl_close(pipe)
1608 usbd_pipe_handle pipe;
1609 {
1610 DPRINTF(("ohci_root_ctrl_close\n"));
1611 }
1612
1613 usbd_status
1614 ohci_root_intr_transfer(reqh)
1615 usbd_request_handle reqh;
1616 {
1617 usbd_pipe_handle pipe = reqh->pipe;
1618 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1619 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe;
1620 usb_dma_t *dmap;
1621 usbd_status r;
1622 int len;
1623
1624 len = reqh->length;
1625 dmap = &upipe->u.intr.datadma;
1626 if (len == 0)
1627 return (USBD_INVAL); /* XXX should it be? */
1628
1629 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1630 if (r != USBD_NORMAL_COMPLETION)
1631 return (r);
1632 sc->sc_intrreqh = reqh;
1633
1634 return (USBD_IN_PROGRESS);
1635 }
1636
1637 /* Abort a root interrupt request. */
1638 void
1639 ohci_root_intr_abort(reqh)
1640 usbd_request_handle reqh;
1641 {
1642 /* No need to abort. */
1643 }
1644
1645 /* Close the root pipe. */
1646 void
1647 ohci_root_intr_close(pipe)
1648 usbd_pipe_handle pipe;
1649 {
1650 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1651 sc->sc_intrreqh = 0;
1652
1653 DPRINTF(("ohci_root_intr_close\n"));
1654 }
1655
1656 /************************/
1657
1658 usbd_status
1659 ohci_device_ctrl_transfer(reqh)
1660 usbd_request_handle reqh;
1661 {
1662 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1663 usbd_status r;
1664
1665 if (!reqh->isreq) {
1666 /* XXX panic */
1667 printf("ohci_device_ctrl_transfer: not a request\n");
1668 return (USBD_INVAL);
1669 }
1670
1671 r = ohci_device_request(reqh);
1672 if (r != USBD_NORMAL_COMPLETION)
1673 return (r);
1674
1675 if (sc->sc_bus.use_polling)
1676 ohci_waitintr(sc, reqh);
1677 return (USBD_IN_PROGRESS);
1678 }
1679
1680 /* Abort a device control request. */
1681 void
1682 ohci_device_ctrl_abort(reqh)
1683 usbd_request_handle reqh;
1684 {
1685 /* XXX inactivate */
1686 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1687 /* XXX call done */
1688 }
1689
1690 /* Close a device control pipe. */
1691 void
1692 ohci_device_ctrl_close(pipe)
1693 usbd_pipe_handle pipe;
1694 {
1695 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1696 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1697 ohci_soft_ed_t *sed = opipe->sed;
1698 int s;
1699
1700 s = splusb();
1701 sed->ed->ed_flags |= OHCI_ED_SKIP;
1702 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1703 usbd_delay_ms(&sc->sc_bus, 2);
1704 ohci_rem_ed(sed, sc->sc_ctrl_head);
1705 splx(s);
1706 ohci_free_std(sc, opipe->tail);
1707 ohci_free_sed(sc, opipe->sed);
1708 /* XXX free other resources */
1709 }
1710
1711 /************************/
1712
1713 usbd_status
1714 ohci_device_bulk_transfer(reqh)
1715 usbd_request_handle reqh;
1716 {
1717 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1718 usbd_device_handle dev = opipe->pipe.device;
1719 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1720 int addr = dev->address;
1721 ohci_soft_td_t *xfer, *tail;
1722 ohci_soft_ed_t *sed;
1723 usb_dma_t *dmap;
1724 usbd_status r;
1725 int s, len, isread;
1726
1727 if (reqh->isreq) {
1728 /* XXX panic */
1729 printf("ohci_device_bulk_transfer: a request\n");
1730 return (USBD_INVAL);
1731 }
1732
1733 len = reqh->length;
1734 dmap = &opipe->u.bulk.datadma;
1735 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN;
1736 sed = opipe->sed;
1737
1738 opipe->u.bulk.length = len;
1739
1740 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1741 if (r != USBD_NORMAL_COMPLETION)
1742 goto ret1;
1743
1744 tail = ohci_alloc_std(sc);
1745 if (!tail) {
1746 r = USBD_NOMEM;
1747 goto ret2;
1748 }
1749 tail->reqh = 0;
1750
1751 /* Update device address */
1752 sed->ed->ed_flags =
1753 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) |
1754 OHCI_ED_SET_FA(addr);
1755
1756 /* Set up data transaction */
1757 xfer = opipe->tail;
1758 xfer->td->td_flags =
1759 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1760 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
1761 xfer->td->td_cbp = DMAADDR(dmap);
1762 xfer->nexttd = tail;
1763 xfer->td->td_nexttd = tail->physaddr;
1764 xfer->td->td_be = xfer->td->td_cbp + len - 1;
1765 xfer->len = len;
1766 xfer->reqh = reqh;
1767
1768 reqh->actlen = 0;
1769 reqh->hcpriv = xfer;
1770
1771 if (!isread)
1772 memcpy(KERNADDR(dmap), reqh->buffer, len);
1773
1774 /* Insert ED in schedule */
1775 s = splusb();
1776 ohci_hash_add_td(sc, xfer);
1777 sed->ed->ed_tailp = tail->physaddr;
1778 opipe->tail = tail;
1779 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
1780 if (reqh->timeout && !sc->sc_bus.use_polling)
1781 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
1782 splx(s);
1783
1784 return (USBD_IN_PROGRESS);
1785
1786 ret2:
1787 usb_freemem(sc->sc_dmatag, dmap);
1788 ret1:
1789 return (r);
1790 }
1791
1792 /* Abort a device bulk request. */
1793 void
1794 ohci_device_bulk_abort(reqh)
1795 usbd_request_handle reqh;
1796 {
1797 #if 0
1798 sed->ed->ed_flags |= OHCI_ED_SKIP;
1799 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1800 usbd_delay_ms(reqh->pipe->device->bus, 2);
1801 #endif
1802 /* XXX inactivate */
1803 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1804 /* XXX call done */
1805 }
1806
1807 /* Close a device bulk pipe. */
1808 void
1809 ohci_device_bulk_close(pipe)
1810 usbd_pipe_handle pipe;
1811 {
1812 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1813 usbd_device_handle dev = opipe->pipe.device;
1814 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1815 int s;
1816
1817 s = splusb();
1818 ohci_rem_ed(opipe->sed, sc->sc_bulk_head);
1819 splx(s);
1820 ohci_free_std(sc, opipe->tail);
1821 ohci_free_sed(sc, opipe->sed);
1822 /* XXX free other resources */
1823 }
1824
1825 /************************/
1826
1827 usbd_status
1828 ohci_device_intr_transfer(reqh)
1829 usbd_request_handle reqh;
1830 {
1831 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1832 usbd_device_handle dev = opipe->pipe.device;
1833 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1834 ohci_soft_ed_t *sed = opipe->sed;
1835 ohci_soft_td_t *xfer, *tail;
1836 usb_dma_t *dmap;
1837 usbd_status r;
1838 int len;
1839 int s;
1840
1841 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d priv=%p\n",
1842 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv));
1843
1844 if (reqh->isreq)
1845 panic("ohci_device_intr_transfer: a request\n");
1846
1847 len = reqh->length;
1848 dmap = &opipe->u.intr.datadma;
1849 if (len == 0)
1850 return (USBD_INVAL); /* XXX should it be? */
1851
1852 xfer = opipe->tail;
1853 tail = ohci_alloc_std(sc);
1854 if (!tail) {
1855 r = USBD_NOMEM;
1856 goto ret1;
1857 }
1858 tail->reqh = 0;
1859
1860 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1861 if (r != USBD_NORMAL_COMPLETION)
1862 goto ret2;
1863
1864 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC |
1865 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
1866 xfer->td->td_cbp = DMAADDR(dmap);
1867 xfer->nexttd = tail;
1868 xfer->td->td_nexttd = tail->physaddr;
1869 xfer->td->td_be = xfer->td->td_cbp + len - 1;
1870 xfer->len = len;
1871 xfer->reqh = reqh;
1872
1873 reqh->actlen = 0;
1874 reqh->hcpriv = xfer;
1875
1876 #if USB_DEBUG
1877 if (ohcidebug > 5) {
1878 printf("ohci_device_intr_transfer:\n");
1879 ohci_dump_ed(sed);
1880 ohci_dump_tds(xfer);
1881 }
1882 #endif
1883
1884 /* Insert ED in schedule */
1885 s = splusb();
1886 ohci_hash_add_td(sc, xfer);
1887 sed->ed->ed_tailp = tail->physaddr;
1888 opipe->tail = tail;
1889 #if 0
1890 if (reqh->timeout && !sc->sc_bus.use_polling)
1891 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
1892 #endif
1893 sed->ed->ed_flags &= ~OHCI_ED_SKIP;
1894 splx(s);
1895
1896 #ifdef USB_DEBUG
1897 if (ohcidebug > 5) {
1898 delay(5000);
1899 printf("ohci_device_intr_transfer: status=%x\n",
1900 OREAD4(sc, OHCI_COMMAND_STATUS));
1901 ohci_dump_ed(sed);
1902 ohci_dump_tds(xfer);
1903 }
1904 #endif
1905
1906 return (USBD_IN_PROGRESS);
1907
1908 ret2:
1909 ohci_free_std(sc, xfer);
1910 ret1:
1911 return (r);
1912 }
1913
1914 /* Abort a device control request. */
1915 void
1916 ohci_device_intr_abort(reqh)
1917 usbd_request_handle reqh;
1918 {
1919 /* XXX inactivate */
1920 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1921 if (reqh->pipe->intrreqh == reqh) {
1922 DPRINTF(("ohci_device_intr_abort: remove\n"));
1923 reqh->pipe->intrreqh = 0;
1924 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh);
1925 }
1926 }
1927
1928 /* Close a device interrupt pipe. */
1929 void
1930 ohci_device_intr_close(pipe)
1931 usbd_pipe_handle pipe;
1932 {
1933 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1934 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1935 int nslots = opipe->u.intr.nslots;
1936 int pos = opipe->u.intr.pos;
1937 int j;
1938 ohci_soft_ed_t *p, *sed = opipe->sed;
1939 int s;
1940
1941 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
1942 pipe, nslots, pos));
1943 s = splusb();
1944 sed->ed->ed_flags |= OHCI_ED_SKIP;
1945 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1946 usbd_delay_ms(&sc->sc_bus, 2);
1947
1948 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
1949 ;
1950 if (!p)
1951 panic("ohci_device_intr_close: ED not found\n");
1952 p->next = sed->next;
1953 p->ed->ed_nexted = sed->ed->ed_nexted;
1954 splx(s);
1955
1956 for (j = 0; j < nslots; j++)
1957 --sc->sc_bws[pos * nslots + j];
1958
1959 ohci_free_std(sc, opipe->tail);
1960 ohci_free_sed(sc, opipe->sed);
1961 /* XXX free other resources */
1962 }
1963
1964 usbd_status
1965 ohci_device_setintr(sc, opipe, ival)
1966 ohci_softc_t *sc;
1967 struct ohci_pipe *opipe;
1968 int ival;
1969 {
1970 int i, j, s, best;
1971 u_int npoll, slow, shigh, nslots;
1972 u_int bestbw, bw;
1973 ohci_soft_ed_t *hsed, *sed = opipe->sed;
1974
1975 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
1976 if (ival == 0) {
1977 printf("ohci_setintr: 0 interval\n");
1978 return (USBD_INVAL);
1979 }
1980
1981 npoll = OHCI_NO_INTRS;
1982 while (npoll > ival)
1983 npoll /= 2;
1984 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
1985
1986 /*
1987 * We now know which level in the tree the ED must go into.
1988 * Figure out which slot has most bandwidth left over.
1989 * Slots to examine:
1990 * npoll
1991 * 1 0
1992 * 2 1 2
1993 * 4 3 4 5 6
1994 * 8 7 8 9 10 11 12 13 14
1995 * N (N-1) .. (N-1+N-1)
1996 */
1997 slow = npoll-1;
1998 shigh = slow + npoll;
1999 nslots = OHCI_NO_INTRS / npoll;
2000 for (best = i = slow, bestbw = ~0; i < shigh; i++) {
2001 bw = 0;
2002 for (j = 0; j < nslots; j++)
2003 bw += sc->sc_bws[i * nslots + j];
2004 if (bw < bestbw) {
2005 best = i;
2006 bestbw = bw;
2007 }
2008 }
2009 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
2010 best, slow, shigh, bestbw));
2011
2012 s = splusb();
2013 hsed = sc->sc_eds[best];
2014 sed->next = hsed->next;
2015 sed->ed->ed_nexted = hsed->ed->ed_nexted;
2016 hsed->next = sed;
2017 hsed->ed->ed_nexted = sed->physaddr;
2018 splx(s);
2019
2020 for (j = 0; j < nslots; j++)
2021 ++sc->sc_bws[best * nslots + j];
2022 opipe->u.intr.nslots = nslots;
2023 opipe->u.intr.pos = best;
2024
2025 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
2026 return (USBD_NORMAL_COMPLETION);
2027 }
2028
2029