ohci.c revision 1.11 1 /* $NetBSD: ohci.c,v 1.11 1998/11/25 22:32:04 augustss Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (augustss (at) carlstedt.se) at
9 * Carlstedt Research & Technology.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * USB Open Host Controller driver.
42 *
43 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf
44 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/device.h>
52 #include <sys/proc.h>
53 #include <sys/queue.h>
54 #include <sys/select.h>
55
56 #include <machine/bus.h>
57
58 #include <dev/usb/usb.h>
59 #include <dev/usb/usbdi.h>
60 #include <dev/usb/usbdivar.h>
61 #include <dev/usb/usb_quirks.h>
62 #include <dev/usb/usb_mem.h>
63
64 #include <dev/usb/ohcireg.h>
65 #include <dev/usb/ohcivar.h>
66
67 int ohcidebug = 0;
68
69 struct ohci_pipe;
70
71 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *));
72 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *));
73
74 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *));
75 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *));
76
77 usbd_status ohci_open __P((usbd_pipe_handle));
78 void ohci_poll __P((struct usbd_bus *));
79 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle));
80 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle));
81 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t));
82 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle));
83 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle));
84 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle));
85
86 usbd_status ohci_device_request __P((usbd_request_handle reqh));
87 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
88 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
89 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *));
90 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *));
91 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t));
92
93 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle));
94 void ohci_root_ctrl_abort __P((usbd_request_handle));
95 void ohci_root_ctrl_close __P((usbd_pipe_handle));
96
97 usbd_status ohci_root_intr_transfer __P((usbd_request_handle));
98 void ohci_root_intr_abort __P((usbd_request_handle));
99 void ohci_root_intr_close __P((usbd_pipe_handle));
100
101 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle));
102 void ohci_device_ctrl_abort __P((usbd_request_handle));
103 void ohci_device_ctrl_close __P((usbd_pipe_handle));
104
105 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle));
106 void ohci_device_bulk_abort __P((usbd_request_handle));
107 void ohci_device_bulk_close __P((usbd_pipe_handle));
108
109 usbd_status ohci_device_intr_transfer __P((usbd_request_handle));
110 void ohci_device_intr_abort __P((usbd_request_handle));
111 void ohci_device_intr_close __P((usbd_pipe_handle));
112 usbd_status ohci_device_setintr __P((ohci_softc_t *sc,
113 struct ohci_pipe *pipe, int ival));
114
115 int ohci_str __P((usb_string_descriptor_t *, int, char *));
116
117 void ohci_timeout __P((void *));
118 void ohci_rhsc_able __P((ohci_softc_t *, int));
119
120 #ifdef USB_DEBUG
121 ohci_softc_t *thesc;
122 void ohci_dumpregs __P((ohci_softc_t *));
123 void ohci_dump_tds __P((ohci_soft_td_t *));
124 void ohci_dump_td __P((ohci_soft_td_t *));
125 void ohci_dump_ed __P((ohci_soft_ed_t *));
126 #endif
127
128 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x))
129 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r))
130 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r))
131
132 /* Reverse the bits in a value 0 .. 31 */
133 static u_int8_t revbits[OHCI_NO_INTRS] =
134 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
135 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
136 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
137 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
138
139 struct ohci_pipe {
140 struct usbd_pipe pipe;
141 ohci_soft_ed_t *sed;
142 ohci_soft_td_t *tail;
143 /* Info needed for different pipe kinds. */
144 union {
145 /* Control pipe */
146 struct {
147 usb_dma_t datadma;
148 usb_dma_t reqdma;
149 u_int length;
150 ohci_soft_td_t *setup, *xfer, *stat;
151 } ctl;
152 /* Interrupt pipe */
153 struct {
154 usb_dma_t datadma;
155 int nslots;
156 int pos;
157 } intr;
158 /* Bulk pipe */
159 struct {
160 usb_dma_t datadma;
161 u_int length;
162 } bulk;
163 } u;
164 };
165
166 #define OHCI_INTR_ENDPT 1
167
168 struct usbd_methods ohci_root_ctrl_methods = {
169 ohci_root_ctrl_transfer,
170 ohci_root_ctrl_abort,
171 ohci_root_ctrl_close,
172 0,
173 };
174
175 struct usbd_methods ohci_root_intr_methods = {
176 ohci_root_intr_transfer,
177 ohci_root_intr_abort,
178 ohci_root_intr_close,
179 0,
180 };
181
182 struct usbd_methods ohci_device_ctrl_methods = {
183 ohci_device_ctrl_transfer,
184 ohci_device_ctrl_abort,
185 ohci_device_ctrl_close,
186 0,
187 };
188
189 struct usbd_methods ohci_device_intr_methods = {
190 ohci_device_intr_transfer,
191 ohci_device_intr_abort,
192 ohci_device_intr_close,
193 };
194
195 struct usbd_methods ohci_device_bulk_methods = {
196 ohci_device_bulk_transfer,
197 ohci_device_bulk_abort,
198 ohci_device_bulk_close,
199 0,
200 };
201
202 ohci_soft_ed_t *
203 ohci_alloc_sed(sc)
204 ohci_softc_t *sc;
205 {
206 ohci_soft_ed_t *sed;
207 usbd_status r;
208 int i, offs;
209 usb_dma_t dma;
210
211 if (!sc->sc_freeeds) {
212 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
213 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK,
214 M_USBDEV, M_NOWAIT);
215 if (!sed)
216 return 0;
217 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK,
218 OHCI_ED_ALIGN, &dma);
219 if (r != USBD_NORMAL_COMPLETION) {
220 free(sed, M_USBDEV);
221 return 0;
222 }
223 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) {
224 offs = i * OHCI_ED_SIZE;
225 sed->physaddr = DMAADDR(&dma) + offs;
226 sed->ed = (ohci_ed_t *)
227 ((char *)KERNADDR(&dma) + offs);
228 sed->next = sc->sc_freeeds;
229 sc->sc_freeeds = sed;
230 }
231 }
232 sed = sc->sc_freeeds;
233 sc->sc_freeeds = sed->next;
234 memset(sed->ed, 0, OHCI_ED_SIZE);
235 sed->next = 0;
236 return sed;
237 }
238
239 void
240 ohci_free_sed(sc, sed)
241 ohci_softc_t *sc;
242 ohci_soft_ed_t *sed;
243 {
244 sed->next = sc->sc_freeeds;
245 sc->sc_freeeds = sed;
246 }
247
248 ohci_soft_td_t *
249 ohci_alloc_std(sc)
250 ohci_softc_t *sc;
251 {
252 ohci_soft_td_t *std;
253 usbd_status r;
254 int i, offs;
255 usb_dma_t dma;
256
257 if (!sc->sc_freetds) {
258 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
259 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK,
260 M_USBDEV, M_NOWAIT);
261 if (!std)
262 return 0;
263 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK,
264 OHCI_TD_ALIGN, &dma);
265 if (r != USBD_NORMAL_COMPLETION) {
266 free(std, M_USBDEV);
267 return 0;
268 }
269 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) {
270 offs = i * OHCI_TD_SIZE;
271 std->physaddr = DMAADDR(&dma) + offs;
272 std->td = (ohci_td_t *)
273 ((char *)KERNADDR(&dma) + offs);
274 std->nexttd = sc->sc_freetds;
275 sc->sc_freetds = std;
276 }
277 }
278 std = sc->sc_freetds;
279 sc->sc_freetds = std->nexttd;
280 memset(std->td, 0, OHCI_TD_SIZE);
281 std->nexttd = 0;
282 return (std);
283 }
284
285 void
286 ohci_free_std(sc, std)
287 ohci_softc_t *sc;
288 ohci_soft_td_t *std;
289 {
290 std->nexttd = sc->sc_freetds;
291 sc->sc_freetds = std;
292 }
293
294 usbd_status
295 ohci_init(sc)
296 ohci_softc_t *sc;
297 {
298 ohci_soft_ed_t *sed, *psed;
299 usbd_status r;
300 int rev;
301 int i;
302 u_int32_t s, ctl, ival, hcr, fm, per;
303
304 DPRINTF(("ohci_init: start\n"));
305 rev = OREAD4(sc, OHCI_REVISION);
306 printf("%s: OHCI version %d.%d%s\n", sc->sc_bus.bdev.dv_xname,
307 OHCI_REV_HI(rev), OHCI_REV_LO(rev),
308 OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
309 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
310 printf("%s: unsupported OHCI revision\n",
311 sc->sc_bus.bdev.dv_xname);
312 return (USBD_INVAL);
313 }
314
315 for (i = 0; i < OHCI_HASH_SIZE; i++)
316 LIST_INIT(&sc->sc_hash_tds[i]);
317
318 /* Allocate the HCCA area. */
319 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE,
320 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
321 if (r != USBD_NORMAL_COMPLETION)
322 return (r);
323 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
324 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
325
326 sc->sc_eintrs = OHCI_NORMAL_INTRS;
327
328 sc->sc_ctrl_head = ohci_alloc_sed(sc);
329 if (!sc->sc_ctrl_head) {
330 r = USBD_NOMEM;
331 goto bad1;
332 }
333 sc->sc_ctrl_head->ed->ed_flags |= OHCI_ED_SKIP;
334 sc->sc_bulk_head = ohci_alloc_sed(sc);
335 if (!sc->sc_bulk_head) {
336 r = USBD_NOMEM;
337 goto bad2;
338 }
339 sc->sc_bulk_head->ed->ed_flags |= OHCI_ED_SKIP;
340
341 /* Allocate all the dummy EDs that make up the interrupt tree. */
342 for (i = 0; i < OHCI_NO_EDS; i++) {
343 sed = ohci_alloc_sed(sc);
344 if (!sed) {
345 while (--i >= 0)
346 ohci_free_sed(sc, sc->sc_eds[i]);
347 r = USBD_NOMEM;
348 goto bad3;
349 }
350 /* All ED fields are set to 0. */
351 sc->sc_eds[i] = sed;
352 sed->ed->ed_flags |= OHCI_ED_SKIP;
353 if (i != 0) {
354 psed = sc->sc_eds[(i-1) / 2];
355 sed->next = psed;
356 sed->ed->ed_nexted = psed->physaddr;
357 }
358 }
359 /*
360 * Fill HCCA interrupt table. The bit reversal is to get
361 * the tree set up properly to spread the interrupts.
362 */
363 for (i = 0; i < OHCI_NO_INTRS; i++)
364 sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
365 sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr;
366
367 /* Determine in what context we are running. */
368 ctl = OREAD4(sc, OHCI_CONTROL);
369 if (ctl & OHCI_IR) {
370 /* SMM active, request change */
371 DPRINTF(("ohci_init: SMM active, request owner change\n"));
372 s = OREAD4(sc, OHCI_COMMAND_STATUS);
373 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
374 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
375 delay(1000);
376 ctl = OREAD4(sc, OHCI_CONTROL);
377 }
378 if ((ctl & OHCI_IR) == 0) {
379 printf("%s: SMM does not respond, resetting\n",
380 sc->sc_bus.bdev.dv_xname);
381 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
382 goto reset;
383 }
384 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
385 /* BIOS started controller. */
386 DPRINTF(("ohci_init: BIOS active\n"));
387 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
388 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL);
389 delay(USB_RESUME_DELAY * 1000);
390 }
391 } else {
392 DPRINTF(("ohci_init: cold started\n"));
393 reset:
394 /* Controller was cold started. */
395 delay(USB_RESET_DELAY * 1000);
396 }
397
398 /* We now own the host controller and the bus has been reset. */
399 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
400
401 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
402 /* Nominal time for a reset is 10 us. */
403 for (i = 0; i < 10; i++) {
404 delay(10);
405 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
406 if (!hcr)
407 break;
408 }
409 if (hcr) {
410 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname);
411 r = USBD_IOERROR;
412 goto bad3;
413 }
414 #ifdef USB_DEBUG
415 thesc = sc;
416 if (ohcidebug > 15)
417 ohci_dumpregs(sc);
418 #endif
419
420 /* The controller is now in suspend state, we have 2ms to finish. */
421
422 /* Set up HC registers. */
423 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma));
424 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
425 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
426 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
427 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
428 ctl = OREAD4(sc, OHCI_CONTROL);
429 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
430 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
431 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
432 /* And finally start it! */
433 OWRITE4(sc, OHCI_CONTROL, ctl);
434
435 /*
436 * The controller is now OPERATIONAL. Set a some final
437 * registers that should be set earlier, but that the
438 * controller ignores when in the SUSPEND state.
439 */
440 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
441 fm |= OHCI_FSMPS(ival) | ival;
442 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
443 per = OHCI_PERIODIC(ival); /* 90% periodic */
444 OWRITE4(sc, OHCI_PERIODIC_START, per);
445
446 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
447
448 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
449 printf("%s: %d downstream port%s\n",
450 sc->sc_bus.bdev.dv_xname, sc->sc_noport,
451 sc->sc_noport != 1 ? "s" : "");
452
453 #ifdef USB_DEBUG
454 if (ohcidebug > 5)
455 ohci_dumpregs(sc);
456 #endif
457
458 /* Set up the bus struct. */
459 sc->sc_bus.open_pipe = ohci_open;
460 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
461 sc->sc_bus.do_poll = ohci_poll;
462
463 return (USBD_NORMAL_COMPLETION);
464
465 bad3:
466 ohci_free_sed(sc, sc->sc_ctrl_head);
467 bad2:
468 ohci_free_sed(sc, sc->sc_bulk_head);
469 bad1:
470 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma);
471 return (r);
472 }
473
474 #ifdef USB_DEBUG
475 void ohcidump(void);
476 void ohcidump(void) { ohci_dumpregs(thesc); }
477
478 void
479 ohci_dumpregs(sc)
480 ohci_softc_t *sc;
481 {
482 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
483 OREAD4(sc, OHCI_REVISION),
484 OREAD4(sc, OHCI_CONTROL),
485 OREAD4(sc, OHCI_COMMAND_STATUS));
486 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
487 OREAD4(sc, OHCI_INTERRUPT_STATUS),
488 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
489 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
490 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
491 OREAD4(sc, OHCI_HCCA),
492 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
493 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
494 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
495 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
496 OREAD4(sc, OHCI_BULK_HEAD_ED),
497 OREAD4(sc, OHCI_BULK_CURRENT_ED));
498 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
499 OREAD4(sc, OHCI_DONE_HEAD),
500 OREAD4(sc, OHCI_FM_INTERVAL),
501 OREAD4(sc, OHCI_FM_REMAINING));
502 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
503 OREAD4(sc, OHCI_FM_NUMBER),
504 OREAD4(sc, OHCI_PERIODIC_START),
505 OREAD4(sc, OHCI_LS_THRESHOLD));
506 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
507 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
508 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
509 OREAD4(sc, OHCI_RH_STATUS));
510 printf(" port1=0x%08x port2=0x%08x\n",
511 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
512 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
513 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
514 sc->sc_hcca->hcca_frame_number,
515 sc->sc_hcca->hcca_done_head);
516 }
517 #endif
518
519 int
520 ohci_intr(p)
521 void *p;
522 {
523 ohci_softc_t *sc = p;
524 u_int32_t intrs, eintrs;
525 ohci_physaddr_t done;
526
527 done = sc->sc_hcca->hcca_done_head;
528 if (done != 0) {
529 intrs = OHCI_WDH;
530 if (done & OHCI_DONE_INTRS)
531 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
532 } else
533 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
534 if (!intrs)
535 return (0);
536 intrs &= ~OHCI_MIE;
537 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */
538 eintrs = intrs & sc->sc_eintrs;
539 if (!eintrs)
540 return (0);
541
542 sc->sc_intrs++;
543 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n",
544 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
545 (u_int)eintrs));
546
547 if (eintrs & OHCI_SO) {
548 printf("%s: scheduling overrun\n", sc->sc_bus.bdev.dv_xname);
549 /* XXX do what */
550 intrs &= ~OHCI_SO;
551 }
552 if (eintrs & OHCI_WDH) {
553 ohci_process_done(sc, done &~ OHCI_DONE_INTRS);
554 sc->sc_hcca->hcca_done_head = 0;
555 intrs &= ~OHCI_WDH;
556 }
557 if (eintrs & OHCI_RD) {
558 /* XXX process resume detect */
559 }
560 if (eintrs & OHCI_UE) {
561 printf("%s: unrecoverable error, controller halted\n",
562 sc->sc_bus.bdev.dv_xname);
563 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
564 /* XXX what else */
565 }
566 if (eintrs & OHCI_RHSC) {
567 ohci_rhsc(sc, sc->sc_intrreqh);
568 intrs &= ~OHCI_RHSC;
569
570 /*
571 * Disable RHSC interrupt for now, because it will be
572 * on until the port has been reset.
573 */
574 ohci_rhsc_able(sc, 0);
575 }
576
577 /* Block unprocessed interrupts. XXX */
578 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs);
579 sc->sc_eintrs &= ~intrs;
580
581 return (1);
582 }
583
584 void
585 ohci_rhsc_able(sc, on)
586 ohci_softc_t *sc;
587 int on;
588 {
589 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on));
590 if (on) {
591 sc->sc_eintrs |= OHCI_RHSC;
592 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
593 } else {
594 sc->sc_eintrs &= ~OHCI_RHSC;
595 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
596 }
597 }
598
599 void
600 ohci_process_done(sc, done)
601 ohci_softc_t *sc;
602 ohci_physaddr_t done;
603 {
604 ohci_soft_td_t *std, *sdone;
605 usbd_request_handle reqh;
606 int len, cc;
607
608 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done));
609
610 /* Reverse the done list. */
611 for (sdone = 0; done; done = std->td->td_nexttd) {
612 std = ohci_hash_find_td(sc, done);
613 std->dnext = sdone;
614 sdone = std;
615 }
616
617 #ifdef USB_DEBUG
618 if (ohcidebug > 10) {
619 printf("ohci_process_done: TD done:\n");
620 ohci_dump_tds(sdone);
621 }
622 #endif
623
624 for (std = sdone; std; std = std->dnext) {
625 reqh = std->reqh;
626 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh));
627 cc = OHCI_TD_GET_CC(std->td->td_flags);
628 if (cc == OHCI_CC_NO_ERROR) {
629 if (std->td->td_cbp == 0)
630 len = std->len;
631 else
632 len = std->td->td_be - std->td->td_cbp + 1;
633 reqh->actlen += len;
634 if (reqh->hcpriv == std) {
635 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
636 case UE_CONTROL:
637 ohci_ctrl_done(sc, reqh);
638 break;
639 case UE_INTERRUPT:
640 ohci_intr_done(sc, reqh);
641 break;
642 case UE_BULK:
643 ohci_bulk_done(sc, reqh);
644 break;
645 case UE_ISOCHRONOUS:
646 printf("ohci_process_done: ISO done?\n");
647 break;
648 }
649 /* And finally execute callback. */
650 reqh->status = USBD_NORMAL_COMPLETION;
651 reqh->xfercb(reqh);
652 }
653 } else {
654 ohci_soft_td_t *p, *n;
655 struct ohci_pipe *opipe =
656 (struct ohci_pipe *)reqh->pipe;
657 DPRINTFN(-1,("ohci_process_done: error cc=%d\n",
658 OHCI_TD_GET_CC(std->td->td_flags)));
659 /*
660 * Endpoint is halted. First unlink all the TDs
661 * belonging to the failed transfer, and then restart
662 * the endpoint.
663 */
664 for (p = std->nexttd; p->reqh == reqh; p = n) {
665 n = p->nexttd;
666 ohci_hash_rem_td(sc, p);
667 ohci_free_std(sc, p);
668 }
669 opipe->sed->ed->ed_headp = p->physaddr;/* clear halt */
670 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
671
672 if (cc == OHCI_CC_STALL)
673 reqh->status = USBD_STALLED;
674 else
675 reqh->status = USBD_IOERROR;
676 reqh->xfercb(reqh);
677 }
678 ohci_hash_rem_td(sc, std);
679 ohci_free_std(sc, std);
680 }
681 }
682
683 void
684 ohci_ctrl_done(sc, reqh)
685 ohci_softc_t *sc;
686 usbd_request_handle reqh;
687 {
688 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
689 u_int len = opipe->u.ctl.length;
690 usb_dma_t *dma;
691
692 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh));
693
694 if (!reqh->isreq) {
695 panic("ohci_ctrl_done: not a request\n");
696 return;
697 }
698
699 if (len != 0) {
700 dma = &opipe->u.ctl.datadma;
701 if (reqh->request.bmRequestType & UT_READ)
702 memcpy(reqh->buffer, KERNADDR(dma), len);
703 usb_freemem(sc->sc_dmatag, dma);
704 }
705 }
706
707 void
708 ohci_intr_done(sc, reqh)
709 ohci_softc_t *sc;
710 usbd_request_handle reqh;
711 {
712 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
713 usb_dma_t *dma;
714 ohci_soft_ed_t *sed = opipe->sed;
715 ohci_soft_td_t *xfer, *tail;
716
717
718 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n",
719 reqh, reqh->actlen));
720
721 dma = &opipe->u.intr.datadma;
722 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
723
724 if (reqh->pipe->intrreqh == reqh) {
725 xfer = opipe->tail;
726 tail = ohci_alloc_std(sc); /* XXX should reuse TD */
727 if (!tail) {
728 reqh->status = USBD_NOMEM;
729 return;
730 }
731 tail->reqh = 0;
732
733 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC |
734 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
735 xfer->td->td_cbp = DMAADDR(dma);
736 xfer->nexttd = tail;
737 xfer->td->td_nexttd = tail->physaddr;
738 xfer->td->td_be = xfer->td->td_cbp + reqh->length - 1;
739 xfer->len = reqh->length;
740 xfer->reqh = reqh;
741
742 reqh->actlen = 0;
743 reqh->hcpriv = xfer;
744
745 ohci_hash_add_td(sc, xfer);
746 sed->ed->ed_tailp = tail->physaddr;
747 opipe->tail = tail;
748 } else {
749 usb_freemem(sc->sc_dmatag, dma);
750 }
751 }
752
753 void
754 ohci_bulk_done(sc, reqh)
755 ohci_softc_t *sc;
756 usbd_request_handle reqh;
757 {
758 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
759 usb_dma_t *dma;
760
761
762 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n",
763 reqh, reqh->actlen));
764
765 dma = &opipe->u.bulk.datadma;
766 if (reqh->request.bmRequestType & UT_READ)
767 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
768 usb_freemem(sc->sc_dmatag, dma);
769 }
770
771 void
772 ohci_rhsc(sc, reqh)
773 ohci_softc_t *sc;
774 usbd_request_handle reqh;
775 {
776 usbd_pipe_handle pipe;
777 struct ohci_pipe *opipe;
778 u_char *p;
779 int i, m;
780 int hstatus;
781
782 hstatus = OREAD4(sc, OHCI_RH_STATUS);
783 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n",
784 sc, reqh, hstatus));
785
786 if (reqh == 0) {
787 /* Just ignore the change. */
788 return;
789 }
790
791 pipe = reqh->pipe;
792 opipe = (struct ohci_pipe *)pipe;
793
794 p = KERNADDR(&opipe->u.intr.datadma);
795 m = min(sc->sc_noport, reqh->length * 8 - 1);
796 memset(p, 0, reqh->length);
797 for (i = 1; i <= m; i++) {
798 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
799 p[i/8] |= 1 << (i%8);
800 }
801 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
802 reqh->actlen = reqh->length;
803 reqh->status = USBD_NORMAL_COMPLETION;
804 reqh->xfercb(reqh);
805
806 if (reqh->pipe->intrreqh != reqh) {
807 sc->sc_intrreqh = 0;
808 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma);
809 }
810 }
811
812 /*
813 * Wait here until controller claims to have an interrupt.
814 * Then call ohci_intr and return. Use timeout to avoid waiting
815 * too long.
816 */
817 void
818 ohci_waitintr(sc, reqh)
819 ohci_softc_t *sc;
820 usbd_request_handle reqh;
821 {
822 int timo = reqh->timeout;
823 int usecs;
824 u_int32_t intrs;
825
826 reqh->status = USBD_IN_PROGRESS;
827 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
828 delay(1000);
829 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
830 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs));
831 #ifdef USB_DEBUG
832 if (ohcidebug > 15)
833 ohci_dumpregs(sc);
834 #endif
835 if (intrs) {
836 ohci_intr(sc);
837 if (reqh->status != USBD_IN_PROGRESS)
838 return;
839 }
840 }
841 DPRINTF(("ohci_waitintr: timeout\n"));
842 reqh->status = USBD_TIMEOUT;
843 reqh->xfercb(reqh);
844 }
845
846 void
847 ohci_poll(bus)
848 struct usbd_bus *bus;
849 {
850 ohci_softc_t *sc = (ohci_softc_t *)bus;
851
852 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs)
853 ohci_intr(sc);
854 }
855
856 usbd_status
857 ohci_device_request(reqh)
858 usbd_request_handle reqh;
859 {
860 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
861 usb_device_request_t *req = &reqh->request;
862 usbd_device_handle dev = opipe->pipe.device;
863 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
864 int addr = dev->address;
865 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail;
866 ohci_soft_ed_t *sed;
867 usb_dma_t *dmap;
868 int isread;
869 int len;
870 usbd_status r;
871 int s;
872
873 isread = req->bmRequestType & UT_READ;
874 len = UGETW(req->wLength);
875
876 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
877 req->bmRequestType, req->bRequest, UGETW(req->wValue),
878 UGETW(req->wIndex), len, addr,
879 opipe->pipe.endpoint->edesc->bEndpointAddress));
880
881 setup = opipe->tail;
882 stat = ohci_alloc_std(sc);
883 if (!stat) {
884 r = USBD_NOMEM;
885 goto bad1;
886 }
887 tail = ohci_alloc_std(sc);
888 if (!tail) {
889 r = USBD_NOMEM;
890 goto bad2;
891 }
892 tail->reqh = 0;
893
894 sed = opipe->sed;
895 dmap = &opipe->u.ctl.datadma;
896 opipe->u.ctl.length = len;
897
898 /* Update device address and length since they may have changed. */
899 /* XXX This only needs to be done once, but it's too early in open. */
900 sed->ed->ed_flags =
901 (sed->ed->ed_flags & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
902 OHCI_ED_SET_FA(addr) |
903 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize));
904
905 /* Set up data transaction */
906 if (len != 0) {
907 xfer = ohci_alloc_std(sc);
908 if (!xfer) {
909 r = USBD_NOMEM;
910 goto bad3;
911 }
912 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
913 if (r != USBD_NORMAL_COMPLETION)
914 goto bad4;
915 xfer->td->td_flags =
916 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
917 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR;
918 xfer->td->td_cbp = DMAADDR(dmap);
919 xfer->nexttd = stat;
920 xfer->td->td_nexttd = stat->physaddr;
921 xfer->td->td_be = xfer->td->td_cbp + len - 1;
922 xfer->len = len;
923 xfer->reqh = reqh;
924
925 next = xfer;
926 } else
927 next = stat;
928
929 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req);
930 if (!isread && len != 0)
931 memcpy(KERNADDR(dmap), reqh->buffer, len);
932
933 setup->td->td_flags = OHCI_TD_SETUP | OHCI_TD_NOCC |
934 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR;
935 setup->td->td_cbp = DMAADDR(&opipe->u.ctl.reqdma);
936 setup->nexttd = next;
937 setup->td->td_nexttd = next->physaddr;
938 setup->td->td_be = setup->td->td_cbp + sizeof *req - 1;
939 setup->len = 0; /* XXX The number of byte we count */
940 setup->reqh = reqh;
941
942 stat->td->td_flags =
943 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC |
944 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1);
945 stat->td->td_cbp = 0;
946 stat->nexttd = tail;
947 stat->td->td_nexttd = tail->physaddr;
948 stat->td->td_be = 0;
949 stat->len = 0;
950 stat->reqh = reqh;
951
952 reqh->actlen = 0;
953 reqh->hcpriv = stat;
954
955 #if USB_DEBUG
956 if (ohcidebug > 5) {
957 printf("ohci_device_request:\n");
958 ohci_dump_ed(sed);
959 ohci_dump_tds(setup);
960 }
961 #endif
962
963 /* Insert ED in schedule */
964 s = splusb();
965 ohci_hash_add_td(sc, setup);
966 if (len != 0)
967 ohci_hash_add_td(sc, xfer);
968 ohci_hash_add_td(sc, stat);
969 sed->ed->ed_tailp = tail->physaddr;
970 opipe->tail = tail;
971 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
972 if (reqh->timeout && !sc->sc_bus.use_polling)
973 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
974 splx(s);
975
976 #if USB_DEBUG
977 if (ohcidebug > 5) {
978 delay(5000);
979 printf("ohci_device_request: status=%x\n",
980 OREAD4(sc, OHCI_COMMAND_STATUS));
981 ohci_dump_ed(sed);
982 ohci_dump_tds(setup);
983 }
984 #endif
985
986 return (USBD_NORMAL_COMPLETION);
987
988 bad4:
989 ohci_free_std(sc, xfer);
990 bad3:
991 ohci_free_std(sc, tail);
992 bad2:
993 ohci_free_std(sc, stat);
994 bad1:
995 return (r);
996 }
997
998 /*
999 * Add an ED to the schedule. Called at splusb().
1000 */
1001 void
1002 ohci_add_ed(sed, head)
1003 ohci_soft_ed_t *sed;
1004 ohci_soft_ed_t *head;
1005 {
1006 sed->next = head->next;
1007 sed->ed->ed_nexted = head->ed->ed_nexted;
1008 head->next = sed;
1009 head->ed->ed_nexted = sed->physaddr;
1010 }
1011
1012 /*
1013 * Remove an ED from the schedule. Called at splusb().
1014 */
1015 void
1016 ohci_rem_ed(sed, head)
1017 ohci_soft_ed_t *sed;
1018 ohci_soft_ed_t *head;
1019 {
1020 ohci_soft_ed_t *p;
1021
1022 /* XXX */
1023 for (p = head; p && p->next != sed; p = p->next)
1024 ;
1025 if (!p)
1026 panic("ohci_rem_ed: ED not found\n");
1027 p->next = sed->next;
1028 p->ed->ed_nexted = sed->ed->ed_nexted;
1029 }
1030
1031 /*
1032 * When a transfer is completed the TD is added to the done queue by
1033 * the host controller. This queue is the processed by software.
1034 * Unfortunately the queue contains the physical address of the TD
1035 * and we have no simple way to translate this back to a kernel address.
1036 * To make the translation possible (and fast) we use a hash table of
1037 * TDs currently in the schedule. The physical address is used as the
1038 * hash value.
1039 */
1040
1041 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1042 /* Called at splusb() */
1043 void
1044 ohci_hash_add_td(sc, std)
1045 ohci_softc_t *sc;
1046 ohci_soft_td_t *std;
1047 {
1048 int h = HASH(std->physaddr);
1049
1050 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1051 }
1052
1053 /* Called at splusb() */
1054 void
1055 ohci_hash_rem_td(sc, std)
1056 ohci_softc_t *sc;
1057 ohci_soft_td_t *std;
1058 {
1059 LIST_REMOVE(std, hnext);
1060 }
1061
1062 ohci_soft_td_t *
1063 ohci_hash_find_td(sc, a)
1064 ohci_softc_t *sc;
1065 ohci_physaddr_t a;
1066 {
1067 int h = HASH(a);
1068 ohci_soft_td_t *std;
1069
1070 for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1071 std != 0;
1072 std = LIST_NEXT(std, hnext))
1073 if (std->physaddr == a)
1074 return (std);
1075 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a);
1076 }
1077
1078 void
1079 ohci_timeout(addr)
1080 void *addr;
1081 {
1082 #if 0
1083 usbd_request_handle *reqh = addr;
1084 int s;
1085
1086 DPRINTF(("ohci_timeout: reqh=%p\n", reqh));
1087 s = splusb();
1088 /* XXX need to inactivate TD before calling interrupt routine */
1089 ohci_XXX_done(reqh);
1090 splx(s);
1091 #endif
1092 }
1093
1094 #ifdef USB_DEBUG
1095 void
1096 ohci_dump_tds(std)
1097 ohci_soft_td_t *std;
1098 {
1099 for (; std; std = std->nexttd)
1100 ohci_dump_td(std);
1101 }
1102
1103 void
1104 ohci_dump_td(std)
1105 ohci_soft_td_t *std;
1106 {
1107 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n",
1108 std, (u_long)std->physaddr,
1109 (u_long)std->td->td_flags,
1110 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
1111 OHCI_TD_GET_DI(std->td->td_flags),
1112 OHCI_TD_GET_EC(std->td->td_flags),
1113 OHCI_TD_GET_CC(std->td->td_flags),
1114 (u_long)std->td->td_cbp,
1115 (u_long)std->td->td_nexttd, (u_long)std->td->td_be);
1116 }
1117
1118 void
1119 ohci_dump_ed(sed)
1120 ohci_soft_ed_t *sed;
1121 {
1122 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx headp=%b nexted=0x%08lx\n",
1123 sed, (u_long)sed->physaddr,
1124 OHCI_ED_GET_FA(sed->ed->ed_flags),
1125 OHCI_ED_GET_EN(sed->ed->ed_flags),
1126 OHCI_ED_GET_MAXP(sed->ed->ed_flags),
1127 (u_long)sed->ed->ed_flags,
1128 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO",
1129 (u_long)sed->ed->ed_tailp,
1130 (u_long)sed->ed->ed_headp, "\20\1HALT\2CARRY",
1131 (u_long)sed->ed->ed_nexted);
1132 }
1133 #endif
1134
1135 usbd_status
1136 ohci_open(pipe)
1137 usbd_pipe_handle pipe;
1138 {
1139 usbd_device_handle dev = pipe->device;
1140 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1141 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1142 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1143 u_int8_t addr = dev->address;
1144 ohci_soft_ed_t *sed;
1145 ohci_soft_td_t *std;
1146 usbd_status r;
1147 int s;
1148
1149 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1150 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1151 if (addr == sc->sc_addr) {
1152 switch (ed->bEndpointAddress) {
1153 case USB_CONTROL_ENDPOINT:
1154 pipe->methods = &ohci_root_ctrl_methods;
1155 break;
1156 case UE_IN | OHCI_INTR_ENDPT:
1157 pipe->methods = &ohci_root_intr_methods;
1158 break;
1159 default:
1160 return (USBD_INVAL);
1161 }
1162 } else {
1163 sed = ohci_alloc_sed(sc);
1164 if (sed == 0)
1165 goto bad0;
1166 std = ohci_alloc_std(sc);
1167 if (std == 0)
1168 goto bad1;
1169 opipe->sed = sed;
1170 opipe->tail = std;
1171 sed->ed->ed_flags =
1172 OHCI_ED_SET_FA(addr) |
1173 OHCI_ED_SET_EN(ed->bEndpointAddress) |
1174 OHCI_ED_DIR_TD |
1175 (dev->lowspeed ? OHCI_ED_SPEED : 0) |
1176 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ?
1177 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) |
1178 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize));
1179 sed->ed->ed_headp = sed->ed->ed_tailp = std->physaddr;
1180
1181 switch (ed->bmAttributes & UE_XFERTYPE) {
1182 case UE_CONTROL:
1183 pipe->methods = &ohci_device_ctrl_methods;
1184 r = usb_allocmem(sc->sc_dmatag,
1185 sizeof(usb_device_request_t),
1186 0, &opipe->u.ctl.reqdma);
1187 if (r != USBD_NORMAL_COMPLETION)
1188 goto bad;
1189 s = splusb();
1190 ohci_add_ed(sed, sc->sc_ctrl_head);
1191 splx(s);
1192 break;
1193 case UE_INTERRUPT:
1194 pipe->methods = &ohci_device_intr_methods;
1195 return (ohci_device_setintr(sc, opipe, ed->bInterval));
1196 case UE_ISOCHRONOUS:
1197 printf("ohci_open: open iso unimplemented\n");
1198 return (USBD_XXX);
1199 case UE_BULK:
1200 pipe->methods = &ohci_device_bulk_methods;
1201 s = splusb();
1202 ohci_add_ed(sed, sc->sc_bulk_head);
1203 splx(s);
1204 break;
1205 }
1206 }
1207 return (USBD_NORMAL_COMPLETION);
1208
1209 bad:
1210 ohci_free_std(sc, std);
1211 bad1:
1212 ohci_free_sed(sc, sed);
1213 bad0:
1214 return (USBD_NOMEM);
1215
1216 }
1217
1218 /*
1219 * Data structures and routines to emulate the root hub.
1220 */
1221 usb_device_descriptor_t ohci_devd = {
1222 USB_DEVICE_DESCRIPTOR_SIZE,
1223 UDESC_DEVICE, /* type */
1224 {0x00, 0x01}, /* USB version */
1225 UCLASS_HUB, /* class */
1226 USUBCLASS_HUB, /* subclass */
1227 0, /* protocol */
1228 64, /* max packet */
1229 {0},{0},{0x00,0x01}, /* device id */
1230 1,2,0, /* string indicies */
1231 1 /* # of configurations */
1232 };
1233
1234 usb_config_descriptor_t ohci_confd = {
1235 USB_CONFIG_DESCRIPTOR_SIZE,
1236 UDESC_CONFIG,
1237 {USB_CONFIG_DESCRIPTOR_SIZE +
1238 USB_INTERFACE_DESCRIPTOR_SIZE +
1239 USB_ENDPOINT_DESCRIPTOR_SIZE},
1240 1,
1241 1,
1242 0,
1243 UC_SELF_POWERED,
1244 0 /* max power */
1245 };
1246
1247 usb_interface_descriptor_t ohci_ifcd = {
1248 USB_INTERFACE_DESCRIPTOR_SIZE,
1249 UDESC_INTERFACE,
1250 0,
1251 0,
1252 1,
1253 UCLASS_HUB,
1254 USUBCLASS_HUB,
1255 0,
1256 0
1257 };
1258
1259 usb_endpoint_descriptor_t ohci_endpd = {
1260 USB_ENDPOINT_DESCRIPTOR_SIZE,
1261 UDESC_ENDPOINT,
1262 UE_IN | OHCI_INTR_ENDPT,
1263 UE_INTERRUPT,
1264 {8, 0}, /* max packet */
1265 255
1266 };
1267
1268 usb_hub_descriptor_t ohci_hubd = {
1269 USB_HUB_DESCRIPTOR_SIZE,
1270 UDESC_HUB,
1271 0,
1272 {0,0},
1273 0,
1274 0,
1275 {0},
1276 {0},
1277 };
1278
1279 int
1280 ohci_str(p, l, s)
1281 usb_string_descriptor_t *p;
1282 int l;
1283 char *s;
1284 {
1285 int i;
1286
1287 if (l == 0)
1288 return (0);
1289 p->bLength = 2 * strlen(s) + 2;
1290 if (l == 1)
1291 return (1);
1292 p->bDescriptorType = UDESC_STRING;
1293 l -= 2;
1294 for (i = 0; s[i] && l > 1; i++, l -= 2)
1295 USETW2(p->bString[i], 0, s[i]);
1296 return (2*i+2);
1297 }
1298
1299 /*
1300 * Simulate a hardware hub by handling all the necessary requests.
1301 */
1302 usbd_status
1303 ohci_root_ctrl_transfer(reqh)
1304 usbd_request_handle reqh;
1305 {
1306 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1307 usb_device_request_t *req;
1308 void *buf;
1309 int port, i;
1310 int len, value, index, l, totlen = 0;
1311 usb_port_status_t ps;
1312 usb_hub_descriptor_t hubd;
1313 usbd_status r;
1314 u_int32_t v;
1315
1316 if (!reqh->isreq)
1317 /* XXX panic */
1318 return (USBD_INVAL);
1319 req = &reqh->request;
1320 buf = reqh->buffer;
1321
1322 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
1323 req->bmRequestType, req->bRequest));
1324
1325 len = UGETW(req->wLength);
1326 value = UGETW(req->wValue);
1327 index = UGETW(req->wIndex);
1328 #define C(x,y) ((x) | ((y) << 8))
1329 switch(C(req->bRequest, req->bmRequestType)) {
1330 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1331 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1332 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1333 /*
1334 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops
1335 * for the integrated root hub.
1336 */
1337 break;
1338 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1339 if (len > 0) {
1340 *(u_int8_t *)buf = sc->sc_conf;
1341 totlen = 1;
1342 }
1343 break;
1344 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1345 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
1346 switch(value >> 8) {
1347 case UDESC_DEVICE:
1348 if ((value & 0xff) != 0) {
1349 r = USBD_IOERROR;
1350 goto ret;
1351 }
1352 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1353 memcpy(buf, &ohci_devd, l);
1354 break;
1355 case UDESC_CONFIG:
1356 if ((value & 0xff) != 0) {
1357 r = USBD_IOERROR;
1358 goto ret;
1359 }
1360 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1361 memcpy(buf, &ohci_confd, l);
1362 buf = (char *)buf + l;
1363 len -= l;
1364 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1365 totlen += l;
1366 memcpy(buf, &ohci_ifcd, l);
1367 buf = (char *)buf + l;
1368 len -= l;
1369 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1370 totlen += l;
1371 memcpy(buf, &ohci_endpd, l);
1372 break;
1373 case UDESC_STRING:
1374 if (len == 0)
1375 break;
1376 *(u_int8_t *)buf = 0;
1377 totlen = 1;
1378 switch (value & 0xff) {
1379 case 1: /* Vendor */
1380 totlen = ohci_str(buf, len, sc->sc_vendor);
1381 break;
1382 case 2: /* Product */
1383 totlen = ohci_str(buf, len, "OHCI root hub");
1384 break;
1385 }
1386 break;
1387 default:
1388 r = USBD_IOERROR;
1389 goto ret;
1390 }
1391 break;
1392 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1393 if (len > 0) {
1394 *(u_int8_t *)buf = 0;
1395 totlen = 1;
1396 }
1397 break;
1398 case C(UR_GET_STATUS, UT_READ_DEVICE):
1399 if (len > 1) {
1400 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1401 totlen = 2;
1402 }
1403 break;
1404 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1405 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1406 if (len > 1) {
1407 USETW(((usb_status_t *)buf)->wStatus, 0);
1408 totlen = 2;
1409 }
1410 break;
1411 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1412 if (value >= USB_MAX_DEVICES) {
1413 r = USBD_IOERROR;
1414 goto ret;
1415 }
1416 sc->sc_addr = value;
1417 break;
1418 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1419 if (value != 0 && value != 1) {
1420 r = USBD_IOERROR;
1421 goto ret;
1422 }
1423 sc->sc_conf = value;
1424 break;
1425 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1426 break;
1427 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1428 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1429 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1430 r = USBD_IOERROR;
1431 goto ret;
1432 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1433 break;
1434 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1435 break;
1436 /* Hub requests */
1437 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1438 break;
1439 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1440 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n",
1441 index, value));
1442 if (index < 1 || index > sc->sc_noport) {
1443 r = USBD_IOERROR;
1444 goto ret;
1445 }
1446 port = OHCI_RH_PORT_STATUS(index);
1447 switch(value) {
1448 case UHF_PORT_ENABLE:
1449 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
1450 break;
1451 case UHF_PORT_SUSPEND:
1452 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
1453 break;
1454 case UHF_PORT_POWER:
1455 OWRITE4(sc, port, UPS_LOW_SPEED);
1456 break;
1457 case UHF_C_PORT_CONNECTION:
1458 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
1459 break;
1460 case UHF_C_PORT_ENABLE:
1461 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
1462 break;
1463 case UHF_C_PORT_SUSPEND:
1464 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
1465 break;
1466 case UHF_C_PORT_OVER_CURRENT:
1467 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
1468 break;
1469 case UHF_C_PORT_RESET:
1470 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
1471 break;
1472 default:
1473 r = USBD_IOERROR;
1474 goto ret;
1475 }
1476 switch(value) {
1477 case UHF_C_PORT_CONNECTION:
1478 case UHF_C_PORT_ENABLE:
1479 case UHF_C_PORT_SUSPEND:
1480 case UHF_C_PORT_OVER_CURRENT:
1481 case UHF_C_PORT_RESET:
1482 /* Enable RHSC interrupt if condition is cleared. */
1483 if ((OREAD4(sc, port) >> 16) == 0)
1484 ohci_rhsc_able(sc, 1);
1485 break;
1486 default:
1487 break;
1488 }
1489 break;
1490 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1491 if (value != 0) {
1492 r = USBD_IOERROR;
1493 goto ret;
1494 }
1495 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
1496 hubd = ohci_hubd;
1497 hubd.bNbrPorts = sc->sc_noport;
1498 USETW(hubd.bHubCharacteristics,
1499 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
1500 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
1501 /* XXX overcurrent */
1502 );
1503 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
1504 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
1505 if (sc->sc_noport < 8) {
1506 hubd.DeviceRemovable[0] = (u_int8_t)v;
1507 hubd.PortPowerCtrlMask[0] = (u_int8_t)(v >> 16);
1508 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE;
1509 } else {
1510 hubd.DeviceRemovable[0] = (u_int8_t)v;
1511 hubd.DeviceRemovable[1] = (u_int8_t)(v>>8);
1512 hubd.PortPowerCtrlMask[1] = (u_int8_t)(v >> 16);
1513 hubd.PortPowerCtrlMask[2] = (u_int8_t)(v >> 24);
1514 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + 2;
1515 }
1516 l = min(len, hubd.bDescLength);
1517 totlen = l;
1518 memcpy(buf, &hubd, l);
1519 break;
1520 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1521 if (len != 4) {
1522 r = USBD_IOERROR;
1523 goto ret;
1524 }
1525 memset(buf, 0, len); /* ? XXX */
1526 totlen = len;
1527 break;
1528 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1529 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
1530 index));
1531 if (index < 1 || index > sc->sc_noport) {
1532 r = USBD_IOERROR;
1533 goto ret;
1534 }
1535 if (len != 4) {
1536 r = USBD_IOERROR;
1537 goto ret;
1538 }
1539 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
1540 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
1541 v));
1542 USETW(ps.wPortStatus, v);
1543 USETW(ps.wPortChange, v >> 16);
1544 l = min(len, sizeof ps);
1545 memcpy(buf, &ps, l);
1546 totlen = l;
1547 break;
1548 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1549 r = USBD_IOERROR;
1550 goto ret;
1551 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1552 break;
1553 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1554 if (index < 1 || index > sc->sc_noport) {
1555 r = USBD_IOERROR;
1556 goto ret;
1557 }
1558 port = OHCI_RH_PORT_STATUS(index);
1559 switch(value) {
1560 case UHF_PORT_ENABLE:
1561 OWRITE4(sc, port, UPS_PORT_ENABLED);
1562 break;
1563 case UHF_PORT_SUSPEND:
1564 OWRITE4(sc, port, UPS_SUSPEND);
1565 break;
1566 case UHF_PORT_RESET:
1567 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", index));
1568 OWRITE4(sc, port, UPS_RESET);
1569 for (i = 0; i < 10; i++) {
1570 usbd_delay_ms(&sc->sc_bus, 10);
1571 if ((OREAD4(sc, port) & UPS_RESET) == 0)
1572 break;
1573 }
1574 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
1575 index, OREAD4(sc, port)));
1576 break;
1577 case UHF_PORT_POWER:
1578 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power %d\n", index));
1579 OWRITE4(sc, port, UPS_PORT_POWER);
1580 break;
1581 default:
1582 r = USBD_IOERROR;
1583 goto ret;
1584 }
1585 break;
1586 default:
1587 r = USBD_IOERROR;
1588 goto ret;
1589 }
1590 reqh->actlen = totlen;
1591 r = USBD_NORMAL_COMPLETION;
1592 ret:
1593 reqh->status = r;
1594 reqh->xfercb(reqh);
1595 return (USBD_IN_PROGRESS);
1596 }
1597
1598 /* Abort a root control request. */
1599 void
1600 ohci_root_ctrl_abort(reqh)
1601 usbd_request_handle reqh;
1602 {
1603 /* Nothing to do, all transfers are synchronous. */
1604 }
1605
1606 /* Close the root pipe. */
1607 void
1608 ohci_root_ctrl_close(pipe)
1609 usbd_pipe_handle pipe;
1610 {
1611 DPRINTF(("ohci_root_ctrl_close\n"));
1612 }
1613
1614 usbd_status
1615 ohci_root_intr_transfer(reqh)
1616 usbd_request_handle reqh;
1617 {
1618 usbd_pipe_handle pipe = reqh->pipe;
1619 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1620 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe;
1621 usb_dma_t *dmap;
1622 usbd_status r;
1623 int len;
1624
1625 len = reqh->length;
1626 dmap = &upipe->u.intr.datadma;
1627 if (len == 0)
1628 return (USBD_INVAL); /* XXX should it be? */
1629
1630 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1631 if (r != USBD_NORMAL_COMPLETION)
1632 return (r);
1633 sc->sc_intrreqh = reqh;
1634
1635 return (USBD_IN_PROGRESS);
1636 }
1637
1638 /* Abort a root interrupt request. */
1639 void
1640 ohci_root_intr_abort(reqh)
1641 usbd_request_handle reqh;
1642 {
1643 /* No need to abort. */
1644 }
1645
1646 /* Close the root pipe. */
1647 void
1648 ohci_root_intr_close(pipe)
1649 usbd_pipe_handle pipe;
1650 {
1651 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1652 sc->sc_intrreqh = 0;
1653
1654 DPRINTF(("ohci_root_intr_close\n"));
1655 }
1656
1657 /************************/
1658
1659 usbd_status
1660 ohci_device_ctrl_transfer(reqh)
1661 usbd_request_handle reqh;
1662 {
1663 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1664 usbd_status r;
1665
1666 if (!reqh->isreq) {
1667 /* XXX panic */
1668 printf("ohci_device_ctrl_transfer: not a request\n");
1669 return (USBD_INVAL);
1670 }
1671
1672 r = ohci_device_request(reqh);
1673 if (r != USBD_NORMAL_COMPLETION)
1674 return (r);
1675
1676 if (sc->sc_bus.use_polling)
1677 ohci_waitintr(sc, reqh);
1678 return (USBD_IN_PROGRESS);
1679 }
1680
1681 /* Abort a device control request. */
1682 void
1683 ohci_device_ctrl_abort(reqh)
1684 usbd_request_handle reqh;
1685 {
1686 /* XXX inactivate */
1687 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1688 /* XXX call done */
1689 }
1690
1691 /* Close a device control pipe. */
1692 void
1693 ohci_device_ctrl_close(pipe)
1694 usbd_pipe_handle pipe;
1695 {
1696 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1697 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1698 ohci_soft_ed_t *sed = opipe->sed;
1699 int s;
1700
1701 s = splusb();
1702 sed->ed->ed_flags |= OHCI_ED_SKIP;
1703 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1704 usbd_delay_ms(&sc->sc_bus, 2);
1705 ohci_rem_ed(sed, sc->sc_ctrl_head);
1706 splx(s);
1707 ohci_free_std(sc, opipe->tail);
1708 ohci_free_sed(sc, opipe->sed);
1709 /* XXX free other resources */
1710 }
1711
1712 /************************/
1713
1714 usbd_status
1715 ohci_device_bulk_transfer(reqh)
1716 usbd_request_handle reqh;
1717 {
1718 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1719 usbd_device_handle dev = opipe->pipe.device;
1720 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1721 int addr = dev->address;
1722 ohci_soft_td_t *xfer, *tail;
1723 ohci_soft_ed_t *sed;
1724 usb_dma_t *dmap;
1725 usbd_status r;
1726 int s, len, isread;
1727
1728 if (reqh->isreq) {
1729 /* XXX panic */
1730 printf("ohci_device_bulk_transfer: a request\n");
1731 return (USBD_INVAL);
1732 }
1733
1734 len = reqh->length;
1735 dmap = &opipe->u.bulk.datadma;
1736 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN;
1737 sed = opipe->sed;
1738
1739 opipe->u.bulk.length = len;
1740
1741 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1742 if (r != USBD_NORMAL_COMPLETION)
1743 goto ret1;
1744
1745 tail = ohci_alloc_std(sc);
1746 if (!tail) {
1747 r = USBD_NOMEM;
1748 goto ret2;
1749 }
1750 tail->reqh = 0;
1751
1752 /* Update device address */
1753 sed->ed->ed_flags =
1754 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) |
1755 OHCI_ED_SET_FA(addr);
1756
1757 /* Set up data transaction */
1758 xfer = opipe->tail;
1759 xfer->td->td_flags =
1760 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1761 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
1762 xfer->td->td_cbp = DMAADDR(dmap);
1763 xfer->nexttd = tail;
1764 xfer->td->td_nexttd = tail->physaddr;
1765 xfer->td->td_be = xfer->td->td_cbp + len - 1;
1766 xfer->len = len;
1767 xfer->reqh = reqh;
1768
1769 reqh->actlen = 0;
1770 reqh->hcpriv = xfer;
1771
1772 if (!isread)
1773 memcpy(KERNADDR(dmap), reqh->buffer, len);
1774
1775 /* Insert ED in schedule */
1776 s = splusb();
1777 ohci_hash_add_td(sc, xfer);
1778 sed->ed->ed_tailp = tail->physaddr;
1779 opipe->tail = tail;
1780 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
1781 if (reqh->timeout && !sc->sc_bus.use_polling)
1782 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
1783 splx(s);
1784
1785 return (USBD_IN_PROGRESS);
1786
1787 ret2:
1788 usb_freemem(sc->sc_dmatag, dmap);
1789 ret1:
1790 return (r);
1791 }
1792
1793 /* Abort a device bulk request. */
1794 void
1795 ohci_device_bulk_abort(reqh)
1796 usbd_request_handle reqh;
1797 {
1798 #if 0
1799 sed->ed->ed_flags |= OHCI_ED_SKIP;
1800 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1801 usbd_delay_ms(reqh->pipe->device->bus, 2);
1802 #endif
1803 /* XXX inactivate */
1804 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1805 /* XXX call done */
1806 }
1807
1808 /* Close a device bulk pipe. */
1809 void
1810 ohci_device_bulk_close(pipe)
1811 usbd_pipe_handle pipe;
1812 {
1813 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1814 usbd_device_handle dev = opipe->pipe.device;
1815 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1816 int s;
1817
1818 s = splusb();
1819 ohci_rem_ed(opipe->sed, sc->sc_bulk_head);
1820 splx(s);
1821 ohci_free_std(sc, opipe->tail);
1822 ohci_free_sed(sc, opipe->sed);
1823 /* XXX free other resources */
1824 }
1825
1826 /************************/
1827
1828 usbd_status
1829 ohci_device_intr_transfer(reqh)
1830 usbd_request_handle reqh;
1831 {
1832 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1833 usbd_device_handle dev = opipe->pipe.device;
1834 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1835 ohci_soft_ed_t *sed = opipe->sed;
1836 ohci_soft_td_t *xfer, *tail;
1837 usb_dma_t *dmap;
1838 usbd_status r;
1839 int len;
1840 int s;
1841
1842 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d priv=%p\n",
1843 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv));
1844
1845 if (reqh->isreq)
1846 panic("ohci_device_intr_transfer: a request\n");
1847
1848 len = reqh->length;
1849 dmap = &opipe->u.intr.datadma;
1850 if (len == 0)
1851 return (USBD_INVAL); /* XXX should it be? */
1852
1853 xfer = opipe->tail;
1854 tail = ohci_alloc_std(sc);
1855 if (!tail) {
1856 r = USBD_NOMEM;
1857 goto ret1;
1858 }
1859 tail->reqh = 0;
1860
1861 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1862 if (r != USBD_NORMAL_COMPLETION)
1863 goto ret2;
1864
1865 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC |
1866 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY;
1867 xfer->td->td_cbp = DMAADDR(dmap);
1868 xfer->nexttd = tail;
1869 xfer->td->td_nexttd = tail->physaddr;
1870 xfer->td->td_be = xfer->td->td_cbp + len - 1;
1871 xfer->len = len;
1872 xfer->reqh = reqh;
1873
1874 reqh->actlen = 0;
1875 reqh->hcpriv = xfer;
1876
1877 #if USB_DEBUG
1878 if (ohcidebug > 5) {
1879 printf("ohci_device_intr_transfer:\n");
1880 ohci_dump_ed(sed);
1881 ohci_dump_tds(xfer);
1882 }
1883 #endif
1884
1885 /* Insert ED in schedule */
1886 s = splusb();
1887 ohci_hash_add_td(sc, xfer);
1888 sed->ed->ed_tailp = tail->physaddr;
1889 opipe->tail = tail;
1890 #if 0
1891 if (reqh->timeout && !sc->sc_bus.use_polling)
1892 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout));
1893 #endif
1894 sed->ed->ed_flags &= ~OHCI_ED_SKIP;
1895 splx(s);
1896
1897 #ifdef USB_DEBUG
1898 if (ohcidebug > 5) {
1899 delay(5000);
1900 printf("ohci_device_intr_transfer: status=%x\n",
1901 OREAD4(sc, OHCI_COMMAND_STATUS));
1902 ohci_dump_ed(sed);
1903 ohci_dump_tds(xfer);
1904 }
1905 #endif
1906
1907 return (USBD_IN_PROGRESS);
1908
1909 ret2:
1910 ohci_free_std(sc, xfer);
1911 ret1:
1912 return (r);
1913 }
1914
1915 /* Abort a device control request. */
1916 void
1917 ohci_device_intr_abort(reqh)
1918 usbd_request_handle reqh;
1919 {
1920 /* XXX inactivate */
1921 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is finished */
1922 if (reqh->pipe->intrreqh == reqh) {
1923 DPRINTF(("ohci_device_intr_abort: remove\n"));
1924 reqh->pipe->intrreqh = 0;
1925 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh);
1926 }
1927 }
1928
1929 /* Close a device interrupt pipe. */
1930 void
1931 ohci_device_intr_close(pipe)
1932 usbd_pipe_handle pipe;
1933 {
1934 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1935 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1936 int nslots = opipe->u.intr.nslots;
1937 int pos = opipe->u.intr.pos;
1938 int j;
1939 ohci_soft_ed_t *p, *sed = opipe->sed;
1940 int s;
1941
1942 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
1943 pipe, nslots, pos));
1944 s = splusb();
1945 sed->ed->ed_flags |= OHCI_ED_SKIP;
1946 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp)
1947 usbd_delay_ms(&sc->sc_bus, 2);
1948
1949 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
1950 ;
1951 if (!p)
1952 panic("ohci_device_intr_close: ED not found\n");
1953 p->next = sed->next;
1954 p->ed->ed_nexted = sed->ed->ed_nexted;
1955 splx(s);
1956
1957 for (j = 0; j < nslots; j++)
1958 --sc->sc_bws[pos * nslots + j];
1959
1960 ohci_free_std(sc, opipe->tail);
1961 ohci_free_sed(sc, opipe->sed);
1962 /* XXX free other resources */
1963 }
1964
1965 usbd_status
1966 ohci_device_setintr(sc, opipe, ival)
1967 ohci_softc_t *sc;
1968 struct ohci_pipe *opipe;
1969 int ival;
1970 {
1971 int i, j, s, best;
1972 u_int npoll, slow, shigh, nslots;
1973 u_int bestbw, bw;
1974 ohci_soft_ed_t *hsed, *sed = opipe->sed;
1975
1976 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
1977 if (ival == 0) {
1978 printf("ohci_setintr: 0 interval\n");
1979 return (USBD_INVAL);
1980 }
1981
1982 npoll = OHCI_NO_INTRS;
1983 while (npoll > ival)
1984 npoll /= 2;
1985 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
1986
1987 /*
1988 * We now know which level in the tree the ED must go into.
1989 * Figure out which slot has most bandwidth left over.
1990 * Slots to examine:
1991 * npoll
1992 * 1 0
1993 * 2 1 2
1994 * 4 3 4 5 6
1995 * 8 7 8 9 10 11 12 13 14
1996 * N (N-1) .. (N-1+N-1)
1997 */
1998 slow = npoll-1;
1999 shigh = slow + npoll;
2000 nslots = OHCI_NO_INTRS / npoll;
2001 for (best = i = slow, bestbw = ~0; i < shigh; i++) {
2002 bw = 0;
2003 for (j = 0; j < nslots; j++)
2004 bw += sc->sc_bws[i * nslots + j];
2005 if (bw < bestbw) {
2006 best = i;
2007 bestbw = bw;
2008 }
2009 }
2010 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
2011 best, slow, shigh, bestbw));
2012
2013 s = splusb();
2014 hsed = sc->sc_eds[best];
2015 sed->next = hsed->next;
2016 sed->ed->ed_nexted = hsed->ed->ed_nexted;
2017 hsed->next = sed;
2018 hsed->ed->ed_nexted = sed->physaddr;
2019 splx(s);
2020
2021 for (j = 0; j < nslots; j++)
2022 ++sc->sc_bws[best * nslots + j];
2023 opipe->u.intr.nslots = nslots;
2024 opipe->u.intr.pos = best;
2025
2026 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
2027 return (USBD_NORMAL_COMPLETION);
2028 }
2029
2030