ohci.c revision 1.17 1 /* $NetBSD: ohci.c,v 1.17 1998/12/28 20:13:59 augustss Exp $ */
2
3 /*
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (augustss (at) carlstedt.se) at
9 * Carlstedt Research & Technology.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * USB Open Host Controller driver.
42 *
43 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf
44 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl
45 */
46
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #if defined(__NetBSD__)
52 #include <sys/device.h>
53 #elif defined(__FreeBSD__)
54 #include <sys/module.h>
55 #include <sys/bus.h>
56 #endif
57 #include <sys/proc.h>
58 #include <sys/queue.h>
59 #include <sys/select.h>
60
61 #include <machine/bus.h>
62 #include <machine/endian.h>
63
64 #include <dev/usb/usb.h>
65 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usbdivar.h>
67 #include <dev/usb/usb_quirks.h>
68 #include <dev/usb/usb_mem.h>
69
70 #include <dev/usb/ohcireg.h>
71 #include <dev/usb/ohcivar.h>
72
73 #if defined(__FreeBSD__)
74 #include <machine/clock.h>
75 #include "dev/usb/queue.addendum.h"
76
77 #define delay(d) DELAY(d)
78
79 #endif
80
81 /*
82 * The OHCI controller is little endian, so on big endian machines
83 * the data strored in memory needs to be swapped.
84 */
85 #if BYTE_ORDER == BIG_ENDIAN
86 #define LE(x) (bswap32(x))
87 #else
88 #define LE(x) (x)
89 #endif
90
91 struct ohci_pipe;
92
93 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *));
94 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *));
95
96 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *));
97 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *));
98
99 usbd_status ohci_open __P((usbd_pipe_handle));
100 void ohci_poll __P((struct usbd_bus *));
101 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle));
102 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle));
103 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t));
104 void ohci_ii_done __P((ohci_softc_t *, usbd_request_handle));
105 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle));
106 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle));
107 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle));
108
109 usbd_status ohci_device_request __P((usbd_request_handle reqh));
110 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
111 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *));
112 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *));
113 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *));
114 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t));
115
116 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle));
117 usbd_status ohci_root_ctrl_start __P((usbd_request_handle));
118 void ohci_root_ctrl_abort __P((usbd_request_handle));
119 void ohci_root_ctrl_close __P((usbd_pipe_handle));
120
121 usbd_status ohci_root_intr_transfer __P((usbd_request_handle));
122 usbd_status ohci_root_intr_start __P((usbd_request_handle));
123 void ohci_root_intr_abort __P((usbd_request_handle));
124 void ohci_root_intr_close __P((usbd_pipe_handle));
125
126 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle));
127 usbd_status ohci_device_ctrl_start __P((usbd_request_handle));
128 void ohci_device_ctrl_abort __P((usbd_request_handle));
129 void ohci_device_ctrl_close __P((usbd_pipe_handle));
130
131 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle));
132 usbd_status ohci_device_bulk_start __P((usbd_request_handle));
133 void ohci_device_bulk_abort __P((usbd_request_handle));
134 void ohci_device_bulk_close __P((usbd_pipe_handle));
135
136 usbd_status ohci_device_intr_transfer __P((usbd_request_handle));
137 usbd_status ohci_device_intr_start __P((usbd_request_handle));
138 void ohci_device_intr_abort __P((usbd_request_handle));
139 void ohci_device_intr_close __P((usbd_pipe_handle));
140 usbd_status ohci_device_setintr __P((ohci_softc_t *sc,
141 struct ohci_pipe *pipe, int ival));
142
143 int ohci_str __P((usb_string_descriptor_t *, int, char *));
144
145 void ohci_timeout __P((void *));
146 void ohci_rhsc_able __P((ohci_softc_t *, int));
147
148 #ifdef USB_DEBUG
149 ohci_softc_t *thesc;
150 void ohci_dumpregs __P((ohci_softc_t *));
151 void ohci_dump_tds __P((ohci_soft_td_t *));
152 void ohci_dump_td __P((ohci_soft_td_t *));
153 void ohci_dump_ed __P((ohci_soft_ed_t *));
154 #endif
155
156 #if defined(__NetBSD__)
157 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x))
158 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r))
159 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r))
160 #elif defined(__FreeBSD__)
161 #define OWRITE4(sc, r, x) outl((sc)->sc_iobase + (r), (x))
162 #define OREAD4(sc, r) inl((sc)->sc_iobase + (r))
163 #define OREAD2(sc, r) inw((sc)->sc_iobase + (r))
164 #endif
165
166 /* Reverse the bits in a value 0 .. 31 */
167 static u_int8_t revbits[OHCI_NO_INTRS] =
168 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c,
169 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e,
170 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d,
171 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f };
172
173 struct ohci_pipe {
174 struct usbd_pipe pipe;
175 ohci_soft_ed_t *sed;
176 ohci_soft_td_t *tail;
177 /* Info needed for different pipe kinds. */
178 union {
179 /* Control pipe */
180 struct {
181 usb_dma_t datadma;
182 usb_dma_t reqdma;
183 u_int length;
184 ohci_soft_td_t *setup, *xfer, *stat;
185 } ctl;
186 /* Interrupt pipe */
187 struct {
188 usb_dma_t datadma;
189 int nslots;
190 int pos;
191 } intr;
192 /* Bulk pipe */
193 struct {
194 usb_dma_t datadma;
195 u_int length;
196 } bulk;
197 } u;
198 };
199
200 #define OHCI_INTR_ENDPT 1
201
202 struct usbd_methods ohci_root_ctrl_methods = {
203 ohci_root_ctrl_transfer,
204 ohci_root_ctrl_start,
205 ohci_root_ctrl_abort,
206 ohci_root_ctrl_close,
207 0,
208 };
209
210 struct usbd_methods ohci_root_intr_methods = {
211 ohci_root_intr_transfer,
212 ohci_root_intr_start,
213 ohci_root_intr_abort,
214 ohci_root_intr_close,
215 0,
216 };
217
218 struct usbd_methods ohci_device_ctrl_methods = {
219 ohci_device_ctrl_transfer,
220 ohci_device_ctrl_start,
221 ohci_device_ctrl_abort,
222 ohci_device_ctrl_close,
223 0,
224 };
225
226 struct usbd_methods ohci_device_intr_methods = {
227 ohci_device_intr_transfer,
228 ohci_device_intr_start,
229 ohci_device_intr_abort,
230 ohci_device_intr_close,
231 };
232
233 struct usbd_methods ohci_device_bulk_methods = {
234 ohci_device_bulk_transfer,
235 ohci_device_bulk_start,
236 ohci_device_bulk_abort,
237 ohci_device_bulk_close,
238 0,
239 };
240
241 ohci_soft_ed_t *
242 ohci_alloc_sed(sc)
243 ohci_softc_t *sc;
244 {
245 ohci_soft_ed_t *sed;
246 usbd_status r;
247 int i, offs;
248 usb_dma_t dma;
249
250 if (!sc->sc_freeeds) {
251 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n"));
252 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK,
253 M_USBDEV, M_NOWAIT);
254 if (!sed)
255 return 0;
256 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK,
257 OHCI_ED_ALIGN, &dma);
258 if (r != USBD_NORMAL_COMPLETION) {
259 free(sed, M_USBDEV);
260 return 0;
261 }
262 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) {
263 offs = i * OHCI_ED_SIZE;
264 sed->physaddr = DMAADDR(&dma) + offs;
265 sed->ed = (ohci_ed_t *)
266 ((char *)KERNADDR(&dma) + offs);
267 sed->next = sc->sc_freeeds;
268 sc->sc_freeeds = sed;
269 }
270 }
271 sed = sc->sc_freeeds;
272 sc->sc_freeeds = sed->next;
273 memset(sed->ed, 0, OHCI_ED_SIZE);
274 sed->next = 0;
275 return sed;
276 }
277
278 void
279 ohci_free_sed(sc, sed)
280 ohci_softc_t *sc;
281 ohci_soft_ed_t *sed;
282 {
283 sed->next = sc->sc_freeeds;
284 sc->sc_freeeds = sed;
285 }
286
287 ohci_soft_td_t *
288 ohci_alloc_std(sc)
289 ohci_softc_t *sc;
290 {
291 ohci_soft_td_t *std;
292 usbd_status r;
293 int i, offs;
294 usb_dma_t dma;
295
296 if (!sc->sc_freetds) {
297 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n"));
298 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK,
299 M_USBDEV, M_NOWAIT);
300 if (!std)
301 return 0;
302 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK,
303 OHCI_TD_ALIGN, &dma);
304 if (r != USBD_NORMAL_COMPLETION) {
305 free(std, M_USBDEV);
306 return 0;
307 }
308 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) {
309 offs = i * OHCI_TD_SIZE;
310 std->physaddr = DMAADDR(&dma) + offs;
311 std->td = (ohci_td_t *)
312 ((char *)KERNADDR(&dma) + offs);
313 std->nexttd = sc->sc_freetds;
314 sc->sc_freetds = std;
315 }
316 }
317 std = sc->sc_freetds;
318 sc->sc_freetds = std->nexttd;
319 memset(std->td, 0, OHCI_TD_SIZE);
320 std->nexttd = 0;
321 return (std);
322 }
323
324 void
325 ohci_free_std(sc, std)
326 ohci_softc_t *sc;
327 ohci_soft_td_t *std;
328 {
329 std->nexttd = sc->sc_freetds;
330 sc->sc_freetds = std;
331 }
332
333 usbd_status
334 ohci_init(sc)
335 ohci_softc_t *sc;
336 {
337 ohci_soft_ed_t *sed, *psed;
338 usbd_status r;
339 int rev;
340 int i;
341 u_int32_t s, ctl, ival, hcr, fm, per;
342
343 #ifdef macppc
344 /* XXX without reset, keyboard and mouse are never attached */
345 printf("%s: resetting\n", sc->sc_bus.bdev.dv_xname);
346 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
347 delay(USB_RESET_DELAY * 10000);
348 #endif
349
350 DPRINTF(("ohci_init: start\n"));
351 rev = OREAD4(sc, OHCI_REVISION);
352 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev),
353 OHCI_REV_HI(rev), OHCI_REV_LO(rev),
354 OHCI_REV_LEGACY(rev) ? ", legacy support" : "");
355 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) {
356 printf("%s: unsupported OHCI revision\n",
357 USBDEVNAME(sc->sc_bus.bdev));
358 return (USBD_INVAL);
359 }
360
361 for (i = 0; i < OHCI_HASH_SIZE; i++)
362 LIST_INIT(&sc->sc_hash_tds[i]);
363
364 /* Allocate the HCCA area. */
365 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE,
366 OHCI_HCCA_ALIGN, &sc->sc_hccadma);
367 if (r != USBD_NORMAL_COMPLETION)
368 return (r);
369 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma);
370 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE);
371
372 sc->sc_eintrs = OHCI_NORMAL_INTRS;
373
374 sc->sc_ctrl_head = ohci_alloc_sed(sc);
375 if (!sc->sc_ctrl_head) {
376 r = USBD_NOMEM;
377 goto bad1;
378 }
379 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
380 sc->sc_bulk_head = ohci_alloc_sed(sc);
381 if (!sc->sc_bulk_head) {
382 r = USBD_NOMEM;
383 goto bad2;
384 }
385 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP);
386
387 /* Allocate all the dummy EDs that make up the interrupt tree. */
388 for (i = 0; i < OHCI_NO_EDS; i++) {
389 sed = ohci_alloc_sed(sc);
390 if (!sed) {
391 while (--i >= 0)
392 ohci_free_sed(sc, sc->sc_eds[i]);
393 r = USBD_NOMEM;
394 goto bad3;
395 }
396 /* All ED fields are set to 0. */
397 sc->sc_eds[i] = sed;
398 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
399 if (i != 0) {
400 psed = sc->sc_eds[(i-1) / 2];
401 sed->next = psed;
402 sed->ed->ed_nexted = LE(psed->physaddr);
403 }
404 }
405 /*
406 * Fill HCCA interrupt table. The bit reversal is to get
407 * the tree set up properly to spread the interrupts.
408 */
409 for (i = 0; i < OHCI_NO_INTRS; i++)
410 sc->sc_hcca->hcca_interrupt_table[revbits[i]] =
411 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr);
412
413 /* Determine in what context we are running. */
414 ctl = OREAD4(sc, OHCI_CONTROL);
415 if (ctl & OHCI_IR) {
416 /* SMM active, request change */
417 DPRINTF(("ohci_init: SMM active, request owner change\n"));
418 s = OREAD4(sc, OHCI_COMMAND_STATUS);
419 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR);
420 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) {
421 delay(1000);
422 ctl = OREAD4(sc, OHCI_CONTROL);
423 }
424 if ((ctl & OHCI_IR) == 0) {
425 printf("%s: SMM does not respond, resetting\n",
426 USBDEVNAME(sc->sc_bus.bdev));
427 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
428 goto reset;
429 }
430 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) {
431 /* BIOS started controller. */
432 DPRINTF(("ohci_init: BIOS active\n"));
433 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) {
434 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL);
435 delay(USB_RESUME_DELAY * 1000);
436 }
437 } else {
438 DPRINTF(("ohci_init: cold started\n"));
439 reset:
440 /* Controller was cold started. */
441 delay(USB_BUS_RESET_DELAY * 1000);
442 }
443
444 /*
445 * This reset should be necessary according to the OHCI spec, but
446 * without it some controller don't start.
447 */
448 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
449 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
450 delay(USB_BUS_RESET_DELAY * 1000);
451
452 /* We now own the host controller and the bus has been reset. */
453 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL));
454
455 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */
456 /* Nominal time for a reset is 10 us. */
457 for (i = 0; i < 10; i++) {
458 delay(10);
459 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR;
460 if (!hcr)
461 break;
462 }
463 if (hcr) {
464 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
465 r = USBD_IOERROR;
466 goto bad3;
467 }
468 #ifdef USB_DEBUG
469 thesc = sc;
470 if (ohcidebug > 15)
471 ohci_dumpregs(sc);
472 #endif
473
474 /* The controller is now in suspend state, we have 2ms to finish. */
475
476 /* Set up HC registers. */
477 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma));
478 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
479 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
480 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS);
481 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE);
482 ctl = OREAD4(sc, OHCI_CONTROL);
483 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR);
484 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE |
485 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL;
486 /* And finally start it! */
487 OWRITE4(sc, OHCI_CONTROL, ctl);
488
489 /*
490 * The controller is now OPERATIONAL. Set a some final
491 * registers that should be set earlier, but that the
492 * controller ignores when in the SUSPEND state.
493 */
494 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT;
495 fm |= OHCI_FSMPS(ival) | ival;
496 OWRITE4(sc, OHCI_FM_INTERVAL, fm);
497 per = OHCI_PERIODIC(ival); /* 90% periodic */
498 OWRITE4(sc, OHCI_PERIODIC_START, per);
499
500 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */
501
502 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A));
503
504 #ifdef USB_DEBUG
505 if (ohcidebug > 5)
506 ohci_dumpregs(sc);
507 #endif
508
509 /* Set up the bus struct. */
510 sc->sc_bus.open_pipe = ohci_open;
511 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe);
512 sc->sc_bus.do_poll = ohci_poll;
513
514 return (USBD_NORMAL_COMPLETION);
515
516 bad3:
517 ohci_free_sed(sc, sc->sc_ctrl_head);
518 bad2:
519 ohci_free_sed(sc, sc->sc_bulk_head);
520 bad1:
521 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma);
522 return (r);
523 }
524
525 #ifdef USB_DEBUG
526 void ohcidump(void);
527 void ohcidump(void) { ohci_dumpregs(thesc); }
528
529 void
530 ohci_dumpregs(sc)
531 ohci_softc_t *sc;
532 {
533 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n",
534 OREAD4(sc, OHCI_REVISION),
535 OREAD4(sc, OHCI_CONTROL),
536 OREAD4(sc, OHCI_COMMAND_STATUS));
537 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n",
538 OREAD4(sc, OHCI_INTERRUPT_STATUS),
539 OREAD4(sc, OHCI_INTERRUPT_ENABLE),
540 OREAD4(sc, OHCI_INTERRUPT_DISABLE));
541 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n",
542 OREAD4(sc, OHCI_HCCA),
543 OREAD4(sc, OHCI_PERIOD_CURRENT_ED),
544 OREAD4(sc, OHCI_CONTROL_HEAD_ED));
545 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n",
546 OREAD4(sc, OHCI_CONTROL_CURRENT_ED),
547 OREAD4(sc, OHCI_BULK_HEAD_ED),
548 OREAD4(sc, OHCI_BULK_CURRENT_ED));
549 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n",
550 OREAD4(sc, OHCI_DONE_HEAD),
551 OREAD4(sc, OHCI_FM_INTERVAL),
552 OREAD4(sc, OHCI_FM_REMAINING));
553 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n",
554 OREAD4(sc, OHCI_FM_NUMBER),
555 OREAD4(sc, OHCI_PERIODIC_START),
556 OREAD4(sc, OHCI_LS_THRESHOLD));
557 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n",
558 OREAD4(sc, OHCI_RH_DESCRIPTOR_A),
559 OREAD4(sc, OHCI_RH_DESCRIPTOR_B),
560 OREAD4(sc, OHCI_RH_STATUS));
561 printf(" port1=0x%08x port2=0x%08x\n",
562 OREAD4(sc, OHCI_RH_PORT_STATUS(1)),
563 OREAD4(sc, OHCI_RH_PORT_STATUS(2)));
564 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n",
565 LE(sc->sc_hcca->hcca_frame_number),
566 LE(sc->sc_hcca->hcca_done_head));
567 }
568 #endif
569
570 int
571 ohci_intr(p)
572 void *p;
573 {
574 ohci_softc_t *sc = p;
575 u_int32_t intrs, eintrs;
576 ohci_physaddr_t done;
577
578 /* In case the interrupt occurs before initialization has completed. */
579 if (sc->sc_hcca == NULL) {
580 #ifdef DIAGNOSTIC
581 printf("ohci_intr: sc->sc_hcca == NULL\n");
582 #endif
583 return (0);
584 }
585
586 done = LE(sc->sc_hcca->hcca_done_head);
587 if (done != 0) {
588 intrs = OHCI_WDH;
589 if (done & OHCI_DONE_INTRS)
590 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS);
591 } else
592 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS);
593 if (!intrs)
594 return (0);
595 intrs &= ~OHCI_MIE;
596 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */
597 eintrs = intrs & sc->sc_eintrs;
598 if (!eintrs)
599 return (0);
600
601 sc->sc_intrs++;
602 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n",
603 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS),
604 (u_int)eintrs));
605
606 if (eintrs & OHCI_SO) {
607 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev));
608 /* XXX do what */
609 intrs &= ~OHCI_SO;
610 }
611 if (eintrs & OHCI_WDH) {
612 ohci_process_done(sc, done &~ OHCI_DONE_INTRS);
613 sc->sc_hcca->hcca_done_head = 0;
614 intrs &= ~OHCI_WDH;
615 }
616 if (eintrs & OHCI_RD) {
617 /* XXX process resume detect */
618 }
619 if (eintrs & OHCI_UE) {
620 printf("%s: unrecoverable error, controller halted\n",
621 USBDEVNAME(sc->sc_bus.bdev));
622 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET);
623 /* XXX what else */
624 }
625 if (eintrs & OHCI_RHSC) {
626 ohci_rhsc(sc, sc->sc_intrreqh);
627 intrs &= ~OHCI_RHSC;
628
629 /*
630 * Disable RHSC interrupt for now, because it will be
631 * on until the port has been reset.
632 */
633 ohci_rhsc_able(sc, 0);
634 }
635
636 /* Block unprocessed interrupts. XXX */
637 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs);
638 sc->sc_eintrs &= ~intrs;
639
640 return (1);
641 }
642
643 void
644 ohci_rhsc_able(sc, on)
645 ohci_softc_t *sc;
646 int on;
647 {
648 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on));
649 if (on) {
650 sc->sc_eintrs |= OHCI_RHSC;
651 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC);
652 } else {
653 sc->sc_eintrs &= ~OHCI_RHSC;
654 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC);
655 }
656 }
657
658 #ifdef USB_DEBUG
659 char *ohci_cc_strs[] = {
660 "NO_ERROR",
661 "CRC",
662 "BIT_STUFFING",
663 "DATA_TOGGLE_MISMATCH",
664 "STALL",
665 "DEVICE_NOT_RESPONDING",
666 "PID_CHECK_FAILURE",
667 "UNEXPECTED_PID",
668 "DATA_OVERRUN",
669 "DATA_UNDERRUN",
670 "BUFFER_OVERRUN",
671 "BUFFER_UNDERRUN",
672 "NOT_ACCESSED",
673 };
674 #endif
675
676 void
677 ohci_process_done(sc, done)
678 ohci_softc_t *sc;
679 ohci_physaddr_t done;
680 {
681 ohci_soft_td_t *std, *sdone;
682 usbd_request_handle reqh;
683 int len, cc;
684
685 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done));
686
687 /* Reverse the done list. */
688 for (sdone = 0; done; done = LE(std->td->td_nexttd)) {
689 std = ohci_hash_find_td(sc, done);
690 std->dnext = sdone;
691 sdone = std;
692 }
693
694 #ifdef USB_DEBUG
695 if (ohcidebug > 10) {
696 printf("ohci_process_done: TD done:\n");
697 ohci_dump_tds(sdone);
698 }
699 #endif
700
701 for (std = sdone; std; std = std->dnext) {
702 reqh = std->reqh;
703 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh));
704 cc = OHCI_TD_GET_CC(LE(std->td->td_flags));
705 if (cc == OHCI_CC_NO_ERROR) {
706 if (std->td->td_cbp == 0)
707 len = std->len;
708 else
709 len = LE(std->td->td_be) -
710 LE(std->td->td_cbp) + 1;
711 reqh->actlen += len;
712 reqh->status = USBD_NORMAL_COMPLETION;
713 /*
714 * Only do a callback on the last stage of a transfer.
715 * Others have hcpriv = 0.
716 */
717 if (reqh->hcpriv == std)
718 ohci_ii_done(sc, reqh);
719 } else {
720 ohci_soft_td_t *p, *n;
721 struct ohci_pipe *opipe =
722 (struct ohci_pipe *)reqh->pipe;
723 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n",
724 OHCI_TD_GET_CC(LE(std->td->td_flags)),
725 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))]));
726 /*
727 * Endpoint is halted. First unlink all the TDs
728 * belonging to the failed transfer, and then restart
729 * the endpoint.
730 */
731 for (p = std->nexttd; p->reqh == reqh; p = n) {
732 n = p->nexttd;
733 ohci_hash_rem_td(sc, p);
734 ohci_free_std(sc, p);
735 }
736 /* clear halt */
737 opipe->sed->ed->ed_headp = LE(p->physaddr);
738 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
739
740 if (cc == OHCI_CC_STALL)
741 reqh->status = USBD_STALLED;
742 else
743 reqh->status = USBD_IOERROR;
744 ohci_ii_done(sc, reqh);
745 }
746 ohci_hash_rem_td(sc, std);
747 ohci_free_std(sc, std);
748 }
749 }
750
751 void
752 ohci_ii_done(sc, reqh)
753 ohci_softc_t *sc;
754 usbd_request_handle reqh;
755 {
756 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
757 case UE_CONTROL:
758 ohci_ctrl_done(sc, reqh);
759 usb_start_next(reqh->pipe);
760 break;
761 case UE_INTERRUPT:
762 ohci_intr_done(sc, reqh);
763 break;
764 case UE_BULK:
765 ohci_bulk_done(sc, reqh);
766 usb_start_next(reqh->pipe);
767 break;
768 case UE_ISOCHRONOUS:
769 printf("ohci_process_done: ISO done?\n");
770 usb_start_next(reqh->pipe);
771 break;
772 }
773
774 /* And finally execute callback. */
775 reqh->xfercb(reqh);
776 }
777
778 void
779 ohci_ctrl_done(sc, reqh)
780 ohci_softc_t *sc;
781 usbd_request_handle reqh;
782 {
783 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
784 u_int len = opipe->u.ctl.length;
785 usb_dma_t *dma;
786
787 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh));
788
789 if (!reqh->isreq) {
790 panic("ohci_ctrl_done: not a request\n");
791 return;
792 }
793
794 if (len != 0) {
795 dma = &opipe->u.ctl.datadma;
796 if (reqh->request.bmRequestType & UT_READ)
797 memcpy(reqh->buffer, KERNADDR(dma), len);
798 usb_freemem(sc->sc_dmatag, dma);
799 }
800 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
801 }
802
803 void
804 ohci_intr_done(sc, reqh)
805 ohci_softc_t *sc;
806 usbd_request_handle reqh;
807 {
808 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
809 usb_dma_t *dma;
810 ohci_soft_ed_t *sed = opipe->sed;
811 ohci_soft_td_t *xfer, *tail;
812
813
814 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n",
815 reqh, reqh->actlen));
816
817 dma = &opipe->u.intr.datadma;
818 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
819
820 if (reqh->pipe->intrreqh == reqh) {
821 xfer = opipe->tail;
822 tail = ohci_alloc_std(sc); /* XXX should reuse TD */
823 if (!tail) {
824 reqh->status = USBD_NOMEM;
825 return;
826 }
827 tail->reqh = 0;
828
829 xfer->td->td_flags = LE(
830 OHCI_TD_IN | OHCI_TD_NOCC |
831 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
832 xfer->td->td_cbp = LE(DMAADDR(dma));
833 xfer->nexttd = tail;
834 xfer->td->td_nexttd = LE(tail->physaddr);
835 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1);
836 xfer->len = reqh->length;
837 xfer->reqh = reqh;
838
839 reqh->actlen = 0;
840 reqh->hcpriv = xfer;
841
842 ohci_hash_add_td(sc, xfer);
843 sed->ed->ed_tailp = LE(tail->physaddr);
844 opipe->tail = tail;
845 } else {
846 usb_freemem(sc->sc_dmatag, dma);
847 usb_start_next(reqh->pipe);
848 }
849 }
850
851 void
852 ohci_bulk_done(sc, reqh)
853 ohci_softc_t *sc;
854 usbd_request_handle reqh;
855 {
856 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
857 usb_dma_t *dma;
858
859
860 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n",
861 reqh, reqh->actlen));
862
863 dma = &opipe->u.bulk.datadma;
864 if (reqh->request.bmRequestType & UT_READ)
865 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen);
866 usb_freemem(sc->sc_dmatag, dma);
867 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle);
868 }
869
870 void
871 ohci_rhsc(sc, reqh)
872 ohci_softc_t *sc;
873 usbd_request_handle reqh;
874 {
875 usbd_pipe_handle pipe;
876 struct ohci_pipe *opipe;
877 u_char *p;
878 int i, m;
879 int hstatus;
880
881 hstatus = OREAD4(sc, OHCI_RH_STATUS);
882 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n",
883 sc, reqh, hstatus));
884
885 if (reqh == 0) {
886 /* Just ignore the change. */
887 return;
888 }
889
890 pipe = reqh->pipe;
891 opipe = (struct ohci_pipe *)pipe;
892
893 p = KERNADDR(&opipe->u.intr.datadma);
894 m = min(sc->sc_noport, reqh->length * 8 - 1);
895 memset(p, 0, reqh->length);
896 for (i = 1; i <= m; i++) {
897 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16)
898 p[i/8] |= 1 << (i%8);
899 }
900 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p));
901 reqh->actlen = reqh->length;
902 reqh->status = USBD_NORMAL_COMPLETION;
903 reqh->xfercb(reqh);
904
905 if (reqh->pipe->intrreqh != reqh) {
906 sc->sc_intrreqh = 0;
907 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma);
908 usb_start_next(reqh->pipe);
909 }
910 }
911
912 /*
913 * Wait here until controller claims to have an interrupt.
914 * Then call ohci_intr and return. Use timeout to avoid waiting
915 * too long.
916 */
917 void
918 ohci_waitintr(sc, reqh)
919 ohci_softc_t *sc;
920 usbd_request_handle reqh;
921 {
922 int timo = reqh->timeout;
923 int usecs;
924 u_int32_t intrs;
925
926 reqh->status = USBD_IN_PROGRESS;
927 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
928 usbd_delay_ms(&sc->sc_bus, 1);
929 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs;
930 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs));
931 #ifdef USB_DEBUG
932 if (ohcidebug > 15)
933 ohci_dumpregs(sc);
934 #endif
935 if (intrs) {
936 ohci_intr(sc);
937 if (reqh->status != USBD_IN_PROGRESS)
938 return;
939 }
940 }
941
942 /* Timeout */
943 DPRINTF(("ohci_waitintr: timeout\n"));
944 reqh->status = USBD_TIMEOUT;
945 ohci_ii_done(sc, reqh);
946 /* XXX should free TD */
947 }
948
949 void
950 ohci_poll(bus)
951 struct usbd_bus *bus;
952 {
953 ohci_softc_t *sc = (ohci_softc_t *)bus;
954
955 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs)
956 ohci_intr(sc);
957 }
958
959 usbd_status
960 ohci_device_request(reqh)
961 usbd_request_handle reqh;
962 {
963 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
964 usb_device_request_t *req = &reqh->request;
965 usbd_device_handle dev = opipe->pipe.device;
966 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
967 int addr = dev->address;
968 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail;
969 ohci_soft_ed_t *sed;
970 usb_dma_t *dmap;
971 int isread;
972 int len;
973 usbd_status r;
974 int s;
975
976 isread = req->bmRequestType & UT_READ;
977 len = UGETW(req->wLength);
978
979 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, "
980 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
981 req->bmRequestType, req->bRequest, UGETW(req->wValue),
982 UGETW(req->wIndex), len, addr,
983 opipe->pipe.endpoint->edesc->bEndpointAddress));
984
985 setup = opipe->tail;
986 stat = ohci_alloc_std(sc);
987 if (!stat) {
988 r = USBD_NOMEM;
989 goto bad1;
990 }
991 tail = ohci_alloc_std(sc);
992 if (!tail) {
993 r = USBD_NOMEM;
994 goto bad2;
995 }
996 tail->reqh = 0;
997
998 sed = opipe->sed;
999 dmap = &opipe->u.ctl.datadma;
1000 opipe->u.ctl.length = len;
1001
1002 /* Update device address and length since they may have changed. */
1003 /* XXX This only needs to be done once, but it's too early in open. */
1004 sed->ed->ed_flags = LE(
1005 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) |
1006 OHCI_ED_SET_FA(addr) |
1007 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize)));
1008
1009 /* Set up data transaction */
1010 if (len != 0) {
1011 xfer = ohci_alloc_std(sc);
1012 if (!xfer) {
1013 r = USBD_NOMEM;
1014 goto bad3;
1015 }
1016 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1017 if (r != USBD_NORMAL_COMPLETION)
1018 goto bad4;
1019 xfer->td->td_flags = LE(
1020 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1021 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR);
1022 xfer->td->td_cbp = LE(DMAADDR(dmap));
1023 xfer->nexttd = stat;
1024 xfer->td->td_nexttd = LE(stat->physaddr);
1025 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
1026 xfer->len = len;
1027 xfer->reqh = reqh;
1028
1029 next = xfer;
1030 } else
1031 next = stat;
1032
1033 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req);
1034 if (!isread && len != 0)
1035 memcpy(KERNADDR(dmap), reqh->buffer, len);
1036
1037 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC |
1038 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR);
1039 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma));
1040 setup->nexttd = next;
1041 setup->td->td_nexttd = LE(next->physaddr);
1042 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1);
1043 setup->len = 0; /* XXX The number of byte we count */
1044 setup->reqh = reqh;
1045
1046 stat->td->td_flags = LE(
1047 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC |
1048 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1));
1049 stat->td->td_cbp = 0;
1050 stat->nexttd = tail;
1051 stat->td->td_nexttd = LE(tail->physaddr);
1052 stat->td->td_be = 0;
1053 stat->len = 0;
1054 stat->reqh = reqh;
1055
1056 reqh->actlen = 0;
1057 reqh->hcpriv = stat;
1058
1059 #if USB_DEBUG
1060 if (ohcidebug > 5) {
1061 printf("ohci_device_request:\n");
1062 ohci_dump_ed(sed);
1063 ohci_dump_tds(setup);
1064 }
1065 #endif
1066
1067 /* Insert ED in schedule */
1068 s = splusb();
1069 ohci_hash_add_td(sc, setup);
1070 if (len != 0)
1071 ohci_hash_add_td(sc, xfer);
1072 ohci_hash_add_td(sc, stat);
1073 sed->ed->ed_tailp = LE(tail->physaddr);
1074 opipe->tail = tail;
1075 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF);
1076 if (reqh->timeout && !sc->sc_bus.use_polling) {
1077 usb_timeout(ohci_timeout, reqh,
1078 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
1079 }
1080 splx(s);
1081
1082 #if USB_DEBUG
1083 if (ohcidebug > 5) {
1084 delay(5000);
1085 printf("ohci_device_request: status=%x\n",
1086 OREAD4(sc, OHCI_COMMAND_STATUS));
1087 ohci_dump_ed(sed);
1088 ohci_dump_tds(setup);
1089 }
1090 #endif
1091
1092 return (USBD_NORMAL_COMPLETION);
1093
1094 bad4:
1095 ohci_free_std(sc, xfer);
1096 bad3:
1097 ohci_free_std(sc, tail);
1098 bad2:
1099 ohci_free_std(sc, stat);
1100 bad1:
1101 return (r);
1102 }
1103
1104 /*
1105 * Add an ED to the schedule. Called at splusb().
1106 */
1107 void
1108 ohci_add_ed(sed, head)
1109 ohci_soft_ed_t *sed;
1110 ohci_soft_ed_t *head;
1111 {
1112 sed->next = head->next;
1113 sed->ed->ed_nexted = head->ed->ed_nexted;
1114 head->next = sed;
1115 head->ed->ed_nexted = LE(sed->physaddr);
1116 }
1117
1118 /*
1119 * Remove an ED from the schedule. Called at splusb().
1120 */
1121 void
1122 ohci_rem_ed(sed, head)
1123 ohci_soft_ed_t *sed;
1124 ohci_soft_ed_t *head;
1125 {
1126 ohci_soft_ed_t *p;
1127
1128 /* XXX */
1129 for (p = head; p && p->next != sed; p = p->next)
1130 ;
1131 if (!p)
1132 panic("ohci_rem_ed: ED not found\n");
1133 p->next = sed->next;
1134 p->ed->ed_nexted = sed->ed->ed_nexted;
1135 }
1136
1137 /*
1138 * When a transfer is completed the TD is added to the done queue by
1139 * the host controller. This queue is the processed by software.
1140 * Unfortunately the queue contains the physical address of the TD
1141 * and we have no simple way to translate this back to a kernel address.
1142 * To make the translation possible (and fast) we use a hash table of
1143 * TDs currently in the schedule. The physical address is used as the
1144 * hash value.
1145 */
1146
1147 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE)
1148 /* Called at splusb() */
1149 void
1150 ohci_hash_add_td(sc, std)
1151 ohci_softc_t *sc;
1152 ohci_soft_td_t *std;
1153 {
1154 int h = HASH(std->physaddr);
1155
1156 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext);
1157 }
1158
1159 /* Called at splusb() */
1160 void
1161 ohci_hash_rem_td(sc, std)
1162 ohci_softc_t *sc;
1163 ohci_soft_td_t *std;
1164 {
1165 LIST_REMOVE(std, hnext);
1166 }
1167
1168 ohci_soft_td_t *
1169 ohci_hash_find_td(sc, a)
1170 ohci_softc_t *sc;
1171 ohci_physaddr_t a;
1172 {
1173 int h = HASH(a);
1174 ohci_soft_td_t *std;
1175
1176 for (std = LIST_FIRST(&sc->sc_hash_tds[h]);
1177 std != 0;
1178 std = LIST_NEXT(std, hnext))
1179 if (std->physaddr == a)
1180 return (std);
1181 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a);
1182 }
1183
1184 void
1185 ohci_timeout(addr)
1186 void *addr;
1187 {
1188 #if 0
1189 usbd_request_handle *reqh = addr;
1190 int s;
1191
1192 DPRINTF(("ohci_timeout: reqh=%p\n", reqh));
1193 s = splusb();
1194 /* XXX need to inactivate TD before calling interrupt routine */
1195 ohci_XXX_done(reqh);
1196 splx(s);
1197 #endif
1198 }
1199
1200 #ifdef USB_DEBUG
1201 void
1202 ohci_dump_tds(std)
1203 ohci_soft_td_t *std;
1204 {
1205 for (; std; std = std->nexttd)
1206 ohci_dump_td(std);
1207 }
1208
1209 void
1210 ohci_dump_td(std)
1211 ohci_soft_td_t *std;
1212 {
1213 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx "
1214 "nexttd=0x%08lx be=0x%08lx\n",
1215 std, (u_long)std->physaddr,
1216 (u_long)LE(std->td->td_flags),
1217 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE",
1218 OHCI_TD_GET_DI(LE(std->td->td_flags)),
1219 OHCI_TD_GET_EC(LE(std->td->td_flags)),
1220 OHCI_TD_GET_CC(LE(std->td->td_flags)),
1221 (u_long)LE(std->td->td_cbp),
1222 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be));
1223 }
1224
1225 void
1226 ohci_dump_ed(sed)
1227 ohci_soft_ed_t *sed;
1228 {
1229 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx "
1230 "headp=%b nexted=0x%08lx\n",
1231 sed, (u_long)sed->physaddr,
1232 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)),
1233 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)),
1234 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)),
1235 (u_long)LE(sed->ed->ed_flags),
1236 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO",
1237 (u_long)LE(sed->ed->ed_tailp),
1238 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY",
1239 (u_long)LE(sed->ed->ed_nexted));
1240 }
1241 #endif
1242
1243 usbd_status
1244 ohci_open(pipe)
1245 usbd_pipe_handle pipe;
1246 {
1247 usbd_device_handle dev = pipe->device;
1248 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1249 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1250 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1251 u_int8_t addr = dev->address;
1252 ohci_soft_ed_t *sed;
1253 ohci_soft_td_t *std;
1254 usbd_status r;
1255 int s;
1256
1257 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1258 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1259 if (addr == sc->sc_addr) {
1260 switch (ed->bEndpointAddress) {
1261 case USB_CONTROL_ENDPOINT:
1262 pipe->methods = &ohci_root_ctrl_methods;
1263 break;
1264 case UE_IN | OHCI_INTR_ENDPT:
1265 pipe->methods = &ohci_root_intr_methods;
1266 break;
1267 default:
1268 return (USBD_INVAL);
1269 }
1270 } else {
1271 sed = ohci_alloc_sed(sc);
1272 if (sed == 0)
1273 goto bad0;
1274 std = ohci_alloc_std(sc);
1275 if (std == 0)
1276 goto bad1;
1277 opipe->sed = sed;
1278 opipe->tail = std;
1279 sed->ed->ed_flags = LE(
1280 OHCI_ED_SET_FA(addr) |
1281 OHCI_ED_SET_EN(ed->bEndpointAddress) |
1282 OHCI_ED_DIR_TD |
1283 (dev->lowspeed ? OHCI_ED_SPEED : 0) |
1284 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ?
1285 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) |
1286 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize)));
1287 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr);
1288
1289 switch (ed->bmAttributes & UE_XFERTYPE) {
1290 case UE_CONTROL:
1291 pipe->methods = &ohci_device_ctrl_methods;
1292 r = usb_allocmem(sc->sc_dmatag,
1293 sizeof(usb_device_request_t),
1294 0, &opipe->u.ctl.reqdma);
1295 if (r != USBD_NORMAL_COMPLETION)
1296 goto bad;
1297 s = splusb();
1298 ohci_add_ed(sed, sc->sc_ctrl_head);
1299 splx(s);
1300 break;
1301 case UE_INTERRUPT:
1302 pipe->methods = &ohci_device_intr_methods;
1303 return (ohci_device_setintr(sc, opipe, ed->bInterval));
1304 case UE_ISOCHRONOUS:
1305 printf("ohci_open: open iso unimplemented\n");
1306 return (USBD_XXX);
1307 case UE_BULK:
1308 pipe->methods = &ohci_device_bulk_methods;
1309 s = splusb();
1310 ohci_add_ed(sed, sc->sc_bulk_head);
1311 splx(s);
1312 break;
1313 }
1314 }
1315 return (USBD_NORMAL_COMPLETION);
1316
1317 bad:
1318 ohci_free_std(sc, std);
1319 bad1:
1320 ohci_free_sed(sc, sed);
1321 bad0:
1322 return (USBD_NOMEM);
1323
1324 }
1325
1326 /*
1327 * Data structures and routines to emulate the root hub.
1328 */
1329 usb_device_descriptor_t ohci_devd = {
1330 USB_DEVICE_DESCRIPTOR_SIZE,
1331 UDESC_DEVICE, /* type */
1332 {0x00, 0x01}, /* USB version */
1333 UCLASS_HUB, /* class */
1334 USUBCLASS_HUB, /* subclass */
1335 0, /* protocol */
1336 64, /* max packet */
1337 {0},{0},{0x00,0x01}, /* device id */
1338 1,2,0, /* string indicies */
1339 1 /* # of configurations */
1340 };
1341
1342 usb_config_descriptor_t ohci_confd = {
1343 USB_CONFIG_DESCRIPTOR_SIZE,
1344 UDESC_CONFIG,
1345 {USB_CONFIG_DESCRIPTOR_SIZE +
1346 USB_INTERFACE_DESCRIPTOR_SIZE +
1347 USB_ENDPOINT_DESCRIPTOR_SIZE},
1348 1,
1349 1,
1350 0,
1351 UC_SELF_POWERED,
1352 0 /* max power */
1353 };
1354
1355 usb_interface_descriptor_t ohci_ifcd = {
1356 USB_INTERFACE_DESCRIPTOR_SIZE,
1357 UDESC_INTERFACE,
1358 0,
1359 0,
1360 1,
1361 UCLASS_HUB,
1362 USUBCLASS_HUB,
1363 0,
1364 0
1365 };
1366
1367 usb_endpoint_descriptor_t ohci_endpd = {
1368 USB_ENDPOINT_DESCRIPTOR_SIZE,
1369 UDESC_ENDPOINT,
1370 UE_IN | OHCI_INTR_ENDPT,
1371 UE_INTERRUPT,
1372 {8, 0}, /* max packet */
1373 255
1374 };
1375
1376 usb_hub_descriptor_t ohci_hubd = {
1377 USB_HUB_DESCRIPTOR_SIZE,
1378 UDESC_HUB,
1379 0,
1380 {0,0},
1381 0,
1382 0,
1383 {0},
1384 };
1385
1386 int
1387 ohci_str(p, l, s)
1388 usb_string_descriptor_t *p;
1389 int l;
1390 char *s;
1391 {
1392 int i;
1393
1394 if (l == 0)
1395 return (0);
1396 p->bLength = 2 * strlen(s) + 2;
1397 if (l == 1)
1398 return (1);
1399 p->bDescriptorType = UDESC_STRING;
1400 l -= 2;
1401 for (i = 0; s[i] && l > 1; i++, l -= 2)
1402 USETW2(p->bString[i], 0, s[i]);
1403 return (2*i+2);
1404 }
1405
1406 /*
1407 * Simulate a hardware hub by handling all the necessary requests.
1408 */
1409 usbd_status
1410 ohci_root_ctrl_transfer(reqh)
1411 usbd_request_handle reqh;
1412 {
1413 int s;
1414 usbd_status r;
1415
1416 s = splusb();
1417 r = usb_insert_transfer(reqh);
1418 splx(s);
1419 if (r != USBD_NORMAL_COMPLETION)
1420 return (r);
1421 else
1422 return (ohci_root_ctrl_start(reqh));
1423 }
1424
1425 usbd_status
1426 ohci_root_ctrl_start(reqh)
1427 usbd_request_handle reqh;
1428 {
1429 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1430 usb_device_request_t *req;
1431 void *buf;
1432 int port, i;
1433 int len, value, index, l, totlen = 0;
1434 usb_port_status_t ps;
1435 usb_hub_descriptor_t hubd;
1436 usbd_status r;
1437 u_int32_t v;
1438
1439 if (!reqh->isreq)
1440 /* XXX panic */
1441 return (USBD_INVAL);
1442 req = &reqh->request;
1443 buf = reqh->buffer;
1444
1445 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n",
1446 req->bmRequestType, req->bRequest));
1447
1448 len = UGETW(req->wLength);
1449 value = UGETW(req->wValue);
1450 index = UGETW(req->wIndex);
1451 #define C(x,y) ((x) | ((y) << 8))
1452 switch(C(req->bRequest, req->bmRequestType)) {
1453 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1454 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1455 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1456 /*
1457 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1458 * for the integrated root hub.
1459 */
1460 break;
1461 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1462 if (len > 0) {
1463 *(u_int8_t *)buf = sc->sc_conf;
1464 totlen = 1;
1465 }
1466 break;
1467 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1468 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value));
1469 switch(value >> 8) {
1470 case UDESC_DEVICE:
1471 if ((value & 0xff) != 0) {
1472 r = USBD_IOERROR;
1473 goto ret;
1474 }
1475 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1476 memcpy(buf, &ohci_devd, l);
1477 break;
1478 case UDESC_CONFIG:
1479 if ((value & 0xff) != 0) {
1480 r = USBD_IOERROR;
1481 goto ret;
1482 }
1483 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1484 memcpy(buf, &ohci_confd, l);
1485 buf = (char *)buf + l;
1486 len -= l;
1487 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1488 totlen += l;
1489 memcpy(buf, &ohci_ifcd, l);
1490 buf = (char *)buf + l;
1491 len -= l;
1492 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1493 totlen += l;
1494 memcpy(buf, &ohci_endpd, l);
1495 break;
1496 case UDESC_STRING:
1497 if (len == 0)
1498 break;
1499 *(u_int8_t *)buf = 0;
1500 totlen = 1;
1501 switch (value & 0xff) {
1502 case 1: /* Vendor */
1503 totlen = ohci_str(buf, len, sc->sc_vendor);
1504 break;
1505 case 2: /* Product */
1506 totlen = ohci_str(buf, len, "OHCI root hub");
1507 break;
1508 }
1509 break;
1510 default:
1511 r = USBD_IOERROR;
1512 goto ret;
1513 }
1514 break;
1515 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1516 if (len > 0) {
1517 *(u_int8_t *)buf = 0;
1518 totlen = 1;
1519 }
1520 break;
1521 case C(UR_GET_STATUS, UT_READ_DEVICE):
1522 if (len > 1) {
1523 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1524 totlen = 2;
1525 }
1526 break;
1527 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1528 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1529 if (len > 1) {
1530 USETW(((usb_status_t *)buf)->wStatus, 0);
1531 totlen = 2;
1532 }
1533 break;
1534 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1535 if (value >= USB_MAX_DEVICES) {
1536 r = USBD_IOERROR;
1537 goto ret;
1538 }
1539 sc->sc_addr = value;
1540 break;
1541 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1542 if (value != 0 && value != 1) {
1543 r = USBD_IOERROR;
1544 goto ret;
1545 }
1546 sc->sc_conf = value;
1547 break;
1548 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1549 break;
1550 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1551 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1552 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1553 r = USBD_IOERROR;
1554 goto ret;
1555 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1556 break;
1557 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1558 break;
1559 /* Hub requests */
1560 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1561 break;
1562 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1563 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
1564 "port=%d feature=%d\n",
1565 index, value));
1566 if (index < 1 || index > sc->sc_noport) {
1567 r = USBD_IOERROR;
1568 goto ret;
1569 }
1570 port = OHCI_RH_PORT_STATUS(index);
1571 switch(value) {
1572 case UHF_PORT_ENABLE:
1573 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS);
1574 break;
1575 case UHF_PORT_SUSPEND:
1576 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR);
1577 break;
1578 case UHF_PORT_POWER:
1579 OWRITE4(sc, port, UPS_LOW_SPEED);
1580 break;
1581 case UHF_C_PORT_CONNECTION:
1582 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16);
1583 break;
1584 case UHF_C_PORT_ENABLE:
1585 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16);
1586 break;
1587 case UHF_C_PORT_SUSPEND:
1588 OWRITE4(sc, port, UPS_C_SUSPEND << 16);
1589 break;
1590 case UHF_C_PORT_OVER_CURRENT:
1591 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16);
1592 break;
1593 case UHF_C_PORT_RESET:
1594 OWRITE4(sc, port, UPS_C_PORT_RESET << 16);
1595 break;
1596 default:
1597 r = USBD_IOERROR;
1598 goto ret;
1599 }
1600 switch(value) {
1601 case UHF_C_PORT_CONNECTION:
1602 case UHF_C_PORT_ENABLE:
1603 case UHF_C_PORT_SUSPEND:
1604 case UHF_C_PORT_OVER_CURRENT:
1605 case UHF_C_PORT_RESET:
1606 /* Enable RHSC interrupt if condition is cleared. */
1607 if ((OREAD4(sc, port) >> 16) == 0)
1608 ohci_rhsc_able(sc, 1);
1609 break;
1610 default:
1611 break;
1612 }
1613 break;
1614 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1615 if (value != 0) {
1616 r = USBD_IOERROR;
1617 goto ret;
1618 }
1619 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A);
1620 hubd = ohci_hubd;
1621 hubd.bNbrPorts = sc->sc_noport;
1622 USETW(hubd.wHubCharacteristics,
1623 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH :
1624 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL)
1625 /* XXX overcurrent */
1626 );
1627 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v);
1628 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B);
1629 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1630 hubd.DeviceRemovable[i++] = (u_int8_t)v;
1631 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1632 l = min(len, hubd.bDescLength);
1633 totlen = l;
1634 memcpy(buf, &hubd, l);
1635 break;
1636 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1637 if (len != 4) {
1638 r = USBD_IOERROR;
1639 goto ret;
1640 }
1641 memset(buf, 0, len); /* ? XXX */
1642 totlen = len;
1643 break;
1644 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1645 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n",
1646 index));
1647 if (index < 1 || index > sc->sc_noport) {
1648 r = USBD_IOERROR;
1649 goto ret;
1650 }
1651 if (len != 4) {
1652 r = USBD_IOERROR;
1653 goto ret;
1654 }
1655 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index));
1656 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n",
1657 v));
1658 USETW(ps.wPortStatus, v);
1659 USETW(ps.wPortChange, v >> 16);
1660 l = min(len, sizeof ps);
1661 memcpy(buf, &ps, l);
1662 totlen = l;
1663 break;
1664 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1665 r = USBD_IOERROR;
1666 goto ret;
1667 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1668 break;
1669 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1670 if (index < 1 || index > sc->sc_noport) {
1671 r = USBD_IOERROR;
1672 goto ret;
1673 }
1674 port = OHCI_RH_PORT_STATUS(index);
1675 switch(value) {
1676 case UHF_PORT_ENABLE:
1677 OWRITE4(sc, port, UPS_PORT_ENABLED);
1678 break;
1679 case UHF_PORT_SUSPEND:
1680 OWRITE4(sc, port, UPS_SUSPEND);
1681 break;
1682 case UHF_PORT_RESET:
1683 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n",
1684 index));
1685 OWRITE4(sc, port, UPS_RESET);
1686 for (i = 0; i < 10; i++) {
1687 usbd_delay_ms(&sc->sc_bus, 10);
1688 if ((OREAD4(sc, port) & UPS_RESET) == 0)
1689 break;
1690 }
1691 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n",
1692 index, OREAD4(sc, port)));
1693 break;
1694 case UHF_PORT_POWER:
1695 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power "
1696 "%d\n", index));
1697 OWRITE4(sc, port, UPS_PORT_POWER);
1698 break;
1699 default:
1700 r = USBD_IOERROR;
1701 goto ret;
1702 }
1703 break;
1704 default:
1705 r = USBD_IOERROR;
1706 goto ret;
1707 }
1708 reqh->actlen = totlen;
1709 r = USBD_NORMAL_COMPLETION;
1710 ret:
1711 reqh->status = r;
1712 reqh->xfercb(reqh);
1713 usb_start_next(reqh->pipe);
1714 return (USBD_IN_PROGRESS);
1715 }
1716
1717 /* Abort a root control request. */
1718 void
1719 ohci_root_ctrl_abort(reqh)
1720 usbd_request_handle reqh;
1721 {
1722 /* Nothing to do, all transfers are synchronous. */
1723 }
1724
1725 /* Close the root pipe. */
1726 void
1727 ohci_root_ctrl_close(pipe)
1728 usbd_pipe_handle pipe;
1729 {
1730 DPRINTF(("ohci_root_ctrl_close\n"));
1731 }
1732
1733 usbd_status
1734 ohci_root_intr_transfer(reqh)
1735 usbd_request_handle reqh;
1736 {
1737 int s;
1738 usbd_status r;
1739
1740 s = splusb();
1741 r = usb_insert_transfer(reqh);
1742 splx(s);
1743 if (r != USBD_NORMAL_COMPLETION)
1744 return (r);
1745 else
1746 return (ohci_root_intr_start(reqh));
1747 }
1748
1749 usbd_status
1750 ohci_root_intr_start(reqh)
1751 usbd_request_handle reqh;
1752 {
1753 usbd_pipe_handle pipe = reqh->pipe;
1754 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1755 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe;
1756 usb_dma_t *dmap;
1757 usbd_status r;
1758 int len;
1759
1760 len = reqh->length;
1761 dmap = &upipe->u.intr.datadma;
1762 if (len == 0)
1763 return (USBD_INVAL); /* XXX should it be? */
1764
1765 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1766 if (r != USBD_NORMAL_COMPLETION)
1767 return (r);
1768 sc->sc_intrreqh = reqh;
1769
1770 return (USBD_IN_PROGRESS);
1771 }
1772
1773 /* Abort a root interrupt request. */
1774 void
1775 ohci_root_intr_abort(reqh)
1776 usbd_request_handle reqh;
1777 {
1778 /* No need to abort. */
1779 }
1780
1781 /* Close the root pipe. */
1782 void
1783 ohci_root_intr_close(pipe)
1784 usbd_pipe_handle pipe;
1785 {
1786 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1787 sc->sc_intrreqh = 0;
1788
1789 DPRINTF(("ohci_root_intr_close\n"));
1790 }
1791
1792 /************************/
1793
1794 usbd_status
1795 ohci_device_ctrl_transfer(reqh)
1796 usbd_request_handle reqh;
1797 {
1798 int s;
1799 usbd_status r;
1800
1801 s = splusb();
1802 r = usb_insert_transfer(reqh);
1803 splx(s);
1804 if (r != USBD_NORMAL_COMPLETION)
1805 return (r);
1806 else
1807 return (ohci_device_ctrl_start(reqh));
1808 }
1809
1810 usbd_status
1811 ohci_device_ctrl_start(reqh)
1812 usbd_request_handle reqh;
1813 {
1814 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus;
1815 usbd_status r;
1816
1817 if (!reqh->isreq) {
1818 /* XXX panic */
1819 printf("ohci_device_ctrl_transfer: not a request\n");
1820 return (USBD_INVAL);
1821 }
1822
1823 r = ohci_device_request(reqh);
1824 if (r != USBD_NORMAL_COMPLETION)
1825 return (r);
1826
1827 if (sc->sc_bus.use_polling)
1828 ohci_waitintr(sc, reqh);
1829 return (USBD_IN_PROGRESS);
1830 }
1831
1832 /* Abort a device control request. */
1833 void
1834 ohci_device_ctrl_abort(reqh)
1835 usbd_request_handle reqh;
1836 {
1837 /* XXX inactivate */
1838 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is donw */
1839 /* XXX call done */
1840 }
1841
1842 /* Close a device control pipe. */
1843 void
1844 ohci_device_ctrl_close(pipe)
1845 usbd_pipe_handle pipe;
1846 {
1847 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1848 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
1849 ohci_soft_ed_t *sed = opipe->sed;
1850 int s;
1851
1852 s = splusb();
1853 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
1854 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp))
1855 usbd_delay_ms(&sc->sc_bus, 2);
1856 ohci_rem_ed(sed, sc->sc_ctrl_head);
1857 splx(s);
1858 ohci_free_std(sc, opipe->tail);
1859 ohci_free_sed(sc, opipe->sed);
1860 /* XXX free other resources */
1861 }
1862
1863 /************************/
1864
1865 usbd_status
1866 ohci_device_bulk_transfer(reqh)
1867 usbd_request_handle reqh;
1868 {
1869 int s;
1870 usbd_status r;
1871
1872 s = splusb();
1873 r = usb_insert_transfer(reqh);
1874 splx(s);
1875 if (r != USBD_NORMAL_COMPLETION)
1876 return (r);
1877 else
1878 return (ohci_device_bulk_start(reqh));
1879 }
1880
1881 usbd_status
1882 ohci_device_bulk_start(reqh)
1883 usbd_request_handle reqh;
1884 {
1885 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
1886 usbd_device_handle dev = opipe->pipe.device;
1887 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1888 int addr = dev->address;
1889 ohci_soft_td_t *xfer, *tail;
1890 ohci_soft_ed_t *sed;
1891 usb_dma_t *dmap;
1892 usbd_status r;
1893 int s, len, isread;
1894
1895 if (reqh->isreq) {
1896 /* XXX panic */
1897 printf("ohci_device_bulk_transfer: a request\n");
1898 return (USBD_INVAL);
1899 }
1900
1901 len = reqh->length;
1902 dmap = &opipe->u.bulk.datadma;
1903 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN;
1904 sed = opipe->sed;
1905
1906 opipe->u.bulk.length = len;
1907
1908 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
1909 if (r != USBD_NORMAL_COMPLETION)
1910 goto ret1;
1911
1912 tail = ohci_alloc_std(sc);
1913 if (!tail) {
1914 r = USBD_NOMEM;
1915 goto ret2;
1916 }
1917 tail->reqh = 0;
1918
1919 /* Update device address */
1920 sed->ed->ed_flags = LE(
1921 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) |
1922 OHCI_ED_SET_FA(addr));
1923
1924 /* Set up data transaction */
1925 xfer = opipe->tail;
1926 xfer->td->td_flags = LE(
1927 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC |
1928 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
1929 xfer->td->td_cbp = LE(DMAADDR(dmap));
1930 xfer->nexttd = tail;
1931 xfer->td->td_nexttd = LE(tail->physaddr);
1932 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
1933 xfer->len = len;
1934 xfer->reqh = reqh;
1935
1936 reqh->actlen = 0;
1937 reqh->hcpriv = xfer;
1938
1939 if (!isread)
1940 memcpy(KERNADDR(dmap), reqh->buffer, len);
1941
1942 /* Insert ED in schedule */
1943 s = splusb();
1944 ohci_hash_add_td(sc, xfer);
1945 sed->ed->ed_tailp = LE(tail->physaddr);
1946 opipe->tail = tail;
1947 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF);
1948 if (reqh->timeout && !sc->sc_bus.use_polling) {
1949 usb_timeout(ohci_timeout, reqh,
1950 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
1951 }
1952 splx(s);
1953
1954 return (USBD_IN_PROGRESS);
1955
1956 ret2:
1957 usb_freemem(sc->sc_dmatag, dmap);
1958 ret1:
1959 return (r);
1960 }
1961
1962 /* Abort a device bulk request. */
1963 void
1964 ohci_device_bulk_abort(reqh)
1965 usbd_request_handle reqh;
1966 {
1967 #if 0
1968 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
1969 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp))
1970 usbd_delay_ms(reqh->pipe->device->bus, 2);
1971 #endif
1972 /* XXX inactivate */
1973 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */
1974 /* XXX call done */
1975 }
1976
1977 /* Close a device bulk pipe. */
1978 void
1979 ohci_device_bulk_close(pipe)
1980 usbd_pipe_handle pipe;
1981 {
1982 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
1983 usbd_device_handle dev = opipe->pipe.device;
1984 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
1985 int s;
1986
1987 s = splusb();
1988 ohci_rem_ed(opipe->sed, sc->sc_bulk_head);
1989 splx(s);
1990 ohci_free_std(sc, opipe->tail);
1991 ohci_free_sed(sc, opipe->sed);
1992 /* XXX free other resources */
1993 }
1994
1995 /************************/
1996
1997 usbd_status
1998 ohci_device_intr_transfer(reqh)
1999 usbd_request_handle reqh;
2000 {
2001 int s;
2002 usbd_status r;
2003
2004 s = splusb();
2005 r = usb_insert_transfer(reqh);
2006 splx(s);
2007 if (r != USBD_NORMAL_COMPLETION)
2008 return (r);
2009 else
2010 return (ohci_device_intr_start(reqh));
2011 }
2012
2013 usbd_status
2014 ohci_device_intr_start(reqh)
2015 usbd_request_handle reqh;
2016 {
2017 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe;
2018 usbd_device_handle dev = opipe->pipe.device;
2019 ohci_softc_t *sc = (ohci_softc_t *)dev->bus;
2020 ohci_soft_ed_t *sed = opipe->sed;
2021 ohci_soft_td_t *xfer, *tail;
2022 usb_dma_t *dmap;
2023 usbd_status r;
2024 int len;
2025 int s;
2026
2027 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d "
2028 "flags=%d priv=%p\n",
2029 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv));
2030
2031 if (reqh->isreq)
2032 panic("ohci_device_intr_transfer: a request\n");
2033
2034 len = reqh->length;
2035 dmap = &opipe->u.intr.datadma;
2036 if (len == 0)
2037 return (USBD_INVAL); /* XXX should it be? */
2038
2039 xfer = opipe->tail;
2040 tail = ohci_alloc_std(sc);
2041 if (!tail) {
2042 r = USBD_NOMEM;
2043 goto ret1;
2044 }
2045 tail->reqh = 0;
2046
2047 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap);
2048 if (r != USBD_NORMAL_COMPLETION)
2049 goto ret2;
2050
2051 xfer->td->td_flags = LE(
2052 OHCI_TD_IN | OHCI_TD_NOCC |
2053 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY);
2054 xfer->td->td_cbp = LE(DMAADDR(dmap));
2055 xfer->nexttd = tail;
2056 xfer->td->td_nexttd = LE(tail->physaddr);
2057 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1);
2058 xfer->len = len;
2059 xfer->reqh = reqh;
2060
2061 reqh->actlen = 0;
2062 reqh->hcpriv = xfer;
2063
2064 #if USB_DEBUG
2065 if (ohcidebug > 5) {
2066 printf("ohci_device_intr_transfer:\n");
2067 ohci_dump_ed(sed);
2068 ohci_dump_tds(xfer);
2069 }
2070 #endif
2071
2072 /* Insert ED in schedule */
2073 s = splusb();
2074 ohci_hash_add_td(sc, xfer);
2075 sed->ed->ed_tailp = LE(tail->physaddr);
2076 opipe->tail = tail;
2077 #if 0
2078 if (reqh->timeout && !sc->sc_bus.use_polling) {
2079 usb_timeout(ohci_timeout, reqh,
2080 MS_TO_TICKS(reqh->timeout), reqh->timo_handle);
2081 }
2082 #endif
2083 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP);
2084 splx(s);
2085
2086 #ifdef USB_DEBUG
2087 if (ohcidebug > 5) {
2088 delay(5000);
2089 printf("ohci_device_intr_transfer: status=%x\n",
2090 OREAD4(sc, OHCI_COMMAND_STATUS));
2091 ohci_dump_ed(sed);
2092 ohci_dump_tds(xfer);
2093 }
2094 #endif
2095
2096 return (USBD_IN_PROGRESS);
2097
2098 ret2:
2099 ohci_free_std(sc, xfer);
2100 ret1:
2101 return (r);
2102 }
2103
2104 /* Abort a device control request. */
2105 void
2106 ohci_device_intr_abort(reqh)
2107 usbd_request_handle reqh;
2108 {
2109 /* XXX inactivate */
2110 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */
2111 if (reqh->pipe->intrreqh == reqh) {
2112 DPRINTF(("ohci_device_intr_abort: remove\n"));
2113 reqh->pipe->intrreqh = 0;
2114 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh);
2115 }
2116 }
2117
2118 /* Close a device interrupt pipe. */
2119 void
2120 ohci_device_intr_close(pipe)
2121 usbd_pipe_handle pipe;
2122 {
2123 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe;
2124 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus;
2125 int nslots = opipe->u.intr.nslots;
2126 int pos = opipe->u.intr.pos;
2127 int j;
2128 ohci_soft_ed_t *p, *sed = opipe->sed;
2129 int s;
2130
2131 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n",
2132 pipe, nslots, pos));
2133 s = splusb();
2134 sed->ed->ed_flags |= LE(OHCI_ED_SKIP);
2135 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) != sed->ed->ed_headp)
2136 usbd_delay_ms(&sc->sc_bus, 2);
2137
2138 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next)
2139 ;
2140 if (!p)
2141 panic("ohci_device_intr_close: ED not found\n");
2142 p->next = sed->next;
2143 p->ed->ed_nexted = sed->ed->ed_nexted;
2144 splx(s);
2145
2146 for (j = 0; j < nslots; j++)
2147 --sc->sc_bws[pos * nslots + j];
2148
2149 ohci_free_std(sc, opipe->tail);
2150 ohci_free_sed(sc, opipe->sed);
2151 /* XXX free other resources */
2152 }
2153
2154 usbd_status
2155 ohci_device_setintr(sc, opipe, ival)
2156 ohci_softc_t *sc;
2157 struct ohci_pipe *opipe;
2158 int ival;
2159 {
2160 int i, j, s, best;
2161 u_int npoll, slow, shigh, nslots;
2162 u_int bestbw, bw;
2163 ohci_soft_ed_t *hsed, *sed = opipe->sed;
2164
2165 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe));
2166 if (ival == 0) {
2167 printf("ohci_setintr: 0 interval\n");
2168 return (USBD_INVAL);
2169 }
2170
2171 npoll = OHCI_NO_INTRS;
2172 while (npoll > ival)
2173 npoll /= 2;
2174 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll));
2175
2176 /*
2177 * We now know which level in the tree the ED must go into.
2178 * Figure out which slot has most bandwidth left over.
2179 * Slots to examine:
2180 * npoll
2181 * 1 0
2182 * 2 1 2
2183 * 4 3 4 5 6
2184 * 8 7 8 9 10 11 12 13 14
2185 * N (N-1) .. (N-1+N-1)
2186 */
2187 slow = npoll-1;
2188 shigh = slow + npoll;
2189 nslots = OHCI_NO_INTRS / npoll;
2190 for (best = i = slow, bestbw = ~0; i < shigh; i++) {
2191 bw = 0;
2192 for (j = 0; j < nslots; j++)
2193 bw += sc->sc_bws[i * nslots + j];
2194 if (bw < bestbw) {
2195 best = i;
2196 bestbw = bw;
2197 }
2198 }
2199 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n",
2200 best, slow, shigh, bestbw));
2201
2202 s = splusb();
2203 hsed = sc->sc_eds[best];
2204 sed->next = hsed->next;
2205 sed->ed->ed_nexted = hsed->ed->ed_nexted;
2206 hsed->next = sed;
2207 hsed->ed->ed_nexted = LE(sed->physaddr);
2208 splx(s);
2209
2210 for (j = 0; j < nslots; j++)
2211 ++sc->sc_bws[best * nslots + j];
2212 opipe->u.intr.nslots = nslots;
2213 opipe->u.intr.pos = best;
2214
2215 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe));
2216 return (USBD_NORMAL_COMPLETION);
2217 }
2218
2219