ohci.c revision 1.18
1 /* $NetBSD: ohci.c,v 1.18 1998/12/29 03:01:44 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (augustss (at) carlstedt.se) at 9 * Carlstedt Research & Technology. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * USB Open Host Controller driver. 42 * 43 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf 44 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/malloc.h> 51 #if defined(__NetBSD__) 52 #include <sys/device.h> 53 #elif defined(__FreeBSD__) 54 #include <sys/module.h> 55 #include <sys/bus.h> 56 #endif 57 #include <sys/proc.h> 58 #include <sys/queue.h> 59 #include <sys/select.h> 60 61 #include <machine/bus.h> 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_quirks.h> 68 #include <dev/usb/usb_mem.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 73 #if defined(__FreeBSD__) 74 #include <machine/clock.h> 75 #include "dev/usb/queue.addendum.h" 76 77 #define delay(d) DELAY(d) 78 79 #endif 80 81 /* 82 * The OHCI controller is little endian, so on big endian machines 83 * the data strored in memory needs to be swapped. 84 */ 85 #if BYTE_ORDER == BIG_ENDIAN 86 #define LE(x) (bswap32(x)) 87 #else 88 #define LE(x) (x) 89 #endif 90 91 struct ohci_pipe; 92 93 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 94 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 95 96 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 97 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 98 99 usbd_status ohci_open __P((usbd_pipe_handle)); 100 void ohci_poll __P((struct usbd_bus *)); 101 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 102 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 103 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 104 void ohci_ii_done __P((ohci_softc_t *, usbd_request_handle)); 105 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 106 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 107 void ohci_bulk_done __P((ohci_softc_t *, usbd_request_handle)); 108 109 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 110 void ohci_add_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 111 void ohci_rem_ed __P((ohci_soft_ed_t *, ohci_soft_ed_t *)); 112 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 113 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 114 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 115 116 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 117 usbd_status ohci_root_ctrl_start __P((usbd_request_handle)); 118 void ohci_root_ctrl_abort __P((usbd_request_handle)); 119 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 120 121 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 122 usbd_status ohci_root_intr_start __P((usbd_request_handle)); 123 void ohci_root_intr_abort __P((usbd_request_handle)); 124 void ohci_root_intr_close __P((usbd_pipe_handle)); 125 126 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 127 usbd_status ohci_device_ctrl_start __P((usbd_request_handle)); 128 void ohci_device_ctrl_abort __P((usbd_request_handle)); 129 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 130 131 usbd_status ohci_device_bulk_transfer __P((usbd_request_handle)); 132 usbd_status ohci_device_bulk_start __P((usbd_request_handle)); 133 void ohci_device_bulk_abort __P((usbd_request_handle)); 134 void ohci_device_bulk_close __P((usbd_pipe_handle)); 135 136 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 137 usbd_status ohci_device_intr_start __P((usbd_request_handle)); 138 void ohci_device_intr_abort __P((usbd_request_handle)); 139 void ohci_device_intr_close __P((usbd_pipe_handle)); 140 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 141 struct ohci_pipe *pipe, int ival)); 142 143 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 144 145 void ohci_timeout __P((void *)); 146 void ohci_rhsc_able __P((ohci_softc_t *, int)); 147 148 #ifdef USB_DEBUG 149 ohci_softc_t *thesc; 150 void ohci_dumpregs __P((ohci_softc_t *)); 151 void ohci_dump_tds __P((ohci_soft_td_t *)); 152 void ohci_dump_td __P((ohci_soft_td_t *)); 153 void ohci_dump_ed __P((ohci_soft_ed_t *)); 154 #endif 155 156 #if defined(__NetBSD__) 157 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 158 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 159 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 160 #elif defined(__FreeBSD__) 161 #define OWRITE4(sc, r, x) outl((sc)->sc_iobase + (r), (x)) 162 #define OREAD4(sc, r) inl((sc)->sc_iobase + (r)) 163 #define OREAD2(sc, r) inw((sc)->sc_iobase + (r)) 164 #endif 165 166 /* Reverse the bits in a value 0 .. 31 */ 167 static u_int8_t revbits[OHCI_NO_INTRS] = 168 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 169 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 170 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 171 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 172 173 struct ohci_pipe { 174 struct usbd_pipe pipe; 175 ohci_soft_ed_t *sed; 176 ohci_soft_td_t *tail; 177 /* Info needed for different pipe kinds. */ 178 union { 179 /* Control pipe */ 180 struct { 181 usb_dma_t datadma; 182 usb_dma_t reqdma; 183 u_int length; 184 ohci_soft_td_t *setup, *xfer, *stat; 185 } ctl; 186 /* Interrupt pipe */ 187 struct { 188 usb_dma_t datadma; 189 int nslots; 190 int pos; 191 } intr; 192 /* Bulk pipe */ 193 struct { 194 usb_dma_t datadma; 195 u_int length; 196 } bulk; 197 } u; 198 }; 199 200 #define OHCI_INTR_ENDPT 1 201 202 struct usbd_methods ohci_root_ctrl_methods = { 203 ohci_root_ctrl_transfer, 204 ohci_root_ctrl_start, 205 ohci_root_ctrl_abort, 206 ohci_root_ctrl_close, 207 0, 208 }; 209 210 struct usbd_methods ohci_root_intr_methods = { 211 ohci_root_intr_transfer, 212 ohci_root_intr_start, 213 ohci_root_intr_abort, 214 ohci_root_intr_close, 215 0, 216 }; 217 218 struct usbd_methods ohci_device_ctrl_methods = { 219 ohci_device_ctrl_transfer, 220 ohci_device_ctrl_start, 221 ohci_device_ctrl_abort, 222 ohci_device_ctrl_close, 223 0, 224 }; 225 226 struct usbd_methods ohci_device_intr_methods = { 227 ohci_device_intr_transfer, 228 ohci_device_intr_start, 229 ohci_device_intr_abort, 230 ohci_device_intr_close, 231 }; 232 233 struct usbd_methods ohci_device_bulk_methods = { 234 ohci_device_bulk_transfer, 235 ohci_device_bulk_start, 236 ohci_device_bulk_abort, 237 ohci_device_bulk_close, 238 0, 239 }; 240 241 ohci_soft_ed_t * 242 ohci_alloc_sed(sc) 243 ohci_softc_t *sc; 244 { 245 ohci_soft_ed_t *sed; 246 usbd_status r; 247 int i, offs; 248 usb_dma_t dma; 249 250 if (!sc->sc_freeeds) { 251 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 252 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 253 M_USBDEV, M_NOWAIT); 254 if (!sed) 255 return 0; 256 r = usb_allocmem(sc->sc_dmatag, OHCI_ED_SIZE * OHCI_ED_CHUNK, 257 OHCI_ED_ALIGN, &dma); 258 if (r != USBD_NORMAL_COMPLETION) { 259 free(sed, M_USBDEV); 260 return 0; 261 } 262 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 263 offs = i * OHCI_ED_SIZE; 264 sed->physaddr = DMAADDR(&dma) + offs; 265 sed->ed = (ohci_ed_t *) 266 ((char *)KERNADDR(&dma) + offs); 267 sed->next = sc->sc_freeeds; 268 sc->sc_freeeds = sed; 269 } 270 } 271 sed = sc->sc_freeeds; 272 sc->sc_freeeds = sed->next; 273 memset(sed->ed, 0, OHCI_ED_SIZE); 274 sed->next = 0; 275 return sed; 276 } 277 278 void 279 ohci_free_sed(sc, sed) 280 ohci_softc_t *sc; 281 ohci_soft_ed_t *sed; 282 { 283 sed->next = sc->sc_freeeds; 284 sc->sc_freeeds = sed; 285 } 286 287 ohci_soft_td_t * 288 ohci_alloc_std(sc) 289 ohci_softc_t *sc; 290 { 291 ohci_soft_td_t *std; 292 usbd_status r; 293 int i, offs; 294 usb_dma_t dma; 295 296 if (!sc->sc_freetds) { 297 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 298 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 299 M_USBDEV, M_NOWAIT); 300 if (!std) 301 return 0; 302 r = usb_allocmem(sc->sc_dmatag, OHCI_TD_SIZE * OHCI_TD_CHUNK, 303 OHCI_TD_ALIGN, &dma); 304 if (r != USBD_NORMAL_COMPLETION) { 305 free(std, M_USBDEV); 306 return 0; 307 } 308 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 309 offs = i * OHCI_TD_SIZE; 310 std->physaddr = DMAADDR(&dma) + offs; 311 std->td = (ohci_td_t *) 312 ((char *)KERNADDR(&dma) + offs); 313 std->nexttd = sc->sc_freetds; 314 sc->sc_freetds = std; 315 } 316 } 317 std = sc->sc_freetds; 318 sc->sc_freetds = std->nexttd; 319 memset(std->td, 0, OHCI_TD_SIZE); 320 std->nexttd = 0; 321 return (std); 322 } 323 324 void 325 ohci_free_std(sc, std) 326 ohci_softc_t *sc; 327 ohci_soft_td_t *std; 328 { 329 std->nexttd = sc->sc_freetds; 330 sc->sc_freetds = std; 331 } 332 333 usbd_status 334 ohci_init(sc) 335 ohci_softc_t *sc; 336 { 337 ohci_soft_ed_t *sed, *psed; 338 usbd_status r; 339 int rev; 340 int i; 341 u_int32_t s, ctl, ival, hcr, fm, per; 342 343 DPRINTF(("ohci_init: start\n")); 344 rev = OREAD4(sc, OHCI_REVISION); 345 printf("%s: OHCI version %d.%d%s\n", USBDEVNAME(sc->sc_bus.bdev), 346 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 347 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 348 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 349 printf("%s: unsupported OHCI revision\n", 350 USBDEVNAME(sc->sc_bus.bdev)); 351 return (USBD_INVAL); 352 } 353 354 for (i = 0; i < OHCI_HASH_SIZE; i++) 355 LIST_INIT(&sc->sc_hash_tds[i]); 356 357 /* Allocate the HCCA area. */ 358 r = usb_allocmem(sc->sc_dmatag, OHCI_HCCA_SIZE, 359 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 360 if (r != USBD_NORMAL_COMPLETION) 361 return (r); 362 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 363 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 364 365 sc->sc_eintrs = OHCI_NORMAL_INTRS; 366 367 sc->sc_ctrl_head = ohci_alloc_sed(sc); 368 if (!sc->sc_ctrl_head) { 369 r = USBD_NOMEM; 370 goto bad1; 371 } 372 sc->sc_ctrl_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 373 sc->sc_bulk_head = ohci_alloc_sed(sc); 374 if (!sc->sc_bulk_head) { 375 r = USBD_NOMEM; 376 goto bad2; 377 } 378 sc->sc_bulk_head->ed->ed_flags |= LE(OHCI_ED_SKIP); 379 380 /* Allocate all the dummy EDs that make up the interrupt tree. */ 381 for (i = 0; i < OHCI_NO_EDS; i++) { 382 sed = ohci_alloc_sed(sc); 383 if (!sed) { 384 while (--i >= 0) 385 ohci_free_sed(sc, sc->sc_eds[i]); 386 r = USBD_NOMEM; 387 goto bad3; 388 } 389 /* All ED fields are set to 0. */ 390 sc->sc_eds[i] = sed; 391 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 392 if (i != 0) { 393 psed = sc->sc_eds[(i-1) / 2]; 394 sed->next = psed; 395 sed->ed->ed_nexted = LE(psed->physaddr); 396 } 397 } 398 /* 399 * Fill HCCA interrupt table. The bit reversal is to get 400 * the tree set up properly to spread the interrupts. 401 */ 402 for (i = 0; i < OHCI_NO_INTRS; i++) 403 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 404 LE(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 405 406 /* Determine in what context we are running. */ 407 ctl = OREAD4(sc, OHCI_CONTROL); 408 if (ctl & OHCI_IR) { 409 /* SMM active, request change */ 410 DPRINTF(("ohci_init: SMM active, request owner change\n")); 411 s = OREAD4(sc, OHCI_COMMAND_STATUS); 412 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 413 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 414 delay(1000); 415 ctl = OREAD4(sc, OHCI_CONTROL); 416 } 417 if ((ctl & OHCI_IR) == 0) { 418 printf("%s: SMM does not respond, resetting\n", 419 USBDEVNAME(sc->sc_bus.bdev)); 420 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 421 goto reset; 422 } 423 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 424 /* BIOS started controller. */ 425 DPRINTF(("ohci_init: BIOS active\n")); 426 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 427 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 428 delay(USB_RESUME_DELAY * 1000); 429 } 430 } else { 431 DPRINTF(("ohci_init: cold started\n")); 432 reset: 433 /* Controller was cold started. */ 434 delay(USB_BUS_RESET_DELAY * 1000); 435 } 436 437 /* 438 * This reset should be necessary according to the OHCI spec, but 439 * without it some controller don't start. 440 */ 441 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 442 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 443 delay(USB_BUS_RESET_DELAY * 1000); 444 445 /* We now own the host controller and the bus has been reset. */ 446 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 447 448 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 449 /* Nominal time for a reset is 10 us. */ 450 for (i = 0; i < 10; i++) { 451 delay(10); 452 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 453 if (!hcr) 454 break; 455 } 456 if (hcr) { 457 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 458 r = USBD_IOERROR; 459 goto bad3; 460 } 461 #ifdef USB_DEBUG 462 thesc = sc; 463 if (ohcidebug > 15) 464 ohci_dumpregs(sc); 465 #endif 466 467 /* The controller is now in suspend state, we have 2ms to finish. */ 468 469 /* Set up HC registers. */ 470 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 471 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 472 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 473 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 474 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 475 ctl = OREAD4(sc, OHCI_CONTROL); 476 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 477 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 478 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 479 /* And finally start it! */ 480 OWRITE4(sc, OHCI_CONTROL, ctl); 481 482 /* 483 * The controller is now OPERATIONAL. Set a some final 484 * registers that should be set earlier, but that the 485 * controller ignores when in the SUSPEND state. 486 */ 487 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 488 fm |= OHCI_FSMPS(ival) | ival; 489 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 490 per = OHCI_PERIODIC(ival); /* 90% periodic */ 491 OWRITE4(sc, OHCI_PERIODIC_START, per); 492 493 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 494 495 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 496 497 #ifdef USB_DEBUG 498 if (ohcidebug > 5) 499 ohci_dumpregs(sc); 500 #endif 501 502 /* Set up the bus struct. */ 503 sc->sc_bus.open_pipe = ohci_open; 504 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 505 sc->sc_bus.do_poll = ohci_poll; 506 507 return (USBD_NORMAL_COMPLETION); 508 509 bad3: 510 ohci_free_sed(sc, sc->sc_ctrl_head); 511 bad2: 512 ohci_free_sed(sc, sc->sc_bulk_head); 513 bad1: 514 usb_freemem(sc->sc_dmatag, &sc->sc_hccadma); 515 return (r); 516 } 517 518 #ifdef USB_DEBUG 519 void ohcidump(void); 520 void ohcidump(void) { ohci_dumpregs(thesc); } 521 522 void 523 ohci_dumpregs(sc) 524 ohci_softc_t *sc; 525 { 526 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 527 OREAD4(sc, OHCI_REVISION), 528 OREAD4(sc, OHCI_CONTROL), 529 OREAD4(sc, OHCI_COMMAND_STATUS)); 530 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 531 OREAD4(sc, OHCI_INTERRUPT_STATUS), 532 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 533 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 534 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 535 OREAD4(sc, OHCI_HCCA), 536 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 537 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 538 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 539 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 540 OREAD4(sc, OHCI_BULK_HEAD_ED), 541 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 542 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 543 OREAD4(sc, OHCI_DONE_HEAD), 544 OREAD4(sc, OHCI_FM_INTERVAL), 545 OREAD4(sc, OHCI_FM_REMAINING)); 546 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 547 OREAD4(sc, OHCI_FM_NUMBER), 548 OREAD4(sc, OHCI_PERIODIC_START), 549 OREAD4(sc, OHCI_LS_THRESHOLD)); 550 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 551 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 552 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 553 OREAD4(sc, OHCI_RH_STATUS)); 554 printf(" port1=0x%08x port2=0x%08x\n", 555 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 556 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 557 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 558 LE(sc->sc_hcca->hcca_frame_number), 559 LE(sc->sc_hcca->hcca_done_head)); 560 } 561 #endif 562 563 int 564 ohci_intr(p) 565 void *p; 566 { 567 ohci_softc_t *sc = p; 568 u_int32_t intrs, eintrs; 569 ohci_physaddr_t done; 570 571 /* In case the interrupt occurs before initialization has completed. */ 572 if (sc->sc_hcca == NULL) { 573 #ifdef DIAGNOSTIC 574 printf("ohci_intr: sc->sc_hcca == NULL\n"); 575 #endif 576 return (0); 577 } 578 579 done = LE(sc->sc_hcca->hcca_done_head); 580 if (done != 0) { 581 intrs = OHCI_WDH; 582 if (done & OHCI_DONE_INTRS) 583 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 584 } else 585 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 586 if (!intrs) 587 return (0); 588 intrs &= ~OHCI_MIE; 589 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 590 eintrs = intrs & sc->sc_eintrs; 591 if (!eintrs) 592 return (0); 593 594 sc->sc_intrs++; 595 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 596 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 597 (u_int)eintrs)); 598 599 if (eintrs & OHCI_SO) { 600 printf("%s: scheduling overrun\n",USBDEVNAME(sc->sc_bus.bdev)); 601 /* XXX do what */ 602 intrs &= ~OHCI_SO; 603 } 604 if (eintrs & OHCI_WDH) { 605 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 606 sc->sc_hcca->hcca_done_head = 0; 607 intrs &= ~OHCI_WDH; 608 } 609 if (eintrs & OHCI_RD) { 610 /* XXX process resume detect */ 611 } 612 if (eintrs & OHCI_UE) { 613 printf("%s: unrecoverable error, controller halted\n", 614 USBDEVNAME(sc->sc_bus.bdev)); 615 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 616 /* XXX what else */ 617 } 618 if (eintrs & OHCI_RHSC) { 619 ohci_rhsc(sc, sc->sc_intrreqh); 620 intrs &= ~OHCI_RHSC; 621 622 /* 623 * Disable RHSC interrupt for now, because it will be 624 * on until the port has been reset. 625 */ 626 ohci_rhsc_able(sc, 0); 627 } 628 629 /* Block unprocessed interrupts. XXX */ 630 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 631 sc->sc_eintrs &= ~intrs; 632 633 return (1); 634 } 635 636 void 637 ohci_rhsc_able(sc, on) 638 ohci_softc_t *sc; 639 int on; 640 { 641 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 642 if (on) { 643 sc->sc_eintrs |= OHCI_RHSC; 644 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 645 } else { 646 sc->sc_eintrs &= ~OHCI_RHSC; 647 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 648 } 649 } 650 651 #ifdef USB_DEBUG 652 char *ohci_cc_strs[] = { 653 "NO_ERROR", 654 "CRC", 655 "BIT_STUFFING", 656 "DATA_TOGGLE_MISMATCH", 657 "STALL", 658 "DEVICE_NOT_RESPONDING", 659 "PID_CHECK_FAILURE", 660 "UNEXPECTED_PID", 661 "DATA_OVERRUN", 662 "DATA_UNDERRUN", 663 "BUFFER_OVERRUN", 664 "BUFFER_UNDERRUN", 665 "NOT_ACCESSED", 666 }; 667 #endif 668 669 void 670 ohci_process_done(sc, done) 671 ohci_softc_t *sc; 672 ohci_physaddr_t done; 673 { 674 ohci_soft_td_t *std, *sdone; 675 usbd_request_handle reqh; 676 int len, cc; 677 678 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 679 680 /* Reverse the done list. */ 681 for (sdone = 0; done; done = LE(std->td->td_nexttd)) { 682 std = ohci_hash_find_td(sc, done); 683 std->dnext = sdone; 684 sdone = std; 685 } 686 687 #ifdef USB_DEBUG 688 if (ohcidebug > 10) { 689 printf("ohci_process_done: TD done:\n"); 690 ohci_dump_tds(sdone); 691 } 692 #endif 693 694 for (std = sdone; std; std = std->dnext) { 695 reqh = std->reqh; 696 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh)); 697 cc = OHCI_TD_GET_CC(LE(std->td->td_flags)); 698 if (cc == OHCI_CC_NO_ERROR) { 699 if (std->td->td_cbp == 0) 700 len = std->len; 701 else 702 len = LE(std->td->td_be) - 703 LE(std->td->td_cbp) + 1; 704 reqh->actlen += len; 705 reqh->status = USBD_NORMAL_COMPLETION; 706 /* 707 * Only do a callback on the last stage of a transfer. 708 * Others have hcpriv = 0. 709 */ 710 if (reqh->hcpriv == std) 711 ohci_ii_done(sc, reqh); 712 } else { 713 ohci_soft_td_t *p, *n; 714 struct ohci_pipe *opipe = 715 (struct ohci_pipe *)reqh->pipe; 716 DPRINTFN(-1,("ohci_process_done: error cc=%d (%s)\n", 717 OHCI_TD_GET_CC(LE(std->td->td_flags)), 718 ohci_cc_strs[OHCI_TD_GET_CC(LE(std->td->td_flags))])); 719 /* 720 * Endpoint is halted. First unlink all the TDs 721 * belonging to the failed transfer, and then restart 722 * the endpoint. 723 */ 724 for (p = std->nexttd; p->reqh == reqh; p = n) { 725 n = p->nexttd; 726 ohci_hash_rem_td(sc, p); 727 ohci_free_std(sc, p); 728 } 729 /* clear halt */ 730 opipe->sed->ed->ed_headp = LE(p->physaddr); 731 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 732 733 if (cc == OHCI_CC_STALL) 734 reqh->status = USBD_STALLED; 735 else 736 reqh->status = USBD_IOERROR; 737 ohci_ii_done(sc, reqh); 738 } 739 ohci_hash_rem_td(sc, std); 740 ohci_free_std(sc, std); 741 } 742 } 743 744 void 745 ohci_ii_done(sc, reqh) 746 ohci_softc_t *sc; 747 usbd_request_handle reqh; 748 { 749 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 750 case UE_CONTROL: 751 ohci_ctrl_done(sc, reqh); 752 usb_start_next(reqh->pipe); 753 break; 754 case UE_INTERRUPT: 755 ohci_intr_done(sc, reqh); 756 break; 757 case UE_BULK: 758 ohci_bulk_done(sc, reqh); 759 usb_start_next(reqh->pipe); 760 break; 761 case UE_ISOCHRONOUS: 762 printf("ohci_process_done: ISO done?\n"); 763 usb_start_next(reqh->pipe); 764 break; 765 } 766 767 /* And finally execute callback. */ 768 reqh->xfercb(reqh); 769 } 770 771 void 772 ohci_ctrl_done(sc, reqh) 773 ohci_softc_t *sc; 774 usbd_request_handle reqh; 775 { 776 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 777 u_int len = opipe->u.ctl.length; 778 usb_dma_t *dma; 779 780 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 781 782 if (!reqh->isreq) { 783 panic("ohci_ctrl_done: not a request\n"); 784 return; 785 } 786 787 if (len != 0) { 788 dma = &opipe->u.ctl.datadma; 789 if (reqh->request.bmRequestType & UT_READ) 790 memcpy(reqh->buffer, KERNADDR(dma), len); 791 usb_freemem(sc->sc_dmatag, dma); 792 } 793 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 794 } 795 796 void 797 ohci_intr_done(sc, reqh) 798 ohci_softc_t *sc; 799 usbd_request_handle reqh; 800 { 801 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 802 usb_dma_t *dma; 803 ohci_soft_ed_t *sed = opipe->sed; 804 ohci_soft_td_t *xfer, *tail; 805 806 807 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 808 reqh, reqh->actlen)); 809 810 dma = &opipe->u.intr.datadma; 811 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 812 813 if (reqh->pipe->intrreqh == reqh) { 814 xfer = opipe->tail; 815 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 816 if (!tail) { 817 reqh->status = USBD_NOMEM; 818 return; 819 } 820 tail->reqh = 0; 821 822 xfer->td->td_flags = LE( 823 OHCI_TD_IN | OHCI_TD_NOCC | 824 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 825 xfer->td->td_cbp = LE(DMAADDR(dma)); 826 xfer->nexttd = tail; 827 xfer->td->td_nexttd = LE(tail->physaddr); 828 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + reqh->length - 1); 829 xfer->len = reqh->length; 830 xfer->reqh = reqh; 831 832 reqh->actlen = 0; 833 reqh->hcpriv = xfer; 834 835 ohci_hash_add_td(sc, xfer); 836 sed->ed->ed_tailp = LE(tail->physaddr); 837 opipe->tail = tail; 838 } else { 839 usb_freemem(sc->sc_dmatag, dma); 840 usb_start_next(reqh->pipe); 841 } 842 } 843 844 void 845 ohci_bulk_done(sc, reqh) 846 ohci_softc_t *sc; 847 usbd_request_handle reqh; 848 { 849 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 850 usb_dma_t *dma; 851 852 853 DPRINTFN(10,("ohci_bulk_done: reqh=%p, actlen=%d\n", 854 reqh, reqh->actlen)); 855 856 dma = &opipe->u.bulk.datadma; 857 if (reqh->request.bmRequestType & UT_READ) 858 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 859 usb_freemem(sc->sc_dmatag, dma); 860 usb_untimeout(ohci_timeout, reqh, reqh->timo_handle); 861 } 862 863 void 864 ohci_rhsc(sc, reqh) 865 ohci_softc_t *sc; 866 usbd_request_handle reqh; 867 { 868 usbd_pipe_handle pipe; 869 struct ohci_pipe *opipe; 870 u_char *p; 871 int i, m; 872 int hstatus; 873 874 hstatus = OREAD4(sc, OHCI_RH_STATUS); 875 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 876 sc, reqh, hstatus)); 877 878 if (reqh == 0) { 879 /* Just ignore the change. */ 880 return; 881 } 882 883 pipe = reqh->pipe; 884 opipe = (struct ohci_pipe *)pipe; 885 886 p = KERNADDR(&opipe->u.intr.datadma); 887 m = min(sc->sc_noport, reqh->length * 8 - 1); 888 memset(p, 0, reqh->length); 889 for (i = 1; i <= m; i++) { 890 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 891 p[i/8] |= 1 << (i%8); 892 } 893 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 894 reqh->actlen = reqh->length; 895 reqh->status = USBD_NORMAL_COMPLETION; 896 reqh->xfercb(reqh); 897 898 if (reqh->pipe->intrreqh != reqh) { 899 sc->sc_intrreqh = 0; 900 usb_freemem(sc->sc_dmatag, &opipe->u.intr.datadma); 901 usb_start_next(reqh->pipe); 902 } 903 } 904 905 /* 906 * Wait here until controller claims to have an interrupt. 907 * Then call ohci_intr and return. Use timeout to avoid waiting 908 * too long. 909 */ 910 void 911 ohci_waitintr(sc, reqh) 912 ohci_softc_t *sc; 913 usbd_request_handle reqh; 914 { 915 int timo = reqh->timeout; 916 int usecs; 917 u_int32_t intrs; 918 919 reqh->status = USBD_IN_PROGRESS; 920 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 921 usbd_delay_ms(&sc->sc_bus, 1); 922 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 923 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs)); 924 #ifdef USB_DEBUG 925 if (ohcidebug > 15) 926 ohci_dumpregs(sc); 927 #endif 928 if (intrs) { 929 ohci_intr(sc); 930 if (reqh->status != USBD_IN_PROGRESS) 931 return; 932 } 933 } 934 935 /* Timeout */ 936 DPRINTF(("ohci_waitintr: timeout\n")); 937 reqh->status = USBD_TIMEOUT; 938 ohci_ii_done(sc, reqh); 939 /* XXX should free TD */ 940 } 941 942 void 943 ohci_poll(bus) 944 struct usbd_bus *bus; 945 { 946 ohci_softc_t *sc = (ohci_softc_t *)bus; 947 948 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 949 ohci_intr(sc); 950 } 951 952 usbd_status 953 ohci_device_request(reqh) 954 usbd_request_handle reqh; 955 { 956 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 957 usb_device_request_t *req = &reqh->request; 958 usbd_device_handle dev = opipe->pipe.device; 959 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 960 int addr = dev->address; 961 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 962 ohci_soft_ed_t *sed; 963 usb_dma_t *dmap; 964 int isread; 965 int len; 966 usbd_status r; 967 int s; 968 969 isread = req->bmRequestType & UT_READ; 970 len = UGETW(req->wLength); 971 972 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 973 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 974 req->bmRequestType, req->bRequest, UGETW(req->wValue), 975 UGETW(req->wIndex), len, addr, 976 opipe->pipe.endpoint->edesc->bEndpointAddress)); 977 978 setup = opipe->tail; 979 stat = ohci_alloc_std(sc); 980 if (!stat) { 981 r = USBD_NOMEM; 982 goto bad1; 983 } 984 tail = ohci_alloc_std(sc); 985 if (!tail) { 986 r = USBD_NOMEM; 987 goto bad2; 988 } 989 tail->reqh = 0; 990 991 sed = opipe->sed; 992 dmap = &opipe->u.ctl.datadma; 993 opipe->u.ctl.length = len; 994 995 /* Update device address and length since they may have changed. */ 996 /* XXX This only needs to be done once, but it's too early in open. */ 997 sed->ed->ed_flags = LE( 998 (LE(sed->ed->ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 999 OHCI_ED_SET_FA(addr) | 1000 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1001 1002 /* Set up data transaction */ 1003 if (len != 0) { 1004 xfer = ohci_alloc_std(sc); 1005 if (!xfer) { 1006 r = USBD_NOMEM; 1007 goto bad3; 1008 } 1009 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1010 if (r != USBD_NORMAL_COMPLETION) 1011 goto bad4; 1012 xfer->td->td_flags = LE( 1013 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1014 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR); 1015 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1016 xfer->nexttd = stat; 1017 xfer->td->td_nexttd = LE(stat->physaddr); 1018 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1019 xfer->len = len; 1020 xfer->reqh = reqh; 1021 1022 next = xfer; 1023 } else 1024 next = stat; 1025 1026 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 1027 if (!isread && len != 0) 1028 memcpy(KERNADDR(dmap), reqh->buffer, len); 1029 1030 setup->td->td_flags = LE(OHCI_TD_SETUP | OHCI_TD_NOCC | 1031 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1032 setup->td->td_cbp = LE(DMAADDR(&opipe->u.ctl.reqdma)); 1033 setup->nexttd = next; 1034 setup->td->td_nexttd = LE(next->physaddr); 1035 setup->td->td_be = LE(LE(setup->td->td_cbp) + sizeof *req - 1); 1036 setup->len = 0; /* XXX The number of byte we count */ 1037 setup->reqh = reqh; 1038 1039 stat->td->td_flags = LE( 1040 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 1041 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1042 stat->td->td_cbp = 0; 1043 stat->nexttd = tail; 1044 stat->td->td_nexttd = LE(tail->physaddr); 1045 stat->td->td_be = 0; 1046 stat->len = 0; 1047 stat->reqh = reqh; 1048 1049 reqh->actlen = 0; 1050 reqh->hcpriv = stat; 1051 1052 #if USB_DEBUG 1053 if (ohcidebug > 5) { 1054 printf("ohci_device_request:\n"); 1055 ohci_dump_ed(sed); 1056 ohci_dump_tds(setup); 1057 } 1058 #endif 1059 1060 /* Insert ED in schedule */ 1061 s = splusb(); 1062 ohci_hash_add_td(sc, setup); 1063 if (len != 0) 1064 ohci_hash_add_td(sc, xfer); 1065 ohci_hash_add_td(sc, stat); 1066 sed->ed->ed_tailp = LE(tail->physaddr); 1067 opipe->tail = tail; 1068 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1069 if (reqh->timeout && !sc->sc_bus.use_polling) { 1070 usb_timeout(ohci_timeout, reqh, 1071 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1072 } 1073 splx(s); 1074 1075 #if USB_DEBUG 1076 if (ohcidebug > 5) { 1077 delay(5000); 1078 printf("ohci_device_request: status=%x\n", 1079 OREAD4(sc, OHCI_COMMAND_STATUS)); 1080 ohci_dump_ed(sed); 1081 ohci_dump_tds(setup); 1082 } 1083 #endif 1084 1085 return (USBD_NORMAL_COMPLETION); 1086 1087 bad4: 1088 ohci_free_std(sc, xfer); 1089 bad3: 1090 ohci_free_std(sc, tail); 1091 bad2: 1092 ohci_free_std(sc, stat); 1093 bad1: 1094 return (r); 1095 } 1096 1097 /* 1098 * Add an ED to the schedule. Called at splusb(). 1099 */ 1100 void 1101 ohci_add_ed(sed, head) 1102 ohci_soft_ed_t *sed; 1103 ohci_soft_ed_t *head; 1104 { 1105 sed->next = head->next; 1106 sed->ed->ed_nexted = head->ed->ed_nexted; 1107 head->next = sed; 1108 head->ed->ed_nexted = LE(sed->physaddr); 1109 } 1110 1111 /* 1112 * Remove an ED from the schedule. Called at splusb(). 1113 */ 1114 void 1115 ohci_rem_ed(sed, head) 1116 ohci_soft_ed_t *sed; 1117 ohci_soft_ed_t *head; 1118 { 1119 ohci_soft_ed_t *p; 1120 1121 /* XXX */ 1122 for (p = head; p && p->next != sed; p = p->next) 1123 ; 1124 if (!p) 1125 panic("ohci_rem_ed: ED not found\n"); 1126 p->next = sed->next; 1127 p->ed->ed_nexted = sed->ed->ed_nexted; 1128 } 1129 1130 /* 1131 * When a transfer is completed the TD is added to the done queue by 1132 * the host controller. This queue is the processed by software. 1133 * Unfortunately the queue contains the physical address of the TD 1134 * and we have no simple way to translate this back to a kernel address. 1135 * To make the translation possible (and fast) we use a hash table of 1136 * TDs currently in the schedule. The physical address is used as the 1137 * hash value. 1138 */ 1139 1140 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1141 /* Called at splusb() */ 1142 void 1143 ohci_hash_add_td(sc, std) 1144 ohci_softc_t *sc; 1145 ohci_soft_td_t *std; 1146 { 1147 int h = HASH(std->physaddr); 1148 1149 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1150 } 1151 1152 /* Called at splusb() */ 1153 void 1154 ohci_hash_rem_td(sc, std) 1155 ohci_softc_t *sc; 1156 ohci_soft_td_t *std; 1157 { 1158 LIST_REMOVE(std, hnext); 1159 } 1160 1161 ohci_soft_td_t * 1162 ohci_hash_find_td(sc, a) 1163 ohci_softc_t *sc; 1164 ohci_physaddr_t a; 1165 { 1166 int h = HASH(a); 1167 ohci_soft_td_t *std; 1168 1169 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1170 std != 0; 1171 std = LIST_NEXT(std, hnext)) 1172 if (std->physaddr == a) 1173 return (std); 1174 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1175 } 1176 1177 void 1178 ohci_timeout(addr) 1179 void *addr; 1180 { 1181 #if 0 1182 usbd_request_handle *reqh = addr; 1183 int s; 1184 1185 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1186 s = splusb(); 1187 /* XXX need to inactivate TD before calling interrupt routine */ 1188 ohci_XXX_done(reqh); 1189 splx(s); 1190 #endif 1191 } 1192 1193 #ifdef USB_DEBUG 1194 void 1195 ohci_dump_tds(std) 1196 ohci_soft_td_t *std; 1197 { 1198 for (; std; std = std->nexttd) 1199 ohci_dump_td(std); 1200 } 1201 1202 void 1203 ohci_dump_td(std) 1204 ohci_soft_td_t *std; 1205 { 1206 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1207 "nexttd=0x%08lx be=0x%08lx\n", 1208 std, (u_long)std->physaddr, 1209 (u_long)LE(std->td->td_flags), 1210 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1211 OHCI_TD_GET_DI(LE(std->td->td_flags)), 1212 OHCI_TD_GET_EC(LE(std->td->td_flags)), 1213 OHCI_TD_GET_CC(LE(std->td->td_flags)), 1214 (u_long)LE(std->td->td_cbp), 1215 (u_long)LE(std->td->td_nexttd), (u_long)LE(std->td->td_be)); 1216 } 1217 1218 void 1219 ohci_dump_ed(sed) 1220 ohci_soft_ed_t *sed; 1221 { 1222 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx " 1223 "headp=%b nexted=0x%08lx\n", 1224 sed, (u_long)sed->physaddr, 1225 OHCI_ED_GET_FA(LE(sed->ed->ed_flags)), 1226 OHCI_ED_GET_EN(LE(sed->ed->ed_flags)), 1227 OHCI_ED_GET_MAXP(LE(sed->ed->ed_flags)), 1228 (u_long)LE(sed->ed->ed_flags), 1229 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO", 1230 (u_long)LE(sed->ed->ed_tailp), 1231 (u_long)LE(sed->ed->ed_headp), "\20\1HALT\2CARRY", 1232 (u_long)LE(sed->ed->ed_nexted)); 1233 } 1234 #endif 1235 1236 usbd_status 1237 ohci_open(pipe) 1238 usbd_pipe_handle pipe; 1239 { 1240 usbd_device_handle dev = pipe->device; 1241 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1242 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1243 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1244 u_int8_t addr = dev->address; 1245 ohci_soft_ed_t *sed; 1246 ohci_soft_td_t *std; 1247 usbd_status r; 1248 int s; 1249 1250 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1251 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1252 if (addr == sc->sc_addr) { 1253 switch (ed->bEndpointAddress) { 1254 case USB_CONTROL_ENDPOINT: 1255 pipe->methods = &ohci_root_ctrl_methods; 1256 break; 1257 case UE_IN | OHCI_INTR_ENDPT: 1258 pipe->methods = &ohci_root_intr_methods; 1259 break; 1260 default: 1261 return (USBD_INVAL); 1262 } 1263 } else { 1264 sed = ohci_alloc_sed(sc); 1265 if (sed == 0) 1266 goto bad0; 1267 std = ohci_alloc_std(sc); 1268 if (std == 0) 1269 goto bad1; 1270 opipe->sed = sed; 1271 opipe->tail = std; 1272 sed->ed->ed_flags = LE( 1273 OHCI_ED_SET_FA(addr) | 1274 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1275 OHCI_ED_DIR_TD | 1276 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1277 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1278 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1279 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 1280 sed->ed->ed_headp = sed->ed->ed_tailp = LE(std->physaddr); 1281 1282 switch (ed->bmAttributes & UE_XFERTYPE) { 1283 case UE_CONTROL: 1284 pipe->methods = &ohci_device_ctrl_methods; 1285 r = usb_allocmem(sc->sc_dmatag, 1286 sizeof(usb_device_request_t), 1287 0, &opipe->u.ctl.reqdma); 1288 if (r != USBD_NORMAL_COMPLETION) 1289 goto bad; 1290 s = splusb(); 1291 ohci_add_ed(sed, sc->sc_ctrl_head); 1292 splx(s); 1293 break; 1294 case UE_INTERRUPT: 1295 pipe->methods = &ohci_device_intr_methods; 1296 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1297 case UE_ISOCHRONOUS: 1298 printf("ohci_open: open iso unimplemented\n"); 1299 return (USBD_XXX); 1300 case UE_BULK: 1301 pipe->methods = &ohci_device_bulk_methods; 1302 s = splusb(); 1303 ohci_add_ed(sed, sc->sc_bulk_head); 1304 splx(s); 1305 break; 1306 } 1307 } 1308 return (USBD_NORMAL_COMPLETION); 1309 1310 bad: 1311 ohci_free_std(sc, std); 1312 bad1: 1313 ohci_free_sed(sc, sed); 1314 bad0: 1315 return (USBD_NOMEM); 1316 1317 } 1318 1319 /* 1320 * Data structures and routines to emulate the root hub. 1321 */ 1322 usb_device_descriptor_t ohci_devd = { 1323 USB_DEVICE_DESCRIPTOR_SIZE, 1324 UDESC_DEVICE, /* type */ 1325 {0x00, 0x01}, /* USB version */ 1326 UCLASS_HUB, /* class */ 1327 USUBCLASS_HUB, /* subclass */ 1328 0, /* protocol */ 1329 64, /* max packet */ 1330 {0},{0},{0x00,0x01}, /* device id */ 1331 1,2,0, /* string indicies */ 1332 1 /* # of configurations */ 1333 }; 1334 1335 usb_config_descriptor_t ohci_confd = { 1336 USB_CONFIG_DESCRIPTOR_SIZE, 1337 UDESC_CONFIG, 1338 {USB_CONFIG_DESCRIPTOR_SIZE + 1339 USB_INTERFACE_DESCRIPTOR_SIZE + 1340 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1341 1, 1342 1, 1343 0, 1344 UC_SELF_POWERED, 1345 0 /* max power */ 1346 }; 1347 1348 usb_interface_descriptor_t ohci_ifcd = { 1349 USB_INTERFACE_DESCRIPTOR_SIZE, 1350 UDESC_INTERFACE, 1351 0, 1352 0, 1353 1, 1354 UCLASS_HUB, 1355 USUBCLASS_HUB, 1356 0, 1357 0 1358 }; 1359 1360 usb_endpoint_descriptor_t ohci_endpd = { 1361 USB_ENDPOINT_DESCRIPTOR_SIZE, 1362 UDESC_ENDPOINT, 1363 UE_IN | OHCI_INTR_ENDPT, 1364 UE_INTERRUPT, 1365 {8, 0}, /* max packet */ 1366 255 1367 }; 1368 1369 usb_hub_descriptor_t ohci_hubd = { 1370 USB_HUB_DESCRIPTOR_SIZE, 1371 UDESC_HUB, 1372 0, 1373 {0,0}, 1374 0, 1375 0, 1376 {0}, 1377 }; 1378 1379 int 1380 ohci_str(p, l, s) 1381 usb_string_descriptor_t *p; 1382 int l; 1383 char *s; 1384 { 1385 int i; 1386 1387 if (l == 0) 1388 return (0); 1389 p->bLength = 2 * strlen(s) + 2; 1390 if (l == 1) 1391 return (1); 1392 p->bDescriptorType = UDESC_STRING; 1393 l -= 2; 1394 for (i = 0; s[i] && l > 1; i++, l -= 2) 1395 USETW2(p->bString[i], 0, s[i]); 1396 return (2*i+2); 1397 } 1398 1399 /* 1400 * Simulate a hardware hub by handling all the necessary requests. 1401 */ 1402 usbd_status 1403 ohci_root_ctrl_transfer(reqh) 1404 usbd_request_handle reqh; 1405 { 1406 int s; 1407 usbd_status r; 1408 1409 s = splusb(); 1410 r = usb_insert_transfer(reqh); 1411 splx(s); 1412 if (r != USBD_NORMAL_COMPLETION) 1413 return (r); 1414 else 1415 return (ohci_root_ctrl_start(reqh)); 1416 } 1417 1418 usbd_status 1419 ohci_root_ctrl_start(reqh) 1420 usbd_request_handle reqh; 1421 { 1422 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1423 usb_device_request_t *req; 1424 void *buf; 1425 int port, i; 1426 int len, value, index, l, totlen = 0; 1427 usb_port_status_t ps; 1428 usb_hub_descriptor_t hubd; 1429 usbd_status r; 1430 u_int32_t v; 1431 1432 if (!reqh->isreq) 1433 /* XXX panic */ 1434 return (USBD_INVAL); 1435 req = &reqh->request; 1436 buf = reqh->buffer; 1437 1438 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1439 req->bmRequestType, req->bRequest)); 1440 1441 len = UGETW(req->wLength); 1442 value = UGETW(req->wValue); 1443 index = UGETW(req->wIndex); 1444 #define C(x,y) ((x) | ((y) << 8)) 1445 switch(C(req->bRequest, req->bmRequestType)) { 1446 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1447 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1448 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1449 /* 1450 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1451 * for the integrated root hub. 1452 */ 1453 break; 1454 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1455 if (len > 0) { 1456 *(u_int8_t *)buf = sc->sc_conf; 1457 totlen = 1; 1458 } 1459 break; 1460 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1461 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1462 switch(value >> 8) { 1463 case UDESC_DEVICE: 1464 if ((value & 0xff) != 0) { 1465 r = USBD_IOERROR; 1466 goto ret; 1467 } 1468 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1469 memcpy(buf, &ohci_devd, l); 1470 break; 1471 case UDESC_CONFIG: 1472 if ((value & 0xff) != 0) { 1473 r = USBD_IOERROR; 1474 goto ret; 1475 } 1476 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1477 memcpy(buf, &ohci_confd, l); 1478 buf = (char *)buf + l; 1479 len -= l; 1480 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1481 totlen += l; 1482 memcpy(buf, &ohci_ifcd, l); 1483 buf = (char *)buf + l; 1484 len -= l; 1485 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1486 totlen += l; 1487 memcpy(buf, &ohci_endpd, l); 1488 break; 1489 case UDESC_STRING: 1490 if (len == 0) 1491 break; 1492 *(u_int8_t *)buf = 0; 1493 totlen = 1; 1494 switch (value & 0xff) { 1495 case 1: /* Vendor */ 1496 totlen = ohci_str(buf, len, sc->sc_vendor); 1497 break; 1498 case 2: /* Product */ 1499 totlen = ohci_str(buf, len, "OHCI root hub"); 1500 break; 1501 } 1502 break; 1503 default: 1504 r = USBD_IOERROR; 1505 goto ret; 1506 } 1507 break; 1508 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1509 if (len > 0) { 1510 *(u_int8_t *)buf = 0; 1511 totlen = 1; 1512 } 1513 break; 1514 case C(UR_GET_STATUS, UT_READ_DEVICE): 1515 if (len > 1) { 1516 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1517 totlen = 2; 1518 } 1519 break; 1520 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1521 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1522 if (len > 1) { 1523 USETW(((usb_status_t *)buf)->wStatus, 0); 1524 totlen = 2; 1525 } 1526 break; 1527 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1528 if (value >= USB_MAX_DEVICES) { 1529 r = USBD_IOERROR; 1530 goto ret; 1531 } 1532 sc->sc_addr = value; 1533 break; 1534 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1535 if (value != 0 && value != 1) { 1536 r = USBD_IOERROR; 1537 goto ret; 1538 } 1539 sc->sc_conf = value; 1540 break; 1541 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1542 break; 1543 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1544 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1545 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1546 r = USBD_IOERROR; 1547 goto ret; 1548 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1549 break; 1550 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1551 break; 1552 /* Hub requests */ 1553 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1554 break; 1555 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1556 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1557 "port=%d feature=%d\n", 1558 index, value)); 1559 if (index < 1 || index > sc->sc_noport) { 1560 r = USBD_IOERROR; 1561 goto ret; 1562 } 1563 port = OHCI_RH_PORT_STATUS(index); 1564 switch(value) { 1565 case UHF_PORT_ENABLE: 1566 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1567 break; 1568 case UHF_PORT_SUSPEND: 1569 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1570 break; 1571 case UHF_PORT_POWER: 1572 OWRITE4(sc, port, UPS_LOW_SPEED); 1573 break; 1574 case UHF_C_PORT_CONNECTION: 1575 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1576 break; 1577 case UHF_C_PORT_ENABLE: 1578 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1579 break; 1580 case UHF_C_PORT_SUSPEND: 1581 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1582 break; 1583 case UHF_C_PORT_OVER_CURRENT: 1584 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1585 break; 1586 case UHF_C_PORT_RESET: 1587 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1588 break; 1589 default: 1590 r = USBD_IOERROR; 1591 goto ret; 1592 } 1593 switch(value) { 1594 case UHF_C_PORT_CONNECTION: 1595 case UHF_C_PORT_ENABLE: 1596 case UHF_C_PORT_SUSPEND: 1597 case UHF_C_PORT_OVER_CURRENT: 1598 case UHF_C_PORT_RESET: 1599 /* Enable RHSC interrupt if condition is cleared. */ 1600 if ((OREAD4(sc, port) >> 16) == 0) 1601 ohci_rhsc_able(sc, 1); 1602 break; 1603 default: 1604 break; 1605 } 1606 break; 1607 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1608 if (value != 0) { 1609 r = USBD_IOERROR; 1610 goto ret; 1611 } 1612 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1613 hubd = ohci_hubd; 1614 hubd.bNbrPorts = sc->sc_noport; 1615 USETW(hubd.wHubCharacteristics, 1616 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1617 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1618 /* XXX overcurrent */ 1619 ); 1620 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1621 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1622 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1623 hubd.DeviceRemovable[i++] = (u_int8_t)v; 1624 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1625 l = min(len, hubd.bDescLength); 1626 totlen = l; 1627 memcpy(buf, &hubd, l); 1628 break; 1629 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1630 if (len != 4) { 1631 r = USBD_IOERROR; 1632 goto ret; 1633 } 1634 memset(buf, 0, len); /* ? XXX */ 1635 totlen = len; 1636 break; 1637 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1638 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1639 index)); 1640 if (index < 1 || index > sc->sc_noport) { 1641 r = USBD_IOERROR; 1642 goto ret; 1643 } 1644 if (len != 4) { 1645 r = USBD_IOERROR; 1646 goto ret; 1647 } 1648 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1649 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1650 v)); 1651 USETW(ps.wPortStatus, v); 1652 USETW(ps.wPortChange, v >> 16); 1653 l = min(len, sizeof ps); 1654 memcpy(buf, &ps, l); 1655 totlen = l; 1656 break; 1657 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1658 r = USBD_IOERROR; 1659 goto ret; 1660 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1661 break; 1662 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1663 if (index < 1 || index > sc->sc_noport) { 1664 r = USBD_IOERROR; 1665 goto ret; 1666 } 1667 port = OHCI_RH_PORT_STATUS(index); 1668 switch(value) { 1669 case UHF_PORT_ENABLE: 1670 OWRITE4(sc, port, UPS_PORT_ENABLED); 1671 break; 1672 case UHF_PORT_SUSPEND: 1673 OWRITE4(sc, port, UPS_SUSPEND); 1674 break; 1675 case UHF_PORT_RESET: 1676 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 1677 index)); 1678 OWRITE4(sc, port, UPS_RESET); 1679 for (i = 0; i < 10; i++) { 1680 usbd_delay_ms(&sc->sc_bus, 10); 1681 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1682 break; 1683 } 1684 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1685 index, OREAD4(sc, port))); 1686 break; 1687 case UHF_PORT_POWER: 1688 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 1689 "%d\n", index)); 1690 OWRITE4(sc, port, UPS_PORT_POWER); 1691 break; 1692 default: 1693 r = USBD_IOERROR; 1694 goto ret; 1695 } 1696 break; 1697 default: 1698 r = USBD_IOERROR; 1699 goto ret; 1700 } 1701 reqh->actlen = totlen; 1702 r = USBD_NORMAL_COMPLETION; 1703 ret: 1704 reqh->status = r; 1705 reqh->xfercb(reqh); 1706 usb_start_next(reqh->pipe); 1707 return (USBD_IN_PROGRESS); 1708 } 1709 1710 /* Abort a root control request. */ 1711 void 1712 ohci_root_ctrl_abort(reqh) 1713 usbd_request_handle reqh; 1714 { 1715 /* Nothing to do, all transfers are synchronous. */ 1716 } 1717 1718 /* Close the root pipe. */ 1719 void 1720 ohci_root_ctrl_close(pipe) 1721 usbd_pipe_handle pipe; 1722 { 1723 DPRINTF(("ohci_root_ctrl_close\n")); 1724 } 1725 1726 usbd_status 1727 ohci_root_intr_transfer(reqh) 1728 usbd_request_handle reqh; 1729 { 1730 int s; 1731 usbd_status r; 1732 1733 s = splusb(); 1734 r = usb_insert_transfer(reqh); 1735 splx(s); 1736 if (r != USBD_NORMAL_COMPLETION) 1737 return (r); 1738 else 1739 return (ohci_root_intr_start(reqh)); 1740 } 1741 1742 usbd_status 1743 ohci_root_intr_start(reqh) 1744 usbd_request_handle reqh; 1745 { 1746 usbd_pipe_handle pipe = reqh->pipe; 1747 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1748 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1749 usb_dma_t *dmap; 1750 usbd_status r; 1751 int len; 1752 1753 len = reqh->length; 1754 dmap = &upipe->u.intr.datadma; 1755 if (len == 0) 1756 return (USBD_INVAL); /* XXX should it be? */ 1757 1758 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1759 if (r != USBD_NORMAL_COMPLETION) 1760 return (r); 1761 sc->sc_intrreqh = reqh; 1762 1763 return (USBD_IN_PROGRESS); 1764 } 1765 1766 /* Abort a root interrupt request. */ 1767 void 1768 ohci_root_intr_abort(reqh) 1769 usbd_request_handle reqh; 1770 { 1771 /* No need to abort. */ 1772 } 1773 1774 /* Close the root pipe. */ 1775 void 1776 ohci_root_intr_close(pipe) 1777 usbd_pipe_handle pipe; 1778 { 1779 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1780 sc->sc_intrreqh = 0; 1781 1782 DPRINTF(("ohci_root_intr_close\n")); 1783 } 1784 1785 /************************/ 1786 1787 usbd_status 1788 ohci_device_ctrl_transfer(reqh) 1789 usbd_request_handle reqh; 1790 { 1791 int s; 1792 usbd_status r; 1793 1794 s = splusb(); 1795 r = usb_insert_transfer(reqh); 1796 splx(s); 1797 if (r != USBD_NORMAL_COMPLETION) 1798 return (r); 1799 else 1800 return (ohci_device_ctrl_start(reqh)); 1801 } 1802 1803 usbd_status 1804 ohci_device_ctrl_start(reqh) 1805 usbd_request_handle reqh; 1806 { 1807 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1808 usbd_status r; 1809 1810 if (!reqh->isreq) { 1811 /* XXX panic */ 1812 printf("ohci_device_ctrl_transfer: not a request\n"); 1813 return (USBD_INVAL); 1814 } 1815 1816 r = ohci_device_request(reqh); 1817 if (r != USBD_NORMAL_COMPLETION) 1818 return (r); 1819 1820 if (sc->sc_bus.use_polling) 1821 ohci_waitintr(sc, reqh); 1822 return (USBD_IN_PROGRESS); 1823 } 1824 1825 /* Abort a device control request. */ 1826 void 1827 ohci_device_ctrl_abort(reqh) 1828 usbd_request_handle reqh; 1829 { 1830 /* XXX inactivate */ 1831 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is donw */ 1832 /* XXX call done */ 1833 } 1834 1835 /* Close a device control pipe. */ 1836 void 1837 ohci_device_ctrl_close(pipe) 1838 usbd_pipe_handle pipe; 1839 { 1840 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1841 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1842 ohci_soft_ed_t *sed = opipe->sed; 1843 int s; 1844 1845 s = splusb(); 1846 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1847 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1848 usbd_delay_ms(&sc->sc_bus, 2); 1849 ohci_rem_ed(sed, sc->sc_ctrl_head); 1850 splx(s); 1851 ohci_free_std(sc, opipe->tail); 1852 ohci_free_sed(sc, opipe->sed); 1853 /* XXX free other resources */ 1854 } 1855 1856 /************************/ 1857 1858 usbd_status 1859 ohci_device_bulk_transfer(reqh) 1860 usbd_request_handle reqh; 1861 { 1862 int s; 1863 usbd_status r; 1864 1865 s = splusb(); 1866 r = usb_insert_transfer(reqh); 1867 splx(s); 1868 if (r != USBD_NORMAL_COMPLETION) 1869 return (r); 1870 else 1871 return (ohci_device_bulk_start(reqh)); 1872 } 1873 1874 usbd_status 1875 ohci_device_bulk_start(reqh) 1876 usbd_request_handle reqh; 1877 { 1878 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1879 usbd_device_handle dev = opipe->pipe.device; 1880 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1881 int addr = dev->address; 1882 ohci_soft_td_t *xfer, *tail; 1883 ohci_soft_ed_t *sed; 1884 usb_dma_t *dmap; 1885 usbd_status r; 1886 int s, len, isread; 1887 1888 if (reqh->isreq) { 1889 /* XXX panic */ 1890 printf("ohci_device_bulk_transfer: a request\n"); 1891 return (USBD_INVAL); 1892 } 1893 1894 len = reqh->length; 1895 dmap = &opipe->u.bulk.datadma; 1896 isread = reqh->pipe->endpoint->edesc->bEndpointAddress & UE_IN; 1897 sed = opipe->sed; 1898 1899 opipe->u.bulk.length = len; 1900 1901 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 1902 if (r != USBD_NORMAL_COMPLETION) 1903 goto ret1; 1904 1905 tail = ohci_alloc_std(sc); 1906 if (!tail) { 1907 r = USBD_NOMEM; 1908 goto ret2; 1909 } 1910 tail->reqh = 0; 1911 1912 /* Update device address */ 1913 sed->ed->ed_flags = LE( 1914 (LE(sed->ed->ed_flags) & ~OHCI_ED_ADDRMASK) | 1915 OHCI_ED_SET_FA(addr)); 1916 1917 /* Set up data transaction */ 1918 xfer = opipe->tail; 1919 xfer->td->td_flags = LE( 1920 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 1921 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1922 xfer->td->td_cbp = LE(DMAADDR(dmap)); 1923 xfer->nexttd = tail; 1924 xfer->td->td_nexttd = LE(tail->physaddr); 1925 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 1926 xfer->len = len; 1927 xfer->reqh = reqh; 1928 1929 reqh->actlen = 0; 1930 reqh->hcpriv = xfer; 1931 1932 if (!isread) 1933 memcpy(KERNADDR(dmap), reqh->buffer, len); 1934 1935 /* Insert ED in schedule */ 1936 s = splusb(); 1937 ohci_hash_add_td(sc, xfer); 1938 sed->ed->ed_tailp = LE(tail->physaddr); 1939 opipe->tail = tail; 1940 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 1941 if (reqh->timeout && !sc->sc_bus.use_polling) { 1942 usb_timeout(ohci_timeout, reqh, 1943 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 1944 } 1945 splx(s); 1946 1947 return (USBD_IN_PROGRESS); 1948 1949 ret2: 1950 usb_freemem(sc->sc_dmatag, dmap); 1951 ret1: 1952 return (r); 1953 } 1954 1955 /* Abort a device bulk request. */ 1956 void 1957 ohci_device_bulk_abort(reqh) 1958 usbd_request_handle reqh; 1959 { 1960 #if 0 1961 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 1962 if ((LE(sed->ed->ed_tailp) & OHCI_TAILMASK) != LE(sed->ed->ed_headp)) 1963 usbd_delay_ms(reqh->pipe->device->bus, 2); 1964 #endif 1965 /* XXX inactivate */ 1966 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 1967 /* XXX call done */ 1968 } 1969 1970 /* Close a device bulk pipe. */ 1971 void 1972 ohci_device_bulk_close(pipe) 1973 usbd_pipe_handle pipe; 1974 { 1975 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1976 usbd_device_handle dev = opipe->pipe.device; 1977 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1978 int s; 1979 1980 s = splusb(); 1981 ohci_rem_ed(opipe->sed, sc->sc_bulk_head); 1982 splx(s); 1983 ohci_free_std(sc, opipe->tail); 1984 ohci_free_sed(sc, opipe->sed); 1985 /* XXX free other resources */ 1986 } 1987 1988 /************************/ 1989 1990 usbd_status 1991 ohci_device_intr_transfer(reqh) 1992 usbd_request_handle reqh; 1993 { 1994 int s; 1995 usbd_status r; 1996 1997 s = splusb(); 1998 r = usb_insert_transfer(reqh); 1999 splx(s); 2000 if (r != USBD_NORMAL_COMPLETION) 2001 return (r); 2002 else 2003 return (ohci_device_intr_start(reqh)); 2004 } 2005 2006 usbd_status 2007 ohci_device_intr_start(reqh) 2008 usbd_request_handle reqh; 2009 { 2010 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 2011 usbd_device_handle dev = opipe->pipe.device; 2012 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2013 ohci_soft_ed_t *sed = opipe->sed; 2014 ohci_soft_td_t *xfer, *tail; 2015 usb_dma_t *dmap; 2016 usbd_status r; 2017 int len; 2018 int s; 2019 2020 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d " 2021 "flags=%d priv=%p\n", 2022 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 2023 2024 if (reqh->isreq) 2025 panic("ohci_device_intr_transfer: a request\n"); 2026 2027 len = reqh->length; 2028 dmap = &opipe->u.intr.datadma; 2029 if (len == 0) 2030 return (USBD_INVAL); /* XXX should it be? */ 2031 2032 xfer = opipe->tail; 2033 tail = ohci_alloc_std(sc); 2034 if (!tail) { 2035 r = USBD_NOMEM; 2036 goto ret1; 2037 } 2038 tail->reqh = 0; 2039 2040 r = usb_allocmem(sc->sc_dmatag, len, 0, dmap); 2041 if (r != USBD_NORMAL_COMPLETION) 2042 goto ret2; 2043 2044 xfer->td->td_flags = LE( 2045 OHCI_TD_IN | OHCI_TD_NOCC | 2046 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2047 xfer->td->td_cbp = LE(DMAADDR(dmap)); 2048 xfer->nexttd = tail; 2049 xfer->td->td_nexttd = LE(tail->physaddr); 2050 xfer->td->td_be = LE(LE(xfer->td->td_cbp) + len - 1); 2051 xfer->len = len; 2052 xfer->reqh = reqh; 2053 2054 reqh->actlen = 0; 2055 reqh->hcpriv = xfer; 2056 2057 #if USB_DEBUG 2058 if (ohcidebug > 5) { 2059 printf("ohci_device_intr_transfer:\n"); 2060 ohci_dump_ed(sed); 2061 ohci_dump_tds(xfer); 2062 } 2063 #endif 2064 2065 /* Insert ED in schedule */ 2066 s = splusb(); 2067 ohci_hash_add_td(sc, xfer); 2068 sed->ed->ed_tailp = LE(tail->physaddr); 2069 opipe->tail = tail; 2070 #if 0 2071 if (reqh->timeout && !sc->sc_bus.use_polling) { 2072 usb_timeout(ohci_timeout, reqh, 2073 MS_TO_TICKS(reqh->timeout), reqh->timo_handle); 2074 } 2075 #endif 2076 sed->ed->ed_flags &= LE(~OHCI_ED_SKIP); 2077 splx(s); 2078 2079 #ifdef USB_DEBUG 2080 if (ohcidebug > 5) { 2081 delay(5000); 2082 printf("ohci_device_intr_transfer: status=%x\n", 2083 OREAD4(sc, OHCI_COMMAND_STATUS)); 2084 ohci_dump_ed(sed); 2085 ohci_dump_tds(xfer); 2086 } 2087 #endif 2088 2089 return (USBD_IN_PROGRESS); 2090 2091 ret2: 2092 ohci_free_std(sc, xfer); 2093 ret1: 2094 return (r); 2095 } 2096 2097 /* Abort a device control request. */ 2098 void 2099 ohci_device_intr_abort(reqh) 2100 usbd_request_handle reqh; 2101 { 2102 /* XXX inactivate */ 2103 usbd_delay_ms(reqh->pipe->device->bus, 1); /* make sure it is done */ 2104 if (reqh->pipe->intrreqh == reqh) { 2105 DPRINTF(("ohci_device_intr_abort: remove\n")); 2106 reqh->pipe->intrreqh = 0; 2107 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 2108 } 2109 } 2110 2111 /* Close a device interrupt pipe. */ 2112 void 2113 ohci_device_intr_close(pipe) 2114 usbd_pipe_handle pipe; 2115 { 2116 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2117 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2118 int nslots = opipe->u.intr.nslots; 2119 int pos = opipe->u.intr.pos; 2120 int j; 2121 ohci_soft_ed_t *p, *sed = opipe->sed; 2122 int s; 2123 2124 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 2125 pipe, nslots, pos)); 2126 s = splusb(); 2127 sed->ed->ed_flags |= LE(OHCI_ED_SKIP); 2128 if ((sed->ed->ed_tailp & LE(OHCI_TAILMASK)) != sed->ed->ed_headp) 2129 usbd_delay_ms(&sc->sc_bus, 2); 2130 2131 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 2132 ; 2133 if (!p) 2134 panic("ohci_device_intr_close: ED not found\n"); 2135 p->next = sed->next; 2136 p->ed->ed_nexted = sed->ed->ed_nexted; 2137 splx(s); 2138 2139 for (j = 0; j < nslots; j++) 2140 --sc->sc_bws[pos * nslots + j]; 2141 2142 ohci_free_std(sc, opipe->tail); 2143 ohci_free_sed(sc, opipe->sed); 2144 /* XXX free other resources */ 2145 } 2146 2147 usbd_status 2148 ohci_device_setintr(sc, opipe, ival) 2149 ohci_softc_t *sc; 2150 struct ohci_pipe *opipe; 2151 int ival; 2152 { 2153 int i, j, s, best; 2154 u_int npoll, slow, shigh, nslots; 2155 u_int bestbw, bw; 2156 ohci_soft_ed_t *hsed, *sed = opipe->sed; 2157 2158 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 2159 if (ival == 0) { 2160 printf("ohci_setintr: 0 interval\n"); 2161 return (USBD_INVAL); 2162 } 2163 2164 npoll = OHCI_NO_INTRS; 2165 while (npoll > ival) 2166 npoll /= 2; 2167 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 2168 2169 /* 2170 * We now know which level in the tree the ED must go into. 2171 * Figure out which slot has most bandwidth left over. 2172 * Slots to examine: 2173 * npoll 2174 * 1 0 2175 * 2 1 2 2176 * 4 3 4 5 6 2177 * 8 7 8 9 10 11 12 13 14 2178 * N (N-1) .. (N-1+N-1) 2179 */ 2180 slow = npoll-1; 2181 shigh = slow + npoll; 2182 nslots = OHCI_NO_INTRS / npoll; 2183 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 2184 bw = 0; 2185 for (j = 0; j < nslots; j++) 2186 bw += sc->sc_bws[i * nslots + j]; 2187 if (bw < bestbw) { 2188 best = i; 2189 bestbw = bw; 2190 } 2191 } 2192 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 2193 best, slow, shigh, bestbw)); 2194 2195 s = splusb(); 2196 hsed = sc->sc_eds[best]; 2197 sed->next = hsed->next; 2198 sed->ed->ed_nexted = hsed->ed->ed_nexted; 2199 hsed->next = sed; 2200 hsed->ed->ed_nexted = LE(sed->physaddr); 2201 splx(s); 2202 2203 for (j = 0; j < nslots; j++) 2204 ++sc->sc_bws[best * nslots + j]; 2205 opipe->u.intr.nslots = nslots; 2206 opipe->u.intr.pos = best; 2207 2208 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 2209 return (USBD_NORMAL_COMPLETION); 2210 } 2211 2212
Indexes created Fri Oct 03 02:09:57 GMT 2025