ohci.c revision 1.182.12.1
1 /* $NetBSD: ohci.c,v 1.182.12.1 2007/05/22 14:57:39 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology. 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Charles M. Hannum. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * USB Open Host Controller driver. 44 * 45 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 46 * USB spec: http://www.usb.org/developers/docs/ 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.182.12.1 2007/05/22 14:57:39 itohy Exp $"); 51 /* __FBSDID("$FreeBSD: src/sys/dev/usb/ohci.c,v 1.167 2006/10/19 01:15:58 iedowse Exp $"); */ 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #if defined(__NetBSD__) || defined(__OpenBSD__) 58 #include <sys/device.h> 59 #include <sys/select.h> 60 #include <uvm/uvm_extern.h> 61 #elif defined(__FreeBSD__) 62 #include <sys/endian.h> 63 #include <sys/module.h> 64 #include <sys/bus.h> 65 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 66 #include <machine/cpu.h> 67 #endif 68 #endif 69 #include <sys/proc.h> 70 #include <sys/queue.h> 71 72 #include <machine/bus.h> 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ohcireg.h> 82 #include <dev/usb/ohcivar.h> 83 84 #if defined(__FreeBSD__) 85 #include <sys/sysctl.h> 86 87 #define delay(d) DELAY(d) 88 #endif 89 90 #if defined(__OpenBSD__) 91 struct cfdriver ohci_cd = { 92 NULL, "ohci", DV_DULL 93 }; 94 #endif 95 96 #ifdef USB_DEBUG 97 #define DPRINTF(x) if (ohcidebug) logprintf x 98 #define DPRINTFN(n,x) if (ohcidebug>(n)) logprintf x 99 int ohcidebug = 0; 100 #ifdef __FreeBSD__ 101 SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 102 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 103 &ohcidebug, 0, "ohci debug level"); 104 #endif 105 #ifndef __NetBSD__ 106 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 107 #endif 108 #else 109 #define DPRINTF(x) 110 #define DPRINTFN(n,x) 111 #endif 112 113 /* 114 * The OHCI controller is either little endian or host endian, 115 * so on big endian machines with little endian controller 116 * the data strored in memory needs to be swapped. 117 */ 118 #define O16TOH(val) (sc->sc_endian ? (val) : le16toh(val)) 119 #define O32TOH(val) (sc->sc_endian ? (val) : le32toh(val)) 120 #define HTOO16(val) (sc->sc_endian ? (val) : htole16(val)) 121 #define HTOO32(val) (sc->sc_endian ? (val) : htole32(val)) 122 123 struct ohci_pipe; 124 125 Static void ohci_free_desc_chunks(ohci_softc_t *, 126 struct ohci_mdescs *); 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static usbd_status ohci_grow_std(ohci_softc_t *); 131 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 132 Static ohci_soft_td_t *ohci_alloc_std_norsv(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_norsv(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static usbd_status ohci_grow_sitd(ohci_softc_t *); 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static ohci_soft_itd_t *ohci_alloc_sitd_norsv(ohci_softc_t *); 139 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 140 Static void ohci_free_sitd_norsv(ohci_softc_t *,ohci_soft_itd_t *); 141 142 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 143 ohci_soft_td_t *); 144 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 145 ohci_softc_t *, int, int, usbd_xfer_handle, 146 ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(usbd_pipe_handle); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 152 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 153 154 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 158 Static void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 159 Static ohci_soft_td_t *ohci_find_td(ohci_softc_t *, ohci_physaddr_t); 160 Static ohci_soft_itd_t *ohci_find_itd(ohci_softc_t *, ohci_physaddr_t); 161 162 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 163 Static void ohci_device_isoc_enter(usbd_xfer_handle); 164 165 Static usbd_status ohci_prealloc(struct ohci_softc *, 166 struct ohci_xfer *, size_t, int); 167 Static usbd_status ohci_allocm(struct usbd_bus *, usbd_xfer_handle, 168 void *buf, size_t); 169 Static void ohci_freem(struct usbd_bus *, usbd_xfer_handle, 170 enum usbd_waitflg); 171 172 Static usbd_status ohci_map_alloc(usbd_xfer_handle); 173 Static void ohci_map_free(usbd_xfer_handle); 174 Static void ohci_mapm(usbd_xfer_handle, void *, size_t); 175 Static void ohci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 176 Static void ohci_unmapm(usbd_xfer_handle); 177 178 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *, usbd_pipe_handle, 179 enum usbd_waitflg); 180 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 181 182 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 183 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 184 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 185 Static void ohci_root_ctrl_close(usbd_pipe_handle); 186 Static void ohci_root_ctrl_done(usbd_xfer_handle); 187 188 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 189 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 190 Static void ohci_root_intr_abort(usbd_xfer_handle); 191 Static void ohci_root_intr_close(usbd_pipe_handle); 192 Static void ohci_root_intr_done(usbd_xfer_handle); 193 194 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 195 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 196 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 197 Static void ohci_device_ctrl_close(usbd_pipe_handle); 198 Static void ohci_device_ctrl_done(usbd_xfer_handle); 199 200 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 201 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 202 Static void ohci_device_bulk_abort(usbd_xfer_handle); 203 Static void ohci_device_bulk_close(usbd_pipe_handle); 204 Static void ohci_device_bulk_done(usbd_xfer_handle); 205 206 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 207 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 208 Static void ohci_device_intr_abort(usbd_xfer_handle); 209 Static void ohci_device_intr_close(usbd_pipe_handle); 210 Static void ohci_device_intr_done(usbd_xfer_handle); 211 212 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 213 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 214 Static void ohci_device_isoc_abort(usbd_xfer_handle); 215 Static void ohci_device_isoc_close(usbd_pipe_handle); 216 Static void ohci_device_isoc_done(usbd_xfer_handle); 217 218 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 219 struct ohci_pipe *pipe, int ival); 220 Static usbd_status ohci_device_intr_insert(ohci_softc_t *sc, 221 usbd_xfer_handle xfer); 222 223 Static int ohci_str(usb_string_descriptor_t *, int, const char *); 224 225 Static void ohci_timeout(void *); 226 Static void ohci_timeout_task(void *); 227 Static void ohci_rhsc_enable(void *); 228 229 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 230 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 231 232 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 233 Static void ohci_noop(usbd_pipe_handle pipe); 234 235 Static usbd_status ohci_controller_init(ohci_softc_t *sc); 236 237 #ifdef USB_DEBUG 238 Static void ohci_dumpregs(ohci_softc_t *); 239 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 240 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 241 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 242 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 243 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 244 #endif 245 246 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 247 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 248 #define OWRITE1(sc, r, x) \ 249 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 250 #define OWRITE2(sc, r, x) \ 251 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 252 #define OWRITE4(sc, r, x) \ 253 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 254 static __inline uint8_t 255 OREAD1(ohci_softc_t *sc, bus_size_t r) 256 { 257 258 OBARR(sc); 259 return bus_space_read_1(sc->iot, sc->ioh, r); 260 } 261 262 static __inline uint16_t 263 OREAD2(ohci_softc_t *sc, bus_size_t r) 264 { 265 266 OBARR(sc); 267 return bus_space_read_2(sc->iot, sc->ioh, r); 268 } 269 270 static __inline uint32_t 271 OREAD4(ohci_softc_t *sc, bus_size_t r) 272 { 273 274 OBARR(sc); 275 return bus_space_read_4(sc->iot, sc->ioh, r); 276 } 277 278 /* Reverse the bits in a value 0 .. 31 */ 279 Static u_int8_t revbits[OHCI_NO_INTRS] = 280 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 281 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 282 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 283 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 284 285 struct ohci_pipe { 286 struct usbd_pipe pipe; 287 ohci_soft_ed_t *sed; 288 u_int32_t aborting; 289 union { 290 ohci_soft_td_t *td; 291 ohci_soft_itd_t *itd; 292 } tail; 293 /* Info needed for different pipe kinds. */ 294 union { 295 /* Control pipe */ 296 struct { 297 usb_dma_t reqdma; 298 u_int length; 299 ohci_soft_td_t *setup, *data, *stat; 300 } ctl; 301 /* Interrupt pipe */ 302 struct { 303 int nslots; 304 int pos; 305 } intr; 306 /* Bulk pipe */ 307 struct { 308 u_int length; 309 int isread; 310 } bulk; 311 /* Iso pipe */ 312 struct iso { 313 int next, inuse; 314 } iso; 315 } u; 316 }; 317 318 #define OHCI_INTR_ENDPT 1 319 320 Static const struct usbd_bus_methods ohci_bus_methods = { 321 ohci_open, 322 ohci_softintr, 323 ohci_poll, 324 ohci_allocm, 325 ohci_freem, 326 ohci_map_alloc, 327 ohci_map_free, 328 ohci_mapm, 329 ohci_mapm_mbuf, 330 ohci_unmapm, 331 ohci_allocx, 332 ohci_freex, 333 }; 334 335 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 336 ohci_root_ctrl_transfer, 337 ohci_root_ctrl_start, 338 ohci_root_ctrl_abort, 339 ohci_root_ctrl_close, 340 ohci_noop, 341 ohci_root_ctrl_done, 342 }; 343 344 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 345 ohci_root_intr_transfer, 346 ohci_root_intr_start, 347 ohci_root_intr_abort, 348 ohci_root_intr_close, 349 ohci_noop, 350 ohci_root_intr_done, 351 }; 352 353 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 354 ohci_device_ctrl_transfer, 355 ohci_device_ctrl_start, 356 ohci_device_ctrl_abort, 357 ohci_device_ctrl_close, 358 ohci_noop, 359 ohci_device_ctrl_done, 360 }; 361 362 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 363 ohci_device_intr_transfer, 364 ohci_device_intr_start, 365 ohci_device_intr_abort, 366 ohci_device_intr_close, 367 ohci_device_clear_toggle, 368 ohci_device_intr_done, 369 }; 370 371 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 372 ohci_device_bulk_transfer, 373 ohci_device_bulk_start, 374 ohci_device_bulk_abort, 375 ohci_device_bulk_close, 376 ohci_device_clear_toggle, 377 ohci_device_bulk_done, 378 }; 379 380 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 381 ohci_device_isoc_transfer, 382 ohci_device_isoc_start, 383 ohci_device_isoc_abort, 384 ohci_device_isoc_close, 385 ohci_noop, 386 ohci_device_isoc_done, 387 }; 388 389 #if defined(__NetBSD__) || defined(__OpenBSD__) 390 int 391 ohci_activate(device_t self, enum devact act) 392 { 393 struct ohci_softc *sc = (struct ohci_softc *)self; 394 int rv = 0; 395 396 switch (act) { 397 case DVACT_ACTIVATE: 398 return (EOPNOTSUPP); 399 400 case DVACT_DEACTIVATE: 401 if (sc->sc_child != NULL) 402 rv = config_deactivate(sc->sc_child); 403 sc->sc_dying = 1; 404 break; 405 } 406 return (rv); 407 } 408 #endif 409 410 int 411 ohci_detach(struct ohci_softc *sc, int flags) 412 { 413 int rv = 0; 414 usbd_xfer_handle xfer; 415 416 sc->sc_dying = 1; 417 418 #if defined(__NetBSD__) || defined(__OpenBSD__) 419 if (sc->sc_child != NULL) 420 rv = config_detach(sc->sc_child, flags); 421 422 if (rv != 0) 423 return (rv); 424 #endif 425 426 if (sc->sc_bus.methods == NULL) 427 return (rv); /* attach has been aborted */ 428 429 usb_uncallout(sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 430 431 #if defined(__NetBSD__) || defined(__OpenBSD__) 432 powerhook_disestablish(sc->sc_powerhook); 433 shutdownhook_disestablish(sc->sc_shutdownhook); 434 #endif 435 436 #if defined(__NetBSD__) || defined(__OpenBSD__) 437 /* Don't touch hardware if it has already been gone. */ 438 if ((flags & DETACH_FORCE) == 0) 439 #endif 440 { 441 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 442 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 443 } 444 445 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 446 447 #if 0 /* freed by ohci_free_desc_chunks(sc, &sc->sc_sed_chunks) below */ 448 for (i = 0; i < OHCI_NO_EDS; i++) 449 ohci_free_sed(sc, sc->sc_eds[i]); 450 ohci_free_sed(sc, sc->sc_isoc_head); 451 ohci_free_sed(sc, sc->sc_bulk_head); 452 ohci_free_sed(sc, sc->sc_ctrl_head); 453 #endif 454 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 455 456 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 457 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 458 usb_clean_buffer_dma(&sc->sc_dmatag, &OXFER(xfer)->dmabuf); 459 free(xfer, M_USB); 460 } 461 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 462 ohci_free_desc_chunks(sc, &sc->sc_std_chunks); 463 ohci_free_desc_chunks(sc, &sc->sc_sitd_chunks); 464 usb_dma_tag_finish(&sc->sc_dmatag); 465 466 return (rv); 467 } 468 469 Static void 470 ohci_free_desc_chunks(ohci_softc_t *sc, struct ohci_mdescs *c) 471 { 472 struct ohci_mem_desc *om; 473 474 while ((om = SIMPLEQ_FIRST(c)) != NULL) { 475 SIMPLEQ_REMOVE_HEAD(c, om_next); 476 usb_freemem(&sc->sc_dmatag, &om->om_dma); 477 } 478 } 479 480 ohci_soft_ed_t * 481 ohci_alloc_sed(ohci_softc_t *sc) 482 { 483 ohci_soft_ed_t *sed; 484 usbd_status err; 485 int i, offs; 486 usb_dma_t dma; 487 struct ohci_mem_desc *om; 488 489 if (sc->sc_freeeds == NULL) { 490 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 491 err = usb_allocmem(&sc->sc_dmatag, 492 OHCI_SED_SIZE*OHCI_SED_CHUNK + sizeof(struct ohci_mem_desc), 493 OHCI_ED_ALIGN, &dma); 494 if (err) 495 return (NULL); 496 om = KERNADDR(&dma, OHCI_SED_SIZE * OHCI_SED_CHUNK); 497 om->om_top = KERNADDR(&dma, 0); 498 om->om_topdma = DMAADDR(&dma, 0); 499 om->om_dma = dma; 500 SIMPLEQ_INSERT_HEAD(&sc->sc_sed_chunks, om, om_next); 501 for(i = 0; i < OHCI_SED_CHUNK; i++) { 502 offs = i * OHCI_SED_SIZE; 503 sed = KERNADDR(&dma, offs); 504 sed->oe_mdesc = om; 505 sed->next = sc->sc_freeeds; 506 sc->sc_freeeds = sed; 507 } 508 } 509 sed = sc->sc_freeeds; 510 sc->sc_freeeds = sed->next; 511 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 512 sed->next = 0; 513 return (sed); 514 } 515 516 void 517 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 518 { 519 sed->next = sc->sc_freeeds; 520 sc->sc_freeeds = sed; 521 } 522 523 Static usbd_status 524 ohci_grow_std(ohci_softc_t *sc) 525 { 526 usb_dma_t dma; 527 struct ohci_mem_desc *om; 528 ohci_soft_td_t *std; 529 usbd_status err; 530 int i, s, offs; 531 532 DPRINTFN(2, ("ohci_grow_std: allocating chunk\n")); 533 err = usb_allocmem(&sc->sc_dmatag, 534 OHCI_STD_SIZE*OHCI_STD_CHUNK + sizeof(struct ohci_mem_desc), 535 OHCI_TD_ALIGN, &dma); 536 if (err) 537 return (err); 538 om = KERNADDR(&dma, OHCI_STD_SIZE * OHCI_STD_CHUNK); 539 om->om_top = KERNADDR(&dma, 0); 540 om->om_topdma = DMAADDR(&dma, 0); 541 om->om_dma = dma; 542 s = splusb(); 543 SIMPLEQ_INSERT_HEAD(&sc->sc_std_chunks, om, om_next); 544 for(i = 0; i < OHCI_STD_CHUNK; i++) { 545 offs = i * OHCI_STD_SIZE; 546 std = KERNADDR(&dma, offs); 547 std->ot_mdesc = om; 548 std->nexttd = sc->sc_freetds; 549 sc->sc_freetds = std; 550 sc->sc_nfreetds++; 551 } 552 splx(s); 553 554 return (USBD_NORMAL_COMPLETION); 555 } 556 557 ohci_soft_td_t * 558 ohci_alloc_std(ohci_softc_t *sc) 559 { 560 ohci_soft_td_t *std; 561 int s; 562 563 s = splusb(); 564 565 #ifdef DIAGNOSTIC 566 if (sc->sc_freetds == NULL) 567 panic("ohci_alloc_std: %d", sc->sc_nfreetds); 568 #endif 569 std = sc->sc_freetds; 570 sc->sc_freetds = std->nexttd; 571 splx(s); 572 memset(&std->td, 0, sizeof(ohci_td_t)); 573 std->nexttd = NULL; 574 std->xfer = NULL; 575 std->flags = 0; 576 577 return (std); 578 } 579 580 Static ohci_soft_td_t * 581 ohci_alloc_std_norsv(ohci_softc_t *sc) 582 { 583 int s; 584 585 s = splusb(); 586 if (sc->sc_nfreetds < 1) 587 if (ohci_grow_std(sc)) 588 return (NULL); 589 sc->sc_nfreetds--; 590 splx(s); 591 return (ohci_alloc_std(sc)); 592 } 593 594 void 595 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 596 { 597 int s; 598 599 s = splusb(); 600 std->flags = OHCI_TD_FREE; 601 std->nexttd = sc->sc_freetds; 602 sc->sc_freetds = std; 603 splx(s); 604 } 605 606 Static void 607 ohci_free_std_norsv(ohci_softc_t *sc, ohci_soft_td_t *std) 608 { 609 int s; 610 611 ohci_free_std(sc, std); 612 s = splusb(); 613 sc->sc_nfreetds++; 614 splx(s); 615 } 616 617 usbd_status 618 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 619 int alen, int rd, usbd_xfer_handle xfer, 620 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 621 { 622 ohci_soft_td_t *next, *cur, *end; 623 ohci_physaddr_t tddma, segdmaadr, dmaend; 624 u_int32_t tdflags; 625 int len, maxp, curlen, seg, seglen; 626 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 627 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 628 int nsegs = USB_BUFFER_NSEGS(ub); 629 u_int16_t flags = xfer->flags; 630 631 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 632 633 len = alen; 634 cur = sp; 635 end = NULL; 636 637 maxp = UE_MAXPKTSZ(opipe->pipe.endpoint->edesc); 638 tdflags = HTOO32( 639 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 640 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 641 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_SET_DI(6)); 642 643 seg = 0; 644 seglen = 0; 645 segdmaadr = 0; 646 while (len > 0) { 647 /* sync last entry */ 648 if (end) 649 OHCI_STD_SYNC(sc, end, 650 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 651 652 next = ohci_alloc_std(sc); 653 if (next == NULL) 654 goto nomem; 655 656 /* 657 * The OHCI hardware can handle at most one 4K crossing. 658 * The OHCI spec says: If during the data transfer the buffer 659 * address contained in the HC's working copy of 660 * CurrentBufferPointer crosses a 4K boundary, the upper 20 661 * bits of Buffer End are copied to the working value of 662 * CurrentBufferPointer causing the next buffer address to 663 * be the 0th byte in the same 4K page that contains the 664 * last byte of the buffer (the 4K boundary crossing may 665 * occur within a data packet transfer.) 666 */ 667 668 /* gather segments that are continuous in DMA address */ 669 /* XXX Does this make any sense? */ 670 if (seglen == 0) { 671 USB_KASSERT2(seg < nsegs, 672 ("ohci_alloc_std_chain: overrun")); 673 segdmaadr = segs[seg].ds_addr; 674 do { 675 seglen += segs[seg].ds_len; 676 } while (++seg < nsegs && 677 segdmaadr + seglen == segs[seg].ds_addr); 678 679 if (seglen > len) 680 seglen = len; 681 } 682 683 curlen = seglen; 684 dmaend = segdmaadr + curlen; 685 if ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) == 0) 686 dmaend--; 687 dmaend = OHCI_PAGE(dmaend); 688 689 if (OHCI_PAGE(segdmaadr) != dmaend && 690 OHCI_PAGE(segdmaadr) + OHCI_PAGE_SIZE != dmaend) { 691 /* must use multiple TDs, fill as much as possible. */ 692 curlen = 2 * OHCI_PAGE_SIZE - 693 (segdmaadr & (OHCI_PAGE_SIZE-1)); 694 695 if (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) 696 curlen--; 697 698 /* the length must be a multiple of the max size */ 699 if (curlen < len) 700 curlen -= curlen % maxp; 701 USB_KASSERT(curlen); 702 USB_KASSERT2(curlen <= seglen, 703 ("ohci_alloc_std_chain: curlen %d > seglen %d", 704 curlen, len)); 705 } 706 DPRINTFN(4,("ohci_alloc_std_chain: segdmaadr=0x%08x " 707 "dmaend=0x%08x len=%d seglen=%d curlen=%d\n", 708 segdmaadr, dmaend, 709 len, seglen, curlen)); 710 len -= curlen; 711 712 cur->td.td_flags = tdflags; 713 cur->td.td_cbp = HTOO32(segdmaadr); 714 cur->nexttd = next; 715 tddma = OHCI_STD_DMAADDR(next); 716 cur->td.td_nexttd = HTOO32(tddma); 717 cur->td.td_be = HTOO32(segdmaadr + curlen - 1); 718 cur->len = curlen; 719 cur->flags = OHCI_ADD_LEN; 720 cur->xfer = xfer; 721 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 722 segdmaadr, segdmaadr + curlen - 1)); 723 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 724 seglen -= curlen; 725 segdmaadr += curlen; 726 727 end = cur; 728 cur = next; 729 } 730 if (((flags & USBD_FORCE_SHORT_XFER) || alen == 0) && 731 alen % maxp == 0) { 732 if (end) 733 OHCI_STD_SYNC(sc, end, 734 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 735 736 /* Force a 0 length transfer at the end. */ 737 next = ohci_alloc_std(sc); 738 if (next == NULL) 739 goto nomem; 740 741 cur->td.td_flags = tdflags; 742 cur->td.td_cbp = 0; /* indicate 0 length packet */ 743 cur->nexttd = next; 744 tddma = OHCI_STD_DMAADDR(next); 745 cur->td.td_nexttd = HTOO32(tddma); 746 cur->td.td_be = ~0; 747 cur->len = 0; 748 cur->flags = 0; 749 cur->xfer = xfer; 750 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 751 end = cur; 752 } 753 *ep = end; 754 755 return (USBD_NORMAL_COMPLETION); 756 757 nomem: 758 /* free chain */ 759 if (end) 760 ohci_free_std_chain(sc, sp->nexttd, end); 761 return (USBD_NOMEM); 762 } 763 764 Static void 765 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 766 ohci_soft_td_t *stdend) 767 { 768 ohci_soft_td_t *p; 769 770 for (; std != stdend; std = p) { 771 p = std->nexttd; 772 ohci_free_std(sc, std); 773 } 774 ohci_free_std(sc, stdend); 775 } 776 777 Static usbd_status 778 ohci_grow_sitd(ohci_softc_t *sc) 779 { 780 usb_dma_t dma; 781 struct ohci_mem_desc *om; 782 ohci_soft_itd_t *sitd; 783 usbd_status err; 784 int i, s, offs; 785 786 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 787 err = usb_allocmem(&sc->sc_dmatag, 788 OHCI_SITD_SIZE*OHCI_SITD_CHUNK + sizeof(struct ohci_mem_desc), 789 OHCI_ITD_ALIGN, &dma); 790 if (err) 791 return (err); 792 om = KERNADDR(&dma, OHCI_SITD_SIZE * OHCI_SITD_CHUNK); 793 om->om_top = KERNADDR(&dma, 0); 794 om->om_topdma = DMAADDR(&dma, 0); 795 om->om_dma = dma; 796 s = splusb(); 797 SIMPLEQ_INSERT_HEAD(&sc->sc_sitd_chunks, om, om_next); 798 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 799 offs = i * OHCI_SITD_SIZE; 800 sitd = KERNADDR(&dma, offs); 801 sitd->oit_mdesc = om; 802 sitd->nextitd = sc->sc_freeitds; 803 sc->sc_freeitds = sitd; 804 sc->sc_nfreeitds++; 805 } 806 splx(s); 807 808 return (USBD_NORMAL_COMPLETION); 809 } 810 811 ohci_soft_itd_t * 812 ohci_alloc_sitd(ohci_softc_t *sc) 813 { 814 ohci_soft_itd_t *sitd; 815 int s; 816 817 #ifdef DIAGNOSTIC 818 if (sc->sc_freeitds == NULL) 819 panic("ohci_alloc_sitd: %d", sc->sc_nfreeitds); 820 #endif 821 822 s = splusb(); 823 sitd = sc->sc_freeitds; 824 sc->sc_freeitds = sitd->nextitd; 825 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 826 sitd->nextitd = NULL; 827 sitd->xfer = NULL; 828 sitd->flags = 0; 829 splx(s); 830 831 #ifdef DIAGNOSTIC 832 sitd->isdone = 0; 833 #endif 834 835 return (sitd); 836 } 837 838 Static ohci_soft_itd_t * 839 ohci_alloc_sitd_norsv(ohci_softc_t *sc) 840 { 841 int s; 842 843 s = splusb(); 844 if (sc->sc_nfreeitds < 1) 845 if (ohci_grow_sitd(sc)) 846 return (NULL); 847 sc->sc_nfreeitds--; 848 splx(s); 849 return (ohci_alloc_sitd_norsv(sc)); 850 } 851 852 void 853 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 854 { 855 int s; 856 857 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 858 859 #ifdef DIAGNOSTIC 860 if (!sitd->isdone) { 861 panic("ohci_free_sitd: sitd=%p not done", sitd); 862 return; 863 } 864 /* Warn double free */ 865 sitd->isdone = 0; 866 #endif 867 868 s = splusb(); 869 sitd->flags = OHCI_ITD_FREE; 870 sitd->nextitd = sc->sc_freeitds; 871 sc->sc_freeitds = sitd; 872 splx(s); 873 } 874 875 Static void 876 ohci_free_sitd_norsv(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 877 { 878 int s; 879 880 ohci_free_sitd(sc, sitd); 881 s = splusb(); 882 sc->sc_nfreeitds++; 883 splx(s); 884 } 885 886 usbd_status 887 ohci_init(ohci_softc_t *sc) 888 { 889 ohci_soft_ed_t *sed, *psed; 890 ohci_physaddr_t eddma; 891 usbd_status err; 892 int i; 893 u_int32_t rev; 894 895 DPRINTF(("ohci_init: start\n")); 896 #if defined(__OpenBSD__) 897 printf(","); 898 #else 899 printf("%s:", USBDEVNAME(sc->sc_bus.bdev)); 900 #endif 901 rev = OREAD4(sc, OHCI_REVISION); 902 printf(" OHCI version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 903 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 904 905 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 906 printf("%s: unsupported OHCI revision\n", 907 USBDEVNAME(sc->sc_bus.bdev)); 908 sc->sc_bus.usbrev = USBREV_UNKNOWN; 909 return (USBD_INVAL); 910 } 911 sc->sc_bus.usbrev = USBREV_1_0; 912 913 SIMPLEQ_INIT(&sc->sc_free_xfers); 914 SIMPLEQ_INIT(&sc->sc_sed_chunks); 915 SIMPLEQ_INIT(&sc->sc_std_chunks); 916 SIMPLEQ_INIT(&sc->sc_sitd_chunks); 917 918 usb_dma_tag_init(&sc->sc_dmatag); 919 920 /* XXX determine alignment by R/W */ 921 /* Allocate the HCCA area. */ 922 err = usb_allocmem(&sc->sc_dmatag, OHCI_HCCA_SIZE, 923 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 924 if (err) 925 goto bad1; 926 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 927 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 928 929 sc->sc_eintrs = OHCI_NORMAL_INTRS; 930 931 /* Allocate dummy ED that starts the control list. */ 932 sc->sc_ctrl_head = ohci_alloc_sed(sc); 933 if (sc->sc_ctrl_head == NULL) { 934 err = USBD_NOMEM; 935 goto bad2; 936 } 937 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 938 939 /* Allocate dummy ED that starts the bulk list. */ 940 sc->sc_bulk_head = ohci_alloc_sed(sc); 941 if (sc->sc_bulk_head == NULL) { 942 err = USBD_NOMEM; 943 goto bad3; 944 } 945 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 946 947 /* Allocate dummy ED that starts the isochronous list. */ 948 sc->sc_isoc_head = ohci_alloc_sed(sc); 949 if (sc->sc_isoc_head == NULL) { 950 err = USBD_NOMEM; 951 goto bad3; 952 } 953 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 954 955 /* Allocate all the dummy EDs that make up the interrupt tree. */ 956 for (i = 0; i < OHCI_NO_EDS; i++) { 957 sed = ohci_alloc_sed(sc); 958 if (sed == NULL) { 959 while (--i >= 0) 960 ohci_free_sed(sc, sc->sc_eds[i]); 961 err = USBD_NOMEM; 962 goto bad3; 963 } 964 /* All ED fields are set to 0. */ 965 sc->sc_eds[i] = sed; 966 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 967 if (i != 0) 968 psed = sc->sc_eds[(i-1) / 2]; 969 else 970 psed = sc->sc_isoc_head; 971 sed->next = psed; 972 eddma = OHCI_SED_DMAADDR(psed); 973 sed->ed.ed_nexted = HTOO32(eddma); 974 } 975 /* 976 * Fill HCCA interrupt table. The bit reversal is to get 977 * the tree set up properly to spread the interrupts. 978 */ 979 for (i = 0; i < OHCI_NO_INTRS; i++) { 980 eddma = OHCI_SED_DMAADDR(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]); 981 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = HTOO32(eddma); 982 } 983 984 #ifdef USB_DEBUG 985 if (ohcidebug > 15) { 986 for (i = 0; i < OHCI_NO_EDS; i++) { 987 printf("ed#%d ", i); 988 ohci_dump_ed(sc, sc->sc_eds[i]); 989 } 990 printf("iso "); 991 ohci_dump_ed(sc, sc->sc_isoc_head); 992 } 993 #endif 994 995 err = ohci_controller_init(sc); 996 if (err != USBD_NORMAL_COMPLETION) 997 goto bad3; 998 999 /* Set up the bus struct. */ 1000 sc->sc_bus.methods = &ohci_bus_methods; 1001 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 1002 1003 #if defined(__NetBSD__) || defined(__OpenBSD__) 1004 sc->sc_control = sc->sc_intre = 0; 1005 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 1006 ohci_power, sc); 1007 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 1008 #endif 1009 1010 usb_callout_init(sc->sc_tmo_rhsc); 1011 1012 /* Finally, turn on interrupts. */ 1013 DPRINTFN(1,("ohci_init: enabling\n")); 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1015 1016 return (USBD_NORMAL_COMPLETION); 1017 1018 bad3: 1019 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 1020 bad2: 1021 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 1022 bad1: 1023 usb_dma_tag_finish(&sc->sc_dmatag); 1024 return (err); 1025 } 1026 1027 Static usbd_status 1028 ohci_controller_init(ohci_softc_t *sc) 1029 { 1030 int i; 1031 u_int32_t s, ctl, rwc, ival, hcr, fm, per, desca, descb; 1032 1033 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 1034 ctl = OREAD4(sc, OHCI_CONTROL); 1035 rwc = ctl & OHCI_RWC; 1036 fm = OREAD4(sc, OHCI_FM_INTERVAL); 1037 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1038 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1039 1040 /* Determine in what context we are running. */ 1041 if (ctl & OHCI_IR) { 1042 /* SMM active, request change */ 1043 DPRINTF(("ohci_init: SMM active, request owner change\n")); 1044 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 1045 (OHCI_OC | OHCI_MIE)) 1046 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 1047 s = OREAD4(sc, OHCI_COMMAND_STATUS); 1048 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 1049 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 1050 usb_delay_ms(&sc->sc_bus, 1); 1051 ctl = OREAD4(sc, OHCI_CONTROL); 1052 } 1053 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 1054 if ((ctl & OHCI_IR) == 0) { 1055 printf("%s: SMM does not respond, resetting\n", 1056 USBDEVNAME(sc->sc_bus.bdev)); 1057 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1058 goto reset; 1059 } 1060 #if 0 1061 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 1062 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 1063 /* BIOS started controller. */ 1064 DPRINTF(("ohci_init: BIOS active\n")); 1065 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 1066 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 1067 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1068 } 1069 #endif 1070 } else { 1071 DPRINTF(("ohci_init: cold started\n")); 1072 reset: 1073 /* Controller was cold started. */ 1074 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1075 } 1076 1077 /* 1078 * This reset should not be necessary according to the OHCI spec, but 1079 * without it some controllers do not start. 1080 */ 1081 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 1082 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1083 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1084 1085 /* We now own the host controller and the bus has been reset. */ 1086 1087 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1088 /* Nominal time for a reset is 10 us. */ 1089 for (i = 0; i < 10; i++) { 1090 delay(10); 1091 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1092 if (!hcr) 1093 break; 1094 } 1095 if (hcr) { 1096 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 1097 return (USBD_IOERROR); 1098 } 1099 #ifdef USB_DEBUG 1100 if (ohcidebug > 15) 1101 ohci_dumpregs(sc); 1102 #endif 1103 1104 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1105 1106 /* Set up HC registers. */ 1107 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1108 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_ctrl_head)); 1109 OWRITE4(sc, OHCI_BULK_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_bulk_head)); 1110 /* disable all interrupts and then switch on all desired interrupts */ 1111 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1112 /* switch on desired functional features */ 1113 ctl = OREAD4(sc, OHCI_CONTROL); 1114 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1115 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1116 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1117 /* And finally start it! */ 1118 OWRITE4(sc, OHCI_CONTROL, ctl); 1119 1120 /* 1121 * The controller is now OPERATIONAL. Set a some final 1122 * registers that should be set earlier, but that the 1123 * controller ignores when in the SUSPEND state. 1124 */ 1125 ival = OHCI_GET_IVAL(fm); 1126 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1127 fm |= OHCI_FSMPS(ival) | ival; 1128 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1129 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1130 OWRITE4(sc, OHCI_PERIODIC_START, per); 1131 1132 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1133 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1134 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1135 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1136 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1137 1138 /* 1139 * The AMD756 requires a delay before re-reading the register, 1140 * otherwise it will occasionally report 0 ports. 1141 */ 1142 sc->sc_noport = 0; 1143 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1144 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1145 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1146 } 1147 1148 #ifdef USB_DEBUG 1149 if (ohcidebug > 5) 1150 ohci_dumpregs(sc); 1151 #endif 1152 return (USBD_NORMAL_COMPLETION); 1153 } 1154 1155 Static usbd_status 1156 ohci_prealloc(struct ohci_softc *sc, struct ohci_xfer *oxfer, 1157 size_t bufsize, int nseg) 1158 { 1159 struct usbd_pipe *pipe; 1160 int maxseg, maxp; 1161 int seglen, ntd; 1162 int s; 1163 int err; 1164 1165 pipe = oxfer->xfer.pipe; 1166 maxp = UE_MAXPKTSZ(pipe->endpoint->edesc); 1167 1168 if (maxp == 0) 1169 return (USBD_INVAL); 1170 1171 /* (over) estimate needed number of TDs */ 1172 maxseg = (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) ? 4096 : 8192; 1173 seglen = maxseg - (maxseg % maxp); 1174 ntd = bufsize / seglen + nseg; 1175 1176 s = splusb(); 1177 if ((pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1178 UE_ISOCHRONOUS) { 1179 /* pre-allocate ITDs */ 1180 while (sc->sc_nfreeitds < ntd) { 1181 DPRINTF(("%s: ohci_prealloc: need %d ITD (%d cur)\n", 1182 USBDEVNAME(sc->sc_bus.bdev), 1183 ntd, sc->sc_nfreeitds)); 1184 if ((err = ohci_grow_sitd(sc)) 1185 != USBD_NORMAL_COMPLETION) { 1186 splx(s); 1187 return (err); 1188 } 1189 } 1190 sc->sc_nfreeitds -= ntd; 1191 } else { 1192 /* pre-allocate TDs */ 1193 while (sc->sc_nfreetds < ntd) { 1194 DPRINTF(("%s: ohci_prealloc: need %d TD (%d cur)\n", 1195 USBDEVNAME(sc->sc_bus.bdev), 1196 ntd, sc->sc_nfreetds)); 1197 if ((err = ohci_grow_std(sc)) 1198 != USBD_NORMAL_COMPLETION) { 1199 splx(s); 1200 return (err); 1201 } 1202 } 1203 sc->sc_nfreetds -= ntd; 1204 } 1205 splx(s); 1206 1207 oxfer->rsvd_tds = ntd; 1208 1209 return (USBD_NORMAL_COMPLETION); 1210 } 1211 1212 usbd_status 1213 ohci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1214 { 1215 struct ohci_softc *sc = (struct ohci_softc *)bus; 1216 struct ohci_xfer *oxfer = OXFER(xfer); 1217 usbd_status err; 1218 1219 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1220 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1221 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1222 (err = ohci_prealloc(sc, oxfer, size, 1223 USB_BUFFER_NSEGS(&oxfer->dmabuf))) 1224 != USBD_NORMAL_COMPLETION) { 1225 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1226 U_WAITOK); 1227 } 1228 } 1229 1230 return err; 1231 } 1232 1233 void 1234 ohci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1235 enum usbd_waitflg waitflg) 1236 { 1237 struct ohci_softc *sc = (struct ohci_softc *)bus; 1238 struct ohci_xfer *oxfer = OXFER(xfer); 1239 int s; 1240 1241 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, waitflg); 1242 1243 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1244 s = splusb(); 1245 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1246 UE_ISOCHRONOUS) { 1247 sc->sc_nfreeitds += oxfer->rsvd_tds; 1248 } else { 1249 sc->sc_nfreetds += oxfer->rsvd_tds; 1250 } 1251 splx(s); 1252 oxfer->rsvd_tds = 0; 1253 } 1254 } 1255 1256 Static usbd_status 1257 ohci_map_alloc(usbd_xfer_handle xfer) 1258 { 1259 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1260 struct ohci_xfer *oxfer = OXFER(xfer); 1261 usbd_status st; 1262 1263 st = usb_alloc_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1264 if (st) 1265 return st; 1266 1267 if ((st = ohci_prealloc(sc, oxfer, MAXPHYS, USB_DMA_NSEG))) { 1268 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1269 } 1270 1271 return st; 1272 } 1273 1274 Static void 1275 ohci_map_free(usbd_xfer_handle xfer) 1276 { 1277 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1278 struct ohci_xfer *oxfer = OXFER(xfer); 1279 int s; 1280 1281 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1282 1283 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1284 1285 s = splusb(); 1286 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1287 UE_ISOCHRONOUS) { 1288 sc->sc_nfreeitds += oxfer->rsvd_tds; 1289 } else { 1290 sc->sc_nfreetds += oxfer->rsvd_tds; 1291 } 1292 splx(s); 1293 oxfer->rsvd_tds = 0; 1294 } 1295 1296 Static void 1297 ohci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1298 { 1299 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1300 struct ohci_xfer *oxfer = OXFER(xfer); 1301 1302 usb_map_dma(&sc->sc_dmatag, &oxfer->dmabuf, buf, size); 1303 } 1304 1305 Static void 1306 ohci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1307 { 1308 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1309 struct ohci_xfer *oxfer = OXFER(xfer); 1310 1311 usb_map_mbuf_dma(&sc->sc_dmatag, &oxfer->dmabuf, chain); 1312 } 1313 1314 Static void 1315 ohci_unmapm(usbd_xfer_handle xfer) 1316 { 1317 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1318 struct ohci_xfer *oxfer = OXFER(xfer); 1319 1320 usb_unmap_dma(&sc->sc_dmatag, &oxfer->dmabuf); 1321 } 1322 1323 usbd_xfer_handle 1324 ohci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1325 enum usbd_waitflg waitflg) 1326 { 1327 struct ohci_softc *sc = (struct ohci_softc *)bus; 1328 usbd_xfer_handle xfer; 1329 1330 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1331 if (xfer != NULL) { 1332 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1333 #ifdef DIAGNOSTIC 1334 if (xfer->busy_free != XFER_FREE) { 1335 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1336 xfer->busy_free); 1337 } 1338 #endif 1339 } else { 1340 xfer = malloc(sizeof(struct ohci_xfer), M_USB, 1341 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1342 } 1343 if (xfer != NULL) { 1344 memset(xfer, 0, sizeof (struct ohci_xfer)); 1345 usb_init_task(&OXFER(xfer)->abort_task, ohci_timeout_task, 1346 xfer); 1347 OXFER(xfer)->ohci_xfer_flags = 0; 1348 OXFER(xfer)->rsvd_tds = 0; 1349 #ifdef DIAGNOSTIC 1350 xfer->busy_free = XFER_BUSY; 1351 #endif 1352 } 1353 return (xfer); 1354 } 1355 1356 void 1357 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1358 { 1359 struct ohci_softc *sc = (struct ohci_softc *)bus; 1360 1361 #ifdef DIAGNOSTIC 1362 if (xfer->busy_free != XFER_BUSY) { 1363 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1364 xfer->busy_free); 1365 } 1366 xfer->busy_free = XFER_FREE; 1367 #endif 1368 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1369 } 1370 1371 /* 1372 * Shut down the controller when the system is going down. 1373 */ 1374 void 1375 ohci_shutdown(void *v) 1376 { 1377 ohci_softc_t *sc = v; 1378 1379 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1380 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1381 } 1382 1383 /* 1384 * Handle suspend/resume. 1385 * 1386 * We need to switch to polling mode here, because this routine is 1387 * called from an interupt context. This is all right since we 1388 * are almost suspended anyway. 1389 */ 1390 void 1391 ohci_power(int why, void *v) 1392 { 1393 ohci_softc_t *sc = v; 1394 u_int32_t ctl; 1395 int s; 1396 1397 #ifdef USB_DEBUG 1398 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 1399 ohci_dumpregs(sc); 1400 #endif 1401 1402 s = splhardusb(); 1403 switch (why) { 1404 USB_PWR_CASE_SUSPEND: 1405 sc->sc_bus.use_polling++; 1406 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1407 if (sc->sc_control == 0) { 1408 /* 1409 * Preserve register values, in case that APM BIOS 1410 * does not recover them. 1411 */ 1412 sc->sc_control = ctl; 1413 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 1414 } 1415 ctl |= OHCI_HCFS_SUSPEND; 1416 OWRITE4(sc, OHCI_CONTROL, ctl); 1417 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1418 sc->sc_bus.use_polling--; 1419 break; 1420 1421 USB_PWR_CASE_RESUME: 1422 sc->sc_bus.use_polling++; 1423 1424 /* Some broken BIOSes never initialize Controller chip */ 1425 ohci_controller_init(sc); 1426 1427 if (sc->sc_intre) 1428 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 1429 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 1430 if (sc->sc_control) 1431 ctl = sc->sc_control; 1432 else 1433 ctl = OREAD4(sc, OHCI_CONTROL); 1434 ctl |= OHCI_HCFS_RESUME; 1435 OWRITE4(sc, OHCI_CONTROL, ctl); 1436 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1437 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1438 OWRITE4(sc, OHCI_CONTROL, ctl); 1439 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1440 sc->sc_control = sc->sc_intre = 0; 1441 sc->sc_bus.use_polling--; 1442 break; 1443 1444 default: 1445 break; 1446 } 1447 splx(s); 1448 } 1449 1450 #ifdef USB_DEBUG 1451 void 1452 ohci_dumpregs(ohci_softc_t *sc) 1453 { 1454 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1455 OREAD4(sc, OHCI_REVISION), 1456 OREAD4(sc, OHCI_CONTROL), 1457 OREAD4(sc, OHCI_COMMAND_STATUS))); 1458 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1459 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1460 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1461 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1462 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1463 OREAD4(sc, OHCI_HCCA), 1464 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1465 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1466 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1467 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1468 OREAD4(sc, OHCI_BULK_HEAD_ED), 1469 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1470 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1471 OREAD4(sc, OHCI_DONE_HEAD), 1472 OREAD4(sc, OHCI_FM_INTERVAL), 1473 OREAD4(sc, OHCI_FM_REMAINING))); 1474 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1475 OREAD4(sc, OHCI_FM_NUMBER), 1476 OREAD4(sc, OHCI_PERIODIC_START), 1477 OREAD4(sc, OHCI_LS_THRESHOLD))); 1478 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1479 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1480 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1481 OREAD4(sc, OHCI_RH_STATUS))); 1482 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1483 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1484 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1485 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1486 O32TOH(sc->sc_hcca->hcca_frame_number), 1487 O32TOH(sc->sc_hcca->hcca_done_head))); 1488 } 1489 #endif 1490 1491 Static int ohci_intr1(ohci_softc_t *); 1492 1493 #if defined(__NetBSD__) || defined(__OpenBSD__) 1494 int 1495 #elif defined(__FreeBSD__) 1496 void 1497 #endif 1498 ohci_intr(void *p) 1499 { 1500 ohci_softc_t *sc = p; 1501 1502 if (sc == NULL || sc->sc_dying) 1503 #if defined(__NetBSD__) || defined(__OpenBSD__) 1504 return (0); 1505 #elif defined(__FreeBSD__) 1506 return; 1507 #endif 1508 1509 /* If we get an interrupt while polling, then just ignore it. */ 1510 if (sc->sc_bus.use_polling) { 1511 #ifdef DIAGNOSTIC 1512 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1513 #endif 1514 /* for level triggered intrs, should do something to ack */ 1515 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1516 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1517 1518 #if defined(__NetBSD__) || defined(__OpenBSD__) 1519 return (0); 1520 #elif defined(__FreeBSD__) 1521 return; 1522 #endif 1523 } 1524 1525 #if defined(__NetBSD__) || defined(__OpenBSD__) 1526 return 1527 #endif 1528 ohci_intr1(sc); 1529 } 1530 1531 Static int 1532 ohci_intr1(ohci_softc_t *sc) 1533 { 1534 u_int32_t intrs, eintrs; 1535 1536 DPRINTFN(14,("ohci_intr1: enter\n")); 1537 1538 /* In case the interrupt occurs before initialization has completed. */ 1539 if (sc == NULL || sc->sc_hcca == NULL) { 1540 #ifdef DIAGNOSTIC 1541 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1542 #endif 1543 return (0); 1544 } 1545 1546 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1547 1548 if (intrs == 0) /* nothing to be done (PCI shared interrupt) */ 1549 return (0); 1550 1551 /* Acknowledge */ 1552 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1553 1554 eintrs = intrs & sc->sc_eintrs; 1555 if (!eintrs) 1556 return (0); 1557 1558 sc->sc_bus.intr_context++; 1559 sc->sc_bus.no_intrs++; 1560 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1561 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1562 (u_int)eintrs)); 1563 1564 if (eintrs & OHCI_SO) { 1565 sc->sc_overrun_cnt++; 1566 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1567 printf("%s: %u scheduling overruns\n", 1568 USBDEVNAME(sc->sc_bus.bdev), sc->sc_overrun_cnt); 1569 sc->sc_overrun_cnt = 0; 1570 } 1571 /* XXX do what */ 1572 eintrs &= ~OHCI_SO; 1573 } 1574 if (eintrs & OHCI_WDH) { 1575 /* 1576 * We block the interrupt below, and reenable it later from 1577 * ohci_softintr(). 1578 */ 1579 usb_schedsoftintr(&sc->sc_bus); 1580 } 1581 if (eintrs & OHCI_RD) { 1582 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 1583 /* XXX process resume detect */ 1584 } 1585 if (eintrs & OHCI_UE) { 1586 printf("%s: unrecoverable error, controller halted\n", 1587 USBDEVNAME(sc->sc_bus.bdev)); 1588 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1589 /* XXX what else */ 1590 } 1591 if (eintrs & OHCI_RHSC) { 1592 /* 1593 * We block the interrupt below, and reenable it later from 1594 * a timeout. 1595 */ 1596 ohci_rhsc(sc, sc->sc_intrxfer); 1597 /* Do not allow RHSC interrupts > 1 per second */ 1598 usb_callout(sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1599 } 1600 1601 sc->sc_bus.intr_context--; 1602 1603 if (eintrs != 0) { 1604 /* Block unprocessed interrupts. */ 1605 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1606 sc->sc_eintrs &= ~eintrs; 1607 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1608 USBDEVNAME(sc->sc_bus.bdev), eintrs)); 1609 } 1610 1611 return (1); 1612 } 1613 1614 void 1615 ohci_rhsc_enable(void *v_sc) 1616 { 1617 ohci_softc_t *sc = v_sc; 1618 int s; 1619 1620 s = splhardusb(); 1621 sc->sc_eintrs |= OHCI_RHSC; 1622 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1623 splx(s); 1624 } 1625 1626 #ifdef USB_DEBUG 1627 const char *ohci_cc_strs[] = { 1628 "NO_ERROR", 1629 "CRC", 1630 "BIT_STUFFING", 1631 "DATA_TOGGLE_MISMATCH", 1632 "STALL", 1633 "DEVICE_NOT_RESPONDING", 1634 "PID_CHECK_FAILURE", 1635 "UNEXPECTED_PID", 1636 "DATA_OVERRUN", 1637 "DATA_UNDERRUN", 1638 "BUFFER_OVERRUN", 1639 "BUFFER_UNDERRUN", 1640 "reserved", 1641 "reserved", 1642 "NOT_ACCESSED", 1643 "NOT_ACCESSED" 1644 }; 1645 #endif 1646 1647 void 1648 ohci_softintr(void *v) 1649 { 1650 ohci_softc_t *sc = v; 1651 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1652 ohci_soft_td_t *std, *sdone, *stdnext, *p, *n; 1653 usbd_xfer_handle xfer; 1654 struct ohci_pipe *opipe; 1655 int len, cc, s; 1656 int i, j, iframes; 1657 ohci_physaddr_t done; 1658 ohci_physaddr_t dmaadr; 1659 1660 DPRINTFN(10,("ohci_softintr: enter\n")); 1661 1662 sc->sc_bus.intr_context++; 1663 1664 s = splhardusb(); 1665 USB_MEM_SYNC(&sc->sc_dmatag, &sc->sc_hccadma, 1666 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1667 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1668 sc->sc_hcca->hcca_done_head = 0; 1669 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1670 sc->sc_eintrs |= OHCI_WDH; 1671 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1672 splx(s); 1673 1674 /* Reverse the done list. */ 1675 for (sdone = NULL, sidone = NULL; done != 0; ) { 1676 std = ohci_find_td(sc, done); 1677 if (std != NULL) { 1678 OHCI_STD_SYNC(sc, std, 1679 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1680 std->dnext = sdone; 1681 done = O32TOH(std->td.td_nexttd); 1682 sdone = std; 1683 DPRINTFN(10,("add TD %p\n", std)); 1684 continue; 1685 } 1686 sitd = ohci_find_itd(sc, done); 1687 if (sitd != NULL) { 1688 OHCI_SITD_SYNC(sc, sitd, 1689 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1690 sitd->dnext = sidone; 1691 done = O32TOH(sitd->itd.itd_nextitd); 1692 sidone = sitd; 1693 DPRINTFN(5,("add ITD %p\n", sitd)); 1694 continue; 1695 } 1696 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1697 } 1698 1699 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1700 1701 #ifdef USB_DEBUG 1702 if (ohcidebug > 10) { 1703 DPRINTF(("ohci_process_done: TD done:\n")); 1704 ohci_dump_tds(sc, sdone); 1705 } 1706 #endif 1707 1708 for (std = sdone; std; std = stdnext) { 1709 xfer = std->xfer; 1710 stdnext = std->dnext; 1711 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1712 std, xfer, (xfer ? xfer->hcpriv : NULL))); 1713 if (xfer == NULL) { 1714 /* 1715 * xfer == NULL: There seems to be no xfer associated 1716 * with this TD. It is tailp that happened to end up on 1717 * the done queue. 1718 */ 1719 continue; 1720 } 1721 if (xfer->status == USBD_CANCELLED || 1722 xfer->status == USBD_TIMEOUT) { 1723 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1724 xfer)); 1725 /* Handled by abort routine. */ 1726 continue; 1727 } 1728 1729 len = std->len; 1730 if (std->td.td_cbp != 0) 1731 len -= O32TOH(std->td.td_be) - 1732 O32TOH(std->td.td_cbp) + 1; 1733 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1734 std->flags)); 1735 if (std->flags & OHCI_ADD_LEN) 1736 xfer->actlen += len; 1737 1738 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1739 if (cc != OHCI_CC_NO_ERROR) { 1740 /* 1741 * Endpoint is halted. First unlink all the TDs 1742 * belonging to the failed transfer, and then restart 1743 * the endpoint. 1744 */ 1745 opipe = (struct ohci_pipe *)xfer->pipe; 1746 1747 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1748 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1749 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1750 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 1751 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 1752 &OXFER(xfer)->abort_task); 1753 1754 /* Remove all this xfer's TDs from the done queue. */ 1755 for (p = std; p->dnext != NULL; p = p->dnext) { 1756 if (p->dnext->xfer != xfer) 1757 continue; 1758 p->dnext = p->dnext->dnext; 1759 } 1760 /* The next TD may have been removed. */ 1761 stdnext = std->dnext; 1762 1763 /* Remove all TDs belonging to this xfer. */ 1764 for (p = xfer->hcpriv; p->xfer == xfer; p = n) { 1765 n = p->nexttd; 1766 ohci_free_std(sc, p); 1767 } 1768 1769 /* clear halt */ 1770 OHCI_SED_SYNC(sc, opipe->sed, 1771 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1772 dmaadr = OHCI_STD_DMAADDR(p); 1773 opipe->sed->ed.ed_headp = HTOO32(dmaadr); 1774 OHCI_SED_SYNC(sc, opipe->sed, 1775 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1776 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1777 1778 if (cc == OHCI_CC_STALL) 1779 xfer->status = USBD_STALLED; 1780 else 1781 xfer->status = USBD_IOERROR; 1782 s = splusb(); 1783 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 1784 &OXFER(xfer)->dmabuf); 1785 splx(s); 1786 continue; 1787 } 1788 /* 1789 * Skip intermediate TDs. They remain linked from 1790 * xfer->hcpriv and we free them when the transfer completes. 1791 */ 1792 if ((std->flags & OHCI_CALL_DONE) == 0) 1793 continue; 1794 1795 /* Normal transfer completion */ 1796 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 1797 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 1798 &OXFER(xfer)->abort_task); 1799 for (p = xfer->hcpriv; p->xfer == xfer; p = n) { 1800 n = p->nexttd; 1801 ohci_free_std(sc, p); 1802 } 1803 xfer->status = USBD_NORMAL_COMPLETION; 1804 xfer->hcpriv = NULL; 1805 s = splusb(); 1806 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 1807 &OXFER(xfer)->dmabuf); 1808 splx(s); 1809 } 1810 1811 #ifdef USB_DEBUG 1812 if (ohcidebug > 10) { 1813 DPRINTF(("ohci_softintr: ITD done:\n")); 1814 ohci_dump_itds(sc, sidone); 1815 } 1816 #endif 1817 1818 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1819 xfer = sitd->xfer; 1820 sitdnext = sitd->dnext; 1821 sitd->flags |= OHCI_ITD_INTFIN; 1822 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1823 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1824 if (xfer == NULL) 1825 continue; 1826 if (xfer->status == USBD_CANCELLED || 1827 xfer->status == USBD_TIMEOUT) { 1828 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1829 xfer)); 1830 /* Handled by abort routine. */ 1831 continue; 1832 } 1833 if (xfer->pipe) 1834 if (xfer->pipe->aborting) 1835 continue; /*Ignore.*/ 1836 #ifdef DIAGNOSTIC 1837 if (sitd->isdone) 1838 printf("ohci_softintr: sitd=%p is done\n", sitd); 1839 sitd->isdone = 1; 1840 #endif 1841 opipe = (struct ohci_pipe *)xfer->pipe; 1842 if (opipe->aborting) 1843 continue; 1844 1845 if (sitd->flags & OHCI_CALL_DONE) { 1846 ohci_soft_itd_t *next; 1847 1848 opipe->u.iso.inuse -= xfer->nframes; 1849 xfer->status = USBD_NORMAL_COMPLETION; 1850 for (i = 0, sitd = xfer->hcpriv;;sitd = next) { 1851 next = sitd->nextitd; 1852 if (OHCI_ITD_GET_CC(sitd->itd.itd_flags) != OHCI_CC_NO_ERROR) 1853 xfer->status = USBD_IOERROR; 1854 1855 if (xfer->status == USBD_NORMAL_COMPLETION) { 1856 iframes = OHCI_ITD_GET_FC(sitd->itd.itd_flags); 1857 for (j = 0; j < iframes; i++, j++) { 1858 len = O16TOH(sitd->itd.itd_offset[j]); 1859 len = 1860 ((OHCI_ITD_PSW_GET_CC(len) & 1861 OHCI_CC_NOT_ACCESSED_MASK) 1862 == OHCI_CC_NOT_ACCESSED) ? 1863 0 : 1864 OHCI_ITD_PSW_LENGTH(len); 1865 xfer->frlengths[i] = len; 1866 } 1867 } 1868 if (sitd->flags & OHCI_CALL_DONE) 1869 break; 1870 } 1871 for (sitd = xfer->hcpriv; sitd->xfer == xfer; 1872 sitd = next) { 1873 next = sitd->nextitd; 1874 ohci_free_sitd(sc, sitd); 1875 } 1876 1877 s = splusb(); 1878 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 1879 &OXFER(xfer)->dmabuf); 1880 splx(s); 1881 } 1882 } 1883 1884 #ifdef USB_USE_SOFTINTR 1885 if (sc->sc_softwake) { 1886 sc->sc_softwake = 0; 1887 wakeup(&sc->sc_softwake); 1888 } 1889 #endif /* USB_USE_SOFTINTR */ 1890 1891 sc->sc_bus.intr_context--; 1892 DPRINTFN(10,("ohci_softintr: done:\n")); 1893 } 1894 1895 void 1896 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1897 { 1898 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1899 1900 #ifdef DIAGNOSTIC 1901 if (!(xfer->rqflags & URQ_REQUEST)) { 1902 panic("ohci_device_ctrl_done: not a request"); 1903 } 1904 #endif 1905 } 1906 1907 void 1908 ohci_device_intr_done(usbd_xfer_handle xfer) 1909 { 1910 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1911 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1912 usbd_status err; 1913 1914 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1915 xfer, xfer->actlen)); 1916 1917 if (xfer->pipe->repeat) { 1918 err = ohci_device_intr_insert(sc, xfer); 1919 if (err) { 1920 xfer->status = err; 1921 return; 1922 } 1923 } 1924 } 1925 1926 void 1927 ohci_device_bulk_done(usbd_xfer_handle xfer) 1928 { 1929 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1930 xfer, xfer->actlen)); 1931 } 1932 1933 void 1934 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1935 { 1936 usbd_pipe_handle pipe; 1937 u_char *p; 1938 int i, m; 1939 int hstatus; 1940 1941 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1942 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1943 sc, xfer, hstatus)); 1944 1945 if (xfer == NULL) { 1946 /* Just ignore the change. */ 1947 return; 1948 } 1949 1950 pipe = xfer->pipe; 1951 1952 p = xfer->hcbuffer; 1953 m = min(sc->sc_noport, xfer->length * 8 - 1); 1954 memset(p, 0, xfer->length); 1955 for (i = 1; i <= m; i++) { 1956 /* Pick out CHANGE bits from the status reg. */ 1957 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1958 p[i/8] |= 1 << (i%8); 1959 } 1960 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1961 xfer->actlen = xfer->length; 1962 xfer->status = USBD_NORMAL_COMPLETION; 1963 1964 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 1965 &OXFER(xfer)->dmabuf); 1966 } 1967 1968 void 1969 ohci_root_intr_done(usbd_xfer_handle xfer) 1970 { 1971 } 1972 1973 void 1974 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1975 { 1976 } 1977 1978 /* 1979 * Wait here until controller claims to have an interrupt. 1980 * Then call ohci_intr and return. Use timeout to avoid waiting 1981 * too long. 1982 */ 1983 void 1984 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1985 { 1986 int timo; 1987 u_int32_t intrs; 1988 1989 xfer->status = USBD_IN_PROGRESS; 1990 for (timo = xfer->timeout; timo >= 0; timo--) { 1991 usb_delay_ms(&sc->sc_bus, 1); 1992 if (sc->sc_dying) 1993 break; 1994 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1995 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1996 #ifdef USB_DEBUG 1997 if (ohcidebug > 15) 1998 ohci_dumpregs(sc); 1999 #endif 2000 if (intrs) { 2001 ohci_intr1(sc); 2002 if (xfer->status != USBD_IN_PROGRESS) 2003 return; 2004 } 2005 } 2006 2007 /* Timeout */ 2008 DPRINTF(("ohci_waitintr: timeout\n")); 2009 xfer->status = USBD_TIMEOUT; 2010 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 2011 &OXFER(xfer)->dmabuf); 2012 /* XXX should free TD */ 2013 } 2014 2015 void 2016 ohci_poll(struct usbd_bus *bus) 2017 { 2018 ohci_softc_t *sc = (ohci_softc_t *)bus; 2019 #ifdef USB_DEBUG 2020 static int last; 2021 int new; 2022 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 2023 if (new != last) { 2024 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 2025 last = new; 2026 } 2027 #endif 2028 2029 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 2030 ohci_intr1(sc); 2031 } 2032 2033 usbd_status 2034 ohci_device_request(usbd_xfer_handle xfer) 2035 { 2036 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2037 usb_device_request_t *req = &xfer->request; 2038 usbd_device_handle dev = opipe->pipe.device; 2039 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2040 ohci_soft_td_t *setup, *stat, *next, *tail; 2041 ohci_soft_ed_t *sed; 2042 int isread; 2043 int len; 2044 usbd_status err; 2045 int s; 2046 ohci_physaddr_t dmaadr; 2047 2048 isread = req->bmRequestType & UT_READ; 2049 len = UGETW(req->wLength); 2050 2051 DPRINTFN(3,("ohci_device_request: type=0x%02x, request=0x%02x, " 2052 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2053 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2054 UGETW(req->wIndex), len, dev->address, 2055 opipe->pipe.endpoint->edesc->bEndpointAddress)); 2056 2057 setup = opipe->tail.td; 2058 stat = ohci_alloc_std(sc); 2059 if (stat == NULL) { 2060 err = USBD_NOMEM; 2061 goto bad1; 2062 } 2063 tail = ohci_alloc_std(sc); 2064 if (tail == NULL) { 2065 err = USBD_NOMEM; 2066 goto bad2; 2067 } 2068 tail->xfer = NULL; 2069 2070 sed = opipe->sed; 2071 opipe->u.ctl.length = len; 2072 next = stat; 2073 2074 /* Set up data transaction */ 2075 if (len != 0) { 2076 ohci_soft_td_t *std = stat; 2077 2078 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2079 std, &stat); 2080 if (err) 2081 goto bad3; 2082 OHCI_STD_SYNC(sc, stat, 2083 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2084 stat = stat->nexttd; /* point at free TD */ 2085 /* Start toggle at 1 and then use the carried toggle. */ 2086 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2087 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2088 } 2089 2090 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 2091 2092 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2093 OHCI_TD_TOGGLE_0 | OHCI_TD_SET_DI(6)); 2094 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 2095 setup->nexttd = next; 2096 dmaadr = OHCI_STD_DMAADDR(next); 2097 setup->td.td_nexttd = HTOO32(dmaadr); 2098 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 2099 setup->len = 0; 2100 setup->xfer = xfer; 2101 setup->flags = 0; 2102 xfer->hcpriv = setup; 2103 OHCI_STD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2104 2105 stat->td.td_flags = HTOO32( 2106 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2107 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2108 stat->td.td_cbp = 0; 2109 stat->nexttd = tail; 2110 dmaadr = OHCI_STD_DMAADDR(tail); 2111 stat->td.td_nexttd = HTOO32(dmaadr); 2112 stat->td.td_be = 0; 2113 stat->flags = OHCI_CALL_DONE; 2114 stat->len = 0; 2115 stat->xfer = xfer; 2116 OHCI_STD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2117 2118 #ifdef USB_DEBUG 2119 if (ohcidebug > 5) { 2120 DPRINTF(("ohci_device_request:\n")); 2121 ohci_dump_ed(sc, sed); 2122 ohci_dump_tds(sc, setup); 2123 } 2124 #endif 2125 2126 USB_MEM_SYNC(&sc->sc_dmatag, &sc->sc_hccadma, 2127 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2128 2129 /* Insert ED in schedule */ 2130 s = splusb(); 2131 dmaadr = OHCI_STD_DMAADDR(tail); 2132 sed->ed.ed_tailp = HTOO32(dmaadr); 2133 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2134 opipe->tail.td = tail; 2135 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2136 if (xfer->timeout && !sc->sc_bus.use_polling) { 2137 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2138 ohci_timeout, xfer); 2139 } 2140 splx(s); 2141 2142 #ifdef USB_DEBUG 2143 if (ohcidebug > 20) { 2144 delay(10000); 2145 DPRINTF(("ohci_device_request: status=%x\n", 2146 OREAD4(sc, OHCI_COMMAND_STATUS))); 2147 ohci_dumpregs(sc); 2148 printf("ctrl head:\n"); 2149 ohci_dump_ed(sc, sc->sc_ctrl_head); 2150 printf("sed:\n"); 2151 ohci_dump_ed(sc, sed); 2152 ohci_dump_tds(sc, setup); 2153 } 2154 #endif 2155 2156 return (USBD_NORMAL_COMPLETION); 2157 2158 bad3: 2159 ohci_free_std(sc, tail); 2160 bad2: 2161 ohci_free_std(sc, stat); 2162 bad1: 2163 return (err); 2164 } 2165 2166 /* 2167 * Add an ED to the schedule. Called at splusb(). 2168 */ 2169 void 2170 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2171 { 2172 ohci_physaddr_t dmaadr; 2173 2174 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 2175 2176 SPLUSBCHECK; 2177 sed->next = head->next; 2178 sed->ed.ed_nexted = head->ed.ed_nexted; 2179 head->next = sed; 2180 dmaadr = OHCI_SED_DMAADDR(sed); 2181 head->ed.ed_nexted = HTOO32(dmaadr); 2182 } 2183 2184 /* 2185 * Remove an ED from the schedule. Called at splusb(). 2186 */ 2187 void 2188 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2189 { 2190 ohci_soft_ed_t *p; 2191 2192 SPLUSBCHECK; 2193 2194 /* XXX */ 2195 for (p = head; p != NULL && p->next != sed; p = p->next) 2196 ; 2197 if (p == NULL) 2198 panic("ohci_rem_ed: ED not found"); 2199 p->next = sed->next; 2200 p->ed.ed_nexted = sed->ed.ed_nexted; 2201 } 2202 2203 /* 2204 * When a transfer is completed the TD is added to the done queue by 2205 * the host controller. This queue is the processed by software. 2206 * Unfortunately the queue contains the physical address of the TD 2207 * and we have no simple way to translate this back to a kernel address. 2208 * To make the translation possible (and fast) we use the chunk of 2209 * TDs used for allocation. 2210 */ 2211 2212 ohci_soft_td_t * 2213 ohci_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 2214 { 2215 struct ohci_mem_desc *om; 2216 ohci_soft_td_t *std; 2217 size_t off; 2218 2219 /* if these are present they should be masked out at an earlier 2220 * stage. 2221 */ 2222 USB_KASSERT2((a&~OHCI_HEADMASK) == 0, ("%s: 0x%b has lower bits set\n", 2223 USBDEVNAME(sc->sc_bus.bdev), 2224 (int) a, "\20\1HALT\2TOGGLE")); 2225 2226 SIMPLEQ_FOREACH(om, &sc->sc_std_chunks, om_next) { 2227 if (a >= om->om_topdma && 2228 a < om->om_topdma + OHCI_STD_SIZE * OHCI_STD_CHUNK) { 2229 off = a - om->om_topdma; 2230 if (off % OHCI_STD_SIZE) { 2231 #ifdef DIAGNOSTIC 2232 printf("ohci_find_td: 0x%x bad address\n", 2233 (unsigned)a); 2234 #endif 2235 break; 2236 } 2237 std = (ohci_soft_td_t *)(om->om_top + off); 2238 if (std->flags & OHCI_TD_FREE) { 2239 #ifdef DIAGNOSTIC 2240 printf("ohci_find_td: 0x%x: free td\n", 2241 (unsigned)OHCI_STD_DMAADDR(std)); 2242 #endif 2243 break; 2244 } 2245 return std; 2246 } 2247 } 2248 2249 DPRINTF(("%s: ohci_find_td: addr 0x%08lx not found\n", 2250 USBDEVNAME(sc->sc_bus.bdev), (u_long) a)); 2251 return (NULL); 2252 } 2253 2254 ohci_soft_itd_t * 2255 ohci_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 2256 { 2257 struct ohci_mem_desc *om; 2258 ohci_soft_itd_t *sitd; 2259 size_t off; 2260 2261 SIMPLEQ_FOREACH(om, &sc->sc_sitd_chunks, om_next) { 2262 if (a >= om->om_topdma && 2263 a < om->om_topdma + OHCI_SITD_SIZE * OHCI_SITD_CHUNK) { 2264 off = a - om->om_topdma; 2265 if (off % OHCI_SITD_SIZE) { 2266 #ifdef DIAGNOSTIC 2267 printf("ohci_find_itd: 0x%x bad address\n", 2268 (unsigned)a); 2269 #endif 2270 break; 2271 } 2272 sitd = (ohci_soft_itd_t *)(om->om_top + off); 2273 if (sitd->flags & OHCI_ITD_FREE) { 2274 #ifdef DIAGNOSTIC 2275 printf("ohci_find_itd: 0x%x: free itd\n", 2276 (unsigned)OHCI_SITD_DMAADDR(sitd)); 2277 #endif 2278 break; 2279 } 2280 return sitd; 2281 } 2282 } 2283 return (NULL); 2284 } 2285 2286 void 2287 ohci_timeout(void *addr) 2288 { 2289 struct ohci_xfer *oxfer = addr; 2290 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2291 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2292 2293 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2294 2295 if (sc->sc_dying) { 2296 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2297 return; 2298 } 2299 2300 /* Execute the abort in a process context. */ 2301 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2302 USB_TASKQ_HC); 2303 } 2304 2305 void 2306 ohci_timeout_task(void *addr) 2307 { 2308 usbd_xfer_handle xfer = addr; 2309 int s; 2310 2311 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2312 2313 s = splusb(); 2314 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2315 splx(s); 2316 } 2317 2318 #ifdef USB_DEBUG 2319 void 2320 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2321 { 2322 for (; std; std = std->nexttd) 2323 ohci_dump_td(sc, std); 2324 } 2325 2326 void 2327 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2328 { 2329 char sbuf[128]; 2330 2331 bitmask_snprintf((u_int32_t)O32TOH(std->td.td_flags), 2332 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2333 sbuf, sizeof(sbuf)); 2334 2335 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2336 "nexttd=0x%08lx be=0x%08lx\n", 2337 std, (u_long)OHCI_STD_DMAADDR(std), sbuf, 2338 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2339 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2340 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2341 (u_long)O32TOH(std->td.td_cbp), 2342 (u_long)O32TOH(std->td.td_nexttd), 2343 (u_long)O32TOH(std->td.td_be)); 2344 } 2345 2346 void 2347 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2348 { 2349 int i; 2350 2351 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2352 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2353 sitd, (u_long)OHCI_SITD_DMAADDR(sitd), 2354 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2355 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2356 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2357 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2358 (u_long)O32TOH(sitd->itd.itd_bp0), 2359 (u_long)O32TOH(sitd->itd.itd_nextitd), 2360 (u_long)O32TOH(sitd->itd.itd_be)); 2361 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2362 printf("offs[%d]=0x%04x ", i, 2363 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2364 printf("\n"); 2365 } 2366 2367 void 2368 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2369 { 2370 for (; sitd; sitd = sitd->nextitd) 2371 ohci_dump_itd(sc, sitd); 2372 } 2373 2374 void 2375 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2376 { 2377 char sbuf[128], sbuf2[128]; 2378 2379 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_flags), 2380 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2381 sbuf, sizeof(sbuf)); 2382 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_headp), 2383 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 2384 2385 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2386 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2387 sed, (u_long)OHCI_SED_DMAADDR(sed), 2388 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2389 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2390 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2391 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2392 (u_long)O32TOH(sed->ed.ed_headp), 2393 (u_long)O32TOH(sed->ed.ed_nexted)); 2394 } 2395 #endif 2396 2397 usbd_status 2398 ohci_open(usbd_pipe_handle pipe) 2399 { 2400 usbd_device_handle dev = pipe->device; 2401 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2402 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2403 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2404 u_int8_t addr = dev->address; 2405 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2406 ohci_soft_ed_t *sed; 2407 ohci_soft_td_t *std; 2408 ohci_soft_itd_t *sitd; 2409 ohci_physaddr_t tdphys; 2410 u_int32_t fmt; 2411 usbd_status err; 2412 int s; 2413 int ival; 2414 2415 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2416 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2417 2418 if (sc->sc_dying) 2419 return (USBD_IOERROR); 2420 2421 std = NULL; 2422 sed = NULL; 2423 2424 if (addr == sc->sc_addr) { 2425 switch (ed->bEndpointAddress) { 2426 case USB_CONTROL_ENDPOINT: 2427 pipe->methods = &ohci_root_ctrl_methods; 2428 break; 2429 case UE_DIR_IN | OHCI_INTR_ENDPT: 2430 pipe->methods = &ohci_root_intr_methods; 2431 break; 2432 default: 2433 return (USBD_INVAL); 2434 } 2435 } else { 2436 sed = ohci_alloc_sed(sc); 2437 if (sed == NULL) 2438 goto bad0; 2439 opipe->sed = sed; 2440 if (xfertype == UE_ISOCHRONOUS) { 2441 sitd = ohci_alloc_sitd_norsv(sc); 2442 if (sitd == NULL) 2443 goto bad1; 2444 opipe->tail.itd = sitd; 2445 opipe->aborting = 0; 2446 tdphys = OHCI_SITD_DMAADDR(sitd); 2447 fmt = OHCI_ED_FORMAT_ISO; 2448 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2449 fmt |= OHCI_ED_DIR_IN; 2450 else 2451 fmt |= OHCI_ED_DIR_OUT; 2452 } else { 2453 std = ohci_alloc_std_norsv(sc); 2454 if (std == NULL) 2455 goto bad1; 2456 opipe->tail.td = std; 2457 tdphys = OHCI_STD_DMAADDR(std); 2458 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2459 } 2460 sed->ed.ed_flags = HTOO32( 2461 OHCI_ED_SET_FA(addr) | 2462 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2463 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2464 fmt | 2465 OHCI_ED_SET_MAXP(UE_MAXPKTSZ(ed))); 2466 sed->ed.ed_headp = HTOO32(tdphys | 2467 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2468 sed->ed.ed_tailp = HTOO32(tdphys); 2469 2470 switch (xfertype) { 2471 case UE_CONTROL: 2472 pipe->methods = &ohci_device_ctrl_methods; 2473 err = usb_allocmem(&sc->sc_dmatag, 2474 sizeof(usb_device_request_t), 2475 0, &opipe->u.ctl.reqdma); 2476 if (err) 2477 goto bad; 2478 s = splusb(); 2479 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2480 splx(s); 2481 break; 2482 case UE_INTERRUPT: 2483 pipe->methods = &ohci_device_intr_methods; 2484 ival = pipe->interval; 2485 if (ival == USBD_DEFAULT_INTERVAL) 2486 ival = ed->bInterval; 2487 return (ohci_device_setintr(sc, opipe, ival)); 2488 case UE_ISOCHRONOUS: 2489 pipe->methods = &ohci_device_isoc_methods; 2490 return (ohci_setup_isoc(pipe)); 2491 case UE_BULK: 2492 pipe->methods = &ohci_device_bulk_methods; 2493 s = splusb(); 2494 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2495 splx(s); 2496 break; 2497 } 2498 } 2499 return (USBD_NORMAL_COMPLETION); 2500 2501 bad: 2502 if (std != NULL) 2503 ohci_free_std(sc, std); 2504 bad1: 2505 if (sed != NULL) 2506 ohci_free_sed(sc, sed); 2507 bad0: 2508 return (USBD_NOMEM); 2509 2510 } 2511 2512 /* 2513 * Close a reqular pipe. 2514 * Assumes that there are no pending transactions. 2515 */ 2516 void 2517 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2518 { 2519 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2520 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2521 ohci_soft_ed_t *sed = opipe->sed; 2522 int s; 2523 2524 s = splusb(); 2525 #ifdef DIAGNOSTIC 2526 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2527 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2528 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2529 ohci_soft_td_t *std; 2530 std = ohci_find_td(sc, O32TOH(sed->ed.ed_headp)); 2531 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2532 "tl=0x%x pipe=%p, std=%p\n", sed, 2533 (int)O32TOH(sed->ed.ed_headp), 2534 (int)O32TOH(sed->ed.ed_tailp), 2535 pipe, std); 2536 #ifdef USB_DEBUG 2537 usbd_dump_pipe(&opipe->pipe); 2538 #endif 2539 #ifdef USB_DEBUG 2540 ohci_dump_ed(sc, sed); 2541 if (std) 2542 ohci_dump_td(sc, std); 2543 #endif 2544 usb_delay_ms(&sc->sc_bus, 2); 2545 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2546 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2547 printf("ohci_close_pipe: pipe still not empty\n"); 2548 } 2549 #endif 2550 ohci_rem_ed(sed, head); 2551 /* Make sure the host controller is not touching this ED */ 2552 usb_delay_ms(&sc->sc_bus, 1); 2553 splx(s); 2554 pipe->endpoint->savedtoggle = 2555 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2556 ohci_free_sed(sc, opipe->sed); 2557 } 2558 2559 /* 2560 * Abort a device request. 2561 * If this routine is called at splusb() it guarantees that the request 2562 * will be removed from the hardware scheduling and that the callback 2563 * for it will be called with USBD_CANCELLED status. 2564 * It's impossible to guarantee that the requested transfer will not 2565 * have happened since the hardware runs concurrently. 2566 * If the transaction has already happened we rely on the ordinary 2567 * interrupt processing to process it. 2568 */ 2569 void 2570 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2571 { 2572 struct ohci_xfer *oxfer = OXFER(xfer); 2573 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2574 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2575 ohci_soft_ed_t *sed = opipe->sed; 2576 ohci_soft_td_t *p, *n; 2577 ohci_physaddr_t headp; 2578 ohci_physaddr_t dmaadr; 2579 int s, hit; 2580 int wake; 2581 2582 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2583 2584 if (sc->sc_dying) { 2585 /* If we're dying, just do the software part. */ 2586 s = splusb(); 2587 xfer->status = status; /* make software ignore it */ 2588 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2589 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2590 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 2591 &oxfer->dmabuf); 2592 splx(s); 2593 return; 2594 } 2595 2596 if (xfer->device->bus->intr_context || !curproc) 2597 panic("ohci_abort_xfer: not in process context"); 2598 2599 /* 2600 * If an abort is already in progress then just wait for it to 2601 * complete and return. 2602 */ 2603 if (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) { 2604 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2605 /* No need to wait if we're aborting from a timeout. */ 2606 if (status == USBD_TIMEOUT) 2607 return; 2608 /* Override the status which might be USBD_TIMEOUT. */ 2609 xfer->status = status; 2610 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2611 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTWAIT; 2612 while (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) 2613 tsleep(&oxfer->ohci_xfer_flags, PZERO, "ohciaw", 0); 2614 return; 2615 } 2616 2617 /* 2618 * Step 1: Make interrupt routine and hardware ignore xfer. 2619 */ 2620 s = splusb(); 2621 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTING; 2622 xfer->status = status; /* make software ignore it */ 2623 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2624 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2625 splx(s); 2626 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2627 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2628 2629 /* 2630 * Step 2: Wait until we know hardware has finished any possible 2631 * use of the xfer. Also make sure the soft interrupt routine 2632 * has run. 2633 */ 2634 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2635 s = splusb(); 2636 #ifdef USB_USE_SOFTINTR 2637 sc->sc_softwake = 1; 2638 #endif /* USB_USE_SOFTINTR */ 2639 usb_schedsoftintr(&sc->sc_bus); 2640 #ifdef USB_USE_SOFTINTR 2641 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2642 #endif /* USB_USE_SOFTINTR */ 2643 splx(s); 2644 2645 /* 2646 * Step 3: Remove any vestiges of the xfer from the hardware. 2647 * The complication here is that the hardware may have executed 2648 * beyond the xfer we're trying to abort. So as we're scanning 2649 * the TDs of this xfer we check if the hardware points to 2650 * any of them. 2651 */ 2652 s = splusb(); /* XXX why? */ 2653 p = xfer->hcpriv; 2654 #ifdef DIAGNOSTIC 2655 if (p == NULL) { 2656 oxfer->ohci_xfer_flags &= ~OHCI_XFER_ABORTING; /* XXX */ 2657 splx(s); 2658 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2659 return; 2660 } 2661 #endif 2662 #ifdef USB_DEBUG 2663 if (ohcidebug > 1) { 2664 DPRINTF(("ohci_abort_xfer: sed=\n")); 2665 ohci_dump_ed(sc, sed); 2666 ohci_dump_tds(sc, p); 2667 } 2668 #endif 2669 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2670 hit = 0; 2671 for (; p->xfer == xfer; p = n) { 2672 hit |= headp == OHCI_STD_DMAADDR(p); 2673 n = p->nexttd; 2674 ohci_free_std(sc, p); 2675 } 2676 /* Zap headp register if hardware pointed inside the xfer. */ 2677 if (hit) { 2678 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2679 (int)OHCI_STD_DMAADDR(p), (int)O32TOH(sed->ed.ed_tailp))); 2680 dmaadr = OHCI_STD_DMAADDR(p); 2681 sed->ed.ed_headp = HTOO32(dmaadr); /* unlink TDs */ 2682 } else { 2683 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2684 } 2685 2686 /* 2687 * Step 4: Turn on hardware again. 2688 */ 2689 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2690 2691 /* 2692 * Step 5: Execute callback. 2693 */ 2694 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2695 wake = oxfer->ohci_xfer_flags & OHCI_XFER_ABORTWAIT; 2696 oxfer->ohci_xfer_flags &= ~(OHCI_XFER_ABORTING | OHCI_XFER_ABORTWAIT); 2697 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &oxfer->dmabuf); 2698 if (wake) 2699 wakeup(&oxfer->ohci_xfer_flags); 2700 2701 splx(s); 2702 } 2703 2704 /* 2705 * Data structures and routines to emulate the root hub. 2706 */ 2707 Static usb_device_descriptor_t ohci_devd = { 2708 USB_DEVICE_DESCRIPTOR_SIZE, 2709 UDESC_DEVICE, /* type */ 2710 {0x00, 0x01}, /* USB version */ 2711 UDCLASS_HUB, /* class */ 2712 UDSUBCLASS_HUB, /* subclass */ 2713 UDPROTO_FSHUB, /* protocol */ 2714 64, /* max packet */ 2715 {0},{0},{0x00,0x01}, /* device id */ 2716 1,2,0, /* string indicies */ 2717 1 /* # of configurations */ 2718 }; 2719 2720 Static usb_config_descriptor_t ohci_confd = { 2721 USB_CONFIG_DESCRIPTOR_SIZE, 2722 UDESC_CONFIG, 2723 {USB_CONFIG_DESCRIPTOR_SIZE + 2724 USB_INTERFACE_DESCRIPTOR_SIZE + 2725 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2726 1, 2727 1, 2728 0, 2729 UC_ATTR_MBO | UC_SELF_POWERED, 2730 0 /* max power */ 2731 }; 2732 2733 Static usb_interface_descriptor_t ohci_ifcd = { 2734 USB_INTERFACE_DESCRIPTOR_SIZE, 2735 UDESC_INTERFACE, 2736 0, 2737 0, 2738 1, 2739 UICLASS_HUB, 2740 UISUBCLASS_HUB, 2741 UIPROTO_FSHUB, 2742 0 2743 }; 2744 2745 Static usb_endpoint_descriptor_t ohci_endpd = { 2746 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2747 .bDescriptorType = UDESC_ENDPOINT, 2748 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2749 .bmAttributes = UE_INTERRUPT, 2750 .wMaxPacketSize = {8, 0}, /* max packet */ 2751 .bInterval = 255, 2752 }; 2753 2754 Static usb_hub_descriptor_t ohci_hubd = { 2755 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2756 .bDescriptorType = UDESC_HUB, 2757 }; 2758 2759 Static int 2760 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 2761 { 2762 int i; 2763 2764 if (l == 0) 2765 return (0); 2766 p->bLength = 2 * strlen(s) + 2; 2767 if (l == 1) 2768 return (1); 2769 p->bDescriptorType = UDESC_STRING; 2770 l -= 2; 2771 for (i = 0; s[i] && l > 1; i++, l -= 2) 2772 USETW2(p->bString[i], 0, s[i]); 2773 return (2*i+2); 2774 } 2775 2776 /* 2777 * Simulate a hardware hub by handling all the necessary requests. 2778 */ 2779 Static usbd_status 2780 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2781 { 2782 usbd_status err; 2783 2784 /* Insert last in queue. */ 2785 #if 0 /* root ctrl doesn't do DMA */ 2786 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 2787 &OXFER(xfer)->dmabuf); 2788 #else 2789 err = usb_insert_transfer(xfer); 2790 #endif 2791 if (err) 2792 return (err); 2793 2794 /* Pipe isn't running, start first */ 2795 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2796 } 2797 2798 Static usbd_status 2799 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2800 { 2801 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 2802 usb_device_request_t *req; 2803 void *buf = NULL; 2804 int port, i; 2805 int s, len, value, index, l, totlen = 0; 2806 usb_port_status_t ps; 2807 usb_hub_descriptor_t hubd; 2808 usbd_status err; 2809 u_int32_t v; 2810 2811 if (sc->sc_dying) 2812 return (USBD_IOERROR); 2813 2814 #ifdef DIAGNOSTIC 2815 if (!(xfer->rqflags & URQ_REQUEST)) 2816 /* XXX panic */ 2817 return (USBD_INVAL); 2818 #endif 2819 req = &xfer->request; 2820 2821 DPRINTFN(4,("ohci_root_ctrl_start: type=0x%02x request=%02x\n", 2822 req->bmRequestType, req->bRequest)); 2823 2824 len = UGETW(req->wLength); 2825 value = UGETW(req->wValue); 2826 index = UGETW(req->wIndex); 2827 2828 if (len != 0) 2829 buf = xfer->hcbuffer; 2830 2831 #define C(x,y) ((x) | ((y) << 8)) 2832 switch(C(req->bRequest, req->bmRequestType)) { 2833 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2834 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2835 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2836 /* 2837 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2838 * for the integrated root hub. 2839 */ 2840 break; 2841 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2842 if (len > 0) { 2843 *(u_int8_t *)buf = sc->sc_conf; 2844 totlen = 1; 2845 } 2846 break; 2847 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2848 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2849 if (len == 0) 2850 break; 2851 switch(value >> 8) { 2852 case UDESC_DEVICE: 2853 if ((value & 0xff) != 0) { 2854 err = USBD_IOERROR; 2855 goto ret; 2856 } 2857 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2858 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2859 memcpy(buf, &ohci_devd, l); 2860 break; 2861 case UDESC_CONFIG: 2862 if ((value & 0xff) != 0) { 2863 err = USBD_IOERROR; 2864 goto ret; 2865 } 2866 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2867 memcpy(buf, &ohci_confd, l); 2868 buf = (char *)buf + l; 2869 len -= l; 2870 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2871 totlen += l; 2872 memcpy(buf, &ohci_ifcd, l); 2873 buf = (char *)buf + l; 2874 len -= l; 2875 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2876 totlen += l; 2877 memcpy(buf, &ohci_endpd, l); 2878 break; 2879 case UDESC_STRING: 2880 *(u_int8_t *)buf = 0; 2881 totlen = 1; 2882 switch (value & 0xff) { 2883 case 0: /* Language table */ 2884 if (len > 0) 2885 *(u_int8_t *)buf = 4; 2886 if (len >= 4) { 2887 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 2888 totlen = 4; 2889 } 2890 break; 2891 case 1: /* Vendor */ 2892 totlen = ohci_str(buf, len, sc->sc_vendor); 2893 break; 2894 case 2: /* Product */ 2895 totlen = ohci_str(buf, len, "OHCI root hub"); 2896 break; 2897 } 2898 break; 2899 default: 2900 err = USBD_IOERROR; 2901 goto ret; 2902 } 2903 break; 2904 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2905 if (len > 0) { 2906 *(u_int8_t *)buf = 0; 2907 totlen = 1; 2908 } 2909 break; 2910 case C(UR_GET_STATUS, UT_READ_DEVICE): 2911 if (len > 1) { 2912 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2913 totlen = 2; 2914 } 2915 break; 2916 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2917 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2918 if (len > 1) { 2919 USETW(((usb_status_t *)buf)->wStatus, 0); 2920 totlen = 2; 2921 } 2922 break; 2923 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2924 if (value >= USB_MAX_DEVICES) { 2925 err = USBD_IOERROR; 2926 goto ret; 2927 } 2928 sc->sc_addr = value; 2929 break; 2930 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2931 if (value != 0 && value != 1) { 2932 err = USBD_IOERROR; 2933 goto ret; 2934 } 2935 sc->sc_conf = value; 2936 break; 2937 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2938 break; 2939 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2940 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2941 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2942 err = USBD_IOERROR; 2943 goto ret; 2944 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2945 break; 2946 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2947 break; 2948 /* Hub requests */ 2949 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2950 break; 2951 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2952 DPRINTFN(8, ("ohci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2953 "port=%d feature=%d\n", 2954 index, value)); 2955 if (index < 1 || index > sc->sc_noport) { 2956 err = USBD_IOERROR; 2957 goto ret; 2958 } 2959 port = OHCI_RH_PORT_STATUS(index); 2960 switch(value) { 2961 case UHF_PORT_ENABLE: 2962 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2963 break; 2964 case UHF_PORT_SUSPEND: 2965 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2966 break; 2967 case UHF_PORT_POWER: 2968 /* Yes, writing to the LOW_SPEED bit clears power. */ 2969 OWRITE4(sc, port, UPS_LOW_SPEED); 2970 break; 2971 case UHF_C_PORT_CONNECTION: 2972 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2973 break; 2974 case UHF_C_PORT_ENABLE: 2975 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2976 break; 2977 case UHF_C_PORT_SUSPEND: 2978 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2979 break; 2980 case UHF_C_PORT_OVER_CURRENT: 2981 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2982 break; 2983 case UHF_C_PORT_RESET: 2984 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2985 break; 2986 default: 2987 err = USBD_IOERROR; 2988 goto ret; 2989 } 2990 switch(value) { 2991 case UHF_C_PORT_CONNECTION: 2992 case UHF_C_PORT_ENABLE: 2993 case UHF_C_PORT_SUSPEND: 2994 case UHF_C_PORT_OVER_CURRENT: 2995 case UHF_C_PORT_RESET: 2996 /* Enable RHSC interrupt if condition is cleared. */ 2997 if ((OREAD4(sc, port) >> 16) == 0) 2998 ohci_rhsc_enable(sc); 2999 break; 3000 default: 3001 break; 3002 } 3003 break; 3004 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3005 if (len == 0) 3006 break; 3007 if ((value & 0xff) != 0) { 3008 err = USBD_IOERROR; 3009 goto ret; 3010 } 3011 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 3012 hubd = ohci_hubd; 3013 hubd.bNbrPorts = sc->sc_noport; 3014 USETW(hubd.wHubCharacteristics, 3015 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 3016 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 3017 /* XXX overcurrent */ 3018 ); 3019 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 3020 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 3021 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 3022 hubd.DeviceRemovable[i++] = (u_int8_t)v; 3023 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3024 l = min(len, hubd.bDescLength); 3025 totlen = l; 3026 memcpy(buf, &hubd, l); 3027 break; 3028 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3029 if (len != 4) { 3030 err = USBD_IOERROR; 3031 goto ret; 3032 } 3033 memset(buf, 0, len); /* ? XXX */ 3034 totlen = len; 3035 break; 3036 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3037 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 3038 index)); 3039 if (index < 1 || index > sc->sc_noport) { 3040 err = USBD_IOERROR; 3041 goto ret; 3042 } 3043 if (len != 4) { 3044 err = USBD_IOERROR; 3045 goto ret; 3046 } 3047 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 3048 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 3049 v)); 3050 USETW(ps.wPortStatus, v); 3051 USETW(ps.wPortChange, v >> 16); 3052 l = min(len, sizeof ps); 3053 memcpy(buf, &ps, l); 3054 totlen = l; 3055 break; 3056 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3057 err = USBD_IOERROR; 3058 goto ret; 3059 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3060 break; 3061 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3062 if (index < 1 || index > sc->sc_noport) { 3063 err = USBD_IOERROR; 3064 goto ret; 3065 } 3066 port = OHCI_RH_PORT_STATUS(index); 3067 switch(value) { 3068 case UHF_PORT_ENABLE: 3069 OWRITE4(sc, port, UPS_PORT_ENABLED); 3070 break; 3071 case UHF_PORT_SUSPEND: 3072 OWRITE4(sc, port, UPS_SUSPEND); 3073 break; 3074 case UHF_PORT_RESET: 3075 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 3076 index)); 3077 OWRITE4(sc, port, UPS_RESET); 3078 for (i = 0; i < 5; i++) { 3079 usb_delay_ms(&sc->sc_bus, 3080 USB_PORT_ROOT_RESET_DELAY); 3081 if (sc->sc_dying) { 3082 err = USBD_IOERROR; 3083 goto ret; 3084 } 3085 if ((OREAD4(sc, port) & UPS_RESET) == 0) 3086 break; 3087 } 3088 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 3089 index, OREAD4(sc, port))); 3090 break; 3091 case UHF_PORT_POWER: 3092 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 3093 "%d\n", index)); 3094 OWRITE4(sc, port, UPS_PORT_POWER); 3095 break; 3096 default: 3097 err = USBD_IOERROR; 3098 goto ret; 3099 } 3100 break; 3101 default: 3102 err = USBD_IOERROR; 3103 goto ret; 3104 } 3105 xfer->actlen = totlen; 3106 err = USBD_NORMAL_COMPLETION; 3107 ret: 3108 xfer->status = err; 3109 s = splusb(); 3110 #if 0 /* root ctrl doesn't do DMA */ 3111 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &OXFER(xfer)->dmabuf); 3112 #else 3113 usb_transfer_complete(xfer); 3114 #endif 3115 splx(s); 3116 return (USBD_IN_PROGRESS); 3117 } 3118 3119 /* Abort a root control request. */ 3120 Static void 3121 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 3122 { 3123 /* Nothing to do, all transfers are synchronous. */ 3124 } 3125 3126 /* Close the root pipe. */ 3127 Static void 3128 ohci_root_ctrl_close(usbd_pipe_handle pipe) 3129 { 3130 DPRINTF(("ohci_root_ctrl_close\n")); 3131 /* Nothing to do. */ 3132 } 3133 3134 Static usbd_status 3135 ohci_root_intr_transfer(usbd_xfer_handle xfer) 3136 { 3137 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3138 usbd_status err; 3139 3140 /* Insert last in queue. */ 3141 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3142 &OXFER(xfer)->dmabuf); 3143 if (err) 3144 return (err); 3145 3146 /* Pipe isn't running, start first */ 3147 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3148 } 3149 3150 Static usbd_status 3151 ohci_root_intr_start(usbd_xfer_handle xfer) 3152 { 3153 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3154 3155 if (sc->sc_dying) 3156 return (USBD_IOERROR); 3157 3158 sc->sc_intrxfer = xfer; 3159 3160 return (USBD_IN_PROGRESS); 3161 } 3162 3163 /* Abort a root interrupt request. */ 3164 Static void 3165 ohci_root_intr_abort(usbd_xfer_handle xfer) 3166 { 3167 usbd_pipe_handle pipe = xfer->pipe; 3168 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3169 int s; 3170 3171 if (pipe->intrxfer == xfer) { 3172 DPRINTF(("ohci_root_intr_abort: remove\n")); 3173 pipe->intrxfer = NULL; 3174 } 3175 xfer->status = USBD_CANCELLED; 3176 s = splusb(); 3177 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &OXFER(xfer)->dmabuf); 3178 splx(s); 3179 } 3180 3181 /* Close the root pipe. */ 3182 Static void 3183 ohci_root_intr_close(usbd_pipe_handle pipe) 3184 { 3185 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3186 3187 DPRINTF(("ohci_root_intr_close\n")); 3188 3189 sc->sc_intrxfer = NULL; 3190 } 3191 3192 /************************/ 3193 3194 Static usbd_status 3195 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 3196 { 3197 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3198 usbd_status err; 3199 3200 /* Insert last in queue. */ 3201 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3202 &OXFER(xfer)->dmabuf); 3203 if (err) 3204 return (err); 3205 3206 /* Pipe isn't running, start first */ 3207 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3208 } 3209 3210 Static usbd_status 3211 ohci_device_ctrl_start(usbd_xfer_handle xfer) 3212 { 3213 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3214 usbd_status err; 3215 3216 if (sc->sc_dying) 3217 return (USBD_IOERROR); 3218 3219 #ifdef DIAGNOSTIC 3220 if (!(xfer->rqflags & URQ_REQUEST)) { 3221 /* XXX panic */ 3222 printf("ohci_device_ctrl_transfer: not a request\n"); 3223 return (USBD_INVAL); 3224 } 3225 #endif 3226 3227 err = ohci_device_request(xfer); 3228 if (err) 3229 return (err); 3230 3231 if (sc->sc_bus.use_polling) 3232 ohci_waitintr(sc, xfer); 3233 return (USBD_IN_PROGRESS); 3234 } 3235 3236 /* Abort a device control request. */ 3237 Static void 3238 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 3239 { 3240 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 3241 ohci_abort_xfer(xfer, USBD_CANCELLED); 3242 } 3243 3244 /* Close a device control pipe. */ 3245 Static void 3246 ohci_device_ctrl_close(usbd_pipe_handle pipe) 3247 { 3248 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3249 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3250 3251 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 3252 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3253 ohci_free_std_norsv(sc, opipe->tail.td); 3254 usb_freemem(&sc->sc_dmatag, &opipe->u.ctl.reqdma); 3255 } 3256 3257 /************************/ 3258 3259 Static void 3260 ohci_device_clear_toggle(usbd_pipe_handle pipe) 3261 { 3262 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3263 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3264 3265 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3266 } 3267 3268 Static void 3269 ohci_noop(usbd_pipe_handle pipe) 3270 { 3271 } 3272 3273 Static usbd_status 3274 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 3275 { 3276 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3277 usbd_status err; 3278 3279 /* Insert last in queue. */ 3280 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3281 &OXFER(xfer)->dmabuf); 3282 if (err) 3283 return (err); 3284 3285 /* Pipe isn't running, start first */ 3286 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3287 } 3288 3289 Static usbd_status 3290 ohci_device_bulk_start(usbd_xfer_handle xfer) 3291 { 3292 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3293 usbd_device_handle dev = opipe->pipe.device; 3294 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3295 int addr = dev->address; 3296 ohci_soft_td_t *data, *tail, *tdp; 3297 ohci_soft_ed_t *sed; 3298 ohci_physaddr_t dmaadr; 3299 int s, len, isread, endpt; 3300 usbd_status err; 3301 3302 if (sc->sc_dying) 3303 return (USBD_IOERROR); 3304 3305 #ifdef DIAGNOSTIC 3306 if (xfer->rqflags & URQ_REQUEST) { 3307 /* XXX panic */ 3308 printf("ohci_device_bulk_start: a request\n"); 3309 return (USBD_INVAL); 3310 } 3311 #endif 3312 3313 len = xfer->length; 3314 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3315 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3316 sed = opipe->sed; 3317 3318 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3319 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3320 endpt)); 3321 3322 opipe->u.bulk.isread = isread; 3323 opipe->u.bulk.length = len; 3324 3325 /* Update device address */ 3326 sed->ed.ed_flags = HTOO32( 3327 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3328 OHCI_ED_SET_FA(addr)); 3329 3330 /* Allocate a chain of new TDs (including a new tail). */ 3331 data = opipe->tail.td; 3332 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3333 data, &tail); 3334 /* We want interrupt at the end of the transfer. */ 3335 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3336 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3337 tail->flags |= OHCI_CALL_DONE; 3338 OHCI_STD_SYNC(sc, tail, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3339 tail = tail->nexttd; /* point at sentinel */ 3340 if (err) 3341 return (err); 3342 3343 tail->xfer = NULL; 3344 xfer->hcpriv = data; 3345 3346 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3347 "td_cbp=0x%08x td_be=0x%08x\n", 3348 (int)O32TOH(sed->ed.ed_flags), 3349 (int)O32TOH(data->td.td_flags), 3350 (int)O32TOH(data->td.td_cbp), 3351 (int)O32TOH(data->td.td_be))); 3352 3353 #ifdef USB_DEBUG 3354 if (ohcidebug > 5) { 3355 ohci_dump_ed(sc, sed); 3356 ohci_dump_tds(sc, data); 3357 } 3358 #endif 3359 3360 /* Insert ED in schedule */ 3361 s = splusb(); 3362 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3363 tdp->xfer = xfer; 3364 } 3365 dmaadr = OHCI_STD_DMAADDR(tail); 3366 sed->ed.ed_tailp = HTOO32(dmaadr); 3367 opipe->tail.td = tail; 3368 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3369 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3370 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3371 if (xfer->timeout && !sc->sc_bus.use_polling) { 3372 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3373 ohci_timeout, xfer); 3374 } 3375 3376 #if 0 3377 /* This goes wrong if we are too slow. */ 3378 if (ohcidebug > 10) { 3379 delay(10000); 3380 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3381 OREAD4(sc, OHCI_COMMAND_STATUS))); 3382 ohci_dump_ed(sc, sed); 3383 ohci_dump_tds(sc, data); 3384 } 3385 #endif 3386 3387 splx(s); 3388 3389 if (sc->sc_bus.use_polling) 3390 ohci_waitintr(sc, xfer); 3391 3392 return (USBD_IN_PROGRESS); 3393 } 3394 3395 Static void 3396 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3397 { 3398 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3399 ohci_abort_xfer(xfer, USBD_CANCELLED); 3400 } 3401 3402 /* 3403 * Close a device bulk pipe. 3404 */ 3405 Static void 3406 ohci_device_bulk_close(usbd_pipe_handle pipe) 3407 { 3408 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3409 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3410 3411 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3412 ohci_close_pipe(pipe, sc->sc_bulk_head); 3413 ohci_free_std_norsv(sc, opipe->tail.td); 3414 } 3415 3416 /************************/ 3417 3418 Static usbd_status 3419 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3420 { 3421 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3422 usbd_status err; 3423 3424 /* Insert last in queue. */ 3425 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3426 &OXFER(xfer)->dmabuf); 3427 if (err) 3428 return (err); 3429 3430 /* Pipe isn't running, start first */ 3431 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3432 } 3433 3434 Static usbd_status 3435 ohci_device_intr_start(usbd_xfer_handle xfer) 3436 { 3437 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3438 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3439 ohci_soft_ed_t *sed = opipe->sed; 3440 usbd_status err; 3441 3442 if (sc->sc_dying) 3443 return (USBD_IOERROR); 3444 3445 DPRINTFN(3, ("ohci_device_intr_start: xfer=%p len=%d " 3446 "flags=%d priv=%p\n", 3447 xfer, xfer->length, xfer->flags, xfer->priv)); 3448 3449 #ifdef DIAGNOSTIC 3450 if (xfer->rqflags & URQ_REQUEST) 3451 panic("ohci_device_intr_start: a request"); 3452 #endif 3453 3454 err = ohci_device_intr_insert(sc, xfer); 3455 if (err) 3456 return (err); 3457 3458 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3459 3460 return (USBD_IN_PROGRESS); 3461 } 3462 3463 /* 3464 * Insert an interrupt transfer into an endpoint descriptor list 3465 */ 3466 Static usbd_status 3467 ohci_device_intr_insert(ohci_softc_t *sc, usbd_xfer_handle xfer) 3468 { 3469 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3470 ohci_soft_ed_t *sed = opipe->sed; 3471 ohci_soft_td_t *data, *tail; 3472 ohci_physaddr_t dataphys, physend; 3473 ohci_physaddr_t dmaadr; 3474 int s, isread, endpt; 3475 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 3476 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 3477 int nsegs = USB_BUFFER_NSEGS(ub); 3478 3479 DPRINTFN(4, ("ohci_device_intr_insert: xfer=%p", xfer)); 3480 3481 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3482 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3483 3484 data = opipe->tail.td; 3485 tail = ohci_alloc_std(sc); 3486 if (tail == NULL) 3487 return (USBD_NOMEM); 3488 tail->xfer = NULL; 3489 3490 data->td.td_flags = HTOO32( 3491 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3492 OHCI_TD_NOCC | 3493 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3494 if (xfer->flags & USBD_SHORT_XFER_OK) 3495 data->td.td_flags |= HTOO32(OHCI_TD_R); 3496 /* 3497 * Assume a short mapping with no complications, which 3498 * should always be true for <= 4k buffers in contiguous 3499 * virtual memory. The data can take the following forms: 3500 * 1 segment in 1 OHCI page 3501 * 1 segment in 2 OHCI pages 3502 * 2 segments in 2 OHCI pages 3503 * (see comment in ohci_alloc_std_chain() for details) 3504 */ 3505 USB_KASSERT2(xfer->length > 0 && xfer->length <= OHCI_PAGE_SIZE, 3506 ("ohci_device_intr_insert: bad length %d", xfer->length)); 3507 dataphys = segs[0].ds_addr; 3508 physend = dataphys + xfer->length - 1; 3509 if (nsegs == 2) { 3510 USB_KASSERT2(OHCI_PAGE_OFFSET(dataphys + 3511 segs[0].ds_len) == 0, 3512 ("ohci_device_intr_insert: bad seg 0 termination")); 3513 physend = segs[1].ds_addr + xfer->length - 3514 segs[0].ds_len - 1; 3515 } else { 3516 USB_KASSERT2(nsegs == 1, 3517 ("ohci_device_intr_insert: bad seg count %d", 3518 (u_int)nsegs)); 3519 } 3520 data->td.td_cbp = HTOO32(dataphys); 3521 data->nexttd = tail; 3522 dmaadr = OHCI_STD_DMAADDR(tail); 3523 data->td.td_nexttd = HTOO32(dmaadr); 3524 data->td.td_be = HTOO32(physend); 3525 data->len = xfer->length; 3526 data->xfer = xfer; 3527 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3528 xfer->hcpriv = data; 3529 xfer->actlen = 0; 3530 OHCI_STD_SYNC(sc, data, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3531 3532 #ifdef USB_DEBUG 3533 if (ohcidebug > 5) { 3534 DPRINTF(("ohci_device_intr_insert:\n")); 3535 ohci_dump_ed(sc, sed); 3536 ohci_dump_tds(sc, data); 3537 } 3538 #endif 3539 3540 /* Insert ED in schedule */ 3541 s = splusb(); 3542 dmaadr = OHCI_STD_DMAADDR(tail); 3543 sed->ed.ed_tailp = HTOO32(dmaadr); 3544 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3545 opipe->tail.td = tail; 3546 splx(s); 3547 3548 return (USBD_NORMAL_COMPLETION); 3549 } 3550 3551 /* Abort a device control request. */ 3552 Static void 3553 ohci_device_intr_abort(usbd_xfer_handle xfer) 3554 { 3555 if (xfer->pipe->intrxfer == xfer) { 3556 DPRINTF(("ohci_device_intr_abort: remove\n")); 3557 xfer->pipe->intrxfer = NULL; 3558 } 3559 ohci_abort_xfer(xfer, USBD_CANCELLED); 3560 } 3561 3562 /* Close a device interrupt pipe. */ 3563 Static void 3564 ohci_device_intr_close(usbd_pipe_handle pipe) 3565 { 3566 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3567 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3568 int nslots = opipe->u.intr.nslots; 3569 int pos = opipe->u.intr.pos; 3570 int j; 3571 ohci_soft_ed_t *p, *sed = opipe->sed; 3572 int s; 3573 3574 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3575 pipe, nslots, pos)); 3576 s = splusb(); 3577 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3578 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3579 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3580 usb_delay_ms(&sc->sc_bus, 2); 3581 #ifdef DIAGNOSTIC 3582 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3583 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3584 panic("%s: Intr pipe %p still has TDs queued", 3585 USBDEVNAME(sc->sc_bus.bdev), pipe); 3586 #endif 3587 3588 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3589 ; 3590 #ifdef DIAGNOSTIC 3591 if (p == NULL) 3592 panic("ohci_device_intr_close: ED not found"); 3593 #endif 3594 p->next = sed->next; 3595 p->ed.ed_nexted = sed->ed.ed_nexted; 3596 splx(s); 3597 3598 for (j = 0; j < nslots; j++) 3599 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3600 3601 ohci_free_std_norsv(sc, opipe->tail.td); 3602 ohci_free_sed(sc, opipe->sed); 3603 } 3604 3605 Static usbd_status 3606 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3607 { 3608 int i, j, s, best; 3609 u_int npoll, slow, shigh, nslots; 3610 u_int bestbw, bw; 3611 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3612 ohci_physaddr_t dmaadr; 3613 3614 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3615 if (ival == 0) { 3616 printf("ohci_setintr: 0 interval\n"); 3617 return (USBD_INVAL); 3618 } 3619 3620 npoll = OHCI_NO_INTRS; 3621 while (npoll > ival) 3622 npoll /= 2; 3623 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3624 3625 /* 3626 * We now know which level in the tree the ED must go into. 3627 * Figure out which slot has most bandwidth left over. 3628 * Slots to examine: 3629 * npoll 3630 * 1 0 3631 * 2 1 2 3632 * 4 3 4 5 6 3633 * 8 7 8 9 10 11 12 13 14 3634 * N (N-1) .. (N-1+N-1) 3635 */ 3636 slow = npoll-1; 3637 shigh = slow + npoll; 3638 nslots = OHCI_NO_INTRS / npoll; 3639 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3640 bw = 0; 3641 for (j = 0; j < nslots; j++) 3642 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3643 if (bw < bestbw) { 3644 best = i; 3645 bestbw = bw; 3646 } 3647 } 3648 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3649 best, slow, shigh, bestbw)); 3650 3651 s = splusb(); 3652 hsed = sc->sc_eds[best]; 3653 sed->next = hsed->next; 3654 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3655 hsed->next = sed; 3656 dmaadr = OHCI_SED_DMAADDR(sed); 3657 hsed->ed.ed_nexted = HTOO32(dmaadr); 3658 splx(s); 3659 3660 for (j = 0; j < nslots; j++) 3661 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3662 opipe->u.intr.nslots = nslots; 3663 opipe->u.intr.pos = best; 3664 3665 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3666 return (USBD_NORMAL_COMPLETION); 3667 } 3668 3669 /***********************/ 3670 3671 usbd_status 3672 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3673 { 3674 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3675 usbd_status err; 3676 3677 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3678 3679 /* Put it on our queue, */ 3680 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3681 &OXFER(xfer)->dmabuf); 3682 3683 /* bail out on error, */ 3684 if (err && err != USBD_IN_PROGRESS) 3685 return (err); 3686 3687 /* XXX should check inuse here */ 3688 3689 /* insert into schedule, */ 3690 ohci_device_isoc_enter(xfer); 3691 3692 /* and start if the pipe wasn't running */ 3693 if (!err) 3694 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3695 3696 return (err); 3697 } 3698 3699 void 3700 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3701 { 3702 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3703 usbd_device_handle dev = opipe->pipe.device; 3704 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3705 ohci_soft_ed_t *sed = opipe->sed; 3706 struct iso *iso = &opipe->u.iso; 3707 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 3708 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 3709 int nsegs = USB_BUFFER_NSEGS(ub); 3710 ohci_soft_itd_t *sitd, *nsitd; 3711 ohci_physaddr_t dataphys, bp0, physend, prevpage; 3712 ohci_physaddr_t dmaadr; 3713 int curlen, i, len, ncur, nframes, npages, seg, segoff; 3714 int s; 3715 3716 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3717 "nframes=%d\n", 3718 iso->inuse, iso->next, xfer, xfer->nframes)); 3719 3720 if (sc->sc_dying) 3721 return; 3722 3723 if (iso->next == -1) { 3724 /* Not in use yet, schedule it a few frames ahead. */ 3725 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3726 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3727 iso->next)); 3728 } 3729 3730 sitd = opipe->tail.itd; 3731 nframes = xfer->nframes; 3732 xfer->hcpriv = sitd; 3733 seg = 0; 3734 segoff = 0; 3735 i = 0; 3736 while (i < nframes) { 3737 /* 3738 * Fill in as many ITD frames as possible. 3739 */ 3740 USB_KASSERT2(seg < nsegs, 3741 ("ohci_device_isoc_enter: overrun")); 3742 bp0 = segs[seg].ds_addr + segoff; 3743 sitd->itd.itd_bp0 = HTOO32(bp0); 3744 prevpage = OHCI_PAGE(bp0); 3745 npages = 1; 3746 3747 ncur = 0; 3748 while (ncur < OHCI_ITD_NOFFSET && i < nframes) { 3749 /* Find the frame start and end physical addresses. */ 3750 len = xfer->frlengths[i]; 3751 dataphys = segs[seg].ds_addr + segoff; 3752 curlen = segs[seg].ds_len - segoff; 3753 if (len > curlen) { 3754 USB_KASSERT2(seg + 1 < nsegs, 3755 ("ohci_device_isoc_enter: overrun2")); 3756 seg++; 3757 segoff = len - curlen; 3758 } else { 3759 segoff += len; 3760 } 3761 USB_KASSERT2(segoff <= segs[seg].ds_len, 3762 ("ohci_device_isoc_enter: overrun3")); 3763 physend = segs[seg].ds_addr + segoff - 1; 3764 3765 /* Check if there would be more than 2 pages . */ 3766 if (OHCI_PAGE(dataphys) != prevpage) { 3767 prevpage = OHCI_PAGE(dataphys); 3768 npages++; 3769 } 3770 if (OHCI_PAGE(physend) != prevpage) { 3771 prevpage = OHCI_PAGE(physend); 3772 npages++; 3773 } 3774 if (npages > 2 || 3775 ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) && 3776 npages == 2 && 3777 OHCI_PAGE_OFFSET(physend) == OHCI_PAGE_SIZE - 1)) { 3778 /* We cannot fit this frame now. */ 3779 segoff -= len; 3780 if (segoff < 0) { 3781 seg--; 3782 segoff += segs[seg].ds_len; 3783 } 3784 break; 3785 } 3786 3787 sitd->itd.itd_be = HTOO32(physend); 3788 sitd->itd.itd_offset[ncur] = 3789 HTOO16(OHCI_ITD_MK_OFFS(OHCI_PAGE(dataphys) == 3790 OHCI_PAGE(bp0) ? 0 : 1, dataphys)); 3791 i++; 3792 ncur++; 3793 } 3794 if (segoff >= segs[seg].ds_len) { 3795 USB_KASSERT2(segoff == segs[seg].ds_len, 3796 ("ohci_device_isoc_enter: overlap")); 3797 seg++; 3798 segoff = 0; 3799 } 3800 3801 /* Allocate next ITD */ 3802 nsitd = ohci_alloc_sitd(sc); 3803 if (nsitd == NULL) { 3804 /* XXX what now? */ 3805 printf("%s: isoc TD alloc failed\n", 3806 USBDEVNAME(sc->sc_bus.bdev)); 3807 return; 3808 } 3809 3810 /* Fill out remaining fields of current ITD */ 3811 sitd->nextitd = nsitd; 3812 dmaadr = OHCI_SITD_DMAADDR(nsitd); 3813 sitd->itd.itd_nextitd = HTOO32(dmaadr); 3814 sitd->xfer = xfer; 3815 if (i < nframes) { 3816 sitd->itd.itd_flags = HTOO32( 3817 OHCI_ITD_NOCC | 3818 OHCI_ITD_SET_SF(iso->next) | 3819 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3820 OHCI_ITD_SET_FC(ncur)); 3821 sitd->flags = OHCI_ITD_ACTIVE; 3822 } else { 3823 sitd->itd.itd_flags = HTOO32( 3824 OHCI_ITD_NOCC | 3825 OHCI_ITD_SET_SF(iso->next) | 3826 OHCI_ITD_SET_DI(0) | 3827 OHCI_ITD_SET_FC(ncur)); 3828 sitd->flags = OHCI_CALL_DONE | OHCI_ITD_ACTIVE; 3829 } 3830 iso->next += ncur; 3831 3832 OHCI_SITD_SYNC(sc, sitd, 3833 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3834 sitd = nsitd; 3835 } 3836 3837 iso->inuse += nframes; 3838 3839 /* XXX pretend we did it all */ 3840 xfer->actlen = 0; 3841 for (i = 0; i < nframes; i++) 3842 xfer->actlen += xfer->frlengths[i]; 3843 3844 xfer->status = USBD_IN_PROGRESS; 3845 3846 #ifdef USB_DEBUG 3847 if (ohcidebug > 5) { 3848 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3849 O32TOH(sc->sc_hcca->hcca_frame_number))); 3850 ohci_dump_itds(sc, xfer->hcpriv); 3851 ohci_dump_ed(sc, sed); 3852 } 3853 #endif 3854 3855 s = splusb(); 3856 opipe->tail.itd = sitd; 3857 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3858 dmaadr = OHCI_SITD_DMAADDR(sitd); 3859 sed->ed.ed_tailp = HTOO32(dmaadr); 3860 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3861 splx(s); 3862 3863 #ifdef USB_DEBUG 3864 if (ohcidebug > 5) { 3865 delay(150000); 3866 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3867 O32TOH(sc->sc_hcca->hcca_frame_number))); 3868 ohci_dump_itds(sc, xfer->hcpriv); 3869 ohci_dump_ed(sc, sed); 3870 } 3871 #endif 3872 } 3873 3874 usbd_status 3875 ohci_device_isoc_start(usbd_xfer_handle xfer) 3876 { 3877 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3878 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3879 ohci_soft_ed_t *sed; 3880 int s; 3881 3882 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3883 3884 if (sc->sc_dying) 3885 return (USBD_IOERROR); 3886 3887 #ifdef DIAGNOSTIC 3888 if (xfer->status != USBD_IN_PROGRESS) 3889 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3890 #endif 3891 3892 /* XXX anything to do? */ 3893 3894 s = splusb(); 3895 sed = opipe->sed; /* Turn off ED skip-bit to start processing */ 3896 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* ED's ITD list.*/ 3897 splx(s); 3898 3899 return (USBD_IN_PROGRESS); 3900 } 3901 3902 void 3903 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3904 { 3905 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3906 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3907 ohci_soft_ed_t *sed; 3908 ohci_soft_itd_t *sitd, *sitdnext, *tmp_sitd; 3909 ohci_physaddr_t dmaadr; 3910 int s,undone,num_sitds; 3911 3912 s = splusb(); 3913 opipe->aborting = 1; 3914 3915 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3916 3917 /* Transfer is already done. */ 3918 if (xfer->status != USBD_NOT_STARTED && 3919 xfer->status != USBD_IN_PROGRESS) { 3920 splx(s); 3921 printf("ohci_device_isoc_abort: early return\n"); 3922 return; 3923 } 3924 3925 /* Give xfer the requested abort code. */ 3926 xfer->status = USBD_CANCELLED; 3927 3928 sed = opipe->sed; 3929 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3930 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3931 3932 num_sitds = 0; 3933 sitd = xfer->hcpriv; 3934 #ifdef DIAGNOSTIC 3935 if (sitd == NULL) { 3936 splx(s); 3937 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3938 return; 3939 } 3940 #endif 3941 for (; sitd != NULL && sitd->xfer == xfer; sitd = sitd->nextitd) { 3942 num_sitds++; 3943 #ifdef DIAGNOSTIC 3944 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3945 sitd->isdone = 1; 3946 #endif 3947 } 3948 3949 splx(s); 3950 3951 /* 3952 * Each sitd has up to OHCI_ITD_NOFFSET transfers, each can 3953 * take a usb 1ms cycle. Conservatively wait for it to drain. 3954 * Even with DMA done, it can take awhile for the "batch" 3955 * delivery of completion interrupts to occur thru the controller. 3956 */ 3957 3958 do { 3959 usb_delay_ms(&sc->sc_bus, 2*(num_sitds*OHCI_ITD_NOFFSET)); 3960 3961 undone = 0; 3962 tmp_sitd = xfer->hcpriv; 3963 for (; tmp_sitd != NULL && tmp_sitd->xfer == xfer; 3964 tmp_sitd = tmp_sitd->nextitd) { 3965 OHCI_SITD_SYNC(sc, tmp_sitd, 3966 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3967 if (OHCI_CC_NO_ERROR == 3968 OHCI_ITD_GET_CC(O32TOH(tmp_sitd->itd.itd_flags)) && 3969 tmp_sitd->flags & OHCI_ITD_ACTIVE && 3970 (tmp_sitd->flags & OHCI_ITD_INTFIN) == 0) 3971 undone++; 3972 } 3973 } while( undone != 0 ); 3974 3975 /* Free the sitds */ 3976 for (sitd = xfer->hcpriv; sitd->xfer == xfer; 3977 sitd = sitdnext) { 3978 sitdnext = sitd->nextitd; 3979 ohci_free_sitd(sc, sitd); 3980 } 3981 3982 s = splusb(); 3983 3984 /* Run callback. */ 3985 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &OXFER(xfer)->dmabuf); 3986 3987 /* There is always a `next' sitd so link it up. */ 3988 dmaadr = OHCI_SITD_DMAADDR(sitd); 3989 sed->ed.ed_headp = HTOO32(dmaadr); 3990 3991 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3992 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3993 3994 splx(s); 3995 } 3996 3997 void 3998 ohci_device_isoc_done(usbd_xfer_handle xfer) 3999 { 4000 /* This null routine corresponds to non-isoc "done()" routines 4001 * that free the stds associated with an xfer after a completed 4002 * xfer interrupt. However, in the case of isoc transfers, the 4003 * sitds associated with the transfer have already been processed 4004 * and reallocated for the next iteration by 4005 * "ohci_device_isoc_transfer()". 4006 * 4007 * Routine "usb_transfer_complete()" is called at the end of every 4008 * relevant usb interrupt. "usb_transfer_complete()" indirectly 4009 * calls 1) "ohci_device_isoc_transfer()" (which keeps pumping the 4010 * pipeline by setting up the next transfer iteration) and 2) then 4011 * calls "ohci_device_isoc_done()". Isoc transfers have not been 4012 * working for the ohci usb because this routine was trashing the 4013 * xfer set up for the next iteration (thus, only the first 4014 * UGEN_NISOREQS xfers outstanding on an open would work). Perhaps 4015 * this could all be re-factored, but that's another pass... 4016 */ 4017 } 4018 4019 usbd_status 4020 ohci_setup_isoc(usbd_pipe_handle pipe) 4021 { 4022 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4023 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4024 struct iso *iso = &opipe->u.iso; 4025 int s; 4026 4027 iso->next = -1; 4028 iso->inuse = 0; 4029 4030 s = splusb(); 4031 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 4032 splx(s); 4033 4034 return (USBD_NORMAL_COMPLETION); 4035 } 4036 4037 void 4038 ohci_device_isoc_close(usbd_pipe_handle pipe) 4039 { 4040 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4041 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4042 ohci_soft_ed_t *sed; 4043 4044 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 4045 4046 sed = opipe->sed; 4047 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4048 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* Stop device. */ 4049 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4050 4051 ohci_close_pipe(pipe, sc->sc_isoc_head); /* Stop isoc list, free ED.*/ 4052 4053 /* up to NISOREQs xfers still outstanding. */ 4054 4055 #ifdef DIAGNOSTIC 4056 opipe->tail.itd->isdone = 1; 4057 #endif 4058 ohci_free_sitd_norsv(sc, opipe->tail.itd); /* Next `avail free' sitd.*/ 4059 } 4060
Indexes created Fri Oct 03 02:09:57 GMT 2025