ohci.c revision 1.182.12.3
1 /* $NetBSD: ohci.c,v 1.182.12.3 2008/05/21 05:02:11 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology. 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Charles M. Hannum. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * USB Open Host Controller driver. 44 * 45 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 46 * USB spec: http://www.usb.org/developers/docs/ 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.182.12.3 2008/05/21 05:02:11 itohy Exp $"); 51 /* __FBSDID("$FreeBSD: src/sys/dev/usb/ohci.c,v 1.167 2006/10/19 01:15:58 iedowse Exp $"); */ 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #if defined(__NetBSD__) || defined(__OpenBSD__) 58 #include <sys/device.h> 59 #include <sys/select.h> 60 #include <uvm/uvm_extern.h> 61 #elif defined(__FreeBSD__) 62 #include <sys/endian.h> 63 #include <sys/module.h> 64 #include <sys/bus.h> 65 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 66 #include <machine/cpu.h> 67 #endif 68 #endif 69 #include <sys/proc.h> 70 #include <sys/queue.h> 71 72 #include <machine/bus.h> 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ohcireg.h> 82 #include <dev/usb/ohcivar.h> 83 84 #if defined(__FreeBSD__) 85 #include <sys/sysctl.h> 86 87 #define delay(d) DELAY(d) 88 #endif 89 90 #if defined(__OpenBSD__) 91 struct cfdriver ohci_cd = { 92 NULL, "ohci", DV_DULL 93 }; 94 #endif 95 96 #ifdef USB_DEBUG 97 #define DPRINTF(x) if (ohcidebug) logprintf x 98 #define DPRINTFN(n,x) if (ohcidebug>(n)) logprintf x 99 int ohcidebug = 0; 100 #ifdef __FreeBSD__ 101 SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 102 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 103 &ohcidebug, 0, "ohci debug level"); 104 #endif 105 #ifndef __NetBSD__ 106 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 107 #endif 108 #else 109 #define DPRINTF(x) 110 #define DPRINTFN(n,x) 111 #endif 112 113 /* 114 * The OHCI controller is either little endian or host endian, 115 * so on big endian machines with little endian controller 116 * the data strored in memory needs to be swapped. 117 */ 118 #define O16TOH(val) (sc->sc_endian ? (val) : le16toh(val)) 119 #define O32TOH(val) (sc->sc_endian ? (val) : le32toh(val)) 120 #define HTOO16(val) (sc->sc_endian ? (val) : htole16(val)) 121 #define HTOO32(val) (sc->sc_endian ? (val) : htole32(val)) 122 123 struct ohci_pipe; 124 125 Static void ohci_free_desc_chunks(ohci_softc_t *, 126 struct ohci_mdescs *); 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static usbd_status ohci_grow_std(ohci_softc_t *); 131 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 132 Static ohci_soft_td_t *ohci_alloc_std_norsv(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_norsv(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static usbd_status ohci_grow_sitd(ohci_softc_t *); 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static ohci_soft_itd_t *ohci_alloc_sitd_norsv(ohci_softc_t *); 139 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 140 Static void ohci_free_sitd_norsv(ohci_softc_t *,ohci_soft_itd_t *); 141 142 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 143 ohci_soft_td_t *); 144 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 145 ohci_softc_t *, int, int, usbd_xfer_handle, 146 ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(usbd_pipe_handle); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 152 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 153 154 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 160 Static ohci_soft_td_t *ohci_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static ohci_soft_itd_t *ohci_find_itd(ohci_softc_t *, ohci_physaddr_t); 162 163 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 164 Static void ohci_device_isoc_enter(usbd_xfer_handle); 165 166 Static usbd_status ohci_prealloc(struct ohci_softc *, 167 struct ohci_xfer *, size_t, int); 168 Static usbd_status ohci_allocm(struct usbd_bus *, usbd_xfer_handle, 169 void *buf, size_t); 170 Static void ohci_freem(struct usbd_bus *, usbd_xfer_handle, 171 enum usbd_waitflg); 172 173 Static usbd_status ohci_map_alloc(usbd_xfer_handle); 174 Static void ohci_map_free(usbd_xfer_handle); 175 Static void ohci_mapm(usbd_xfer_handle, void *, size_t); 176 Static usbd_status ohci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 177 Static void ohci_unmapm(usbd_xfer_handle); 178 179 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *, usbd_pipe_handle, 180 enum usbd_waitflg); 181 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 182 183 Static void ohci_transfer_complete(usbd_xfer_handle, int); 184 185 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 187 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 188 Static void ohci_root_ctrl_close(usbd_pipe_handle); 189 Static void ohci_root_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 192 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 193 Static void ohci_root_intr_abort(usbd_xfer_handle); 194 Static void ohci_root_intr_close(usbd_pipe_handle); 195 Static void ohci_root_intr_done(usbd_xfer_handle); 196 197 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 198 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 199 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 200 Static void ohci_device_ctrl_close(usbd_pipe_handle); 201 Static void ohci_device_ctrl_done(usbd_xfer_handle); 202 203 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 204 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 205 Static void ohci_device_bulk_abort(usbd_xfer_handle); 206 Static void ohci_device_bulk_close(usbd_pipe_handle); 207 Static void ohci_device_bulk_done(usbd_xfer_handle); 208 209 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 210 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 211 Static void ohci_device_intr_abort(usbd_xfer_handle); 212 Static void ohci_device_intr_close(usbd_pipe_handle); 213 Static void ohci_device_intr_done(usbd_xfer_handle); 214 215 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 216 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 217 Static void ohci_device_isoc_abort(usbd_xfer_handle); 218 Static void ohci_device_isoc_close(usbd_pipe_handle); 219 Static void ohci_device_isoc_done(usbd_xfer_handle); 220 221 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 222 struct ohci_pipe *pipe, int ival); 223 Static usbd_status ohci_device_intr_insert(ohci_softc_t *sc, 224 usbd_xfer_handle xfer); 225 226 Static int ohci_str(usb_string_descriptor_t *, int, const char *); 227 228 Static void ohci_timeout(void *); 229 Static void ohci_timeout_task(void *); 230 Static void ohci_rhsc_enable(void *); 231 232 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 233 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 234 235 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 236 Static void ohci_noop(usbd_pipe_handle pipe); 237 238 Static usbd_status ohci_controller_init(ohci_softc_t *sc); 239 240 Static void ohci_aux_mem_init(struct ohci_aux_mem *); 241 Static usbd_status ohci_aux_mem_alloc(ohci_softc_t *, 242 struct ohci_aux_mem *, 243 int /*naux*/, int /*maxp*/); 244 Static void ohci_aux_mem_free(ohci_softc_t *, 245 struct ohci_aux_mem *); 246 Static bus_addr_t ohci_aux_dma_alloc(struct ohci_aux_mem *, 247 const union usb_bufptr *, int, 248 struct usb_aux_desc *); 249 Static void ohci_aux_dma_complete(struct usb_aux_desc *, 250 struct ohci_aux_mem *, 251 int /*is_mbuf*/, int /*isread*/); 252 Static void ohci_aux_dma_sync(ohci_softc_t *, 253 struct ohci_aux_mem *, int /*op*/); 254 255 #ifdef USB_DEBUG 256 Static void ohci_dumpregs(ohci_softc_t *); 257 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 258 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 259 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 260 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 261 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 262 #endif 263 264 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 265 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 266 #define OWRITE1(sc, r, x) \ 267 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 268 #define OWRITE2(sc, r, x) \ 269 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 270 #define OWRITE4(sc, r, x) \ 271 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 272 static __inline uint8_t 273 OREAD1(ohci_softc_t *sc, bus_size_t r) 274 { 275 276 OBARR(sc); 277 return bus_space_read_1(sc->iot, sc->ioh, r); 278 } 279 280 static __inline uint16_t 281 OREAD2(ohci_softc_t *sc, bus_size_t r) 282 { 283 284 OBARR(sc); 285 return bus_space_read_2(sc->iot, sc->ioh, r); 286 } 287 288 static __inline uint32_t 289 OREAD4(ohci_softc_t *sc, bus_size_t r) 290 { 291 292 OBARR(sc); 293 return bus_space_read_4(sc->iot, sc->ioh, r); 294 } 295 296 /* Reverse the bits in a value 0 .. 31 */ 297 Static u_int8_t revbits[OHCI_NO_INTRS] = 298 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 299 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 300 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 301 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 302 303 struct ohci_pipe { 304 struct usbd_pipe pipe; 305 ohci_soft_ed_t *sed; 306 u_int32_t aborting; 307 union { 308 ohci_soft_td_t *td; 309 ohci_soft_itd_t *itd; 310 } tail; 311 /* Info needed for different pipe kinds. */ 312 union { 313 /* Control pipe */ 314 struct { 315 usb_dma_t reqdma; 316 u_int length; 317 ohci_soft_td_t *setup, *data, *stat; 318 } ctl; 319 /* Interrupt pipe */ 320 struct { 321 int nslots; 322 int pos; 323 } intr; 324 /* Bulk pipe */ 325 struct { 326 u_int length; 327 int isread; 328 } bulk; 329 /* Iso pipe */ 330 struct iso { 331 int next, inuse; 332 } iso; 333 } u; 334 }; 335 336 #define OHCI_INTR_ENDPT 1 337 338 Static const struct usbd_bus_methods ohci_bus_methods = { 339 ohci_open, 340 ohci_softintr, 341 ohci_poll, 342 ohci_allocm, 343 ohci_freem, 344 ohci_map_alloc, 345 ohci_map_free, 346 ohci_mapm, 347 ohci_mapm_mbuf, 348 ohci_unmapm, 349 ohci_allocx, 350 ohci_freex, 351 }; 352 353 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 354 ohci_root_ctrl_transfer, 355 ohci_root_ctrl_start, 356 ohci_root_ctrl_abort, 357 ohci_root_ctrl_close, 358 ohci_noop, 359 ohci_root_ctrl_done, 360 }; 361 362 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 363 ohci_root_intr_transfer, 364 ohci_root_intr_start, 365 ohci_root_intr_abort, 366 ohci_root_intr_close, 367 ohci_noop, 368 ohci_root_intr_done, 369 }; 370 371 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 372 ohci_device_ctrl_transfer, 373 ohci_device_ctrl_start, 374 ohci_device_ctrl_abort, 375 ohci_device_ctrl_close, 376 ohci_noop, 377 ohci_device_ctrl_done, 378 }; 379 380 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 381 ohci_device_intr_transfer, 382 ohci_device_intr_start, 383 ohci_device_intr_abort, 384 ohci_device_intr_close, 385 ohci_device_clear_toggle, 386 ohci_device_intr_done, 387 }; 388 389 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 390 ohci_device_bulk_transfer, 391 ohci_device_bulk_start, 392 ohci_device_bulk_abort, 393 ohci_device_bulk_close, 394 ohci_device_clear_toggle, 395 ohci_device_bulk_done, 396 }; 397 398 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 399 ohci_device_isoc_transfer, 400 ohci_device_isoc_start, 401 ohci_device_isoc_abort, 402 ohci_device_isoc_close, 403 ohci_noop, 404 ohci_device_isoc_done, 405 }; 406 407 #if defined(__NetBSD__) || defined(__OpenBSD__) 408 int 409 ohci_activate(device_t self, enum devact act) 410 { 411 struct ohci_softc *sc = (struct ohci_softc *)self; 412 int rv = 0; 413 414 switch (act) { 415 case DVACT_ACTIVATE: 416 return (EOPNOTSUPP); 417 418 case DVACT_DEACTIVATE: 419 if (sc->sc_child != NULL) 420 rv = config_deactivate(sc->sc_child); 421 sc->sc_dying = 1; 422 break; 423 } 424 return (rv); 425 } 426 #endif 427 428 int 429 ohci_detach(struct ohci_softc *sc, int flags) 430 { 431 int rv = 0; 432 usbd_xfer_handle xfer; 433 434 sc->sc_dying = 1; 435 436 #if defined(__NetBSD__) || defined(__OpenBSD__) 437 if (sc->sc_child != NULL) 438 rv = config_detach(sc->sc_child, flags); 439 440 if (rv != 0) 441 return (rv); 442 #endif 443 444 if (sc->sc_bus.methods == NULL) 445 return (rv); /* attach has been aborted */ 446 447 usb_uncallout(sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 448 449 #if defined(__NetBSD__) || defined(__OpenBSD__) 450 powerhook_disestablish(sc->sc_powerhook); 451 shutdownhook_disestablish(sc->sc_shutdownhook); 452 #endif 453 454 #if defined(__NetBSD__) || defined(__OpenBSD__) 455 /* Don't touch hardware if it has already been gone. */ 456 if ((flags & DETACH_FORCE) == 0) 457 #endif 458 { 459 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 460 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 461 } 462 463 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 464 465 #if 0 /* freed by ohci_free_desc_chunks(sc, &sc->sc_sed_chunks) below */ 466 for (i = 0; i < OHCI_NO_EDS; i++) 467 ohci_free_sed(sc, sc->sc_eds[i]); 468 ohci_free_sed(sc, sc->sc_isoc_head); 469 ohci_free_sed(sc, sc->sc_bulk_head); 470 ohci_free_sed(sc, sc->sc_ctrl_head); 471 #endif 472 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 473 474 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 475 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 476 usb_clean_buffer_dma(&sc->sc_dmatag, &OXFER(xfer)->dmabuf); 477 free(xfer, M_USB); 478 } 479 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 480 ohci_free_desc_chunks(sc, &sc->sc_std_chunks); 481 ohci_free_desc_chunks(sc, &sc->sc_sitd_chunks); 482 usb_dma_tag_finish(&sc->sc_dmatag); 483 484 return (rv); 485 } 486 487 Static void 488 ohci_free_desc_chunks(ohci_softc_t *sc, struct ohci_mdescs *c) 489 { 490 struct ohci_mem_desc *om; 491 492 while ((om = SIMPLEQ_FIRST(c)) != NULL) { 493 SIMPLEQ_REMOVE_HEAD(c, om_next); 494 usb_freemem(&sc->sc_dmatag, &om->om_dma); 495 } 496 } 497 498 ohci_soft_ed_t * 499 ohci_alloc_sed(ohci_softc_t *sc) 500 { 501 ohci_soft_ed_t *sed; 502 usbd_status err; 503 int i, offs; 504 usb_dma_t dma; 505 struct ohci_mem_desc *om; 506 507 if (sc->sc_freeeds == NULL) { 508 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 509 err = usb_allocmem(&sc->sc_dmatag, 510 OHCI_SED_SIZE*OHCI_SED_CHUNK + sizeof(struct ohci_mem_desc), 511 OHCI_ED_ALIGN, &dma); 512 if (err) 513 return (NULL); 514 om = KERNADDR(&dma, OHCI_SED_SIZE * OHCI_SED_CHUNK); 515 om->om_top = KERNADDR(&dma, 0); 516 om->om_topdma = DMAADDR(&dma, 0); 517 om->om_dma = dma; 518 SIMPLEQ_INSERT_HEAD(&sc->sc_sed_chunks, om, om_next); 519 for(i = 0; i < OHCI_SED_CHUNK; i++) { 520 offs = i * OHCI_SED_SIZE; 521 sed = KERNADDR(&dma, offs); 522 sed->oe_mdesc = om; 523 sed->next = sc->sc_freeeds; 524 sc->sc_freeeds = sed; 525 } 526 } 527 sed = sc->sc_freeeds; 528 sc->sc_freeeds = sed->next; 529 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 530 sed->next = 0; 531 return (sed); 532 } 533 534 void 535 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 536 { 537 sed->next = sc->sc_freeeds; 538 sc->sc_freeeds = sed; 539 } 540 541 Static usbd_status 542 ohci_grow_std(ohci_softc_t *sc) 543 { 544 usb_dma_t dma; 545 struct ohci_mem_desc *om; 546 ohci_soft_td_t *std; 547 usbd_status err; 548 int i, s, offs; 549 550 DPRINTFN(2, ("ohci_grow_std: allocating chunk\n")); 551 err = usb_allocmem(&sc->sc_dmatag, 552 OHCI_STD_SIZE*OHCI_STD_CHUNK + sizeof(struct ohci_mem_desc), 553 OHCI_TD_ALIGN, &dma); 554 if (err) 555 return (err); 556 om = KERNADDR(&dma, OHCI_STD_SIZE * OHCI_STD_CHUNK); 557 om->om_top = KERNADDR(&dma, 0); 558 om->om_topdma = DMAADDR(&dma, 0); 559 om->om_dma = dma; 560 s = splusb(); 561 SIMPLEQ_INSERT_HEAD(&sc->sc_std_chunks, om, om_next); 562 for(i = 0; i < OHCI_STD_CHUNK; i++) { 563 offs = i * OHCI_STD_SIZE; 564 std = KERNADDR(&dma, offs); 565 std->ot_mdesc = om; 566 std->nexttd = sc->sc_freetds; 567 std->ad.aux_len = 0; 568 sc->sc_freetds = std; 569 sc->sc_nfreetds++; 570 } 571 splx(s); 572 573 return (USBD_NORMAL_COMPLETION); 574 } 575 576 ohci_soft_td_t * 577 ohci_alloc_std(ohci_softc_t *sc) 578 { 579 ohci_soft_td_t *std; 580 int s; 581 582 s = splusb(); 583 584 #ifdef DIAGNOSTIC 585 if (sc->sc_freetds == NULL) 586 panic("ohci_alloc_std: %d", sc->sc_nfreetds); 587 #endif 588 std = sc->sc_freetds; 589 sc->sc_freetds = std->nexttd; 590 splx(s); 591 memset(&std->td, 0, sizeof(ohci_td_t)); 592 std->nexttd = NULL; 593 std->xfer = NULL; 594 std->flags = 0; 595 596 return (std); 597 } 598 599 Static ohci_soft_td_t * 600 ohci_alloc_std_norsv(ohci_softc_t *sc) 601 { 602 int s; 603 604 s = splusb(); 605 if (sc->sc_nfreetds < 1) 606 if (ohci_grow_std(sc)) 607 return (NULL); 608 sc->sc_nfreetds--; 609 splx(s); 610 return (ohci_alloc_std(sc)); 611 } 612 613 void 614 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 615 { 616 int s; 617 618 s = splusb(); 619 std->flags = OHCI_TD_FREE; 620 std->nexttd = sc->sc_freetds; 621 sc->sc_freetds = std; 622 splx(s); 623 } 624 625 Static void 626 ohci_free_std_norsv(ohci_softc_t *sc, ohci_soft_td_t *std) 627 { 628 int s; 629 630 ohci_free_std(sc, std); 631 s = splusb(); 632 sc->sc_nfreetds++; 633 splx(s); 634 } 635 636 usbd_status 637 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 638 int alen, int rd, usbd_xfer_handle xfer, 639 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 640 { 641 ohci_soft_td_t *next, *cur, *end; 642 ohci_physaddr_t tddma, segdmaadr, dmaend; 643 u_int32_t tdflags; 644 int len, maxp, curlen, seg, seglen, seglen1; 645 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 646 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 647 int nsegs = USB_BUFFER_NSEGS(ub); 648 u_int16_t flags = xfer->flags; 649 usb_endpoint_descriptor_t *ed; 650 #if 1 651 int needaux; 652 union usb_bufptr bufptr; 653 bus_addr_t auxdma; 654 #endif 655 656 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 657 658 len = alen; 659 cur = sp; 660 end = NULL; 661 662 ed = opipe->pipe.endpoint->edesc; 663 maxp = UE_MAXPKTSZ(ed); 664 tdflags = HTOO32( 665 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 666 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 667 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_SET_DI(6)); 668 #if 1 669 /* 670 * aux memory is possibly required if 671 * buffer has more than one segments, 672 * the transfer direction is OUT, 673 * and 674 * buffer is an mbuf chain, or 675 * buffer is not maxp aligned 676 */ 677 needaux = 678 nsegs > 1 && 679 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 680 ((xfer->rqflags & URQ_DEV_MAP_MBUF) || 681 (maxp & (maxp - 1)) != 0 /* maxp is not a power of 2 */ || 682 (segs[0].ds_addr & (maxp - 1)) != 0 /* buffer is unaligned */); 683 684 if (needaux) { 685 usb_bufptr_init(&bufptr, xfer); 686 } 687 #endif 688 689 seg = 0; 690 seglen = 0; 691 segdmaadr = 0; /* XXX -Wuninitialized */ 692 while (len > 0) { 693 /* sync last entry */ 694 if (end) 695 OHCI_STD_SYNC(sc, end, 696 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 697 698 next = ohci_alloc_std(sc); 699 if (next == NULL) 700 goto nomem; 701 702 /* 703 * The OHCI hardware can handle at most one 4K crossing. 704 * The OHCI spec says: If during the data transfer the buffer 705 * address contained in the HC's working copy of 706 * CurrentBufferPointer crosses a 4K boundary, the upper 20 707 * bits of Buffer End are copied to the working value of 708 * CurrentBufferPointer causing the next buffer address to 709 * be the 0th byte in the same 4K page that contains the 710 * last byte of the buffer (the 4K boundary crossing may 711 * occur within a data packet transfer.) 712 */ 713 714 /* 715 * 1. skip handled segments 716 * 2. gather segments that are continuous in DMA address 717 * (Does this make any sense?) 718 */ 719 if (seglen <= 0) { 720 USB_KASSERT2(seg < nsegs, 721 ("ohci_alloc_std_chain: overrun")); 722 do { 723 seglen1 = seglen; 724 seglen += segs[seg].ds_len; 725 if (seglen1 <= 0 && seglen > 0) 726 segdmaadr = segs[seg].ds_addr - seglen1; 727 } while (++seg < nsegs && (seglen <= 0 || 728 segdmaadr + seglen == segs[seg].ds_addr)); 729 730 if (seglen > len) 731 seglen = len; 732 } 733 734 #if 1 735 if (needaux && seglen < len && seglen < maxp) { 736 /* need aux -- a packet is not contiguous */ 737 curlen = len < maxp ? len : maxp; 738 USB_KASSERT(seglen < curlen); 739 auxdma = ohci_aux_dma_alloc(&OXFER(xfer)->aux, &bufptr, 740 curlen, &cur->ad); 741 742 /* prepare aux DMA */ 743 usb_bufptr_wr(&bufptr, cur->ad.aux_kern, 744 curlen, xfer->rqflags & URQ_DEV_MAP_MBUF); 745 cur->td.td_cbp = HTOO32(auxdma); 746 cur->td.td_be = HTOO32(auxdma + curlen - 1); 747 748 /* handled segments will be skipped above */ 749 } else { 750 #ifdef DIAGNOSTIC 751 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 752 USB_KASSERT(seglen >= maxp || seglen >= len); 753 #endif 754 #endif 755 curlen = seglen; 756 dmaend = segdmaadr + curlen; 757 if ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) == 0) 758 dmaend--; 759 dmaend = OHCI_PAGE(dmaend); 760 761 if (OHCI_PAGE(segdmaadr) != dmaend && 762 OHCI_PAGE(segdmaadr) + OHCI_PAGE_SIZE != dmaend) { 763 /* must use multiple TDs, fill as much as possible. */ 764 curlen = 2 * OHCI_PAGE_SIZE - 765 (segdmaadr & (OHCI_PAGE_SIZE-1)); 766 767 if (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) 768 curlen--; 769 } 770 771 /* the length must be a multiple of the max size */ 772 if (curlen < len) 773 curlen -= curlen % maxp; 774 USB_KASSERT(curlen); 775 USB_KASSERT2(curlen <= seglen, 776 ("ohci_alloc_std_chain: curlen %d > seglen %d", 777 curlen, len)); 778 779 DPRINTFN(4,("ohci_alloc_std_chain: segdmaadr=0x%08x " 780 "dmaend=0x%08x len=%d seglen=%d curlen=%d\n", 781 segdmaadr, segdmaadr + curlen - 1, 782 len, seglen, curlen)); 783 cur->td.td_cbp = HTOO32(segdmaadr); 784 cur->td.td_be = HTOO32(segdmaadr + curlen - 1); 785 } 786 len -= curlen; 787 788 cur->td.td_flags = tdflags; 789 cur->nexttd = next; 790 tddma = OHCI_STD_DMAADDR(next); 791 cur->td.td_nexttd = HTOO32(tddma); 792 cur->len = curlen; 793 cur->flags = OHCI_ADD_LEN; 794 cur->xfer = xfer; 795 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x", 796 O32TOH(cur->td.td_cbp), O32TOH(cur->td.td_be))); 797 seglen -= curlen; 798 segdmaadr += curlen; 799 DPRINTFN(10,("%s\n", seglen < 0 ? " (aux)" : "")); 800 801 if (needaux) 802 usb_bufptr_advance(&bufptr, curlen, 803 xfer->rqflags & URQ_DEV_MAP_MBUF); 804 805 end = cur; 806 cur = next; 807 } 808 if (((flags & USBD_FORCE_SHORT_XFER) || alen == 0) && 809 alen % maxp == 0) { 810 if (end) 811 OHCI_STD_SYNC(sc, end, 812 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 813 814 /* Force a 0 length transfer at the end. */ 815 next = ohci_alloc_std(sc); 816 if (next == NULL) 817 goto nomem; 818 819 cur->td.td_flags = tdflags; 820 cur->td.td_cbp = 0; /* indicate 0 length packet */ 821 cur->nexttd = next; 822 tddma = OHCI_STD_DMAADDR(next); 823 cur->td.td_nexttd = HTOO32(tddma); 824 cur->td.td_be = ~0; 825 cur->len = 0; 826 cur->flags = 0; 827 cur->xfer = xfer; 828 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 829 end = cur; 830 } 831 *ep = end; 832 833 if (needaux) 834 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, BUS_DMASYNC_PREWRITE); 835 836 return (USBD_NORMAL_COMPLETION); 837 838 nomem: 839 /* free chain */ 840 if (end) 841 ohci_free_std_chain(sc, sp->nexttd, end); 842 return (USBD_NOMEM); 843 } 844 845 Static void 846 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 847 ohci_soft_td_t *stdend) 848 { 849 ohci_soft_td_t *p; 850 851 for (; std != stdend; std = p) { 852 p = std->nexttd; 853 ohci_free_std(sc, std); 854 } 855 ohci_free_std(sc, stdend); 856 } 857 858 Static usbd_status 859 ohci_grow_sitd(ohci_softc_t *sc) 860 { 861 usb_dma_t dma; 862 struct ohci_mem_desc *om; 863 ohci_soft_itd_t *sitd; 864 usbd_status err; 865 int i, s, offs; 866 867 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 868 err = usb_allocmem(&sc->sc_dmatag, 869 OHCI_SITD_SIZE*OHCI_SITD_CHUNK + sizeof(struct ohci_mem_desc), 870 OHCI_ITD_ALIGN, &dma); 871 if (err) 872 return (err); 873 om = KERNADDR(&dma, OHCI_SITD_SIZE * OHCI_SITD_CHUNK); 874 om->om_top = KERNADDR(&dma, 0); 875 om->om_topdma = DMAADDR(&dma, 0); 876 om->om_dma = dma; 877 s = splusb(); 878 SIMPLEQ_INSERT_HEAD(&sc->sc_sitd_chunks, om, om_next); 879 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 880 offs = i * OHCI_SITD_SIZE; 881 sitd = KERNADDR(&dma, offs); 882 sitd->oit_mdesc = om; 883 sitd->nextitd = sc->sc_freeitds; 884 sitd->ad.aux_len = 0; 885 sc->sc_freeitds = sitd; 886 sc->sc_nfreeitds++; 887 } 888 splx(s); 889 890 return (USBD_NORMAL_COMPLETION); 891 } 892 893 ohci_soft_itd_t * 894 ohci_alloc_sitd(ohci_softc_t *sc) 895 { 896 ohci_soft_itd_t *sitd; 897 int s; 898 899 #ifdef DIAGNOSTIC 900 if (sc->sc_freeitds == NULL) 901 panic("ohci_alloc_sitd: %d", sc->sc_nfreeitds); 902 #endif 903 904 s = splusb(); 905 sitd = sc->sc_freeitds; 906 sc->sc_freeitds = sitd->nextitd; 907 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 908 sitd->nextitd = NULL; 909 sitd->xfer = NULL; 910 sitd->flags = 0; 911 splx(s); 912 913 #ifdef DIAGNOSTIC 914 sitd->isdone = 0; 915 #endif 916 917 return (sitd); 918 } 919 920 Static ohci_soft_itd_t * 921 ohci_alloc_sitd_norsv(ohci_softc_t *sc) 922 { 923 int s; 924 925 s = splusb(); 926 if (sc->sc_nfreeitds < 1) 927 if (ohci_grow_sitd(sc)) 928 return (NULL); 929 sc->sc_nfreeitds--; 930 splx(s); 931 return (ohci_alloc_sitd(sc)); 932 } 933 934 void 935 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 936 { 937 int s; 938 939 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 940 941 #ifdef DIAGNOSTIC 942 if (!sitd->isdone) { 943 panic("ohci_free_sitd: sitd=%p not done", sitd); 944 return; 945 } 946 /* Warn double free */ 947 sitd->isdone = 0; 948 #endif 949 950 s = splusb(); 951 sitd->flags = OHCI_ITD_FREE; 952 sitd->nextitd = sc->sc_freeitds; 953 sc->sc_freeitds = sitd; 954 splx(s); 955 } 956 957 Static void 958 ohci_free_sitd_norsv(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 959 { 960 int s; 961 962 ohci_free_sitd(sc, sitd); 963 s = splusb(); 964 sc->sc_nfreeitds++; 965 splx(s); 966 } 967 968 usbd_status 969 ohci_init(ohci_softc_t *sc) 970 { 971 ohci_soft_ed_t *sed, *psed; 972 ohci_physaddr_t eddma; 973 usbd_status err; 974 int i; 975 u_int32_t rev; 976 977 DPRINTF(("ohci_init: start\n")); 978 #if defined(__OpenBSD__) 979 printf(","); 980 #else 981 printf("%s:", USBDEVNAME(sc->sc_bus.bdev)); 982 #endif 983 rev = OREAD4(sc, OHCI_REVISION); 984 printf(" OHCI version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 985 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 986 987 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 988 printf("%s: unsupported OHCI revision\n", 989 USBDEVNAME(sc->sc_bus.bdev)); 990 sc->sc_bus.usbrev = USBREV_UNKNOWN; 991 return (USBD_INVAL); 992 } 993 sc->sc_bus.usbrev = USBREV_1_0; 994 995 SIMPLEQ_INIT(&sc->sc_free_xfers); 996 SIMPLEQ_INIT(&sc->sc_sed_chunks); 997 SIMPLEQ_INIT(&sc->sc_std_chunks); 998 SIMPLEQ_INIT(&sc->sc_sitd_chunks); 999 1000 usb_dma_tag_init(&sc->sc_dmatag); 1001 1002 /* XXX determine alignment by R/W */ 1003 /* Allocate the HCCA area. */ 1004 err = usb_allocmem(&sc->sc_dmatag, OHCI_HCCA_SIZE, 1005 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 1006 if (err) 1007 goto bad1; 1008 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 1009 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 1010 1011 sc->sc_eintrs = OHCI_NORMAL_INTRS; 1012 1013 /* Allocate dummy ED that starts the control list. */ 1014 sc->sc_ctrl_head = ohci_alloc_sed(sc); 1015 if (sc->sc_ctrl_head == NULL) { 1016 err = USBD_NOMEM; 1017 goto bad2; 1018 } 1019 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1020 1021 /* Allocate dummy ED that starts the bulk list. */ 1022 sc->sc_bulk_head = ohci_alloc_sed(sc); 1023 if (sc->sc_bulk_head == NULL) { 1024 err = USBD_NOMEM; 1025 goto bad3; 1026 } 1027 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1028 1029 /* Allocate dummy ED that starts the isochronous list. */ 1030 sc->sc_isoc_head = ohci_alloc_sed(sc); 1031 if (sc->sc_isoc_head == NULL) { 1032 err = USBD_NOMEM; 1033 goto bad3; 1034 } 1035 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1036 1037 /* Allocate all the dummy EDs that make up the interrupt tree. */ 1038 for (i = 0; i < OHCI_NO_EDS; i++) { 1039 sed = ohci_alloc_sed(sc); 1040 if (sed == NULL) { 1041 while (--i >= 0) 1042 ohci_free_sed(sc, sc->sc_eds[i]); 1043 err = USBD_NOMEM; 1044 goto bad3; 1045 } 1046 /* All ED fields are set to 0. */ 1047 sc->sc_eds[i] = sed; 1048 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1049 if (i != 0) 1050 psed = sc->sc_eds[(i-1) / 2]; 1051 else 1052 psed = sc->sc_isoc_head; 1053 sed->next = psed; 1054 eddma = OHCI_SED_DMAADDR(psed); 1055 sed->ed.ed_nexted = HTOO32(eddma); 1056 } 1057 /* 1058 * Fill HCCA interrupt table. The bit reversal is to get 1059 * the tree set up properly to spread the interrupts. 1060 */ 1061 for (i = 0; i < OHCI_NO_INTRS; i++) { 1062 eddma = OHCI_SED_DMAADDR(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]); 1063 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = HTOO32(eddma); 1064 } 1065 USB_MEM_SYNC(&sc->sc_dmatag, &sc->sc_hccadma, 1066 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1067 1068 #ifdef USB_DEBUG 1069 if (ohcidebug > 15) { 1070 for (i = 0; i < OHCI_NO_EDS; i++) { 1071 printf("ed#%d ", i); 1072 ohci_dump_ed(sc, sc->sc_eds[i]); 1073 } 1074 printf("iso "); 1075 ohci_dump_ed(sc, sc->sc_isoc_head); 1076 } 1077 #endif 1078 1079 err = ohci_controller_init(sc); 1080 if (err != USBD_NORMAL_COMPLETION) 1081 goto bad3; 1082 1083 /* Set up the bus struct. */ 1084 sc->sc_bus.methods = &ohci_bus_methods; 1085 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 1086 1087 #if defined(__NetBSD__) || defined(__OpenBSD__) 1088 sc->sc_control = sc->sc_intre = 0; 1089 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 1090 ohci_power, sc); 1091 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 1092 #endif 1093 1094 usb_callout_init(sc->sc_tmo_rhsc); 1095 1096 /* Finally, turn on interrupts. */ 1097 DPRINTFN(1,("ohci_init: enabling\n")); 1098 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1099 1100 return (USBD_NORMAL_COMPLETION); 1101 1102 bad3: 1103 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 1104 bad2: 1105 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 1106 bad1: 1107 usb_dma_tag_finish(&sc->sc_dmatag); 1108 return (err); 1109 } 1110 1111 Static usbd_status 1112 ohci_controller_init(ohci_softc_t *sc) 1113 { 1114 int i; 1115 u_int32_t s, ctl, rwc, ival, hcr, fm, per, desca, descb; 1116 1117 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 1118 ctl = OREAD4(sc, OHCI_CONTROL); 1119 rwc = ctl & OHCI_RWC; 1120 fm = OREAD4(sc, OHCI_FM_INTERVAL); 1121 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1122 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1123 1124 /* Determine in what context we are running. */ 1125 if (ctl & OHCI_IR) { 1126 /* SMM active, request change */ 1127 DPRINTF(("ohci_init: SMM active, request owner change\n")); 1128 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 1129 (OHCI_OC | OHCI_MIE)) 1130 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 1131 s = OREAD4(sc, OHCI_COMMAND_STATUS); 1132 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 1133 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 1134 usb_delay_ms(&sc->sc_bus, 1); 1135 ctl = OREAD4(sc, OHCI_CONTROL); 1136 } 1137 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 1138 if ((ctl & OHCI_IR) == 0) { 1139 printf("%s: SMM does not respond, resetting\n", 1140 USBDEVNAME(sc->sc_bus.bdev)); 1141 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1142 goto reset; 1143 } 1144 #if 0 1145 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 1146 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 1147 /* BIOS started controller. */ 1148 DPRINTF(("ohci_init: BIOS active\n")); 1149 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 1150 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 1151 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1152 } 1153 #endif 1154 } else { 1155 DPRINTF(("ohci_init: cold started\n")); 1156 reset: 1157 /* Controller was cold started. */ 1158 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1159 } 1160 1161 /* 1162 * This reset should not be necessary according to the OHCI spec, but 1163 * without it some controllers do not start. 1164 */ 1165 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 1166 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1167 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1168 1169 /* We now own the host controller and the bus has been reset. */ 1170 1171 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1172 /* Nominal time for a reset is 10 us. */ 1173 for (i = 0; i < 10; i++) { 1174 delay(10); 1175 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1176 if (!hcr) 1177 break; 1178 } 1179 if (hcr) { 1180 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 1181 return (USBD_IOERROR); 1182 } 1183 #ifdef USB_DEBUG 1184 if (ohcidebug > 15) 1185 ohci_dumpregs(sc); 1186 #endif 1187 1188 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1189 1190 /* Set up HC registers. */ 1191 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1192 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_ctrl_head)); 1193 OWRITE4(sc, OHCI_BULK_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_bulk_head)); 1194 /* disable all interrupts and then switch on all desired interrupts */ 1195 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1196 /* switch on desired functional features */ 1197 ctl = OREAD4(sc, OHCI_CONTROL); 1198 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1199 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1200 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1201 /* And finally start it! */ 1202 OWRITE4(sc, OHCI_CONTROL, ctl); 1203 1204 /* 1205 * The controller is now OPERATIONAL. Set a some final 1206 * registers that should be set earlier, but that the 1207 * controller ignores when in the SUSPEND state. 1208 */ 1209 ival = OHCI_GET_IVAL(fm); 1210 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1211 fm |= OHCI_FSMPS(ival) | ival; 1212 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1213 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1214 OWRITE4(sc, OHCI_PERIODIC_START, per); 1215 1216 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1217 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1218 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1219 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1220 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1221 1222 /* 1223 * The AMD756 requires a delay before re-reading the register, 1224 * otherwise it will occasionally report 0 ports. 1225 */ 1226 sc->sc_noport = 0; 1227 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1228 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1229 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1230 } 1231 1232 #ifdef USB_DEBUG 1233 if (ohcidebug > 5) 1234 ohci_dumpregs(sc); 1235 #endif 1236 return (USBD_NORMAL_COMPLETION); 1237 } 1238 1239 /* 1240 * Allocate a physically contiguous buffer to handle cases where OHCI 1241 * cannot handle a packet because it is not physically contiguous. 1242 */ 1243 Static void 1244 ohci_aux_mem_init(struct ohci_aux_mem *aux) 1245 { 1246 1247 aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0; 1248 } 1249 1250 Static usbd_status 1251 ohci_aux_mem_alloc(ohci_softc_t *sc, struct ohci_aux_mem *aux, 1252 int naux, int maxp) 1253 { 1254 int nchunk, i, j; 1255 usbd_status err; 1256 1257 USB_KASSERT(aux->aux_nchunk == 0); 1258 1259 nchunk = OHCI_NCHUNK(naux, maxp); 1260 for (i = 0; i < nchunk; i++) { 1261 err = usb_allocmem(&sc->sc_dmatag, OHCI_AUX_CHUNK_SIZE, 1262 OHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]); 1263 if (err) { 1264 for (j = 0; j < i; j++) 1265 usb_freemem(&sc->sc_dmatag, 1266 &aux->aux_chunk_dma[j]); 1267 return (err); 1268 } 1269 } 1270 1271 aux->aux_nchunk = nchunk; 1272 ohci_aux_mem_init(aux); 1273 1274 return (USBD_NORMAL_COMPLETION); 1275 } 1276 1277 Static void 1278 ohci_aux_mem_free(ohci_softc_t *sc, struct ohci_aux_mem *aux) 1279 { 1280 int i; 1281 1282 for (i = 0; i < aux->aux_nchunk; i++) 1283 usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]); 1284 1285 aux->aux_nchunk = 0; 1286 } 1287 1288 Static bus_addr_t 1289 ohci_aux_dma_alloc(struct ohci_aux_mem *aux, 1290 const union usb_bufptr *bufptr, int len, 1291 struct usb_aux_desc *ad) 1292 { 1293 bus_addr_t auxdma; 1294 1295 if (aux->aux_chunkoff + len > OHCI_AUX_CHUNK_SIZE) { 1296 aux->aux_curchunk++; 1297 aux->aux_chunkoff = 0; 1298 } 1299 USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk); 1300 1301 auxdma = 1302 DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1303 ad->aux_kern = 1304 KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1305 ad->aux_ptr = *bufptr; 1306 ad->aux_len = len; 1307 1308 aux->aux_chunkoff += len; 1309 aux->aux_naux++; 1310 1311 return auxdma; 1312 } 1313 1314 Static void 1315 ohci_aux_dma_complete(struct usb_aux_desc *ad, struct ohci_aux_mem *aux, 1316 int is_mbuf, int isread) 1317 { 1318 1319 if (isread) { 1320 usb_bufptr_rd(&ad->aux_ptr, ad->aux_kern, ad->aux_len, 1321 is_mbuf); 1322 } 1323 ad->aux_len = 0; 1324 USB_KASSERT(aux->aux_naux > 0); 1325 if (--aux->aux_naux == 0) 1326 ohci_aux_mem_init(aux); 1327 } 1328 1329 Static void 1330 ohci_aux_dma_sync(ohci_softc_t *sc, struct ohci_aux_mem *aux, int op) 1331 { 1332 int i; 1333 1334 for (i = 0; i < aux->aux_curchunk; i++) 1335 USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op); 1336 if (aux->aux_chunkoff) 1337 USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i], 1338 0, aux->aux_chunkoff, op); 1339 } 1340 1341 Static usbd_status 1342 ohci_prealloc(struct ohci_softc *sc, struct ohci_xfer *oxfer, 1343 size_t bufsize, int nseg) 1344 { 1345 usb_endpoint_descriptor_t *ed; 1346 int maxseg, maxp, naux; 1347 int seglen, ntd; 1348 int s; 1349 int err; 1350 1351 ed = oxfer->xfer.pipe->endpoint->edesc; 1352 maxp = UE_MAXPKTSZ(ed); 1353 1354 if (maxp == 0) 1355 return (USBD_INVAL); 1356 1357 /* (over) estimate needed number of TDs */ 1358 maxseg = (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) ? 4096 : 8192; 1359 seglen = maxseg - (maxseg % maxp); 1360 ntd = bufsize / seglen + nseg; 1361 1362 #if 1 1363 /* allocate aux buffer for non-isoc OUT or isoc transfer */ 1364 naux = 0; 1365 if (nseg > 1 && 1366 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS || 1367 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)) { 1368 /* estimate needed aux segments */ 1369 naux = nseg - 1; 1370 1371 /* pre-allocate aux memory */ 1372 err = ohci_aux_mem_alloc(sc, &oxfer->aux, naux, maxp); 1373 if (err) 1374 return err; 1375 1376 /* an aux segment will consume a TD */ 1377 ntd += naux; 1378 } 1379 #endif 1380 1381 s = splusb(); 1382 if ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) { 1383 /* pre-allocate ITDs */ 1384 while (sc->sc_nfreeitds < ntd) { 1385 DPRINTF(("%s: ohci_prealloc: need %d ITD (%d cur)\n", 1386 USBDEVNAME(sc->sc_bus.bdev), 1387 ntd, sc->sc_nfreeitds)); 1388 if ((err = ohci_grow_sitd(sc)) 1389 != USBD_NORMAL_COMPLETION) { 1390 splx(s); 1391 ohci_aux_mem_free(sc, &oxfer->aux); 1392 return (err); 1393 } 1394 } 1395 sc->sc_nfreeitds -= ntd; 1396 } else { 1397 /* pre-allocate TDs */ 1398 while (sc->sc_nfreetds < ntd) { 1399 DPRINTF(("%s: ohci_prealloc: need %d TD (%d cur)\n", 1400 USBDEVNAME(sc->sc_bus.bdev), 1401 ntd, sc->sc_nfreetds)); 1402 if ((err = ohci_grow_std(sc)) 1403 != USBD_NORMAL_COMPLETION) { 1404 splx(s); 1405 ohci_aux_mem_free(sc, &oxfer->aux); 1406 return (err); 1407 } 1408 } 1409 sc->sc_nfreetds -= ntd; 1410 } 1411 splx(s); 1412 1413 oxfer->rsvd_tds = ntd; 1414 1415 return (USBD_NORMAL_COMPLETION); 1416 } 1417 1418 usbd_status 1419 ohci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1420 { 1421 struct ohci_softc *sc = (struct ohci_softc *)bus; 1422 struct ohci_xfer *oxfer = OXFER(xfer); 1423 usbd_status err; 1424 1425 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1426 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1427 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1428 (err = ohci_prealloc(sc, oxfer, size, 1429 USB_BUFFER_NSEGS(&oxfer->dmabuf))) 1430 != USBD_NORMAL_COMPLETION) { 1431 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1432 U_WAITOK); 1433 } 1434 } 1435 1436 return err; 1437 } 1438 1439 void 1440 ohci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1441 enum usbd_waitflg waitflg) 1442 { 1443 struct ohci_softc *sc = (struct ohci_softc *)bus; 1444 struct ohci_xfer *oxfer = OXFER(xfer); 1445 int s; 1446 1447 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, waitflg); 1448 1449 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1450 s = splusb(); 1451 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1452 UE_ISOCHRONOUS) { 1453 sc->sc_nfreeitds += oxfer->rsvd_tds; 1454 } else { 1455 sc->sc_nfreetds += oxfer->rsvd_tds; 1456 } 1457 splx(s); 1458 ohci_aux_mem_free(sc, &oxfer->aux); 1459 oxfer->rsvd_tds = 0; 1460 } 1461 } 1462 1463 Static usbd_status 1464 ohci_map_alloc(usbd_xfer_handle xfer) 1465 { 1466 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1467 struct ohci_xfer *oxfer = OXFER(xfer); 1468 usbd_status st; 1469 1470 st = usb_alloc_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1471 if (st) 1472 return st; 1473 1474 if ((st = ohci_prealloc(sc, oxfer, MAXPHYS, USB_DMA_NSEG))) { 1475 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1476 } 1477 1478 return st; 1479 } 1480 1481 Static void 1482 ohci_map_free(usbd_xfer_handle xfer) 1483 { 1484 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1485 struct ohci_xfer *oxfer = OXFER(xfer); 1486 int s; 1487 1488 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1489 1490 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1491 1492 s = splusb(); 1493 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1494 UE_ISOCHRONOUS) { 1495 sc->sc_nfreeitds += oxfer->rsvd_tds; 1496 } else { 1497 sc->sc_nfreetds += oxfer->rsvd_tds; 1498 } 1499 splx(s); 1500 ohci_aux_mem_free(sc, &oxfer->aux); 1501 oxfer->rsvd_tds = 0; 1502 } 1503 1504 Static void 1505 ohci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1506 { 1507 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1508 struct ohci_xfer *oxfer = OXFER(xfer); 1509 1510 usb_map_dma(&sc->sc_dmatag, &oxfer->dmabuf, buf, size); 1511 } 1512 1513 Static usbd_status 1514 ohci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1515 { 1516 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1517 struct ohci_xfer *oxfer = OXFER(xfer); 1518 1519 return (usb_map_mbuf_dma(&sc->sc_dmatag, &oxfer->dmabuf, chain)); 1520 } 1521 1522 Static void 1523 ohci_unmapm(usbd_xfer_handle xfer) 1524 { 1525 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1526 struct ohci_xfer *oxfer = OXFER(xfer); 1527 1528 usb_unmap_dma(&sc->sc_dmatag, &oxfer->dmabuf); 1529 } 1530 1531 usbd_xfer_handle 1532 ohci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1533 enum usbd_waitflg waitflg) 1534 { 1535 struct ohci_softc *sc = (struct ohci_softc *)bus; 1536 usbd_xfer_handle xfer; 1537 1538 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1539 if (xfer != NULL) { 1540 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1541 #ifdef DIAGNOSTIC 1542 if (xfer->busy_free != XFER_FREE) { 1543 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1544 xfer->busy_free); 1545 } 1546 #endif 1547 } else { 1548 xfer = malloc(sizeof(struct ohci_xfer), M_USB, 1549 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1550 } 1551 if (xfer != NULL) { 1552 memset(xfer, 0, sizeof (struct ohci_xfer)); 1553 usb_init_task(&OXFER(xfer)->abort_task, ohci_timeout_task, 1554 xfer); 1555 OXFER(xfer)->ohci_xfer_flags = 0; 1556 OXFER(xfer)->rsvd_tds = 0; 1557 #ifdef DIAGNOSTIC 1558 xfer->busy_free = XFER_BUSY; 1559 #endif 1560 } 1561 return (xfer); 1562 } 1563 1564 void 1565 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1566 { 1567 struct ohci_softc *sc = (struct ohci_softc *)bus; 1568 1569 #ifdef DIAGNOSTIC 1570 if (xfer->busy_free != XFER_BUSY) { 1571 #if 1 1572 panic("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1573 xfer->busy_free); 1574 #else 1575 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1576 xfer->busy_free); 1577 #endif 1578 } 1579 xfer->busy_free = XFER_FREE; 1580 #endif 1581 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1582 } 1583 1584 /* 1585 * Perform any OHCI-specific transfer completion operations, then 1586 * call usb_transfer_complete(). 1587 */ 1588 Static void 1589 ohci_transfer_complete(usbd_xfer_handle xfer, int clear_halt) 1590 { 1591 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1592 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1593 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 1594 ohci_soft_itd_t *sitd, *sitdnext; 1595 ohci_soft_td_t *std, *stdnext; 1596 ohci_physaddr_t dmaadr; 1597 int isread, is_mbuf; 1598 int s; 1599 1600 isread = usbd_xfer_isread(xfer); 1601 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 1602 1603 if (ub) 1604 usb_sync_buffer_dma(&sc->sc_dmatag, ub, 1605 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1606 1607 if (OXFER(xfer)->aux.aux_naux) { 1608 /* sync aux */ 1609 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, 1610 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1611 } 1612 1613 /* Copy back from any auxillary buffers after a read operation. */ 1614 if (xfer->hcpriv == NULL) { 1615 DPRINTFN(-1, ("ohci_transfer_complete: hcpriv == NULL\n")); 1616 } else if (xfer->nframes == 0) { 1617 /* Bulk/Interrupt transfer */ 1618 /* Remove all TDs belonging to this xfer. */ 1619 for (std = xfer->hcpriv; std->xfer == xfer; std = stdnext) { 1620 stdnext = std->nexttd; 1621 if (std->ad.aux_len) 1622 ohci_aux_dma_complete(&std->ad, 1623 &OXFER(xfer)->aux, is_mbuf, isread); 1624 ohci_free_std(sc, std); 1625 } 1626 if (clear_halt) { 1627 /* clear halt */ 1628 OHCI_SED_SYNC_POST(sc, opipe->sed); 1629 dmaadr = OHCI_STD_DMAADDR(std); 1630 opipe->sed->ed.ed_headp = HTOO32(dmaadr); 1631 OHCI_SED_SYNC2(sc, opipe->sed, 1632 offsetof(ohci_ed_t, ed_headp), 1633 sizeof(ohci_physaddr_t), 1634 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1635 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1636 } 1637 } else { 1638 /* Isoc transfer */ 1639 /* Remove all ITDs belonging to this xfer. */ 1640 for (sitd = xfer->hcpriv; sitd->xfer == xfer; 1641 sitd = sitdnext) { 1642 sitdnext = sitd->nextitd; 1643 if (sitd->ad.aux_len) 1644 ohci_aux_dma_complete(&sitd->ad, 1645 &OXFER(xfer)->aux, is_mbuf, isread); 1646 ohci_free_sitd(sc, sitd); 1647 } 1648 } 1649 1650 USB_KASSERT(OXFER(xfer)->aux.aux_naux == 0); 1651 xfer->hcpriv = NULL; 1652 1653 s = splusb(); 1654 usb_transfer_complete(xfer); 1655 splx(s); 1656 } 1657 1658 /* 1659 * Shut down the controller when the system is going down. 1660 */ 1661 void 1662 ohci_shutdown(void *v) 1663 { 1664 ohci_softc_t *sc = v; 1665 1666 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1667 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1668 } 1669 1670 /* 1671 * Handle suspend/resume. 1672 * 1673 * We need to switch to polling mode here, because this routine is 1674 * called from an interupt context. This is all right since we 1675 * are almost suspended anyway. 1676 */ 1677 void 1678 ohci_power(int why, void *v) 1679 { 1680 ohci_softc_t *sc = v; 1681 u_int32_t ctl; 1682 int s; 1683 1684 #ifdef USB_DEBUG 1685 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 1686 ohci_dumpregs(sc); 1687 #endif 1688 1689 s = splhardusb(); 1690 switch (why) { 1691 USB_PWR_CASE_SUSPEND: 1692 sc->sc_bus.use_polling++; 1693 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1694 if (sc->sc_control == 0) { 1695 /* 1696 * Preserve register values, in case that APM BIOS 1697 * does not recover them. 1698 */ 1699 sc->sc_control = ctl; 1700 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 1701 } 1702 ctl |= OHCI_HCFS_SUSPEND; 1703 OWRITE4(sc, OHCI_CONTROL, ctl); 1704 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1705 sc->sc_bus.use_polling--; 1706 break; 1707 1708 USB_PWR_CASE_RESUME: 1709 sc->sc_bus.use_polling++; 1710 1711 /* Some broken BIOSes never initialize Controller chip */ 1712 ohci_controller_init(sc); 1713 1714 if (sc->sc_intre) 1715 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 1716 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 1717 if (sc->sc_control) 1718 ctl = sc->sc_control; 1719 else 1720 ctl = OREAD4(sc, OHCI_CONTROL); 1721 ctl |= OHCI_HCFS_RESUME; 1722 OWRITE4(sc, OHCI_CONTROL, ctl); 1723 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1724 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1725 OWRITE4(sc, OHCI_CONTROL, ctl); 1726 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1727 sc->sc_control = sc->sc_intre = 0; 1728 sc->sc_bus.use_polling--; 1729 break; 1730 1731 default: 1732 break; 1733 } 1734 splx(s); 1735 } 1736 1737 #ifdef USB_DEBUG 1738 void 1739 ohci_dumpregs(ohci_softc_t *sc) 1740 { 1741 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1742 OREAD4(sc, OHCI_REVISION), 1743 OREAD4(sc, OHCI_CONTROL), 1744 OREAD4(sc, OHCI_COMMAND_STATUS))); 1745 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1746 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1747 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1748 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1749 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1750 OREAD4(sc, OHCI_HCCA), 1751 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1752 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1753 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1754 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1755 OREAD4(sc, OHCI_BULK_HEAD_ED), 1756 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1757 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1758 OREAD4(sc, OHCI_DONE_HEAD), 1759 OREAD4(sc, OHCI_FM_INTERVAL), 1760 OREAD4(sc, OHCI_FM_REMAINING))); 1761 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1762 OREAD4(sc, OHCI_FM_NUMBER), 1763 OREAD4(sc, OHCI_PERIODIC_START), 1764 OREAD4(sc, OHCI_LS_THRESHOLD))); 1765 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1766 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1767 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1768 OREAD4(sc, OHCI_RH_STATUS))); 1769 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1770 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1771 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1772 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1773 O32TOH(sc->sc_hcca->hcca_frame_number), 1774 O32TOH(sc->sc_hcca->hcca_done_head))); 1775 } 1776 #endif 1777 1778 Static int ohci_intr1(ohci_softc_t *); 1779 1780 #if defined(__NetBSD__) || defined(__OpenBSD__) 1781 int 1782 #elif defined(__FreeBSD__) 1783 void 1784 #endif 1785 ohci_intr(void *p) 1786 { 1787 ohci_softc_t *sc = p; 1788 1789 if (sc == NULL || sc->sc_dying) 1790 #if defined(__NetBSD__) || defined(__OpenBSD__) 1791 return (0); 1792 #elif defined(__FreeBSD__) 1793 return; 1794 #endif 1795 1796 /* If we get an interrupt while polling, then just ignore it. */ 1797 if (sc->sc_bus.use_polling) { 1798 #ifdef DIAGNOSTIC 1799 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1800 #endif 1801 /* for level triggered intrs, should do something to ack */ 1802 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1803 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1804 1805 #if defined(__NetBSD__) || defined(__OpenBSD__) 1806 return (0); 1807 #elif defined(__FreeBSD__) 1808 return; 1809 #endif 1810 } 1811 1812 #if defined(__NetBSD__) || defined(__OpenBSD__) 1813 return 1814 #endif 1815 ohci_intr1(sc); 1816 } 1817 1818 Static int 1819 ohci_intr1(ohci_softc_t *sc) 1820 { 1821 u_int32_t intrs, eintrs; 1822 1823 DPRINTFN(14,("ohci_intr1: enter\n")); 1824 1825 /* In case the interrupt occurs before initialization has completed. */ 1826 if (sc == NULL || sc->sc_hcca == NULL) { 1827 #ifdef DIAGNOSTIC 1828 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1829 #endif 1830 return (0); 1831 } 1832 1833 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1834 1835 if (intrs == 0) /* nothing to be done (PCI shared interrupt) */ 1836 return (0); 1837 1838 /* Acknowledge */ 1839 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1840 1841 eintrs = intrs & sc->sc_eintrs; 1842 if (!eintrs) 1843 return (0); 1844 1845 sc->sc_bus.intr_context++; 1846 sc->sc_bus.no_intrs++; 1847 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1848 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1849 (u_int)eintrs)); 1850 1851 if (eintrs & OHCI_SO) { 1852 sc->sc_overrun_cnt++; 1853 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1854 printf("%s: %u scheduling overruns\n", 1855 USBDEVNAME(sc->sc_bus.bdev), sc->sc_overrun_cnt); 1856 sc->sc_overrun_cnt = 0; 1857 } 1858 /* XXX do what */ 1859 eintrs &= ~OHCI_SO; 1860 } 1861 if (eintrs & OHCI_WDH) { 1862 /* 1863 * We block the interrupt below, and reenable it later from 1864 * ohci_softintr(). 1865 */ 1866 usb_schedsoftintr(&sc->sc_bus); 1867 } 1868 if (eintrs & OHCI_RD) { 1869 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 1870 /* XXX process resume detect */ 1871 } 1872 if (eintrs & OHCI_UE) { 1873 printf("%s: unrecoverable error, controller halted\n", 1874 USBDEVNAME(sc->sc_bus.bdev)); 1875 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1876 /* XXX what else */ 1877 } 1878 if (eintrs & OHCI_RHSC) { 1879 /* 1880 * We block the interrupt below, and reenable it later from 1881 * a timeout. 1882 */ 1883 ohci_rhsc(sc, sc->sc_intrxfer); 1884 /* Do not allow RHSC interrupts > 1 per second */ 1885 usb_callout(sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1886 } 1887 1888 sc->sc_bus.intr_context--; 1889 1890 if (eintrs != 0) { 1891 /* Block unprocessed interrupts. */ 1892 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1893 sc->sc_eintrs &= ~eintrs; 1894 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1895 USBDEVNAME(sc->sc_bus.bdev), eintrs)); 1896 } 1897 1898 return (1); 1899 } 1900 1901 void 1902 ohci_rhsc_enable(void *v_sc) 1903 { 1904 ohci_softc_t *sc = v_sc; 1905 int s; 1906 1907 s = splhardusb(); 1908 sc->sc_eintrs |= OHCI_RHSC; 1909 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1910 splx(s); 1911 } 1912 1913 #ifdef USB_DEBUG 1914 const char *ohci_cc_strs[] = { 1915 "NO_ERROR", 1916 "CRC", 1917 "BIT_STUFFING", 1918 "DATA_TOGGLE_MISMATCH", 1919 "STALL", 1920 "DEVICE_NOT_RESPONDING", 1921 "PID_CHECK_FAILURE", 1922 "UNEXPECTED_PID", 1923 "DATA_OVERRUN", 1924 "DATA_UNDERRUN", 1925 "BUFFER_OVERRUN", 1926 "BUFFER_UNDERRUN", 1927 "reserved", 1928 "reserved", 1929 "NOT_ACCESSED", 1930 "NOT_ACCESSED" 1931 }; 1932 #endif 1933 1934 void 1935 ohci_softintr(void *v) 1936 { 1937 ohci_softc_t *sc = v; 1938 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1939 ohci_soft_td_t *std, *sdone, *stdnext, *p; 1940 usbd_xfer_handle xfer; 1941 struct ohci_pipe *opipe; 1942 int len, cc, s; 1943 int i, j, iframes; 1944 ohci_physaddr_t done; 1945 #if 0 1946 int isread, is_mbuf; 1947 #endif 1948 1949 DPRINTFN(10,("ohci_softintr: enter\n")); 1950 1951 sc->sc_bus.intr_context++; 1952 1953 s = splhardusb(); 1954 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 1955 offsetof(struct ohci_hcca, hcca_done_head), 1956 sizeof(sc->sc_hcca->hcca_done_head), 1957 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1958 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1959 sc->sc_hcca->hcca_done_head = 0; 1960 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 1961 offsetof(struct ohci_hcca, hcca_done_head), 1962 sizeof(sc->sc_hcca->hcca_done_head), 1963 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1964 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1965 sc->sc_eintrs |= OHCI_WDH; 1966 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1967 splx(s); 1968 1969 /* Reverse the done list. */ 1970 for (sdone = NULL, sidone = NULL; done != 0; ) { 1971 std = ohci_find_td(sc, done); 1972 if (std != NULL) { 1973 OHCI_STD_SYNC(sc, std, 1974 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1975 std->dnext = sdone; 1976 done = O32TOH(std->td.td_nexttd); 1977 sdone = std; 1978 DPRINTFN(10,("add TD %p\n", std)); 1979 continue; 1980 } 1981 sitd = ohci_find_itd(sc, done); 1982 if (sitd != NULL) { 1983 OHCI_SITD_SYNC(sc, sitd, 1984 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1985 sitd->dnext = sidone; 1986 done = O32TOH(sitd->itd.itd_nextitd); 1987 sidone = sitd; 1988 DPRINTFN(5,("add ITD %p\n", sitd)); 1989 continue; 1990 } 1991 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1992 } 1993 1994 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1995 1996 #ifdef USB_DEBUG 1997 if (ohcidebug > 10) { 1998 DPRINTF(("ohci_process_done: TD done:\n")); 1999 ohci_dump_tds(sc, sdone); 2000 } 2001 #endif 2002 2003 for (std = sdone; std; std = stdnext) { 2004 xfer = std->xfer; 2005 stdnext = std->dnext; 2006 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 2007 std, xfer, (xfer ? xfer->hcpriv : NULL))); 2008 if (xfer == NULL) { 2009 /* 2010 * xfer == NULL: There seems to be no xfer associated 2011 * with this TD. It is tailp that happened to end up on 2012 * the done queue. 2013 */ 2014 continue; 2015 } 2016 if (xfer->status == USBD_CANCELLED || 2017 xfer->status == USBD_TIMEOUT) { 2018 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 2019 xfer)); 2020 /* Handled by abort routine. */ 2021 continue; 2022 } 2023 2024 len = std->len; 2025 if (std->td.td_cbp != 0) 2026 len -= O32TOH(std->td.td_be) - 2027 O32TOH(std->td.td_cbp) + 1; 2028 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 2029 std->flags)); 2030 if (std->flags & OHCI_ADD_LEN) 2031 xfer->actlen += len; 2032 2033 #if 0 2034 isread = usbd_xfer_isread(xfer); 2035 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 2036 #endif 2037 2038 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 2039 if (cc != OHCI_CC_NO_ERROR) { 2040 /* 2041 * Endpoint is halted. First unlink all the TDs 2042 * belonging to the failed transfer, and then restart 2043 * the endpoint. 2044 */ 2045 opipe = (struct ohci_pipe *)xfer->pipe; 2046 2047 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 2048 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2049 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 2050 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2051 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 2052 &OXFER(xfer)->abort_task); 2053 2054 /* Remove all this xfer's TDs from the done queue. */ 2055 for (p = std; p->dnext != NULL; p = p->dnext) { 2056 if (p->dnext->xfer != xfer) 2057 continue; 2058 p->dnext = p->dnext->dnext; 2059 } 2060 /* The next TD may have been removed. */ 2061 stdnext = std->dnext; 2062 2063 #if 0 2064 /* Remove all TDs belonging to this xfer. */ 2065 for (p = xfer->hcpriv; p->xfer == xfer; p = n) { 2066 n = p->nexttd; 2067 #if 1 2068 if (p->ad.aux_len) 2069 ohci_aux_dma_complete(&p->ad, 2070 &OXFER(xfer)->aux, is_mbuf, isread); 2071 #endif 2072 ohci_free_std(sc, p); 2073 } 2074 2075 /* clear halt */ 2076 OHCI_SED_SYNC_POST(sc, opipe->sed); 2077 dmaadr = OHCI_STD_DMAADDR(p); 2078 opipe->sed->ed.ed_headp = HTOO32(dmaadr); 2079 OHCI_SED_SYNC2(sc, opipe->sed, 2080 offsetof(ohci_ed_t, ed_headp), 2081 sizeof(ohci_physaddr_t), 2082 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2083 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2084 #endif 2085 2086 if (cc == OHCI_CC_STALL) 2087 xfer->status = USBD_STALLED; 2088 else 2089 xfer->status = USBD_IOERROR; 2090 ohci_transfer_complete(xfer, 1); 2091 continue; 2092 } 2093 /* 2094 * Skip intermediate TDs. They remain linked from 2095 * xfer->hcpriv and we free them when the transfer completes. 2096 */ 2097 if ((std->flags & OHCI_CALL_DONE) == 0) 2098 continue; 2099 2100 /* Normal transfer completion */ 2101 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2102 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 2103 &OXFER(xfer)->abort_task); 2104 #if 0 2105 for (p = xfer->hcpriv; p->xfer == xfer; p = n) { 2106 n = p->nexttd; 2107 #if 1 2108 if (p->ad.aux_len) 2109 ohci_aux_dma_complete(&p->ad, 2110 &OXFER(xfer)->aux, is_mbuf, isread); 2111 #endif 2112 ohci_free_std(sc, p); 2113 } 2114 #endif 2115 xfer->status = USBD_NORMAL_COMPLETION; 2116 #if 0 /* will be done in ohci_transfer_complete() */ 2117 xfer->hcpriv = NULL; 2118 #endif 2119 ohci_transfer_complete(xfer, 0); 2120 } 2121 2122 #ifdef USB_DEBUG 2123 if (ohcidebug > 10) { 2124 DPRINTF(("ohci_softintr: ITD done:\n")); 2125 ohci_dump_itds(sc, sidone); 2126 } 2127 #endif 2128 2129 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 2130 xfer = sitd->xfer; 2131 sitdnext = sitd->dnext; 2132 sitd->flags |= OHCI_ITD_INTFIN; 2133 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 2134 sitd, xfer, xfer ? xfer->hcpriv : 0)); 2135 if (xfer == NULL) 2136 continue; 2137 if (xfer->status == USBD_CANCELLED || 2138 xfer->status == USBD_TIMEOUT) { 2139 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 2140 xfer)); 2141 /* Handled by abort routine. */ 2142 continue; 2143 } 2144 if (xfer->pipe) 2145 if (xfer->pipe->aborting) 2146 continue; /*Ignore.*/ 2147 #ifdef DIAGNOSTIC 2148 if (sitd->isdone) 2149 printf("ohci_softintr: sitd=%p is done\n", sitd); 2150 sitd->isdone = 1; 2151 #endif 2152 opipe = (struct ohci_pipe *)xfer->pipe; 2153 if (opipe->aborting) 2154 continue; 2155 2156 if (sitd->flags & OHCI_CALL_DONE) { 2157 ohci_soft_itd_t *next; 2158 int isread = opipe->pipe.endpoint->edesc->bEndpointAddress & UE_DIR_IN; 2159 2160 opipe->u.iso.inuse -= xfer->nframes; 2161 xfer->status = USBD_NORMAL_COMPLETION; 2162 for (i = 0, sitd = xfer->hcpriv;;sitd = next) { 2163 next = sitd->nextitd; 2164 cc = OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)); 2165 if (cc != OHCI_CC_NO_ERROR) { 2166 xfer->status = USBD_IOERROR; 2167 } 2168 2169 { 2170 iframes = OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)); 2171 for (j = 0; j < iframes; i++, j++) { 2172 len = O16TOH(sitd->itd.itd_offset[j]); 2173 #if 1 2174 cc = OHCI_ITD_PSW_GET_CC(len); 2175 switch (cc & 2176 OHCI_CC_NOT_ACCESSED_MASK) { 2177 case OHCI_CC_NOT_ACCESSED: 2178 len = 0; 2179 break; 2180 case OHCI_CC_BUFFER_OVERRUN: 2181 /* or BUFFER_UNDERRUN */ 2182 xfer->status = USBD_IOERROR; 2183 /* FALLTHROUGH */ 2184 default: 2185 len = OHCI_ITD_PSW_LENGTH(len); 2186 break; 2187 } 2188 #endif 2189 #if 0 2190 len = 2191 ((OHCI_ITD_PSW_GET_CC(len) & 2192 OHCI_CC_NOT_ACCESSED_MASK) 2193 == OHCI_CC_NOT_ACCESSED) ? 2194 0 : 2195 OHCI_ITD_PSW_LENGTH(len); 2196 #endif 2197 if (isread) 2198 xfer->frlengths[i] = len; 2199 } 2200 } 2201 if (sitd->flags & OHCI_CALL_DONE) 2202 break; 2203 } 2204 if (xfer->status != USBD_NORMAL_COMPLETION) { 2205 /* resync frame */ 2206 opipe->u.iso.next = -1; 2207 } 2208 #if 1 2209 /* XXX? */ 2210 xfer->status = USBD_NORMAL_COMPLETION; 2211 #endif 2212 2213 ohci_transfer_complete(xfer, 0); 2214 } 2215 } 2216 2217 #ifdef USB_USE_SOFTINTR 2218 if (sc->sc_softwake) { 2219 sc->sc_softwake = 0; 2220 wakeup(&sc->sc_softwake); 2221 } 2222 #endif /* USB_USE_SOFTINTR */ 2223 2224 sc->sc_bus.intr_context--; 2225 DPRINTFN(10,("ohci_softintr: done:\n")); 2226 } 2227 2228 void 2229 ohci_device_ctrl_done(usbd_xfer_handle xfer) 2230 { 2231 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 2232 2233 #ifdef DIAGNOSTIC 2234 if (!(xfer->rqflags & URQ_REQUEST)) { 2235 panic("ohci_device_ctrl_done: not a request"); 2236 } 2237 #endif 2238 } 2239 2240 void 2241 ohci_device_intr_done(usbd_xfer_handle xfer) 2242 { 2243 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2244 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2245 usbd_status err; 2246 2247 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 2248 xfer, xfer->actlen)); 2249 2250 if (xfer->pipe->repeat) { 2251 err = ohci_device_intr_insert(sc, xfer); 2252 if (err) { 2253 xfer->status = err; 2254 return; 2255 } 2256 } 2257 } 2258 2259 void 2260 ohci_device_bulk_done(usbd_xfer_handle xfer) 2261 { 2262 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 2263 xfer, xfer->actlen)); 2264 } 2265 2266 void 2267 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 2268 { 2269 usbd_pipe_handle pipe; 2270 u_char *p; 2271 int i, m; 2272 int hstatus; 2273 2274 hstatus = OREAD4(sc, OHCI_RH_STATUS); 2275 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 2276 sc, xfer, hstatus)); 2277 2278 if (xfer == NULL) { 2279 /* Just ignore the change. */ 2280 return; 2281 } 2282 2283 pipe = xfer->pipe; 2284 2285 p = xfer->hcbuffer; 2286 m = min(sc->sc_noport, xfer->length * 8 - 1); 2287 memset(p, 0, xfer->length); 2288 for (i = 1; i <= m; i++) { 2289 /* Pick out CHANGE bits from the status reg. */ 2290 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 2291 p[i/8] |= 1 << (i%8); 2292 } 2293 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 2294 xfer->actlen = xfer->length; 2295 xfer->status = USBD_NORMAL_COMPLETION; 2296 2297 usb_transfer_complete(xfer); 2298 } 2299 2300 void 2301 ohci_root_intr_done(usbd_xfer_handle xfer) 2302 { 2303 } 2304 2305 void 2306 ohci_root_ctrl_done(usbd_xfer_handle xfer) 2307 { 2308 } 2309 2310 /* 2311 * Wait here until controller claims to have an interrupt. 2312 * Then call ohci_intr and return. Use timeout to avoid waiting 2313 * too long. 2314 */ 2315 void 2316 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 2317 { 2318 int timo; 2319 u_int32_t intrs; 2320 2321 xfer->status = USBD_IN_PROGRESS; 2322 for (timo = xfer->timeout; timo >= 0; timo--) { 2323 usb_delay_ms(&sc->sc_bus, 1); 2324 if (sc->sc_dying) 2325 break; 2326 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 2327 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 2328 #ifdef USB_DEBUG 2329 if (ohcidebug > 15) 2330 ohci_dumpregs(sc); 2331 #endif 2332 if (intrs) { 2333 ohci_intr1(sc); 2334 if (xfer->status != USBD_IN_PROGRESS) 2335 return; 2336 } 2337 } 2338 2339 /* Timeout */ 2340 DPRINTF(("ohci_waitintr: timeout\n")); 2341 xfer->status = USBD_TIMEOUT; 2342 ohci_transfer_complete(xfer, 0); 2343 } 2344 2345 void 2346 ohci_poll(struct usbd_bus *bus) 2347 { 2348 ohci_softc_t *sc = (ohci_softc_t *)bus; 2349 #ifdef USB_DEBUG 2350 static int last; 2351 int new; 2352 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 2353 if (new != last) { 2354 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 2355 last = new; 2356 } 2357 #endif 2358 2359 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 2360 ohci_intr1(sc); 2361 } 2362 2363 usbd_status 2364 ohci_device_request(usbd_xfer_handle xfer) 2365 { 2366 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2367 usb_device_request_t *req = &xfer->request; 2368 usbd_device_handle dev = opipe->pipe.device; 2369 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2370 ohci_soft_td_t *setup, *stat, *next, *tail; 2371 ohci_soft_ed_t *sed; 2372 int isread; 2373 int len; 2374 usbd_status err; 2375 int s; 2376 ohci_physaddr_t dmaadr; 2377 2378 isread = req->bmRequestType & UT_READ; 2379 len = UGETW(req->wLength); 2380 2381 DPRINTFN(3,("ohci_device_request: type=0x%02x, request=0x%02x, " 2382 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2383 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2384 UGETW(req->wIndex), len, dev->address, 2385 opipe->pipe.endpoint->edesc->bEndpointAddress)); 2386 2387 setup = opipe->tail.td; 2388 stat = ohci_alloc_std(sc); 2389 if (stat == NULL) { 2390 err = USBD_NOMEM; 2391 goto bad1; 2392 } 2393 tail = ohci_alloc_std(sc); 2394 if (tail == NULL) { 2395 err = USBD_NOMEM; 2396 goto bad2; 2397 } 2398 tail->xfer = NULL; 2399 2400 sed = opipe->sed; 2401 opipe->u.ctl.length = len; 2402 next = stat; 2403 2404 /* Set up data transaction */ 2405 if (len != 0) { 2406 ohci_soft_td_t *std = stat; 2407 2408 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2409 std, &stat); 2410 if (err) 2411 goto bad3; 2412 OHCI_STD_SYNC(sc, stat, 2413 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2414 stat = stat->nexttd; /* point at free TD */ 2415 /* Start toggle at 1 and then use the carried toggle. */ 2416 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2417 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2418 } 2419 2420 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 2421 2422 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2423 OHCI_TD_TOGGLE_0 | OHCI_TD_SET_DI(6)); 2424 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 2425 setup->nexttd = next; 2426 dmaadr = OHCI_STD_DMAADDR(next); 2427 setup->td.td_nexttd = HTOO32(dmaadr); 2428 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 2429 setup->len = 0; 2430 setup->xfer = xfer; 2431 setup->flags = 0; 2432 xfer->hcpriv = setup; 2433 OHCI_STD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2434 2435 stat->td.td_flags = HTOO32( 2436 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2437 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2438 stat->td.td_cbp = 0; 2439 stat->nexttd = tail; 2440 dmaadr = OHCI_STD_DMAADDR(tail); 2441 stat->td.td_nexttd = HTOO32(dmaadr); 2442 stat->td.td_be = 0; 2443 stat->flags = OHCI_CALL_DONE; 2444 stat->len = 0; 2445 stat->xfer = xfer; 2446 OHCI_STD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2447 2448 #ifdef USB_DEBUG 2449 if (ohcidebug > 5) { 2450 DPRINTF(("ohci_device_request:\n")); 2451 ohci_dump_ed(sc, sed); 2452 ohci_dump_tds(sc, setup); 2453 } 2454 #endif 2455 2456 /* Insert ED in schedule */ 2457 s = splusb(); 2458 dmaadr = OHCI_STD_DMAADDR(tail); 2459 sed->ed.ed_tailp = HTOO32(dmaadr); 2460 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2461 opipe->tail.td = tail; 2462 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2463 if (xfer->timeout && !sc->sc_bus.use_polling) { 2464 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2465 ohci_timeout, xfer); 2466 } 2467 splx(s); 2468 2469 #ifdef USB_DEBUG 2470 if (ohcidebug > 20) { 2471 delay(10000); 2472 DPRINTF(("ohci_device_request: status=%x\n", 2473 OREAD4(sc, OHCI_COMMAND_STATUS))); 2474 ohci_dumpregs(sc); 2475 printf("ctrl head:\n"); 2476 ohci_dump_ed(sc, sc->sc_ctrl_head); 2477 printf("sed:\n"); 2478 ohci_dump_ed(sc, sed); 2479 ohci_dump_tds(sc, setup); 2480 } 2481 #endif 2482 2483 return (USBD_NORMAL_COMPLETION); 2484 2485 bad3: 2486 ohci_free_std(sc, tail); 2487 bad2: 2488 ohci_free_std(sc, stat); 2489 bad1: 2490 return (err); 2491 } 2492 2493 /* 2494 * Add an ED to the schedule. Called at splusb(). 2495 */ 2496 void 2497 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2498 { 2499 ohci_physaddr_t dmaadr; 2500 2501 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 2502 2503 SPLUSBCHECK; 2504 sed->next = head->next; 2505 sed->ed.ed_nexted = head->ed.ed_nexted; 2506 OHCI_SED_SYNC2(sc, sed, 2507 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2508 BUS_DMASYNC_PREWRITE); 2509 head->next = sed; 2510 dmaadr = OHCI_SED_DMAADDR(sed); 2511 head->ed.ed_nexted = HTOO32(dmaadr); 2512 OHCI_SED_SYNC2(sc, head, 2513 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2514 BUS_DMASYNC_PREWRITE); 2515 } 2516 2517 /* 2518 * Remove an ED from the schedule. Called at splusb(). 2519 */ 2520 void 2521 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2522 { 2523 ohci_soft_ed_t *p; 2524 2525 SPLUSBCHECK; 2526 2527 /* XXX */ 2528 for (p = head; p != NULL && p->next != sed; p = p->next) 2529 ; 2530 if (p == NULL) 2531 panic("ohci_rem_ed: ED not found"); 2532 p->next = sed->next; 2533 p->ed.ed_nexted = sed->ed.ed_nexted; 2534 OHCI_SED_SYNC2(sc, p, 2535 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2536 BUS_DMASYNC_PREWRITE); 2537 } 2538 2539 /* 2540 * When a transfer is completed the TD is added to the done queue by 2541 * the host controller. This queue is the processed by software. 2542 * Unfortunately the queue contains the physical address of the TD 2543 * and we have no simple way to translate this back to a kernel address. 2544 * To make the translation possible (and fast) we use the chunk of 2545 * TDs used for allocation. 2546 */ 2547 2548 ohci_soft_td_t * 2549 ohci_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 2550 { 2551 struct ohci_mem_desc *om; 2552 ohci_soft_td_t *std; 2553 size_t off; 2554 2555 /* if these are present they should be masked out at an earlier 2556 * stage. 2557 */ 2558 USB_KASSERT2((a&~OHCI_HEADMASK) == 0, ("%s: 0x%b has lower bits set\n", 2559 USBDEVNAME(sc->sc_bus.bdev), 2560 (int) a, "\20\1HALT\2TOGGLE")); 2561 2562 SIMPLEQ_FOREACH(om, &sc->sc_std_chunks, om_next) { 2563 if (a >= om->om_topdma && 2564 a < om->om_topdma + OHCI_STD_SIZE * OHCI_STD_CHUNK) { 2565 off = a - om->om_topdma; 2566 if (off % OHCI_STD_SIZE) { 2567 #ifdef DIAGNOSTIC 2568 printf("ohci_find_td: 0x%x bad address\n", 2569 (unsigned)a); 2570 #endif 2571 break; 2572 } 2573 std = (ohci_soft_td_t *)(om->om_top + off); 2574 if (std->flags & OHCI_TD_FREE) { 2575 #ifdef DIAGNOSTIC 2576 printf("ohci_find_td: 0x%x: free td\n", 2577 (unsigned)OHCI_STD_DMAADDR(std)); 2578 #endif 2579 break; 2580 } 2581 return std; 2582 } 2583 } 2584 2585 return (NULL); 2586 } 2587 2588 ohci_soft_itd_t * 2589 ohci_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 2590 { 2591 struct ohci_mem_desc *om; 2592 ohci_soft_itd_t *sitd; 2593 size_t off; 2594 2595 SIMPLEQ_FOREACH(om, &sc->sc_sitd_chunks, om_next) { 2596 if (a >= om->om_topdma && 2597 a < om->om_topdma + OHCI_SITD_SIZE * OHCI_SITD_CHUNK) { 2598 off = a - om->om_topdma; 2599 if (off % OHCI_SITD_SIZE) { 2600 #ifdef DIAGNOSTIC 2601 printf("ohci_find_itd: 0x%x bad address\n", 2602 (unsigned)a); 2603 #endif 2604 break; 2605 } 2606 sitd = (ohci_soft_itd_t *)(om->om_top + off); 2607 if (sitd->flags & OHCI_ITD_FREE) { 2608 #ifdef DIAGNOSTIC 2609 printf("ohci_find_itd: 0x%x: free itd\n", 2610 (unsigned)OHCI_SITD_DMAADDR(sitd)); 2611 #endif 2612 break; 2613 } 2614 return sitd; 2615 } 2616 } 2617 return (NULL); 2618 } 2619 2620 void 2621 ohci_timeout(void *addr) 2622 { 2623 struct ohci_xfer *oxfer = addr; 2624 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2625 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2626 2627 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2628 2629 if (sc->sc_dying) { 2630 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2631 return; 2632 } 2633 2634 /* Execute the abort in a process context. */ 2635 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2636 USB_TASKQ_HC); 2637 } 2638 2639 void 2640 ohci_timeout_task(void *addr) 2641 { 2642 usbd_xfer_handle xfer = addr; 2643 int s; 2644 2645 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2646 2647 s = splusb(); 2648 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2649 splx(s); 2650 } 2651 2652 #ifdef USB_DEBUG 2653 void 2654 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2655 { 2656 for (; std; std = std->nexttd) 2657 ohci_dump_td(sc, std); 2658 } 2659 2660 void 2661 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2662 { 2663 char sbuf[128]; 2664 2665 bitmask_snprintf((u_int32_t)O32TOH(std->td.td_flags), 2666 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2667 sbuf, sizeof(sbuf)); 2668 2669 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2670 "nexttd=0x%08lx be=0x%08lx\n", 2671 std, (u_long)OHCI_STD_DMAADDR(std), sbuf, 2672 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2673 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2674 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2675 (u_long)O32TOH(std->td.td_cbp), 2676 (u_long)O32TOH(std->td.td_nexttd), 2677 (u_long)O32TOH(std->td.td_be)); 2678 } 2679 2680 void 2681 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2682 { 2683 int i; 2684 2685 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2686 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2687 sitd, (u_long)OHCI_SITD_DMAADDR(sitd), 2688 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2689 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2690 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2691 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2692 (u_long)O32TOH(sitd->itd.itd_bp0), 2693 (u_long)O32TOH(sitd->itd.itd_nextitd), 2694 (u_long)O32TOH(sitd->itd.itd_be)); 2695 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2696 printf("offs[%d]=0x%04x ", i, 2697 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2698 printf("\n"); 2699 } 2700 2701 void 2702 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2703 { 2704 for (; sitd; sitd = sitd->nextitd) 2705 ohci_dump_itd(sc, sitd); 2706 } 2707 2708 void 2709 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2710 { 2711 char sbuf[128], sbuf2[128]; 2712 2713 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_flags), 2714 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2715 sbuf, sizeof(sbuf)); 2716 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_headp), 2717 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 2718 2719 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2720 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2721 sed, (u_long)OHCI_SED_DMAADDR(sed), 2722 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2723 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2724 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2725 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2726 (u_long)O32TOH(sed->ed.ed_headp), 2727 (u_long)O32TOH(sed->ed.ed_nexted)); 2728 } 2729 #endif 2730 2731 usbd_status 2732 ohci_open(usbd_pipe_handle pipe) 2733 { 2734 usbd_device_handle dev = pipe->device; 2735 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2736 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2737 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2738 u_int8_t addr = dev->address; 2739 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2740 ohci_soft_ed_t *sed; 2741 ohci_soft_td_t *std; 2742 ohci_soft_itd_t *sitd; 2743 ohci_physaddr_t tdphys; 2744 u_int32_t fmt; 2745 usbd_status err; 2746 int s; 2747 int ival; 2748 2749 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2750 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2751 2752 if (sc->sc_dying) 2753 return (USBD_IOERROR); 2754 2755 std = NULL; 2756 sed = NULL; 2757 2758 if (addr == sc->sc_addr) { 2759 switch (ed->bEndpointAddress) { 2760 case USB_CONTROL_ENDPOINT: 2761 pipe->methods = &ohci_root_ctrl_methods; 2762 break; 2763 case UE_DIR_IN | OHCI_INTR_ENDPT: 2764 pipe->methods = &ohci_root_intr_methods; 2765 break; 2766 default: 2767 return (USBD_INVAL); 2768 } 2769 } else { 2770 sed = ohci_alloc_sed(sc); 2771 if (sed == NULL) 2772 goto bad0; 2773 opipe->sed = sed; 2774 if (xfertype == UE_ISOCHRONOUS) { 2775 sitd = ohci_alloc_sitd_norsv(sc); 2776 if (sitd == NULL) 2777 goto bad1; 2778 opipe->tail.itd = sitd; 2779 opipe->aborting = 0; 2780 tdphys = OHCI_SITD_DMAADDR(sitd); 2781 fmt = OHCI_ED_FORMAT_ISO; 2782 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2783 fmt |= OHCI_ED_DIR_IN; 2784 else 2785 fmt |= OHCI_ED_DIR_OUT; 2786 } else { 2787 std = ohci_alloc_std_norsv(sc); 2788 if (std == NULL) 2789 goto bad1; 2790 opipe->tail.td = std; 2791 tdphys = OHCI_STD_DMAADDR(std); 2792 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2793 } 2794 sed->ed.ed_flags = HTOO32( 2795 OHCI_ED_SET_FA(addr) | 2796 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2797 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2798 fmt | 2799 OHCI_ED_SET_MAXP(UE_MAXPKTSZ(ed))); 2800 sed->ed.ed_headp = HTOO32(tdphys | 2801 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2802 sed->ed.ed_tailp = HTOO32(tdphys); 2803 2804 switch (xfertype) { 2805 case UE_CONTROL: 2806 pipe->methods = &ohci_device_ctrl_methods; 2807 err = usb_allocmem(&sc->sc_dmatag, 2808 sizeof(usb_device_request_t), 2809 0, &opipe->u.ctl.reqdma); 2810 if (err) 2811 goto bad; 2812 s = splusb(); 2813 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2814 splx(s); 2815 break; 2816 case UE_INTERRUPT: 2817 pipe->methods = &ohci_device_intr_methods; 2818 ival = pipe->interval; 2819 if (ival == USBD_DEFAULT_INTERVAL) 2820 ival = ed->bInterval; 2821 return (ohci_device_setintr(sc, opipe, ival)); 2822 case UE_ISOCHRONOUS: 2823 pipe->methods = &ohci_device_isoc_methods; 2824 return (ohci_setup_isoc(pipe)); 2825 case UE_BULK: 2826 pipe->methods = &ohci_device_bulk_methods; 2827 s = splusb(); 2828 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2829 splx(s); 2830 break; 2831 } 2832 } 2833 return (USBD_NORMAL_COMPLETION); 2834 2835 bad: 2836 if (std != NULL) 2837 ohci_free_std(sc, std); 2838 bad1: 2839 if (sed != NULL) 2840 ohci_free_sed(sc, sed); 2841 bad0: 2842 return (USBD_NOMEM); 2843 2844 } 2845 2846 /* 2847 * Close a reqular pipe. 2848 * Assumes that there are no pending transactions. 2849 */ 2850 void 2851 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2852 { 2853 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2854 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2855 ohci_soft_ed_t *sed = opipe->sed; 2856 int s; 2857 2858 s = splusb(); 2859 #ifdef DIAGNOSTIC 2860 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2861 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2862 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2863 ohci_soft_td_t *std; 2864 std = ohci_find_td(sc, 2865 O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK); 2866 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2867 "tl=0x%x pipe=%p, std=%p\n", sed, 2868 (int)O32TOH(sed->ed.ed_headp), 2869 (int)O32TOH(sed->ed.ed_tailp), 2870 pipe, std); 2871 #ifdef USB_DEBUG 2872 usbd_dump_pipe(&opipe->pipe); 2873 #endif 2874 #ifdef USB_DEBUG 2875 ohci_dump_ed(sc, sed); 2876 if (std) 2877 ohci_dump_td(sc, std); 2878 #endif 2879 usb_delay_ms(&sc->sc_bus, 2); 2880 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2881 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2882 printf("ohci_close_pipe: pipe still not empty\n"); 2883 } 2884 #endif 2885 ohci_rem_ed(sc, sed, head); 2886 /* Make sure the host controller is not touching this ED */ 2887 usb_delay_ms(&sc->sc_bus, 1); 2888 splx(s); 2889 pipe->endpoint->savedtoggle = 2890 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2891 ohci_free_sed(sc, sed); 2892 } 2893 2894 /* 2895 * Abort a device request. 2896 * If this routine is called at splusb() it guarantees that the request 2897 * will be removed from the hardware scheduling and that the callback 2898 * for it will be called with USBD_CANCELLED status. 2899 * It's impossible to guarantee that the requested transfer will not 2900 * have happened since the hardware runs concurrently. 2901 * If the transaction has already happened we rely on the ordinary 2902 * interrupt processing to process it. 2903 */ 2904 void 2905 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2906 { 2907 struct ohci_xfer *oxfer = OXFER(xfer); 2908 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2909 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2910 ohci_soft_ed_t *sed = opipe->sed; 2911 ohci_soft_td_t *p, *n; 2912 ohci_physaddr_t headp; 2913 ohci_physaddr_t dmaadr; 2914 int s, hit; 2915 int wake; 2916 int isread, is_mbuf; 2917 2918 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2919 2920 if (sc->sc_dying) { 2921 /* If we're dying, just do the software part. */ 2922 s = splusb(); 2923 xfer->status = status; /* make software ignore it */ 2924 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2925 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2926 ohci_transfer_complete(xfer, 0); 2927 splx(s); 2928 return; 2929 } 2930 2931 if (xfer->device->bus->intr_context || !curproc) 2932 panic("ohci_abort_xfer: not in process context"); 2933 2934 /* 2935 * If an abort is already in progress then just wait for it to 2936 * complete and return. 2937 */ 2938 if (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) { 2939 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2940 /* No need to wait if we're aborting from a timeout. */ 2941 if (status == USBD_TIMEOUT) 2942 return; 2943 /* Override the status which might be USBD_TIMEOUT. */ 2944 xfer->status = status; 2945 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2946 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTWAIT; 2947 while (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) 2948 tsleep(&oxfer->ohci_xfer_flags, PZERO, "ohciaw", 0); 2949 return; 2950 } 2951 2952 /* 2953 * Step 1: Make interrupt routine and hardware ignore xfer. 2954 */ 2955 s = splusb(); 2956 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTING; 2957 xfer->status = status; /* make software ignore it */ 2958 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2959 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2960 splx(s); 2961 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2962 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2963 2964 /* 2965 * Step 2: Wait until we know hardware has finished any possible 2966 * use of the xfer. Also make sure the soft interrupt routine 2967 * has run. 2968 */ 2969 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2970 s = splusb(); 2971 #ifdef USB_USE_SOFTINTR 2972 sc->sc_softwake = 1; 2973 #endif /* USB_USE_SOFTINTR */ 2974 usb_schedsoftintr(&sc->sc_bus); 2975 #ifdef USB_USE_SOFTINTR 2976 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2977 #endif /* USB_USE_SOFTINTR */ 2978 splx(s); 2979 2980 /* 2981 * Step 3: Remove any vestiges of the xfer from the hardware. 2982 * The complication here is that the hardware may have executed 2983 * beyond the xfer we're trying to abort. So as we're scanning 2984 * the TDs of this xfer we check if the hardware points to 2985 * any of them. 2986 */ 2987 s = splusb(); /* XXX why? */ 2988 p = xfer->hcpriv; 2989 #ifdef DIAGNOSTIC 2990 if (p == NULL) { 2991 oxfer->ohci_xfer_flags &= ~OHCI_XFER_ABORTING; /* XXX */ 2992 splx(s); 2993 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2994 return; 2995 } 2996 #endif 2997 #ifdef USB_DEBUG 2998 if (ohcidebug > 1) { 2999 DPRINTF(("ohci_abort_xfer: sed=\n")); 3000 ohci_dump_ed(sc, sed); 3001 ohci_dump_tds(sc, p); 3002 } 3003 #endif 3004 isread = usbd_xfer_isread(xfer); 3005 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 3006 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 3007 hit = 0; 3008 for (; p->xfer == xfer; p = n) { 3009 hit |= headp == OHCI_STD_DMAADDR(p); 3010 n = p->nexttd; 3011 #if 0 3012 #if 1 3013 if (p->ad.aux_len) 3014 ohci_aux_dma_complete(&p->ad, 3015 &OXFER(xfer)->aux, is_mbuf, isread); 3016 #endif 3017 ohci_free_std(sc, p); 3018 #endif 3019 } 3020 /* Zap headp register if hardware pointed inside the xfer. */ 3021 if (hit) { 3022 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 3023 (int)OHCI_STD_DMAADDR(p), (int)O32TOH(sed->ed.ed_tailp))); 3024 dmaadr = OHCI_STD_DMAADDR(p); 3025 sed->ed.ed_headp = HTOO32(dmaadr); /* unlink TDs */ 3026 } else { 3027 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 3028 } 3029 3030 /* 3031 * Step 4: Turn on hardware again. 3032 */ 3033 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3034 3035 /* 3036 * Step 5: Execute callback. 3037 */ 3038 /* Do the wakeup first to avoid touching the xfer after the callback. */ 3039 wake = oxfer->ohci_xfer_flags & OHCI_XFER_ABORTWAIT; 3040 oxfer->ohci_xfer_flags &= ~(OHCI_XFER_ABORTING | OHCI_XFER_ABORTWAIT); 3041 ohci_transfer_complete(xfer, 0); 3042 if (wake) 3043 wakeup(&oxfer->ohci_xfer_flags); 3044 3045 splx(s); 3046 } 3047 3048 /* 3049 * Data structures and routines to emulate the root hub. 3050 */ 3051 Static usb_device_descriptor_t ohci_devd = { 3052 USB_DEVICE_DESCRIPTOR_SIZE, 3053 UDESC_DEVICE, /* type */ 3054 {0x00, 0x01}, /* USB version */ 3055 UDCLASS_HUB, /* class */ 3056 UDSUBCLASS_HUB, /* subclass */ 3057 UDPROTO_FSHUB, /* protocol */ 3058 64, /* max packet */ 3059 {0},{0},{0x00,0x01}, /* device id */ 3060 1,2,0, /* string indicies */ 3061 1 /* # of configurations */ 3062 }; 3063 3064 Static usb_config_descriptor_t ohci_confd = { 3065 USB_CONFIG_DESCRIPTOR_SIZE, 3066 UDESC_CONFIG, 3067 {USB_CONFIG_DESCRIPTOR_SIZE + 3068 USB_INTERFACE_DESCRIPTOR_SIZE + 3069 USB_ENDPOINT_DESCRIPTOR_SIZE}, 3070 1, 3071 1, 3072 0, 3073 UC_ATTR_MBO | UC_SELF_POWERED, 3074 0 /* max power */ 3075 }; 3076 3077 Static usb_interface_descriptor_t ohci_ifcd = { 3078 USB_INTERFACE_DESCRIPTOR_SIZE, 3079 UDESC_INTERFACE, 3080 0, 3081 0, 3082 1, 3083 UICLASS_HUB, 3084 UISUBCLASS_HUB, 3085 UIPROTO_FSHUB, 3086 0 3087 }; 3088 3089 Static usb_endpoint_descriptor_t ohci_endpd = { 3090 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 3091 .bDescriptorType = UDESC_ENDPOINT, 3092 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 3093 .bmAttributes = UE_INTERRUPT, 3094 .wMaxPacketSize = {8, 0}, /* max packet */ 3095 .bInterval = 255, 3096 }; 3097 3098 Static usb_hub_descriptor_t ohci_hubd = { 3099 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 3100 .bDescriptorType = UDESC_HUB, 3101 }; 3102 3103 Static int 3104 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 3105 { 3106 int i; 3107 3108 if (l == 0) 3109 return (0); 3110 p->bLength = 2 * strlen(s) + 2; 3111 if (l == 1) 3112 return (1); 3113 p->bDescriptorType = UDESC_STRING; 3114 l -= 2; 3115 for (i = 0; s[i] && l > 1; i++, l -= 2) 3116 USETW2(p->bString[i], 0, s[i]); 3117 return (2*i+2); 3118 } 3119 3120 /* 3121 * Simulate a hardware hub by handling all the necessary requests. 3122 */ 3123 Static usbd_status 3124 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 3125 { 3126 usbd_status err; 3127 3128 /* Insert last in queue. */ 3129 #if 0 /* root ctrl doesn't do DMA */ 3130 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3131 &OXFER(xfer)->dmabuf); 3132 #else 3133 err = usb_insert_transfer(xfer); 3134 #endif 3135 if (err) 3136 return (err); 3137 3138 /* Pipe isn't running, start first */ 3139 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3140 } 3141 3142 Static usbd_status 3143 ohci_root_ctrl_start(usbd_xfer_handle xfer) 3144 { 3145 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3146 usb_device_request_t *req; 3147 void *buf = NULL; 3148 int port, i; 3149 int s, len, value, index, l, totlen = 0; 3150 usb_port_status_t ps; 3151 usb_hub_descriptor_t hubd; 3152 usbd_status err; 3153 u_int32_t v; 3154 3155 if (sc->sc_dying) 3156 return (USBD_IOERROR); 3157 3158 #ifdef DIAGNOSTIC 3159 if (!(xfer->rqflags & URQ_REQUEST)) 3160 /* XXX panic */ 3161 return (USBD_INVAL); 3162 #endif 3163 req = &xfer->request; 3164 3165 DPRINTFN(4,("ohci_root_ctrl_start: type=0x%02x request=%02x\n", 3166 req->bmRequestType, req->bRequest)); 3167 3168 len = UGETW(req->wLength); 3169 value = UGETW(req->wValue); 3170 index = UGETW(req->wIndex); 3171 3172 if (len != 0) { 3173 /* mbuf transfer is not supported */ 3174 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 3175 return (USBD_INVAL); 3176 buf = xfer->hcbuffer; 3177 } 3178 3179 #define C(x,y) ((x) | ((y) << 8)) 3180 switch(C(req->bRequest, req->bmRequestType)) { 3181 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3182 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3183 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3184 /* 3185 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3186 * for the integrated root hub. 3187 */ 3188 break; 3189 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3190 if (len > 0) { 3191 *(u_int8_t *)buf = sc->sc_conf; 3192 totlen = 1; 3193 } 3194 break; 3195 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3196 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 3197 if (len == 0) 3198 break; 3199 switch(value >> 8) { 3200 case UDESC_DEVICE: 3201 if ((value & 0xff) != 0) { 3202 err = USBD_IOERROR; 3203 goto ret; 3204 } 3205 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3206 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 3207 memcpy(buf, &ohci_devd, l); 3208 break; 3209 case UDESC_CONFIG: 3210 if ((value & 0xff) != 0) { 3211 err = USBD_IOERROR; 3212 goto ret; 3213 } 3214 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3215 memcpy(buf, &ohci_confd, l); 3216 buf = (char *)buf + l; 3217 len -= l; 3218 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3219 totlen += l; 3220 memcpy(buf, &ohci_ifcd, l); 3221 buf = (char *)buf + l; 3222 len -= l; 3223 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3224 totlen += l; 3225 memcpy(buf, &ohci_endpd, l); 3226 break; 3227 case UDESC_STRING: 3228 *(u_int8_t *)buf = 0; 3229 totlen = 1; 3230 switch (value & 0xff) { 3231 case 0: /* Language table */ 3232 if (len > 0) 3233 *(u_int8_t *)buf = 4; 3234 if (len >= 4) { 3235 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 3236 totlen = 4; 3237 } 3238 break; 3239 case 1: /* Vendor */ 3240 totlen = ohci_str(buf, len, sc->sc_vendor); 3241 break; 3242 case 2: /* Product */ 3243 totlen = ohci_str(buf, len, "OHCI root hub"); 3244 break; 3245 } 3246 break; 3247 default: 3248 err = USBD_IOERROR; 3249 goto ret; 3250 } 3251 break; 3252 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3253 if (len > 0) { 3254 *(u_int8_t *)buf = 0; 3255 totlen = 1; 3256 } 3257 break; 3258 case C(UR_GET_STATUS, UT_READ_DEVICE): 3259 if (len > 1) { 3260 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3261 totlen = 2; 3262 } 3263 break; 3264 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3265 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3266 if (len > 1) { 3267 USETW(((usb_status_t *)buf)->wStatus, 0); 3268 totlen = 2; 3269 } 3270 break; 3271 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3272 if (value >= USB_MAX_DEVICES) { 3273 err = USBD_IOERROR; 3274 goto ret; 3275 } 3276 sc->sc_addr = value; 3277 break; 3278 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3279 if (value != 0 && value != 1) { 3280 err = USBD_IOERROR; 3281 goto ret; 3282 } 3283 sc->sc_conf = value; 3284 break; 3285 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3286 break; 3287 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3288 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3289 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3290 err = USBD_IOERROR; 3291 goto ret; 3292 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3293 break; 3294 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3295 break; 3296 /* Hub requests */ 3297 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3298 break; 3299 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3300 DPRINTFN(8, ("ohci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 3301 "port=%d feature=%d\n", 3302 index, value)); 3303 if (index < 1 || index > sc->sc_noport) { 3304 err = USBD_IOERROR; 3305 goto ret; 3306 } 3307 port = OHCI_RH_PORT_STATUS(index); 3308 switch(value) { 3309 case UHF_PORT_ENABLE: 3310 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 3311 break; 3312 case UHF_PORT_SUSPEND: 3313 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 3314 break; 3315 case UHF_PORT_POWER: 3316 /* Yes, writing to the LOW_SPEED bit clears power. */ 3317 OWRITE4(sc, port, UPS_LOW_SPEED); 3318 break; 3319 case UHF_C_PORT_CONNECTION: 3320 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 3321 break; 3322 case UHF_C_PORT_ENABLE: 3323 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 3324 break; 3325 case UHF_C_PORT_SUSPEND: 3326 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 3327 break; 3328 case UHF_C_PORT_OVER_CURRENT: 3329 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 3330 break; 3331 case UHF_C_PORT_RESET: 3332 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 3333 break; 3334 default: 3335 err = USBD_IOERROR; 3336 goto ret; 3337 } 3338 switch(value) { 3339 case UHF_C_PORT_CONNECTION: 3340 case UHF_C_PORT_ENABLE: 3341 case UHF_C_PORT_SUSPEND: 3342 case UHF_C_PORT_OVER_CURRENT: 3343 case UHF_C_PORT_RESET: 3344 /* Enable RHSC interrupt if condition is cleared. */ 3345 if ((OREAD4(sc, port) >> 16) == 0) 3346 ohci_rhsc_enable(sc); 3347 break; 3348 default: 3349 break; 3350 } 3351 break; 3352 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3353 if (len == 0) 3354 break; 3355 if ((value & 0xff) != 0) { 3356 err = USBD_IOERROR; 3357 goto ret; 3358 } 3359 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 3360 hubd = ohci_hubd; 3361 hubd.bNbrPorts = sc->sc_noport; 3362 USETW(hubd.wHubCharacteristics, 3363 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 3364 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 3365 /* XXX overcurrent */ 3366 ); 3367 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 3368 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 3369 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 3370 hubd.DeviceRemovable[i++] = (u_int8_t)v; 3371 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3372 l = min(len, hubd.bDescLength); 3373 totlen = l; 3374 memcpy(buf, &hubd, l); 3375 break; 3376 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3377 if (len != 4) { 3378 err = USBD_IOERROR; 3379 goto ret; 3380 } 3381 memset(buf, 0, len); /* ? XXX */ 3382 totlen = len; 3383 break; 3384 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3385 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 3386 index)); 3387 if (index < 1 || index > sc->sc_noport) { 3388 err = USBD_IOERROR; 3389 goto ret; 3390 } 3391 if (len != 4) { 3392 err = USBD_IOERROR; 3393 goto ret; 3394 } 3395 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 3396 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 3397 v)); 3398 USETW(ps.wPortStatus, v); 3399 USETW(ps.wPortChange, v >> 16); 3400 l = min(len, sizeof ps); 3401 memcpy(buf, &ps, l); 3402 totlen = l; 3403 break; 3404 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3405 err = USBD_IOERROR; 3406 goto ret; 3407 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3408 break; 3409 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3410 if (index < 1 || index > sc->sc_noport) { 3411 err = USBD_IOERROR; 3412 goto ret; 3413 } 3414 port = OHCI_RH_PORT_STATUS(index); 3415 switch(value) { 3416 case UHF_PORT_ENABLE: 3417 OWRITE4(sc, port, UPS_PORT_ENABLED); 3418 break; 3419 case UHF_PORT_SUSPEND: 3420 OWRITE4(sc, port, UPS_SUSPEND); 3421 break; 3422 case UHF_PORT_RESET: 3423 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 3424 index)); 3425 OWRITE4(sc, port, UPS_RESET); 3426 for (i = 0; i < 5; i++) { 3427 usb_delay_ms(&sc->sc_bus, 3428 USB_PORT_ROOT_RESET_DELAY); 3429 if (sc->sc_dying) { 3430 err = USBD_IOERROR; 3431 goto ret; 3432 } 3433 if ((OREAD4(sc, port) & UPS_RESET) == 0) 3434 break; 3435 } 3436 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 3437 index, OREAD4(sc, port))); 3438 break; 3439 case UHF_PORT_POWER: 3440 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 3441 "%d\n", index)); 3442 OWRITE4(sc, port, UPS_PORT_POWER); 3443 break; 3444 default: 3445 err = USBD_IOERROR; 3446 goto ret; 3447 } 3448 break; 3449 default: 3450 err = USBD_IOERROR; 3451 goto ret; 3452 } 3453 xfer->actlen = totlen; 3454 err = USBD_NORMAL_COMPLETION; 3455 ret: 3456 xfer->status = err; 3457 #if 0 /* root ctrl doesn't do DMA */ 3458 ohci_transfer_complete(xfer, 0); 3459 #else 3460 s = splusb(); 3461 usb_transfer_complete(xfer); 3462 splx(s); 3463 #endif 3464 return (USBD_IN_PROGRESS); 3465 } 3466 3467 /* Abort a root control request. */ 3468 Static void 3469 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 3470 { 3471 /* Nothing to do, all transfers are synchronous. */ 3472 } 3473 3474 /* Close the root pipe. */ 3475 Static void 3476 ohci_root_ctrl_close(usbd_pipe_handle pipe) 3477 { 3478 DPRINTF(("ohci_root_ctrl_close\n")); 3479 /* Nothing to do. */ 3480 } 3481 3482 Static usbd_status 3483 ohci_root_intr_transfer(usbd_xfer_handle xfer) 3484 { 3485 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3486 usbd_status err; 3487 3488 /* Insert last in queue. */ 3489 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3490 &OXFER(xfer)->dmabuf); 3491 if (err) 3492 return (err); 3493 3494 /* Pipe isn't running, start first */ 3495 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3496 } 3497 3498 Static usbd_status 3499 ohci_root_intr_start(usbd_xfer_handle xfer) 3500 { 3501 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3502 3503 if (sc->sc_dying) 3504 return (USBD_IOERROR); 3505 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 3506 return (USBD_INVAL); /* mbuf transfer is not supported */ 3507 3508 sc->sc_intrxfer = xfer; 3509 3510 return (USBD_IN_PROGRESS); 3511 } 3512 3513 /* Abort a root interrupt request. */ 3514 Static void 3515 ohci_root_intr_abort(usbd_xfer_handle xfer) 3516 { 3517 usbd_pipe_handle pipe = xfer->pipe; 3518 3519 if (pipe->intrxfer == xfer) { 3520 DPRINTF(("ohci_root_intr_abort: remove\n")); 3521 pipe->intrxfer = NULL; 3522 } 3523 xfer->status = USBD_CANCELLED; 3524 ohci_transfer_complete(xfer, 0); 3525 } 3526 3527 /* Close the root pipe. */ 3528 Static void 3529 ohci_root_intr_close(usbd_pipe_handle pipe) 3530 { 3531 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3532 3533 DPRINTF(("ohci_root_intr_close\n")); 3534 3535 sc->sc_intrxfer = NULL; 3536 } 3537 3538 /************************/ 3539 3540 Static usbd_status 3541 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 3542 { 3543 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3548 &OXFER(xfer)->dmabuf); 3549 if (err) 3550 return (err); 3551 3552 /* Pipe isn't running, start first */ 3553 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3554 } 3555 3556 Static usbd_status 3557 ohci_device_ctrl_start(usbd_xfer_handle xfer) 3558 { 3559 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3560 usbd_status err; 3561 3562 if (sc->sc_dying) 3563 return (USBD_IOERROR); 3564 3565 #ifdef DIAGNOSTIC 3566 if (!(xfer->rqflags & URQ_REQUEST)) { 3567 /* XXX panic */ 3568 printf("ohci_device_ctrl_transfer: not a request\n"); 3569 return (USBD_INVAL); 3570 } 3571 #endif 3572 3573 err = ohci_device_request(xfer); 3574 if (err) 3575 return (err); 3576 3577 if (sc->sc_bus.use_polling) 3578 ohci_waitintr(sc, xfer); 3579 return (USBD_IN_PROGRESS); 3580 } 3581 3582 /* Abort a device control request. */ 3583 Static void 3584 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 3585 { 3586 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 3587 ohci_abort_xfer(xfer, USBD_CANCELLED); 3588 } 3589 3590 /* Close a device control pipe. */ 3591 Static void 3592 ohci_device_ctrl_close(usbd_pipe_handle pipe) 3593 { 3594 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3595 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3596 3597 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 3598 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3599 ohci_free_std_norsv(sc, opipe->tail.td); 3600 usb_freemem(&sc->sc_dmatag, &opipe->u.ctl.reqdma); 3601 } 3602 3603 /************************/ 3604 3605 Static void 3606 ohci_device_clear_toggle(usbd_pipe_handle pipe) 3607 { 3608 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3609 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3610 3611 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3612 } 3613 3614 Static void 3615 ohci_noop(usbd_pipe_handle pipe) 3616 { 3617 } 3618 3619 Static usbd_status 3620 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 3621 { 3622 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3623 usbd_status err; 3624 3625 /* Insert last in queue. */ 3626 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3627 &OXFER(xfer)->dmabuf); 3628 if (err) 3629 return (err); 3630 3631 /* Pipe isn't running, start first */ 3632 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3633 } 3634 3635 Static usbd_status 3636 ohci_device_bulk_start(usbd_xfer_handle xfer) 3637 { 3638 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3639 usbd_device_handle dev = opipe->pipe.device; 3640 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3641 int addr = dev->address; 3642 ohci_soft_td_t *data, *tail, *tdp; 3643 ohci_soft_ed_t *sed; 3644 ohci_physaddr_t dmaadr; 3645 int s, len, isread, endpt; 3646 usbd_status err; 3647 3648 if (sc->sc_dying) 3649 return (USBD_IOERROR); 3650 3651 #ifdef DIAGNOSTIC 3652 if (xfer->rqflags & URQ_REQUEST) { 3653 /* XXX panic */ 3654 printf("ohci_device_bulk_start: a request\n"); 3655 return (USBD_INVAL); 3656 } 3657 #endif 3658 3659 len = xfer->length; 3660 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3661 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3662 sed = opipe->sed; 3663 3664 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3665 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3666 endpt)); 3667 3668 opipe->u.bulk.isread = isread; 3669 opipe->u.bulk.length = len; 3670 3671 /* Update device address */ 3672 sed->ed.ed_flags = HTOO32( 3673 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3674 OHCI_ED_SET_FA(addr)); 3675 3676 /* Allocate a chain of new TDs (including a new tail). */ 3677 data = opipe->tail.td; 3678 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3679 data, &tail); 3680 /* We want interrupt at the end of the transfer. */ 3681 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3682 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3683 tail->flags |= OHCI_CALL_DONE; 3684 OHCI_STD_SYNC(sc, tail, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3685 tail = tail->nexttd; /* point at sentinel */ 3686 if (err) 3687 return (err); 3688 3689 tail->xfer = NULL; 3690 xfer->hcpriv = data; 3691 3692 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3693 "td_cbp=0x%08x td_be=0x%08x\n", 3694 (int)O32TOH(sed->ed.ed_flags), 3695 (int)O32TOH(data->td.td_flags), 3696 (int)O32TOH(data->td.td_cbp), 3697 (int)O32TOH(data->td.td_be))); 3698 3699 #ifdef USB_DEBUG 3700 if (ohcidebug > 5) { 3701 ohci_dump_ed(sc, sed); 3702 ohci_dump_tds(sc, data); 3703 } 3704 #endif 3705 3706 /* Insert ED in schedule */ 3707 s = splusb(); 3708 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3709 tdp->xfer = xfer; 3710 } 3711 dmaadr = OHCI_STD_DMAADDR(tail); 3712 sed->ed.ed_tailp = HTOO32(dmaadr); 3713 opipe->tail.td = tail; 3714 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3715 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3716 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3717 if (xfer->timeout && !sc->sc_bus.use_polling) { 3718 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3719 ohci_timeout, xfer); 3720 } 3721 3722 #if 0 3723 /* This goes wrong if we are too slow. */ 3724 if (ohcidebug > 10) { 3725 delay(10000); 3726 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3727 OREAD4(sc, OHCI_COMMAND_STATUS))); 3728 ohci_dump_ed(sc, sed); 3729 ohci_dump_tds(sc, data); 3730 } 3731 #endif 3732 3733 splx(s); 3734 3735 if (sc->sc_bus.use_polling) 3736 ohci_waitintr(sc, xfer); 3737 3738 return (USBD_IN_PROGRESS); 3739 } 3740 3741 Static void 3742 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3743 { 3744 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3745 ohci_abort_xfer(xfer, USBD_CANCELLED); 3746 } 3747 3748 /* 3749 * Close a device bulk pipe. 3750 */ 3751 Static void 3752 ohci_device_bulk_close(usbd_pipe_handle pipe) 3753 { 3754 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3755 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3756 3757 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3758 ohci_close_pipe(pipe, sc->sc_bulk_head); 3759 ohci_free_std_norsv(sc, opipe->tail.td); 3760 } 3761 3762 /************************/ 3763 3764 Static usbd_status 3765 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3766 { 3767 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3768 usbd_status err; 3769 3770 /* Insert last in queue. */ 3771 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3772 &OXFER(xfer)->dmabuf); 3773 if (err) 3774 return (err); 3775 3776 /* Pipe isn't running, start first */ 3777 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3778 } 3779 3780 Static usbd_status 3781 ohci_device_intr_start(usbd_xfer_handle xfer) 3782 { 3783 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3784 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3785 ohci_soft_ed_t *sed = opipe->sed; 3786 usbd_status err; 3787 3788 if (sc->sc_dying) 3789 return (USBD_IOERROR); 3790 3791 DPRINTFN(3, ("ohci_device_intr_start: xfer=%p len=%d " 3792 "flags=%d priv=%p\n", 3793 xfer, xfer->length, xfer->flags, xfer->priv)); 3794 3795 #ifdef DIAGNOSTIC 3796 if (xfer->rqflags & URQ_REQUEST) 3797 panic("ohci_device_intr_start: a request"); 3798 #endif 3799 3800 err = ohci_device_intr_insert(sc, xfer); 3801 if (err) 3802 return (err); 3803 3804 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3805 3806 return (USBD_IN_PROGRESS); 3807 } 3808 3809 /* 3810 * Insert an interrupt transfer into an endpoint descriptor list 3811 */ 3812 Static usbd_status 3813 ohci_device_intr_insert(ohci_softc_t *sc, usbd_xfer_handle xfer) 3814 { 3815 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3816 ohci_soft_ed_t *sed = opipe->sed; 3817 ohci_soft_td_t *data, *tail; 3818 ohci_physaddr_t dataphys, physend; 3819 ohci_physaddr_t dmaadr; 3820 int s, isread, endpt; 3821 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 3822 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 3823 int nsegs = USB_BUFFER_NSEGS(ub); 3824 3825 DPRINTFN(4, ("ohci_device_intr_insert: xfer=%p", xfer)); 3826 3827 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3828 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3829 3830 data = opipe->tail.td; 3831 tail = ohci_alloc_std(sc); 3832 if (tail == NULL) 3833 return (USBD_NOMEM); 3834 tail->xfer = NULL; 3835 3836 data->td.td_flags = HTOO32( 3837 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3838 OHCI_TD_NOCC | 3839 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3840 if (xfer->flags & USBD_SHORT_XFER_OK) 3841 data->td.td_flags |= HTOO32(OHCI_TD_R); 3842 /* 3843 * Assume a short mapping with no complications, which 3844 * should always be true for <= 4k buffers in contiguous 3845 * virtual memory. The data can take the following forms: 3846 * 1 segment in 1 OHCI page 3847 * 1 segment in 2 OHCI pages 3848 * 2 segments in 2 OHCI pages 3849 * (see comment in ohci_alloc_std_chain() for details) 3850 */ 3851 USB_KASSERT2(xfer->length > 0 && xfer->length <= OHCI_PAGE_SIZE, 3852 ("ohci_device_intr_insert: bad length %d", xfer->length)); 3853 dataphys = segs[0].ds_addr; 3854 physend = dataphys + xfer->length - 1; 3855 if (nsegs == 2) { 3856 USB_KASSERT2(OHCI_PAGE_OFFSET(dataphys + 3857 segs[0].ds_len) == 0, 3858 ("ohci_device_intr_insert: bad seg 0 termination")); 3859 physend = segs[1].ds_addr + xfer->length - 3860 segs[0].ds_len - 1; 3861 } else { 3862 USB_KASSERT2(nsegs == 1, 3863 ("ohci_device_intr_insert: bad seg count %d", 3864 (u_int)nsegs)); 3865 } 3866 data->td.td_cbp = HTOO32(dataphys); 3867 data->nexttd = tail; 3868 dmaadr = OHCI_STD_DMAADDR(tail); 3869 data->td.td_nexttd = HTOO32(dmaadr); 3870 data->td.td_be = HTOO32(physend); 3871 data->len = xfer->length; 3872 data->xfer = xfer; 3873 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3874 xfer->hcpriv = data; 3875 xfer->actlen = 0; 3876 OHCI_STD_SYNC(sc, data, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3877 3878 #ifdef USB_DEBUG 3879 if (ohcidebug > 5) { 3880 DPRINTF(("ohci_device_intr_insert:\n")); 3881 ohci_dump_ed(sc, sed); 3882 ohci_dump_tds(sc, data); 3883 } 3884 #endif 3885 3886 /* Insert ED in schedule */ 3887 s = splusb(); 3888 dmaadr = OHCI_STD_DMAADDR(tail); 3889 sed->ed.ed_tailp = HTOO32(dmaadr); 3890 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3891 opipe->tail.td = tail; 3892 splx(s); 3893 3894 return (USBD_NORMAL_COMPLETION); 3895 } 3896 3897 /* Abort a device control request. */ 3898 Static void 3899 ohci_device_intr_abort(usbd_xfer_handle xfer) 3900 { 3901 if (xfer->pipe->intrxfer == xfer) { 3902 DPRINTF(("ohci_device_intr_abort: remove\n")); 3903 xfer->pipe->intrxfer = NULL; 3904 } 3905 ohci_abort_xfer(xfer, USBD_CANCELLED); 3906 } 3907 3908 /* Close a device interrupt pipe. */ 3909 Static void 3910 ohci_device_intr_close(usbd_pipe_handle pipe) 3911 { 3912 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3913 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3914 int nslots = opipe->u.intr.nslots; 3915 int pos = opipe->u.intr.pos; 3916 int j; 3917 ohci_soft_ed_t *p, *sed = opipe->sed; 3918 int s; 3919 3920 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3921 pipe, nslots, pos)); 3922 s = splusb(); 3923 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3924 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3925 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3926 usb_delay_ms(&sc->sc_bus, 2); 3927 #ifdef DIAGNOSTIC 3928 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3929 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3930 panic("%s: Intr pipe %p still has TDs queued", 3931 USBDEVNAME(sc->sc_bus.bdev), pipe); 3932 #endif 3933 3934 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3935 ; 3936 #ifdef DIAGNOSTIC 3937 if (p == NULL) 3938 panic("ohci_device_intr_close: ED not found"); 3939 #endif 3940 p->next = sed->next; 3941 p->ed.ed_nexted = sed->ed.ed_nexted; 3942 splx(s); 3943 3944 for (j = 0; j < nslots; j++) 3945 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3946 3947 ohci_free_std_norsv(sc, opipe->tail.td); 3948 ohci_free_sed(sc, opipe->sed); 3949 } 3950 3951 Static usbd_status 3952 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3953 { 3954 int i, j, s, best; 3955 u_int npoll, slow, shigh, nslots; 3956 u_int bestbw, bw; 3957 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3958 ohci_physaddr_t dmaadr; 3959 3960 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3961 if (ival == 0) { 3962 printf("ohci_setintr: 0 interval\n"); 3963 return (USBD_INVAL); 3964 } 3965 3966 npoll = OHCI_NO_INTRS; 3967 while (npoll > ival) 3968 npoll /= 2; 3969 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3970 3971 /* 3972 * We now know which level in the tree the ED must go into. 3973 * Figure out which slot has most bandwidth left over. 3974 * Slots to examine: 3975 * npoll 3976 * 1 0 3977 * 2 1 2 3978 * 4 3 4 5 6 3979 * 8 7 8 9 10 11 12 13 14 3980 * N (N-1) .. (N-1+N-1) 3981 */ 3982 slow = npoll-1; 3983 shigh = slow + npoll; 3984 nslots = OHCI_NO_INTRS / npoll; 3985 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3986 bw = 0; 3987 for (j = 0; j < nslots; j++) 3988 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3989 if (bw < bestbw) { 3990 best = i; 3991 bestbw = bw; 3992 } 3993 } 3994 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3995 best, slow, shigh, bestbw)); 3996 3997 s = splusb(); 3998 hsed = sc->sc_eds[best]; 3999 sed->next = hsed->next; 4000 sed->ed.ed_nexted = hsed->ed.ed_nexted; 4001 hsed->next = sed; 4002 dmaadr = OHCI_SED_DMAADDR(sed); 4003 hsed->ed.ed_nexted = HTOO32(dmaadr); 4004 splx(s); 4005 4006 for (j = 0; j < nslots; j++) 4007 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 4008 opipe->u.intr.nslots = nslots; 4009 opipe->u.intr.pos = best; 4010 4011 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 4012 return (USBD_NORMAL_COMPLETION); 4013 } 4014 4015 /***********************/ 4016 4017 usbd_status 4018 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 4019 { 4020 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 4021 usbd_status err; 4022 4023 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 4024 4025 /* Put it on our queue, */ 4026 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 4027 &OXFER(xfer)->dmabuf); 4028 4029 /* bail out on error, */ 4030 if (err && err != USBD_IN_PROGRESS) 4031 return (err); 4032 4033 /* XXX should check inuse here */ 4034 4035 /* insert into schedule, */ 4036 ohci_device_isoc_enter(xfer); 4037 4038 /* and start if the pipe wasn't running */ 4039 if (!err) 4040 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 4041 4042 return (err); 4043 } 4044 4045 void 4046 ohci_device_isoc_enter(usbd_xfer_handle xfer) 4047 { 4048 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 4049 usbd_device_handle dev = opipe->pipe.device; 4050 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 4051 ohci_soft_ed_t *sed = opipe->sed; 4052 struct iso *iso = &opipe->u.iso; 4053 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 4054 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 4055 int nsegs = USB_BUFFER_NSEGS(ub); 4056 ohci_soft_itd_t *sitd, *nsitd; 4057 ohci_physaddr_t dataphys, physend, prevphysend; 4058 ohci_physaddr_t segdmaadr; 4059 ohci_physaddr_t dmaadr; 4060 int i, len, ncur, nframes, seg, seglen, seglen1; 4061 int useaux, npagecross; 4062 int s; 4063 #if 1 4064 union usb_bufptr bufptr; 4065 int endpt, isread, is_mbuf; 4066 bus_addr_t auxdma; 4067 #endif 4068 #if 1 4069 uint32_t sitdo, tailo; 4070 #endif 4071 4072 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 4073 "nframes=%d\n", 4074 iso->inuse, iso->next, xfer, xfer->nframes)); 4075 4076 if (sc->sc_dying) 4077 return; 4078 4079 if (iso->next == -1) { 4080 /* Not in use yet, schedule it a few frames ahead. */ 4081 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4082 offsetof(struct ohci_hcca, hcca_frame_number), 4083 sizeof(sc->sc_hcca->hcca_frame_number), 4084 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4085 iso->next = (uint16_t)(O32TOH(sc->sc_hcca->hcca_frame_number) + 5); 4086 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 4087 iso->next)); 4088 4089 #if 1 4090 OHCI_SED_SYNC_POST(sc, sed); 4091 if (sed->ed.ed_headp != sed->ed.ed_tailp) { 4092 /* set SKIP first */ 4093 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 4094 OHCI_SED_SYNC2(sc, sed, 4095 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4096 BUS_DMASYNC_PREWRITE); 4097 4098 /* wait for SKIP to take effect */ 4099 delay(2100); 4100 4101 OHCI_SED_SYNC_POST(sc, sed); 4102 4103 tailo = sed->ed.ed_tailp; 4104 for (sitdo = sed->ed.ed_headp; sitdo != tailo; 4105 sitdo = sitd->itd.itd_nextitd) { 4106 sitd = ohci_find_itd(sc, O32TOH(sitdo)); 4107 *(uint16_t *)&sitd->itd.itd_flags = 4108 HTOO16(iso->next); 4109 iso->next = (uint16_t)(iso->next + 4110 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags))); 4111 OHCI_SITD_SYNC(sc, sitd, 4112 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4113 } 4114 4115 /* clear SKIP */ 4116 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 4117 OHCI_SED_SYNC2(sc, sed, 4118 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4119 BUS_DMASYNC_PREWRITE); 4120 } 4121 #endif 4122 } 4123 4124 usb_bufptr_init(&bufptr, xfer); 4125 4126 sitd = opipe->tail.itd; 4127 nframes = xfer->nframes; 4128 xfer->hcpriv = sitd; 4129 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 4130 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4131 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 4132 4133 #ifdef DIAGNOSTIC 4134 segdmaadr = 0xbbbbbbbb; /* XXX -Wuninitialized */ 4135 dataphys = 0x77777777; /* XXX -Wuninitialized */ 4136 physend = 0xeeeeeeee; /* XXX -Wuninitialized */ 4137 prevphysend = 0x99999999; /* XXX -Wuninitialized */ 4138 #else 4139 segdmaadr = 0; /* XXX -Wuninitialized */ 4140 dataphys = 0; /* XXX -Wuninitialized */ 4141 physend = 0; /* XXX -Wuninitialized */ 4142 prevphysend = 0; /* XXX -Wuninitialized */ 4143 #endif 4144 4145 seg = 0; 4146 seglen = 0; 4147 useaux = 0; 4148 i = 0; 4149 while (i < nframes) { 4150 ncur = 0; 4151 npagecross = 0; 4152 do { 4153 /* 4154 * Fill in as many ITD frames as possible. 4155 */ 4156 4157 /* Find the frame start and end physical addresses. */ 4158 len = xfer->frlengths[i]; 4159 4160 if (useaux == 0) { 4161 /* skip handled segments */ 4162 if (seglen <= 0) { 4163 USB_KASSERT2(seg < nsegs, 4164 ("ohci_device_isoc_enter: overrun")); 4165 do { 4166 seglen1 = seglen; 4167 seglen += segs[seg].ds_len; 4168 if (seglen1 <= 0 && seglen > 0) 4169 segdmaadr = 4170 segs[seg].ds_addr 4171 - seglen1; 4172 } while (++seg < nsegs && 4173 (seglen <= 0 || 4174 segdmaadr + seglen == 4175 segs[seg].ds_addr)); 4176 } 4177 4178 /* DMA start and end addresses of the frame */ 4179 if (len <= seglen) { 4180 /* the frame fits in the segment */ 4181 physend = segdmaadr + len - 1; 4182 dataphys = segdmaadr; 4183 } else if (/* len > seglen */ 4184 (OHCI_PAGE_OFFSET(segdmaadr + seglen) || 4185 OHCI_PAGE_OFFSET(segs[seg].ds_addr) || 4186 len > seglen + segs[seg].ds_len)) { 4187 4188 DPRINTF(("ohci_device_isoc_enter: need aux len %#x dma %#x seglen %#x nextseg %#x\n", len, segdmaadr, seglen, (unsigned)segs[seg].ds_addr)); 4189 /* need aux memory */ 4190 useaux = 1; 4191 if (ncur > 0) { 4192 /* doesn't fit for now */ 4193 break; 4194 } else { 4195 goto doaux; /* shortcut */ 4196 } 4197 } else { /* len > seglen */ 4198 /* the frame ends in the next segment */ 4199 physend = segs[seg].ds_addr + 4200 (len - seglen - 1); 4201 dataphys = segdmaadr; 4202 } 4203 } 4204 4205 if (useaux) { 4206 doaux: 4207 USB_KASSERT(ncur == 0); /* for simplicity */ 4208 4209 /* need aux memory */ 4210 auxdma = ohci_aux_dma_alloc(&OXFER(xfer)->aux, 4211 &bufptr, len, &sitd->ad); 4212 4213 /* prepare aux DMA */ 4214 if (!isread) 4215 usb_bufptr_wr(&bufptr, 4216 sitd->ad.aux_kern, len, is_mbuf); 4217 dataphys = auxdma; 4218 physend = dataphys + len - 1; 4219 4220 useaux = 0; 4221 } 4222 4223 if (ncur == 0) { 4224 sitd->itd.itd_bp0 = HTOO32(dataphys); 4225 } else { 4226 /* check start of new page */ 4227 if (OHCI_PAGE_OFFSET(dataphys) == 0) 4228 npagecross++; 4229 } 4230 4231 sitd->itd.itd_offset[ncur] = 4232 HTOO16(OHCI_ITD_MK_OFFS(npagecross, dataphys)); 4233 4234 if (OHCI_PAGE(dataphys) != OHCI_PAGE(physend)) 4235 npagecross++; 4236 if (npagecross > 1 || 4237 ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) && 4238 npagecross == 1 && 4239 OHCI_PAGE_OFFSET(physend) == OHCI_PAGE_SIZE - 1)) { 4240 /* the frame doesn't fit in the ITD */ 4241 physend = prevphysend; 4242 break; 4243 } 4244 4245 /* the frame is handled */ 4246 seglen -= len; 4247 segdmaadr += len; 4248 usb_bufptr_advance(&bufptr, len, is_mbuf); 4249 prevphysend = physend; 4250 4251 i++; 4252 ncur++; 4253 4254 } while (ncur < OHCI_ITD_NOFFSET && i < nframes); 4255 4256 /* Allocate next ITD */ 4257 nsitd = ohci_alloc_sitd(sc); 4258 if (nsitd == NULL) { 4259 /* XXX what now? */ 4260 printf("%s: isoc TD alloc failed\n", 4261 USBDEVNAME(sc->sc_bus.bdev)); 4262 return; 4263 } 4264 4265 /* Fill out remaining fields of current ITD */ 4266 sitd->itd.itd_be = HTOO32(physend); 4267 sitd->nextitd = nsitd; 4268 dmaadr = OHCI_SITD_DMAADDR(nsitd); 4269 sitd->itd.itd_nextitd = HTOO32(dmaadr); 4270 sitd->xfer = xfer; 4271 4272 if (i < nframes) { 4273 sitd->itd.itd_flags = HTOO32( 4274 OHCI_ITD_NOCC | 4275 OHCI_ITD_SET_SF(iso->next) | 4276 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 4277 OHCI_ITD_SET_FC(ncur)); 4278 sitd->flags = OHCI_ITD_ACTIVE; 4279 } else { 4280 sitd->itd.itd_flags = HTOO32( 4281 OHCI_ITD_NOCC | 4282 OHCI_ITD_SET_SF(iso->next) | 4283 OHCI_ITD_SET_DI(0) | 4284 OHCI_ITD_SET_FC(ncur)); 4285 sitd->flags = OHCI_CALL_DONE | OHCI_ITD_ACTIVE; 4286 } 4287 iso->next = (uint16_t)(iso->next + ncur); 4288 4289 OHCI_SITD_SYNC(sc, sitd, 4290 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4291 sitd = nsitd; 4292 } 4293 4294 iso->inuse += nframes; 4295 4296 /* XXX pretend we did it all */ 4297 xfer->actlen = 0; 4298 for (i = 0; i < nframes; i++) 4299 xfer->actlen += xfer->frlengths[i]; 4300 4301 xfer->status = USBD_IN_PROGRESS; 4302 4303 #ifdef USB_DEBUG 4304 if (ohcidebug > 5) { 4305 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4306 offsetof(struct ohci_hcca, hcca_frame_number), 4307 sizeof(sc->sc_hcca->hcca_frame_number), 4308 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4309 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 4310 O32TOH(sc->sc_hcca->hcca_frame_number))); 4311 ohci_dump_itds(sc, xfer->hcpriv); 4312 ohci_dump_ed(sc, sed); 4313 } 4314 #endif 4315 4316 /* sync aux */ 4317 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, 4318 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4319 4320 s = splusb(); 4321 opipe->tail.itd = sitd; 4322 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 4323 dmaadr = OHCI_SITD_DMAADDR(sitd); 4324 sed->ed.ed_tailp = HTOO32(dmaadr); 4325 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4326 splx(s); 4327 4328 #ifdef USB_DEBUG 4329 if (ohcidebug > 5) { 4330 delay(150000); 4331 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4332 offsetof(struct ohci_hcca, hcca_frame_number), 4333 sizeof(sc->sc_hcca->hcca_frame_number), 4334 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4335 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 4336 O32TOH(sc->sc_hcca->hcca_frame_number))); 4337 ohci_dump_itds(sc, xfer->hcpriv); 4338 ohci_dump_ed(sc, sed); 4339 } 4340 #endif 4341 } 4342 4343 usbd_status 4344 ohci_device_isoc_start(usbd_xfer_handle xfer) 4345 { 4346 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 4347 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 4348 ohci_soft_ed_t *sed; 4349 int s; 4350 4351 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 4352 4353 if (sc->sc_dying) 4354 return (USBD_IOERROR); 4355 4356 #ifdef DIAGNOSTIC 4357 if (xfer->status != USBD_IN_PROGRESS) 4358 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 4359 #endif 4360 4361 /* XXX anything to do? */ 4362 4363 s = splusb(); 4364 sed = opipe->sed; /* Turn off ED skip-bit to start processing */ 4365 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* ED's ITD list.*/ 4366 splx(s); 4367 4368 return (USBD_IN_PROGRESS); 4369 } 4370 4371 void 4372 ohci_device_isoc_abort(usbd_xfer_handle xfer) 4373 { 4374 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 4375 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 4376 ohci_soft_ed_t *sed; 4377 ohci_soft_itd_t *sitd, *tmp_sitd; 4378 ohci_physaddr_t dmaadr; 4379 int s,undone,num_sitds; 4380 4381 s = splusb(); 4382 opipe->aborting = 1; 4383 4384 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 4385 4386 /* Transfer is already done. */ 4387 if (xfer->status != USBD_NOT_STARTED && 4388 xfer->status != USBD_IN_PROGRESS) { 4389 splx(s); 4390 printf("ohci_device_isoc_abort: early return\n"); 4391 return; 4392 } 4393 4394 /* Give xfer the requested abort code. */ 4395 xfer->status = USBD_CANCELLED; 4396 4397 sed = opipe->sed; 4398 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 4399 OHCI_SED_SYNC2(sc, sed, 4400 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4401 BUS_DMASYNC_PREWRITE); 4402 4403 num_sitds = 0; 4404 sitd = xfer->hcpriv; 4405 #ifdef DIAGNOSTIC 4406 if (sitd == NULL) { 4407 splx(s); 4408 printf("ohci_device_isoc_abort: hcpriv==0\n"); 4409 return; 4410 } 4411 #endif 4412 for (; sitd != NULL && sitd->xfer == xfer; sitd = sitd->nextitd) { 4413 num_sitds++; 4414 #ifdef DIAGNOSTIC 4415 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 4416 sitd->isdone = 1; 4417 #endif 4418 } 4419 4420 splx(s); 4421 4422 /* 4423 * Each sitd has up to OHCI_ITD_NOFFSET transfers, each can 4424 * take a usb 1ms cycle. Conservatively wait for it to drain. 4425 * Even with DMA done, it can take awhile for the "batch" 4426 * delivery of completion interrupts to occur thru the controller. 4427 */ 4428 4429 do { 4430 usb_delay_ms(&sc->sc_bus, 2*(num_sitds*OHCI_ITD_NOFFSET)); 4431 4432 undone = 0; 4433 tmp_sitd = xfer->hcpriv; 4434 for (; tmp_sitd != NULL && tmp_sitd->xfer == xfer; 4435 tmp_sitd = tmp_sitd->nextitd) { 4436 OHCI_SITD_SYNC(sc, tmp_sitd, 4437 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4438 if (OHCI_CC_NO_ERROR == 4439 OHCI_ITD_GET_CC(O32TOH(tmp_sitd->itd.itd_flags)) && 4440 tmp_sitd->flags & OHCI_ITD_ACTIVE && 4441 (tmp_sitd->flags & OHCI_ITD_INTFIN) == 0) 4442 undone++; 4443 } 4444 } while (undone != 0); 4445 4446 #if 0 4447 /* Free the sitds */ 4448 for (sitd = xfer->hcpriv; sitd->xfer == xfer; 4449 sitd = sitdnext) { 4450 sitdnext = sitd->nextitd; 4451 ohci_free_sitd(sc, sitd); 4452 } 4453 4454 /* free aux memory if any */ 4455 ohci_aux_mem_init(&OXFER(xfer)->aux); 4456 #endif 4457 4458 s = splusb(); 4459 4460 /* Run callback. */ 4461 ohci_transfer_complete(xfer, 0); 4462 4463 /* There is always a `next' sitd so link it up. */ 4464 dmaadr = OHCI_SITD_DMAADDR(sitd); 4465 sed->ed.ed_headp = HTOO32(dmaadr); 4466 4467 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 4468 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4469 #if 0 /* above should be like this? */ 4470 OHCI_SED_SYNC2(sc, sed, 4471 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4472 BUS_DMASYNC_PREWRITE); 4473 #endif 4474 4475 splx(s); 4476 } 4477 4478 void 4479 ohci_device_isoc_done(usbd_xfer_handle xfer) 4480 { 4481 /* This null routine corresponds to non-isoc "done()" routines 4482 * that free the stds associated with an xfer after a completed 4483 * xfer interrupt. However, in the case of isoc transfers, the 4484 * sitds associated with the transfer have already been processed 4485 * and reallocated for the next iteration by 4486 * "ohci_device_isoc_transfer()". 4487 * 4488 * Routine "usb_transfer_complete()" is called at the end of every 4489 * relevant usb interrupt. "usb_transfer_complete()" indirectly 4490 * calls 1) "ohci_device_isoc_transfer()" (which keeps pumping the 4491 * pipeline by setting up the next transfer iteration) and 2) then 4492 * calls "ohci_device_isoc_done()". Isoc transfers have not been 4493 * working for the ohci usb because this routine was trashing the 4494 * xfer set up for the next iteration (thus, only the first 4495 * UGEN_NISOREQS xfers outstanding on an open would work). Perhaps 4496 * this could all be re-factored, but that's another pass... 4497 */ 4498 } 4499 4500 usbd_status 4501 ohci_setup_isoc(usbd_pipe_handle pipe) 4502 { 4503 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4504 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4505 struct iso *iso = &opipe->u.iso; 4506 int s; 4507 4508 iso->next = -1; 4509 iso->inuse = 0; 4510 4511 s = splusb(); 4512 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 4513 splx(s); 4514 4515 return (USBD_NORMAL_COMPLETION); 4516 } 4517 4518 void 4519 ohci_device_isoc_close(usbd_pipe_handle pipe) 4520 { 4521 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4522 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4523 ohci_soft_ed_t *sed; 4524 4525 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 4526 4527 sed = opipe->sed; 4528 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* Stop device. */ 4529 OHCI_SED_SYNC2(sc, sed, 4530 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4531 BUS_DMASYNC_PREWRITE); 4532 4533 ohci_close_pipe(pipe, sc->sc_isoc_head); /* Stop isoc list, free ED.*/ 4534 4535 /* up to NISOREQs xfers still outstanding. */ 4536 4537 #ifdef DIAGNOSTIC 4538 opipe->tail.itd->isdone = 1; 4539 #endif 4540 ohci_free_sitd_norsv(sc, opipe->tail.itd); /* Next `avail free' sitd.*/ 4541 } 4542
Indexes created Fri Oct 03 02:09:57 GMT 2025