ohci.c revision 1.182.12.4
1 /* $NetBSD: ohci.c,v 1.182.12.4 2008/05/21 05:26:13 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology. 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Charles M. Hannum. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * USB Open Host Controller driver. 44 * 45 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 46 * USB spec: http://www.usb.org/developers/docs/ 47 */ 48 49 #include <sys/cdefs.h> 50 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.182.12.4 2008/05/21 05:26:13 itohy Exp $"); 51 /* __FBSDID("$FreeBSD: src/sys/dev/usb/ohci.c,v 1.167 2006/10/19 01:15:58 iedowse Exp $"); */ 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #if defined(__NetBSD__) || defined(__OpenBSD__) 58 #include <sys/device.h> 59 #include <sys/select.h> 60 #include <uvm/uvm_extern.h> 61 #elif defined(__FreeBSD__) 62 #include <sys/endian.h> 63 #include <sys/module.h> 64 #include <sys/bus.h> 65 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 66 #include <machine/cpu.h> 67 #endif 68 #endif 69 #include <sys/proc.h> 70 #include <sys/queue.h> 71 72 #include <machine/bus.h> 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ohcireg.h> 82 #include <dev/usb/ohcivar.h> 83 84 #if defined(__FreeBSD__) 85 #include <sys/sysctl.h> 86 87 #define delay(d) DELAY(d) 88 #endif 89 90 #if defined(__OpenBSD__) 91 struct cfdriver ohci_cd = { 92 NULL, "ohci", DV_DULL 93 }; 94 #endif 95 96 #ifdef USB_DEBUG 97 #define DPRINTF(x) if (ohcidebug) logprintf x 98 #define DPRINTFN(n,x) if (ohcidebug>(n)) logprintf x 99 int ohcidebug = 0; 100 #ifdef __FreeBSD__ 101 SYSCTL_NODE(_hw_usb, OID_AUTO, ohci, CTLFLAG_RW, 0, "USB ohci"); 102 SYSCTL_INT(_hw_usb_ohci, OID_AUTO, debug, CTLFLAG_RW, 103 &ohcidebug, 0, "ohci debug level"); 104 #endif 105 #ifndef __NetBSD__ 106 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 107 #endif 108 #else 109 #define DPRINTF(x) 110 #define DPRINTFN(n,x) 111 #endif 112 113 /* 114 * The OHCI controller is either little endian or host endian, 115 * so on big endian machines with little endian controller 116 * the data strored in memory needs to be swapped. 117 */ 118 #define O16TOH(val) (sc->sc_endian ? (val) : le16toh(val)) 119 #define O32TOH(val) (sc->sc_endian ? (val) : le32toh(val)) 120 #define HTOO16(val) (sc->sc_endian ? (val) : htole16(val)) 121 #define HTOO32(val) (sc->sc_endian ? (val) : htole32(val)) 122 123 struct ohci_pipe; 124 125 Static void ohci_free_desc_chunks(ohci_softc_t *, 126 struct ohci_mdescs *); 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static usbd_status ohci_grow_std(ohci_softc_t *); 131 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 132 Static ohci_soft_td_t *ohci_alloc_std_norsv(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_norsv(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static usbd_status ohci_grow_sitd(ohci_softc_t *); 137 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 138 Static ohci_soft_itd_t *ohci_alloc_sitd_norsv(ohci_softc_t *); 139 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 140 Static void ohci_free_sitd_norsv(ohci_softc_t *,ohci_soft_itd_t *); 141 142 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 143 ohci_soft_td_t *); 144 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 145 ohci_softc_t *, int, int, usbd_xfer_handle, 146 ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(usbd_pipe_handle); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 152 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 153 154 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 155 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 156 ohci_soft_ed_t *); 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 160 Static ohci_soft_td_t *ohci_find_td(ohci_softc_t *, ohci_physaddr_t); 161 Static ohci_soft_itd_t *ohci_find_itd(ohci_softc_t *, ohci_physaddr_t); 162 163 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 164 Static void ohci_device_isoc_enter(usbd_xfer_handle); 165 166 Static usbd_status ohci_prealloc(struct ohci_softc *, 167 struct ohci_xfer *, size_t, int); 168 Static usbd_status ohci_allocm(struct usbd_bus *, usbd_xfer_handle, 169 void *buf, size_t); 170 Static void ohci_freem(struct usbd_bus *, usbd_xfer_handle, 171 enum usbd_waitflg); 172 173 Static usbd_status ohci_map_alloc(usbd_xfer_handle); 174 Static void ohci_map_free(usbd_xfer_handle); 175 Static void ohci_mapm(usbd_xfer_handle, void *, size_t); 176 Static usbd_status ohci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 177 Static void ohci_unmapm(usbd_xfer_handle); 178 179 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *, usbd_pipe_handle, 180 enum usbd_waitflg); 181 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 182 183 Static void ohci_transfer_complete(usbd_xfer_handle, int); 184 185 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 187 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 188 Static void ohci_root_ctrl_close(usbd_pipe_handle); 189 Static void ohci_root_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 192 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 193 Static void ohci_root_intr_abort(usbd_xfer_handle); 194 Static void ohci_root_intr_close(usbd_pipe_handle); 195 Static void ohci_root_intr_done(usbd_xfer_handle); 196 197 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 198 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 199 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 200 Static void ohci_device_ctrl_close(usbd_pipe_handle); 201 Static void ohci_device_ctrl_done(usbd_xfer_handle); 202 203 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 204 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 205 Static void ohci_device_bulk_abort(usbd_xfer_handle); 206 Static void ohci_device_bulk_close(usbd_pipe_handle); 207 Static void ohci_device_bulk_done(usbd_xfer_handle); 208 209 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 210 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 211 Static void ohci_device_intr_abort(usbd_xfer_handle); 212 Static void ohci_device_intr_close(usbd_pipe_handle); 213 Static void ohci_device_intr_done(usbd_xfer_handle); 214 215 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 216 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 217 Static void ohci_device_isoc_abort(usbd_xfer_handle); 218 Static void ohci_device_isoc_close(usbd_pipe_handle); 219 Static void ohci_device_isoc_done(usbd_xfer_handle); 220 221 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 222 struct ohci_pipe *pipe, int ival); 223 Static usbd_status ohci_device_intr_insert(ohci_softc_t *sc, 224 usbd_xfer_handle xfer); 225 226 Static int ohci_str(usb_string_descriptor_t *, int, const char *); 227 228 Static void ohci_timeout(void *); 229 Static void ohci_timeout_task(void *); 230 Static void ohci_rhsc_enable(void *); 231 232 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 233 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 234 235 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 236 Static void ohci_noop(usbd_pipe_handle pipe); 237 238 Static usbd_status ohci_controller_init(ohci_softc_t *sc); 239 240 Static void ohci_aux_mem_init(struct ohci_aux_mem *); 241 Static usbd_status ohci_aux_mem_alloc(ohci_softc_t *, 242 struct ohci_aux_mem *, 243 int /*naux*/, int /*maxp*/); 244 Static void ohci_aux_mem_free(ohci_softc_t *, 245 struct ohci_aux_mem *); 246 Static bus_addr_t ohci_aux_dma_alloc(struct ohci_aux_mem *, 247 const union usb_bufptr *, int, 248 struct usb_aux_desc *); 249 Static void ohci_aux_dma_complete(struct usb_aux_desc *, 250 struct ohci_aux_mem *, 251 int /*is_mbuf*/, int /*isread*/); 252 Static void ohci_aux_dma_sync(ohci_softc_t *, 253 struct ohci_aux_mem *, int /*op*/); 254 255 #ifdef USB_DEBUG 256 Static void ohci_dumpregs(ohci_softc_t *); 257 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 258 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 259 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 260 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 261 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 262 #endif 263 264 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 265 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 266 #define OWRITE1(sc, r, x) \ 267 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 268 #define OWRITE2(sc, r, x) \ 269 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 270 #define OWRITE4(sc, r, x) \ 271 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 272 static __inline uint8_t 273 OREAD1(ohci_softc_t *sc, bus_size_t r) 274 { 275 276 OBARR(sc); 277 return bus_space_read_1(sc->iot, sc->ioh, r); 278 } 279 280 static __inline uint16_t 281 OREAD2(ohci_softc_t *sc, bus_size_t r) 282 { 283 284 OBARR(sc); 285 return bus_space_read_2(sc->iot, sc->ioh, r); 286 } 287 288 static __inline uint32_t 289 OREAD4(ohci_softc_t *sc, bus_size_t r) 290 { 291 292 OBARR(sc); 293 return bus_space_read_4(sc->iot, sc->ioh, r); 294 } 295 296 /* Reverse the bits in a value 0 .. 31 */ 297 Static u_int8_t revbits[OHCI_NO_INTRS] = 298 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 299 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 300 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 301 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 302 303 struct ohci_pipe { 304 struct usbd_pipe pipe; 305 ohci_soft_ed_t *sed; 306 u_int32_t aborting; 307 union { 308 ohci_soft_td_t *td; 309 ohci_soft_itd_t *itd; 310 } tail; 311 /* Info needed for different pipe kinds. */ 312 union { 313 /* Control pipe */ 314 struct { 315 usb_dma_t reqdma; 316 u_int length; 317 ohci_soft_td_t *setup, *data, *stat; 318 } ctl; 319 /* Interrupt pipe */ 320 struct { 321 int nslots; 322 int pos; 323 } intr; 324 /* Bulk pipe */ 325 struct { 326 u_int length; 327 int isread; 328 } bulk; 329 /* Iso pipe */ 330 struct iso { 331 int next, inuse; 332 } iso; 333 } u; 334 }; 335 336 #define OHCI_INTR_ENDPT 1 337 338 Static const struct usbd_bus_methods ohci_bus_methods = { 339 ohci_open, 340 ohci_softintr, 341 ohci_poll, 342 ohci_allocm, 343 ohci_freem, 344 ohci_map_alloc, 345 ohci_map_free, 346 ohci_mapm, 347 ohci_mapm_mbuf, 348 ohci_unmapm, 349 ohci_allocx, 350 ohci_freex, 351 }; 352 353 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 354 ohci_root_ctrl_transfer, 355 ohci_root_ctrl_start, 356 ohci_root_ctrl_abort, 357 ohci_root_ctrl_close, 358 ohci_noop, 359 ohci_root_ctrl_done, 360 }; 361 362 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 363 ohci_root_intr_transfer, 364 ohci_root_intr_start, 365 ohci_root_intr_abort, 366 ohci_root_intr_close, 367 ohci_noop, 368 ohci_root_intr_done, 369 }; 370 371 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 372 ohci_device_ctrl_transfer, 373 ohci_device_ctrl_start, 374 ohci_device_ctrl_abort, 375 ohci_device_ctrl_close, 376 ohci_noop, 377 ohci_device_ctrl_done, 378 }; 379 380 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 381 ohci_device_intr_transfer, 382 ohci_device_intr_start, 383 ohci_device_intr_abort, 384 ohci_device_intr_close, 385 ohci_device_clear_toggle, 386 ohci_device_intr_done, 387 }; 388 389 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 390 ohci_device_bulk_transfer, 391 ohci_device_bulk_start, 392 ohci_device_bulk_abort, 393 ohci_device_bulk_close, 394 ohci_device_clear_toggle, 395 ohci_device_bulk_done, 396 }; 397 398 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 399 ohci_device_isoc_transfer, 400 ohci_device_isoc_start, 401 ohci_device_isoc_abort, 402 ohci_device_isoc_close, 403 ohci_noop, 404 ohci_device_isoc_done, 405 }; 406 407 #if defined(__NetBSD__) || defined(__OpenBSD__) 408 int 409 ohci_activate(device_t self, enum devact act) 410 { 411 struct ohci_softc *sc = (struct ohci_softc *)self; 412 int rv = 0; 413 414 switch (act) { 415 case DVACT_ACTIVATE: 416 return (EOPNOTSUPP); 417 418 case DVACT_DEACTIVATE: 419 if (sc->sc_child != NULL) 420 rv = config_deactivate(sc->sc_child); 421 sc->sc_dying = 1; 422 break; 423 } 424 return (rv); 425 } 426 #endif 427 428 int 429 ohci_detach(struct ohci_softc *sc, int flags) 430 { 431 int rv = 0; 432 usbd_xfer_handle xfer; 433 434 sc->sc_dying = 1; 435 436 #if defined(__NetBSD__) || defined(__OpenBSD__) 437 if (sc->sc_child != NULL) 438 rv = config_detach(sc->sc_child, flags); 439 440 if (rv != 0) 441 return (rv); 442 #endif 443 444 if (sc->sc_bus.methods == NULL) 445 return (rv); /* attach has been aborted */ 446 447 usb_uncallout(sc->sc_tmo_rhsc, ohci_rhsc_enable, sc); 448 449 #if defined(__NetBSD__) || defined(__OpenBSD__) 450 powerhook_disestablish(sc->sc_powerhook); 451 shutdownhook_disestablish(sc->sc_shutdownhook); 452 #endif 453 454 #if defined(__NetBSD__) || defined(__OpenBSD__) 455 /* Don't touch hardware if it has already been gone. */ 456 if ((flags & DETACH_FORCE) == 0) 457 #endif 458 { 459 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 460 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 461 } 462 463 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 464 465 #if 0 /* freed by ohci_free_desc_chunks(sc, &sc->sc_sed_chunks) below */ 466 for (i = 0; i < OHCI_NO_EDS; i++) 467 ohci_free_sed(sc, sc->sc_eds[i]); 468 ohci_free_sed(sc, sc->sc_isoc_head); 469 ohci_free_sed(sc, sc->sc_bulk_head); 470 ohci_free_sed(sc, sc->sc_ctrl_head); 471 #endif 472 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 473 474 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 475 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 476 usb_clean_buffer_dma(&sc->sc_dmatag, &OXFER(xfer)->dmabuf); 477 free(xfer, M_USB); 478 } 479 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 480 ohci_free_desc_chunks(sc, &sc->sc_std_chunks); 481 ohci_free_desc_chunks(sc, &sc->sc_sitd_chunks); 482 usb_dma_tag_finish(&sc->sc_dmatag); 483 484 return (rv); 485 } 486 487 Static void 488 ohci_free_desc_chunks(ohci_softc_t *sc, struct ohci_mdescs *c) 489 { 490 struct ohci_mem_desc *om; 491 492 while ((om = SIMPLEQ_FIRST(c)) != NULL) { 493 SIMPLEQ_REMOVE_HEAD(c, om_next); 494 usb_freemem(&sc->sc_dmatag, &om->om_dma); 495 } 496 } 497 498 ohci_soft_ed_t * 499 ohci_alloc_sed(ohci_softc_t *sc) 500 { 501 ohci_soft_ed_t *sed; 502 usbd_status err; 503 int i, offs; 504 usb_dma_t dma; 505 struct ohci_mem_desc *om; 506 507 if (sc->sc_freeeds == NULL) { 508 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 509 err = usb_allocmem(&sc->sc_dmatag, 510 OHCI_SED_SIZE*OHCI_SED_CHUNK + sizeof(struct ohci_mem_desc), 511 OHCI_ED_ALIGN, &dma); 512 if (err) 513 return (NULL); 514 om = KERNADDR(&dma, OHCI_SED_SIZE * OHCI_SED_CHUNK); 515 om->om_top = KERNADDR(&dma, 0); 516 om->om_topdma = DMAADDR(&dma, 0); 517 om->om_dma = dma; 518 SIMPLEQ_INSERT_HEAD(&sc->sc_sed_chunks, om, om_next); 519 for(i = 0; i < OHCI_SED_CHUNK; i++) { 520 offs = i * OHCI_SED_SIZE; 521 sed = KERNADDR(&dma, offs); 522 sed->oe_mdesc = om; 523 sed->next = sc->sc_freeeds; 524 sc->sc_freeeds = sed; 525 } 526 } 527 sed = sc->sc_freeeds; 528 sc->sc_freeeds = sed->next; 529 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 530 sed->next = 0; 531 return (sed); 532 } 533 534 void 535 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 536 { 537 sed->next = sc->sc_freeeds; 538 sc->sc_freeeds = sed; 539 } 540 541 Static usbd_status 542 ohci_grow_std(ohci_softc_t *sc) 543 { 544 usb_dma_t dma; 545 struct ohci_mem_desc *om; 546 ohci_soft_td_t *std; 547 usbd_status err; 548 int i, s, offs; 549 550 DPRINTFN(2, ("ohci_grow_std: allocating chunk\n")); 551 err = usb_allocmem(&sc->sc_dmatag, 552 OHCI_STD_SIZE*OHCI_STD_CHUNK + sizeof(struct ohci_mem_desc), 553 OHCI_TD_ALIGN, &dma); 554 if (err) 555 return (err); 556 om = KERNADDR(&dma, OHCI_STD_SIZE * OHCI_STD_CHUNK); 557 om->om_top = KERNADDR(&dma, 0); 558 om->om_topdma = DMAADDR(&dma, 0); 559 om->om_dma = dma; 560 s = splusb(); 561 SIMPLEQ_INSERT_HEAD(&sc->sc_std_chunks, om, om_next); 562 for(i = 0; i < OHCI_STD_CHUNK; i++) { 563 offs = i * OHCI_STD_SIZE; 564 std = KERNADDR(&dma, offs); 565 std->ot_mdesc = om; 566 std->nexttd = sc->sc_freetds; 567 std->ad.aux_len = 0; 568 sc->sc_freetds = std; 569 sc->sc_nfreetds++; 570 } 571 splx(s); 572 573 return (USBD_NORMAL_COMPLETION); 574 } 575 576 ohci_soft_td_t * 577 ohci_alloc_std(ohci_softc_t *sc) 578 { 579 ohci_soft_td_t *std; 580 int s; 581 582 s = splusb(); 583 584 #ifdef DIAGNOSTIC 585 if (sc->sc_freetds == NULL) 586 panic("ohci_alloc_std: %d", sc->sc_nfreetds); 587 #endif 588 std = sc->sc_freetds; 589 sc->sc_freetds = std->nexttd; 590 splx(s); 591 memset(&std->td, 0, sizeof(ohci_td_t)); 592 std->nexttd = NULL; 593 std->xfer = NULL; 594 std->flags = 0; 595 596 return (std); 597 } 598 599 Static ohci_soft_td_t * 600 ohci_alloc_std_norsv(ohci_softc_t *sc) 601 { 602 int s; 603 604 s = splusb(); 605 if (sc->sc_nfreetds < 1) 606 if (ohci_grow_std(sc)) 607 return (NULL); 608 sc->sc_nfreetds--; 609 splx(s); 610 return (ohci_alloc_std(sc)); 611 } 612 613 void 614 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 615 { 616 int s; 617 618 s = splusb(); 619 std->flags = OHCI_TD_FREE; 620 std->nexttd = sc->sc_freetds; 621 sc->sc_freetds = std; 622 splx(s); 623 } 624 625 Static void 626 ohci_free_std_norsv(ohci_softc_t *sc, ohci_soft_td_t *std) 627 { 628 int s; 629 630 ohci_free_std(sc, std); 631 s = splusb(); 632 sc->sc_nfreetds++; 633 splx(s); 634 } 635 636 usbd_status 637 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 638 int alen, int rd, usbd_xfer_handle xfer, 639 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 640 { 641 ohci_soft_td_t *next, *cur, *end; 642 ohci_physaddr_t tddma, segdmaadr, dmaend; 643 u_int32_t tdflags; 644 int len, maxp, curlen, seg, seglen, seglen1; 645 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 646 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 647 int nsegs = USB_BUFFER_NSEGS(ub); 648 u_int16_t flags = xfer->flags; 649 usb_endpoint_descriptor_t *ed; 650 int needaux; 651 union usb_bufptr bufptr; 652 bus_addr_t auxdma; 653 654 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 655 656 len = alen; 657 cur = sp; 658 end = NULL; 659 660 ed = opipe->pipe.endpoint->edesc; 661 maxp = UE_MAXPKTSZ(ed); 662 tdflags = HTOO32( 663 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 664 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 665 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_SET_DI(6)); 666 /* 667 * aux memory is possibly required if 668 * buffer has more than one segments, 669 * the transfer direction is OUT, 670 * and 671 * buffer is an mbuf chain, or 672 * buffer is not maxp aligned 673 */ 674 needaux = 675 nsegs > 1 && 676 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT && 677 ((xfer->rqflags & URQ_DEV_MAP_MBUF) || 678 (maxp & (maxp - 1)) != 0 /* maxp is not a power of 2 */ || 679 (segs[0].ds_addr & (maxp - 1)) != 0 /* buffer is unaligned */); 680 681 if (needaux) { 682 usb_bufptr_init(&bufptr, xfer); 683 } 684 685 seg = 0; 686 seglen = 0; 687 segdmaadr = 0; /* XXX -Wuninitialized */ 688 while (len > 0) { 689 /* sync last entry */ 690 if (end) 691 OHCI_STD_SYNC(sc, end, 692 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 693 694 next = ohci_alloc_std(sc); 695 if (next == NULL) 696 goto nomem; 697 698 /* 699 * The OHCI hardware can handle at most one 4K crossing. 700 * The OHCI spec says: If during the data transfer the buffer 701 * address contained in the HC's working copy of 702 * CurrentBufferPointer crosses a 4K boundary, the upper 20 703 * bits of Buffer End are copied to the working value of 704 * CurrentBufferPointer causing the next buffer address to 705 * be the 0th byte in the same 4K page that contains the 706 * last byte of the buffer (the 4K boundary crossing may 707 * occur within a data packet transfer.) 708 */ 709 710 /* 711 * 1. skip handled segments 712 * 2. gather segments that are continuous in DMA address 713 * (Does this make any sense?) 714 */ 715 if (seglen <= 0) { 716 USB_KASSERT2(seg < nsegs, 717 ("ohci_alloc_std_chain: overrun")); 718 do { 719 seglen1 = seglen; 720 seglen += segs[seg].ds_len; 721 if (seglen1 <= 0 && seglen > 0) 722 segdmaadr = segs[seg].ds_addr - seglen1; 723 } while (++seg < nsegs && (seglen <= 0 || 724 segdmaadr + seglen == segs[seg].ds_addr)); 725 726 if (seglen > len) 727 seglen = len; 728 } 729 730 if (needaux && seglen < len && seglen < maxp) { 731 /* need aux -- a packet is not contiguous */ 732 curlen = len < maxp ? len : maxp; 733 USB_KASSERT(seglen < curlen); 734 auxdma = ohci_aux_dma_alloc(&OXFER(xfer)->aux, &bufptr, 735 curlen, &cur->ad); 736 737 /* prepare aux DMA */ 738 usb_bufptr_wr(&bufptr, cur->ad.aux_kern, 739 curlen, xfer->rqflags & URQ_DEV_MAP_MBUF); 740 cur->td.td_cbp = HTOO32(auxdma); 741 cur->td.td_be = HTOO32(auxdma + curlen - 1); 742 743 /* handled segments will be skipped above */ 744 } else { 745 #ifdef DIAGNOSTIC 746 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT) 747 USB_KASSERT(seglen >= maxp || seglen >= len); 748 #endif 749 curlen = seglen; 750 dmaend = segdmaadr + curlen; 751 if ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) == 0) 752 dmaend--; 753 dmaend = OHCI_PAGE(dmaend); 754 755 if (OHCI_PAGE(segdmaadr) != dmaend && 756 OHCI_PAGE(segdmaadr) + OHCI_PAGE_SIZE != dmaend) { 757 /* must use multiple TDs, fill as much as possible. */ 758 curlen = 2 * OHCI_PAGE_SIZE - 759 (segdmaadr & (OHCI_PAGE_SIZE-1)); 760 761 if (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) 762 curlen--; 763 } 764 765 /* the length must be a multiple of the max size */ 766 if (curlen < len) 767 curlen -= curlen % maxp; 768 USB_KASSERT(curlen); 769 USB_KASSERT2(curlen <= seglen, 770 ("ohci_alloc_std_chain: curlen %d > seglen %d", 771 curlen, len)); 772 773 DPRINTFN(4,("ohci_alloc_std_chain: segdmaadr=0x%08x " 774 "dmaend=0x%08x len=%d seglen=%d curlen=%d\n", 775 segdmaadr, segdmaadr + curlen - 1, 776 len, seglen, curlen)); 777 cur->td.td_cbp = HTOO32(segdmaadr); 778 cur->td.td_be = HTOO32(segdmaadr + curlen - 1); 779 } 780 len -= curlen; 781 782 cur->td.td_flags = tdflags; 783 cur->nexttd = next; 784 tddma = OHCI_STD_DMAADDR(next); 785 cur->td.td_nexttd = HTOO32(tddma); 786 cur->len = curlen; 787 cur->flags = OHCI_ADD_LEN; 788 cur->xfer = xfer; 789 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x", 790 O32TOH(cur->td.td_cbp), O32TOH(cur->td.td_be))); 791 seglen -= curlen; 792 segdmaadr += curlen; 793 DPRINTFN(10,("%s\n", seglen < 0 ? " (aux)" : "")); 794 795 if (needaux) 796 usb_bufptr_advance(&bufptr, curlen, 797 xfer->rqflags & URQ_DEV_MAP_MBUF); 798 799 end = cur; 800 cur = next; 801 } 802 if (((flags & USBD_FORCE_SHORT_XFER) || alen == 0) && 803 alen % maxp == 0) { 804 if (end) 805 OHCI_STD_SYNC(sc, end, 806 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 807 808 /* Force a 0 length transfer at the end. */ 809 next = ohci_alloc_std(sc); 810 if (next == NULL) 811 goto nomem; 812 813 cur->td.td_flags = tdflags; 814 cur->td.td_cbp = 0; /* indicate 0 length packet */ 815 cur->nexttd = next; 816 tddma = OHCI_STD_DMAADDR(next); 817 cur->td.td_nexttd = HTOO32(tddma); 818 cur->td.td_be = ~0; 819 cur->len = 0; 820 cur->flags = 0; 821 cur->xfer = xfer; 822 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 823 end = cur; 824 } 825 *ep = end; 826 827 if (needaux) 828 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, BUS_DMASYNC_PREWRITE); 829 830 return (USBD_NORMAL_COMPLETION); 831 832 nomem: 833 /* free chain */ 834 if (end) 835 ohci_free_std_chain(sc, sp->nexttd, end); 836 return (USBD_NOMEM); 837 } 838 839 Static void 840 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 841 ohci_soft_td_t *stdend) 842 { 843 ohci_soft_td_t *p; 844 845 for (; std != stdend; std = p) { 846 p = std->nexttd; 847 ohci_free_std(sc, std); 848 } 849 ohci_free_std(sc, stdend); 850 } 851 852 Static usbd_status 853 ohci_grow_sitd(ohci_softc_t *sc) 854 { 855 usb_dma_t dma; 856 struct ohci_mem_desc *om; 857 ohci_soft_itd_t *sitd; 858 usbd_status err; 859 int i, s, offs; 860 861 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 862 err = usb_allocmem(&sc->sc_dmatag, 863 OHCI_SITD_SIZE*OHCI_SITD_CHUNK + sizeof(struct ohci_mem_desc), 864 OHCI_ITD_ALIGN, &dma); 865 if (err) 866 return (err); 867 om = KERNADDR(&dma, OHCI_SITD_SIZE * OHCI_SITD_CHUNK); 868 om->om_top = KERNADDR(&dma, 0); 869 om->om_topdma = DMAADDR(&dma, 0); 870 om->om_dma = dma; 871 s = splusb(); 872 SIMPLEQ_INSERT_HEAD(&sc->sc_sitd_chunks, om, om_next); 873 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 874 offs = i * OHCI_SITD_SIZE; 875 sitd = KERNADDR(&dma, offs); 876 sitd->oit_mdesc = om; 877 sitd->nextitd = sc->sc_freeitds; 878 sitd->ad.aux_len = 0; 879 sc->sc_freeitds = sitd; 880 sc->sc_nfreeitds++; 881 } 882 splx(s); 883 884 return (USBD_NORMAL_COMPLETION); 885 } 886 887 ohci_soft_itd_t * 888 ohci_alloc_sitd(ohci_softc_t *sc) 889 { 890 ohci_soft_itd_t *sitd; 891 int s; 892 893 #ifdef DIAGNOSTIC 894 if (sc->sc_freeitds == NULL) 895 panic("ohci_alloc_sitd: %d", sc->sc_nfreeitds); 896 #endif 897 898 s = splusb(); 899 sitd = sc->sc_freeitds; 900 sc->sc_freeitds = sitd->nextitd; 901 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 902 sitd->nextitd = NULL; 903 sitd->xfer = NULL; 904 sitd->flags = 0; 905 splx(s); 906 907 #ifdef DIAGNOSTIC 908 sitd->isdone = 0; 909 #endif 910 911 return (sitd); 912 } 913 914 Static ohci_soft_itd_t * 915 ohci_alloc_sitd_norsv(ohci_softc_t *sc) 916 { 917 int s; 918 919 s = splusb(); 920 if (sc->sc_nfreeitds < 1) 921 if (ohci_grow_sitd(sc)) 922 return (NULL); 923 sc->sc_nfreeitds--; 924 splx(s); 925 return (ohci_alloc_sitd(sc)); 926 } 927 928 void 929 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 930 { 931 int s; 932 933 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 934 935 #ifdef DIAGNOSTIC 936 if (!sitd->isdone) { 937 panic("ohci_free_sitd: sitd=%p not done", sitd); 938 return; 939 } 940 /* Warn double free */ 941 sitd->isdone = 0; 942 #endif 943 944 s = splusb(); 945 sitd->flags = OHCI_ITD_FREE; 946 sitd->nextitd = sc->sc_freeitds; 947 sc->sc_freeitds = sitd; 948 splx(s); 949 } 950 951 Static void 952 ohci_free_sitd_norsv(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 953 { 954 int s; 955 956 ohci_free_sitd(sc, sitd); 957 s = splusb(); 958 sc->sc_nfreeitds++; 959 splx(s); 960 } 961 962 usbd_status 963 ohci_init(ohci_softc_t *sc) 964 { 965 ohci_soft_ed_t *sed, *psed; 966 ohci_physaddr_t eddma; 967 usbd_status err; 968 int i; 969 u_int32_t rev; 970 971 DPRINTF(("ohci_init: start\n")); 972 #if defined(__OpenBSD__) 973 printf(","); 974 #else 975 printf("%s:", USBDEVNAME(sc->sc_bus.bdev)); 976 #endif 977 rev = OREAD4(sc, OHCI_REVISION); 978 printf(" OHCI version %d.%d%s\n", OHCI_REV_HI(rev), OHCI_REV_LO(rev), 979 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 980 981 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 982 printf("%s: unsupported OHCI revision\n", 983 USBDEVNAME(sc->sc_bus.bdev)); 984 sc->sc_bus.usbrev = USBREV_UNKNOWN; 985 return (USBD_INVAL); 986 } 987 sc->sc_bus.usbrev = USBREV_1_0; 988 989 SIMPLEQ_INIT(&sc->sc_free_xfers); 990 SIMPLEQ_INIT(&sc->sc_sed_chunks); 991 SIMPLEQ_INIT(&sc->sc_std_chunks); 992 SIMPLEQ_INIT(&sc->sc_sitd_chunks); 993 994 usb_dma_tag_init(&sc->sc_dmatag); 995 996 /* XXX determine alignment by R/W */ 997 /* Allocate the HCCA area. */ 998 err = usb_allocmem(&sc->sc_dmatag, OHCI_HCCA_SIZE, 999 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 1000 if (err) 1001 goto bad1; 1002 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 1003 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 1004 1005 sc->sc_eintrs = OHCI_NORMAL_INTRS; 1006 1007 /* Allocate dummy ED that starts the control list. */ 1008 sc->sc_ctrl_head = ohci_alloc_sed(sc); 1009 if (sc->sc_ctrl_head == NULL) { 1010 err = USBD_NOMEM; 1011 goto bad2; 1012 } 1013 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1014 1015 /* Allocate dummy ED that starts the bulk list. */ 1016 sc->sc_bulk_head = ohci_alloc_sed(sc); 1017 if (sc->sc_bulk_head == NULL) { 1018 err = USBD_NOMEM; 1019 goto bad3; 1020 } 1021 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1022 1023 /* Allocate dummy ED that starts the isochronous list. */ 1024 sc->sc_isoc_head = ohci_alloc_sed(sc); 1025 if (sc->sc_isoc_head == NULL) { 1026 err = USBD_NOMEM; 1027 goto bad3; 1028 } 1029 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1030 1031 /* Allocate all the dummy EDs that make up the interrupt tree. */ 1032 for (i = 0; i < OHCI_NO_EDS; i++) { 1033 sed = ohci_alloc_sed(sc); 1034 if (sed == NULL) { 1035 while (--i >= 0) 1036 ohci_free_sed(sc, sc->sc_eds[i]); 1037 err = USBD_NOMEM; 1038 goto bad3; 1039 } 1040 /* All ED fields are set to 0. */ 1041 sc->sc_eds[i] = sed; 1042 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 1043 if (i != 0) 1044 psed = sc->sc_eds[(i-1) / 2]; 1045 else 1046 psed = sc->sc_isoc_head; 1047 sed->next = psed; 1048 eddma = OHCI_SED_DMAADDR(psed); 1049 sed->ed.ed_nexted = HTOO32(eddma); 1050 } 1051 /* 1052 * Fill HCCA interrupt table. The bit reversal is to get 1053 * the tree set up properly to spread the interrupts. 1054 */ 1055 for (i = 0; i < OHCI_NO_INTRS; i++) { 1056 eddma = OHCI_SED_DMAADDR(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]); 1057 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = HTOO32(eddma); 1058 } 1059 USB_MEM_SYNC(&sc->sc_dmatag, &sc->sc_hccadma, 1060 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1061 1062 #ifdef USB_DEBUG 1063 if (ohcidebug > 15) { 1064 for (i = 0; i < OHCI_NO_EDS; i++) { 1065 printf("ed#%d ", i); 1066 ohci_dump_ed(sc, sc->sc_eds[i]); 1067 } 1068 printf("iso "); 1069 ohci_dump_ed(sc, sc->sc_isoc_head); 1070 } 1071 #endif 1072 1073 err = ohci_controller_init(sc); 1074 if (err != USBD_NORMAL_COMPLETION) 1075 goto bad3; 1076 1077 /* Set up the bus struct. */ 1078 sc->sc_bus.methods = &ohci_bus_methods; 1079 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 1080 1081 #if defined(__NetBSD__) || defined(__OpenBSD__) 1082 sc->sc_control = sc->sc_intre = 0; 1083 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 1084 ohci_power, sc); 1085 sc->sc_shutdownhook = shutdownhook_establish(ohci_shutdown, sc); 1086 #endif 1087 1088 usb_callout_init(sc->sc_tmo_rhsc); 1089 1090 /* Finally, turn on interrupts. */ 1091 DPRINTFN(1,("ohci_init: enabling\n")); 1092 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1093 1094 return (USBD_NORMAL_COMPLETION); 1095 1096 bad3: 1097 ohci_free_desc_chunks(sc, &sc->sc_sed_chunks); 1098 bad2: 1099 usb_freemem(&sc->sc_dmatag, &sc->sc_hccadma); 1100 bad1: 1101 usb_dma_tag_finish(&sc->sc_dmatag); 1102 return (err); 1103 } 1104 1105 Static usbd_status 1106 ohci_controller_init(ohci_softc_t *sc) 1107 { 1108 int i; 1109 u_int32_t s, ctl, rwc, ival, hcr, fm, per, desca, descb; 1110 1111 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 1112 ctl = OREAD4(sc, OHCI_CONTROL); 1113 rwc = ctl & OHCI_RWC; 1114 fm = OREAD4(sc, OHCI_FM_INTERVAL); 1115 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1116 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1117 1118 /* Determine in what context we are running. */ 1119 if (ctl & OHCI_IR) { 1120 /* SMM active, request change */ 1121 DPRINTF(("ohci_init: SMM active, request owner change\n")); 1122 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 1123 (OHCI_OC | OHCI_MIE)) 1124 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 1125 s = OREAD4(sc, OHCI_COMMAND_STATUS); 1126 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 1127 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 1128 usb_delay_ms(&sc->sc_bus, 1); 1129 ctl = OREAD4(sc, OHCI_CONTROL); 1130 } 1131 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 1132 if ((ctl & OHCI_IR) == 0) { 1133 printf("%s: SMM does not respond, resetting\n", 1134 USBDEVNAME(sc->sc_bus.bdev)); 1135 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1136 goto reset; 1137 } 1138 #if 0 1139 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 1140 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 1141 /* BIOS started controller. */ 1142 DPRINTF(("ohci_init: BIOS active\n")); 1143 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 1144 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 1145 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1146 } 1147 #endif 1148 } else { 1149 DPRINTF(("ohci_init: cold started\n")); 1150 reset: 1151 /* Controller was cold started. */ 1152 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1153 } 1154 1155 /* 1156 * This reset should not be necessary according to the OHCI spec, but 1157 * without it some controllers do not start. 1158 */ 1159 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 1160 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 1161 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 1162 1163 /* We now own the host controller and the bus has been reset. */ 1164 1165 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 1166 /* Nominal time for a reset is 10 us. */ 1167 for (i = 0; i < 10; i++) { 1168 delay(10); 1169 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 1170 if (!hcr) 1171 break; 1172 } 1173 if (hcr) { 1174 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 1175 return (USBD_IOERROR); 1176 } 1177 #ifdef USB_DEBUG 1178 if (ohcidebug > 15) 1179 ohci_dumpregs(sc); 1180 #endif 1181 1182 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 1183 1184 /* Set up HC registers. */ 1185 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1186 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_ctrl_head)); 1187 OWRITE4(sc, OHCI_BULK_HEAD_ED, OHCI_SED_DMAADDR(sc->sc_bulk_head)); 1188 /* disable all interrupts and then switch on all desired interrupts */ 1189 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 1190 /* switch on desired functional features */ 1191 ctl = OREAD4(sc, OHCI_CONTROL); 1192 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 1193 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 1194 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 1195 /* And finally start it! */ 1196 OWRITE4(sc, OHCI_CONTROL, ctl); 1197 1198 /* 1199 * The controller is now OPERATIONAL. Set a some final 1200 * registers that should be set earlier, but that the 1201 * controller ignores when in the SUSPEND state. 1202 */ 1203 ival = OHCI_GET_IVAL(fm); 1204 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1205 fm |= OHCI_FSMPS(ival) | ival; 1206 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1207 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1208 OWRITE4(sc, OHCI_PERIODIC_START, per); 1209 1210 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1211 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1212 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1213 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1214 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1215 1216 /* 1217 * The AMD756 requires a delay before re-reading the register, 1218 * otherwise it will occasionally report 0 ports. 1219 */ 1220 sc->sc_noport = 0; 1221 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1222 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1223 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1224 } 1225 1226 #ifdef USB_DEBUG 1227 if (ohcidebug > 5) 1228 ohci_dumpregs(sc); 1229 #endif 1230 return (USBD_NORMAL_COMPLETION); 1231 } 1232 1233 /* 1234 * Allocate a physically contiguous buffer to handle cases where OHCI 1235 * cannot handle a packet because it is not physically contiguous. 1236 */ 1237 Static void 1238 ohci_aux_mem_init(struct ohci_aux_mem *aux) 1239 { 1240 1241 aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0; 1242 } 1243 1244 Static usbd_status 1245 ohci_aux_mem_alloc(ohci_softc_t *sc, struct ohci_aux_mem *aux, 1246 int naux, int maxp) 1247 { 1248 int nchunk, i, j; 1249 usbd_status err; 1250 1251 USB_KASSERT(aux->aux_nchunk == 0); 1252 1253 nchunk = OHCI_NCHUNK(naux, maxp); 1254 for (i = 0; i < nchunk; i++) { 1255 err = usb_allocmem(&sc->sc_dmatag, OHCI_AUX_CHUNK_SIZE, 1256 OHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]); 1257 if (err) { 1258 for (j = 0; j < i; j++) 1259 usb_freemem(&sc->sc_dmatag, 1260 &aux->aux_chunk_dma[j]); 1261 return (err); 1262 } 1263 } 1264 1265 aux->aux_nchunk = nchunk; 1266 ohci_aux_mem_init(aux); 1267 1268 return (USBD_NORMAL_COMPLETION); 1269 } 1270 1271 Static void 1272 ohci_aux_mem_free(ohci_softc_t *sc, struct ohci_aux_mem *aux) 1273 { 1274 int i; 1275 1276 for (i = 0; i < aux->aux_nchunk; i++) 1277 usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]); 1278 1279 aux->aux_nchunk = 0; 1280 } 1281 1282 Static bus_addr_t 1283 ohci_aux_dma_alloc(struct ohci_aux_mem *aux, 1284 const union usb_bufptr *bufptr, int len, 1285 struct usb_aux_desc *ad) 1286 { 1287 bus_addr_t auxdma; 1288 1289 if (aux->aux_chunkoff + len > OHCI_AUX_CHUNK_SIZE) { 1290 aux->aux_curchunk++; 1291 aux->aux_chunkoff = 0; 1292 } 1293 USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk); 1294 1295 auxdma = 1296 DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1297 ad->aux_kern = 1298 KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1299 ad->aux_ptr = *bufptr; 1300 ad->aux_len = len; 1301 1302 aux->aux_chunkoff += len; 1303 aux->aux_naux++; 1304 1305 return auxdma; 1306 } 1307 1308 Static void 1309 ohci_aux_dma_complete(struct usb_aux_desc *ad, struct ohci_aux_mem *aux, 1310 int is_mbuf, int isread) 1311 { 1312 1313 if (isread) { 1314 usb_bufptr_rd(&ad->aux_ptr, ad->aux_kern, ad->aux_len, 1315 is_mbuf); 1316 } 1317 ad->aux_len = 0; 1318 USB_KASSERT(aux->aux_naux > 0); 1319 if (--aux->aux_naux == 0) 1320 ohci_aux_mem_init(aux); 1321 } 1322 1323 Static void 1324 ohci_aux_dma_sync(ohci_softc_t *sc, struct ohci_aux_mem *aux, int op) 1325 { 1326 int i; 1327 1328 for (i = 0; i < aux->aux_curchunk; i++) 1329 USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op); 1330 if (aux->aux_chunkoff) 1331 USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i], 1332 0, aux->aux_chunkoff, op); 1333 } 1334 1335 Static usbd_status 1336 ohci_prealloc(struct ohci_softc *sc, struct ohci_xfer *oxfer, 1337 size_t bufsize, int nseg) 1338 { 1339 usb_endpoint_descriptor_t *ed; 1340 int maxseg, maxp, naux; 1341 int seglen, ntd; 1342 int s; 1343 int err; 1344 1345 ed = oxfer->xfer.pipe->endpoint->edesc; 1346 maxp = UE_MAXPKTSZ(ed); 1347 1348 if (maxp == 0) 1349 return (USBD_INVAL); 1350 1351 /* (over) estimate needed number of TDs */ 1352 maxseg = (sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) ? 4096 : 8192; 1353 seglen = maxseg - (maxseg % maxp); 1354 ntd = bufsize / seglen + nseg; 1355 1356 /* allocate aux buffer for non-isoc OUT or isoc transfer */ 1357 naux = 0; 1358 if (nseg > 1 && 1359 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS || 1360 UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_OUT)) { 1361 /* estimate needed aux segments */ 1362 naux = nseg - 1; 1363 1364 /* pre-allocate aux memory */ 1365 err = ohci_aux_mem_alloc(sc, &oxfer->aux, naux, maxp); 1366 if (err) 1367 return err; 1368 1369 /* an aux segment will consume a TD */ 1370 ntd += naux; 1371 } 1372 1373 s = splusb(); 1374 if ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS) { 1375 /* pre-allocate ITDs */ 1376 while (sc->sc_nfreeitds < ntd) { 1377 DPRINTF(("%s: ohci_prealloc: need %d ITD (%d cur)\n", 1378 USBDEVNAME(sc->sc_bus.bdev), 1379 ntd, sc->sc_nfreeitds)); 1380 if ((err = ohci_grow_sitd(sc)) 1381 != USBD_NORMAL_COMPLETION) { 1382 splx(s); 1383 ohci_aux_mem_free(sc, &oxfer->aux); 1384 return (err); 1385 } 1386 } 1387 sc->sc_nfreeitds -= ntd; 1388 } else { 1389 /* pre-allocate TDs */ 1390 while (sc->sc_nfreetds < ntd) { 1391 DPRINTF(("%s: ohci_prealloc: need %d TD (%d cur)\n", 1392 USBDEVNAME(sc->sc_bus.bdev), 1393 ntd, sc->sc_nfreetds)); 1394 if ((err = ohci_grow_std(sc)) 1395 != USBD_NORMAL_COMPLETION) { 1396 splx(s); 1397 ohci_aux_mem_free(sc, &oxfer->aux); 1398 return (err); 1399 } 1400 } 1401 sc->sc_nfreetds -= ntd; 1402 } 1403 splx(s); 1404 1405 oxfer->rsvd_tds = ntd; 1406 1407 return (USBD_NORMAL_COMPLETION); 1408 } 1409 1410 usbd_status 1411 ohci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1412 { 1413 struct ohci_softc *sc = (struct ohci_softc *)bus; 1414 struct ohci_xfer *oxfer = OXFER(xfer); 1415 usbd_status err; 1416 1417 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1418 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1419 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1420 (err = ohci_prealloc(sc, oxfer, size, 1421 USB_BUFFER_NSEGS(&oxfer->dmabuf))) 1422 != USBD_NORMAL_COMPLETION) { 1423 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, 1424 U_WAITOK); 1425 } 1426 } 1427 1428 return err; 1429 } 1430 1431 void 1432 ohci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1433 enum usbd_waitflg waitflg) 1434 { 1435 struct ohci_softc *sc = (struct ohci_softc *)bus; 1436 struct ohci_xfer *oxfer = OXFER(xfer); 1437 int s; 1438 1439 usb_free_buffer_dma(&sc->sc_dmatag, &oxfer->dmabuf, waitflg); 1440 1441 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1442 s = splusb(); 1443 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1444 UE_ISOCHRONOUS) { 1445 sc->sc_nfreeitds += oxfer->rsvd_tds; 1446 } else { 1447 sc->sc_nfreetds += oxfer->rsvd_tds; 1448 } 1449 splx(s); 1450 ohci_aux_mem_free(sc, &oxfer->aux); 1451 oxfer->rsvd_tds = 0; 1452 } 1453 } 1454 1455 Static usbd_status 1456 ohci_map_alloc(usbd_xfer_handle xfer) 1457 { 1458 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1459 struct ohci_xfer *oxfer = OXFER(xfer); 1460 usbd_status st; 1461 1462 st = usb_alloc_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1463 if (st) 1464 return st; 1465 1466 if ((st = ohci_prealloc(sc, oxfer, MAXPHYS, USB_DMA_NSEG))) { 1467 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1468 } 1469 1470 return st; 1471 } 1472 1473 Static void 1474 ohci_map_free(usbd_xfer_handle xfer) 1475 { 1476 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1477 struct ohci_xfer *oxfer = OXFER(xfer); 1478 int s; 1479 1480 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1481 1482 usb_free_dma_resources(&sc->sc_dmatag, &oxfer->dmabuf); 1483 1484 s = splusb(); 1485 if ((xfer->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) == 1486 UE_ISOCHRONOUS) { 1487 sc->sc_nfreeitds += oxfer->rsvd_tds; 1488 } else { 1489 sc->sc_nfreetds += oxfer->rsvd_tds; 1490 } 1491 splx(s); 1492 ohci_aux_mem_free(sc, &oxfer->aux); 1493 oxfer->rsvd_tds = 0; 1494 } 1495 1496 Static void 1497 ohci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1498 { 1499 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1500 struct ohci_xfer *oxfer = OXFER(xfer); 1501 1502 usb_map_dma(&sc->sc_dmatag, &oxfer->dmabuf, buf, size); 1503 } 1504 1505 Static usbd_status 1506 ohci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1507 { 1508 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1509 struct ohci_xfer *oxfer = OXFER(xfer); 1510 1511 return (usb_map_mbuf_dma(&sc->sc_dmatag, &oxfer->dmabuf, chain)); 1512 } 1513 1514 Static void 1515 ohci_unmapm(usbd_xfer_handle xfer) 1516 { 1517 struct ohci_softc *sc = (struct ohci_softc *)xfer->device->bus; 1518 struct ohci_xfer *oxfer = OXFER(xfer); 1519 1520 usb_unmap_dma(&sc->sc_dmatag, &oxfer->dmabuf); 1521 } 1522 1523 usbd_xfer_handle 1524 ohci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1525 enum usbd_waitflg waitflg) 1526 { 1527 struct ohci_softc *sc = (struct ohci_softc *)bus; 1528 usbd_xfer_handle xfer; 1529 1530 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1531 if (xfer != NULL) { 1532 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1533 #ifdef DIAGNOSTIC 1534 if (xfer->busy_free != XFER_FREE) { 1535 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1536 xfer->busy_free); 1537 } 1538 #endif 1539 } else { 1540 xfer = malloc(sizeof(struct ohci_xfer), M_USB, 1541 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1542 } 1543 if (xfer != NULL) { 1544 memset(xfer, 0, sizeof (struct ohci_xfer)); 1545 usb_init_task(&OXFER(xfer)->abort_task, ohci_timeout_task, 1546 xfer); 1547 OXFER(xfer)->ohci_xfer_flags = 0; 1548 OXFER(xfer)->rsvd_tds = 0; 1549 #ifdef DIAGNOSTIC 1550 xfer->busy_free = XFER_BUSY; 1551 #endif 1552 } 1553 return (xfer); 1554 } 1555 1556 void 1557 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1558 { 1559 struct ohci_softc *sc = (struct ohci_softc *)bus; 1560 1561 #ifdef DIAGNOSTIC 1562 if (xfer->busy_free != XFER_BUSY) { 1563 panic("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1564 xfer->busy_free); 1565 } 1566 xfer->busy_free = XFER_FREE; 1567 #endif 1568 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1569 } 1570 1571 /* 1572 * Perform any OHCI-specific transfer completion operations, then 1573 * call usb_transfer_complete(). 1574 */ 1575 Static void 1576 ohci_transfer_complete(usbd_xfer_handle xfer, int clear_halt) 1577 { 1578 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1579 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 1580 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 1581 ohci_soft_itd_t *sitd, *sitdnext; 1582 ohci_soft_td_t *std, *stdnext; 1583 ohci_physaddr_t dmaadr; 1584 int isread, is_mbuf; 1585 int s; 1586 1587 isread = usbd_xfer_isread(xfer); 1588 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 1589 1590 if (ub) 1591 usb_sync_buffer_dma(&sc->sc_dmatag, ub, 1592 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1593 1594 if (OXFER(xfer)->aux.aux_naux) { 1595 /* sync aux */ 1596 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, 1597 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1598 } 1599 1600 /* Copy back from any auxillary buffers after a read operation. */ 1601 if (xfer->hcpriv == NULL) { 1602 DPRINTFN(-1, ("ohci_transfer_complete: hcpriv == NULL\n")); 1603 } else if (xfer->nframes == 0) { 1604 /* Bulk/Interrupt transfer */ 1605 /* Remove all TDs belonging to this xfer. */ 1606 for (std = xfer->hcpriv; std->xfer == xfer; std = stdnext) { 1607 stdnext = std->nexttd; 1608 if (std->ad.aux_len) 1609 ohci_aux_dma_complete(&std->ad, 1610 &OXFER(xfer)->aux, is_mbuf, isread); 1611 ohci_free_std(sc, std); 1612 } 1613 if (clear_halt) { 1614 /* clear halt */ 1615 OHCI_SED_SYNC_POST(sc, opipe->sed); 1616 dmaadr = OHCI_STD_DMAADDR(std); 1617 opipe->sed->ed.ed_headp = HTOO32(dmaadr); 1618 OHCI_SED_SYNC2(sc, opipe->sed, 1619 offsetof(ohci_ed_t, ed_headp), 1620 sizeof(ohci_physaddr_t), 1621 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1622 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1623 } 1624 } else { 1625 /* Isoc transfer */ 1626 /* Remove all ITDs belonging to this xfer. */ 1627 for (sitd = xfer->hcpriv; sitd->xfer == xfer; 1628 sitd = sitdnext) { 1629 sitdnext = sitd->nextitd; 1630 if (sitd->ad.aux_len) 1631 ohci_aux_dma_complete(&sitd->ad, 1632 &OXFER(xfer)->aux, is_mbuf, isread); 1633 ohci_free_sitd(sc, sitd); 1634 } 1635 } 1636 1637 USB_KASSERT(OXFER(xfer)->aux.aux_naux == 0); 1638 xfer->hcpriv = NULL; 1639 1640 s = splusb(); 1641 usb_transfer_complete(xfer); 1642 splx(s); 1643 } 1644 1645 /* 1646 * Shut down the controller when the system is going down. 1647 */ 1648 void 1649 ohci_shutdown(void *v) 1650 { 1651 ohci_softc_t *sc = v; 1652 1653 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1654 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1655 } 1656 1657 /* 1658 * Handle suspend/resume. 1659 * 1660 * We need to switch to polling mode here, because this routine is 1661 * called from an interupt context. This is all right since we 1662 * are almost suspended anyway. 1663 */ 1664 void 1665 ohci_power(int why, void *v) 1666 { 1667 ohci_softc_t *sc = v; 1668 u_int32_t ctl; 1669 int s; 1670 1671 #ifdef USB_DEBUG 1672 DPRINTF(("ohci_power: sc=%p, why=%d\n", sc, why)); 1673 ohci_dumpregs(sc); 1674 #endif 1675 1676 s = splhardusb(); 1677 switch (why) { 1678 USB_PWR_CASE_SUSPEND: 1679 sc->sc_bus.use_polling++; 1680 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1681 if (sc->sc_control == 0) { 1682 /* 1683 * Preserve register values, in case that APM BIOS 1684 * does not recover them. 1685 */ 1686 sc->sc_control = ctl; 1687 sc->sc_intre = OREAD4(sc, OHCI_INTERRUPT_ENABLE); 1688 } 1689 ctl |= OHCI_HCFS_SUSPEND; 1690 OWRITE4(sc, OHCI_CONTROL, ctl); 1691 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1692 sc->sc_bus.use_polling--; 1693 break; 1694 1695 USB_PWR_CASE_RESUME: 1696 sc->sc_bus.use_polling++; 1697 1698 /* Some broken BIOSes never initialize Controller chip */ 1699 ohci_controller_init(sc); 1700 1701 if (sc->sc_intre) 1702 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, 1703 sc->sc_intre & (OHCI_ALL_INTRS | OHCI_MIE)); 1704 if (sc->sc_control) 1705 ctl = sc->sc_control; 1706 else 1707 ctl = OREAD4(sc, OHCI_CONTROL); 1708 ctl |= OHCI_HCFS_RESUME; 1709 OWRITE4(sc, OHCI_CONTROL, ctl); 1710 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1711 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1712 OWRITE4(sc, OHCI_CONTROL, ctl); 1713 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1714 sc->sc_control = sc->sc_intre = 0; 1715 sc->sc_bus.use_polling--; 1716 break; 1717 1718 default: 1719 break; 1720 } 1721 splx(s); 1722 } 1723 1724 #ifdef USB_DEBUG 1725 void 1726 ohci_dumpregs(ohci_softc_t *sc) 1727 { 1728 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1729 OREAD4(sc, OHCI_REVISION), 1730 OREAD4(sc, OHCI_CONTROL), 1731 OREAD4(sc, OHCI_COMMAND_STATUS))); 1732 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1733 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1734 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1735 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1736 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1737 OREAD4(sc, OHCI_HCCA), 1738 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1739 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1740 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1741 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1742 OREAD4(sc, OHCI_BULK_HEAD_ED), 1743 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1744 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1745 OREAD4(sc, OHCI_DONE_HEAD), 1746 OREAD4(sc, OHCI_FM_INTERVAL), 1747 OREAD4(sc, OHCI_FM_REMAINING))); 1748 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1749 OREAD4(sc, OHCI_FM_NUMBER), 1750 OREAD4(sc, OHCI_PERIODIC_START), 1751 OREAD4(sc, OHCI_LS_THRESHOLD))); 1752 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1753 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1754 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1755 OREAD4(sc, OHCI_RH_STATUS))); 1756 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1757 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1758 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1759 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1760 O32TOH(sc->sc_hcca->hcca_frame_number), 1761 O32TOH(sc->sc_hcca->hcca_done_head))); 1762 } 1763 #endif 1764 1765 Static int ohci_intr1(ohci_softc_t *); 1766 1767 #if defined(__NetBSD__) || defined(__OpenBSD__) 1768 int 1769 #elif defined(__FreeBSD__) 1770 void 1771 #endif 1772 ohci_intr(void *p) 1773 { 1774 ohci_softc_t *sc = p; 1775 1776 if (sc == NULL || sc->sc_dying) 1777 #if defined(__NetBSD__) || defined(__OpenBSD__) 1778 return (0); 1779 #elif defined(__FreeBSD__) 1780 return; 1781 #endif 1782 1783 /* If we get an interrupt while polling, then just ignore it. */ 1784 if (sc->sc_bus.use_polling) { 1785 #ifdef DIAGNOSTIC 1786 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1787 #endif 1788 /* for level triggered intrs, should do something to ack */ 1789 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1790 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1791 1792 #if defined(__NetBSD__) || defined(__OpenBSD__) 1793 return (0); 1794 #elif defined(__FreeBSD__) 1795 return; 1796 #endif 1797 } 1798 1799 #if defined(__NetBSD__) || defined(__OpenBSD__) 1800 return 1801 #endif 1802 ohci_intr1(sc); 1803 } 1804 1805 Static int 1806 ohci_intr1(ohci_softc_t *sc) 1807 { 1808 u_int32_t intrs, eintrs; 1809 1810 DPRINTFN(14,("ohci_intr1: enter\n")); 1811 1812 /* In case the interrupt occurs before initialization has completed. */ 1813 if (sc == NULL || sc->sc_hcca == NULL) { 1814 #ifdef DIAGNOSTIC 1815 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1816 #endif 1817 return (0); 1818 } 1819 1820 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1821 1822 if (intrs == 0) /* nothing to be done (PCI shared interrupt) */ 1823 return (0); 1824 1825 /* Acknowledge */ 1826 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1827 1828 eintrs = intrs & sc->sc_eintrs; 1829 if (!eintrs) 1830 return (0); 1831 1832 sc->sc_bus.intr_context++; 1833 sc->sc_bus.no_intrs++; 1834 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1835 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1836 (u_int)eintrs)); 1837 1838 if (eintrs & OHCI_SO) { 1839 sc->sc_overrun_cnt++; 1840 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1841 printf("%s: %u scheduling overruns\n", 1842 USBDEVNAME(sc->sc_bus.bdev), sc->sc_overrun_cnt); 1843 sc->sc_overrun_cnt = 0; 1844 } 1845 /* XXX do what */ 1846 eintrs &= ~OHCI_SO; 1847 } 1848 if (eintrs & OHCI_WDH) { 1849 /* 1850 * We block the interrupt below, and reenable it later from 1851 * ohci_softintr(). 1852 */ 1853 usb_schedsoftintr(&sc->sc_bus); 1854 } 1855 if (eintrs & OHCI_RD) { 1856 printf("%s: resume detect\n", USBDEVNAME(sc->sc_bus.bdev)); 1857 /* XXX process resume detect */ 1858 } 1859 if (eintrs & OHCI_UE) { 1860 printf("%s: unrecoverable error, controller halted\n", 1861 USBDEVNAME(sc->sc_bus.bdev)); 1862 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1863 /* XXX what else */ 1864 } 1865 if (eintrs & OHCI_RHSC) { 1866 /* 1867 * We block the interrupt below, and reenable it later from 1868 * a timeout. 1869 */ 1870 ohci_rhsc(sc, sc->sc_intrxfer); 1871 /* Do not allow RHSC interrupts > 1 per second */ 1872 usb_callout(sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1873 } 1874 1875 sc->sc_bus.intr_context--; 1876 1877 if (eintrs != 0) { 1878 /* Block unprocessed interrupts. */ 1879 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1880 sc->sc_eintrs &= ~eintrs; 1881 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1882 USBDEVNAME(sc->sc_bus.bdev), eintrs)); 1883 } 1884 1885 return (1); 1886 } 1887 1888 void 1889 ohci_rhsc_enable(void *v_sc) 1890 { 1891 ohci_softc_t *sc = v_sc; 1892 int s; 1893 1894 s = splhardusb(); 1895 sc->sc_eintrs |= OHCI_RHSC; 1896 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1897 splx(s); 1898 } 1899 1900 #ifdef USB_DEBUG 1901 const char *ohci_cc_strs[] = { 1902 "NO_ERROR", 1903 "CRC", 1904 "BIT_STUFFING", 1905 "DATA_TOGGLE_MISMATCH", 1906 "STALL", 1907 "DEVICE_NOT_RESPONDING", 1908 "PID_CHECK_FAILURE", 1909 "UNEXPECTED_PID", 1910 "DATA_OVERRUN", 1911 "DATA_UNDERRUN", 1912 "BUFFER_OVERRUN", 1913 "BUFFER_UNDERRUN", 1914 "reserved", 1915 "reserved", 1916 "NOT_ACCESSED", 1917 "NOT_ACCESSED" 1918 }; 1919 #endif 1920 1921 void 1922 ohci_softintr(void *v) 1923 { 1924 ohci_softc_t *sc = v; 1925 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1926 ohci_soft_td_t *std, *sdone, *stdnext, *p; 1927 usbd_xfer_handle xfer; 1928 struct ohci_pipe *opipe; 1929 int len, cc, s; 1930 int i, j, iframes; 1931 ohci_physaddr_t done; 1932 1933 DPRINTFN(10,("ohci_softintr: enter\n")); 1934 1935 sc->sc_bus.intr_context++; 1936 1937 s = splhardusb(); 1938 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 1939 offsetof(struct ohci_hcca, hcca_done_head), 1940 sizeof(sc->sc_hcca->hcca_done_head), 1941 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1942 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1943 sc->sc_hcca->hcca_done_head = 0; 1944 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 1945 offsetof(struct ohci_hcca, hcca_done_head), 1946 sizeof(sc->sc_hcca->hcca_done_head), 1947 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1948 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1949 sc->sc_eintrs |= OHCI_WDH; 1950 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1951 splx(s); 1952 1953 /* Reverse the done list. */ 1954 for (sdone = NULL, sidone = NULL; done != 0; ) { 1955 std = ohci_find_td(sc, done); 1956 if (std != NULL) { 1957 OHCI_STD_SYNC(sc, std, 1958 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1959 std->dnext = sdone; 1960 done = O32TOH(std->td.td_nexttd); 1961 sdone = std; 1962 DPRINTFN(10,("add TD %p\n", std)); 1963 continue; 1964 } 1965 sitd = ohci_find_itd(sc, done); 1966 if (sitd != NULL) { 1967 OHCI_SITD_SYNC(sc, sitd, 1968 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1969 sitd->dnext = sidone; 1970 done = O32TOH(sitd->itd.itd_nextitd); 1971 sidone = sitd; 1972 DPRINTFN(5,("add ITD %p\n", sitd)); 1973 continue; 1974 } 1975 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1976 } 1977 1978 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1979 1980 #ifdef USB_DEBUG 1981 if (ohcidebug > 10) { 1982 DPRINTF(("ohci_process_done: TD done:\n")); 1983 ohci_dump_tds(sc, sdone); 1984 } 1985 #endif 1986 1987 for (std = sdone; std; std = stdnext) { 1988 xfer = std->xfer; 1989 stdnext = std->dnext; 1990 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1991 std, xfer, (xfer ? xfer->hcpriv : NULL))); 1992 if (xfer == NULL) { 1993 /* 1994 * xfer == NULL: There seems to be no xfer associated 1995 * with this TD. It is tailp that happened to end up on 1996 * the done queue. 1997 */ 1998 continue; 1999 } 2000 if (xfer->status == USBD_CANCELLED || 2001 xfer->status == USBD_TIMEOUT) { 2002 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 2003 xfer)); 2004 /* Handled by abort routine. */ 2005 continue; 2006 } 2007 2008 len = std->len; 2009 if (std->td.td_cbp != 0) 2010 len -= O32TOH(std->td.td_be) - 2011 O32TOH(std->td.td_cbp) + 1; 2012 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 2013 std->flags)); 2014 if (std->flags & OHCI_ADD_LEN) 2015 xfer->actlen += len; 2016 2017 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 2018 if (cc != OHCI_CC_NO_ERROR) { 2019 /* 2020 * Endpoint is halted. First unlink all the TDs 2021 * belonging to the failed transfer, and then restart 2022 * the endpoint. 2023 */ 2024 opipe = (struct ohci_pipe *)xfer->pipe; 2025 2026 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 2027 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2028 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 2029 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2030 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 2031 &OXFER(xfer)->abort_task); 2032 2033 /* Remove all this xfer's TDs from the done queue. */ 2034 for (p = std; p->dnext != NULL; p = p->dnext) { 2035 if (p->dnext->xfer != xfer) 2036 continue; 2037 p->dnext = p->dnext->dnext; 2038 } 2039 /* The next TD may have been removed. */ 2040 stdnext = std->dnext; 2041 2042 if (cc == OHCI_CC_STALL) 2043 xfer->status = USBD_STALLED; 2044 else 2045 xfer->status = USBD_IOERROR; 2046 ohci_transfer_complete(xfer, 1); 2047 continue; 2048 } 2049 /* 2050 * Skip intermediate TDs. They remain linked from 2051 * xfer->hcpriv and we free them when the transfer completes. 2052 */ 2053 if ((std->flags & OHCI_CALL_DONE) == 0) 2054 continue; 2055 2056 /* Normal transfer completion */ 2057 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2058 usb_rem_task(OXFER(xfer)->xfer.pipe->device, 2059 &OXFER(xfer)->abort_task); 2060 xfer->status = USBD_NORMAL_COMPLETION; 2061 ohci_transfer_complete(xfer, 0); 2062 } 2063 2064 #ifdef USB_DEBUG 2065 if (ohcidebug > 10) { 2066 DPRINTF(("ohci_softintr: ITD done:\n")); 2067 ohci_dump_itds(sc, sidone); 2068 } 2069 #endif 2070 2071 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 2072 xfer = sitd->xfer; 2073 sitdnext = sitd->dnext; 2074 sitd->flags |= OHCI_ITD_INTFIN; 2075 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 2076 sitd, xfer, xfer ? xfer->hcpriv : 0)); 2077 if (xfer == NULL) 2078 continue; 2079 if (xfer->status == USBD_CANCELLED || 2080 xfer->status == USBD_TIMEOUT) { 2081 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 2082 xfer)); 2083 /* Handled by abort routine. */ 2084 continue; 2085 } 2086 if (xfer->pipe) 2087 if (xfer->pipe->aborting) 2088 continue; /*Ignore.*/ 2089 #ifdef DIAGNOSTIC 2090 if (sitd->isdone) 2091 printf("ohci_softintr: sitd=%p is done\n", sitd); 2092 sitd->isdone = 1; 2093 #endif 2094 opipe = (struct ohci_pipe *)xfer->pipe; 2095 if (opipe->aborting) 2096 continue; 2097 2098 if (sitd->flags & OHCI_CALL_DONE) { 2099 ohci_soft_itd_t *next; 2100 int isread = opipe->pipe.endpoint->edesc->bEndpointAddress & UE_DIR_IN; 2101 2102 opipe->u.iso.inuse -= xfer->nframes; 2103 xfer->status = USBD_NORMAL_COMPLETION; 2104 for (i = 0, sitd = xfer->hcpriv;;sitd = next) { 2105 next = sitd->nextitd; 2106 cc = OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)); 2107 if (cc != OHCI_CC_NO_ERROR) { 2108 xfer->status = USBD_IOERROR; 2109 } 2110 2111 { 2112 iframes = OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)); 2113 for (j = 0; j < iframes; i++, j++) { 2114 len = O16TOH(sitd->itd.itd_offset[j]); 2115 cc = OHCI_ITD_PSW_GET_CC(len); 2116 switch (cc & 2117 OHCI_CC_NOT_ACCESSED_MASK) { 2118 case OHCI_CC_NOT_ACCESSED: 2119 len = 0; 2120 break; 2121 case OHCI_CC_BUFFER_OVERRUN: 2122 /* or BUFFER_UNDERRUN */ 2123 xfer->status = USBD_IOERROR; 2124 /* FALLTHROUGH */ 2125 default: 2126 len = OHCI_ITD_PSW_LENGTH(len); 2127 break; 2128 } 2129 if (isread) 2130 xfer->frlengths[i] = len; 2131 } 2132 } 2133 if (sitd->flags & OHCI_CALL_DONE) 2134 break; 2135 } 2136 if (xfer->status != USBD_NORMAL_COMPLETION) { 2137 /* resync frame */ 2138 opipe->u.iso.next = -1; 2139 } 2140 #if 1 2141 /* XXX? */ 2142 xfer->status = USBD_NORMAL_COMPLETION; 2143 #endif 2144 2145 ohci_transfer_complete(xfer, 0); 2146 } 2147 } 2148 2149 #ifdef USB_USE_SOFTINTR 2150 if (sc->sc_softwake) { 2151 sc->sc_softwake = 0; 2152 wakeup(&sc->sc_softwake); 2153 } 2154 #endif /* USB_USE_SOFTINTR */ 2155 2156 sc->sc_bus.intr_context--; 2157 DPRINTFN(10,("ohci_softintr: done:\n")); 2158 } 2159 2160 void 2161 ohci_device_ctrl_done(usbd_xfer_handle xfer) 2162 { 2163 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 2164 2165 #ifdef DIAGNOSTIC 2166 if (!(xfer->rqflags & URQ_REQUEST)) { 2167 panic("ohci_device_ctrl_done: not a request"); 2168 } 2169 #endif 2170 } 2171 2172 void 2173 ohci_device_intr_done(usbd_xfer_handle xfer) 2174 { 2175 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2176 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2177 usbd_status err; 2178 2179 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 2180 xfer, xfer->actlen)); 2181 2182 if (xfer->pipe->repeat) { 2183 err = ohci_device_intr_insert(sc, xfer); 2184 if (err) { 2185 xfer->status = err; 2186 return; 2187 } 2188 } 2189 } 2190 2191 void 2192 ohci_device_bulk_done(usbd_xfer_handle xfer) 2193 { 2194 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 2195 xfer, xfer->actlen)); 2196 } 2197 2198 void 2199 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 2200 { 2201 usbd_pipe_handle pipe; 2202 u_char *p; 2203 int i, m; 2204 int hstatus; 2205 2206 hstatus = OREAD4(sc, OHCI_RH_STATUS); 2207 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 2208 sc, xfer, hstatus)); 2209 2210 if (xfer == NULL) { 2211 /* Just ignore the change. */ 2212 return; 2213 } 2214 2215 pipe = xfer->pipe; 2216 2217 p = xfer->hcbuffer; 2218 m = min(sc->sc_noport, xfer->length * 8 - 1); 2219 memset(p, 0, xfer->length); 2220 for (i = 1; i <= m; i++) { 2221 /* Pick out CHANGE bits from the status reg. */ 2222 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 2223 p[i/8] |= 1 << (i%8); 2224 } 2225 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 2226 xfer->actlen = xfer->length; 2227 xfer->status = USBD_NORMAL_COMPLETION; 2228 2229 usb_transfer_complete(xfer); 2230 } 2231 2232 void 2233 ohci_root_intr_done(usbd_xfer_handle xfer) 2234 { 2235 } 2236 2237 void 2238 ohci_root_ctrl_done(usbd_xfer_handle xfer) 2239 { 2240 } 2241 2242 /* 2243 * Wait here until controller claims to have an interrupt. 2244 * Then call ohci_intr and return. Use timeout to avoid waiting 2245 * too long. 2246 */ 2247 void 2248 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 2249 { 2250 int timo; 2251 u_int32_t intrs; 2252 2253 xfer->status = USBD_IN_PROGRESS; 2254 for (timo = xfer->timeout; timo >= 0; timo--) { 2255 usb_delay_ms(&sc->sc_bus, 1); 2256 if (sc->sc_dying) 2257 break; 2258 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 2259 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 2260 #ifdef USB_DEBUG 2261 if (ohcidebug > 15) 2262 ohci_dumpregs(sc); 2263 #endif 2264 if (intrs) { 2265 ohci_intr1(sc); 2266 if (xfer->status != USBD_IN_PROGRESS) 2267 return; 2268 } 2269 } 2270 2271 /* Timeout */ 2272 DPRINTF(("ohci_waitintr: timeout\n")); 2273 xfer->status = USBD_TIMEOUT; 2274 ohci_transfer_complete(xfer, 0); 2275 } 2276 2277 void 2278 ohci_poll(struct usbd_bus *bus) 2279 { 2280 ohci_softc_t *sc = (ohci_softc_t *)bus; 2281 #ifdef USB_DEBUG 2282 static int last; 2283 int new; 2284 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 2285 if (new != last) { 2286 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 2287 last = new; 2288 } 2289 #endif 2290 2291 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 2292 ohci_intr1(sc); 2293 } 2294 2295 usbd_status 2296 ohci_device_request(usbd_xfer_handle xfer) 2297 { 2298 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2299 usb_device_request_t *req = &xfer->request; 2300 usbd_device_handle dev = opipe->pipe.device; 2301 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2302 ohci_soft_td_t *setup, *stat, *next, *tail; 2303 ohci_soft_ed_t *sed; 2304 int isread; 2305 int len; 2306 usbd_status err; 2307 int s; 2308 ohci_physaddr_t dmaadr; 2309 2310 isread = req->bmRequestType & UT_READ; 2311 len = UGETW(req->wLength); 2312 2313 DPRINTFN(3,("ohci_device_request: type=0x%02x, request=0x%02x, " 2314 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2315 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2316 UGETW(req->wIndex), len, dev->address, 2317 opipe->pipe.endpoint->edesc->bEndpointAddress)); 2318 2319 setup = opipe->tail.td; 2320 stat = ohci_alloc_std(sc); 2321 if (stat == NULL) { 2322 err = USBD_NOMEM; 2323 goto bad1; 2324 } 2325 tail = ohci_alloc_std(sc); 2326 if (tail == NULL) { 2327 err = USBD_NOMEM; 2328 goto bad2; 2329 } 2330 tail->xfer = NULL; 2331 2332 sed = opipe->sed; 2333 opipe->u.ctl.length = len; 2334 next = stat; 2335 2336 /* Set up data transaction */ 2337 if (len != 0) { 2338 ohci_soft_td_t *std = stat; 2339 2340 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2341 std, &stat); 2342 if (err) 2343 goto bad3; 2344 OHCI_STD_SYNC(sc, stat, 2345 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2346 stat = stat->nexttd; /* point at free TD */ 2347 /* Start toggle at 1 and then use the carried toggle. */ 2348 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2349 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2350 } 2351 2352 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 2353 2354 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2355 OHCI_TD_TOGGLE_0 | OHCI_TD_SET_DI(6)); 2356 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 2357 setup->nexttd = next; 2358 dmaadr = OHCI_STD_DMAADDR(next); 2359 setup->td.td_nexttd = HTOO32(dmaadr); 2360 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 2361 setup->len = 0; 2362 setup->xfer = xfer; 2363 setup->flags = 0; 2364 xfer->hcpriv = setup; 2365 OHCI_STD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2366 2367 stat->td.td_flags = HTOO32( 2368 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2369 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2370 stat->td.td_cbp = 0; 2371 stat->nexttd = tail; 2372 dmaadr = OHCI_STD_DMAADDR(tail); 2373 stat->td.td_nexttd = HTOO32(dmaadr); 2374 stat->td.td_be = 0; 2375 stat->flags = OHCI_CALL_DONE; 2376 stat->len = 0; 2377 stat->xfer = xfer; 2378 OHCI_STD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2379 2380 #ifdef USB_DEBUG 2381 if (ohcidebug > 5) { 2382 DPRINTF(("ohci_device_request:\n")); 2383 ohci_dump_ed(sc, sed); 2384 ohci_dump_tds(sc, setup); 2385 } 2386 #endif 2387 2388 /* Insert ED in schedule */ 2389 s = splusb(); 2390 dmaadr = OHCI_STD_DMAADDR(tail); 2391 sed->ed.ed_tailp = HTOO32(dmaadr); 2392 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2393 opipe->tail.td = tail; 2394 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2395 if (xfer->timeout && !sc->sc_bus.use_polling) { 2396 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2397 ohci_timeout, xfer); 2398 } 2399 splx(s); 2400 2401 #ifdef USB_DEBUG 2402 if (ohcidebug > 20) { 2403 delay(10000); 2404 DPRINTF(("ohci_device_request: status=%x\n", 2405 OREAD4(sc, OHCI_COMMAND_STATUS))); 2406 ohci_dumpregs(sc); 2407 printf("ctrl head:\n"); 2408 ohci_dump_ed(sc, sc->sc_ctrl_head); 2409 printf("sed:\n"); 2410 ohci_dump_ed(sc, sed); 2411 ohci_dump_tds(sc, setup); 2412 } 2413 #endif 2414 2415 return (USBD_NORMAL_COMPLETION); 2416 2417 bad3: 2418 ohci_free_std(sc, tail); 2419 bad2: 2420 ohci_free_std(sc, stat); 2421 bad1: 2422 return (err); 2423 } 2424 2425 /* 2426 * Add an ED to the schedule. Called at splusb(). 2427 */ 2428 void 2429 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2430 { 2431 ohci_physaddr_t dmaadr; 2432 2433 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 2434 2435 SPLUSBCHECK; 2436 sed->next = head->next; 2437 sed->ed.ed_nexted = head->ed.ed_nexted; 2438 OHCI_SED_SYNC2(sc, sed, 2439 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2440 BUS_DMASYNC_PREWRITE); 2441 head->next = sed; 2442 dmaadr = OHCI_SED_DMAADDR(sed); 2443 head->ed.ed_nexted = HTOO32(dmaadr); 2444 OHCI_SED_SYNC2(sc, head, 2445 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2446 BUS_DMASYNC_PREWRITE); 2447 } 2448 2449 /* 2450 * Remove an ED from the schedule. Called at splusb(). 2451 */ 2452 void 2453 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 2454 { 2455 ohci_soft_ed_t *p; 2456 2457 SPLUSBCHECK; 2458 2459 /* XXX */ 2460 for (p = head; p != NULL && p->next != sed; p = p->next) 2461 ; 2462 if (p == NULL) 2463 panic("ohci_rem_ed: ED not found"); 2464 p->next = sed->next; 2465 p->ed.ed_nexted = sed->ed.ed_nexted; 2466 OHCI_SED_SYNC2(sc, p, 2467 offsetof(ohci_ed_t, ed_nexted), sizeof(ohci_physaddr_t), 2468 BUS_DMASYNC_PREWRITE); 2469 } 2470 2471 /* 2472 * When a transfer is completed the TD is added to the done queue by 2473 * the host controller. This queue is the processed by software. 2474 * Unfortunately the queue contains the physical address of the TD 2475 * and we have no simple way to translate this back to a kernel address. 2476 * To make the translation possible (and fast) we use the chunk of 2477 * TDs used for allocation. 2478 */ 2479 2480 ohci_soft_td_t * 2481 ohci_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 2482 { 2483 struct ohci_mem_desc *om; 2484 ohci_soft_td_t *std; 2485 size_t off; 2486 2487 /* if these are present they should be masked out at an earlier 2488 * stage. 2489 */ 2490 USB_KASSERT2((a&~OHCI_HEADMASK) == 0, ("%s: 0x%b has lower bits set\n", 2491 USBDEVNAME(sc->sc_bus.bdev), 2492 (int) a, "\20\1HALT\2TOGGLE")); 2493 2494 SIMPLEQ_FOREACH(om, &sc->sc_std_chunks, om_next) { 2495 if (a >= om->om_topdma && 2496 a < om->om_topdma + OHCI_STD_SIZE * OHCI_STD_CHUNK) { 2497 off = a - om->om_topdma; 2498 if (off % OHCI_STD_SIZE) { 2499 #ifdef DIAGNOSTIC 2500 printf("ohci_find_td: 0x%x bad address\n", 2501 (unsigned)a); 2502 #endif 2503 break; 2504 } 2505 std = (ohci_soft_td_t *)(om->om_top + off); 2506 if (std->flags & OHCI_TD_FREE) { 2507 #ifdef DIAGNOSTIC 2508 printf("ohci_find_td: 0x%x: free td\n", 2509 (unsigned)OHCI_STD_DMAADDR(std)); 2510 #endif 2511 break; 2512 } 2513 return std; 2514 } 2515 } 2516 2517 return (NULL); 2518 } 2519 2520 ohci_soft_itd_t * 2521 ohci_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 2522 { 2523 struct ohci_mem_desc *om; 2524 ohci_soft_itd_t *sitd; 2525 size_t off; 2526 2527 SIMPLEQ_FOREACH(om, &sc->sc_sitd_chunks, om_next) { 2528 if (a >= om->om_topdma && 2529 a < om->om_topdma + OHCI_SITD_SIZE * OHCI_SITD_CHUNK) { 2530 off = a - om->om_topdma; 2531 if (off % OHCI_SITD_SIZE) { 2532 #ifdef DIAGNOSTIC 2533 printf("ohci_find_itd: 0x%x bad address\n", 2534 (unsigned)a); 2535 #endif 2536 break; 2537 } 2538 sitd = (ohci_soft_itd_t *)(om->om_top + off); 2539 if (sitd->flags & OHCI_ITD_FREE) { 2540 #ifdef DIAGNOSTIC 2541 printf("ohci_find_itd: 0x%x: free itd\n", 2542 (unsigned)OHCI_SITD_DMAADDR(sitd)); 2543 #endif 2544 break; 2545 } 2546 return sitd; 2547 } 2548 } 2549 return (NULL); 2550 } 2551 2552 void 2553 ohci_timeout(void *addr) 2554 { 2555 struct ohci_xfer *oxfer = addr; 2556 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2557 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2558 2559 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2560 2561 if (sc->sc_dying) { 2562 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2563 return; 2564 } 2565 2566 /* Execute the abort in a process context. */ 2567 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2568 USB_TASKQ_HC); 2569 } 2570 2571 void 2572 ohci_timeout_task(void *addr) 2573 { 2574 usbd_xfer_handle xfer = addr; 2575 int s; 2576 2577 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2578 2579 s = splusb(); 2580 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2581 splx(s); 2582 } 2583 2584 #ifdef USB_DEBUG 2585 void 2586 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2587 { 2588 for (; std; std = std->nexttd) 2589 ohci_dump_td(sc, std); 2590 } 2591 2592 void 2593 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2594 { 2595 char sbuf[128]; 2596 2597 bitmask_snprintf((u_int32_t)O32TOH(std->td.td_flags), 2598 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2599 sbuf, sizeof(sbuf)); 2600 2601 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2602 "nexttd=0x%08lx be=0x%08lx\n", 2603 std, (u_long)OHCI_STD_DMAADDR(std), sbuf, 2604 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2605 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2606 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2607 (u_long)O32TOH(std->td.td_cbp), 2608 (u_long)O32TOH(std->td.td_nexttd), 2609 (u_long)O32TOH(std->td.td_be)); 2610 } 2611 2612 void 2613 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2614 { 2615 int i; 2616 2617 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2618 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2619 sitd, (u_long)OHCI_SITD_DMAADDR(sitd), 2620 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2621 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2622 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2623 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2624 (u_long)O32TOH(sitd->itd.itd_bp0), 2625 (u_long)O32TOH(sitd->itd.itd_nextitd), 2626 (u_long)O32TOH(sitd->itd.itd_be)); 2627 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2628 printf("offs[%d]=0x%04x ", i, 2629 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2630 printf("\n"); 2631 } 2632 2633 void 2634 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2635 { 2636 for (; sitd; sitd = sitd->nextitd) 2637 ohci_dump_itd(sc, sitd); 2638 } 2639 2640 void 2641 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2642 { 2643 char sbuf[128], sbuf2[128]; 2644 2645 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_flags), 2646 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2647 sbuf, sizeof(sbuf)); 2648 bitmask_snprintf((u_int32_t)O32TOH(sed->ed.ed_headp), 2649 "\20\1HALT\2CARRY", sbuf2, sizeof(sbuf2)); 2650 2651 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2652 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2653 sed, (u_long)OHCI_SED_DMAADDR(sed), 2654 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2655 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2656 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2657 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2658 (u_long)O32TOH(sed->ed.ed_headp), 2659 (u_long)O32TOH(sed->ed.ed_nexted)); 2660 } 2661 #endif 2662 2663 usbd_status 2664 ohci_open(usbd_pipe_handle pipe) 2665 { 2666 usbd_device_handle dev = pipe->device; 2667 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 2668 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2669 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2670 u_int8_t addr = dev->address; 2671 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2672 ohci_soft_ed_t *sed; 2673 ohci_soft_td_t *std; 2674 ohci_soft_itd_t *sitd; 2675 ohci_physaddr_t tdphys; 2676 u_int32_t fmt; 2677 usbd_status err; 2678 int s; 2679 int ival; 2680 2681 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2682 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2683 2684 if (sc->sc_dying) 2685 return (USBD_IOERROR); 2686 2687 std = NULL; 2688 sed = NULL; 2689 2690 if (addr == sc->sc_addr) { 2691 switch (ed->bEndpointAddress) { 2692 case USB_CONTROL_ENDPOINT: 2693 pipe->methods = &ohci_root_ctrl_methods; 2694 break; 2695 case UE_DIR_IN | OHCI_INTR_ENDPT: 2696 pipe->methods = &ohci_root_intr_methods; 2697 break; 2698 default: 2699 return (USBD_INVAL); 2700 } 2701 } else { 2702 sed = ohci_alloc_sed(sc); 2703 if (sed == NULL) 2704 goto bad0; 2705 opipe->sed = sed; 2706 if (xfertype == UE_ISOCHRONOUS) { 2707 sitd = ohci_alloc_sitd_norsv(sc); 2708 if (sitd == NULL) 2709 goto bad1; 2710 opipe->tail.itd = sitd; 2711 opipe->aborting = 0; 2712 tdphys = OHCI_SITD_DMAADDR(sitd); 2713 fmt = OHCI_ED_FORMAT_ISO; 2714 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2715 fmt |= OHCI_ED_DIR_IN; 2716 else 2717 fmt |= OHCI_ED_DIR_OUT; 2718 } else { 2719 std = ohci_alloc_std_norsv(sc); 2720 if (std == NULL) 2721 goto bad1; 2722 opipe->tail.td = std; 2723 tdphys = OHCI_STD_DMAADDR(std); 2724 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2725 } 2726 sed->ed.ed_flags = HTOO32( 2727 OHCI_ED_SET_FA(addr) | 2728 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2729 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2730 fmt | 2731 OHCI_ED_SET_MAXP(UE_MAXPKTSZ(ed))); 2732 sed->ed.ed_headp = HTOO32(tdphys | 2733 (pipe->endpoint->savedtoggle ? OHCI_TOGGLECARRY : 0)); 2734 sed->ed.ed_tailp = HTOO32(tdphys); 2735 2736 switch (xfertype) { 2737 case UE_CONTROL: 2738 pipe->methods = &ohci_device_ctrl_methods; 2739 err = usb_allocmem(&sc->sc_dmatag, 2740 sizeof(usb_device_request_t), 2741 0, &opipe->u.ctl.reqdma); 2742 if (err) 2743 goto bad; 2744 s = splusb(); 2745 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2746 splx(s); 2747 break; 2748 case UE_INTERRUPT: 2749 pipe->methods = &ohci_device_intr_methods; 2750 ival = pipe->interval; 2751 if (ival == USBD_DEFAULT_INTERVAL) 2752 ival = ed->bInterval; 2753 return (ohci_device_setintr(sc, opipe, ival)); 2754 case UE_ISOCHRONOUS: 2755 pipe->methods = &ohci_device_isoc_methods; 2756 return (ohci_setup_isoc(pipe)); 2757 case UE_BULK: 2758 pipe->methods = &ohci_device_bulk_methods; 2759 s = splusb(); 2760 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2761 splx(s); 2762 break; 2763 } 2764 } 2765 return (USBD_NORMAL_COMPLETION); 2766 2767 bad: 2768 if (std != NULL) 2769 ohci_free_std(sc, std); 2770 bad1: 2771 if (sed != NULL) 2772 ohci_free_sed(sc, sed); 2773 bad0: 2774 return (USBD_NOMEM); 2775 2776 } 2777 2778 /* 2779 * Close a reqular pipe. 2780 * Assumes that there are no pending transactions. 2781 */ 2782 void 2783 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2784 { 2785 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2786 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 2787 ohci_soft_ed_t *sed = opipe->sed; 2788 int s; 2789 2790 s = splusb(); 2791 #ifdef DIAGNOSTIC 2792 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2793 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2794 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2795 ohci_soft_td_t *std; 2796 std = ohci_find_td(sc, 2797 O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK); 2798 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2799 "tl=0x%x pipe=%p, std=%p\n", sed, 2800 (int)O32TOH(sed->ed.ed_headp), 2801 (int)O32TOH(sed->ed.ed_tailp), 2802 pipe, std); 2803 #ifdef USB_DEBUG 2804 usbd_dump_pipe(&opipe->pipe); 2805 #endif 2806 #ifdef USB_DEBUG 2807 ohci_dump_ed(sc, sed); 2808 if (std) 2809 ohci_dump_td(sc, std); 2810 #endif 2811 usb_delay_ms(&sc->sc_bus, 2); 2812 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2813 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2814 printf("ohci_close_pipe: pipe still not empty\n"); 2815 } 2816 #endif 2817 ohci_rem_ed(sc, sed, head); 2818 /* Make sure the host controller is not touching this ED */ 2819 usb_delay_ms(&sc->sc_bus, 1); 2820 splx(s); 2821 pipe->endpoint->savedtoggle = 2822 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2823 ohci_free_sed(sc, sed); 2824 } 2825 2826 /* 2827 * Abort a device request. 2828 * If this routine is called at splusb() it guarantees that the request 2829 * will be removed from the hardware scheduling and that the callback 2830 * for it will be called with USBD_CANCELLED status. 2831 * It's impossible to guarantee that the requested transfer will not 2832 * have happened since the hardware runs concurrently. 2833 * If the transaction has already happened we rely on the ordinary 2834 * interrupt processing to process it. 2835 */ 2836 void 2837 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2838 { 2839 struct ohci_xfer *oxfer = OXFER(xfer); 2840 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2841 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 2842 ohci_soft_ed_t *sed = opipe->sed; 2843 ohci_soft_td_t *p, *n; 2844 ohci_physaddr_t headp; 2845 ohci_physaddr_t dmaadr; 2846 int s, hit; 2847 int wake; 2848 int isread, is_mbuf; 2849 2850 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2851 2852 if (sc->sc_dying) { 2853 /* If we're dying, just do the software part. */ 2854 s = splusb(); 2855 xfer->status = status; /* make software ignore it */ 2856 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2857 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2858 ohci_transfer_complete(xfer, 0); 2859 splx(s); 2860 return; 2861 } 2862 2863 if (xfer->device->bus->intr_context || !curproc) 2864 panic("ohci_abort_xfer: not in process context"); 2865 2866 /* 2867 * If an abort is already in progress then just wait for it to 2868 * complete and return. 2869 */ 2870 if (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) { 2871 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2872 /* No need to wait if we're aborting from a timeout. */ 2873 if (status == USBD_TIMEOUT) 2874 return; 2875 /* Override the status which might be USBD_TIMEOUT. */ 2876 xfer->status = status; 2877 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2878 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTWAIT; 2879 while (oxfer->ohci_xfer_flags & OHCI_XFER_ABORTING) 2880 tsleep(&oxfer->ohci_xfer_flags, PZERO, "ohciaw", 0); 2881 return; 2882 } 2883 2884 /* 2885 * Step 1: Make interrupt routine and hardware ignore xfer. 2886 */ 2887 s = splusb(); 2888 oxfer->ohci_xfer_flags |= OHCI_XFER_ABORTING; 2889 xfer->status = status; /* make software ignore it */ 2890 usb_uncallout(xfer->timeout_handle, ohci_timeout, xfer); 2891 usb_rem_task(xfer->pipe->device, &oxfer->abort_task); 2892 splx(s); 2893 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2894 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2895 2896 /* 2897 * Step 2: Wait until we know hardware has finished any possible 2898 * use of the xfer. Also make sure the soft interrupt routine 2899 * has run. 2900 */ 2901 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2902 s = splusb(); 2903 #ifdef USB_USE_SOFTINTR 2904 sc->sc_softwake = 1; 2905 #endif /* USB_USE_SOFTINTR */ 2906 usb_schedsoftintr(&sc->sc_bus); 2907 #ifdef USB_USE_SOFTINTR 2908 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2909 #endif /* USB_USE_SOFTINTR */ 2910 splx(s); 2911 2912 /* 2913 * Step 3: Remove any vestiges of the xfer from the hardware. 2914 * The complication here is that the hardware may have executed 2915 * beyond the xfer we're trying to abort. So as we're scanning 2916 * the TDs of this xfer we check if the hardware points to 2917 * any of them. 2918 */ 2919 s = splusb(); /* XXX why? */ 2920 p = xfer->hcpriv; 2921 #ifdef DIAGNOSTIC 2922 if (p == NULL) { 2923 oxfer->ohci_xfer_flags &= ~OHCI_XFER_ABORTING; /* XXX */ 2924 splx(s); 2925 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2926 return; 2927 } 2928 #endif 2929 #ifdef USB_DEBUG 2930 if (ohcidebug > 1) { 2931 DPRINTF(("ohci_abort_xfer: sed=\n")); 2932 ohci_dump_ed(sc, sed); 2933 ohci_dump_tds(sc, p); 2934 } 2935 #endif 2936 isread = usbd_xfer_isread(xfer); 2937 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 2938 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2939 hit = 0; 2940 for (; p->xfer == xfer; p = n) { 2941 hit |= headp == OHCI_STD_DMAADDR(p); 2942 n = p->nexttd; 2943 } 2944 /* Zap headp register if hardware pointed inside the xfer. */ 2945 if (hit) { 2946 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2947 (int)OHCI_STD_DMAADDR(p), (int)O32TOH(sed->ed.ed_tailp))); 2948 dmaadr = OHCI_STD_DMAADDR(p); 2949 sed->ed.ed_headp = HTOO32(dmaadr); /* unlink TDs */ 2950 } else { 2951 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2952 } 2953 2954 /* 2955 * Step 4: Turn on hardware again. 2956 */ 2957 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2958 2959 /* 2960 * Step 5: Execute callback. 2961 */ 2962 /* Do the wakeup first to avoid touching the xfer after the callback. */ 2963 wake = oxfer->ohci_xfer_flags & OHCI_XFER_ABORTWAIT; 2964 oxfer->ohci_xfer_flags &= ~(OHCI_XFER_ABORTING | OHCI_XFER_ABORTWAIT); 2965 ohci_transfer_complete(xfer, 0); 2966 if (wake) 2967 wakeup(&oxfer->ohci_xfer_flags); 2968 2969 splx(s); 2970 } 2971 2972 /* 2973 * Data structures and routines to emulate the root hub. 2974 */ 2975 Static usb_device_descriptor_t ohci_devd = { 2976 USB_DEVICE_DESCRIPTOR_SIZE, 2977 UDESC_DEVICE, /* type */ 2978 {0x00, 0x01}, /* USB version */ 2979 UDCLASS_HUB, /* class */ 2980 UDSUBCLASS_HUB, /* subclass */ 2981 UDPROTO_FSHUB, /* protocol */ 2982 64, /* max packet */ 2983 {0},{0},{0x00,0x01}, /* device id */ 2984 1,2,0, /* string indicies */ 2985 1 /* # of configurations */ 2986 }; 2987 2988 Static usb_config_descriptor_t ohci_confd = { 2989 USB_CONFIG_DESCRIPTOR_SIZE, 2990 UDESC_CONFIG, 2991 {USB_CONFIG_DESCRIPTOR_SIZE + 2992 USB_INTERFACE_DESCRIPTOR_SIZE + 2993 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2994 1, 2995 1, 2996 0, 2997 UC_ATTR_MBO | UC_SELF_POWERED, 2998 0 /* max power */ 2999 }; 3000 3001 Static usb_interface_descriptor_t ohci_ifcd = { 3002 USB_INTERFACE_DESCRIPTOR_SIZE, 3003 UDESC_INTERFACE, 3004 0, 3005 0, 3006 1, 3007 UICLASS_HUB, 3008 UISUBCLASS_HUB, 3009 UIPROTO_FSHUB, 3010 0 3011 }; 3012 3013 Static usb_endpoint_descriptor_t ohci_endpd = { 3014 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 3015 .bDescriptorType = UDESC_ENDPOINT, 3016 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 3017 .bmAttributes = UE_INTERRUPT, 3018 .wMaxPacketSize = {8, 0}, /* max packet */ 3019 .bInterval = 255, 3020 }; 3021 3022 Static usb_hub_descriptor_t ohci_hubd = { 3023 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 3024 .bDescriptorType = UDESC_HUB, 3025 }; 3026 3027 Static int 3028 ohci_str(usb_string_descriptor_t *p, int l, const char *s) 3029 { 3030 int i; 3031 3032 if (l == 0) 3033 return (0); 3034 p->bLength = 2 * strlen(s) + 2; 3035 if (l == 1) 3036 return (1); 3037 p->bDescriptorType = UDESC_STRING; 3038 l -= 2; 3039 for (i = 0; s[i] && l > 1; i++, l -= 2) 3040 USETW2(p->bString[i], 0, s[i]); 3041 return (2*i+2); 3042 } 3043 3044 /* 3045 * Simulate a hardware hub by handling all the necessary requests. 3046 */ 3047 Static usbd_status 3048 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 3049 { 3050 usbd_status err; 3051 3052 /* Insert last in queue. */ 3053 #if 0 /* root ctrl doesn't do DMA */ 3054 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3055 &OXFER(xfer)->dmabuf); 3056 #else 3057 err = usb_insert_transfer(xfer); 3058 #endif 3059 if (err) 3060 return (err); 3061 3062 /* Pipe isn't running, start first */ 3063 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3064 } 3065 3066 Static usbd_status 3067 ohci_root_ctrl_start(usbd_xfer_handle xfer) 3068 { 3069 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3070 usb_device_request_t *req; 3071 void *buf = NULL; 3072 int port, i; 3073 int s, len, value, index, l, totlen = 0; 3074 usb_port_status_t ps; 3075 usb_hub_descriptor_t hubd; 3076 usbd_status err; 3077 u_int32_t v; 3078 3079 if (sc->sc_dying) 3080 return (USBD_IOERROR); 3081 3082 #ifdef DIAGNOSTIC 3083 if (!(xfer->rqflags & URQ_REQUEST)) 3084 /* XXX panic */ 3085 return (USBD_INVAL); 3086 #endif 3087 req = &xfer->request; 3088 3089 DPRINTFN(4,("ohci_root_ctrl_start: type=0x%02x request=%02x\n", 3090 req->bmRequestType, req->bRequest)); 3091 3092 len = UGETW(req->wLength); 3093 value = UGETW(req->wValue); 3094 index = UGETW(req->wIndex); 3095 3096 if (len != 0) { 3097 /* mbuf transfer is not supported */ 3098 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 3099 return (USBD_INVAL); 3100 buf = xfer->hcbuffer; 3101 } 3102 3103 #define C(x,y) ((x) | ((y) << 8)) 3104 switch(C(req->bRequest, req->bmRequestType)) { 3105 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3106 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3107 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3108 /* 3109 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3110 * for the integrated root hub. 3111 */ 3112 break; 3113 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3114 if (len > 0) { 3115 *(u_int8_t *)buf = sc->sc_conf; 3116 totlen = 1; 3117 } 3118 break; 3119 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3120 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 3121 if (len == 0) 3122 break; 3123 switch(value >> 8) { 3124 case UDESC_DEVICE: 3125 if ((value & 0xff) != 0) { 3126 err = USBD_IOERROR; 3127 goto ret; 3128 } 3129 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 3130 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 3131 memcpy(buf, &ohci_devd, l); 3132 break; 3133 case UDESC_CONFIG: 3134 if ((value & 0xff) != 0) { 3135 err = USBD_IOERROR; 3136 goto ret; 3137 } 3138 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 3139 memcpy(buf, &ohci_confd, l); 3140 buf = (char *)buf + l; 3141 len -= l; 3142 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 3143 totlen += l; 3144 memcpy(buf, &ohci_ifcd, l); 3145 buf = (char *)buf + l; 3146 len -= l; 3147 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 3148 totlen += l; 3149 memcpy(buf, &ohci_endpd, l); 3150 break; 3151 case UDESC_STRING: 3152 *(u_int8_t *)buf = 0; 3153 totlen = 1; 3154 switch (value & 0xff) { 3155 case 0: /* Language table */ 3156 if (len > 0) 3157 *(u_int8_t *)buf = 4; 3158 if (len >= 4) { 3159 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 3160 totlen = 4; 3161 } 3162 break; 3163 case 1: /* Vendor */ 3164 totlen = ohci_str(buf, len, sc->sc_vendor); 3165 break; 3166 case 2: /* Product */ 3167 totlen = ohci_str(buf, len, "OHCI root hub"); 3168 break; 3169 } 3170 break; 3171 default: 3172 err = USBD_IOERROR; 3173 goto ret; 3174 } 3175 break; 3176 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3177 if (len > 0) { 3178 *(u_int8_t *)buf = 0; 3179 totlen = 1; 3180 } 3181 break; 3182 case C(UR_GET_STATUS, UT_READ_DEVICE): 3183 if (len > 1) { 3184 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 3185 totlen = 2; 3186 } 3187 break; 3188 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3189 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3190 if (len > 1) { 3191 USETW(((usb_status_t *)buf)->wStatus, 0); 3192 totlen = 2; 3193 } 3194 break; 3195 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3196 if (value >= USB_MAX_DEVICES) { 3197 err = USBD_IOERROR; 3198 goto ret; 3199 } 3200 sc->sc_addr = value; 3201 break; 3202 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3203 if (value != 0 && value != 1) { 3204 err = USBD_IOERROR; 3205 goto ret; 3206 } 3207 sc->sc_conf = value; 3208 break; 3209 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3210 break; 3211 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3212 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3213 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3214 err = USBD_IOERROR; 3215 goto ret; 3216 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3217 break; 3218 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3219 break; 3220 /* Hub requests */ 3221 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3222 break; 3223 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3224 DPRINTFN(8, ("ohci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 3225 "port=%d feature=%d\n", 3226 index, value)); 3227 if (index < 1 || index > sc->sc_noport) { 3228 err = USBD_IOERROR; 3229 goto ret; 3230 } 3231 port = OHCI_RH_PORT_STATUS(index); 3232 switch(value) { 3233 case UHF_PORT_ENABLE: 3234 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 3235 break; 3236 case UHF_PORT_SUSPEND: 3237 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 3238 break; 3239 case UHF_PORT_POWER: 3240 /* Yes, writing to the LOW_SPEED bit clears power. */ 3241 OWRITE4(sc, port, UPS_LOW_SPEED); 3242 break; 3243 case UHF_C_PORT_CONNECTION: 3244 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 3245 break; 3246 case UHF_C_PORT_ENABLE: 3247 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 3248 break; 3249 case UHF_C_PORT_SUSPEND: 3250 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 3251 break; 3252 case UHF_C_PORT_OVER_CURRENT: 3253 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 3254 break; 3255 case UHF_C_PORT_RESET: 3256 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 3257 break; 3258 default: 3259 err = USBD_IOERROR; 3260 goto ret; 3261 } 3262 switch(value) { 3263 case UHF_C_PORT_CONNECTION: 3264 case UHF_C_PORT_ENABLE: 3265 case UHF_C_PORT_SUSPEND: 3266 case UHF_C_PORT_OVER_CURRENT: 3267 case UHF_C_PORT_RESET: 3268 /* Enable RHSC interrupt if condition is cleared. */ 3269 if ((OREAD4(sc, port) >> 16) == 0) 3270 ohci_rhsc_enable(sc); 3271 break; 3272 default: 3273 break; 3274 } 3275 break; 3276 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3277 if (len == 0) 3278 break; 3279 if ((value & 0xff) != 0) { 3280 err = USBD_IOERROR; 3281 goto ret; 3282 } 3283 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 3284 hubd = ohci_hubd; 3285 hubd.bNbrPorts = sc->sc_noport; 3286 USETW(hubd.wHubCharacteristics, 3287 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 3288 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 3289 /* XXX overcurrent */ 3290 ); 3291 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 3292 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 3293 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 3294 hubd.DeviceRemovable[i++] = (u_int8_t)v; 3295 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 3296 l = min(len, hubd.bDescLength); 3297 totlen = l; 3298 memcpy(buf, &hubd, l); 3299 break; 3300 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3301 if (len != 4) { 3302 err = USBD_IOERROR; 3303 goto ret; 3304 } 3305 memset(buf, 0, len); /* ? XXX */ 3306 totlen = len; 3307 break; 3308 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3309 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 3310 index)); 3311 if (index < 1 || index > sc->sc_noport) { 3312 err = USBD_IOERROR; 3313 goto ret; 3314 } 3315 if (len != 4) { 3316 err = USBD_IOERROR; 3317 goto ret; 3318 } 3319 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 3320 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 3321 v)); 3322 USETW(ps.wPortStatus, v); 3323 USETW(ps.wPortChange, v >> 16); 3324 l = min(len, sizeof ps); 3325 memcpy(buf, &ps, l); 3326 totlen = l; 3327 break; 3328 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3329 err = USBD_IOERROR; 3330 goto ret; 3331 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3332 break; 3333 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3334 if (index < 1 || index > sc->sc_noport) { 3335 err = USBD_IOERROR; 3336 goto ret; 3337 } 3338 port = OHCI_RH_PORT_STATUS(index); 3339 switch(value) { 3340 case UHF_PORT_ENABLE: 3341 OWRITE4(sc, port, UPS_PORT_ENABLED); 3342 break; 3343 case UHF_PORT_SUSPEND: 3344 OWRITE4(sc, port, UPS_SUSPEND); 3345 break; 3346 case UHF_PORT_RESET: 3347 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 3348 index)); 3349 OWRITE4(sc, port, UPS_RESET); 3350 for (i = 0; i < 5; i++) { 3351 usb_delay_ms(&sc->sc_bus, 3352 USB_PORT_ROOT_RESET_DELAY); 3353 if (sc->sc_dying) { 3354 err = USBD_IOERROR; 3355 goto ret; 3356 } 3357 if ((OREAD4(sc, port) & UPS_RESET) == 0) 3358 break; 3359 } 3360 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 3361 index, OREAD4(sc, port))); 3362 break; 3363 case UHF_PORT_POWER: 3364 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 3365 "%d\n", index)); 3366 OWRITE4(sc, port, UPS_PORT_POWER); 3367 break; 3368 default: 3369 err = USBD_IOERROR; 3370 goto ret; 3371 } 3372 break; 3373 default: 3374 err = USBD_IOERROR; 3375 goto ret; 3376 } 3377 xfer->actlen = totlen; 3378 err = USBD_NORMAL_COMPLETION; 3379 ret: 3380 xfer->status = err; 3381 #if 0 /* root ctrl doesn't do DMA */ 3382 ohci_transfer_complete(xfer, 0); 3383 #else 3384 s = splusb(); 3385 usb_transfer_complete(xfer); 3386 splx(s); 3387 #endif 3388 return (USBD_IN_PROGRESS); 3389 } 3390 3391 /* Abort a root control request. */ 3392 Static void 3393 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 3394 { 3395 /* Nothing to do, all transfers are synchronous. */ 3396 } 3397 3398 /* Close the root pipe. */ 3399 Static void 3400 ohci_root_ctrl_close(usbd_pipe_handle pipe) 3401 { 3402 DPRINTF(("ohci_root_ctrl_close\n")); 3403 /* Nothing to do. */ 3404 } 3405 3406 Static usbd_status 3407 ohci_root_intr_transfer(usbd_xfer_handle xfer) 3408 { 3409 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3410 usbd_status err; 3411 3412 /* Insert last in queue. */ 3413 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3414 &OXFER(xfer)->dmabuf); 3415 if (err) 3416 return (err); 3417 3418 /* Pipe isn't running, start first */ 3419 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3420 } 3421 3422 Static usbd_status 3423 ohci_root_intr_start(usbd_xfer_handle xfer) 3424 { 3425 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3426 3427 if (sc->sc_dying) 3428 return (USBD_IOERROR); 3429 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 3430 return (USBD_INVAL); /* mbuf transfer is not supported */ 3431 3432 sc->sc_intrxfer = xfer; 3433 3434 return (USBD_IN_PROGRESS); 3435 } 3436 3437 /* Abort a root interrupt request. */ 3438 Static void 3439 ohci_root_intr_abort(usbd_xfer_handle xfer) 3440 { 3441 usbd_pipe_handle pipe = xfer->pipe; 3442 3443 if (pipe->intrxfer == xfer) { 3444 DPRINTF(("ohci_root_intr_abort: remove\n")); 3445 pipe->intrxfer = NULL; 3446 } 3447 xfer->status = USBD_CANCELLED; 3448 ohci_transfer_complete(xfer, 0); 3449 } 3450 3451 /* Close the root pipe. */ 3452 Static void 3453 ohci_root_intr_close(usbd_pipe_handle pipe) 3454 { 3455 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3456 3457 DPRINTF(("ohci_root_intr_close\n")); 3458 3459 sc->sc_intrxfer = NULL; 3460 } 3461 3462 /************************/ 3463 3464 Static usbd_status 3465 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 3466 { 3467 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3468 usbd_status err; 3469 3470 /* Insert last in queue. */ 3471 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3472 &OXFER(xfer)->dmabuf); 3473 if (err) 3474 return (err); 3475 3476 /* Pipe isn't running, start first */ 3477 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3478 } 3479 3480 Static usbd_status 3481 ohci_device_ctrl_start(usbd_xfer_handle xfer) 3482 { 3483 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3484 usbd_status err; 3485 3486 if (sc->sc_dying) 3487 return (USBD_IOERROR); 3488 3489 #ifdef DIAGNOSTIC 3490 if (!(xfer->rqflags & URQ_REQUEST)) { 3491 /* XXX panic */ 3492 printf("ohci_device_ctrl_transfer: not a request\n"); 3493 return (USBD_INVAL); 3494 } 3495 #endif 3496 3497 err = ohci_device_request(xfer); 3498 if (err) 3499 return (err); 3500 3501 if (sc->sc_bus.use_polling) 3502 ohci_waitintr(sc, xfer); 3503 return (USBD_IN_PROGRESS); 3504 } 3505 3506 /* Abort a device control request. */ 3507 Static void 3508 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 3509 { 3510 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 3511 ohci_abort_xfer(xfer, USBD_CANCELLED); 3512 } 3513 3514 /* Close a device control pipe. */ 3515 Static void 3516 ohci_device_ctrl_close(usbd_pipe_handle pipe) 3517 { 3518 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3519 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3520 3521 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 3522 ohci_close_pipe(pipe, sc->sc_ctrl_head); 3523 ohci_free_std_norsv(sc, opipe->tail.td); 3524 usb_freemem(&sc->sc_dmatag, &opipe->u.ctl.reqdma); 3525 } 3526 3527 /************************/ 3528 3529 Static void 3530 ohci_device_clear_toggle(usbd_pipe_handle pipe) 3531 { 3532 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3533 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3534 3535 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 3536 } 3537 3538 Static void 3539 ohci_noop(usbd_pipe_handle pipe) 3540 { 3541 } 3542 3543 Static usbd_status 3544 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 3545 { 3546 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3547 usbd_status err; 3548 3549 /* Insert last in queue. */ 3550 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3551 &OXFER(xfer)->dmabuf); 3552 if (err) 3553 return (err); 3554 3555 /* Pipe isn't running, start first */ 3556 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3557 } 3558 3559 Static usbd_status 3560 ohci_device_bulk_start(usbd_xfer_handle xfer) 3561 { 3562 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3563 usbd_device_handle dev = opipe->pipe.device; 3564 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3565 int addr = dev->address; 3566 ohci_soft_td_t *data, *tail, *tdp; 3567 ohci_soft_ed_t *sed; 3568 ohci_physaddr_t dmaadr; 3569 int s, len, isread, endpt; 3570 usbd_status err; 3571 3572 if (sc->sc_dying) 3573 return (USBD_IOERROR); 3574 3575 #ifdef DIAGNOSTIC 3576 if (xfer->rqflags & URQ_REQUEST) { 3577 /* XXX panic */ 3578 printf("ohci_device_bulk_start: a request\n"); 3579 return (USBD_INVAL); 3580 } 3581 #endif 3582 3583 len = xfer->length; 3584 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3585 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3586 sed = opipe->sed; 3587 3588 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3589 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3590 endpt)); 3591 3592 opipe->u.bulk.isread = isread; 3593 opipe->u.bulk.length = len; 3594 3595 /* Update device address */ 3596 sed->ed.ed_flags = HTOO32( 3597 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3598 OHCI_ED_SET_FA(addr)); 3599 3600 /* Allocate a chain of new TDs (including a new tail). */ 3601 data = opipe->tail.td; 3602 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3603 data, &tail); 3604 /* We want interrupt at the end of the transfer. */ 3605 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3606 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3607 tail->flags |= OHCI_CALL_DONE; 3608 OHCI_STD_SYNC(sc, tail, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3609 tail = tail->nexttd; /* point at sentinel */ 3610 if (err) 3611 return (err); 3612 3613 tail->xfer = NULL; 3614 xfer->hcpriv = data; 3615 3616 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3617 "td_cbp=0x%08x td_be=0x%08x\n", 3618 (int)O32TOH(sed->ed.ed_flags), 3619 (int)O32TOH(data->td.td_flags), 3620 (int)O32TOH(data->td.td_cbp), 3621 (int)O32TOH(data->td.td_be))); 3622 3623 #ifdef USB_DEBUG 3624 if (ohcidebug > 5) { 3625 ohci_dump_ed(sc, sed); 3626 ohci_dump_tds(sc, data); 3627 } 3628 #endif 3629 3630 /* Insert ED in schedule */ 3631 s = splusb(); 3632 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3633 tdp->xfer = xfer; 3634 } 3635 dmaadr = OHCI_STD_DMAADDR(tail); 3636 sed->ed.ed_tailp = HTOO32(dmaadr); 3637 opipe->tail.td = tail; 3638 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3639 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3640 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3641 if (xfer->timeout && !sc->sc_bus.use_polling) { 3642 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3643 ohci_timeout, xfer); 3644 } 3645 3646 #if 0 3647 /* This goes wrong if we are too slow. */ 3648 if (ohcidebug > 10) { 3649 delay(10000); 3650 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3651 OREAD4(sc, OHCI_COMMAND_STATUS))); 3652 ohci_dump_ed(sc, sed); 3653 ohci_dump_tds(sc, data); 3654 } 3655 #endif 3656 3657 splx(s); 3658 3659 if (sc->sc_bus.use_polling) 3660 ohci_waitintr(sc, xfer); 3661 3662 return (USBD_IN_PROGRESS); 3663 } 3664 3665 Static void 3666 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3667 { 3668 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3669 ohci_abort_xfer(xfer, USBD_CANCELLED); 3670 } 3671 3672 /* 3673 * Close a device bulk pipe. 3674 */ 3675 Static void 3676 ohci_device_bulk_close(usbd_pipe_handle pipe) 3677 { 3678 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3679 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3680 3681 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3682 ohci_close_pipe(pipe, sc->sc_bulk_head); 3683 ohci_free_std_norsv(sc, opipe->tail.td); 3684 } 3685 3686 /************************/ 3687 3688 Static usbd_status 3689 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3690 { 3691 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3692 usbd_status err; 3693 3694 /* Insert last in queue. */ 3695 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3696 &OXFER(xfer)->dmabuf); 3697 if (err) 3698 return (err); 3699 3700 /* Pipe isn't running, start first */ 3701 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3702 } 3703 3704 Static usbd_status 3705 ohci_device_intr_start(usbd_xfer_handle xfer) 3706 { 3707 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3708 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 3709 ohci_soft_ed_t *sed = opipe->sed; 3710 usbd_status err; 3711 3712 if (sc->sc_dying) 3713 return (USBD_IOERROR); 3714 3715 DPRINTFN(3, ("ohci_device_intr_start: xfer=%p len=%d " 3716 "flags=%d priv=%p\n", 3717 xfer, xfer->length, xfer->flags, xfer->priv)); 3718 3719 #ifdef DIAGNOSTIC 3720 if (xfer->rqflags & URQ_REQUEST) 3721 panic("ohci_device_intr_start: a request"); 3722 #endif 3723 3724 err = ohci_device_intr_insert(sc, xfer); 3725 if (err) 3726 return (err); 3727 3728 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3729 3730 return (USBD_IN_PROGRESS); 3731 } 3732 3733 /* 3734 * Insert an interrupt transfer into an endpoint descriptor list 3735 */ 3736 Static usbd_status 3737 ohci_device_intr_insert(ohci_softc_t *sc, usbd_xfer_handle xfer) 3738 { 3739 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3740 ohci_soft_ed_t *sed = opipe->sed; 3741 ohci_soft_td_t *data, *tail; 3742 ohci_physaddr_t dataphys, physend; 3743 ohci_physaddr_t dmaadr; 3744 int s, isread, endpt; 3745 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 3746 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 3747 int nsegs = USB_BUFFER_NSEGS(ub); 3748 3749 DPRINTFN(4, ("ohci_device_intr_insert: xfer=%p", xfer)); 3750 3751 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3752 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3753 3754 data = opipe->tail.td; 3755 tail = ohci_alloc_std(sc); 3756 if (tail == NULL) 3757 return (USBD_NOMEM); 3758 tail->xfer = NULL; 3759 3760 data->td.td_flags = HTOO32( 3761 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3762 OHCI_TD_NOCC | 3763 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3764 if (xfer->flags & USBD_SHORT_XFER_OK) 3765 data->td.td_flags |= HTOO32(OHCI_TD_R); 3766 /* 3767 * Assume a short mapping with no complications, which 3768 * should always be true for <= 4k buffers in contiguous 3769 * virtual memory. The data can take the following forms: 3770 * 1 segment in 1 OHCI page 3771 * 1 segment in 2 OHCI pages 3772 * 2 segments in 2 OHCI pages 3773 * (see comment in ohci_alloc_std_chain() for details) 3774 */ 3775 USB_KASSERT2(xfer->length > 0 && xfer->length <= OHCI_PAGE_SIZE, 3776 ("ohci_device_intr_insert: bad length %d", xfer->length)); 3777 dataphys = segs[0].ds_addr; 3778 physend = dataphys + xfer->length - 1; 3779 if (nsegs == 2) { 3780 USB_KASSERT2(OHCI_PAGE_OFFSET(dataphys + 3781 segs[0].ds_len) == 0, 3782 ("ohci_device_intr_insert: bad seg 0 termination")); 3783 physend = segs[1].ds_addr + xfer->length - 3784 segs[0].ds_len - 1; 3785 } else { 3786 USB_KASSERT2(nsegs == 1, 3787 ("ohci_device_intr_insert: bad seg count %d", 3788 (u_int)nsegs)); 3789 } 3790 data->td.td_cbp = HTOO32(dataphys); 3791 data->nexttd = tail; 3792 dmaadr = OHCI_STD_DMAADDR(tail); 3793 data->td.td_nexttd = HTOO32(dmaadr); 3794 data->td.td_be = HTOO32(physend); 3795 data->len = xfer->length; 3796 data->xfer = xfer; 3797 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3798 xfer->hcpriv = data; 3799 xfer->actlen = 0; 3800 OHCI_STD_SYNC(sc, data, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3801 3802 #ifdef USB_DEBUG 3803 if (ohcidebug > 5) { 3804 DPRINTF(("ohci_device_intr_insert:\n")); 3805 ohci_dump_ed(sc, sed); 3806 ohci_dump_tds(sc, data); 3807 } 3808 #endif 3809 3810 /* Insert ED in schedule */ 3811 s = splusb(); 3812 dmaadr = OHCI_STD_DMAADDR(tail); 3813 sed->ed.ed_tailp = HTOO32(dmaadr); 3814 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3815 opipe->tail.td = tail; 3816 splx(s); 3817 3818 return (USBD_NORMAL_COMPLETION); 3819 } 3820 3821 /* Abort a device control request. */ 3822 Static void 3823 ohci_device_intr_abort(usbd_xfer_handle xfer) 3824 { 3825 if (xfer->pipe->intrxfer == xfer) { 3826 DPRINTF(("ohci_device_intr_abort: remove\n")); 3827 xfer->pipe->intrxfer = NULL; 3828 } 3829 ohci_abort_xfer(xfer, USBD_CANCELLED); 3830 } 3831 3832 /* Close a device interrupt pipe. */ 3833 Static void 3834 ohci_device_intr_close(usbd_pipe_handle pipe) 3835 { 3836 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3837 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 3838 int nslots = opipe->u.intr.nslots; 3839 int pos = opipe->u.intr.pos; 3840 int j; 3841 ohci_soft_ed_t *p, *sed = opipe->sed; 3842 int s; 3843 3844 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3845 pipe, nslots, pos)); 3846 s = splusb(); 3847 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3848 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3849 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3850 usb_delay_ms(&sc->sc_bus, 2); 3851 #ifdef DIAGNOSTIC 3852 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3853 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3854 panic("%s: Intr pipe %p still has TDs queued", 3855 USBDEVNAME(sc->sc_bus.bdev), pipe); 3856 #endif 3857 3858 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3859 ; 3860 #ifdef DIAGNOSTIC 3861 if (p == NULL) 3862 panic("ohci_device_intr_close: ED not found"); 3863 #endif 3864 p->next = sed->next; 3865 p->ed.ed_nexted = sed->ed.ed_nexted; 3866 splx(s); 3867 3868 for (j = 0; j < nslots; j++) 3869 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3870 3871 ohci_free_std_norsv(sc, opipe->tail.td); 3872 ohci_free_sed(sc, opipe->sed); 3873 } 3874 3875 Static usbd_status 3876 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3877 { 3878 int i, j, s, best; 3879 u_int npoll, slow, shigh, nslots; 3880 u_int bestbw, bw; 3881 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3882 ohci_physaddr_t dmaadr; 3883 3884 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3885 if (ival == 0) { 3886 printf("ohci_setintr: 0 interval\n"); 3887 return (USBD_INVAL); 3888 } 3889 3890 npoll = OHCI_NO_INTRS; 3891 while (npoll > ival) 3892 npoll /= 2; 3893 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3894 3895 /* 3896 * We now know which level in the tree the ED must go into. 3897 * Figure out which slot has most bandwidth left over. 3898 * Slots to examine: 3899 * npoll 3900 * 1 0 3901 * 2 1 2 3902 * 4 3 4 5 6 3903 * 8 7 8 9 10 11 12 13 14 3904 * N (N-1) .. (N-1+N-1) 3905 */ 3906 slow = npoll-1; 3907 shigh = slow + npoll; 3908 nslots = OHCI_NO_INTRS / npoll; 3909 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3910 bw = 0; 3911 for (j = 0; j < nslots; j++) 3912 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3913 if (bw < bestbw) { 3914 best = i; 3915 bestbw = bw; 3916 } 3917 } 3918 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3919 best, slow, shigh, bestbw)); 3920 3921 s = splusb(); 3922 hsed = sc->sc_eds[best]; 3923 sed->next = hsed->next; 3924 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3925 hsed->next = sed; 3926 dmaadr = OHCI_SED_DMAADDR(sed); 3927 hsed->ed.ed_nexted = HTOO32(dmaadr); 3928 splx(s); 3929 3930 for (j = 0; j < nslots; j++) 3931 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3932 opipe->u.intr.nslots = nslots; 3933 opipe->u.intr.pos = best; 3934 3935 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3936 return (USBD_NORMAL_COMPLETION); 3937 } 3938 3939 /***********************/ 3940 3941 usbd_status 3942 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3943 { 3944 ohci_softc_t *sc = (ohci_softc_t *)xfer->pipe->device->bus; 3945 usbd_status err; 3946 3947 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3948 3949 /* Put it on our queue, */ 3950 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3951 &OXFER(xfer)->dmabuf); 3952 3953 /* bail out on error, */ 3954 if (err && err != USBD_IN_PROGRESS) 3955 return (err); 3956 3957 /* XXX should check inuse here */ 3958 3959 /* insert into schedule, */ 3960 ohci_device_isoc_enter(xfer); 3961 3962 /* and start if the pipe wasn't running */ 3963 if (!err) 3964 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3965 3966 return (err); 3967 } 3968 3969 void 3970 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3971 { 3972 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3973 usbd_device_handle dev = opipe->pipe.device; 3974 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 3975 ohci_soft_ed_t *sed = opipe->sed; 3976 struct iso *iso = &opipe->u.iso; 3977 struct usb_buffer_dma *ub = &OXFER(xfer)->dmabuf; 3978 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 3979 int nsegs = USB_BUFFER_NSEGS(ub); 3980 ohci_soft_itd_t *sitd, *nsitd; 3981 ohci_physaddr_t dataphys, physend, prevphysend; 3982 ohci_physaddr_t segdmaadr; 3983 ohci_physaddr_t dmaadr; 3984 int i, len, ncur, nframes, seg, seglen, seglen1; 3985 int useaux, npagecross; 3986 int s; 3987 #if 1 3988 union usb_bufptr bufptr; 3989 int endpt, isread, is_mbuf; 3990 bus_addr_t auxdma; 3991 #endif 3992 #if 1 3993 uint32_t sitdo, tailo; 3994 #endif 3995 3996 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3997 "nframes=%d\n", 3998 iso->inuse, iso->next, xfer, xfer->nframes)); 3999 4000 if (sc->sc_dying) 4001 return; 4002 4003 if (iso->next == -1) { 4004 /* Not in use yet, schedule it a few frames ahead. */ 4005 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4006 offsetof(struct ohci_hcca, hcca_frame_number), 4007 sizeof(sc->sc_hcca->hcca_frame_number), 4008 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4009 iso->next = (uint16_t)(O32TOH(sc->sc_hcca->hcca_frame_number) + 5); 4010 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 4011 iso->next)); 4012 4013 #if 1 4014 OHCI_SED_SYNC_POST(sc, sed); 4015 if (sed->ed.ed_headp != sed->ed.ed_tailp) { 4016 /* set SKIP first */ 4017 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 4018 OHCI_SED_SYNC2(sc, sed, 4019 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4020 BUS_DMASYNC_PREWRITE); 4021 4022 /* wait for SKIP to take effect */ 4023 delay(2100); 4024 4025 OHCI_SED_SYNC_POST(sc, sed); 4026 4027 tailo = sed->ed.ed_tailp; 4028 for (sitdo = sed->ed.ed_headp; sitdo != tailo; 4029 sitdo = sitd->itd.itd_nextitd) { 4030 sitd = ohci_find_itd(sc, O32TOH(sitdo)); 4031 *(uint16_t *)&sitd->itd.itd_flags = 4032 HTOO16(iso->next); 4033 iso->next = (uint16_t)(iso->next + 4034 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags))); 4035 OHCI_SITD_SYNC(sc, sitd, 4036 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4037 } 4038 4039 /* clear SKIP */ 4040 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 4041 OHCI_SED_SYNC2(sc, sed, 4042 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4043 BUS_DMASYNC_PREWRITE); 4044 } 4045 #endif 4046 } 4047 4048 usb_bufptr_init(&bufptr, xfer); 4049 4050 sitd = opipe->tail.itd; 4051 nframes = xfer->nframes; 4052 xfer->hcpriv = sitd; 4053 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 4054 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4055 is_mbuf = xfer->rqflags & URQ_DEV_MAP_MBUF; 4056 4057 #ifdef DIAGNOSTIC 4058 segdmaadr = 0xbbbbbbbb; /* XXX -Wuninitialized */ 4059 dataphys = 0x77777777; /* XXX -Wuninitialized */ 4060 physend = 0xeeeeeeee; /* XXX -Wuninitialized */ 4061 prevphysend = 0x99999999; /* XXX -Wuninitialized */ 4062 #else 4063 segdmaadr = 0; /* XXX -Wuninitialized */ 4064 dataphys = 0; /* XXX -Wuninitialized */ 4065 physend = 0; /* XXX -Wuninitialized */ 4066 prevphysend = 0; /* XXX -Wuninitialized */ 4067 #endif 4068 4069 seg = 0; 4070 seglen = 0; 4071 useaux = 0; 4072 i = 0; 4073 while (i < nframes) { 4074 ncur = 0; 4075 npagecross = 0; 4076 do { 4077 /* 4078 * Fill in as many ITD frames as possible. 4079 */ 4080 4081 /* Find the frame start and end physical addresses. */ 4082 len = xfer->frlengths[i]; 4083 4084 if (useaux == 0) { 4085 /* skip handled segments */ 4086 if (seglen <= 0) { 4087 USB_KASSERT2(seg < nsegs, 4088 ("ohci_device_isoc_enter: overrun")); 4089 do { 4090 seglen1 = seglen; 4091 seglen += segs[seg].ds_len; 4092 if (seglen1 <= 0 && seglen > 0) 4093 segdmaadr = 4094 segs[seg].ds_addr 4095 - seglen1; 4096 } while (++seg < nsegs && 4097 (seglen <= 0 || 4098 segdmaadr + seglen == 4099 segs[seg].ds_addr)); 4100 } 4101 4102 /* DMA start and end addresses of the frame */ 4103 if (len <= seglen) { 4104 /* the frame fits in the segment */ 4105 physend = segdmaadr + len - 1; 4106 dataphys = segdmaadr; 4107 } else if (/* len > seglen */ 4108 (OHCI_PAGE_OFFSET(segdmaadr + seglen) || 4109 OHCI_PAGE_OFFSET(segs[seg].ds_addr) || 4110 len > seglen + segs[seg].ds_len)) { 4111 4112 DPRINTF(("ohci_device_isoc_enter: need aux len %#x dma %#x seglen %#x nextseg %#x\n", len, segdmaadr, seglen, (unsigned)segs[seg].ds_addr)); 4113 /* need aux memory */ 4114 useaux = 1; 4115 if (ncur > 0) { 4116 /* doesn't fit for now */ 4117 break; 4118 } else { 4119 goto doaux; /* shortcut */ 4120 } 4121 } else { /* len > seglen */ 4122 /* the frame ends in the next segment */ 4123 physend = segs[seg].ds_addr + 4124 (len - seglen - 1); 4125 dataphys = segdmaadr; 4126 } 4127 } 4128 4129 if (useaux) { 4130 doaux: 4131 USB_KASSERT(ncur == 0); /* for simplicity */ 4132 4133 /* need aux memory */ 4134 auxdma = ohci_aux_dma_alloc(&OXFER(xfer)->aux, 4135 &bufptr, len, &sitd->ad); 4136 4137 /* prepare aux DMA */ 4138 if (!isread) 4139 usb_bufptr_wr(&bufptr, 4140 sitd->ad.aux_kern, len, is_mbuf); 4141 dataphys = auxdma; 4142 physend = dataphys + len - 1; 4143 4144 useaux = 0; 4145 } 4146 4147 if (ncur == 0) { 4148 sitd->itd.itd_bp0 = HTOO32(dataphys); 4149 } else { 4150 /* check start of new page */ 4151 if (OHCI_PAGE_OFFSET(dataphys) == 0) 4152 npagecross++; 4153 } 4154 4155 sitd->itd.itd_offset[ncur] = 4156 HTOO16(OHCI_ITD_MK_OFFS(npagecross, dataphys)); 4157 4158 if (OHCI_PAGE(dataphys) != OHCI_PAGE(physend)) 4159 npagecross++; 4160 if (npagecross > 1 || 4161 ((sc->sc_flags & OHCI_FLAG_QUIRK_2ND_4KB) && 4162 npagecross == 1 && 4163 OHCI_PAGE_OFFSET(physend) == OHCI_PAGE_SIZE - 1)) { 4164 /* the frame doesn't fit in the ITD */ 4165 physend = prevphysend; 4166 break; 4167 } 4168 4169 /* the frame is handled */ 4170 seglen -= len; 4171 segdmaadr += len; 4172 usb_bufptr_advance(&bufptr, len, is_mbuf); 4173 prevphysend = physend; 4174 4175 i++; 4176 ncur++; 4177 4178 } while (ncur < OHCI_ITD_NOFFSET && i < nframes); 4179 4180 /* Allocate next ITD */ 4181 nsitd = ohci_alloc_sitd(sc); 4182 if (nsitd == NULL) { 4183 /* XXX what now? */ 4184 printf("%s: isoc TD alloc failed\n", 4185 USBDEVNAME(sc->sc_bus.bdev)); 4186 return; 4187 } 4188 4189 /* Fill out remaining fields of current ITD */ 4190 sitd->itd.itd_be = HTOO32(physend); 4191 sitd->nextitd = nsitd; 4192 dmaadr = OHCI_SITD_DMAADDR(nsitd); 4193 sitd->itd.itd_nextitd = HTOO32(dmaadr); 4194 sitd->xfer = xfer; 4195 4196 if (i < nframes) { 4197 sitd->itd.itd_flags = HTOO32( 4198 OHCI_ITD_NOCC | 4199 OHCI_ITD_SET_SF(iso->next) | 4200 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 4201 OHCI_ITD_SET_FC(ncur)); 4202 sitd->flags = OHCI_ITD_ACTIVE; 4203 } else { 4204 sitd->itd.itd_flags = HTOO32( 4205 OHCI_ITD_NOCC | 4206 OHCI_ITD_SET_SF(iso->next) | 4207 OHCI_ITD_SET_DI(0) | 4208 OHCI_ITD_SET_FC(ncur)); 4209 sitd->flags = OHCI_CALL_DONE | OHCI_ITD_ACTIVE; 4210 } 4211 iso->next = (uint16_t)(iso->next + ncur); 4212 4213 OHCI_SITD_SYNC(sc, sitd, 4214 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4215 sitd = nsitd; 4216 } 4217 4218 iso->inuse += nframes; 4219 4220 /* XXX pretend we did it all */ 4221 xfer->actlen = 0; 4222 for (i = 0; i < nframes; i++) 4223 xfer->actlen += xfer->frlengths[i]; 4224 4225 xfer->status = USBD_IN_PROGRESS; 4226 4227 #ifdef USB_DEBUG 4228 if (ohcidebug > 5) { 4229 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4230 offsetof(struct ohci_hcca, hcca_frame_number), 4231 sizeof(sc->sc_hcca->hcca_frame_number), 4232 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4233 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 4234 O32TOH(sc->sc_hcca->hcca_frame_number))); 4235 ohci_dump_itds(sc, xfer->hcpriv); 4236 ohci_dump_ed(sc, sed); 4237 } 4238 #endif 4239 4240 /* sync aux */ 4241 ohci_aux_dma_sync(sc, &OXFER(xfer)->aux, 4242 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4243 4244 s = splusb(); 4245 opipe->tail.itd = sitd; 4246 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 4247 dmaadr = OHCI_SITD_DMAADDR(sitd); 4248 sed->ed.ed_tailp = HTOO32(dmaadr); 4249 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4250 splx(s); 4251 4252 #ifdef USB_DEBUG 4253 if (ohcidebug > 5) { 4254 delay(150000); 4255 USB_MEM_SYNC2(&sc->sc_dmatag, &sc->sc_hccadma, 4256 offsetof(struct ohci_hcca, hcca_frame_number), 4257 sizeof(sc->sc_hcca->hcca_frame_number), 4258 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4259 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 4260 O32TOH(sc->sc_hcca->hcca_frame_number))); 4261 ohci_dump_itds(sc, xfer->hcpriv); 4262 ohci_dump_ed(sc, sed); 4263 } 4264 #endif 4265 } 4266 4267 usbd_status 4268 ohci_device_isoc_start(usbd_xfer_handle xfer) 4269 { 4270 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 4271 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 4272 ohci_soft_ed_t *sed; 4273 int s; 4274 4275 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 4276 4277 if (sc->sc_dying) 4278 return (USBD_IOERROR); 4279 4280 #ifdef DIAGNOSTIC 4281 if (xfer->status != USBD_IN_PROGRESS) 4282 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 4283 #endif 4284 4285 /* XXX anything to do? */ 4286 4287 s = splusb(); 4288 sed = opipe->sed; /* Turn off ED skip-bit to start processing */ 4289 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* ED's ITD list.*/ 4290 splx(s); 4291 4292 return (USBD_IN_PROGRESS); 4293 } 4294 4295 void 4296 ohci_device_isoc_abort(usbd_xfer_handle xfer) 4297 { 4298 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 4299 ohci_softc_t *sc = (ohci_softc_t *)opipe->pipe.device->bus; 4300 ohci_soft_ed_t *sed; 4301 ohci_soft_itd_t *sitd, *tmp_sitd; 4302 ohci_physaddr_t dmaadr; 4303 int s,undone,num_sitds; 4304 4305 s = splusb(); 4306 opipe->aborting = 1; 4307 4308 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 4309 4310 /* Transfer is already done. */ 4311 if (xfer->status != USBD_NOT_STARTED && 4312 xfer->status != USBD_IN_PROGRESS) { 4313 splx(s); 4314 printf("ohci_device_isoc_abort: early return\n"); 4315 return; 4316 } 4317 4318 /* Give xfer the requested abort code. */ 4319 xfer->status = USBD_CANCELLED; 4320 4321 sed = opipe->sed; 4322 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 4323 OHCI_SED_SYNC2(sc, sed, 4324 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4325 BUS_DMASYNC_PREWRITE); 4326 4327 num_sitds = 0; 4328 sitd = xfer->hcpriv; 4329 #ifdef DIAGNOSTIC 4330 if (sitd == NULL) { 4331 splx(s); 4332 printf("ohci_device_isoc_abort: hcpriv==0\n"); 4333 return; 4334 } 4335 #endif 4336 for (; sitd != NULL && sitd->xfer == xfer; sitd = sitd->nextitd) { 4337 num_sitds++; 4338 #ifdef DIAGNOSTIC 4339 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 4340 sitd->isdone = 1; 4341 #endif 4342 } 4343 4344 splx(s); 4345 4346 /* 4347 * Each sitd has up to OHCI_ITD_NOFFSET transfers, each can 4348 * take a usb 1ms cycle. Conservatively wait for it to drain. 4349 * Even with DMA done, it can take awhile for the "batch" 4350 * delivery of completion interrupts to occur thru the controller. 4351 */ 4352 4353 do { 4354 usb_delay_ms(&sc->sc_bus, 2*(num_sitds*OHCI_ITD_NOFFSET)); 4355 4356 undone = 0; 4357 tmp_sitd = xfer->hcpriv; 4358 for (; tmp_sitd != NULL && tmp_sitd->xfer == xfer; 4359 tmp_sitd = tmp_sitd->nextitd) { 4360 OHCI_SITD_SYNC(sc, tmp_sitd, 4361 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 4362 if (OHCI_CC_NO_ERROR == 4363 OHCI_ITD_GET_CC(O32TOH(tmp_sitd->itd.itd_flags)) && 4364 tmp_sitd->flags & OHCI_ITD_ACTIVE && 4365 (tmp_sitd->flags & OHCI_ITD_INTFIN) == 0) 4366 undone++; 4367 } 4368 } while (undone != 0); 4369 4370 s = splusb(); 4371 4372 /* Run callback. */ 4373 ohci_transfer_complete(xfer, 0); 4374 4375 /* There is always a `next' sitd so link it up. */ 4376 dmaadr = OHCI_SITD_DMAADDR(sitd); 4377 sed->ed.ed_headp = HTOO32(dmaadr); 4378 4379 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 4380 OHCI_SED_SYNC(sc, sed, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 4381 #if 0 /* above should be like this? */ 4382 OHCI_SED_SYNC2(sc, sed, 4383 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4384 BUS_DMASYNC_PREWRITE); 4385 #endif 4386 4387 splx(s); 4388 } 4389 4390 void 4391 ohci_device_isoc_done(usbd_xfer_handle xfer) 4392 { 4393 /* This null routine corresponds to non-isoc "done()" routines 4394 * that free the stds associated with an xfer after a completed 4395 * xfer interrupt. However, in the case of isoc transfers, the 4396 * sitds associated with the transfer have already been processed 4397 * and reallocated for the next iteration by 4398 * "ohci_device_isoc_transfer()". 4399 * 4400 * Routine "usb_transfer_complete()" is called at the end of every 4401 * relevant usb interrupt. "usb_transfer_complete()" indirectly 4402 * calls 1) "ohci_device_isoc_transfer()" (which keeps pumping the 4403 * pipeline by setting up the next transfer iteration) and 2) then 4404 * calls "ohci_device_isoc_done()". Isoc transfers have not been 4405 * working for the ohci usb because this routine was trashing the 4406 * xfer set up for the next iteration (thus, only the first 4407 * UGEN_NISOREQS xfers outstanding on an open would work). Perhaps 4408 * this could all be re-factored, but that's another pass... 4409 */ 4410 } 4411 4412 usbd_status 4413 ohci_setup_isoc(usbd_pipe_handle pipe) 4414 { 4415 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4416 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4417 struct iso *iso = &opipe->u.iso; 4418 int s; 4419 4420 iso->next = -1; 4421 iso->inuse = 0; 4422 4423 s = splusb(); 4424 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 4425 splx(s); 4426 4427 return (USBD_NORMAL_COMPLETION); 4428 } 4429 4430 void 4431 ohci_device_isoc_close(usbd_pipe_handle pipe) 4432 { 4433 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 4434 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 4435 ohci_soft_ed_t *sed; 4436 4437 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 4438 4439 sed = opipe->sed; 4440 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* Stop device. */ 4441 OHCI_SED_SYNC2(sc, sed, 4442 offsetof(ohci_ed_t, ed_flags), sizeof(u_int32_t), 4443 BUS_DMASYNC_PREWRITE); 4444 4445 ohci_close_pipe(pipe, sc->sc_isoc_head); /* Stop isoc list, free ED.*/ 4446 4447 /* up to NISOREQs xfers still outstanding. */ 4448 4449 #ifdef DIAGNOSTIC 4450 opipe->tail.itd->isdone = 1; 4451 #endif 4452 ohci_free_sitd_norsv(sc, opipe->tail.itd); /* Next `avail free' sitd.*/ 4453 } 4454
Indexes created Fri Oct 03 02:09:57 GMT 2025