ohci.c revision 1.2
1 /* $NetBSD: ohci.c,v 1.2 1998/07/23 01:46:27 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Author: Lennart Augustsson <augustss (at) carlstedt.se> 8 * Carlstedt Research & Technology 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Open Host Controller driver. 41 * 42 * OHCI spec: http://www.intel.com/design/usb/ohci11d.pdf 43 * USB spec: http://www.teleport.com/cgi-bin/mailmerge.cgi/~usb/cgiform.tpl 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/device.h> 51 #include <sys/proc.h> 52 #include <sys/queue.h> 53 #include <sys/select.h> 54 55 #include <dev/usb/usb.h> 56 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdivar.h> 59 60 #include <dev/usb/usb_quirks.h> 61 62 #include <machine/bus.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 67 int ohcidebug = 0; 68 69 struct ohci_pipe; 70 71 ohci_soft_ed_t *ohci_alloc_sed __P((ohci_softc_t *)); 72 void ohci_free_sed __P((ohci_softc_t *, ohci_soft_ed_t *)); 73 74 ohci_soft_td_t *ohci_alloc_std __P((ohci_softc_t *)); 75 void ohci_free_std __P((ohci_softc_t *, ohci_soft_td_t *)); 76 77 usbd_status ohci_open __P((usbd_pipe_handle)); 78 void ohci_waitintr __P((ohci_softc_t *, usbd_request_handle)); 79 void ohci_rhsc __P((ohci_softc_t *, usbd_request_handle)); 80 void ohci_process_done __P((ohci_softc_t *, ohci_physaddr_t)); 81 void ohci_ctrl_done __P((ohci_softc_t *, usbd_request_handle)); 82 void ohci_intr_done __P((ohci_softc_t *, usbd_request_handle)); 83 84 usbd_status ohci_allocmem __P((ohci_softc_t *,size_t,size_t, ohci_dma_t*)); 85 void ohci_freemem __P((ohci_softc_t *, ohci_dma_t *)); 86 87 usbd_status ohci_device_request __P((usbd_request_handle reqh)); 88 void ohci_add_ed __P((ohci_softc_t *, ohci_soft_ed_t *, 89 ohci_soft_ed_t *)); 90 void ohci_hash_add_td __P((ohci_softc_t *, ohci_soft_td_t *)); 91 void ohci_hash_rem_td __P((ohci_softc_t *, ohci_soft_td_t *)); 92 ohci_soft_td_t *ohci_hash_find_td __P((ohci_softc_t *, ohci_physaddr_t)); 93 94 usbd_status ohci_root_ctrl_transfer __P((usbd_request_handle)); 95 void ohci_root_ctrl_abort __P((usbd_request_handle)); 96 void ohci_root_ctrl_close __P((usbd_pipe_handle)); 97 98 usbd_status ohci_root_intr_transfer __P((usbd_request_handle)); 99 void ohci_root_intr_abort __P((usbd_request_handle)); 100 void ohci_root_intr_close __P((usbd_pipe_handle)); 101 102 usbd_status ohci_device_ctrl_transfer __P((usbd_request_handle)); 103 void ohci_device_ctrl_abort __P((usbd_request_handle)); 104 void ohci_device_ctrl_close __P((usbd_pipe_handle)); 105 106 usbd_status ohci_device_intr_transfer __P((usbd_request_handle)); 107 void ohci_device_intr_abort __P((usbd_request_handle)); 108 void ohci_device_intr_close __P((usbd_pipe_handle)); 109 usbd_status ohci_device_setintr __P((ohci_softc_t *sc, 110 struct ohci_pipe *pipe, int ival)); 111 112 int ohci_str __P((usb_string_descriptor_t *, int, char *)); 113 114 void ohci_timeout __P((void *)); 115 void ohci_rhsc_able __P((ohci_softc_t *, int)); 116 117 #ifdef USB_DEBUG 118 ohci_softc_t *thesc; 119 void ohci_dumpregs __P((ohci_softc_t *)); 120 void ohci_dump_tds __P((ohci_soft_td_t *)); 121 void ohci_dump_td __P((ohci_soft_td_t *)); 122 void ohci_dump_ed __P((ohci_soft_ed_t *)); 123 #endif 124 125 #define OWRITE4(sc, r, x) bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)) 126 #define OREAD4(sc, r) bus_space_read_4((sc)->iot, (sc)->ioh, (r)) 127 #define OREAD2(sc, r) bus_space_read_2((sc)->iot, (sc)->ioh, (r)) 128 129 /* Reverse the bits in a value 0 .. 31 */ 130 static u_int8_t revbits[OHCI_NO_INTRS] = 131 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 132 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 133 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 134 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 135 136 struct ohci_pipe { 137 struct usbd_pipe pipe; 138 ohci_soft_ed_t *sed; 139 ohci_soft_td_t *tail; 140 /* Info needed for different pipe kinds. */ 141 union { 142 /* Control pipe */ 143 struct { 144 ohci_dma_t datadma; 145 ohci_dma_t reqdma; 146 u_int length; 147 ohci_soft_td_t *setup, *xfer, *stat; 148 } ctl; 149 /* Interrupt pipe */ 150 struct { 151 ohci_dma_t datadma; 152 int nslots; 153 int pos; 154 } intr; 155 } u; 156 }; 157 158 #define OHCI_INTR_ENDPT 1 159 160 struct usbd_methods ohci_root_ctrl_methods = { 161 ohci_root_ctrl_transfer, 162 ohci_root_ctrl_abort, 163 ohci_root_ctrl_close, 164 }; 165 166 struct usbd_methods ohci_root_intr_methods = { 167 ohci_root_intr_transfer, 168 ohci_root_intr_abort, 169 ohci_root_intr_close, 170 }; 171 172 struct usbd_methods ohci_device_ctrl_methods = { 173 ohci_device_ctrl_transfer, 174 ohci_device_ctrl_abort, 175 ohci_device_ctrl_close, 176 }; 177 178 struct usbd_methods ohci_device_intr_methods = { 179 ohci_device_intr_transfer, 180 ohci_device_intr_abort, 181 ohci_device_intr_close, 182 }; 183 184 usbd_status 185 ohci_allocmem(sc, size, align, p) 186 ohci_softc_t *sc; 187 size_t size; 188 size_t align; 189 ohci_dma_t *p; 190 { 191 int error; 192 193 DPRINTFN(5, ("ohci_allocmem: size=%d align=%d\n", size, align)); 194 p->size = size; 195 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0, 196 p->segs, sizeof(p->segs)/sizeof(p->segs[0]), 197 &p->nsegs, BUS_DMA_NOWAIT); 198 if (error) 199 return (USBD_NOMEM); 200 201 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size, 202 &p->kaddr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 203 if (error) 204 goto free; 205 206 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size, 207 0, BUS_DMA_NOWAIT, &p->map); 208 if (error) 209 goto unmap; 210 211 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->kaddr,p->size, NULL, 212 BUS_DMA_NOWAIT); 213 if (error) 214 goto destroy; 215 return 0; 216 217 destroy: 218 bus_dmamap_destroy(sc->sc_dmatag, p->map); 219 unmap: 220 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 221 free: 222 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 223 return (USBD_NOMEM); 224 } 225 226 void 227 ohci_freemem(sc, p) 228 ohci_softc_t *sc; 229 ohci_dma_t *p; 230 { 231 bus_dmamap_unload(sc->sc_dmatag, p->map); 232 bus_dmamap_destroy(sc->sc_dmatag, p->map); 233 bus_dmamem_unmap(sc->sc_dmatag, p->kaddr, p->size); 234 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs); 235 } 236 237 ohci_soft_ed_t * 238 ohci_alloc_sed(sc) 239 ohci_softc_t *sc; 240 { 241 ohci_soft_ed_t *sed; 242 usbd_status r; 243 int i, offs; 244 ohci_dma_t dma; 245 246 if (!sc->sc_freeeds) { 247 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 248 sed = malloc(sizeof(ohci_soft_ed_t) * OHCI_ED_CHUNK, 249 M_USBDEV, M_NOWAIT); 250 if (!sed) 251 return 0; 252 r = ohci_allocmem(sc, OHCI_ED_SIZE * OHCI_ED_CHUNK, 253 OHCI_ED_ALIGN, &dma); 254 if (r != USBD_NORMAL_COMPLETION) { 255 free(sed, M_USBDEV); 256 return 0; 257 } 258 for(i = 0; i < OHCI_ED_CHUNK; i++, sed++) { 259 offs = i * OHCI_ED_SIZE; 260 sed->physaddr = DMAADDR(&dma) + offs; 261 sed->ed = (ohci_ed_t *) 262 ((char *)KERNADDR(&dma) + offs); 263 sed->next = sc->sc_freeeds; 264 sc->sc_freeeds = sed; 265 } 266 } 267 sed = sc->sc_freeeds; 268 sc->sc_freeeds = sed->next; 269 memset(sed->ed, 0, OHCI_ED_SIZE); 270 sed->next = 0; 271 return sed; 272 } 273 274 void 275 ohci_free_sed(sc, sed) 276 ohci_softc_t *sc; 277 ohci_soft_ed_t *sed; 278 { 279 sed->next = sc->sc_freeeds; 280 sc->sc_freeeds = sed; 281 } 282 283 ohci_soft_td_t * 284 ohci_alloc_std(sc) 285 ohci_softc_t *sc; 286 { 287 ohci_soft_td_t *std; 288 usbd_status r; 289 int i, offs; 290 ohci_dma_t dma; 291 292 if (!sc->sc_freetds) { 293 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 294 std = malloc(sizeof(ohci_soft_td_t) * OHCI_TD_CHUNK, 295 M_USBDEV, M_NOWAIT); 296 if (!std) 297 return 0; 298 r = ohci_allocmem(sc, OHCI_TD_SIZE * OHCI_TD_CHUNK, 299 OHCI_TD_ALIGN, &dma); 300 if (r != USBD_NORMAL_COMPLETION) { 301 free(std, M_USBDEV); 302 return 0; 303 } 304 for(i = 0; i < OHCI_TD_CHUNK; i++, std++) { 305 offs = i * OHCI_TD_SIZE; 306 std->physaddr = DMAADDR(&dma) + offs; 307 std->td = (ohci_td_t *) 308 ((char *)KERNADDR(&dma) + offs); 309 std->nexttd = sc->sc_freetds; 310 sc->sc_freetds = std; 311 } 312 } 313 std = sc->sc_freetds; 314 sc->sc_freetds = std->nexttd; 315 memset(std->td, 0, OHCI_TD_SIZE); 316 std->nexttd = 0; 317 return (std); 318 } 319 320 void 321 ohci_free_std(sc, std) 322 ohci_softc_t *sc; 323 ohci_soft_td_t *std; 324 { 325 std->nexttd = sc->sc_freetds; 326 sc->sc_freetds = std; 327 } 328 329 usbd_status 330 ohci_init(sc) 331 ohci_softc_t *sc; 332 { 333 ohci_soft_ed_t *sed, *psed; 334 usbd_status r; 335 int rev; 336 int i; 337 u_int32_t s, ctl, ival, hcr, fm, per; 338 339 DPRINTF(("ohci_init: start\n")); 340 rev = OREAD4(sc, OHCI_REVISION); 341 printf("%s: OHCI version %d.%d%s\n", sc->sc_bus.bdev.dv_xname, 342 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 343 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 344 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 345 printf("%s: unsupported OHCI revision\n", 346 sc->sc_bus.bdev.dv_xname); 347 return (USBD_INVAL); 348 } 349 350 for (i = 0; i < OHCI_HASH_SIZE; i++) 351 LIST_INIT(&sc->sc_hash_tds[i]); 352 353 /* Allocate the HCCA area. */ 354 r = ohci_allocmem(sc, OHCI_HCCA_SIZE, OHCI_HCCA_ALIGN,&sc->sc_hccadma); 355 if (r != USBD_NORMAL_COMPLETION) 356 return (r); 357 sc->sc_hcca = (struct ohci_hcca *)KERNADDR(&sc->sc_hccadma); 358 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 359 360 sc->sc_eintrs = OHCI_NORMAL_INTRS; 361 362 sc->sc_ctrl_head = ohci_alloc_sed(sc); 363 if (!sc->sc_ctrl_head) { 364 r = USBD_NOMEM; 365 goto bad1; 366 } 367 sc->sc_ctrl_head->ed->ed_flags |= OHCI_ED_SKIP; 368 sc->sc_bulk_head = ohci_alloc_sed(sc); 369 if (!sc->sc_bulk_head) { 370 r = USBD_NOMEM; 371 goto bad2; 372 } 373 sc->sc_bulk_head->ed->ed_flags |= OHCI_ED_SKIP; 374 375 /* Allocate all the dummy EDs that make up the interrupt tree. */ 376 for (i = 0; i < OHCI_NO_EDS; i++) { 377 sed = ohci_alloc_sed(sc); 378 if (!sed) { 379 while (--i >= 0) 380 ohci_free_sed(sc, sc->sc_eds[i]); 381 r = USBD_NOMEM; 382 goto bad3; 383 } 384 /* All ED fields are set to 0. */ 385 sc->sc_eds[i] = sed; 386 sed->ed->ed_flags |= OHCI_ED_SKIP; 387 if (i != 0) { 388 psed = sc->sc_eds[(i-1) / 2]; 389 sed->next = psed; 390 sed->ed->ed_nexted = psed->physaddr; 391 } 392 } 393 /* 394 * Fill HCCA interrupt table. The bit reversal is to get 395 * the tree set up properly to spread the interrupts. 396 */ 397 for (i = 0; i < OHCI_NO_INTRS; i++) 398 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 399 sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr; 400 401 /* Determine in what context we are running. */ 402 ctl = OREAD4(sc, OHCI_CONTROL); 403 if (ctl & OHCI_IR) { 404 /* SMM active, request change */ 405 DPRINTF(("ohci_init: SMM active, request owner change\n")); 406 s = OREAD4(sc, OHCI_COMMAND_STATUS); 407 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 408 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 409 delay(1000); 410 ctl = OREAD4(sc, OHCI_CONTROL); 411 } 412 if ((ctl & OHCI_IR) == 0) { 413 printf("%s: SMM does not respond, resetting\n", 414 sc->sc_bus.bdev.dv_xname); 415 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 416 goto reset; 417 } 418 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 419 /* BIOS started controller. */ 420 DPRINTF(("ohci_init: BIOS active\n")); 421 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 422 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL); 423 delay(USB_RESUME_DELAY * 1000); 424 } 425 } else { 426 DPRINTF(("ohci_init: cold started\n")); 427 reset: 428 /* Controller was cold started. */ 429 delay(USB_RESET_DELAY * 1000); 430 } 431 432 /* We now own the host controller and the bus has been reset. */ 433 ival = OHCI_GET_IVAL(OREAD4(sc, OHCI_FM_INTERVAL)); 434 435 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 436 /* Nominal time for a reset is 10 us. */ 437 for (i = 0; i < 10; i++) { 438 delay(10); 439 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 printf("%s: reset timeout\n", sc->sc_bus.bdev.dv_xname); 445 r = USBD_IOERROR; 446 goto bad3; 447 } 448 #ifdef USB_DEBUG 449 thesc = sc; 450 if (ohcidebug > 15) 451 ohci_dumpregs(sc); 452 #endif 453 454 /* The controller is now in suspend state, we have 2ms to finish. */ 455 456 /* Set up HC registers. */ 457 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 458 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 459 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 460 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 461 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 462 ctl = OREAD4(sc, OHCI_CONTROL); 463 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 464 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 465 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL; 466 /* And finally start it! */ 467 OWRITE4(sc, OHCI_CONTROL, ctl); 468 469 /* 470 * The controller is now OPERATIONAL. Set a some final 471 * registers that should be set earlier, but that the 472 * controller ignores when in the SUSPEND state. 473 */ 474 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 475 fm |= OHCI_FSMPS(ival) | ival; 476 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 477 per = OHCI_PERIODIC(ival); /* 90% periodic */ 478 OWRITE4(sc, OHCI_PERIODIC_START, per); 479 480 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 481 482 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 483 printf("%s: %d downstream port%s\n", 484 sc->sc_bus.bdev.dv_xname, sc->sc_noport, 485 sc->sc_noport != 1 ? "s" : ""); 486 487 #ifdef USB_DEBUG 488 if (ohcidebug > 5) 489 ohci_dumpregs(sc); 490 #endif 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.open_pipe = ohci_open; 494 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 495 496 return (USBD_NORMAL_COMPLETION); 497 498 bad3: 499 ohci_free_sed(sc, sc->sc_ctrl_head); 500 bad2: 501 ohci_free_sed(sc, sc->sc_bulk_head); 502 bad1: 503 ohci_freemem(sc, &sc->sc_hccadma); 504 return (r); 505 } 506 507 #ifdef USB_DEBUG 508 void ohcidump(void); 509 void ohcidump(void) { ohci_dumpregs(thesc); } 510 511 void 512 ohci_dumpregs(sc) 513 ohci_softc_t *sc; 514 { 515 printf("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 516 OREAD4(sc, OHCI_REVISION), 517 OREAD4(sc, OHCI_CONTROL), 518 OREAD4(sc, OHCI_COMMAND_STATUS)); 519 printf(" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 520 OREAD4(sc, OHCI_INTERRUPT_STATUS), 521 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 522 OREAD4(sc, OHCI_INTERRUPT_DISABLE)); 523 printf(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 524 OREAD4(sc, OHCI_HCCA), 525 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 526 OREAD4(sc, OHCI_CONTROL_HEAD_ED)); 527 printf(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 528 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 529 OREAD4(sc, OHCI_BULK_HEAD_ED), 530 OREAD4(sc, OHCI_BULK_CURRENT_ED)); 531 printf(" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 532 OREAD4(sc, OHCI_DONE_HEAD), 533 OREAD4(sc, OHCI_FM_INTERVAL), 534 OREAD4(sc, OHCI_FM_REMAINING)); 535 printf(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 536 OREAD4(sc, OHCI_FM_NUMBER), 537 OREAD4(sc, OHCI_PERIODIC_START), 538 OREAD4(sc, OHCI_LS_THRESHOLD)); 539 printf(" desca=0x%08x descb=0x%08x stat=0x%08x\n", 540 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 541 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 542 OREAD4(sc, OHCI_RH_STATUS)); 543 printf(" port1=0x%08x port2=0x%08x\n", 544 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 545 OREAD4(sc, OHCI_RH_PORT_STATUS(2))); 546 printf(" HCCA: frame_number=0x%04x done_head=0x%08x\n", 547 sc->sc_hcca->hcca_frame_number, 548 sc->sc_hcca->hcca_done_head); 549 } 550 #endif 551 552 int 553 ohci_intr(p) 554 void *p; 555 { 556 ohci_softc_t *sc = p; 557 u_int32_t intrs, eintrs; 558 ohci_physaddr_t done; 559 560 done = sc->sc_hcca->hcca_done_head; 561 if (done != 0) { 562 intrs = OHCI_WDH; 563 if (done & OHCI_DONE_INTRS) 564 intrs |= OREAD4(sc, OHCI_INTERRUPT_STATUS); 565 } else 566 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 567 if (!intrs) 568 return (0); 569 intrs &= ~OHCI_MIE; 570 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs); /* Acknowledge */ 571 eintrs = intrs & sc->sc_eintrs; 572 if (!eintrs) 573 return (0); 574 575 sc->sc_intrs++; 576 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%x(%x) eintr=%x\n", 577 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 578 (u_int)eintrs)); 579 580 if (eintrs & OHCI_SO) { 581 printf("%s: scheduling overrun\n", sc->sc_bus.bdev.dv_xname); 582 /* XXX do what */ 583 intrs &= ~OHCI_SO; 584 } 585 if (eintrs & OHCI_WDH) { 586 ohci_process_done(sc, done &~ OHCI_DONE_INTRS); 587 sc->sc_hcca->hcca_done_head = 0; 588 intrs &= ~OHCI_WDH; 589 } 590 if (eintrs & OHCI_RD) { 591 /* XXX process resume detect */ 592 } 593 if (eintrs & OHCI_UE) { 594 printf("%s: unrecoverable error, controller halted\n", 595 sc->sc_bus.bdev.dv_xname); 596 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 597 /* XXX what else */ 598 } 599 if (eintrs & OHCI_RHSC) { 600 ohci_rhsc(sc, sc->sc_intrreqh); 601 intrs &= ~OHCI_RHSC; 602 603 /* 604 * Disable RHSC interrupt for now, because it will be 605 * on until the port has been reset. 606 */ 607 ohci_rhsc_able(sc, 0); 608 } 609 610 /* Block unprocessed interrupts. XXX */ 611 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, intrs); 612 sc->sc_eintrs &= ~intrs; 613 614 return (1); 615 } 616 617 void 618 ohci_rhsc_able(sc, on) 619 ohci_softc_t *sc; 620 int on; 621 { 622 DPRINTFN(4, ("ohci_rhsc_able: on=%d\n", on)); 623 if (on) { 624 sc->sc_eintrs |= OHCI_RHSC; 625 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 626 } else { 627 sc->sc_eintrs &= ~OHCI_RHSC; 628 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_RHSC); 629 } 630 } 631 632 void 633 ohci_process_done(sc, done) 634 ohci_softc_t *sc; 635 ohci_physaddr_t done; 636 { 637 ohci_soft_td_t *std, *sdone; 638 usbd_request_handle reqh; 639 int len, cc; 640 641 DPRINTFN(10,("ohci_process_done: done=0x%08lx\n", (u_long)done)); 642 643 /* Reverse the done list. */ 644 for (sdone = 0; done; done = std->td->td_nexttd) { 645 std = ohci_hash_find_td(sc, done); 646 std->dnext = sdone; 647 sdone = std; 648 } 649 650 #ifdef USB_DEBUG 651 if (ohcidebug > 10) { 652 printf("ohci_process_done: TD done:\n"); 653 ohci_dump_tds(sdone); 654 } 655 #endif 656 657 for (std = sdone; std; std = std->dnext) { 658 reqh = std->reqh; 659 DPRINTFN(10, ("ohci_process_done: std=%p reqh=%p\n",std,reqh)); 660 cc = OHCI_TD_GET_CC(std->td->td_flags); 661 if (cc == OHCI_CC_NO_ERROR) { 662 if (std->td->td_cbp == 0) 663 len = std->len; 664 else 665 len = std->td->td_be - std->td->td_cbp + 1; 666 reqh->actlen += len; 667 if (reqh->hcpriv == std) { 668 switch (reqh->pipe->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 669 case UE_CONTROL: 670 ohci_ctrl_done(sc, reqh); 671 break; 672 case UE_INTERRUPT: 673 ohci_intr_done(sc, reqh); 674 break; 675 case UE_BULK: 676 printf("ohci_process_done: BULK done?\n"); 677 break; 678 case UE_ISOCHRONOUS: 679 printf("ohci_process_done: ISO done?\n"); 680 break; 681 } 682 /* And finally execute callback. */ 683 reqh->status = USBD_NORMAL_COMPLETION; 684 reqh->xfercb(reqh); 685 } 686 } else { 687 ohci_soft_td_t *p, *n; 688 struct ohci_pipe *opipe = 689 (struct ohci_pipe *)reqh->pipe; 690 DPRINTFN(-1,("ohci_process_done: error cc=%d\n", 691 OHCI_TD_GET_CC(std->td->td_flags))); 692 /* 693 * Endpoint is halted. First unlink all the TDs 694 * belonging to the failed transfer, and then restart 695 * the endpoint. 696 */ 697 for (p = std->nexttd; p->reqh == reqh; p = n) { 698 n = p->nexttd; 699 ohci_hash_rem_td(sc, p); 700 ohci_free_std(sc, p); 701 } 702 opipe->sed->ed->ed_headp = p->physaddr;/* clear halt */ 703 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 704 705 if (cc == OHCI_CC_STALL) 706 reqh->status = USBD_STALLED; 707 else 708 reqh->status = USBD_IOERROR; 709 reqh->xfercb(reqh); 710 } 711 ohci_hash_rem_td(sc, std); 712 ohci_free_std(sc, std); 713 } 714 } 715 716 void 717 ohci_ctrl_done(sc, reqh) 718 ohci_softc_t *sc; 719 usbd_request_handle reqh; 720 { 721 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 722 u_int len = opipe->u.ctl.length; 723 ohci_dma_t *dma; 724 725 DPRINTFN(10,("ohci_ctrl_done: reqh=%p\n", reqh)); 726 727 if (!reqh->isreq) { 728 panic("uhci_ctrl_done: not a request\n"); 729 return; 730 } 731 732 if (len != 0) { 733 dma = &opipe->u.ctl.datadma; 734 if (reqh->request.bmRequestType & UT_READ) 735 memcpy(reqh->buffer, KERNADDR(dma), len); 736 ohci_freemem(sc, dma); 737 } 738 } 739 740 void 741 ohci_intr_done(sc, reqh) 742 ohci_softc_t *sc; 743 usbd_request_handle reqh; 744 { 745 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 746 ohci_dma_t *dma; 747 ohci_soft_ed_t *sed = opipe->sed; 748 ohci_soft_td_t *xfer, *tail; 749 750 751 DPRINTFN(10,("ohci_intr_done: reqh=%p, actlen=%d\n", 752 reqh, reqh->actlen)); 753 754 dma = &opipe->u.intr.datadma; 755 memcpy(reqh->buffer, KERNADDR(dma), reqh->actlen); 756 757 if (reqh->pipe->intrreqh == reqh) { 758 xfer = opipe->tail; 759 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 760 if (!tail) { 761 reqh->status = USBD_NOMEM; 762 return; 763 } 764 tail->reqh = 0; 765 766 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 767 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 768 xfer->td->td_cbp = DMAADDR(dma); 769 xfer->nexttd = tail; 770 xfer->td->td_nexttd = tail->physaddr; 771 xfer->td->td_be = xfer->td->td_cbp + reqh->length - 1; 772 xfer->len = reqh->length; 773 xfer->reqh = reqh; 774 775 reqh->actlen = 0; 776 reqh->hcpriv = xfer; 777 778 ohci_hash_add_td(sc, xfer); 779 sed->ed->ed_tailp = tail->physaddr; 780 opipe->tail = tail; 781 } else { 782 ohci_freemem(sc, dma); 783 } 784 } 785 786 void 787 ohci_rhsc(sc, reqh) 788 ohci_softc_t *sc; 789 usbd_request_handle reqh; 790 { 791 usbd_pipe_handle pipe; 792 struct ohci_pipe *opipe; 793 u_char *p; 794 int i, m; 795 int hstatus; 796 797 hstatus = OREAD4(sc, OHCI_RH_STATUS); 798 DPRINTF(("ohci_rhsc: sc=%p reqh=%p hstatus=0x%08x\n", 799 sc, reqh, hstatus)); 800 801 if (reqh == 0) { 802 /* Just ignore the change. */ 803 return; 804 } 805 806 pipe = reqh->pipe; 807 opipe = (struct ohci_pipe *)pipe; 808 809 p = KERNADDR(&opipe->u.intr.datadma); 810 m = min(sc->sc_noport, reqh->length * 8 - 1); 811 memset(p, 0, reqh->length); 812 for (i = 1; i <= m; i++) { 813 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 814 p[i/8] |= 1 << (i%8); 815 } 816 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 817 reqh->actlen = reqh->length; 818 reqh->status = USBD_NORMAL_COMPLETION; 819 reqh->xfercb(reqh); 820 821 if (reqh->pipe->intrreqh != reqh) { 822 sc->sc_intrreqh = 0; 823 ohci_freemem(sc, &opipe->u.intr.datadma); 824 } 825 } 826 827 /* 828 * Wait here until controller claims to have an interrupt. 829 * Then call ohci_intr and return. Use timeout to avoid waiting 830 * too long. 831 */ 832 void 833 ohci_waitintr(sc, reqh) 834 ohci_softc_t *sc; 835 usbd_request_handle reqh; 836 { 837 int timo = reqh->timeout; 838 int usecs; 839 u_int32_t intrs; 840 841 reqh->status = USBD_IN_PROGRESS; 842 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 843 delay(1000); 844 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 845 DPRINTFN(10,("ohci_waitintr: 0x%04x\n", intrs)); 846 #ifdef USB_DEBUG 847 if (ohcidebug > 15) 848 ohci_dumpregs(sc); 849 #endif 850 if (intrs) { 851 ohci_intr(sc); 852 if (reqh->status != USBD_IN_PROGRESS) 853 return; 854 } 855 } 856 DPRINTF(("ohci_waitintr: timeout\n")); 857 reqh->status = USBD_TIMEOUT; 858 reqh->xfercb(reqh); 859 } 860 861 usbd_status 862 ohci_device_request(reqh) 863 usbd_request_handle reqh; 864 { 865 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 866 usb_device_request_t *req = &reqh->request; 867 usbd_device_handle dev = opipe->pipe.device; 868 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 869 int addr = dev->address; 870 ohci_soft_td_t *setup, *xfer = 0, *stat, *next, *tail; 871 ohci_soft_ed_t *sed; 872 ohci_dma_t *dmap; 873 int isread; 874 int len; 875 usbd_status r; 876 int s; 877 878 isread = req->bmRequestType & UT_READ; 879 len = UGETW(req->wLength); 880 881 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 882 req->bmRequestType, req->bRequest, UGETW(req->wValue), 883 UGETW(req->wIndex), len, addr, 884 opipe->pipe.endpoint->edesc->bEndpointAddress)); 885 886 setup = opipe->tail; 887 stat = ohci_alloc_std(sc); 888 if (!stat) { 889 r = USBD_NOMEM; 890 goto bad1; 891 } 892 tail = ohci_alloc_std(sc); 893 if (!tail) { 894 r = USBD_NOMEM; 895 goto bad2; 896 } 897 tail->reqh = 0; 898 899 sed = opipe->sed; 900 dmap = &opipe->u.ctl.datadma; 901 opipe->u.ctl.length = len; 902 903 /* Update device address */ 904 sed->ed->ed_flags = 905 (sed->ed->ed_flags & ~OHCI_ED_ADDRMASK) | 906 OHCI_ED_SET_FA(addr); 907 908 /* Set up data transaction */ 909 if (len != 0) { 910 xfer = ohci_alloc_std(sc); 911 if (!xfer) { 912 r = USBD_NOMEM; 913 goto bad3; 914 } 915 r = ohci_allocmem(sc, len, 0, dmap); 916 if (r != USBD_NORMAL_COMPLETION) 917 goto bad4; 918 xfer->td->td_flags = 919 (isread ? OHCI_TD_IN : OHCI_TD_OUT) | OHCI_TD_NOCC | 920 OHCI_TD_TOGGLE_1 | OHCI_TD_NOINTR; 921 xfer->td->td_cbp = DMAADDR(dmap); 922 xfer->nexttd = stat; 923 xfer->td->td_nexttd = stat->physaddr; 924 xfer->td->td_be = xfer->td->td_cbp + len - 1; 925 xfer->len = len; 926 xfer->reqh = reqh; 927 928 next = xfer; 929 } else 930 next = stat; 931 932 memcpy(KERNADDR(&opipe->u.ctl.reqdma), req, sizeof *req); 933 if (!isread && len != 0) 934 memcpy(KERNADDR(dmap), reqh->buffer, len); 935 936 setup->td->td_flags = OHCI_TD_SETUP | OHCI_TD_NOCC | 937 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR; 938 setup->td->td_cbp = DMAADDR(&opipe->u.ctl.reqdma); 939 setup->nexttd = next; 940 setup->td->td_nexttd = next->physaddr; 941 setup->td->td_be = setup->td->td_cbp + sizeof *req - 1; 942 setup->len = 0; /* XXX The number of byte we count */ 943 setup->reqh = reqh; 944 945 stat->td->td_flags = 946 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | OHCI_TD_NOCC | 947 OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1); 948 stat->td->td_cbp = 0; 949 stat->nexttd = tail; 950 stat->td->td_nexttd = tail->physaddr; 951 stat->td->td_be = 0; 952 stat->len = 0; 953 stat->reqh = reqh; 954 955 reqh->actlen = 0; 956 reqh->hcpriv = stat; 957 958 #if USB_DEBUG 959 if (ohcidebug > 5) { 960 printf("ohci_device_request:\n"); 961 ohci_dump_ed(sed); 962 ohci_dump_tds(setup); 963 } 964 #endif 965 966 /* Insert ED in schedule */ 967 s = splusb(); 968 ohci_hash_add_td(sc, setup); 969 if (len != 0) 970 ohci_hash_add_td(sc, xfer); 971 ohci_hash_add_td(sc, stat); 972 sed->ed->ed_tailp = tail->physaddr; 973 opipe->tail = tail; 974 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 975 if (reqh->timeout && !usbd_use_polling) 976 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 977 splx(s); 978 979 #if USB_DEBUG 980 if (ohcidebug > 5) { 981 delay(5000); 982 printf("ohci_device_request: status=%x\n", 983 OREAD4(sc, OHCI_COMMAND_STATUS)); 984 ohci_dump_ed(sed); 985 ohci_dump_tds(setup); 986 } 987 #endif 988 989 return (USBD_NORMAL_COMPLETION); 990 991 bad4: 992 ohci_free_std(sc, xfer); 993 bad3: 994 ohci_free_std(sc, tail); 995 bad2: 996 ohci_free_std(sc, stat); 997 bad1: 998 return (r); 999 } 1000 1001 /* 1002 * Add an ED to the schedule. Called at splusb(). 1003 */ 1004 void 1005 ohci_add_ed(sc, sed, head) 1006 ohci_softc_t *sc; 1007 ohci_soft_ed_t *sed; 1008 ohci_soft_ed_t *head; 1009 { 1010 sed->next = head->next; 1011 sed->ed->ed_nexted = head->ed->ed_nexted; 1012 head->next = sed; 1013 head->ed->ed_nexted = sed->physaddr; 1014 } 1015 1016 /* 1017 * When a transfer is completed the TD is added to the done queue by 1018 * the host controller. This queue is the processed by software. 1019 * Unfortunately the queue contains the physical address of the TD 1020 * and we have no simple way to translate this back a kernel address. 1021 * To make the translation possible (and fast) we use a hash table of 1022 * TDs currently in the schedule. The physical address is used as the 1023 * hash value. 1024 */ 1025 1026 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1027 /* Called at splusb() */ 1028 void 1029 ohci_hash_add_td(sc, std) 1030 ohci_softc_t *sc; 1031 ohci_soft_td_t *std; 1032 { 1033 int h = HASH(std->physaddr); 1034 1035 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1036 } 1037 1038 /* Called at splusb() */ 1039 void 1040 ohci_hash_rem_td(sc, std) 1041 ohci_softc_t *sc; 1042 ohci_soft_td_t *std; 1043 { 1044 LIST_REMOVE(std, hnext); 1045 } 1046 1047 ohci_soft_td_t * 1048 ohci_hash_find_td(sc, a) 1049 ohci_softc_t *sc; 1050 ohci_physaddr_t a; 1051 { 1052 int h = HASH(a); 1053 ohci_soft_td_t *std; 1054 1055 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1056 std != 0; 1057 std = LIST_NEXT(std, hnext)) 1058 if (std->physaddr == a) 1059 return (std); 1060 panic("ohci_hash_find_td: addr 0x%08lx not found\n", (u_long)a); 1061 } 1062 1063 void 1064 ohci_timeout(addr) 1065 void *addr; 1066 { 1067 #if 0 1068 usbd_request_handle *reqh = addr; 1069 int s; 1070 1071 DPRINTF(("ohci_timeout: reqh=%p\n", reqh)); 1072 s = splusb(); 1073 /* XXX need to inactivate TD before calling interrupt routine */ 1074 ohci_XXX_done(reqh); 1075 splx(s); 1076 #endif 1077 } 1078 1079 #ifdef USB_DEBUG 1080 void 1081 ohci_dump_tds(std) 1082 ohci_soft_td_t *std; 1083 { 1084 for (; std; std = std->nexttd) 1085 ohci_dump_td(std); 1086 } 1087 1088 void 1089 ohci_dump_td(std) 1090 ohci_soft_td_t *std; 1091 { 1092 printf("TD(%p) at %08lx: %b delay=%d ec=%d cc=%d\ncbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 1093 std, (u_long)std->physaddr, 1094 (u_long)std->td->td_flags, 1095 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1096 OHCI_TD_GET_DI(std->td->td_flags), 1097 OHCI_TD_GET_EC(std->td->td_flags), 1098 OHCI_TD_GET_CC(std->td->td_flags), 1099 (u_long)std->td->td_cbp, 1100 (u_long)std->td->td_nexttd, (u_long)std->td->td_be); 1101 } 1102 1103 void 1104 ohci_dump_ed(sed) 1105 ohci_soft_ed_t *sed; 1106 { 1107 printf("ED(%p) at %08lx: addr=%d endpt=%d maxp=%d %b\ntailp=0x%08lx headp=%b nexted=0x%08lx\n", 1108 sed, (u_long)sed->physaddr, 1109 OHCI_ED_GET_FA(sed->ed->ed_flags), 1110 OHCI_ED_GET_EN(sed->ed->ed_flags), 1111 OHCI_ED_GET_MAXP(sed->ed->ed_flags), 1112 (u_long)sed->ed->ed_flags, 1113 "\20\14OUT\15IN\16LOWSPEED\17SKIP\18ISO", 1114 (u_long)sed->ed->ed_tailp, 1115 (u_long)sed->ed->ed_headp, "\20\1HALT\2CARRY", 1116 (u_long)sed->ed->ed_nexted); 1117 } 1118 #endif 1119 1120 usbd_status 1121 ohci_open(pipe) 1122 usbd_pipe_handle pipe; 1123 { 1124 usbd_device_handle dev = pipe->device; 1125 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1126 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1127 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1128 u_int8_t addr = dev->address; 1129 ohci_soft_ed_t *sed; 1130 ohci_soft_td_t *std; 1131 usbd_status r; 1132 int s; 1133 1134 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1135 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1136 if (addr == sc->sc_addr) { 1137 switch (ed->bEndpointAddress) { 1138 case USB_CONTROL_ENDPOINT: 1139 pipe->methods = &ohci_root_ctrl_methods; 1140 break; 1141 case UE_IN | OHCI_INTR_ENDPT: 1142 pipe->methods = &ohci_root_intr_methods; 1143 break; 1144 default: 1145 return (USBD_INVAL); 1146 } 1147 } else { 1148 sed = ohci_alloc_sed(sc); 1149 if (sed == 0) 1150 goto bad0; 1151 std = ohci_alloc_std(sc); 1152 if (std == 0) 1153 goto bad1; 1154 opipe->sed = sed; 1155 opipe->tail = std; 1156 sed->ed->ed_flags = 1157 OHCI_ED_SET_FA(addr) | 1158 OHCI_ED_SET_EN(ed->bEndpointAddress) | 1159 OHCI_ED_DIR_TD | 1160 (dev->lowspeed ? OHCI_ED_SPEED : 0) | 1161 ((ed->bmAttributes & UE_XFERTYPE) == UE_ISOCHRONOUS ? 1162 OHCI_ED_FORMAT_ISO : OHCI_ED_FORMAT_GEN) | 1163 OHCI_ED_SET_MAXP(UGETW(pipe->endpoint->edesc->wMaxPacketSize)); 1164 sed->ed->ed_headp = sed->ed->ed_tailp = std->physaddr; 1165 1166 switch (ed->bmAttributes & UE_XFERTYPE) { 1167 case UE_CONTROL: 1168 pipe->methods = &ohci_device_ctrl_methods; 1169 r = ohci_allocmem(sc, sizeof(ohci_dma_t), 0, 1170 &opipe->u.ctl.reqdma); 1171 if (r != USBD_NORMAL_COMPLETION) 1172 goto bad; 1173 s = splusb(); 1174 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 1175 splx(s); 1176 break; 1177 case UE_INTERRUPT: 1178 pipe->methods = &ohci_device_intr_methods; 1179 return (ohci_device_setintr(sc, opipe, ed->bInterval)); 1180 case UE_ISOCHRONOUS: 1181 printf("ohci_open: open iso unimplemented\n"); 1182 return (USBD_XXX); 1183 case UE_BULK: 1184 printf("ohci_open: open bulk unimplemented\n"); 1185 return (USBD_XXX); 1186 } 1187 } 1188 return (USBD_NORMAL_COMPLETION); 1189 1190 bad: 1191 ohci_free_std(sc, std); 1192 bad1: 1193 ohci_free_sed(sc, sed); 1194 bad0: 1195 return (USBD_NOMEM); 1196 1197 } 1198 1199 /* 1200 * Data structures and routines to emulate the root hub. 1201 */ 1202 usb_device_descriptor_t ohci_devd = { 1203 USB_DEVICE_DESCRIPTOR_SIZE, 1204 UDESC_DEVICE, /* type */ 1205 {0x00, 0x01}, /* USB version */ 1206 UCLASS_HUB, /* class */ 1207 USUBCLASS_HUB, /* subclass */ 1208 0, /* protocol */ 1209 64, /* max packet */ 1210 {0},{0},{0x00,0x01}, /* device id */ 1211 1,2,0, /* string indicies */ 1212 1 /* # of configurations */ 1213 }; 1214 1215 usb_config_descriptor_t ohci_confd = { 1216 USB_CONFIG_DESCRIPTOR_SIZE, 1217 UDESC_CONFIG, 1218 {USB_CONFIG_DESCRIPTOR_SIZE + 1219 USB_INTERFACE_DESCRIPTOR_SIZE + 1220 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1221 1, 1222 1, 1223 0, 1224 UC_SELF_POWERED, 1225 0 /* max power */ 1226 }; 1227 1228 usb_interface_descriptor_t ohci_ifcd = { 1229 USB_INTERFACE_DESCRIPTOR_SIZE, 1230 UDESC_INTERFACE, 1231 0, 1232 0, 1233 1, 1234 UCLASS_HUB, 1235 USUBCLASS_HUB, 1236 0, 1237 0 1238 }; 1239 1240 usb_endpoint_descriptor_t ohci_endpd = { 1241 USB_ENDPOINT_DESCRIPTOR_SIZE, 1242 UDESC_ENDPOINT, 1243 UE_IN | OHCI_INTR_ENDPT, 1244 UE_INTERRUPT, 1245 {8, 0}, /* max packet */ 1246 255 1247 }; 1248 1249 usb_hub_descriptor_t ohci_hubd = { 1250 USB_HUB_DESCRIPTOR_SIZE, 1251 UDESC_HUB, 1252 0, 1253 {0,0}, 1254 0, 1255 0, 1256 {0}, 1257 {0}, 1258 }; 1259 1260 int 1261 ohci_str(p, l, s) 1262 usb_string_descriptor_t *p; 1263 int l; 1264 char *s; 1265 { 1266 int i; 1267 1268 if (l == 0) 1269 return (0); 1270 p->bLength = 2 * strlen(s) + 2; 1271 if (l == 1) 1272 return (1); 1273 p->bDescriptorType = UDESC_STRING; 1274 l -= 2; 1275 for (i = 0; s[i] && l > 1; i++, l -= 2) 1276 USETW2(p->bString[i], 0, s[i]); 1277 return (2*i+2); 1278 } 1279 1280 /* 1281 * Simulate a hardware hub by handling all the necessary requests. 1282 */ 1283 usbd_status 1284 ohci_root_ctrl_transfer(reqh) 1285 usbd_request_handle reqh; 1286 { 1287 ohci_softc_t *sc = (ohci_softc_t *)reqh->pipe->device->bus; 1288 usb_device_request_t *req; 1289 void *buf; 1290 int port, i; 1291 int len, value, index, l, totlen = 0; 1292 usb_port_status_t ps; 1293 usb_hub_descriptor_t hubd; 1294 usbd_status r; 1295 u_int32_t v; 1296 1297 if (!reqh->isreq) 1298 /* XXX panic */ 1299 return (USBD_INVAL); 1300 req = &reqh->request; 1301 buf = reqh->buffer; 1302 1303 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 1304 req->bmRequestType, req->bRequest)); 1305 1306 len = UGETW(req->wLength); 1307 value = UGETW(req->wValue); 1308 index = UGETW(req->wIndex); 1309 #define C(x,y) ((x) | ((y) << 8)) 1310 switch(C(req->bRequest, req->bmRequestType)) { 1311 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1312 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1313 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1314 /* 1315 * DEVICE_REMOTE_WAKEUP and ENDPOINT_STALL are no-ops 1316 * for the integrated root hub. 1317 */ 1318 break; 1319 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1320 if (len > 0) { 1321 *(u_int8_t *)buf = sc->sc_conf; 1322 totlen = 1; 1323 } 1324 break; 1325 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1326 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 1327 switch(value >> 8) { 1328 case UDESC_DEVICE: 1329 if ((value & 0xff) != 0) { 1330 r = USBD_IOERROR; 1331 goto ret; 1332 } 1333 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1334 memcpy(buf, &ohci_devd, l); 1335 break; 1336 case UDESC_CONFIG: 1337 if ((value & 0xff) != 0) { 1338 r = USBD_IOERROR; 1339 goto ret; 1340 } 1341 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1342 memcpy(buf, &ohci_confd, l); 1343 buf = (char *)buf + l; 1344 len -= l; 1345 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1346 totlen += l; 1347 memcpy(buf, &ohci_ifcd, l); 1348 buf = (char *)buf + l; 1349 len -= l; 1350 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1351 totlen += l; 1352 memcpy(buf, &ohci_endpd, l); 1353 break; 1354 case UDESC_STRING: 1355 if (len == 0) 1356 break; 1357 *(u_int8_t *)buf = 0; 1358 totlen = 1; 1359 switch (value & 0xff) { 1360 case 1: /* Vendor */ 1361 totlen = ohci_str(buf, len, sc->sc_vendor); 1362 break; 1363 case 2: /* Product */ 1364 totlen = ohci_str(buf, len, "OHCI root hub"); 1365 break; 1366 } 1367 break; 1368 default: 1369 r = USBD_IOERROR; 1370 goto ret; 1371 } 1372 break; 1373 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1374 if (len > 0) { 1375 *(u_int8_t *)buf = 0; 1376 totlen = 1; 1377 } 1378 break; 1379 case C(UR_GET_STATUS, UT_READ_DEVICE): 1380 if (len > 1) { 1381 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1382 totlen = 2; 1383 } 1384 break; 1385 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1386 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1387 if (len > 1) { 1388 USETW(((usb_status_t *)buf)->wStatus, 0); 1389 totlen = 2; 1390 } 1391 break; 1392 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1393 if (value >= USB_MAX_DEVICES) { 1394 r = USBD_IOERROR; 1395 goto ret; 1396 } 1397 sc->sc_addr = value; 1398 break; 1399 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1400 if (value != 0 && value != 1) { 1401 r = USBD_IOERROR; 1402 goto ret; 1403 } 1404 sc->sc_conf = value; 1405 break; 1406 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1407 break; 1408 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1409 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1410 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1411 r = USBD_IOERROR; 1412 goto ret; 1413 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1414 break; 1415 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1416 break; 1417 /* Hub requests */ 1418 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1419 break; 1420 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1421 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE port=%d feature=%d\n", 1422 index, value)); 1423 if (index < 1 || index > sc->sc_noport) { 1424 r = USBD_IOERROR; 1425 goto ret; 1426 } 1427 port = OHCI_RH_PORT_STATUS(index); 1428 switch(value) { 1429 case UHF_PORT_ENABLE: 1430 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 1431 break; 1432 case UHF_PORT_SUSPEND: 1433 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 1434 break; 1435 case UHF_PORT_POWER: 1436 OWRITE4(sc, port, UPS_LOW_SPEED); 1437 break; 1438 case UHF_C_PORT_CONNECTION: 1439 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 1440 break; 1441 case UHF_C_PORT_ENABLE: 1442 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 1443 break; 1444 case UHF_C_PORT_SUSPEND: 1445 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 1446 break; 1447 case UHF_C_PORT_OVER_CURRENT: 1448 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 1449 break; 1450 case UHF_C_PORT_RESET: 1451 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 1452 break; 1453 default: 1454 r = USBD_IOERROR; 1455 goto ret; 1456 } 1457 switch(value) { 1458 case UHF_C_PORT_CONNECTION: 1459 case UHF_C_PORT_ENABLE: 1460 case UHF_C_PORT_SUSPEND: 1461 case UHF_C_PORT_OVER_CURRENT: 1462 case UHF_C_PORT_RESET: 1463 /* Enable RHSC interrupt if condition is cleared. */ 1464 if ((OREAD4(sc, port) >> 16) == 0) 1465 ohci_rhsc_able(sc, 1); 1466 break; 1467 default: 1468 break; 1469 } 1470 break; 1471 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1472 if (value != 0) { 1473 r = USBD_IOERROR; 1474 goto ret; 1475 } 1476 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 1477 hubd = ohci_hubd; 1478 hubd.bNbrPorts = sc->sc_noport; 1479 USETW(hubd.bHubCharacteristics, 1480 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 1481 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 1482 /* XXX overcurrent */ 1483 ); 1484 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 1485 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 1486 if (sc->sc_noport < 8) { 1487 hubd.DeviceRemovable[0] = (u_int8_t)v; 1488 hubd.PortPowerCtrlMask[0] = (u_int8_t)(v >> 16); 1489 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE; 1490 } else { 1491 hubd.DeviceRemovable[0] = (u_int8_t)v; 1492 hubd.DeviceRemovable[1] = (u_int8_t)(v>>8); 1493 hubd.PortPowerCtrlMask[1] = (u_int8_t)(v >> 16); 1494 hubd.PortPowerCtrlMask[2] = (u_int8_t)(v >> 24); 1495 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + 2; 1496 } 1497 l = min(len, hubd.bDescLength); 1498 totlen = l; 1499 memcpy(buf, &hubd, l); 1500 break; 1501 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1502 if (len != 4) { 1503 r = USBD_IOERROR; 1504 goto ret; 1505 } 1506 memset(buf, 0, len); /* ? XXX */ 1507 totlen = len; 1508 break; 1509 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1510 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 1511 index)); 1512 if (index < 1 || index > sc->sc_noport) { 1513 r = USBD_IOERROR; 1514 goto ret; 1515 } 1516 if (len != 4) { 1517 r = USBD_IOERROR; 1518 goto ret; 1519 } 1520 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 1521 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 1522 v)); 1523 USETW(ps.wPortStatus, v); 1524 USETW(ps.wPortChange, v >> 16); 1525 l = min(len, sizeof ps); 1526 memcpy(buf, &ps, l); 1527 totlen = l; 1528 break; 1529 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1530 r = USBD_IOERROR; 1531 goto ret; 1532 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1533 break; 1534 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1535 if (index < 1 || index > sc->sc_noport) { 1536 r = USBD_IOERROR; 1537 goto ret; 1538 } 1539 port = OHCI_RH_PORT_STATUS(index); 1540 switch(value) { 1541 case UHF_PORT_ENABLE: 1542 OWRITE4(sc, port, UPS_PORT_ENABLED); 1543 break; 1544 case UHF_PORT_SUSPEND: 1545 OWRITE4(sc, port, UPS_SUSPEND); 1546 break; 1547 case UHF_PORT_RESET: 1548 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", index)); 1549 OWRITE4(sc, port, UPS_RESET); 1550 for (i = 0; i < 10; i++) { 1551 usbd_delay_ms(10); 1552 if ((OREAD4(sc, port) & UPS_RESET) == 0) 1553 break; 1554 } 1555 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 1556 index, OREAD4(sc, port))); 1557 break; 1558 case UHF_PORT_POWER: 1559 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power %d\n", index)); 1560 OWRITE4(sc, port, UPS_PORT_POWER); 1561 break; 1562 default: 1563 r = USBD_IOERROR; 1564 goto ret; 1565 } 1566 break; 1567 default: 1568 r = USBD_IOERROR; 1569 goto ret; 1570 } 1571 reqh->actlen = totlen; 1572 r = USBD_NORMAL_COMPLETION; 1573 ret: 1574 reqh->status = r; 1575 reqh->xfercb(reqh); 1576 return (USBD_IN_PROGRESS); 1577 } 1578 1579 /* Abort a root control request. */ 1580 void 1581 ohci_root_ctrl_abort(reqh) 1582 usbd_request_handle reqh; 1583 { 1584 } 1585 1586 /* Close the root pipe. */ 1587 void 1588 ohci_root_ctrl_close(pipe) 1589 usbd_pipe_handle pipe; 1590 { 1591 DPRINTF(("ohci_root_ctrl_close\n")); 1592 } 1593 1594 usbd_status 1595 ohci_root_intr_transfer(reqh) 1596 usbd_request_handle reqh; 1597 { 1598 usbd_pipe_handle pipe = reqh->pipe; 1599 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1600 struct ohci_pipe *upipe = (struct ohci_pipe *)pipe; 1601 ohci_dma_t *dmap; 1602 usbd_status r; 1603 int len; 1604 1605 len = reqh->length; 1606 dmap = &upipe->u.intr.datadma; 1607 if (len == 0) 1608 return (USBD_INVAL); /* XXX should it be? */ 1609 1610 r = ohci_allocmem(sc, len, 0, dmap); 1611 if (r != USBD_NORMAL_COMPLETION) 1612 return (r); 1613 sc->sc_intrreqh = reqh; 1614 1615 return (USBD_IN_PROGRESS); 1616 } 1617 1618 /* Abort a root control request. */ 1619 void 1620 ohci_root_intr_abort(reqh) 1621 usbd_request_handle reqh; 1622 { 1623 } 1624 1625 /* Close the root pipe. */ 1626 void 1627 ohci_root_intr_close(pipe) 1628 usbd_pipe_handle pipe; 1629 { 1630 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1631 sc->sc_intrreqh = 0; 1632 1633 DPRINTF(("ohci_root_intr_close\n")); 1634 } 1635 1636 /************************/ 1637 1638 usbd_status 1639 ohci_device_ctrl_transfer(reqh) 1640 usbd_request_handle reqh; 1641 { 1642 usbd_status r; 1643 1644 if (!reqh->isreq) { 1645 /* XXX panic */ 1646 printf("ohci_device_ctrl_transfer: not a request\n"); 1647 return (USBD_INVAL); 1648 } 1649 1650 r = ohci_device_request(reqh); 1651 if (r != USBD_NORMAL_COMPLETION) 1652 return (r); 1653 1654 if (usbd_use_polling) 1655 ohci_waitintr((ohci_softc_t *)reqh->pipe->device->bus, reqh); 1656 return (USBD_IN_PROGRESS); 1657 } 1658 1659 /* Abort a device control request. */ 1660 void 1661 ohci_device_ctrl_abort(reqh) 1662 usbd_request_handle reqh; 1663 { 1664 /* XXX */ 1665 usbd_delay_ms(2); /* make sure it is finished */ 1666 } 1667 1668 /* Close a device control pipe. */ 1669 void 1670 ohci_device_ctrl_close(pipe) 1671 usbd_pipe_handle pipe; 1672 { 1673 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1674 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1675 ohci_soft_ed_t *p, *sed = opipe->sed; 1676 int s; 1677 1678 s = splusb(); 1679 sed->ed->ed_flags |= OHCI_ED_SKIP; 1680 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1681 usbd_delay_ms(2); 1682 /* XXX */ 1683 for (p = sc->sc_ctrl_head; p && p->next != opipe->sed; p = p->next) 1684 ; 1685 if (!p) 1686 panic("ohci_device_ctrl_close: ED not found\n"); 1687 p->next = p->next->next; 1688 splx(s); 1689 ohci_free_std(sc, opipe->tail); 1690 ohci_free_sed(sc, opipe->sed); 1691 /* XXX free other resources */ 1692 } 1693 1694 /************************/ 1695 1696 usbd_status 1697 ohci_device_intr_transfer(reqh) 1698 usbd_request_handle reqh; 1699 { 1700 struct ohci_pipe *opipe = (struct ohci_pipe *)reqh->pipe; 1701 usbd_device_handle dev = opipe->pipe.device; 1702 ohci_softc_t *sc = (ohci_softc_t *)dev->bus; 1703 ohci_soft_ed_t *sed = opipe->sed; 1704 ohci_soft_td_t *xfer, *tail; 1705 ohci_dma_t *dmap; 1706 usbd_status r; 1707 int len; 1708 int s; 1709 1710 DPRINTFN(3, ("ohci_device_intr_transfer: reqh=%p buf=%p len=%d flags=%d priv=%p\n", 1711 reqh, reqh->buffer, reqh->length, reqh->flags, reqh->priv)); 1712 1713 if (reqh->isreq) 1714 panic("ohci_device_intr_transfer: a request\n"); 1715 1716 len = reqh->length; 1717 dmap = &opipe->u.intr.datadma; 1718 if (len == 0) 1719 return (USBD_INVAL); /* XXX should it be? */ 1720 1721 xfer = opipe->tail; 1722 tail = ohci_alloc_std(sc); 1723 if (!tail) { 1724 r = USBD_NOMEM; 1725 goto ret1; 1726 } 1727 tail->reqh = 0; 1728 1729 r = ohci_allocmem(sc, len, 0, dmap); 1730 if (r != USBD_NORMAL_COMPLETION) 1731 goto ret2; 1732 1733 xfer->td->td_flags = OHCI_TD_IN | OHCI_TD_NOCC | 1734 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY; 1735 xfer->td->td_cbp = DMAADDR(dmap); 1736 xfer->nexttd = tail; 1737 xfer->td->td_nexttd = tail->physaddr; 1738 xfer->td->td_be = xfer->td->td_cbp + len - 1; 1739 xfer->len = len; 1740 xfer->reqh = reqh; 1741 1742 reqh->actlen = 0; 1743 reqh->hcpriv = xfer; 1744 1745 #if USB_DEBUG 1746 if (ohcidebug > 5) { 1747 printf("ohci_device_intr_transfer:\n"); 1748 ohci_dump_ed(sed); 1749 ohci_dump_tds(xfer); 1750 } 1751 #endif 1752 1753 /* Insert ED in schedule */ 1754 s = splusb(); 1755 ohci_hash_add_td(sc, xfer); 1756 sed->ed->ed_tailp = tail->physaddr; 1757 opipe->tail = tail; 1758 #if 0 1759 if (reqh->timeout && !usbd_use_polling) 1760 timeout(ohci_timeout, reqh, MS_TO_TICKS(reqh->timeout)); 1761 #endif 1762 sed->ed->ed_flags &= ~OHCI_ED_SKIP; 1763 splx(s); 1764 1765 #ifdef USB_DEBUG 1766 if (ohcidebug > 5) { 1767 delay(5000); 1768 printf("ohci_device_intr_transfer: status=%x\n", 1769 OREAD4(sc, OHCI_COMMAND_STATUS)); 1770 ohci_dump_ed(sed); 1771 ohci_dump_tds(xfer); 1772 } 1773 #endif 1774 1775 return (USBD_IN_PROGRESS); 1776 1777 ret2: 1778 ohci_free_std(sc, xfer); 1779 ret1: 1780 return (r); 1781 } 1782 1783 /* Abort a device control request. */ 1784 void 1785 ohci_device_intr_abort(reqh) 1786 usbd_request_handle reqh; 1787 { 1788 struct uhci_pipe *opipe; 1789 1790 /* XXX */ 1791 usbd_delay_ms(2); /* make sure it is finished */ 1792 if (reqh->pipe->intrreqh == reqh) { 1793 DPRINTF(("ohci_device_intr_abort: remove\n")); 1794 reqh->pipe->intrreqh = 0; 1795 opipe = (struct uhci_pipe *)reqh->pipe; 1796 ohci_intr_done((ohci_softc_t *)reqh->pipe->device->bus, reqh); 1797 } 1798 } 1799 1800 /* Close a device interrupt pipe. */ 1801 void 1802 ohci_device_intr_close(pipe) 1803 usbd_pipe_handle pipe; 1804 { 1805 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 1806 ohci_softc_t *sc = (ohci_softc_t *)pipe->device->bus; 1807 int nslots = opipe->u.intr.nslots; 1808 int pos = opipe->u.intr.pos; 1809 int j; 1810 ohci_soft_ed_t *p, *sed = opipe->sed; 1811 int s; 1812 1813 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 1814 pipe, nslots, pos)); 1815 s = splusb(); 1816 sed->ed->ed_flags |= OHCI_ED_SKIP; 1817 if ((sed->ed->ed_tailp & OHCI_TAILMASK) != sed->ed->ed_headp) 1818 usbd_delay_ms(2); 1819 1820 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 1821 ; 1822 if (!p) 1823 panic("ohci_device_intr_close: ED not found\n"); 1824 p->next = sed->next; 1825 p->ed->ed_nexted = sed->ed->ed_nexted; 1826 splx(s); 1827 1828 for (j = 0; j < nslots; j++) 1829 --sc->sc_bws[pos * nslots + j]; 1830 1831 ohci_free_std(sc, opipe->tail); 1832 ohci_free_sed(sc, opipe->sed); 1833 /* XXX free other resources */ 1834 } 1835 1836 usbd_status 1837 ohci_device_setintr(sc, opipe, ival) 1838 ohci_softc_t *sc; 1839 struct ohci_pipe *opipe; 1840 int ival; 1841 { 1842 int i, j, s, best; 1843 u_int npoll, slow, shigh, nslots; 1844 u_int bestbw, bw; 1845 ohci_soft_ed_t *hsed, *sed = opipe->sed; 1846 1847 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 1848 if (ival == 0) { 1849 printf("ohci_setintr: 0 interval\n"); 1850 return (USBD_INVAL); 1851 } 1852 1853 npoll = OHCI_NO_INTRS; 1854 while (npoll > ival) 1855 npoll /= 2; 1856 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 1857 1858 /* 1859 * We now know which level in the tree the ED must go into. 1860 * Figure out which slot has most bandwidth left over. 1861 * Slots to examine: 1862 * npoll 1863 * 1 0 1864 * 2 1 2 1865 * 4 3 4 5 6 1866 * 8 7 8 9 10 11 12 13 14 1867 * N (N-1) .. (N-1+N-1) 1868 */ 1869 slow = npoll-1; 1870 shigh = slow + npoll; 1871 nslots = OHCI_NO_INTRS / npoll; 1872 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 1873 bw = 0; 1874 for (j = 0; j < nslots; j++) 1875 bw += sc->sc_bws[i * nslots + j]; 1876 if (bw < bestbw) { 1877 best = i; 1878 bestbw = bw; 1879 } 1880 } 1881 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 1882 best, slow, shigh, bestbw)); 1883 1884 s = splusb(); 1885 hsed = sc->sc_eds[best]; 1886 sed->next = hsed->next; 1887 sed->ed->ed_nexted = hsed->ed->ed_nexted; 1888 hsed->next = sed; 1889 hsed->ed->ed_nexted = sed->physaddr; 1890 splx(s); 1891 1892 for (j = 0; j < nslots; j++) 1893 ++sc->sc_bws[best * nslots + j]; 1894 opipe->u.intr.nslots = nslots; 1895 opipe->u.intr.pos = best; 1896 1897 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 1898 return (USBD_NORMAL_COMPLETION); 1899 } 1900 1901
Indexes created Tue Sep 23 14:10:03 GMT 2025