ohci.c revision 1.206.2.3
1 /* $NetBSD: ohci.c,v 1.206.2.3 2011/06/12 00:24:26 rmind Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.206.2.3 2011/06/12 00:24:26 rmind Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/device.h> 53 #include <sys/select.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 57 #include <sys/bus.h> 58 #include <machine/endian.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/ohcireg.h> 67 #include <dev/usb/ohcivar.h> 68 #include <dev/usb/usbroothub_subr.h> 69 70 71 72 #ifdef OHCI_DEBUG 73 #define DPRINTF(x) if (ohcidebug) printf x 74 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 75 int ohcidebug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n,x) 79 #endif 80 81 #if BYTE_ORDER == BIG_ENDIAN 82 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 83 #else 84 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 85 #endif 86 87 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 88 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 89 #define HTOO16(val) O16TOH(val) 90 #define HTOO32(val) O32TOH(val) 91 92 struct ohci_pipe; 93 94 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 95 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 96 97 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 98 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 99 100 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 101 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 102 103 #if 0 104 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 105 ohci_soft_td_t *); 106 #endif 107 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 108 ohci_softc_t *, int, int, usbd_xfer_handle, 109 ohci_soft_td_t *, ohci_soft_td_t **); 110 111 Static usbd_status ohci_open(usbd_pipe_handle); 112 Static void ohci_poll(struct usbd_bus *); 113 Static void ohci_softintr(void *); 114 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 115 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 116 117 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 118 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 121 Static void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 122 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 123 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 124 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 125 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 126 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 127 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 128 129 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 130 Static void ohci_device_isoc_enter(usbd_xfer_handle); 131 132 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 133 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 134 135 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 136 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 137 138 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 139 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 140 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 141 Static void ohci_root_ctrl_close(usbd_pipe_handle); 142 Static void ohci_root_ctrl_done(usbd_xfer_handle); 143 144 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 145 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 146 Static void ohci_root_intr_abort(usbd_xfer_handle); 147 Static void ohci_root_intr_close(usbd_pipe_handle); 148 Static void ohci_root_intr_done(usbd_xfer_handle); 149 150 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 151 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 152 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 153 Static void ohci_device_ctrl_close(usbd_pipe_handle); 154 Static void ohci_device_ctrl_done(usbd_xfer_handle); 155 156 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 157 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 158 Static void ohci_device_bulk_abort(usbd_xfer_handle); 159 Static void ohci_device_bulk_close(usbd_pipe_handle); 160 Static void ohci_device_bulk_done(usbd_xfer_handle); 161 162 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 164 Static void ohci_device_intr_abort(usbd_xfer_handle); 165 Static void ohci_device_intr_close(usbd_pipe_handle); 166 Static void ohci_device_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 169 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 170 Static void ohci_device_isoc_abort(usbd_xfer_handle); 171 Static void ohci_device_isoc_close(usbd_pipe_handle); 172 Static void ohci_device_isoc_done(usbd_xfer_handle); 173 174 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 175 struct ohci_pipe *pipe, int ival); 176 177 Static void ohci_timeout(void *); 178 Static void ohci_timeout_task(void *); 179 Static void ohci_rhsc_enable(void *); 180 181 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 182 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 183 184 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 185 Static void ohci_noop(usbd_pipe_handle pipe); 186 187 #ifdef OHCI_DEBUG 188 Static void ohci_dumpregs(ohci_softc_t *); 189 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 191 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 192 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 193 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 194 #endif 195 196 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 197 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 198 #define OWRITE1(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 #define OWRITE2(sc, r, x) \ 201 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 202 #define OWRITE4(sc, r, x) \ 203 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 204 static __inline uint8_t 205 OREAD1(ohci_softc_t *sc, bus_size_t r) 206 { 207 208 OBARR(sc); 209 return bus_space_read_1(sc->iot, sc->ioh, r); 210 } 211 212 static __inline uint16_t 213 OREAD2(ohci_softc_t *sc, bus_size_t r) 214 { 215 216 OBARR(sc); 217 return bus_space_read_2(sc->iot, sc->ioh, r); 218 } 219 220 static __inline uint32_t 221 OREAD4(ohci_softc_t *sc, bus_size_t r) 222 { 223 224 OBARR(sc); 225 return bus_space_read_4(sc->iot, sc->ioh, r); 226 } 227 228 /* Reverse the bits in a value 0 .. 31 */ 229 Static u_int8_t revbits[OHCI_NO_INTRS] = 230 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 231 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 232 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 233 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 234 235 struct ohci_pipe { 236 struct usbd_pipe pipe; 237 ohci_soft_ed_t *sed; 238 union { 239 ohci_soft_td_t *td; 240 ohci_soft_itd_t *itd; 241 } tail; 242 /* Info needed for different pipe kinds. */ 243 union { 244 /* Control pipe */ 245 struct { 246 usb_dma_t reqdma; 247 u_int length; 248 ohci_soft_td_t *setup, *data, *stat; 249 } ctl; 250 /* Interrupt pipe */ 251 struct { 252 int nslots; 253 int pos; 254 } intr; 255 /* Bulk pipe */ 256 struct { 257 u_int length; 258 int isread; 259 } bulk; 260 /* Iso pipe */ 261 struct iso { 262 int next, inuse; 263 } iso; 264 } u; 265 }; 266 267 #define OHCI_INTR_ENDPT 1 268 269 Static const struct usbd_bus_methods ohci_bus_methods = { 270 ohci_open, 271 ohci_softintr, 272 ohci_poll, 273 ohci_allocm, 274 ohci_freem, 275 ohci_allocx, 276 ohci_freex, 277 }; 278 279 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 280 ohci_root_ctrl_transfer, 281 ohci_root_ctrl_start, 282 ohci_root_ctrl_abort, 283 ohci_root_ctrl_close, 284 ohci_noop, 285 ohci_root_ctrl_done, 286 }; 287 288 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 289 ohci_root_intr_transfer, 290 ohci_root_intr_start, 291 ohci_root_intr_abort, 292 ohci_root_intr_close, 293 ohci_noop, 294 ohci_root_intr_done, 295 }; 296 297 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 298 ohci_device_ctrl_transfer, 299 ohci_device_ctrl_start, 300 ohci_device_ctrl_abort, 301 ohci_device_ctrl_close, 302 ohci_noop, 303 ohci_device_ctrl_done, 304 }; 305 306 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 307 ohci_device_intr_transfer, 308 ohci_device_intr_start, 309 ohci_device_intr_abort, 310 ohci_device_intr_close, 311 ohci_device_clear_toggle, 312 ohci_device_intr_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 316 ohci_device_bulk_transfer, 317 ohci_device_bulk_start, 318 ohci_device_bulk_abort, 319 ohci_device_bulk_close, 320 ohci_device_clear_toggle, 321 ohci_device_bulk_done, 322 }; 323 324 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 325 ohci_device_isoc_transfer, 326 ohci_device_isoc_start, 327 ohci_device_isoc_abort, 328 ohci_device_isoc_close, 329 ohci_noop, 330 ohci_device_isoc_done, 331 }; 332 333 int 334 ohci_activate(device_t self, enum devact act) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 switch (act) { 339 case DVACT_DEACTIVATE: 340 sc->sc_dying = 1; 341 return 0; 342 default: 343 return EOPNOTSUPP; 344 } 345 } 346 347 void 348 ohci_childdet(device_t self, device_t child) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 KASSERT(sc->sc_child == child); 353 sc->sc_child = NULL; 354 } 355 356 int 357 ohci_detach(struct ohci_softc *sc, int flags) 358 { 359 int rv = 0; 360 usbd_xfer_handle xfer; 361 362 if (sc->sc_child != NULL) 363 rv = config_detach(sc->sc_child, flags); 364 365 if (rv != 0) 366 return (rv); 367 368 callout_stop(&sc->sc_tmo_rhsc); 369 370 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 371 callout_destroy(&sc->sc_tmo_rhsc); 372 373 if (sc->sc_hcca != NULL) 374 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 375 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 376 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 377 free(xfer, M_USB); 378 } 379 380 return (rv); 381 } 382 383 ohci_soft_ed_t * 384 ohci_alloc_sed(ohci_softc_t *sc) 385 { 386 ohci_soft_ed_t *sed; 387 usbd_status err; 388 int i, offs; 389 usb_dma_t dma; 390 391 if (sc->sc_freeeds == NULL) { 392 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 393 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 394 OHCI_ED_ALIGN, &dma); 395 if (err) 396 return (0); 397 for(i = 0; i < OHCI_SED_CHUNK; i++) { 398 offs = i * OHCI_SED_SIZE; 399 sed = KERNADDR(&dma, offs); 400 sed->physaddr = DMAADDR(&dma, offs); 401 sed->dma = dma; 402 sed->offs = offs; 403 sed->next = sc->sc_freeeds; 404 sc->sc_freeeds = sed; 405 } 406 } 407 sed = sc->sc_freeeds; 408 sc->sc_freeeds = sed->next; 409 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 410 sed->next = 0; 411 return (sed); 412 } 413 414 void 415 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 416 { 417 sed->next = sc->sc_freeeds; 418 sc->sc_freeeds = sed; 419 } 420 421 ohci_soft_td_t * 422 ohci_alloc_std(ohci_softc_t *sc) 423 { 424 ohci_soft_td_t *std; 425 usbd_status err; 426 int i, offs; 427 usb_dma_t dma; 428 int s; 429 430 if (sc->sc_freetds == NULL) { 431 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 432 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 433 OHCI_TD_ALIGN, &dma); 434 if (err) 435 return (NULL); 436 s = splusb(); 437 for(i = 0; i < OHCI_STD_CHUNK; i++) { 438 offs = i * OHCI_STD_SIZE; 439 std = KERNADDR(&dma, offs); 440 std->physaddr = DMAADDR(&dma, offs); 441 std->dma = dma; 442 std->offs = offs; 443 std->nexttd = sc->sc_freetds; 444 sc->sc_freetds = std; 445 } 446 splx(s); 447 } 448 449 s = splusb(); 450 std = sc->sc_freetds; 451 sc->sc_freetds = std->nexttd; 452 memset(&std->td, 0, sizeof(ohci_td_t)); 453 std->nexttd = NULL; 454 std->xfer = NULL; 455 ohci_hash_add_td(sc, std); 456 splx(s); 457 458 return (std); 459 } 460 461 void 462 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 463 { 464 int s; 465 466 s = splusb(); 467 ohci_hash_rem_td(sc, std); 468 std->nexttd = sc->sc_freetds; 469 sc->sc_freetds = std; 470 splx(s); 471 } 472 473 usbd_status 474 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 475 int alen, int rd, usbd_xfer_handle xfer, 476 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 477 { 478 ohci_soft_td_t *next, *cur; 479 ohci_physaddr_t dataphys, dataphysend; 480 u_int32_t tdflags; 481 int len, curlen; 482 usb_dma_t *dma = &xfer->dmabuf; 483 u_int16_t flags = xfer->flags; 484 485 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 486 487 len = alen; 488 cur = sp; 489 dataphys = DMAADDR(dma, 0); 490 dataphysend = OHCI_PAGE(dataphys + len - 1); 491 usb_syncmem(dma, 0, len, 492 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 493 tdflags = HTOO32( 494 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 495 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 496 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 497 498 for (;;) { 499 next = ohci_alloc_std(sc); 500 if (next == NULL) 501 goto nomem; 502 503 /* The OHCI hardware can handle at most one page crossing. */ 504 if (OHCI_PAGE(dataphys) == dataphysend || 505 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 506 /* we can handle it in this TD */ 507 curlen = len; 508 } else { 509 /* must use multiple TDs, fill as much as possible. */ 510 curlen = 2 * OHCI_PAGE_SIZE - 511 (dataphys & (OHCI_PAGE_SIZE-1)); 512 /* the length must be a multiple of the max size */ 513 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 514 #ifdef DIAGNOSTIC 515 if (curlen == 0) 516 panic("ohci_alloc_std: curlen == 0"); 517 #endif 518 } 519 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 520 "dataphysend=0x%08x len=%d curlen=%d\n", 521 dataphys, dataphysend, 522 len, curlen)); 523 len -= curlen; 524 525 cur->td.td_flags = tdflags; 526 cur->td.td_cbp = HTOO32(dataphys); 527 cur->nexttd = next; 528 cur->td.td_nexttd = HTOO32(next->physaddr); 529 cur->td.td_be = HTOO32(dataphys + curlen - 1); 530 cur->len = curlen; 531 cur->flags = OHCI_ADD_LEN; 532 cur->xfer = xfer; 533 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 536 dataphys, dataphys + curlen - 1)); 537 if (len == 0) 538 break; 539 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 540 dataphys += curlen; 541 cur = next; 542 } 543 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 544 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 545 /* Force a 0 length transfer at the end. */ 546 547 cur = next; 548 next = ohci_alloc_std(sc); 549 if (next == NULL) 550 goto nomem; 551 552 cur->td.td_flags = tdflags; 553 cur->td.td_cbp = 0; /* indicate 0 length packet */ 554 cur->nexttd = next; 555 cur->td.td_nexttd = HTOO32(next->physaddr); 556 cur->td.td_be = ~0; 557 cur->len = 0; 558 cur->flags = 0; 559 cur->xfer = xfer; 560 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 563 } 564 *ep = cur; 565 566 return (USBD_NORMAL_COMPLETION); 567 568 nomem: 569 /* XXX free chain */ 570 return (USBD_NOMEM); 571 } 572 573 #if 0 574 Static void 575 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 576 ohci_soft_td_t *stdend) 577 { 578 ohci_soft_td_t *p; 579 580 for (; std != stdend; std = p) { 581 p = std->nexttd; 582 ohci_free_std(sc, std); 583 } 584 } 585 #endif 586 587 ohci_soft_itd_t * 588 ohci_alloc_sitd(ohci_softc_t *sc) 589 { 590 ohci_soft_itd_t *sitd; 591 usbd_status err; 592 int i, s, offs; 593 usb_dma_t dma; 594 595 if (sc->sc_freeitds == NULL) { 596 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 597 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 598 OHCI_ITD_ALIGN, &dma); 599 if (err) 600 return (NULL); 601 s = splusb(); 602 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 603 offs = i * OHCI_SITD_SIZE; 604 sitd = KERNADDR(&dma, offs); 605 sitd->physaddr = DMAADDR(&dma, offs); 606 sitd->dma = dma; 607 sitd->offs = offs; 608 sitd->nextitd = sc->sc_freeitds; 609 sc->sc_freeitds = sitd; 610 } 611 splx(s); 612 } 613 614 s = splusb(); 615 sitd = sc->sc_freeitds; 616 sc->sc_freeitds = sitd->nextitd; 617 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 618 sitd->nextitd = NULL; 619 sitd->xfer = NULL; 620 ohci_hash_add_itd(sc, sitd); 621 splx(s); 622 623 #ifdef DIAGNOSTIC 624 sitd->isdone = 0; 625 #endif 626 627 return (sitd); 628 } 629 630 void 631 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 632 { 633 int s; 634 635 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 636 637 #ifdef DIAGNOSTIC 638 if (!sitd->isdone) { 639 panic("ohci_free_sitd: sitd=%p not done", sitd); 640 return; 641 } 642 /* Warn double free */ 643 sitd->isdone = 0; 644 #endif 645 646 s = splusb(); 647 ohci_hash_rem_itd(sc, sitd); 648 sitd->nextitd = sc->sc_freeitds; 649 sc->sc_freeitds = sitd; 650 splx(s); 651 } 652 653 usbd_status 654 ohci_init(ohci_softc_t *sc) 655 { 656 ohci_soft_ed_t *sed, *psed; 657 usbd_status err; 658 int i; 659 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 660 661 DPRINTF(("ohci_init: start\n")); 662 aprint_normal_dev(sc->sc_dev, ""); 663 664 sc->sc_hcca = NULL; 665 callout_init(&sc->sc_tmo_rhsc, 0); 666 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_tds[i]); 669 for (i = 0; i < OHCI_HASH_SIZE; i++) 670 LIST_INIT(&sc->sc_hash_itds[i]); 671 672 SIMPLEQ_INIT(&sc->sc_free_xfers); 673 674 rev = OREAD4(sc, OHCI_REVISION); 675 aprint_normal("OHCI version %d.%d%s\n", 676 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 677 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 678 679 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 680 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 681 sc->sc_bus.usbrev = USBREV_UNKNOWN; 682 return (USBD_INVAL); 683 } 684 sc->sc_bus.usbrev = USBREV_1_0; 685 686 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 687 USB_MEM_RESERVE); 688 689 /* XXX determine alignment by R/W */ 690 /* Allocate the HCCA area. */ 691 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 692 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 693 if (err) { 694 sc->sc_hcca = NULL; 695 return err; 696 } 697 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 698 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 699 700 sc->sc_eintrs = OHCI_NORMAL_INTRS; 701 702 /* Allocate dummy ED that starts the control list. */ 703 sc->sc_ctrl_head = ohci_alloc_sed(sc); 704 if (sc->sc_ctrl_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad1; 707 } 708 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 709 710 /* Allocate dummy ED that starts the bulk list. */ 711 sc->sc_bulk_head = ohci_alloc_sed(sc); 712 if (sc->sc_bulk_head == NULL) { 713 err = USBD_NOMEM; 714 goto bad2; 715 } 716 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 717 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 718 sizeof(sc->sc_bulk_head->ed), 719 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 720 721 /* Allocate dummy ED that starts the isochronous list. */ 722 sc->sc_isoc_head = ohci_alloc_sed(sc); 723 if (sc->sc_isoc_head == NULL) { 724 err = USBD_NOMEM; 725 goto bad3; 726 } 727 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 728 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 729 sizeof(sc->sc_isoc_head->ed), 730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 731 732 /* Allocate all the dummy EDs that make up the interrupt tree. */ 733 for (i = 0; i < OHCI_NO_EDS; i++) { 734 sed = ohci_alloc_sed(sc); 735 if (sed == NULL) { 736 while (--i >= 0) 737 ohci_free_sed(sc, sc->sc_eds[i]); 738 err = USBD_NOMEM; 739 goto bad4; 740 } 741 /* All ED fields are set to 0. */ 742 sc->sc_eds[i] = sed; 743 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 744 if (i != 0) 745 psed = sc->sc_eds[(i-1) / 2]; 746 else 747 psed= sc->sc_isoc_head; 748 sed->next = psed; 749 sed->ed.ed_nexted = HTOO32(psed->physaddr); 750 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 } 753 /* 754 * Fill HCCA interrupt table. The bit reversal is to get 755 * the tree set up properly to spread the interrupts. 756 */ 757 for (i = 0; i < OHCI_NO_INTRS; i++) 758 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 759 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 760 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 761 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 762 763 #ifdef OHCI_DEBUG 764 if (ohcidebug > 15) { 765 for (i = 0; i < OHCI_NO_EDS; i++) { 766 printf("ed#%d ", i); 767 ohci_dump_ed(sc, sc->sc_eds[i]); 768 } 769 printf("iso "); 770 ohci_dump_ed(sc, sc->sc_isoc_head); 771 } 772 #endif 773 774 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 775 ctl = OREAD4(sc, OHCI_CONTROL); 776 rwc = ctl & OHCI_RWC; 777 fm = OREAD4(sc, OHCI_FM_INTERVAL); 778 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 779 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 780 781 /* Determine in what context we are running. */ 782 if (ctl & OHCI_IR) { 783 /* SMM active, request change */ 784 DPRINTF(("ohci_init: SMM active, request owner change\n")); 785 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 786 (OHCI_OC | OHCI_MIE)) 787 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 788 s = OREAD4(sc, OHCI_COMMAND_STATUS); 789 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 790 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 791 usb_delay_ms(&sc->sc_bus, 1); 792 ctl = OREAD4(sc, OHCI_CONTROL); 793 } 794 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 795 if ((ctl & OHCI_IR) == 0) { 796 aprint_error_dev(sc->sc_dev, 797 "SMM does not respond, resetting\n"); 798 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 799 goto reset; 800 } 801 #if 0 802 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 803 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 804 /* BIOS started controller. */ 805 DPRINTF(("ohci_init: BIOS active\n")); 806 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 807 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 808 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 809 } 810 #endif 811 } else { 812 DPRINTF(("ohci_init: cold started\n")); 813 reset: 814 /* Controller was cold started. */ 815 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 816 } 817 818 /* 819 * This reset should not be necessary according to the OHCI spec, but 820 * without it some controllers do not start. 821 */ 822 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 823 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 824 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 825 826 /* We now own the host controller and the bus has been reset. */ 827 828 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 829 /* Nominal time for a reset is 10 us. */ 830 for (i = 0; i < 10; i++) { 831 delay(10); 832 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 833 if (!hcr) 834 break; 835 } 836 if (hcr) { 837 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 838 err = USBD_IOERROR; 839 goto bad5; 840 } 841 #ifdef OHCI_DEBUG 842 if (ohcidebug > 15) 843 ohci_dumpregs(sc); 844 #endif 845 846 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 847 848 /* Set up HC registers. */ 849 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 850 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 851 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 852 /* disable all interrupts and then switch on all desired interrupts */ 853 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 854 /* switch on desired functional features */ 855 ctl = OREAD4(sc, OHCI_CONTROL); 856 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 857 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 858 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 859 /* And finally start it! */ 860 OWRITE4(sc, OHCI_CONTROL, ctl); 861 862 /* 863 * The controller is now OPERATIONAL. Set a some final 864 * registers that should be set earlier, but that the 865 * controller ignores when in the SUSPEND state. 866 */ 867 ival = OHCI_GET_IVAL(fm); 868 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 869 fm |= OHCI_FSMPS(ival) | ival; 870 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 871 per = OHCI_PERIODIC(ival); /* 90% periodic */ 872 OWRITE4(sc, OHCI_PERIODIC_START, per); 873 874 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 875 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 876 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 877 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 878 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 879 880 /* 881 * The AMD756 requires a delay before re-reading the register, 882 * otherwise it will occasionally report 0 ports. 883 */ 884 sc->sc_noport = 0; 885 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 886 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 887 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 888 } 889 890 #ifdef OHCI_DEBUG 891 if (ohcidebug > 5) 892 ohci_dumpregs(sc); 893 #endif 894 895 /* Set up the bus struct. */ 896 sc->sc_bus.methods = &ohci_bus_methods; 897 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 898 899 sc->sc_control = sc->sc_intre = 0; 900 901 /* Finally, turn on interrupts. */ 902 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 903 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 904 905 return (USBD_NORMAL_COMPLETION); 906 907 bad5: 908 for (i = 0; i < OHCI_NO_EDS; i++) 909 ohci_free_sed(sc, sc->sc_eds[i]); 910 bad4: 911 ohci_free_sed(sc, sc->sc_isoc_head); 912 bad3: 913 ohci_free_sed(sc, sc->sc_bulk_head); 914 bad2: 915 ohci_free_sed(sc, sc->sc_ctrl_head); 916 bad1: 917 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 918 sc->sc_hcca = NULL; 919 return (err); 920 } 921 922 usbd_status 923 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 924 { 925 struct ohci_softc *sc = bus->hci_private; 926 usbd_status status; 927 928 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 929 if (status == USBD_NOMEM) 930 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 931 return status; 932 } 933 934 void 935 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 936 { 937 struct ohci_softc *sc = bus->hci_private; 938 if (dma->block->flags & USB_DMA_RESERVE) { 939 usb_reserve_freem(&sc->sc_dma_reserve, dma); 940 return; 941 } 942 usb_freemem(&sc->sc_bus, dma); 943 } 944 945 usbd_xfer_handle 946 ohci_allocx(struct usbd_bus *bus) 947 { 948 struct ohci_softc *sc = bus->hci_private; 949 usbd_xfer_handle xfer; 950 951 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 952 if (xfer != NULL) { 953 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 954 #ifdef DIAGNOSTIC 955 if (xfer->busy_free != XFER_FREE) { 956 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 957 xfer->busy_free); 958 } 959 #endif 960 } else { 961 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 962 } 963 if (xfer != NULL) { 964 memset(xfer, 0, sizeof (struct ohci_xfer)); 965 #ifdef DIAGNOSTIC 966 xfer->busy_free = XFER_BUSY; 967 #endif 968 } 969 return (xfer); 970 } 971 972 void 973 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 974 { 975 struct ohci_softc *sc = bus->hci_private; 976 977 #ifdef DIAGNOSTIC 978 if (xfer->busy_free != XFER_BUSY) { 979 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 980 xfer->busy_free); 981 } 982 xfer->busy_free = XFER_FREE; 983 #endif 984 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 985 } 986 987 /* 988 * Shut down the controller when the system is going down. 989 */ 990 bool 991 ohci_shutdown(device_t self, int flags) 992 { 993 ohci_softc_t *sc = device_private(self); 994 995 DPRINTF(("ohci_shutdown: stopping the HC\n")); 996 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 997 return true; 998 } 999 1000 bool 1001 ohci_resume(device_t dv, const pmf_qual_t *qual) 1002 { 1003 ohci_softc_t *sc = device_private(dv); 1004 uint32_t ctl; 1005 int s; 1006 1007 s = splhardusb(); 1008 sc->sc_bus.use_polling++; 1009 /* Some broken BIOSes do not recover these values */ 1010 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1011 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1012 sc->sc_ctrl_head->physaddr); 1013 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1014 sc->sc_bulk_head->physaddr); 1015 if (sc->sc_intre) 1016 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1017 (OHCI_ALL_INTRS | OHCI_MIE)); 1018 if (sc->sc_control) 1019 ctl = sc->sc_control; 1020 else 1021 ctl = OREAD4(sc, OHCI_CONTROL); 1022 ctl |= OHCI_HCFS_RESUME; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1025 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1026 OWRITE4(sc, OHCI_CONTROL, ctl); 1027 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1028 sc->sc_control = sc->sc_intre = 0; 1029 sc->sc_bus.use_polling--; 1030 splx(s); 1031 1032 return true; 1033 } 1034 1035 bool 1036 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1037 { 1038 ohci_softc_t *sc = device_private(dv); 1039 uint32_t ctl; 1040 int s; 1041 1042 s = splhardusb(); 1043 sc->sc_bus.use_polling++; 1044 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1045 if (sc->sc_control == 0) { 1046 /* 1047 * Preserve register values, in case that BIOS 1048 * does not recover them. 1049 */ 1050 sc->sc_control = ctl; 1051 sc->sc_intre = OREAD4(sc, 1052 OHCI_INTERRUPT_ENABLE); 1053 } 1054 ctl |= OHCI_HCFS_SUSPEND; 1055 OWRITE4(sc, OHCI_CONTROL, ctl); 1056 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1057 sc->sc_bus.use_polling--; 1058 splx(s); 1059 1060 return true; 1061 } 1062 1063 #ifdef OHCI_DEBUG 1064 void 1065 ohci_dumpregs(ohci_softc_t *sc) 1066 { 1067 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1068 OREAD4(sc, OHCI_REVISION), 1069 OREAD4(sc, OHCI_CONTROL), 1070 OREAD4(sc, OHCI_COMMAND_STATUS))); 1071 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1072 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1073 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1074 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1075 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1076 OREAD4(sc, OHCI_HCCA), 1077 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1078 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1079 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1080 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1081 OREAD4(sc, OHCI_BULK_HEAD_ED), 1082 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1083 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1084 OREAD4(sc, OHCI_DONE_HEAD), 1085 OREAD4(sc, OHCI_FM_INTERVAL), 1086 OREAD4(sc, OHCI_FM_REMAINING))); 1087 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1088 OREAD4(sc, OHCI_FM_NUMBER), 1089 OREAD4(sc, OHCI_PERIODIC_START), 1090 OREAD4(sc, OHCI_LS_THRESHOLD))); 1091 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1092 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1093 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1094 OREAD4(sc, OHCI_RH_STATUS))); 1095 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1096 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1097 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1098 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1099 O32TOH(sc->sc_hcca->hcca_frame_number), 1100 O32TOH(sc->sc_hcca->hcca_done_head))); 1101 } 1102 #endif 1103 1104 Static int ohci_intr1(ohci_softc_t *); 1105 1106 int 1107 ohci_intr(void *p) 1108 { 1109 ohci_softc_t *sc = p; 1110 1111 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 1112 return (0); 1113 1114 /* If we get an interrupt while polling, then just ignore it. */ 1115 if (sc->sc_bus.use_polling) { 1116 #ifdef DIAGNOSTIC 1117 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1118 #endif 1119 /* for level triggered intrs, should do something to ack */ 1120 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1121 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1122 1123 return (0); 1124 } 1125 1126 return (ohci_intr1(sc)); 1127 } 1128 1129 Static int 1130 ohci_intr1(ohci_softc_t *sc) 1131 { 1132 u_int32_t intrs, eintrs; 1133 1134 DPRINTFN(14,("ohci_intr1: enter\n")); 1135 1136 /* In case the interrupt occurs before initialization has completed. */ 1137 if (sc == NULL || sc->sc_hcca == NULL) { 1138 #ifdef DIAGNOSTIC 1139 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1140 #endif 1141 return (0); 1142 } 1143 1144 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1145 if (!intrs) 1146 return (0); 1147 1148 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1149 eintrs = intrs & sc->sc_eintrs; 1150 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1151 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1152 (u_int)eintrs, sc->sc_eintrs)); 1153 1154 if (!eintrs) { 1155 return (0); 1156 } 1157 1158 sc->sc_bus.intr_context++; 1159 sc->sc_bus.no_intrs++; 1160 if (eintrs & OHCI_SO) { 1161 sc->sc_overrun_cnt++; 1162 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1163 printf("%s: %u scheduling overruns\n", 1164 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1165 sc->sc_overrun_cnt = 0; 1166 } 1167 /* XXX do what */ 1168 eintrs &= ~OHCI_SO; 1169 } 1170 if (eintrs & OHCI_WDH) { 1171 /* 1172 * We block the interrupt below, and reenable it later from 1173 * ohci_softintr(). 1174 */ 1175 usb_schedsoftintr(&sc->sc_bus); 1176 } 1177 if (eintrs & OHCI_RD) { 1178 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1179 /* XXX process resume detect */ 1180 } 1181 if (eintrs & OHCI_UE) { 1182 printf("%s: unrecoverable error, controller halted\n", 1183 device_xname(sc->sc_dev)); 1184 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1185 /* XXX what else */ 1186 } 1187 if (eintrs & OHCI_RHSC) { 1188 /* 1189 * We block the interrupt below, and reenable it later from 1190 * a timeout. 1191 */ 1192 ohci_rhsc(sc, sc->sc_intrxfer); 1193 /* Do not allow RHSC interrupts > 1 per second */ 1194 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1195 } 1196 1197 sc->sc_bus.intr_context--; 1198 1199 if (eintrs != 0) { 1200 /* Block unprocessed interrupts. */ 1201 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1202 sc->sc_eintrs &= ~eintrs; 1203 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1204 device_xname(sc->sc_dev), eintrs)); 1205 } 1206 1207 return (1); 1208 } 1209 1210 void 1211 ohci_rhsc_enable(void *v_sc) 1212 { 1213 ohci_softc_t *sc = v_sc; 1214 int s; 1215 1216 s = splhardusb(); 1217 sc->sc_eintrs |= OHCI_RHSC; 1218 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1219 splx(s); 1220 } 1221 1222 #ifdef OHCI_DEBUG 1223 const char *ohci_cc_strs[] = { 1224 "NO_ERROR", 1225 "CRC", 1226 "BIT_STUFFING", 1227 "DATA_TOGGLE_MISMATCH", 1228 "STALL", 1229 "DEVICE_NOT_RESPONDING", 1230 "PID_CHECK_FAILURE", 1231 "UNEXPECTED_PID", 1232 "DATA_OVERRUN", 1233 "DATA_UNDERRUN", 1234 "BUFFER_OVERRUN", 1235 "BUFFER_UNDERRUN", 1236 "reserved", 1237 "reserved", 1238 "NOT_ACCESSED", 1239 "NOT_ACCESSED", 1240 }; 1241 #endif 1242 1243 void 1244 ohci_softintr(void *v) 1245 { 1246 struct usbd_bus *bus = v; 1247 ohci_softc_t *sc = bus->hci_private; 1248 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1249 ohci_soft_td_t *std, *sdone, *stdnext; 1250 usbd_xfer_handle xfer; 1251 struct ohci_pipe *opipe; 1252 int len, cc, s; 1253 int i, j, actlen, iframes, uedir; 1254 ohci_physaddr_t done; 1255 1256 DPRINTFN(10,("ohci_softintr: enter\n")); 1257 1258 sc->sc_bus.intr_context++; 1259 1260 s = splhardusb(); 1261 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1262 sizeof(sc->sc_hcca->hcca_done_head), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1265 sc->sc_hcca->hcca_done_head = 0; 1266 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1267 sizeof(sc->sc_hcca->hcca_done_head), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1270 sc->sc_eintrs |= OHCI_WDH; 1271 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1272 splx(s); 1273 1274 /* Reverse the done list. */ 1275 for (sdone = NULL, sidone = NULL; done != 0; ) { 1276 std = ohci_hash_find_td(sc, done); 1277 if (std != NULL) { 1278 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1279 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1280 std->dnext = sdone; 1281 done = O32TOH(std->td.td_nexttd); 1282 sdone = std; 1283 DPRINTFN(10,("add TD %p\n", std)); 1284 continue; 1285 } 1286 sitd = ohci_hash_find_itd(sc, done); 1287 if (sitd != NULL) { 1288 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1289 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1290 sitd->dnext = sidone; 1291 done = O32TOH(sitd->itd.itd_nextitd); 1292 sidone = sitd; 1293 DPRINTFN(5,("add ITD %p\n", sitd)); 1294 continue; 1295 } 1296 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1297 } 1298 1299 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1300 1301 #ifdef OHCI_DEBUG 1302 if (ohcidebug > 10) { 1303 DPRINTF(("ohci_process_done: TD done:\n")); 1304 ohci_dump_tds(sc, sdone); 1305 } 1306 #endif 1307 1308 for (std = sdone; std; std = stdnext) { 1309 xfer = std->xfer; 1310 stdnext = std->dnext; 1311 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1312 std, xfer, xfer ? xfer->hcpriv : 0)); 1313 if (xfer == NULL) { 1314 /* 1315 * xfer == NULL: There seems to be no xfer associated 1316 * with this TD. It is tailp that happened to end up on 1317 * the done queue. 1318 * Shouldn't happen, but some chips are broken(?). 1319 */ 1320 continue; 1321 } 1322 if (xfer->status == USBD_CANCELLED || 1323 xfer->status == USBD_TIMEOUT) { 1324 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1325 xfer)); 1326 /* Handled by abort routine. */ 1327 continue; 1328 } 1329 callout_stop(&xfer->timeout_handle); 1330 1331 len = std->len; 1332 if (std->td.td_cbp != 0) 1333 len -= O32TOH(std->td.td_be) - 1334 O32TOH(std->td.td_cbp) + 1; 1335 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1336 std->flags)); 1337 if (std->flags & OHCI_ADD_LEN) 1338 xfer->actlen += len; 1339 1340 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1341 if (cc == OHCI_CC_NO_ERROR) { 1342 if (std->flags & OHCI_CALL_DONE) { 1343 xfer->status = USBD_NORMAL_COMPLETION; 1344 s = splusb(); 1345 usb_transfer_complete(xfer); 1346 splx(s); 1347 } 1348 ohci_free_std(sc, std); 1349 } else { 1350 /* 1351 * Endpoint is halted. First unlink all the TDs 1352 * belonging to the failed transfer, and then restart 1353 * the endpoint. 1354 */ 1355 ohci_soft_td_t *p, *n; 1356 opipe = (struct ohci_pipe *)xfer->pipe; 1357 1358 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1359 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1360 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1361 1362 /* remove TDs */ 1363 for (p = std; p->xfer == xfer; p = n) { 1364 n = p->nexttd; 1365 ohci_free_std(sc, p); 1366 } 1367 1368 /* clear halt */ 1369 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1370 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1371 1372 if (cc == OHCI_CC_STALL) 1373 xfer->status = USBD_STALLED; 1374 else 1375 xfer->status = USBD_IOERROR; 1376 s = splusb(); 1377 usb_transfer_complete(xfer); 1378 splx(s); 1379 } 1380 } 1381 1382 #ifdef OHCI_DEBUG 1383 if (ohcidebug > 10) { 1384 DPRINTF(("ohci_softintr: ITD done:\n")); 1385 ohci_dump_itds(sc, sidone); 1386 } 1387 #endif 1388 1389 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1390 xfer = sitd->xfer; 1391 sitdnext = sitd->dnext; 1392 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1393 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1394 if (xfer == NULL) 1395 continue; 1396 if (xfer->status == USBD_CANCELLED || 1397 xfer->status == USBD_TIMEOUT) { 1398 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1399 xfer)); 1400 /* Handled by abort routine. */ 1401 continue; 1402 } 1403 #ifdef DIAGNOSTIC 1404 if (sitd->isdone) 1405 printf("ohci_softintr: sitd=%p is done\n", sitd); 1406 sitd->isdone = 1; 1407 #endif 1408 if (sitd->flags & OHCI_CALL_DONE) { 1409 ohci_soft_itd_t *next; 1410 1411 opipe = (struct ohci_pipe *)xfer->pipe; 1412 opipe->u.iso.inuse -= xfer->nframes; 1413 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1414 bEndpointAddress); 1415 xfer->status = USBD_NORMAL_COMPLETION; 1416 actlen = 0; 1417 for (i = 0, sitd = xfer->hcpriv;; 1418 sitd = next) { 1419 next = sitd->nextitd; 1420 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1421 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1422 xfer->status = USBD_IOERROR; 1423 /* For input, update frlengths with actual */ 1424 /* XXX anything necessary for output? */ 1425 if (uedir == UE_DIR_IN && 1426 xfer->status == USBD_NORMAL_COMPLETION) { 1427 iframes = OHCI_ITD_GET_FC(O32TOH( 1428 sitd->itd.itd_flags)); 1429 for (j = 0; j < iframes; i++, j++) { 1430 len = O16TOH(sitd-> 1431 itd.itd_offset[j]); 1432 if ((OHCI_ITD_PSW_GET_CC(len) & 1433 OHCI_CC_NOT_ACCESSED_MASK) 1434 == OHCI_CC_NOT_ACCESSED) 1435 len = 0; 1436 else 1437 len = OHCI_ITD_PSW_LENGTH(len); 1438 xfer->frlengths[i] = len; 1439 actlen += len; 1440 } 1441 } 1442 if (sitd->flags & OHCI_CALL_DONE) 1443 break; 1444 ohci_free_sitd(sc, sitd); 1445 } 1446 ohci_free_sitd(sc, sitd); 1447 if (uedir == UE_DIR_IN && 1448 xfer->status == USBD_NORMAL_COMPLETION) 1449 xfer->actlen = actlen; 1450 xfer->hcpriv = NULL; 1451 1452 s = splusb(); 1453 usb_transfer_complete(xfer); 1454 splx(s); 1455 } 1456 } 1457 1458 #ifdef USB_USE_SOFTINTR 1459 if (sc->sc_softwake) { 1460 sc->sc_softwake = 0; 1461 wakeup(&sc->sc_softwake); 1462 } 1463 #endif /* USB_USE_SOFTINTR */ 1464 1465 sc->sc_bus.intr_context--; 1466 DPRINTFN(10,("ohci_softintr: done:\n")); 1467 } 1468 1469 void 1470 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1471 { 1472 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1473 int len = UGETW(xfer->request.wLength); 1474 int isread = (xfer->request.bmRequestType & UT_READ); 1475 1476 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1477 1478 #ifdef DIAGNOSTIC 1479 if (!(xfer->rqflags & URQ_REQUEST)) { 1480 panic("ohci_device_ctrl_done: not a request"); 1481 } 1482 #endif 1483 if (len) 1484 usb_syncmem(&xfer->dmabuf, 0, len, 1485 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1486 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1487 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1488 } 1489 1490 void 1491 ohci_device_intr_done(usbd_xfer_handle xfer) 1492 { 1493 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1494 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1495 ohci_soft_ed_t *sed = opipe->sed; 1496 ohci_soft_td_t *data, *tail; 1497 int isread = 1498 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1499 1500 1501 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1502 xfer, xfer->actlen)); 1503 1504 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1505 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1506 if (xfer->pipe->repeat) { 1507 data = opipe->tail.td; 1508 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1509 if (tail == NULL) { 1510 xfer->status = USBD_NOMEM; 1511 return; 1512 } 1513 tail->xfer = NULL; 1514 1515 data->td.td_flags = HTOO32( 1516 OHCI_TD_IN | OHCI_TD_NOCC | 1517 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1518 if (xfer->flags & USBD_SHORT_XFER_OK) 1519 data->td.td_flags |= HTOO32(OHCI_TD_R); 1520 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1521 data->nexttd = tail; 1522 data->td.td_nexttd = HTOO32(tail->physaddr); 1523 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1524 xfer->length - 1); 1525 data->len = xfer->length; 1526 data->xfer = xfer; 1527 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1528 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1530 xfer->hcpriv = data; 1531 xfer->actlen = 0; 1532 1533 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1534 usb_syncmem(&sed->dma, 1535 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1536 sizeof(sed->ed.ed_tailp), 1537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1538 opipe->tail.td = tail; 1539 } 1540 } 1541 1542 void 1543 ohci_device_bulk_done(usbd_xfer_handle xfer) 1544 { 1545 int isread = 1546 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1547 1548 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1549 xfer, xfer->actlen)); 1550 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1551 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1552 } 1553 1554 void 1555 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1556 { 1557 usbd_pipe_handle pipe; 1558 u_char *p; 1559 int i, m; 1560 int hstatus; 1561 1562 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1563 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1564 sc, xfer, hstatus)); 1565 1566 if (xfer == NULL) { 1567 /* Just ignore the change. */ 1568 return; 1569 } 1570 1571 pipe = xfer->pipe; 1572 1573 p = KERNADDR(&xfer->dmabuf, 0); 1574 m = min(sc->sc_noport, xfer->length * 8 - 1); 1575 memset(p, 0, xfer->length); 1576 for (i = 1; i <= m; i++) { 1577 /* Pick out CHANGE bits from the status reg. */ 1578 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1579 p[i/8] |= 1 << (i%8); 1580 } 1581 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1582 xfer->actlen = xfer->length; 1583 xfer->status = USBD_NORMAL_COMPLETION; 1584 1585 usb_transfer_complete(xfer); 1586 } 1587 1588 void 1589 ohci_root_intr_done(usbd_xfer_handle xfer) 1590 { 1591 } 1592 1593 void 1594 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1595 { 1596 } 1597 1598 /* 1599 * Wait here until controller claims to have an interrupt. 1600 * Then call ohci_intr and return. Use timeout to avoid waiting 1601 * too long. 1602 */ 1603 void 1604 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1605 { 1606 int timo; 1607 u_int32_t intrs; 1608 1609 xfer->status = USBD_IN_PROGRESS; 1610 for (timo = xfer->timeout; timo >= 0; timo--) { 1611 usb_delay_ms(&sc->sc_bus, 1); 1612 if (sc->sc_dying) 1613 break; 1614 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1615 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1616 #ifdef OHCI_DEBUG 1617 if (ohcidebug > 15) 1618 ohci_dumpregs(sc); 1619 #endif 1620 if (intrs) { 1621 ohci_intr1(sc); 1622 if (xfer->status != USBD_IN_PROGRESS) 1623 return; 1624 } 1625 } 1626 1627 /* Timeout */ 1628 DPRINTF(("ohci_waitintr: timeout\n")); 1629 xfer->status = USBD_TIMEOUT; 1630 usb_transfer_complete(xfer); 1631 /* XXX should free TD */ 1632 } 1633 1634 void 1635 ohci_poll(struct usbd_bus *bus) 1636 { 1637 ohci_softc_t *sc = bus->hci_private; 1638 #ifdef OHCI_DEBUG 1639 static int last; 1640 int new; 1641 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1642 if (new != last) { 1643 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1644 last = new; 1645 } 1646 #endif 1647 1648 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1649 ohci_intr1(sc); 1650 } 1651 1652 usbd_status 1653 ohci_device_request(usbd_xfer_handle xfer) 1654 { 1655 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1656 usb_device_request_t *req = &xfer->request; 1657 usbd_device_handle dev = opipe->pipe.device; 1658 ohci_softc_t *sc = dev->bus->hci_private; 1659 int addr = dev->address; 1660 ohci_soft_td_t *setup, *stat, *next, *tail; 1661 ohci_soft_ed_t *sed; 1662 int isread; 1663 int len; 1664 usbd_status err; 1665 int s; 1666 1667 isread = req->bmRequestType & UT_READ; 1668 len = UGETW(req->wLength); 1669 1670 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1671 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1672 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1673 UGETW(req->wIndex), len, addr, 1674 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1675 1676 setup = opipe->tail.td; 1677 stat = ohci_alloc_std(sc); 1678 if (stat == NULL) { 1679 err = USBD_NOMEM; 1680 goto bad1; 1681 } 1682 tail = ohci_alloc_std(sc); 1683 if (tail == NULL) { 1684 err = USBD_NOMEM; 1685 goto bad2; 1686 } 1687 tail->xfer = NULL; 1688 1689 sed = opipe->sed; 1690 opipe->u.ctl.length = len; 1691 1692 /* Update device address and length since they may have changed 1693 during the setup of the control pipe in usbd_new_device(). */ 1694 /* XXX This only needs to be done once, but it's too early in open. */ 1695 /* XXXX Should not touch ED here! */ 1696 1697 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1698 sizeof(sed->ed.ed_flags), 1699 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1700 sed->ed.ed_flags = HTOO32( 1701 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1702 OHCI_ED_SET_FA(addr) | 1703 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1704 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1705 sizeof(sed->ed.ed_flags), 1706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1707 1708 next = stat; 1709 1710 /* Set up data transaction */ 1711 if (len != 0) { 1712 ohci_soft_td_t *std = stat; 1713 1714 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1715 std, &stat); 1716 stat = stat->nexttd; /* point at free TD */ 1717 if (err) 1718 goto bad3; 1719 /* Start toggle at 1 and then use the carried toggle. */ 1720 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1721 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1722 usb_syncmem(&std->dma, 1723 std->offs + offsetof(ohci_td_t, td_flags), 1724 sizeof(std->td.td_flags), 1725 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1726 } 1727 1728 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1729 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1730 1731 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1732 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1733 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1734 setup->nexttd = next; 1735 setup->td.td_nexttd = HTOO32(next->physaddr); 1736 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1737 setup->len = 0; 1738 setup->xfer = xfer; 1739 setup->flags = 0; 1740 xfer->hcpriv = setup; 1741 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1742 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1743 1744 stat->td.td_flags = HTOO32( 1745 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1746 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1747 stat->td.td_cbp = 0; 1748 stat->nexttd = tail; 1749 stat->td.td_nexttd = HTOO32(tail->physaddr); 1750 stat->td.td_be = 0; 1751 stat->flags = OHCI_CALL_DONE; 1752 stat->len = 0; 1753 stat->xfer = xfer; 1754 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1755 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1756 1757 #ifdef OHCI_DEBUG 1758 if (ohcidebug > 5) { 1759 DPRINTF(("ohci_device_request:\n")); 1760 ohci_dump_ed(sc, sed); 1761 ohci_dump_tds(sc, setup); 1762 } 1763 #endif 1764 1765 /* Insert ED in schedule */ 1766 s = splusb(); 1767 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1768 usb_syncmem(&sed->dma, 1769 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1770 sizeof(sed->ed.ed_tailp), 1771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1772 opipe->tail.td = tail; 1773 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1774 if (xfer->timeout && !sc->sc_bus.use_polling) { 1775 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1776 ohci_timeout, xfer); 1777 } 1778 splx(s); 1779 1780 #ifdef OHCI_DEBUG 1781 if (ohcidebug > 20) { 1782 delay(10000); 1783 DPRINTF(("ohci_device_request: status=%x\n", 1784 OREAD4(sc, OHCI_COMMAND_STATUS))); 1785 ohci_dumpregs(sc); 1786 printf("ctrl head:\n"); 1787 ohci_dump_ed(sc, sc->sc_ctrl_head); 1788 printf("sed:\n"); 1789 ohci_dump_ed(sc, sed); 1790 ohci_dump_tds(sc, setup); 1791 } 1792 #endif 1793 1794 return (USBD_NORMAL_COMPLETION); 1795 1796 bad3: 1797 ohci_free_std(sc, tail); 1798 bad2: 1799 ohci_free_std(sc, stat); 1800 bad1: 1801 return (err); 1802 } 1803 1804 /* 1805 * Add an ED to the schedule. Called at splusb(). 1806 */ 1807 void 1808 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1809 { 1810 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1811 1812 SPLUSBCHECK; 1813 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1814 sizeof(head->ed.ed_nexted), 1815 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1816 sed->next = head->next; 1817 sed->ed.ed_nexted = head->ed.ed_nexted; 1818 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1819 sizeof(sed->ed.ed_nexted), 1820 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1821 head->next = sed; 1822 head->ed.ed_nexted = HTOO32(sed->physaddr); 1823 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1824 sizeof(head->ed.ed_nexted), 1825 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1826 } 1827 1828 /* 1829 * Remove an ED from the schedule. Called at splusb(). 1830 */ 1831 void 1832 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1833 { 1834 ohci_soft_ed_t *p; 1835 1836 SPLUSBCHECK; 1837 1838 /* XXX */ 1839 for (p = head; p != NULL && p->next != sed; p = p->next) 1840 ; 1841 if (p == NULL) 1842 panic("ohci_rem_ed: ED not found"); 1843 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1844 sizeof(sed->ed.ed_nexted), 1845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1846 p->next = sed->next; 1847 p->ed.ed_nexted = sed->ed.ed_nexted; 1848 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1849 sizeof(p->ed.ed_nexted), 1850 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1851 } 1852 1853 /* 1854 * When a transfer is completed the TD is added to the done queue by 1855 * the host controller. This queue is the processed by software. 1856 * Unfortunately the queue contains the physical address of the TD 1857 * and we have no simple way to translate this back to a kernel address. 1858 * To make the translation possible (and fast) we use a hash table of 1859 * TDs currently in the schedule. The physical address is used as the 1860 * hash value. 1861 */ 1862 1863 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1864 /* Called at splusb() */ 1865 void 1866 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1867 { 1868 int h = HASH(std->physaddr); 1869 1870 SPLUSBCHECK; 1871 1872 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1873 } 1874 1875 /* Called at splusb() */ 1876 void 1877 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1878 { 1879 SPLUSBCHECK; 1880 1881 LIST_REMOVE(std, hnext); 1882 } 1883 1884 ohci_soft_td_t * 1885 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1886 { 1887 int h = HASH(a); 1888 ohci_soft_td_t *std; 1889 1890 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1891 std != NULL; 1892 std = LIST_NEXT(std, hnext)) 1893 if (std->physaddr == a) 1894 return (std); 1895 return (NULL); 1896 } 1897 1898 /* Called at splusb() */ 1899 void 1900 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1901 { 1902 int h = HASH(sitd->physaddr); 1903 1904 SPLUSBCHECK; 1905 1906 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1907 sitd, (u_long)sitd->physaddr)); 1908 1909 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1910 } 1911 1912 /* Called at splusb() */ 1913 void 1914 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1915 { 1916 SPLUSBCHECK; 1917 1918 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1919 sitd, (u_long)sitd->physaddr)); 1920 1921 LIST_REMOVE(sitd, hnext); 1922 } 1923 1924 ohci_soft_itd_t * 1925 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1926 { 1927 int h = HASH(a); 1928 ohci_soft_itd_t *sitd; 1929 1930 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1931 sitd != NULL; 1932 sitd = LIST_NEXT(sitd, hnext)) 1933 if (sitd->physaddr == a) 1934 return (sitd); 1935 return (NULL); 1936 } 1937 1938 void 1939 ohci_timeout(void *addr) 1940 { 1941 struct ohci_xfer *oxfer = addr; 1942 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1943 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1944 1945 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1946 1947 if (sc->sc_dying) { 1948 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1949 return; 1950 } 1951 1952 /* Execute the abort in a process context. */ 1953 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1954 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1955 USB_TASKQ_HC); 1956 } 1957 1958 void 1959 ohci_timeout_task(void *addr) 1960 { 1961 usbd_xfer_handle xfer = addr; 1962 int s; 1963 1964 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1965 1966 s = splusb(); 1967 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1968 splx(s); 1969 } 1970 1971 #ifdef OHCI_DEBUG 1972 void 1973 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1974 { 1975 for (; std; std = std->nexttd) 1976 ohci_dump_td(sc, std); 1977 } 1978 1979 void 1980 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1981 { 1982 char sbuf[128]; 1983 1984 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1985 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1986 snprintb(sbuf, sizeof(sbuf), 1987 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1988 (u_int32_t)O32TOH(std->td.td_flags)); 1989 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1990 "nexttd=0x%08lx be=0x%08lx\n", 1991 std, (u_long)std->physaddr, sbuf, 1992 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 1993 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 1994 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1995 (u_long)O32TOH(std->td.td_cbp), 1996 (u_long)O32TOH(std->td.td_nexttd), 1997 (u_long)O32TOH(std->td.td_be)); 1998 } 1999 2000 void 2001 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2002 { 2003 int i; 2004 2005 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2006 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2007 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2008 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2009 sitd, (u_long)sitd->physaddr, 2010 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2011 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2012 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2013 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2014 (u_long)O32TOH(sitd->itd.itd_bp0), 2015 (u_long)O32TOH(sitd->itd.itd_nextitd), 2016 (u_long)O32TOH(sitd->itd.itd_be)); 2017 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2018 printf("offs[%d]=0x%04x ", i, 2019 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2020 printf("\n"); 2021 } 2022 2023 void 2024 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2025 { 2026 for (; sitd; sitd = sitd->nextitd) 2027 ohci_dump_itd(sc, sitd); 2028 } 2029 2030 void 2031 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2032 { 2033 char sbuf[128], sbuf2[128]; 2034 2035 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2037 snprintb(sbuf, sizeof(sbuf), 2038 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2039 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2040 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2041 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2042 2043 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2044 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2045 sed, (u_long)sed->physaddr, 2046 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2047 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2048 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2049 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2050 (u_long)O32TOH(sed->ed.ed_headp), 2051 (u_long)O32TOH(sed->ed.ed_nexted)); 2052 } 2053 #endif 2054 2055 usbd_status 2056 ohci_open(usbd_pipe_handle pipe) 2057 { 2058 usbd_device_handle dev = pipe->device; 2059 ohci_softc_t *sc = dev->bus->hci_private; 2060 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2061 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2062 u_int8_t addr = dev->address; 2063 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2064 ohci_soft_ed_t *sed; 2065 ohci_soft_td_t *std; 2066 ohci_soft_itd_t *sitd; 2067 ohci_physaddr_t tdphys; 2068 u_int32_t fmt; 2069 usbd_status err; 2070 int s; 2071 int ival; 2072 2073 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2074 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2075 2076 if (sc->sc_dying) 2077 return (USBD_IOERROR); 2078 2079 std = NULL; 2080 sed = NULL; 2081 2082 if (addr == sc->sc_addr) { 2083 switch (ed->bEndpointAddress) { 2084 case USB_CONTROL_ENDPOINT: 2085 pipe->methods = &ohci_root_ctrl_methods; 2086 break; 2087 case UE_DIR_IN | OHCI_INTR_ENDPT: 2088 pipe->methods = &ohci_root_intr_methods; 2089 break; 2090 default: 2091 return (USBD_INVAL); 2092 } 2093 } else { 2094 sed = ohci_alloc_sed(sc); 2095 if (sed == NULL) 2096 goto bad0; 2097 opipe->sed = sed; 2098 if (xfertype == UE_ISOCHRONOUS) { 2099 sitd = ohci_alloc_sitd(sc); 2100 if (sitd == NULL) 2101 goto bad1; 2102 opipe->tail.itd = sitd; 2103 tdphys = sitd->physaddr; 2104 fmt = OHCI_ED_FORMAT_ISO; 2105 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2106 fmt |= OHCI_ED_DIR_IN; 2107 else 2108 fmt |= OHCI_ED_DIR_OUT; 2109 } else { 2110 std = ohci_alloc_std(sc); 2111 if (std == NULL) 2112 goto bad1; 2113 opipe->tail.td = std; 2114 tdphys = std->physaddr; 2115 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2116 } 2117 sed->ed.ed_flags = HTOO32( 2118 OHCI_ED_SET_FA(addr) | 2119 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2120 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2121 fmt | 2122 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2123 sed->ed.ed_headp = HTOO32(tdphys | 2124 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2125 sed->ed.ed_tailp = HTOO32(tdphys); 2126 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2127 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2128 2129 switch (xfertype) { 2130 case UE_CONTROL: 2131 pipe->methods = &ohci_device_ctrl_methods; 2132 err = usb_allocmem(&sc->sc_bus, 2133 sizeof(usb_device_request_t), 2134 0, &opipe->u.ctl.reqdma); 2135 if (err) 2136 goto bad; 2137 s = splusb(); 2138 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2139 splx(s); 2140 break; 2141 case UE_INTERRUPT: 2142 pipe->methods = &ohci_device_intr_methods; 2143 ival = pipe->interval; 2144 if (ival == USBD_DEFAULT_INTERVAL) 2145 ival = ed->bInterval; 2146 return (ohci_device_setintr(sc, opipe, ival)); 2147 case UE_ISOCHRONOUS: 2148 pipe->methods = &ohci_device_isoc_methods; 2149 return (ohci_setup_isoc(pipe)); 2150 case UE_BULK: 2151 pipe->methods = &ohci_device_bulk_methods; 2152 s = splusb(); 2153 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2154 splx(s); 2155 break; 2156 } 2157 } 2158 return (USBD_NORMAL_COMPLETION); 2159 2160 bad: 2161 if (std != NULL) 2162 ohci_free_std(sc, std); 2163 bad1: 2164 if (sed != NULL) 2165 ohci_free_sed(sc, sed); 2166 bad0: 2167 return (USBD_NOMEM); 2168 2169 } 2170 2171 /* 2172 * Close a reqular pipe. 2173 * Assumes that there are no pending transactions. 2174 */ 2175 void 2176 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2177 { 2178 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2179 ohci_softc_t *sc = pipe->device->bus->hci_private; 2180 ohci_soft_ed_t *sed = opipe->sed; 2181 int s; 2182 2183 s = splusb(); 2184 #ifdef DIAGNOSTIC 2185 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2186 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2187 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2188 ohci_soft_td_t *std; 2189 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2190 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2191 "tl=0x%x pipe=%p, std=%p\n", sed, 2192 (int)O32TOH(sed->ed.ed_headp), 2193 (int)O32TOH(sed->ed.ed_tailp), 2194 pipe, std); 2195 #ifdef USB_DEBUG 2196 usbd_dump_pipe(&opipe->pipe); 2197 #endif 2198 #ifdef OHCI_DEBUG 2199 ohci_dump_ed(sc, sed); 2200 if (std) 2201 ohci_dump_td(sc, std); 2202 #endif 2203 usb_delay_ms(&sc->sc_bus, 2); 2204 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2205 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2206 printf("ohci_close_pipe: pipe still not empty\n"); 2207 } 2208 #endif 2209 ohci_rem_ed(sed, head); 2210 /* Make sure the host controller is not touching this ED */ 2211 usb_delay_ms(&sc->sc_bus, 1); 2212 pipe->endpoint->datatoggle = 2213 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2214 splx(s); 2215 ohci_free_sed(sc, opipe->sed); 2216 } 2217 2218 /* 2219 * Abort a device request. 2220 * If this routine is called at splusb() it guarantees that the request 2221 * will be removed from the hardware scheduling and that the callback 2222 * for it will be called with USBD_CANCELLED status. 2223 * It's impossible to guarantee that the requested transfer will not 2224 * have happened since the hardware runs concurrently. 2225 * If the transaction has already happened we rely on the ordinary 2226 * interrupt processing to process it. 2227 */ 2228 void 2229 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2230 { 2231 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2232 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2233 ohci_soft_ed_t *sed = opipe->sed; 2234 ohci_soft_td_t *p, *n; 2235 ohci_physaddr_t headp; 2236 int s, hit; 2237 int wake; 2238 2239 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2240 2241 if (sc->sc_dying) { 2242 /* If we're dying, just do the software part. */ 2243 s = splusb(); 2244 xfer->status = status; /* make software ignore it */ 2245 callout_stop(&xfer->timeout_handle); 2246 usb_transfer_complete(xfer); 2247 splx(s); 2248 return; 2249 } 2250 2251 if (xfer->device->bus->intr_context || !curproc) 2252 panic("ohci_abort_xfer: not in process context"); 2253 2254 /* 2255 * If an abort is already in progress then just wait for it to 2256 * complete and return. 2257 */ 2258 if (xfer->hcflags & UXFER_ABORTING) { 2259 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2260 #ifdef DIAGNOSTIC 2261 if (status == USBD_TIMEOUT) 2262 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2263 #endif 2264 /* Override the status which might be USBD_TIMEOUT. */ 2265 xfer->status = status; 2266 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2267 xfer->hcflags |= UXFER_ABORTWAIT; 2268 while (xfer->hcflags & UXFER_ABORTING) 2269 tsleep(&xfer->hcflags, PZERO, "ohciaw", 0); 2270 return; 2271 } 2272 xfer->hcflags |= UXFER_ABORTING; 2273 2274 /* 2275 * Step 1: Make interrupt routine and hardware ignore xfer. 2276 */ 2277 s = splusb(); 2278 xfer->status = status; /* make software ignore it */ 2279 callout_stop(&xfer->timeout_handle); 2280 splx(s); 2281 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2282 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2283 sizeof(sed->ed.ed_flags), 2284 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2285 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2286 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2287 sizeof(sed->ed.ed_flags), 2288 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2289 2290 /* 2291 * Step 2: Wait until we know hardware has finished any possible 2292 * use of the xfer. Also make sure the soft interrupt routine 2293 * has run. 2294 */ 2295 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2296 s = splusb(); 2297 #ifdef USB_USE_SOFTINTR 2298 sc->sc_softwake = 1; 2299 #endif /* USB_USE_SOFTINTR */ 2300 usb_schedsoftintr(&sc->sc_bus); 2301 #ifdef USB_USE_SOFTINTR 2302 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2303 #endif /* USB_USE_SOFTINTR */ 2304 splx(s); 2305 2306 /* 2307 * Step 3: Remove any vestiges of the xfer from the hardware. 2308 * The complication here is that the hardware may have executed 2309 * beyond the xfer we're trying to abort. So as we're scanning 2310 * the TDs of this xfer we check if the hardware points to 2311 * any of them. 2312 */ 2313 s = splusb(); /* XXX why? */ 2314 p = xfer->hcpriv; 2315 #ifdef DIAGNOSTIC 2316 if (p == NULL) { 2317 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2318 splx(s); 2319 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2320 return; 2321 } 2322 #endif 2323 #ifdef OHCI_DEBUG 2324 if (ohcidebug > 1) { 2325 DPRINTF(("ohci_abort_xfer: sed=\n")); 2326 ohci_dump_ed(sc, sed); 2327 ohci_dump_tds(sc, p); 2328 } 2329 #endif 2330 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2331 hit = 0; 2332 for (; p->xfer == xfer; p = n) { 2333 hit |= headp == p->physaddr; 2334 n = p->nexttd; 2335 ohci_free_std(sc, p); 2336 } 2337 /* Zap headp register if hardware pointed inside the xfer. */ 2338 if (hit) { 2339 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2340 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2341 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2342 usb_syncmem(&sed->dma, 2343 sed->offs + offsetof(ohci_ed_t, ed_headp), 2344 sizeof(sed->ed.ed_headp), 2345 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2346 } else { 2347 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2348 } 2349 2350 /* 2351 * Step 4: Turn on hardware again. 2352 */ 2353 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2354 sizeof(sed->ed.ed_flags), 2355 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2356 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2357 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2358 sizeof(sed->ed.ed_flags), 2359 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2360 2361 /* 2362 * Step 5: Execute callback. 2363 */ 2364 wake = xfer->hcflags & UXFER_ABORTWAIT; 2365 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2366 usb_transfer_complete(xfer); 2367 if (wake) 2368 wakeup(&xfer->hcflags); 2369 2370 splx(s); 2371 } 2372 2373 /* 2374 * Data structures and routines to emulate the root hub. 2375 */ 2376 Static usb_device_descriptor_t ohci_devd = { 2377 USB_DEVICE_DESCRIPTOR_SIZE, 2378 UDESC_DEVICE, /* type */ 2379 {0x00, 0x01}, /* USB version */ 2380 UDCLASS_HUB, /* class */ 2381 UDSUBCLASS_HUB, /* subclass */ 2382 UDPROTO_FSHUB, /* protocol */ 2383 64, /* max packet */ 2384 {0},{0},{0x00,0x01}, /* device id */ 2385 1,2,0, /* string indicies */ 2386 1 /* # of configurations */ 2387 }; 2388 2389 Static const usb_config_descriptor_t ohci_confd = { 2390 USB_CONFIG_DESCRIPTOR_SIZE, 2391 UDESC_CONFIG, 2392 {USB_CONFIG_DESCRIPTOR_SIZE + 2393 USB_INTERFACE_DESCRIPTOR_SIZE + 2394 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2395 1, 2396 1, 2397 0, 2398 UC_ATTR_MBO | UC_SELF_POWERED, 2399 0 /* max power */ 2400 }; 2401 2402 Static const usb_interface_descriptor_t ohci_ifcd = { 2403 USB_INTERFACE_DESCRIPTOR_SIZE, 2404 UDESC_INTERFACE, 2405 0, 2406 0, 2407 1, 2408 UICLASS_HUB, 2409 UISUBCLASS_HUB, 2410 UIPROTO_FSHUB, 2411 0 2412 }; 2413 2414 Static const usb_endpoint_descriptor_t ohci_endpd = { 2415 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2416 .bDescriptorType = UDESC_ENDPOINT, 2417 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2418 .bmAttributes = UE_INTERRUPT, 2419 .wMaxPacketSize = {8, 0}, /* max packet */ 2420 .bInterval = 255, 2421 }; 2422 2423 Static const usb_hub_descriptor_t ohci_hubd = { 2424 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2425 .bDescriptorType = UDESC_HUB, 2426 }; 2427 2428 /* 2429 * Simulate a hardware hub by handling all the necessary requests. 2430 */ 2431 Static usbd_status 2432 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2433 { 2434 usbd_status err; 2435 2436 /* Insert last in queue. */ 2437 err = usb_insert_transfer(xfer); 2438 if (err) 2439 return (err); 2440 2441 /* Pipe isn't running, start first */ 2442 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2443 } 2444 2445 Static usbd_status 2446 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2447 { 2448 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2449 usb_device_request_t *req; 2450 void *buf = NULL; 2451 int port, i; 2452 int s, len, value, index, l, totlen = 0; 2453 usb_port_status_t ps; 2454 usb_hub_descriptor_t hubd; 2455 usbd_status err; 2456 u_int32_t v; 2457 2458 if (sc->sc_dying) 2459 return (USBD_IOERROR); 2460 2461 #ifdef DIAGNOSTIC 2462 if (!(xfer->rqflags & URQ_REQUEST)) 2463 /* XXX panic */ 2464 return (USBD_INVAL); 2465 #endif 2466 req = &xfer->request; 2467 2468 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2469 req->bmRequestType, req->bRequest)); 2470 2471 len = UGETW(req->wLength); 2472 value = UGETW(req->wValue); 2473 index = UGETW(req->wIndex); 2474 2475 if (len != 0) 2476 buf = KERNADDR(&xfer->dmabuf, 0); 2477 2478 #define C(x,y) ((x) | ((y) << 8)) 2479 switch(C(req->bRequest, req->bmRequestType)) { 2480 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2481 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2482 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2483 /* 2484 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2485 * for the integrated root hub. 2486 */ 2487 break; 2488 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2489 if (len > 0) { 2490 *(u_int8_t *)buf = sc->sc_conf; 2491 totlen = 1; 2492 } 2493 break; 2494 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2495 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2496 if (len == 0) 2497 break; 2498 switch(value >> 8) { 2499 case UDESC_DEVICE: 2500 if ((value & 0xff) != 0) { 2501 err = USBD_IOERROR; 2502 goto ret; 2503 } 2504 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2505 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2506 memcpy(buf, &ohci_devd, l); 2507 break; 2508 case UDESC_CONFIG: 2509 if ((value & 0xff) != 0) { 2510 err = USBD_IOERROR; 2511 goto ret; 2512 } 2513 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2514 memcpy(buf, &ohci_confd, l); 2515 buf = (char *)buf + l; 2516 len -= l; 2517 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2518 totlen += l; 2519 memcpy(buf, &ohci_ifcd, l); 2520 buf = (char *)buf + l; 2521 len -= l; 2522 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2523 totlen += l; 2524 memcpy(buf, &ohci_endpd, l); 2525 break; 2526 case UDESC_STRING: 2527 #define sd ((usb_string_descriptor_t *)buf) 2528 switch (value & 0xff) { 2529 case 0: /* Language table */ 2530 totlen = usb_makelangtbl(sd, len); 2531 break; 2532 case 1: /* Vendor */ 2533 totlen = usb_makestrdesc(sd, len, 2534 sc->sc_vendor); 2535 break; 2536 case 2: /* Product */ 2537 totlen = usb_makestrdesc(sd, len, 2538 "OHCI root hub"); 2539 break; 2540 } 2541 #undef sd 2542 break; 2543 default: 2544 err = USBD_IOERROR; 2545 goto ret; 2546 } 2547 break; 2548 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2549 if (len > 0) { 2550 *(u_int8_t *)buf = 0; 2551 totlen = 1; 2552 } 2553 break; 2554 case C(UR_GET_STATUS, UT_READ_DEVICE): 2555 if (len > 1) { 2556 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2557 totlen = 2; 2558 } 2559 break; 2560 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2561 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2562 if (len > 1) { 2563 USETW(((usb_status_t *)buf)->wStatus, 0); 2564 totlen = 2; 2565 } 2566 break; 2567 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2568 if (value >= USB_MAX_DEVICES) { 2569 err = USBD_IOERROR; 2570 goto ret; 2571 } 2572 sc->sc_addr = value; 2573 break; 2574 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2575 if (value != 0 && value != 1) { 2576 err = USBD_IOERROR; 2577 goto ret; 2578 } 2579 sc->sc_conf = value; 2580 break; 2581 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2582 break; 2583 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2584 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2585 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2586 err = USBD_IOERROR; 2587 goto ret; 2588 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2589 break; 2590 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2591 break; 2592 /* Hub requests */ 2593 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2594 break; 2595 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2596 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2597 "port=%d feature=%d\n", 2598 index, value)); 2599 if (index < 1 || index > sc->sc_noport) { 2600 err = USBD_IOERROR; 2601 goto ret; 2602 } 2603 port = OHCI_RH_PORT_STATUS(index); 2604 switch(value) { 2605 case UHF_PORT_ENABLE: 2606 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2607 break; 2608 case UHF_PORT_SUSPEND: 2609 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2610 break; 2611 case UHF_PORT_POWER: 2612 /* Yes, writing to the LOW_SPEED bit clears power. */ 2613 OWRITE4(sc, port, UPS_LOW_SPEED); 2614 break; 2615 case UHF_C_PORT_CONNECTION: 2616 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2617 break; 2618 case UHF_C_PORT_ENABLE: 2619 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2620 break; 2621 case UHF_C_PORT_SUSPEND: 2622 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2623 break; 2624 case UHF_C_PORT_OVER_CURRENT: 2625 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2626 break; 2627 case UHF_C_PORT_RESET: 2628 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2629 break; 2630 default: 2631 err = USBD_IOERROR; 2632 goto ret; 2633 } 2634 switch(value) { 2635 case UHF_C_PORT_CONNECTION: 2636 case UHF_C_PORT_ENABLE: 2637 case UHF_C_PORT_SUSPEND: 2638 case UHF_C_PORT_OVER_CURRENT: 2639 case UHF_C_PORT_RESET: 2640 /* Enable RHSC interrupt if condition is cleared. */ 2641 if ((OREAD4(sc, port) >> 16) == 0) 2642 ohci_rhsc_enable(sc); 2643 break; 2644 default: 2645 break; 2646 } 2647 break; 2648 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2649 if (len == 0) 2650 break; 2651 if ((value & 0xff) != 0) { 2652 err = USBD_IOERROR; 2653 goto ret; 2654 } 2655 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2656 hubd = ohci_hubd; 2657 hubd.bNbrPorts = sc->sc_noport; 2658 USETW(hubd.wHubCharacteristics, 2659 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2660 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2661 /* XXX overcurrent */ 2662 ); 2663 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2664 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2665 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2666 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2667 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2668 l = min(len, hubd.bDescLength); 2669 totlen = l; 2670 memcpy(buf, &hubd, l); 2671 break; 2672 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2673 if (len != 4) { 2674 err = USBD_IOERROR; 2675 goto ret; 2676 } 2677 memset(buf, 0, len); /* ? XXX */ 2678 totlen = len; 2679 break; 2680 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2681 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2682 index)); 2683 if (index < 1 || index > sc->sc_noport) { 2684 err = USBD_IOERROR; 2685 goto ret; 2686 } 2687 if (len != 4) { 2688 err = USBD_IOERROR; 2689 goto ret; 2690 } 2691 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2692 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2693 v)); 2694 USETW(ps.wPortStatus, v); 2695 USETW(ps.wPortChange, v >> 16); 2696 l = min(len, sizeof ps); 2697 memcpy(buf, &ps, l); 2698 totlen = l; 2699 break; 2700 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2701 err = USBD_IOERROR; 2702 goto ret; 2703 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2704 break; 2705 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2706 if (index < 1 || index > sc->sc_noport) { 2707 err = USBD_IOERROR; 2708 goto ret; 2709 } 2710 port = OHCI_RH_PORT_STATUS(index); 2711 switch(value) { 2712 case UHF_PORT_ENABLE: 2713 OWRITE4(sc, port, UPS_PORT_ENABLED); 2714 break; 2715 case UHF_PORT_SUSPEND: 2716 OWRITE4(sc, port, UPS_SUSPEND); 2717 break; 2718 case UHF_PORT_RESET: 2719 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2720 index)); 2721 OWRITE4(sc, port, UPS_RESET); 2722 for (i = 0; i < 5; i++) { 2723 usb_delay_ms(&sc->sc_bus, 2724 USB_PORT_ROOT_RESET_DELAY); 2725 if (sc->sc_dying) { 2726 err = USBD_IOERROR; 2727 goto ret; 2728 } 2729 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2730 break; 2731 } 2732 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2733 index, OREAD4(sc, port))); 2734 break; 2735 case UHF_PORT_POWER: 2736 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2737 "%d\n", index)); 2738 OWRITE4(sc, port, UPS_PORT_POWER); 2739 break; 2740 default: 2741 err = USBD_IOERROR; 2742 goto ret; 2743 } 2744 break; 2745 default: 2746 err = USBD_IOERROR; 2747 goto ret; 2748 } 2749 xfer->actlen = totlen; 2750 err = USBD_NORMAL_COMPLETION; 2751 ret: 2752 xfer->status = err; 2753 s = splusb(); 2754 usb_transfer_complete(xfer); 2755 splx(s); 2756 return (USBD_IN_PROGRESS); 2757 } 2758 2759 /* Abort a root control request. */ 2760 Static void 2761 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2762 { 2763 /* Nothing to do, all transfers are synchronous. */ 2764 } 2765 2766 /* Close the root pipe. */ 2767 Static void 2768 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2769 { 2770 DPRINTF(("ohci_root_ctrl_close\n")); 2771 /* Nothing to do. */ 2772 } 2773 2774 Static usbd_status 2775 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2776 { 2777 usbd_status err; 2778 2779 /* Insert last in queue. */ 2780 err = usb_insert_transfer(xfer); 2781 if (err) 2782 return (err); 2783 2784 /* Pipe isn't running, start first */ 2785 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2786 } 2787 2788 Static usbd_status 2789 ohci_root_intr_start(usbd_xfer_handle xfer) 2790 { 2791 usbd_pipe_handle pipe = xfer->pipe; 2792 ohci_softc_t *sc = pipe->device->bus->hci_private; 2793 2794 if (sc->sc_dying) 2795 return (USBD_IOERROR); 2796 2797 sc->sc_intrxfer = xfer; 2798 2799 return (USBD_IN_PROGRESS); 2800 } 2801 2802 /* Abort a root interrupt request. */ 2803 Static void 2804 ohci_root_intr_abort(usbd_xfer_handle xfer) 2805 { 2806 int s; 2807 2808 if (xfer->pipe->intrxfer == xfer) { 2809 DPRINTF(("ohci_root_intr_abort: remove\n")); 2810 xfer->pipe->intrxfer = NULL; 2811 } 2812 xfer->status = USBD_CANCELLED; 2813 s = splusb(); 2814 usb_transfer_complete(xfer); 2815 splx(s); 2816 } 2817 2818 /* Close the root pipe. */ 2819 Static void 2820 ohci_root_intr_close(usbd_pipe_handle pipe) 2821 { 2822 ohci_softc_t *sc = pipe->device->bus->hci_private; 2823 2824 DPRINTF(("ohci_root_intr_close\n")); 2825 2826 sc->sc_intrxfer = NULL; 2827 } 2828 2829 /************************/ 2830 2831 Static usbd_status 2832 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2833 { 2834 usbd_status err; 2835 2836 /* Insert last in queue. */ 2837 err = usb_insert_transfer(xfer); 2838 if (err) 2839 return (err); 2840 2841 /* Pipe isn't running, start first */ 2842 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2843 } 2844 2845 Static usbd_status 2846 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2847 { 2848 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2849 usbd_status err; 2850 2851 if (sc->sc_dying) 2852 return (USBD_IOERROR); 2853 2854 #ifdef DIAGNOSTIC 2855 if (!(xfer->rqflags & URQ_REQUEST)) { 2856 /* XXX panic */ 2857 printf("ohci_device_ctrl_transfer: not a request\n"); 2858 return (USBD_INVAL); 2859 } 2860 #endif 2861 2862 err = ohci_device_request(xfer); 2863 if (err) 2864 return (err); 2865 2866 if (sc->sc_bus.use_polling) 2867 ohci_waitintr(sc, xfer); 2868 return (USBD_IN_PROGRESS); 2869 } 2870 2871 /* Abort a device control request. */ 2872 Static void 2873 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2874 { 2875 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2876 ohci_abort_xfer(xfer, USBD_CANCELLED); 2877 } 2878 2879 /* Close a device control pipe. */ 2880 Static void 2881 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2882 { 2883 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2884 ohci_softc_t *sc = pipe->device->bus->hci_private; 2885 2886 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2887 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2888 ohci_free_std(sc, opipe->tail.td); 2889 } 2890 2891 /************************/ 2892 2893 Static void 2894 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2895 { 2896 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2897 ohci_softc_t *sc = pipe->device->bus->hci_private; 2898 2899 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2900 } 2901 2902 Static void 2903 ohci_noop(usbd_pipe_handle pipe) 2904 { 2905 } 2906 2907 Static usbd_status 2908 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2909 { 2910 usbd_status err; 2911 2912 /* Insert last in queue. */ 2913 err = usb_insert_transfer(xfer); 2914 if (err) 2915 return (err); 2916 2917 /* Pipe isn't running, start first */ 2918 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2919 } 2920 2921 Static usbd_status 2922 ohci_device_bulk_start(usbd_xfer_handle xfer) 2923 { 2924 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2925 usbd_device_handle dev = opipe->pipe.device; 2926 ohci_softc_t *sc = dev->bus->hci_private; 2927 int addr = dev->address; 2928 ohci_soft_td_t *data, *tail, *tdp; 2929 ohci_soft_ed_t *sed; 2930 int s, len, isread, endpt; 2931 usbd_status err; 2932 2933 if (sc->sc_dying) 2934 return (USBD_IOERROR); 2935 2936 #ifdef DIAGNOSTIC 2937 if (xfer->rqflags & URQ_REQUEST) { 2938 /* XXX panic */ 2939 printf("ohci_device_bulk_start: a request\n"); 2940 return (USBD_INVAL); 2941 } 2942 #endif 2943 2944 len = xfer->length; 2945 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2946 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2947 sed = opipe->sed; 2948 2949 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2950 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2951 endpt)); 2952 2953 opipe->u.bulk.isread = isread; 2954 opipe->u.bulk.length = len; 2955 2956 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2957 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2958 /* Update device address */ 2959 sed->ed.ed_flags = HTOO32( 2960 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2961 OHCI_ED_SET_FA(addr)); 2962 2963 /* Allocate a chain of new TDs (including a new tail). */ 2964 data = opipe->tail.td; 2965 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2966 data, &tail); 2967 /* We want interrupt at the end of the transfer. */ 2968 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2969 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2970 tail->flags |= OHCI_CALL_DONE; 2971 tail = tail->nexttd; /* point at sentinel */ 2972 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2973 sizeof(tail->td.td_flags), 2974 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2975 if (err) 2976 return (err); 2977 2978 tail->xfer = NULL; 2979 xfer->hcpriv = data; 2980 2981 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2982 "td_cbp=0x%08x td_be=0x%08x\n", 2983 (int)O32TOH(sed->ed.ed_flags), 2984 (int)O32TOH(data->td.td_flags), 2985 (int)O32TOH(data->td.td_cbp), 2986 (int)O32TOH(data->td.td_be))); 2987 2988 #ifdef OHCI_DEBUG 2989 if (ohcidebug > 5) { 2990 ohci_dump_ed(sc, sed); 2991 ohci_dump_tds(sc, data); 2992 } 2993 #endif 2994 2995 /* Insert ED in schedule */ 2996 s = splusb(); 2997 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2998 tdp->xfer = xfer; 2999 } 3000 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3001 opipe->tail.td = tail; 3002 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3003 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3004 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3005 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3006 if (xfer->timeout && !sc->sc_bus.use_polling) { 3007 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3008 ohci_timeout, xfer); 3009 } 3010 3011 #if 0 3012 /* This goes wrong if we are too slow. */ 3013 if (ohcidebug > 10) { 3014 delay(10000); 3015 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3016 OREAD4(sc, OHCI_COMMAND_STATUS))); 3017 ohci_dump_ed(sc, sed); 3018 ohci_dump_tds(sc, data); 3019 } 3020 #endif 3021 3022 splx(s); 3023 3024 return (USBD_IN_PROGRESS); 3025 } 3026 3027 Static void 3028 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3029 { 3030 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3031 ohci_abort_xfer(xfer, USBD_CANCELLED); 3032 } 3033 3034 /* 3035 * Close a device bulk pipe. 3036 */ 3037 Static void 3038 ohci_device_bulk_close(usbd_pipe_handle pipe) 3039 { 3040 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3041 ohci_softc_t *sc = pipe->device->bus->hci_private; 3042 3043 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3044 ohci_close_pipe(pipe, sc->sc_bulk_head); 3045 ohci_free_std(sc, opipe->tail.td); 3046 } 3047 3048 /************************/ 3049 3050 Static usbd_status 3051 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3052 { 3053 usbd_status err; 3054 3055 /* Insert last in queue. */ 3056 err = usb_insert_transfer(xfer); 3057 if (err) 3058 return (err); 3059 3060 /* Pipe isn't running, start first */ 3061 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3062 } 3063 3064 Static usbd_status 3065 ohci_device_intr_start(usbd_xfer_handle xfer) 3066 { 3067 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3068 usbd_device_handle dev = opipe->pipe.device; 3069 ohci_softc_t *sc = dev->bus->hci_private; 3070 ohci_soft_ed_t *sed = opipe->sed; 3071 ohci_soft_td_t *data, *tail; 3072 int s, len, isread, endpt; 3073 3074 if (sc->sc_dying) 3075 return (USBD_IOERROR); 3076 3077 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3078 "flags=%d priv=%p\n", 3079 xfer, xfer->length, xfer->flags, xfer->priv)); 3080 3081 #ifdef DIAGNOSTIC 3082 if (xfer->rqflags & URQ_REQUEST) 3083 panic("ohci_device_intr_transfer: a request"); 3084 #endif 3085 3086 len = xfer->length; 3087 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3088 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3089 3090 data = opipe->tail.td; 3091 tail = ohci_alloc_std(sc); 3092 if (tail == NULL) 3093 return (USBD_NOMEM); 3094 tail->xfer = NULL; 3095 3096 data->td.td_flags = HTOO32( 3097 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3098 OHCI_TD_NOCC | 3099 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3100 if (xfer->flags & USBD_SHORT_XFER_OK) 3101 data->td.td_flags |= HTOO32(OHCI_TD_R); 3102 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3103 data->nexttd = tail; 3104 data->td.td_nexttd = HTOO32(tail->physaddr); 3105 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3106 data->len = len; 3107 data->xfer = xfer; 3108 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3109 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3110 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3111 xfer->hcpriv = data; 3112 3113 #ifdef OHCI_DEBUG 3114 if (ohcidebug > 5) { 3115 DPRINTF(("ohci_device_intr_transfer:\n")); 3116 ohci_dump_ed(sc, sed); 3117 ohci_dump_tds(sc, data); 3118 } 3119 #endif 3120 3121 /* Insert ED in schedule */ 3122 s = splusb(); 3123 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3124 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3125 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3126 opipe->tail.td = tail; 3127 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3128 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3129 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3130 3131 #if 0 3132 /* 3133 * This goes horribly wrong, printing thousands of descriptors, 3134 * because false references are followed due to the fact that the 3135 * TD is gone. 3136 */ 3137 if (ohcidebug > 5) { 3138 usb_delay_ms(&sc->sc_bus, 5); 3139 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3140 OREAD4(sc, OHCI_COMMAND_STATUS))); 3141 ohci_dump_ed(sc, sed); 3142 ohci_dump_tds(sc, data); 3143 } 3144 #endif 3145 splx(s); 3146 3147 return (USBD_IN_PROGRESS); 3148 } 3149 3150 /* Abort a device control request. */ 3151 Static void 3152 ohci_device_intr_abort(usbd_xfer_handle xfer) 3153 { 3154 if (xfer->pipe->intrxfer == xfer) { 3155 DPRINTF(("ohci_device_intr_abort: remove\n")); 3156 xfer->pipe->intrxfer = NULL; 3157 } 3158 ohci_abort_xfer(xfer, USBD_CANCELLED); 3159 } 3160 3161 /* Close a device interrupt pipe. */ 3162 Static void 3163 ohci_device_intr_close(usbd_pipe_handle pipe) 3164 { 3165 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3166 ohci_softc_t *sc = pipe->device->bus->hci_private; 3167 int nslots = opipe->u.intr.nslots; 3168 int pos = opipe->u.intr.pos; 3169 int j; 3170 ohci_soft_ed_t *p, *sed = opipe->sed; 3171 int s; 3172 3173 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3174 pipe, nslots, pos)); 3175 s = splusb(); 3176 usb_syncmem(&sed->dma, sed->offs, 3177 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3179 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3180 sizeof(sed->ed.ed_flags), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3183 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3184 usb_delay_ms(&sc->sc_bus, 2); 3185 3186 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3187 continue; 3188 #ifdef DIAGNOSTIC 3189 if (p == NULL) 3190 panic("ohci_device_intr_close: ED not found"); 3191 #endif 3192 p->next = sed->next; 3193 p->ed.ed_nexted = sed->ed.ed_nexted; 3194 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3195 sizeof(p->ed.ed_nexted), 3196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3197 splx(s); 3198 3199 for (j = 0; j < nslots; j++) 3200 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3201 3202 ohci_free_std(sc, opipe->tail.td); 3203 ohci_free_sed(sc, opipe->sed); 3204 } 3205 3206 Static usbd_status 3207 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3208 { 3209 int i, j, s, best; 3210 u_int npoll, slow, shigh, nslots; 3211 u_int bestbw, bw; 3212 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3213 3214 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3215 if (ival == 0) { 3216 printf("ohci_setintr: 0 interval\n"); 3217 return (USBD_INVAL); 3218 } 3219 3220 npoll = OHCI_NO_INTRS; 3221 while (npoll > ival) 3222 npoll /= 2; 3223 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3224 3225 /* 3226 * We now know which level in the tree the ED must go into. 3227 * Figure out which slot has most bandwidth left over. 3228 * Slots to examine: 3229 * npoll 3230 * 1 0 3231 * 2 1 2 3232 * 4 3 4 5 6 3233 * 8 7 8 9 10 11 12 13 14 3234 * N (N-1) .. (N-1+N-1) 3235 */ 3236 slow = npoll-1; 3237 shigh = slow + npoll; 3238 nslots = OHCI_NO_INTRS / npoll; 3239 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3240 bw = 0; 3241 for (j = 0; j < nslots; j++) 3242 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3243 if (bw < bestbw) { 3244 best = i; 3245 bestbw = bw; 3246 } 3247 } 3248 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3249 best, slow, shigh, bestbw)); 3250 3251 s = splusb(); 3252 hsed = sc->sc_eds[best]; 3253 sed->next = hsed->next; 3254 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3255 sizeof(hsed->ed.ed_flags), 3256 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3257 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3258 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3259 sizeof(sed->ed.ed_flags), 3260 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3261 hsed->next = sed; 3262 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3263 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3264 sizeof(hsed->ed.ed_flags), 3265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3266 splx(s); 3267 3268 for (j = 0; j < nslots; j++) 3269 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3270 opipe->u.intr.nslots = nslots; 3271 opipe->u.intr.pos = best; 3272 3273 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3274 return (USBD_NORMAL_COMPLETION); 3275 } 3276 3277 /***********************/ 3278 3279 usbd_status 3280 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3281 { 3282 usbd_status err; 3283 3284 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3285 3286 /* Put it on our queue, */ 3287 err = usb_insert_transfer(xfer); 3288 3289 /* bail out on error, */ 3290 if (err && err != USBD_IN_PROGRESS) 3291 return (err); 3292 3293 /* XXX should check inuse here */ 3294 3295 /* insert into schedule, */ 3296 ohci_device_isoc_enter(xfer); 3297 3298 /* and start if the pipe wasn't running */ 3299 if (!err) 3300 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3301 3302 return (err); 3303 } 3304 3305 void 3306 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3307 { 3308 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3309 usbd_device_handle dev = opipe->pipe.device; 3310 ohci_softc_t *sc = dev->bus->hci_private; 3311 ohci_soft_ed_t *sed = opipe->sed; 3312 struct iso *iso = &opipe->u.iso; 3313 ohci_soft_itd_t *sitd, *nsitd; 3314 ohci_physaddr_t buf, offs, noffs, bp0; 3315 int i, ncur, nframes; 3316 int s; 3317 3318 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3319 "nframes=%d\n", 3320 iso->inuse, iso->next, xfer, xfer->nframes)); 3321 3322 if (sc->sc_dying) 3323 return; 3324 3325 if (iso->next == -1) { 3326 /* Not in use yet, schedule it a few frames ahead. */ 3327 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3328 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3329 iso->next)); 3330 } 3331 3332 sitd = opipe->tail.itd; 3333 buf = DMAADDR(&xfer->dmabuf, 0); 3334 bp0 = OHCI_PAGE(buf); 3335 offs = OHCI_PAGE_OFFSET(buf); 3336 nframes = xfer->nframes; 3337 xfer->hcpriv = sitd; 3338 for (i = ncur = 0; i < nframes; i++, ncur++) { 3339 noffs = offs + xfer->frlengths[i]; 3340 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3341 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3342 3343 /* Allocate next ITD */ 3344 nsitd = ohci_alloc_sitd(sc); 3345 if (nsitd == NULL) { 3346 /* XXX what now? */ 3347 printf("%s: isoc TD alloc failed\n", 3348 device_xname(sc->sc_dev)); 3349 return; 3350 } 3351 3352 /* Fill current ITD */ 3353 sitd->itd.itd_flags = HTOO32( 3354 OHCI_ITD_NOCC | 3355 OHCI_ITD_SET_SF(iso->next) | 3356 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3357 OHCI_ITD_SET_FC(ncur)); 3358 sitd->itd.itd_bp0 = HTOO32(bp0); 3359 sitd->nextitd = nsitd; 3360 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3361 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3362 sitd->xfer = xfer; 3363 sitd->flags = 0; 3364 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3365 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3366 3367 sitd = nsitd; 3368 iso->next = iso->next + ncur; 3369 bp0 = OHCI_PAGE(buf + offs); 3370 ncur = 0; 3371 } 3372 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3373 offs = noffs; 3374 } 3375 nsitd = ohci_alloc_sitd(sc); 3376 if (nsitd == NULL) { 3377 /* XXX what now? */ 3378 printf("%s: isoc TD alloc failed\n", 3379 device_xname(sc->sc_dev)); 3380 return; 3381 } 3382 /* Fixup last used ITD */ 3383 sitd->itd.itd_flags = HTOO32( 3384 OHCI_ITD_NOCC | 3385 OHCI_ITD_SET_SF(iso->next) | 3386 OHCI_ITD_SET_DI(0) | 3387 OHCI_ITD_SET_FC(ncur)); 3388 sitd->itd.itd_bp0 = HTOO32(bp0); 3389 sitd->nextitd = nsitd; 3390 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3391 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3392 sitd->xfer = xfer; 3393 sitd->flags = OHCI_CALL_DONE; 3394 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3396 3397 iso->next = iso->next + ncur; 3398 iso->inuse += nframes; 3399 3400 xfer->actlen = offs; /* XXX pretend we did it all */ 3401 3402 xfer->status = USBD_IN_PROGRESS; 3403 3404 #ifdef OHCI_DEBUG 3405 if (ohcidebug > 5) { 3406 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3407 O32TOH(sc->sc_hcca->hcca_frame_number))); 3408 ohci_dump_itds(sc, xfer->hcpriv); 3409 ohci_dump_ed(sc, sed); 3410 } 3411 #endif 3412 3413 s = splusb(); 3414 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3415 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3416 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3417 opipe->tail.itd = nsitd; 3418 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3419 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3420 sizeof(sed->ed.ed_flags), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 splx(s); 3423 3424 #ifdef OHCI_DEBUG 3425 if (ohcidebug > 5) { 3426 delay(150000); 3427 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3428 O32TOH(sc->sc_hcca->hcca_frame_number))); 3429 ohci_dump_itds(sc, xfer->hcpriv); 3430 ohci_dump_ed(sc, sed); 3431 } 3432 #endif 3433 } 3434 3435 usbd_status 3436 ohci_device_isoc_start(usbd_xfer_handle xfer) 3437 { 3438 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3439 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3440 3441 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3442 3443 if (sc->sc_dying) 3444 return (USBD_IOERROR); 3445 3446 #ifdef DIAGNOSTIC 3447 if (xfer->status != USBD_IN_PROGRESS) 3448 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3449 #endif 3450 3451 /* XXX anything to do? */ 3452 3453 return (USBD_IN_PROGRESS); 3454 } 3455 3456 void 3457 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3458 { 3459 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3460 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3461 ohci_soft_ed_t *sed; 3462 ohci_soft_itd_t *sitd; 3463 int s; 3464 3465 s = splusb(); 3466 3467 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3468 3469 /* Transfer is already done. */ 3470 if (xfer->status != USBD_NOT_STARTED && 3471 xfer->status != USBD_IN_PROGRESS) { 3472 splx(s); 3473 printf("ohci_device_isoc_abort: early return\n"); 3474 return; 3475 } 3476 3477 /* Give xfer the requested abort code. */ 3478 xfer->status = USBD_CANCELLED; 3479 3480 sed = opipe->sed; 3481 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3482 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3483 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3484 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3485 sizeof(sed->ed.ed_flags), 3486 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3487 3488 sitd = xfer->hcpriv; 3489 #ifdef DIAGNOSTIC 3490 if (sitd == NULL) { 3491 splx(s); 3492 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3493 return; 3494 } 3495 #endif 3496 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3497 #ifdef DIAGNOSTIC 3498 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3499 sitd->isdone = 1; 3500 #endif 3501 } 3502 3503 splx(s); 3504 3505 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3506 3507 s = splusb(); 3508 3509 /* Run callback. */ 3510 usb_transfer_complete(xfer); 3511 3512 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3513 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3514 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3516 3517 splx(s); 3518 } 3519 3520 void 3521 ohci_device_isoc_done(usbd_xfer_handle xfer) 3522 { 3523 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3524 } 3525 3526 usbd_status 3527 ohci_setup_isoc(usbd_pipe_handle pipe) 3528 { 3529 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3530 ohci_softc_t *sc = pipe->device->bus->hci_private; 3531 struct iso *iso = &opipe->u.iso; 3532 int s; 3533 3534 iso->next = -1; 3535 iso->inuse = 0; 3536 3537 s = splusb(); 3538 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3539 splx(s); 3540 3541 return (USBD_NORMAL_COMPLETION); 3542 } 3543 3544 void 3545 ohci_device_isoc_close(usbd_pipe_handle pipe) 3546 { 3547 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3548 ohci_softc_t *sc = pipe->device->bus->hci_private; 3549 3550 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3551 ohci_close_pipe(pipe, sc->sc_isoc_head); 3552 #ifdef DIAGNOSTIC 3553 opipe->tail.itd->isdone = 1; 3554 #endif 3555 ohci_free_sitd(sc, opipe->tail.itd); 3556 } 3557
Indexes created Fri Oct 03 02:09:57 GMT 2025