ohci.c revision 1.210
1 /* $NetBSD: ohci.c,v 1.210 2010/11/13 13:52:12 uebayasi Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.210 2010/11/13 13:52:12 uebayasi Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 55 #include <sys/bus.h> 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 #if 0 102 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 103 ohci_soft_td_t *); 104 #endif 105 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 106 ohci_softc_t *, int, int, usbd_xfer_handle, 107 ohci_soft_td_t *, ohci_soft_td_t **); 108 109 Static usbd_status ohci_open(usbd_pipe_handle); 110 Static void ohci_poll(struct usbd_bus *); 111 Static void ohci_softintr(void *); 112 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 113 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 114 115 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 116 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 117 ohci_soft_ed_t *); 118 119 Static void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 136 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 137 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 138 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 139 Static void ohci_root_ctrl_close(usbd_pipe_handle); 140 Static void ohci_root_ctrl_done(usbd_xfer_handle); 141 142 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 143 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 144 Static void ohci_root_intr_abort(usbd_xfer_handle); 145 Static void ohci_root_intr_close(usbd_pipe_handle); 146 Static void ohci_root_intr_done(usbd_xfer_handle); 147 148 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 149 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 150 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 151 Static void ohci_device_ctrl_close(usbd_pipe_handle); 152 Static void ohci_device_ctrl_done(usbd_xfer_handle); 153 154 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 155 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 156 Static void ohci_device_bulk_abort(usbd_xfer_handle); 157 Static void ohci_device_bulk_close(usbd_pipe_handle); 158 Static void ohci_device_bulk_done(usbd_xfer_handle); 159 160 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 161 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 162 Static void ohci_device_intr_abort(usbd_xfer_handle); 163 Static void ohci_device_intr_close(usbd_pipe_handle); 164 Static void ohci_device_intr_done(usbd_xfer_handle); 165 166 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 167 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 168 Static void ohci_device_isoc_abort(usbd_xfer_handle); 169 Static void ohci_device_isoc_close(usbd_pipe_handle); 170 Static void ohci_device_isoc_done(usbd_xfer_handle); 171 172 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 173 struct ohci_pipe *pipe, int ival); 174 175 Static void ohci_timeout(void *); 176 Static void ohci_timeout_task(void *); 177 Static void ohci_rhsc_enable(void *); 178 179 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 180 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 181 182 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 183 Static void ohci_noop(usbd_pipe_handle pipe); 184 185 #ifdef OHCI_DEBUG 186 Static void ohci_dumpregs(ohci_softc_t *); 187 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 188 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 190 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 191 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 192 #endif 193 194 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 195 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 196 #define OWRITE1(sc, r, x) \ 197 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 198 #define OWRITE2(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 #define OWRITE4(sc, r, x) \ 201 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 202 static __inline uint8_t 203 OREAD1(ohci_softc_t *sc, bus_size_t r) 204 { 205 206 OBARR(sc); 207 return bus_space_read_1(sc->iot, sc->ioh, r); 208 } 209 210 static __inline uint16_t 211 OREAD2(ohci_softc_t *sc, bus_size_t r) 212 { 213 214 OBARR(sc); 215 return bus_space_read_2(sc->iot, sc->ioh, r); 216 } 217 218 static __inline uint32_t 219 OREAD4(ohci_softc_t *sc, bus_size_t r) 220 { 221 222 OBARR(sc); 223 return bus_space_read_4(sc->iot, sc->ioh, r); 224 } 225 226 /* Reverse the bits in a value 0 .. 31 */ 227 Static u_int8_t revbits[OHCI_NO_INTRS] = 228 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 229 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 230 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 231 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 232 233 struct ohci_pipe { 234 struct usbd_pipe pipe; 235 ohci_soft_ed_t *sed; 236 union { 237 ohci_soft_td_t *td; 238 ohci_soft_itd_t *itd; 239 } tail; 240 /* Info needed for different pipe kinds. */ 241 union { 242 /* Control pipe */ 243 struct { 244 usb_dma_t reqdma; 245 u_int length; 246 ohci_soft_td_t *setup, *data, *stat; 247 } ctl; 248 /* Interrupt pipe */ 249 struct { 250 int nslots; 251 int pos; 252 } intr; 253 /* Bulk pipe */ 254 struct { 255 u_int length; 256 int isread; 257 } bulk; 258 /* Iso pipe */ 259 struct iso { 260 int next, inuse; 261 } iso; 262 } u; 263 }; 264 265 #define OHCI_INTR_ENDPT 1 266 267 Static const struct usbd_bus_methods ohci_bus_methods = { 268 ohci_open, 269 ohci_softintr, 270 ohci_poll, 271 ohci_allocm, 272 ohci_freem, 273 ohci_allocx, 274 ohci_freex, 275 }; 276 277 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 278 ohci_root_ctrl_transfer, 279 ohci_root_ctrl_start, 280 ohci_root_ctrl_abort, 281 ohci_root_ctrl_close, 282 ohci_noop, 283 ohci_root_ctrl_done, 284 }; 285 286 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 287 ohci_root_intr_transfer, 288 ohci_root_intr_start, 289 ohci_root_intr_abort, 290 ohci_root_intr_close, 291 ohci_noop, 292 ohci_root_intr_done, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 296 ohci_device_ctrl_transfer, 297 ohci_device_ctrl_start, 298 ohci_device_ctrl_abort, 299 ohci_device_ctrl_close, 300 ohci_noop, 301 ohci_device_ctrl_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 305 ohci_device_intr_transfer, 306 ohci_device_intr_start, 307 ohci_device_intr_abort, 308 ohci_device_intr_close, 309 ohci_device_clear_toggle, 310 ohci_device_intr_done, 311 }; 312 313 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 314 ohci_device_bulk_transfer, 315 ohci_device_bulk_start, 316 ohci_device_bulk_abort, 317 ohci_device_bulk_close, 318 ohci_device_clear_toggle, 319 ohci_device_bulk_done, 320 }; 321 322 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 323 ohci_device_isoc_transfer, 324 ohci_device_isoc_start, 325 ohci_device_isoc_abort, 326 ohci_device_isoc_close, 327 ohci_noop, 328 ohci_device_isoc_done, 329 }; 330 331 int 332 ohci_activate(device_t self, enum devact act) 333 { 334 struct ohci_softc *sc = device_private(self); 335 336 switch (act) { 337 case DVACT_DEACTIVATE: 338 sc->sc_dying = 1; 339 return 0; 340 default: 341 return EOPNOTSUPP; 342 } 343 } 344 345 void 346 ohci_childdet(device_t self, device_t child) 347 { 348 struct ohci_softc *sc = device_private(self); 349 350 KASSERT(sc->sc_child == child); 351 sc->sc_child = NULL; 352 } 353 354 int 355 ohci_detach(struct ohci_softc *sc, int flags) 356 { 357 int rv = 0; 358 usbd_xfer_handle xfer; 359 360 if (sc->sc_child != NULL) 361 rv = config_detach(sc->sc_child, flags); 362 363 if (rv != 0) 364 return (rv); 365 366 callout_stop(&sc->sc_tmo_rhsc); 367 368 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 369 callout_destroy(&sc->sc_tmo_rhsc); 370 371 if (sc->sc_hcca != NULL) 372 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 373 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 374 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 375 free(xfer, M_USB); 376 } 377 378 return (rv); 379 } 380 381 ohci_soft_ed_t * 382 ohci_alloc_sed(ohci_softc_t *sc) 383 { 384 ohci_soft_ed_t *sed; 385 usbd_status err; 386 int i, offs; 387 usb_dma_t dma; 388 389 if (sc->sc_freeeds == NULL) { 390 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 391 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 392 OHCI_ED_ALIGN, &dma); 393 if (err) 394 return (0); 395 for(i = 0; i < OHCI_SED_CHUNK; i++) { 396 offs = i * OHCI_SED_SIZE; 397 sed = KERNADDR(&dma, offs); 398 sed->physaddr = DMAADDR(&dma, offs); 399 sed->dma = dma; 400 sed->offs = offs; 401 sed->next = sc->sc_freeeds; 402 sc->sc_freeeds = sed; 403 } 404 } 405 sed = sc->sc_freeeds; 406 sc->sc_freeeds = sed->next; 407 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 408 sed->next = 0; 409 return (sed); 410 } 411 412 void 413 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 414 { 415 sed->next = sc->sc_freeeds; 416 sc->sc_freeeds = sed; 417 } 418 419 ohci_soft_td_t * 420 ohci_alloc_std(ohci_softc_t *sc) 421 { 422 ohci_soft_td_t *std; 423 usbd_status err; 424 int i, offs; 425 usb_dma_t dma; 426 int s; 427 428 if (sc->sc_freetds == NULL) { 429 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 430 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 431 OHCI_TD_ALIGN, &dma); 432 if (err) 433 return (NULL); 434 s = splusb(); 435 for(i = 0; i < OHCI_STD_CHUNK; i++) { 436 offs = i * OHCI_STD_SIZE; 437 std = KERNADDR(&dma, offs); 438 std->physaddr = DMAADDR(&dma, offs); 439 std->dma = dma; 440 std->offs = offs; 441 std->nexttd = sc->sc_freetds; 442 sc->sc_freetds = std; 443 } 444 splx(s); 445 } 446 447 s = splusb(); 448 std = sc->sc_freetds; 449 sc->sc_freetds = std->nexttd; 450 memset(&std->td, 0, sizeof(ohci_td_t)); 451 std->nexttd = NULL; 452 std->xfer = NULL; 453 ohci_hash_add_td(sc, std); 454 splx(s); 455 456 return (std); 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 int s; 463 464 s = splusb(); 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 splx(s); 469 } 470 471 usbd_status 472 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 473 int alen, int rd, usbd_xfer_handle xfer, 474 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 475 { 476 ohci_soft_td_t *next, *cur; 477 ohci_physaddr_t dataphys, dataphysend; 478 u_int32_t tdflags; 479 int len, curlen; 480 usb_dma_t *dma = &xfer->dmabuf; 481 u_int16_t flags = xfer->flags; 482 483 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 484 485 len = alen; 486 cur = sp; 487 dataphys = DMAADDR(dma, 0); 488 dataphysend = OHCI_PAGE(dataphys + len - 1); 489 usb_syncmem(dma, 0, len, 490 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 491 tdflags = HTOO32( 492 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 493 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 494 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 495 496 for (;;) { 497 next = ohci_alloc_std(sc); 498 if (next == NULL) 499 goto nomem; 500 501 /* The OHCI hardware can handle at most one page crossing. */ 502 if (OHCI_PAGE(dataphys) == dataphysend || 503 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 504 /* we can handle it in this TD */ 505 curlen = len; 506 } else { 507 /* must use multiple TDs, fill as much as possible. */ 508 curlen = 2 * OHCI_PAGE_SIZE - 509 (dataphys & (OHCI_PAGE_SIZE-1)); 510 /* the length must be a multiple of the max size */ 511 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 512 #ifdef DIAGNOSTIC 513 if (curlen == 0) 514 panic("ohci_alloc_std: curlen == 0"); 515 #endif 516 } 517 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 518 "dataphysend=0x%08x len=%d curlen=%d\n", 519 dataphys, dataphysend, 520 len, curlen)); 521 len -= curlen; 522 523 cur->td.td_flags = tdflags; 524 cur->td.td_cbp = HTOO32(dataphys); 525 cur->nexttd = next; 526 cur->td.td_nexttd = HTOO32(next->physaddr); 527 cur->td.td_be = HTOO32(dataphys + curlen - 1); 528 cur->len = curlen; 529 cur->flags = OHCI_ADD_LEN; 530 cur->xfer = xfer; 531 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 533 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 534 dataphys, dataphys + curlen - 1)); 535 if (len == 0) 536 break; 537 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 538 dataphys += curlen; 539 cur = next; 540 } 541 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 542 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 543 /* Force a 0 length transfer at the end. */ 544 545 cur = next; 546 next = ohci_alloc_std(sc); 547 if (next == NULL) 548 goto nomem; 549 550 cur->td.td_flags = tdflags; 551 cur->td.td_cbp = 0; /* indicate 0 length packet */ 552 cur->nexttd = next; 553 cur->td.td_nexttd = HTOO32(next->physaddr); 554 cur->td.td_be = ~0; 555 cur->len = 0; 556 cur->flags = 0; 557 cur->xfer = xfer; 558 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 560 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 561 } 562 *ep = cur; 563 564 return (USBD_NORMAL_COMPLETION); 565 566 nomem: 567 /* XXX free chain */ 568 return (USBD_NOMEM); 569 } 570 571 #if 0 572 Static void 573 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 574 ohci_soft_td_t *stdend) 575 { 576 ohci_soft_td_t *p; 577 578 for (; std != stdend; std = p) { 579 p = std->nexttd; 580 ohci_free_std(sc, std); 581 } 582 } 583 #endif 584 585 ohci_soft_itd_t * 586 ohci_alloc_sitd(ohci_softc_t *sc) 587 { 588 ohci_soft_itd_t *sitd; 589 usbd_status err; 590 int i, s, offs; 591 usb_dma_t dma; 592 593 if (sc->sc_freeitds == NULL) { 594 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 595 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 596 OHCI_ITD_ALIGN, &dma); 597 if (err) 598 return (NULL); 599 s = splusb(); 600 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 601 offs = i * OHCI_SITD_SIZE; 602 sitd = KERNADDR(&dma, offs); 603 sitd->physaddr = DMAADDR(&dma, offs); 604 sitd->dma = dma; 605 sitd->offs = offs; 606 sitd->nextitd = sc->sc_freeitds; 607 sc->sc_freeitds = sitd; 608 } 609 splx(s); 610 } 611 612 s = splusb(); 613 sitd = sc->sc_freeitds; 614 sc->sc_freeitds = sitd->nextitd; 615 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 616 sitd->nextitd = NULL; 617 sitd->xfer = NULL; 618 ohci_hash_add_itd(sc, sitd); 619 splx(s); 620 621 #ifdef DIAGNOSTIC 622 sitd->isdone = 0; 623 #endif 624 625 return (sitd); 626 } 627 628 void 629 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 630 { 631 int s; 632 633 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 634 635 #ifdef DIAGNOSTIC 636 if (!sitd->isdone) { 637 panic("ohci_free_sitd: sitd=%p not done", sitd); 638 return; 639 } 640 /* Warn double free */ 641 sitd->isdone = 0; 642 #endif 643 644 s = splusb(); 645 ohci_hash_rem_itd(sc, sitd); 646 sitd->nextitd = sc->sc_freeitds; 647 sc->sc_freeitds = sitd; 648 splx(s); 649 } 650 651 usbd_status 652 ohci_init(ohci_softc_t *sc) 653 { 654 ohci_soft_ed_t *sed, *psed; 655 usbd_status err; 656 int i; 657 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 658 659 DPRINTF(("ohci_init: start\n")); 660 aprint_normal_dev(sc->sc_dev, ""); 661 662 sc->sc_hcca = NULL; 663 callout_init(&sc->sc_tmo_rhsc, 0); 664 665 for (i = 0; i < OHCI_HASH_SIZE; i++) 666 LIST_INIT(&sc->sc_hash_tds[i]); 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_itds[i]); 669 670 SIMPLEQ_INIT(&sc->sc_free_xfers); 671 672 rev = OREAD4(sc, OHCI_REVISION); 673 aprint_normal("OHCI version %d.%d%s\n", 674 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 675 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 676 677 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 678 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 679 sc->sc_bus.usbrev = USBREV_UNKNOWN; 680 return (USBD_INVAL); 681 } 682 sc->sc_bus.usbrev = USBREV_1_0; 683 684 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 685 USB_MEM_RESERVE); 686 687 /* XXX determine alignment by R/W */ 688 /* Allocate the HCCA area. */ 689 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 690 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 691 if (err) { 692 sc->sc_hcca = NULL; 693 return err; 694 } 695 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 696 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 697 698 sc->sc_eintrs = OHCI_NORMAL_INTRS; 699 700 /* Allocate dummy ED that starts the control list. */ 701 sc->sc_ctrl_head = ohci_alloc_sed(sc); 702 if (sc->sc_ctrl_head == NULL) { 703 err = USBD_NOMEM; 704 goto bad1; 705 } 706 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 707 708 /* Allocate dummy ED that starts the bulk list. */ 709 sc->sc_bulk_head = ohci_alloc_sed(sc); 710 if (sc->sc_bulk_head == NULL) { 711 err = USBD_NOMEM; 712 goto bad2; 713 } 714 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 715 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 716 sizeof(sc->sc_bulk_head->ed), 717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 718 719 /* Allocate dummy ED that starts the isochronous list. */ 720 sc->sc_isoc_head = ohci_alloc_sed(sc); 721 if (sc->sc_isoc_head == NULL) { 722 err = USBD_NOMEM; 723 goto bad3; 724 } 725 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 726 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 727 sizeof(sc->sc_isoc_head->ed), 728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 729 730 /* Allocate all the dummy EDs that make up the interrupt tree. */ 731 for (i = 0; i < OHCI_NO_EDS; i++) { 732 sed = ohci_alloc_sed(sc); 733 if (sed == NULL) { 734 while (--i >= 0) 735 ohci_free_sed(sc, sc->sc_eds[i]); 736 err = USBD_NOMEM; 737 goto bad4; 738 } 739 /* All ED fields are set to 0. */ 740 sc->sc_eds[i] = sed; 741 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 742 if (i != 0) 743 psed = sc->sc_eds[(i-1) / 2]; 744 else 745 psed= sc->sc_isoc_head; 746 sed->next = psed; 747 sed->ed.ed_nexted = HTOO32(psed->physaddr); 748 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 750 } 751 /* 752 * Fill HCCA interrupt table. The bit reversal is to get 753 * the tree set up properly to spread the interrupts. 754 */ 755 for (i = 0; i < OHCI_NO_INTRS; i++) 756 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 757 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 758 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 760 761 #ifdef OHCI_DEBUG 762 if (ohcidebug > 15) { 763 for (i = 0; i < OHCI_NO_EDS; i++) { 764 printf("ed#%d ", i); 765 ohci_dump_ed(sc, sc->sc_eds[i]); 766 } 767 printf("iso "); 768 ohci_dump_ed(sc, sc->sc_isoc_head); 769 } 770 #endif 771 772 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 773 ctl = OREAD4(sc, OHCI_CONTROL); 774 rwc = ctl & OHCI_RWC; 775 fm = OREAD4(sc, OHCI_FM_INTERVAL); 776 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 777 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 778 779 /* Determine in what context we are running. */ 780 if (ctl & OHCI_IR) { 781 /* SMM active, request change */ 782 DPRINTF(("ohci_init: SMM active, request owner change\n")); 783 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 784 (OHCI_OC | OHCI_MIE)) 785 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 786 s = OREAD4(sc, OHCI_COMMAND_STATUS); 787 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 788 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 789 usb_delay_ms(&sc->sc_bus, 1); 790 ctl = OREAD4(sc, OHCI_CONTROL); 791 } 792 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 793 if ((ctl & OHCI_IR) == 0) { 794 aprint_error_dev(sc->sc_dev, 795 "SMM does not respond, resetting\n"); 796 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 797 goto reset; 798 } 799 #if 0 800 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 801 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 802 /* BIOS started controller. */ 803 DPRINTF(("ohci_init: BIOS active\n")); 804 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 806 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 807 } 808 #endif 809 } else { 810 DPRINTF(("ohci_init: cold started\n")); 811 reset: 812 /* Controller was cold started. */ 813 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 814 } 815 816 /* 817 * This reset should not be necessary according to the OHCI spec, but 818 * without it some controllers do not start. 819 */ 820 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 821 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 822 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 823 824 /* We now own the host controller and the bus has been reset. */ 825 826 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 827 /* Nominal time for a reset is 10 us. */ 828 for (i = 0; i < 10; i++) { 829 delay(10); 830 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 831 if (!hcr) 832 break; 833 } 834 if (hcr) { 835 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 836 err = USBD_IOERROR; 837 goto bad5; 838 } 839 #ifdef OHCI_DEBUG 840 if (ohcidebug > 15) 841 ohci_dumpregs(sc); 842 #endif 843 844 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 845 846 /* Set up HC registers. */ 847 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 848 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 849 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 850 /* disable all interrupts and then switch on all desired interrupts */ 851 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 852 /* switch on desired functional features */ 853 ctl = OREAD4(sc, OHCI_CONTROL); 854 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 855 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 856 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 857 /* And finally start it! */ 858 OWRITE4(sc, OHCI_CONTROL, ctl); 859 860 /* 861 * The controller is now OPERATIONAL. Set a some final 862 * registers that should be set earlier, but that the 863 * controller ignores when in the SUSPEND state. 864 */ 865 ival = OHCI_GET_IVAL(fm); 866 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 867 fm |= OHCI_FSMPS(ival) | ival; 868 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 869 per = OHCI_PERIODIC(ival); /* 90% periodic */ 870 OWRITE4(sc, OHCI_PERIODIC_START, per); 871 872 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 873 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 874 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 875 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 876 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 877 878 /* 879 * The AMD756 requires a delay before re-reading the register, 880 * otherwise it will occasionally report 0 ports. 881 */ 882 sc->sc_noport = 0; 883 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 884 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 885 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 886 } 887 888 #ifdef OHCI_DEBUG 889 if (ohcidebug > 5) 890 ohci_dumpregs(sc); 891 #endif 892 893 /* Set up the bus struct. */ 894 sc->sc_bus.methods = &ohci_bus_methods; 895 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 896 897 sc->sc_control = sc->sc_intre = 0; 898 899 /* Finally, turn on interrupts. */ 900 DPRINTFN(1,("ohci_init: enabling\n")); 901 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 902 903 return (USBD_NORMAL_COMPLETION); 904 905 bad5: 906 for (i = 0; i < OHCI_NO_EDS; i++) 907 ohci_free_sed(sc, sc->sc_eds[i]); 908 bad4: 909 ohci_free_sed(sc, sc->sc_isoc_head); 910 bad3: 911 ohci_free_sed(sc, sc->sc_bulk_head); 912 bad2: 913 ohci_free_sed(sc, sc->sc_ctrl_head); 914 bad1: 915 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 916 sc->sc_hcca = NULL; 917 return (err); 918 } 919 920 usbd_status 921 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 922 { 923 struct ohci_softc *sc = bus->hci_private; 924 usbd_status status; 925 926 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 927 if (status == USBD_NOMEM) 928 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 929 return status; 930 } 931 932 void 933 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 934 { 935 struct ohci_softc *sc = bus->hci_private; 936 if (dma->block->flags & USB_DMA_RESERVE) { 937 usb_reserve_freem(&sc->sc_dma_reserve, dma); 938 return; 939 } 940 usb_freemem(&sc->sc_bus, dma); 941 } 942 943 usbd_xfer_handle 944 ohci_allocx(struct usbd_bus *bus) 945 { 946 struct ohci_softc *sc = bus->hci_private; 947 usbd_xfer_handle xfer; 948 949 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 950 if (xfer != NULL) { 951 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 952 #ifdef DIAGNOSTIC 953 if (xfer->busy_free != XFER_FREE) { 954 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 955 xfer->busy_free); 956 } 957 #endif 958 } else { 959 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 960 } 961 if (xfer != NULL) { 962 memset(xfer, 0, sizeof (struct ohci_xfer)); 963 #ifdef DIAGNOSTIC 964 xfer->busy_free = XFER_BUSY; 965 #endif 966 } 967 return (xfer); 968 } 969 970 void 971 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 972 { 973 struct ohci_softc *sc = bus->hci_private; 974 975 #ifdef DIAGNOSTIC 976 if (xfer->busy_free != XFER_BUSY) { 977 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 978 xfer->busy_free); 979 } 980 xfer->busy_free = XFER_FREE; 981 #endif 982 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 983 } 984 985 /* 986 * Shut down the controller when the system is going down. 987 */ 988 bool 989 ohci_shutdown(device_t self, int flags) 990 { 991 ohci_softc_t *sc = device_private(self); 992 993 DPRINTF(("ohci_shutdown: stopping the HC\n")); 994 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 995 return true; 996 } 997 998 bool 999 ohci_resume(device_t dv, const pmf_qual_t *qual) 1000 { 1001 ohci_softc_t *sc = device_private(dv); 1002 uint32_t ctl; 1003 int s; 1004 1005 s = splhardusb(); 1006 sc->sc_bus.use_polling++; 1007 /* Some broken BIOSes do not recover these values */ 1008 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1009 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1010 sc->sc_ctrl_head->physaddr); 1011 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1012 sc->sc_bulk_head->physaddr); 1013 if (sc->sc_intre) 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1015 (OHCI_ALL_INTRS | OHCI_MIE)); 1016 if (sc->sc_control) 1017 ctl = sc->sc_control; 1018 else 1019 ctl = OREAD4(sc, OHCI_CONTROL); 1020 ctl |= OHCI_HCFS_RESUME; 1021 OWRITE4(sc, OHCI_CONTROL, ctl); 1022 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1023 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1024 OWRITE4(sc, OHCI_CONTROL, ctl); 1025 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1026 sc->sc_control = sc->sc_intre = 0; 1027 sc->sc_bus.use_polling--; 1028 splx(s); 1029 1030 return true; 1031 } 1032 1033 bool 1034 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1035 { 1036 ohci_softc_t *sc = device_private(dv); 1037 uint32_t ctl; 1038 int s; 1039 1040 s = splhardusb(); 1041 sc->sc_bus.use_polling++; 1042 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1043 if (sc->sc_control == 0) { 1044 /* 1045 * Preserve register values, in case that BIOS 1046 * does not recover them. 1047 */ 1048 sc->sc_control = ctl; 1049 sc->sc_intre = OREAD4(sc, 1050 OHCI_INTERRUPT_ENABLE); 1051 } 1052 ctl |= OHCI_HCFS_SUSPEND; 1053 OWRITE4(sc, OHCI_CONTROL, ctl); 1054 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1055 sc->sc_bus.use_polling--; 1056 splx(s); 1057 1058 return true; 1059 } 1060 1061 #ifdef OHCI_DEBUG 1062 void 1063 ohci_dumpregs(ohci_softc_t *sc) 1064 { 1065 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1066 OREAD4(sc, OHCI_REVISION), 1067 OREAD4(sc, OHCI_CONTROL), 1068 OREAD4(sc, OHCI_COMMAND_STATUS))); 1069 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1070 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1071 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1072 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1073 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1074 OREAD4(sc, OHCI_HCCA), 1075 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1076 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1077 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1078 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1079 OREAD4(sc, OHCI_BULK_HEAD_ED), 1080 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1081 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1082 OREAD4(sc, OHCI_DONE_HEAD), 1083 OREAD4(sc, OHCI_FM_INTERVAL), 1084 OREAD4(sc, OHCI_FM_REMAINING))); 1085 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1086 OREAD4(sc, OHCI_FM_NUMBER), 1087 OREAD4(sc, OHCI_PERIODIC_START), 1088 OREAD4(sc, OHCI_LS_THRESHOLD))); 1089 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1090 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1091 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1092 OREAD4(sc, OHCI_RH_STATUS))); 1093 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1094 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1095 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1096 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1097 O32TOH(sc->sc_hcca->hcca_frame_number), 1098 O32TOH(sc->sc_hcca->hcca_done_head))); 1099 } 1100 #endif 1101 1102 Static int ohci_intr1(ohci_softc_t *); 1103 1104 int 1105 ohci_intr(void *p) 1106 { 1107 ohci_softc_t *sc = p; 1108 1109 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 1110 return (0); 1111 1112 /* If we get an interrupt while polling, then just ignore it. */ 1113 if (sc->sc_bus.use_polling) { 1114 #ifdef DIAGNOSTIC 1115 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1116 #endif 1117 /* for level triggered intrs, should do something to ack */ 1118 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1119 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1120 1121 return (0); 1122 } 1123 1124 return (ohci_intr1(sc)); 1125 } 1126 1127 Static int 1128 ohci_intr1(ohci_softc_t *sc) 1129 { 1130 u_int32_t intrs, eintrs; 1131 1132 DPRINTFN(14,("ohci_intr1: enter\n")); 1133 1134 /* In case the interrupt occurs before initialization has completed. */ 1135 if (sc == NULL || sc->sc_hcca == NULL) { 1136 #ifdef DIAGNOSTIC 1137 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1138 #endif 1139 return (0); 1140 } 1141 1142 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1143 if (!intrs) 1144 return (0); 1145 1146 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1147 eintrs = intrs & sc->sc_eintrs; 1148 if (!eintrs) 1149 return (0); 1150 1151 sc->sc_bus.intr_context++; 1152 sc->sc_bus.no_intrs++; 1153 DPRINTFN(7, ("ohci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 1154 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1155 (u_int)eintrs)); 1156 1157 if (eintrs & OHCI_SO) { 1158 sc->sc_overrun_cnt++; 1159 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1160 printf("%s: %u scheduling overruns\n", 1161 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1162 sc->sc_overrun_cnt = 0; 1163 } 1164 /* XXX do what */ 1165 eintrs &= ~OHCI_SO; 1166 } 1167 if (eintrs & OHCI_WDH) { 1168 /* 1169 * We block the interrupt below, and reenable it later from 1170 * ohci_softintr(). 1171 */ 1172 usb_schedsoftintr(&sc->sc_bus); 1173 } 1174 if (eintrs & OHCI_RD) { 1175 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1176 /* XXX process resume detect */ 1177 } 1178 if (eintrs & OHCI_UE) { 1179 printf("%s: unrecoverable error, controller halted\n", 1180 device_xname(sc->sc_dev)); 1181 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1182 /* XXX what else */ 1183 } 1184 if (eintrs & OHCI_RHSC) { 1185 /* 1186 * We block the interrupt below, and reenable it later from 1187 * a timeout. 1188 */ 1189 ohci_rhsc(sc, sc->sc_intrxfer); 1190 /* Do not allow RHSC interrupts > 1 per second */ 1191 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1192 } 1193 1194 sc->sc_bus.intr_context--; 1195 1196 if (eintrs != 0) { 1197 /* Block unprocessed interrupts. */ 1198 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1199 sc->sc_eintrs &= ~eintrs; 1200 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1201 device_xname(sc->sc_dev), eintrs)); 1202 } 1203 1204 return (1); 1205 } 1206 1207 void 1208 ohci_rhsc_enable(void *v_sc) 1209 { 1210 ohci_softc_t *sc = v_sc; 1211 int s; 1212 1213 s = splhardusb(); 1214 sc->sc_eintrs |= OHCI_RHSC; 1215 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1216 splx(s); 1217 } 1218 1219 #ifdef OHCI_DEBUG 1220 const char *ohci_cc_strs[] = { 1221 "NO_ERROR", 1222 "CRC", 1223 "BIT_STUFFING", 1224 "DATA_TOGGLE_MISMATCH", 1225 "STALL", 1226 "DEVICE_NOT_RESPONDING", 1227 "PID_CHECK_FAILURE", 1228 "UNEXPECTED_PID", 1229 "DATA_OVERRUN", 1230 "DATA_UNDERRUN", 1231 "BUFFER_OVERRUN", 1232 "BUFFER_UNDERRUN", 1233 "reserved", 1234 "reserved", 1235 "NOT_ACCESSED", 1236 "NOT_ACCESSED", 1237 }; 1238 #endif 1239 1240 void 1241 ohci_softintr(void *v) 1242 { 1243 struct usbd_bus *bus = v; 1244 ohci_softc_t *sc = bus->hci_private; 1245 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1246 ohci_soft_td_t *std, *sdone, *stdnext; 1247 usbd_xfer_handle xfer; 1248 struct ohci_pipe *opipe; 1249 int len, cc, s; 1250 int i, j, actlen, iframes, uedir; 1251 ohci_physaddr_t done; 1252 1253 DPRINTFN(10,("ohci_softintr: enter\n")); 1254 1255 sc->sc_bus.intr_context++; 1256 1257 s = splhardusb(); 1258 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1259 sizeof(sc->sc_hcca->hcca_done_head), 1260 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1261 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1262 sc->sc_hcca->hcca_done_head = 0; 1263 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1264 sizeof(sc->sc_hcca->hcca_done_head), 1265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1266 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1267 sc->sc_eintrs |= OHCI_WDH; 1268 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1269 splx(s); 1270 1271 /* Reverse the done list. */ 1272 for (sdone = NULL, sidone = NULL; done != 0; ) { 1273 std = ohci_hash_find_td(sc, done); 1274 if (std != NULL) { 1275 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1276 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1277 std->dnext = sdone; 1278 done = O32TOH(std->td.td_nexttd); 1279 sdone = std; 1280 DPRINTFN(10,("add TD %p\n", std)); 1281 continue; 1282 } 1283 sitd = ohci_hash_find_itd(sc, done); 1284 if (sitd != NULL) { 1285 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1286 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1287 sitd->dnext = sidone; 1288 done = O32TOH(sitd->itd.itd_nextitd); 1289 sidone = sitd; 1290 DPRINTFN(5,("add ITD %p\n", sitd)); 1291 continue; 1292 } 1293 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1294 } 1295 1296 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1297 1298 #ifdef OHCI_DEBUG 1299 if (ohcidebug > 10) { 1300 DPRINTF(("ohci_process_done: TD done:\n")); 1301 ohci_dump_tds(sc, sdone); 1302 } 1303 #endif 1304 1305 for (std = sdone; std; std = stdnext) { 1306 xfer = std->xfer; 1307 stdnext = std->dnext; 1308 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1309 std, xfer, xfer ? xfer->hcpriv : 0)); 1310 if (xfer == NULL) { 1311 /* 1312 * xfer == NULL: There seems to be no xfer associated 1313 * with this TD. It is tailp that happened to end up on 1314 * the done queue. 1315 * Shouldn't happen, but some chips are broken(?). 1316 */ 1317 continue; 1318 } 1319 if (xfer->status == USBD_CANCELLED || 1320 xfer->status == USBD_TIMEOUT) { 1321 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1322 xfer)); 1323 /* Handled by abort routine. */ 1324 continue; 1325 } 1326 callout_stop(&xfer->timeout_handle); 1327 1328 len = std->len; 1329 if (std->td.td_cbp != 0) 1330 len -= O32TOH(std->td.td_be) - 1331 O32TOH(std->td.td_cbp) + 1; 1332 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1333 std->flags)); 1334 if (std->flags & OHCI_ADD_LEN) 1335 xfer->actlen += len; 1336 1337 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1338 if (cc == OHCI_CC_NO_ERROR) { 1339 if (std->flags & OHCI_CALL_DONE) { 1340 xfer->status = USBD_NORMAL_COMPLETION; 1341 s = splusb(); 1342 usb_transfer_complete(xfer); 1343 splx(s); 1344 } 1345 ohci_free_std(sc, std); 1346 } else { 1347 /* 1348 * Endpoint is halted. First unlink all the TDs 1349 * belonging to the failed transfer, and then restart 1350 * the endpoint. 1351 */ 1352 ohci_soft_td_t *p, *n; 1353 opipe = (struct ohci_pipe *)xfer->pipe; 1354 1355 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1356 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1357 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1358 1359 /* remove TDs */ 1360 for (p = std; p->xfer == xfer; p = n) { 1361 n = p->nexttd; 1362 ohci_free_std(sc, p); 1363 } 1364 1365 /* clear halt */ 1366 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1367 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1368 1369 if (cc == OHCI_CC_STALL) 1370 xfer->status = USBD_STALLED; 1371 else 1372 xfer->status = USBD_IOERROR; 1373 s = splusb(); 1374 usb_transfer_complete(xfer); 1375 splx(s); 1376 } 1377 } 1378 1379 #ifdef OHCI_DEBUG 1380 if (ohcidebug > 10) { 1381 DPRINTF(("ohci_softintr: ITD done:\n")); 1382 ohci_dump_itds(sc, sidone); 1383 } 1384 #endif 1385 1386 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1387 xfer = sitd->xfer; 1388 sitdnext = sitd->dnext; 1389 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1390 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1391 if (xfer == NULL) 1392 continue; 1393 if (xfer->status == USBD_CANCELLED || 1394 xfer->status == USBD_TIMEOUT) { 1395 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1396 xfer)); 1397 /* Handled by abort routine. */ 1398 continue; 1399 } 1400 #ifdef DIAGNOSTIC 1401 if (sitd->isdone) 1402 printf("ohci_softintr: sitd=%p is done\n", sitd); 1403 sitd->isdone = 1; 1404 #endif 1405 if (sitd->flags & OHCI_CALL_DONE) { 1406 ohci_soft_itd_t *next; 1407 1408 opipe = (struct ohci_pipe *)xfer->pipe; 1409 opipe->u.iso.inuse -= xfer->nframes; 1410 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1411 bEndpointAddress); 1412 xfer->status = USBD_NORMAL_COMPLETION; 1413 actlen = 0; 1414 for (i = 0, sitd = xfer->hcpriv;; 1415 sitd = next) { 1416 next = sitd->nextitd; 1417 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1418 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1419 xfer->status = USBD_IOERROR; 1420 /* For input, update frlengths with actual */ 1421 /* XXX anything necessary for output? */ 1422 if (uedir == UE_DIR_IN && 1423 xfer->status == USBD_NORMAL_COMPLETION) { 1424 iframes = OHCI_ITD_GET_FC(O32TOH( 1425 sitd->itd.itd_flags)); 1426 for (j = 0; j < iframes; i++, j++) { 1427 len = O16TOH(sitd-> 1428 itd.itd_offset[j]); 1429 if ((OHCI_ITD_PSW_GET_CC(len) & 1430 OHCI_CC_NOT_ACCESSED_MASK) 1431 == OHCI_CC_NOT_ACCESSED) 1432 len = 0; 1433 else 1434 len = OHCI_ITD_PSW_LENGTH(len); 1435 xfer->frlengths[i] = len; 1436 actlen += len; 1437 } 1438 } 1439 if (sitd->flags & OHCI_CALL_DONE) 1440 break; 1441 ohci_free_sitd(sc, sitd); 1442 } 1443 ohci_free_sitd(sc, sitd); 1444 if (uedir == UE_DIR_IN && 1445 xfer->status == USBD_NORMAL_COMPLETION) 1446 xfer->actlen = actlen; 1447 xfer->hcpriv = NULL; 1448 1449 s = splusb(); 1450 usb_transfer_complete(xfer); 1451 splx(s); 1452 } 1453 } 1454 1455 #ifdef USB_USE_SOFTINTR 1456 if (sc->sc_softwake) { 1457 sc->sc_softwake = 0; 1458 wakeup(&sc->sc_softwake); 1459 } 1460 #endif /* USB_USE_SOFTINTR */ 1461 1462 sc->sc_bus.intr_context--; 1463 DPRINTFN(10,("ohci_softintr: done:\n")); 1464 } 1465 1466 void 1467 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1468 { 1469 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1470 int len = UGETW(xfer->request.wLength); 1471 int isread = (xfer->request.bmRequestType & UT_READ); 1472 1473 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1474 1475 #ifdef DIAGNOSTIC 1476 if (!(xfer->rqflags & URQ_REQUEST)) { 1477 panic("ohci_device_ctrl_done: not a request"); 1478 } 1479 #endif 1480 if (len) 1481 usb_syncmem(&xfer->dmabuf, 0, len, 1482 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1483 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1484 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1485 } 1486 1487 void 1488 ohci_device_intr_done(usbd_xfer_handle xfer) 1489 { 1490 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1491 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1492 ohci_soft_ed_t *sed = opipe->sed; 1493 ohci_soft_td_t *data, *tail; 1494 int isread = 1495 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1496 1497 1498 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1499 xfer, xfer->actlen)); 1500 1501 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1502 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1503 if (xfer->pipe->repeat) { 1504 data = opipe->tail.td; 1505 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1506 if (tail == NULL) { 1507 xfer->status = USBD_NOMEM; 1508 return; 1509 } 1510 tail->xfer = NULL; 1511 1512 data->td.td_flags = HTOO32( 1513 OHCI_TD_IN | OHCI_TD_NOCC | 1514 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1515 if (xfer->flags & USBD_SHORT_XFER_OK) 1516 data->td.td_flags |= HTOO32(OHCI_TD_R); 1517 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1518 data->nexttd = tail; 1519 data->td.td_nexttd = HTOO32(tail->physaddr); 1520 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1521 xfer->length - 1); 1522 data->len = xfer->length; 1523 data->xfer = xfer; 1524 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1525 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1527 xfer->hcpriv = data; 1528 xfer->actlen = 0; 1529 1530 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1531 usb_syncmem(&sed->dma, 1532 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1533 sizeof(sed->ed.ed_tailp), 1534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1535 opipe->tail.td = tail; 1536 } 1537 } 1538 1539 void 1540 ohci_device_bulk_done(usbd_xfer_handle xfer) 1541 { 1542 int isread = 1543 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1544 1545 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1546 xfer, xfer->actlen)); 1547 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1548 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1549 } 1550 1551 void 1552 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1553 { 1554 usbd_pipe_handle pipe; 1555 u_char *p; 1556 int i, m; 1557 int hstatus; 1558 1559 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1560 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1561 sc, xfer, hstatus)); 1562 1563 if (xfer == NULL) { 1564 /* Just ignore the change. */ 1565 return; 1566 } 1567 1568 pipe = xfer->pipe; 1569 1570 p = KERNADDR(&xfer->dmabuf, 0); 1571 m = min(sc->sc_noport, xfer->length * 8 - 1); 1572 memset(p, 0, xfer->length); 1573 for (i = 1; i <= m; i++) { 1574 /* Pick out CHANGE bits from the status reg. */ 1575 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1576 p[i/8] |= 1 << (i%8); 1577 } 1578 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1579 xfer->actlen = xfer->length; 1580 xfer->status = USBD_NORMAL_COMPLETION; 1581 1582 usb_transfer_complete(xfer); 1583 } 1584 1585 void 1586 ohci_root_intr_done(usbd_xfer_handle xfer) 1587 { 1588 } 1589 1590 void 1591 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1592 { 1593 } 1594 1595 /* 1596 * Wait here until controller claims to have an interrupt. 1597 * Then call ohci_intr and return. Use timeout to avoid waiting 1598 * too long. 1599 */ 1600 void 1601 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1602 { 1603 int timo; 1604 u_int32_t intrs; 1605 1606 xfer->status = USBD_IN_PROGRESS; 1607 for (timo = xfer->timeout; timo >= 0; timo--) { 1608 usb_delay_ms(&sc->sc_bus, 1); 1609 if (sc->sc_dying) 1610 break; 1611 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1612 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1613 #ifdef OHCI_DEBUG 1614 if (ohcidebug > 15) 1615 ohci_dumpregs(sc); 1616 #endif 1617 if (intrs) { 1618 ohci_intr1(sc); 1619 if (xfer->status != USBD_IN_PROGRESS) 1620 return; 1621 } 1622 } 1623 1624 /* Timeout */ 1625 DPRINTF(("ohci_waitintr: timeout\n")); 1626 xfer->status = USBD_TIMEOUT; 1627 usb_transfer_complete(xfer); 1628 /* XXX should free TD */ 1629 } 1630 1631 void 1632 ohci_poll(struct usbd_bus *bus) 1633 { 1634 ohci_softc_t *sc = bus->hci_private; 1635 #ifdef OHCI_DEBUG 1636 static int last; 1637 int new; 1638 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1639 if (new != last) { 1640 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1641 last = new; 1642 } 1643 #endif 1644 1645 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1646 ohci_intr1(sc); 1647 } 1648 1649 usbd_status 1650 ohci_device_request(usbd_xfer_handle xfer) 1651 { 1652 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1653 usb_device_request_t *req = &xfer->request; 1654 usbd_device_handle dev = opipe->pipe.device; 1655 ohci_softc_t *sc = dev->bus->hci_private; 1656 int addr = dev->address; 1657 ohci_soft_td_t *setup, *stat, *next, *tail; 1658 ohci_soft_ed_t *sed; 1659 int isread; 1660 int len; 1661 usbd_status err; 1662 int s; 1663 1664 isread = req->bmRequestType & UT_READ; 1665 len = UGETW(req->wLength); 1666 1667 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1668 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1669 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1670 UGETW(req->wIndex), len, addr, 1671 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1672 1673 setup = opipe->tail.td; 1674 stat = ohci_alloc_std(sc); 1675 if (stat == NULL) { 1676 err = USBD_NOMEM; 1677 goto bad1; 1678 } 1679 tail = ohci_alloc_std(sc); 1680 if (tail == NULL) { 1681 err = USBD_NOMEM; 1682 goto bad2; 1683 } 1684 tail->xfer = NULL; 1685 1686 sed = opipe->sed; 1687 opipe->u.ctl.length = len; 1688 1689 /* Update device address and length since they may have changed 1690 during the setup of the control pipe in usbd_new_device(). */ 1691 /* XXX This only needs to be done once, but it's too early in open. */ 1692 /* XXXX Should not touch ED here! */ 1693 1694 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1695 sizeof(sed->ed.ed_flags), 1696 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1697 sed->ed.ed_flags = HTOO32( 1698 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1699 OHCI_ED_SET_FA(addr) | 1700 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1701 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1702 sizeof(sed->ed.ed_flags), 1703 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1704 1705 next = stat; 1706 1707 /* Set up data transaction */ 1708 if (len != 0) { 1709 ohci_soft_td_t *std = stat; 1710 1711 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1712 std, &stat); 1713 stat = stat->nexttd; /* point at free TD */ 1714 if (err) 1715 goto bad3; 1716 /* Start toggle at 1 and then use the carried toggle. */ 1717 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1718 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1719 usb_syncmem(&std->dma, 1720 std->offs + offsetof(ohci_td_t, td_flags), 1721 sizeof(std->td.td_flags), 1722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1723 } 1724 1725 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1726 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1727 1728 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1729 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1730 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1731 setup->nexttd = next; 1732 setup->td.td_nexttd = HTOO32(next->physaddr); 1733 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1734 setup->len = 0; 1735 setup->xfer = xfer; 1736 setup->flags = 0; 1737 xfer->hcpriv = setup; 1738 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1740 1741 stat->td.td_flags = HTOO32( 1742 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1743 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1744 stat->td.td_cbp = 0; 1745 stat->nexttd = tail; 1746 stat->td.td_nexttd = HTOO32(tail->physaddr); 1747 stat->td.td_be = 0; 1748 stat->flags = OHCI_CALL_DONE; 1749 stat->len = 0; 1750 stat->xfer = xfer; 1751 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1753 1754 #ifdef OHCI_DEBUG 1755 if (ohcidebug > 5) { 1756 DPRINTF(("ohci_device_request:\n")); 1757 ohci_dump_ed(sc, sed); 1758 ohci_dump_tds(sc, setup); 1759 } 1760 #endif 1761 1762 /* Insert ED in schedule */ 1763 s = splusb(); 1764 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1765 usb_syncmem(&sed->dma, 1766 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1767 sizeof(sed->ed.ed_tailp), 1768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1769 opipe->tail.td = tail; 1770 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1771 if (xfer->timeout && !sc->sc_bus.use_polling) { 1772 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1773 ohci_timeout, xfer); 1774 } 1775 splx(s); 1776 1777 #ifdef OHCI_DEBUG 1778 if (ohcidebug > 20) { 1779 delay(10000); 1780 DPRINTF(("ohci_device_request: status=%x\n", 1781 OREAD4(sc, OHCI_COMMAND_STATUS))); 1782 ohci_dumpregs(sc); 1783 printf("ctrl head:\n"); 1784 ohci_dump_ed(sc, sc->sc_ctrl_head); 1785 printf("sed:\n"); 1786 ohci_dump_ed(sc, sed); 1787 ohci_dump_tds(sc, setup); 1788 } 1789 #endif 1790 1791 return (USBD_NORMAL_COMPLETION); 1792 1793 bad3: 1794 ohci_free_std(sc, tail); 1795 bad2: 1796 ohci_free_std(sc, stat); 1797 bad1: 1798 return (err); 1799 } 1800 1801 /* 1802 * Add an ED to the schedule. Called at splusb(). 1803 */ 1804 void 1805 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1806 { 1807 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1808 1809 SPLUSBCHECK; 1810 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1811 sizeof(head->ed.ed_nexted), 1812 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1813 sed->next = head->next; 1814 sed->ed.ed_nexted = head->ed.ed_nexted; 1815 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1816 sizeof(sed->ed.ed_nexted), 1817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1818 head->next = sed; 1819 head->ed.ed_nexted = HTOO32(sed->physaddr); 1820 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1821 sizeof(head->ed.ed_nexted), 1822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1823 } 1824 1825 /* 1826 * Remove an ED from the schedule. Called at splusb(). 1827 */ 1828 void 1829 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1830 { 1831 ohci_soft_ed_t *p; 1832 1833 SPLUSBCHECK; 1834 1835 /* XXX */ 1836 for (p = head; p != NULL && p->next != sed; p = p->next) 1837 ; 1838 if (p == NULL) 1839 panic("ohci_rem_ed: ED not found"); 1840 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1841 sizeof(sed->ed.ed_nexted), 1842 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1843 p->next = sed->next; 1844 p->ed.ed_nexted = sed->ed.ed_nexted; 1845 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1846 sizeof(p->ed.ed_nexted), 1847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1848 } 1849 1850 /* 1851 * When a transfer is completed the TD is added to the done queue by 1852 * the host controller. This queue is the processed by software. 1853 * Unfortunately the queue contains the physical address of the TD 1854 * and we have no simple way to translate this back to a kernel address. 1855 * To make the translation possible (and fast) we use a hash table of 1856 * TDs currently in the schedule. The physical address is used as the 1857 * hash value. 1858 */ 1859 1860 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1861 /* Called at splusb() */ 1862 void 1863 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1864 { 1865 int h = HASH(std->physaddr); 1866 1867 SPLUSBCHECK; 1868 1869 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1870 } 1871 1872 /* Called at splusb() */ 1873 void 1874 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1875 { 1876 SPLUSBCHECK; 1877 1878 LIST_REMOVE(std, hnext); 1879 } 1880 1881 ohci_soft_td_t * 1882 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1883 { 1884 int h = HASH(a); 1885 ohci_soft_td_t *std; 1886 1887 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1888 std != NULL; 1889 std = LIST_NEXT(std, hnext)) 1890 if (std->physaddr == a) 1891 return (std); 1892 return (NULL); 1893 } 1894 1895 /* Called at splusb() */ 1896 void 1897 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1898 { 1899 int h = HASH(sitd->physaddr); 1900 1901 SPLUSBCHECK; 1902 1903 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1904 sitd, (u_long)sitd->physaddr)); 1905 1906 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1907 } 1908 1909 /* Called at splusb() */ 1910 void 1911 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1912 { 1913 SPLUSBCHECK; 1914 1915 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1916 sitd, (u_long)sitd->physaddr)); 1917 1918 LIST_REMOVE(sitd, hnext); 1919 } 1920 1921 ohci_soft_itd_t * 1922 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1923 { 1924 int h = HASH(a); 1925 ohci_soft_itd_t *sitd; 1926 1927 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1928 sitd != NULL; 1929 sitd = LIST_NEXT(sitd, hnext)) 1930 if (sitd->physaddr == a) 1931 return (sitd); 1932 return (NULL); 1933 } 1934 1935 void 1936 ohci_timeout(void *addr) 1937 { 1938 struct ohci_xfer *oxfer = addr; 1939 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1940 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1941 1942 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1943 1944 if (sc->sc_dying) { 1945 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1946 return; 1947 } 1948 1949 /* Execute the abort in a process context. */ 1950 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1951 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1952 USB_TASKQ_HC); 1953 } 1954 1955 void 1956 ohci_timeout_task(void *addr) 1957 { 1958 usbd_xfer_handle xfer = addr; 1959 int s; 1960 1961 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1962 1963 s = splusb(); 1964 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1965 splx(s); 1966 } 1967 1968 #ifdef OHCI_DEBUG 1969 void 1970 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1971 { 1972 for (; std; std = std->nexttd) 1973 ohci_dump_td(sc, std); 1974 } 1975 1976 void 1977 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1978 { 1979 char sbuf[128]; 1980 1981 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1982 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1983 snprintb(sbuf, sizeof(sbuf), 1984 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1985 (u_int32_t)O32TOH(std->td.td_flags)); 1986 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1987 "nexttd=0x%08lx be=0x%08lx\n", 1988 std, (u_long)std->physaddr, sbuf, 1989 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 1990 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 1991 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1992 (u_long)O32TOH(std->td.td_cbp), 1993 (u_long)O32TOH(std->td.td_nexttd), 1994 (u_long)O32TOH(std->td.td_be)); 1995 } 1996 1997 void 1998 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1999 { 2000 int i; 2001 2002 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2003 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2004 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2005 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2006 sitd, (u_long)sitd->physaddr, 2007 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2008 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2009 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2010 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2011 (u_long)O32TOH(sitd->itd.itd_bp0), 2012 (u_long)O32TOH(sitd->itd.itd_nextitd), 2013 (u_long)O32TOH(sitd->itd.itd_be)); 2014 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2015 printf("offs[%d]=0x%04x ", i, 2016 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2017 printf("\n"); 2018 } 2019 2020 void 2021 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2022 { 2023 for (; sitd; sitd = sitd->nextitd) 2024 ohci_dump_itd(sc, sitd); 2025 } 2026 2027 void 2028 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2029 { 2030 char sbuf[128], sbuf2[128]; 2031 2032 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2033 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2034 snprintb(sbuf, sizeof(sbuf), 2035 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2036 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2037 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2038 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2039 2040 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2041 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2042 sed, (u_long)sed->physaddr, 2043 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2044 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2045 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2046 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2047 (u_long)O32TOH(sed->ed.ed_headp), 2048 (u_long)O32TOH(sed->ed.ed_nexted)); 2049 } 2050 #endif 2051 2052 usbd_status 2053 ohci_open(usbd_pipe_handle pipe) 2054 { 2055 usbd_device_handle dev = pipe->device; 2056 ohci_softc_t *sc = dev->bus->hci_private; 2057 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2058 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2059 u_int8_t addr = dev->address; 2060 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2061 ohci_soft_ed_t *sed; 2062 ohci_soft_td_t *std; 2063 ohci_soft_itd_t *sitd; 2064 ohci_physaddr_t tdphys; 2065 u_int32_t fmt; 2066 usbd_status err; 2067 int s; 2068 int ival; 2069 2070 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2071 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2072 2073 if (sc->sc_dying) 2074 return (USBD_IOERROR); 2075 2076 std = NULL; 2077 sed = NULL; 2078 2079 if (addr == sc->sc_addr) { 2080 switch (ed->bEndpointAddress) { 2081 case USB_CONTROL_ENDPOINT: 2082 pipe->methods = &ohci_root_ctrl_methods; 2083 break; 2084 case UE_DIR_IN | OHCI_INTR_ENDPT: 2085 pipe->methods = &ohci_root_intr_methods; 2086 break; 2087 default: 2088 return (USBD_INVAL); 2089 } 2090 } else { 2091 sed = ohci_alloc_sed(sc); 2092 if (sed == NULL) 2093 goto bad0; 2094 opipe->sed = sed; 2095 if (xfertype == UE_ISOCHRONOUS) { 2096 sitd = ohci_alloc_sitd(sc); 2097 if (sitd == NULL) 2098 goto bad1; 2099 opipe->tail.itd = sitd; 2100 tdphys = sitd->physaddr; 2101 fmt = OHCI_ED_FORMAT_ISO; 2102 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2103 fmt |= OHCI_ED_DIR_IN; 2104 else 2105 fmt |= OHCI_ED_DIR_OUT; 2106 } else { 2107 std = ohci_alloc_std(sc); 2108 if (std == NULL) 2109 goto bad1; 2110 opipe->tail.td = std; 2111 tdphys = std->physaddr; 2112 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2113 } 2114 sed->ed.ed_flags = HTOO32( 2115 OHCI_ED_SET_FA(addr) | 2116 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2117 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2118 fmt | 2119 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2120 sed->ed.ed_headp = sed->ed.ed_tailp = HTOO32(tdphys); 2121 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2123 2124 switch (xfertype) { 2125 case UE_CONTROL: 2126 pipe->methods = &ohci_device_ctrl_methods; 2127 err = usb_allocmem(&sc->sc_bus, 2128 sizeof(usb_device_request_t), 2129 0, &opipe->u.ctl.reqdma); 2130 if (err) 2131 goto bad; 2132 s = splusb(); 2133 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2134 splx(s); 2135 break; 2136 case UE_INTERRUPT: 2137 pipe->methods = &ohci_device_intr_methods; 2138 ival = pipe->interval; 2139 if (ival == USBD_DEFAULT_INTERVAL) 2140 ival = ed->bInterval; 2141 return (ohci_device_setintr(sc, opipe, ival)); 2142 case UE_ISOCHRONOUS: 2143 pipe->methods = &ohci_device_isoc_methods; 2144 return (ohci_setup_isoc(pipe)); 2145 case UE_BULK: 2146 pipe->methods = &ohci_device_bulk_methods; 2147 s = splusb(); 2148 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2149 splx(s); 2150 break; 2151 } 2152 } 2153 return (USBD_NORMAL_COMPLETION); 2154 2155 bad: 2156 if (std != NULL) 2157 ohci_free_std(sc, std); 2158 bad1: 2159 if (sed != NULL) 2160 ohci_free_sed(sc, sed); 2161 bad0: 2162 return (USBD_NOMEM); 2163 2164 } 2165 2166 /* 2167 * Close a reqular pipe. 2168 * Assumes that there are no pending transactions. 2169 */ 2170 void 2171 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2172 { 2173 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2174 ohci_softc_t *sc = pipe->device->bus->hci_private; 2175 ohci_soft_ed_t *sed = opipe->sed; 2176 int s; 2177 2178 s = splusb(); 2179 #ifdef DIAGNOSTIC 2180 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2181 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2182 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2183 ohci_soft_td_t *std; 2184 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2185 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2186 "tl=0x%x pipe=%p, std=%p\n", sed, 2187 (int)O32TOH(sed->ed.ed_headp), 2188 (int)O32TOH(sed->ed.ed_tailp), 2189 pipe, std); 2190 #ifdef USB_DEBUG 2191 usbd_dump_pipe(&opipe->pipe); 2192 #endif 2193 #ifdef OHCI_DEBUG 2194 ohci_dump_ed(sc, sed); 2195 if (std) 2196 ohci_dump_td(sc, std); 2197 #endif 2198 usb_delay_ms(&sc->sc_bus, 2); 2199 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2200 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2201 printf("ohci_close_pipe: pipe still not empty\n"); 2202 } 2203 #endif 2204 ohci_rem_ed(sed, head); 2205 /* Make sure the host controller is not touching this ED */ 2206 usb_delay_ms(&sc->sc_bus, 1); 2207 splx(s); 2208 ohci_free_sed(sc, opipe->sed); 2209 } 2210 2211 /* 2212 * Abort a device request. 2213 * If this routine is called at splusb() it guarantees that the request 2214 * will be removed from the hardware scheduling and that the callback 2215 * for it will be called with USBD_CANCELLED status. 2216 * It's impossible to guarantee that the requested transfer will not 2217 * have happened since the hardware runs concurrently. 2218 * If the transaction has already happened we rely on the ordinary 2219 * interrupt processing to process it. 2220 */ 2221 void 2222 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2223 { 2224 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2225 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2226 ohci_soft_ed_t *sed = opipe->sed; 2227 ohci_soft_td_t *p, *n; 2228 ohci_physaddr_t headp; 2229 int s, hit; 2230 int wake; 2231 2232 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2233 2234 if (sc->sc_dying) { 2235 /* If we're dying, just do the software part. */ 2236 s = splusb(); 2237 xfer->status = status; /* make software ignore it */ 2238 callout_stop(&xfer->timeout_handle); 2239 usb_transfer_complete(xfer); 2240 splx(s); 2241 return; 2242 } 2243 2244 if (xfer->device->bus->intr_context || !curproc) 2245 panic("ohci_abort_xfer: not in process context"); 2246 2247 /* 2248 * If an abort is already in progress then just wait for it to 2249 * complete and return. 2250 */ 2251 if (xfer->hcflags & UXFER_ABORTING) { 2252 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2253 #ifdef DIAGNOSTIC 2254 if (status == USBD_TIMEOUT) 2255 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2256 #endif 2257 /* Override the status which might be USBD_TIMEOUT. */ 2258 xfer->status = status; 2259 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2260 xfer->hcflags |= UXFER_ABORTWAIT; 2261 while (xfer->hcflags & UXFER_ABORTING) 2262 tsleep(&xfer->hcflags, PZERO, "ohciaw", 0); 2263 return; 2264 } 2265 xfer->hcflags |= UXFER_ABORTING; 2266 2267 /* 2268 * Step 1: Make interrupt routine and hardware ignore xfer. 2269 */ 2270 s = splusb(); 2271 xfer->status = status; /* make software ignore it */ 2272 callout_stop(&xfer->timeout_handle); 2273 splx(s); 2274 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2275 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2276 sizeof(sed->ed.ed_flags), 2277 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2278 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2279 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2280 sizeof(sed->ed.ed_flags), 2281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2282 2283 /* 2284 * Step 2: Wait until we know hardware has finished any possible 2285 * use of the xfer. Also make sure the soft interrupt routine 2286 * has run. 2287 */ 2288 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2289 s = splusb(); 2290 #ifdef USB_USE_SOFTINTR 2291 sc->sc_softwake = 1; 2292 #endif /* USB_USE_SOFTINTR */ 2293 usb_schedsoftintr(&sc->sc_bus); 2294 #ifdef USB_USE_SOFTINTR 2295 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2296 #endif /* USB_USE_SOFTINTR */ 2297 splx(s); 2298 2299 /* 2300 * Step 3: Remove any vestiges of the xfer from the hardware. 2301 * The complication here is that the hardware may have executed 2302 * beyond the xfer we're trying to abort. So as we're scanning 2303 * the TDs of this xfer we check if the hardware points to 2304 * any of them. 2305 */ 2306 s = splusb(); /* XXX why? */ 2307 p = xfer->hcpriv; 2308 #ifdef DIAGNOSTIC 2309 if (p == NULL) { 2310 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2311 splx(s); 2312 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2313 return; 2314 } 2315 #endif 2316 #ifdef OHCI_DEBUG 2317 if (ohcidebug > 1) { 2318 DPRINTF(("ohci_abort_xfer: sed=\n")); 2319 ohci_dump_ed(sc, sed); 2320 ohci_dump_tds(sc, p); 2321 } 2322 #endif 2323 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2324 hit = 0; 2325 for (; p->xfer == xfer; p = n) { 2326 hit |= headp == p->physaddr; 2327 n = p->nexttd; 2328 ohci_free_std(sc, p); 2329 } 2330 /* Zap headp register if hardware pointed inside the xfer. */ 2331 if (hit) { 2332 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2333 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2334 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2335 usb_syncmem(&sed->dma, 2336 sed->offs + offsetof(ohci_ed_t, ed_headp), 2337 sizeof(sed->ed.ed_headp), 2338 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2339 } else { 2340 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2341 } 2342 2343 /* 2344 * Step 4: Turn on hardware again. 2345 */ 2346 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2347 sizeof(sed->ed.ed_flags), 2348 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2349 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2350 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2351 sizeof(sed->ed.ed_flags), 2352 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2353 2354 /* 2355 * Step 5: Execute callback. 2356 */ 2357 wake = xfer->hcflags & UXFER_ABORTWAIT; 2358 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2359 usb_transfer_complete(xfer); 2360 if (wake) 2361 wakeup(&xfer->hcflags); 2362 2363 splx(s); 2364 } 2365 2366 /* 2367 * Data structures and routines to emulate the root hub. 2368 */ 2369 Static usb_device_descriptor_t ohci_devd = { 2370 USB_DEVICE_DESCRIPTOR_SIZE, 2371 UDESC_DEVICE, /* type */ 2372 {0x00, 0x01}, /* USB version */ 2373 UDCLASS_HUB, /* class */ 2374 UDSUBCLASS_HUB, /* subclass */ 2375 UDPROTO_FSHUB, /* protocol */ 2376 64, /* max packet */ 2377 {0},{0},{0x00,0x01}, /* device id */ 2378 1,2,0, /* string indicies */ 2379 1 /* # of configurations */ 2380 }; 2381 2382 Static const usb_config_descriptor_t ohci_confd = { 2383 USB_CONFIG_DESCRIPTOR_SIZE, 2384 UDESC_CONFIG, 2385 {USB_CONFIG_DESCRIPTOR_SIZE + 2386 USB_INTERFACE_DESCRIPTOR_SIZE + 2387 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2388 1, 2389 1, 2390 0, 2391 UC_ATTR_MBO | UC_SELF_POWERED, 2392 0 /* max power */ 2393 }; 2394 2395 Static const usb_interface_descriptor_t ohci_ifcd = { 2396 USB_INTERFACE_DESCRIPTOR_SIZE, 2397 UDESC_INTERFACE, 2398 0, 2399 0, 2400 1, 2401 UICLASS_HUB, 2402 UISUBCLASS_HUB, 2403 UIPROTO_FSHUB, 2404 0 2405 }; 2406 2407 Static const usb_endpoint_descriptor_t ohci_endpd = { 2408 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2409 .bDescriptorType = UDESC_ENDPOINT, 2410 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2411 .bmAttributes = UE_INTERRUPT, 2412 .wMaxPacketSize = {8, 0}, /* max packet */ 2413 .bInterval = 255, 2414 }; 2415 2416 Static const usb_hub_descriptor_t ohci_hubd = { 2417 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2418 .bDescriptorType = UDESC_HUB, 2419 }; 2420 2421 /* 2422 * Simulate a hardware hub by handling all the necessary requests. 2423 */ 2424 Static usbd_status 2425 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2426 { 2427 usbd_status err; 2428 2429 /* Insert last in queue. */ 2430 err = usb_insert_transfer(xfer); 2431 if (err) 2432 return (err); 2433 2434 /* Pipe isn't running, start first */ 2435 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2436 } 2437 2438 Static usbd_status 2439 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2440 { 2441 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2442 usb_device_request_t *req; 2443 void *buf = NULL; 2444 int port, i; 2445 int s, len, value, index, l, totlen = 0; 2446 usb_port_status_t ps; 2447 usb_hub_descriptor_t hubd; 2448 usbd_status err; 2449 u_int32_t v; 2450 2451 if (sc->sc_dying) 2452 return (USBD_IOERROR); 2453 2454 #ifdef DIAGNOSTIC 2455 if (!(xfer->rqflags & URQ_REQUEST)) 2456 /* XXX panic */ 2457 return (USBD_INVAL); 2458 #endif 2459 req = &xfer->request; 2460 2461 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2462 req->bmRequestType, req->bRequest)); 2463 2464 len = UGETW(req->wLength); 2465 value = UGETW(req->wValue); 2466 index = UGETW(req->wIndex); 2467 2468 if (len != 0) 2469 buf = KERNADDR(&xfer->dmabuf, 0); 2470 2471 #define C(x,y) ((x) | ((y) << 8)) 2472 switch(C(req->bRequest, req->bmRequestType)) { 2473 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2474 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2475 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2476 /* 2477 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2478 * for the integrated root hub. 2479 */ 2480 break; 2481 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2482 if (len > 0) { 2483 *(u_int8_t *)buf = sc->sc_conf; 2484 totlen = 1; 2485 } 2486 break; 2487 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2488 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2489 if (len == 0) 2490 break; 2491 switch(value >> 8) { 2492 case UDESC_DEVICE: 2493 if ((value & 0xff) != 0) { 2494 err = USBD_IOERROR; 2495 goto ret; 2496 } 2497 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2498 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2499 memcpy(buf, &ohci_devd, l); 2500 break; 2501 case UDESC_CONFIG: 2502 if ((value & 0xff) != 0) { 2503 err = USBD_IOERROR; 2504 goto ret; 2505 } 2506 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2507 memcpy(buf, &ohci_confd, l); 2508 buf = (char *)buf + l; 2509 len -= l; 2510 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2511 totlen += l; 2512 memcpy(buf, &ohci_ifcd, l); 2513 buf = (char *)buf + l; 2514 len -= l; 2515 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2516 totlen += l; 2517 memcpy(buf, &ohci_endpd, l); 2518 break; 2519 case UDESC_STRING: 2520 #define sd ((usb_string_descriptor_t *)buf) 2521 switch (value & 0xff) { 2522 case 0: /* Language table */ 2523 totlen = usb_makelangtbl(sd, len); 2524 break; 2525 case 1: /* Vendor */ 2526 totlen = usb_makestrdesc(sd, len, 2527 sc->sc_vendor); 2528 break; 2529 case 2: /* Product */ 2530 totlen = usb_makestrdesc(sd, len, 2531 "OHCI root hub"); 2532 break; 2533 } 2534 #undef sd 2535 break; 2536 default: 2537 err = USBD_IOERROR; 2538 goto ret; 2539 } 2540 break; 2541 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2542 if (len > 0) { 2543 *(u_int8_t *)buf = 0; 2544 totlen = 1; 2545 } 2546 break; 2547 case C(UR_GET_STATUS, UT_READ_DEVICE): 2548 if (len > 1) { 2549 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2550 totlen = 2; 2551 } 2552 break; 2553 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2554 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2555 if (len > 1) { 2556 USETW(((usb_status_t *)buf)->wStatus, 0); 2557 totlen = 2; 2558 } 2559 break; 2560 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2561 if (value >= USB_MAX_DEVICES) { 2562 err = USBD_IOERROR; 2563 goto ret; 2564 } 2565 sc->sc_addr = value; 2566 break; 2567 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2568 if (value != 0 && value != 1) { 2569 err = USBD_IOERROR; 2570 goto ret; 2571 } 2572 sc->sc_conf = value; 2573 break; 2574 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2575 break; 2576 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2577 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2578 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2579 err = USBD_IOERROR; 2580 goto ret; 2581 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2582 break; 2583 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2584 break; 2585 /* Hub requests */ 2586 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2587 break; 2588 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2589 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2590 "port=%d feature=%d\n", 2591 index, value)); 2592 if (index < 1 || index > sc->sc_noport) { 2593 err = USBD_IOERROR; 2594 goto ret; 2595 } 2596 port = OHCI_RH_PORT_STATUS(index); 2597 switch(value) { 2598 case UHF_PORT_ENABLE: 2599 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2600 break; 2601 case UHF_PORT_SUSPEND: 2602 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2603 break; 2604 case UHF_PORT_POWER: 2605 /* Yes, writing to the LOW_SPEED bit clears power. */ 2606 OWRITE4(sc, port, UPS_LOW_SPEED); 2607 break; 2608 case UHF_C_PORT_CONNECTION: 2609 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2610 break; 2611 case UHF_C_PORT_ENABLE: 2612 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2613 break; 2614 case UHF_C_PORT_SUSPEND: 2615 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2616 break; 2617 case UHF_C_PORT_OVER_CURRENT: 2618 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2619 break; 2620 case UHF_C_PORT_RESET: 2621 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2622 break; 2623 default: 2624 err = USBD_IOERROR; 2625 goto ret; 2626 } 2627 switch(value) { 2628 case UHF_C_PORT_CONNECTION: 2629 case UHF_C_PORT_ENABLE: 2630 case UHF_C_PORT_SUSPEND: 2631 case UHF_C_PORT_OVER_CURRENT: 2632 case UHF_C_PORT_RESET: 2633 /* Enable RHSC interrupt if condition is cleared. */ 2634 if ((OREAD4(sc, port) >> 16) == 0) 2635 ohci_rhsc_enable(sc); 2636 break; 2637 default: 2638 break; 2639 } 2640 break; 2641 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2642 if (len == 0) 2643 break; 2644 if ((value & 0xff) != 0) { 2645 err = USBD_IOERROR; 2646 goto ret; 2647 } 2648 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2649 hubd = ohci_hubd; 2650 hubd.bNbrPorts = sc->sc_noport; 2651 USETW(hubd.wHubCharacteristics, 2652 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2653 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2654 /* XXX overcurrent */ 2655 ); 2656 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2657 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2658 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2659 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2660 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2661 l = min(len, hubd.bDescLength); 2662 totlen = l; 2663 memcpy(buf, &hubd, l); 2664 break; 2665 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2666 if (len != 4) { 2667 err = USBD_IOERROR; 2668 goto ret; 2669 } 2670 memset(buf, 0, len); /* ? XXX */ 2671 totlen = len; 2672 break; 2673 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2674 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2675 index)); 2676 if (index < 1 || index > sc->sc_noport) { 2677 err = USBD_IOERROR; 2678 goto ret; 2679 } 2680 if (len != 4) { 2681 err = USBD_IOERROR; 2682 goto ret; 2683 } 2684 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2685 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2686 v)); 2687 USETW(ps.wPortStatus, v); 2688 USETW(ps.wPortChange, v >> 16); 2689 l = min(len, sizeof ps); 2690 memcpy(buf, &ps, l); 2691 totlen = l; 2692 break; 2693 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2694 err = USBD_IOERROR; 2695 goto ret; 2696 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2697 break; 2698 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2699 if (index < 1 || index > sc->sc_noport) { 2700 err = USBD_IOERROR; 2701 goto ret; 2702 } 2703 port = OHCI_RH_PORT_STATUS(index); 2704 switch(value) { 2705 case UHF_PORT_ENABLE: 2706 OWRITE4(sc, port, UPS_PORT_ENABLED); 2707 break; 2708 case UHF_PORT_SUSPEND: 2709 OWRITE4(sc, port, UPS_SUSPEND); 2710 break; 2711 case UHF_PORT_RESET: 2712 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2713 index)); 2714 OWRITE4(sc, port, UPS_RESET); 2715 for (i = 0; i < 5; i++) { 2716 usb_delay_ms(&sc->sc_bus, 2717 USB_PORT_ROOT_RESET_DELAY); 2718 if (sc->sc_dying) { 2719 err = USBD_IOERROR; 2720 goto ret; 2721 } 2722 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2723 break; 2724 } 2725 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2726 index, OREAD4(sc, port))); 2727 break; 2728 case UHF_PORT_POWER: 2729 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2730 "%d\n", index)); 2731 OWRITE4(sc, port, UPS_PORT_POWER); 2732 break; 2733 default: 2734 err = USBD_IOERROR; 2735 goto ret; 2736 } 2737 break; 2738 default: 2739 err = USBD_IOERROR; 2740 goto ret; 2741 } 2742 xfer->actlen = totlen; 2743 err = USBD_NORMAL_COMPLETION; 2744 ret: 2745 xfer->status = err; 2746 s = splusb(); 2747 usb_transfer_complete(xfer); 2748 splx(s); 2749 return (USBD_IN_PROGRESS); 2750 } 2751 2752 /* Abort a root control request. */ 2753 Static void 2754 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2755 { 2756 /* Nothing to do, all transfers are synchronous. */ 2757 } 2758 2759 /* Close the root pipe. */ 2760 Static void 2761 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2762 { 2763 DPRINTF(("ohci_root_ctrl_close\n")); 2764 /* Nothing to do. */ 2765 } 2766 2767 Static usbd_status 2768 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2769 { 2770 usbd_status err; 2771 2772 /* Insert last in queue. */ 2773 err = usb_insert_transfer(xfer); 2774 if (err) 2775 return (err); 2776 2777 /* Pipe isn't running, start first */ 2778 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2779 } 2780 2781 Static usbd_status 2782 ohci_root_intr_start(usbd_xfer_handle xfer) 2783 { 2784 usbd_pipe_handle pipe = xfer->pipe; 2785 ohci_softc_t *sc = pipe->device->bus->hci_private; 2786 2787 if (sc->sc_dying) 2788 return (USBD_IOERROR); 2789 2790 sc->sc_intrxfer = xfer; 2791 2792 return (USBD_IN_PROGRESS); 2793 } 2794 2795 /* Abort a root interrupt request. */ 2796 Static void 2797 ohci_root_intr_abort(usbd_xfer_handle xfer) 2798 { 2799 int s; 2800 2801 if (xfer->pipe->intrxfer == xfer) { 2802 DPRINTF(("ohci_root_intr_abort: remove\n")); 2803 xfer->pipe->intrxfer = NULL; 2804 } 2805 xfer->status = USBD_CANCELLED; 2806 s = splusb(); 2807 usb_transfer_complete(xfer); 2808 splx(s); 2809 } 2810 2811 /* Close the root pipe. */ 2812 Static void 2813 ohci_root_intr_close(usbd_pipe_handle pipe) 2814 { 2815 ohci_softc_t *sc = pipe->device->bus->hci_private; 2816 2817 DPRINTF(("ohci_root_intr_close\n")); 2818 2819 sc->sc_intrxfer = NULL; 2820 } 2821 2822 /************************/ 2823 2824 Static usbd_status 2825 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2826 { 2827 usbd_status err; 2828 2829 /* Insert last in queue. */ 2830 err = usb_insert_transfer(xfer); 2831 if (err) 2832 return (err); 2833 2834 /* Pipe isn't running, start first */ 2835 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2836 } 2837 2838 Static usbd_status 2839 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2840 { 2841 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2842 usbd_status err; 2843 2844 if (sc->sc_dying) 2845 return (USBD_IOERROR); 2846 2847 #ifdef DIAGNOSTIC 2848 if (!(xfer->rqflags & URQ_REQUEST)) { 2849 /* XXX panic */ 2850 printf("ohci_device_ctrl_transfer: not a request\n"); 2851 return (USBD_INVAL); 2852 } 2853 #endif 2854 2855 err = ohci_device_request(xfer); 2856 if (err) 2857 return (err); 2858 2859 if (sc->sc_bus.use_polling) 2860 ohci_waitintr(sc, xfer); 2861 return (USBD_IN_PROGRESS); 2862 } 2863 2864 /* Abort a device control request. */ 2865 Static void 2866 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2867 { 2868 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2869 ohci_abort_xfer(xfer, USBD_CANCELLED); 2870 } 2871 2872 /* Close a device control pipe. */ 2873 Static void 2874 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2875 { 2876 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2877 ohci_softc_t *sc = pipe->device->bus->hci_private; 2878 2879 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2880 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2881 ohci_free_std(sc, opipe->tail.td); 2882 } 2883 2884 /************************/ 2885 2886 Static void 2887 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2888 { 2889 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2890 ohci_softc_t *sc = pipe->device->bus->hci_private; 2891 2892 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2893 } 2894 2895 Static void 2896 ohci_noop(usbd_pipe_handle pipe) 2897 { 2898 } 2899 2900 Static usbd_status 2901 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2902 { 2903 usbd_status err; 2904 2905 /* Insert last in queue. */ 2906 err = usb_insert_transfer(xfer); 2907 if (err) 2908 return (err); 2909 2910 /* Pipe isn't running, start first */ 2911 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2912 } 2913 2914 Static usbd_status 2915 ohci_device_bulk_start(usbd_xfer_handle xfer) 2916 { 2917 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2918 usbd_device_handle dev = opipe->pipe.device; 2919 ohci_softc_t *sc = dev->bus->hci_private; 2920 int addr = dev->address; 2921 ohci_soft_td_t *data, *tail, *tdp; 2922 ohci_soft_ed_t *sed; 2923 int s, len, isread, endpt; 2924 usbd_status err; 2925 2926 if (sc->sc_dying) 2927 return (USBD_IOERROR); 2928 2929 #ifdef DIAGNOSTIC 2930 if (xfer->rqflags & URQ_REQUEST) { 2931 /* XXX panic */ 2932 printf("ohci_device_bulk_start: a request\n"); 2933 return (USBD_INVAL); 2934 } 2935 #endif 2936 2937 len = xfer->length; 2938 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2939 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2940 sed = opipe->sed; 2941 2942 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2943 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2944 endpt)); 2945 2946 opipe->u.bulk.isread = isread; 2947 opipe->u.bulk.length = len; 2948 2949 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2950 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2951 /* Update device address */ 2952 sed->ed.ed_flags = HTOO32( 2953 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2954 OHCI_ED_SET_FA(addr)); 2955 2956 /* Allocate a chain of new TDs (including a new tail). */ 2957 data = opipe->tail.td; 2958 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2959 data, &tail); 2960 /* We want interrupt at the end of the transfer. */ 2961 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2962 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2963 tail->flags |= OHCI_CALL_DONE; 2964 tail = tail->nexttd; /* point at sentinel */ 2965 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2966 sizeof(tail->td.td_flags), 2967 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2968 if (err) 2969 return (err); 2970 2971 tail->xfer = NULL; 2972 xfer->hcpriv = data; 2973 2974 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2975 "td_cbp=0x%08x td_be=0x%08x\n", 2976 (int)O32TOH(sed->ed.ed_flags), 2977 (int)O32TOH(data->td.td_flags), 2978 (int)O32TOH(data->td.td_cbp), 2979 (int)O32TOH(data->td.td_be))); 2980 2981 #ifdef OHCI_DEBUG 2982 if (ohcidebug > 5) { 2983 ohci_dump_ed(sc, sed); 2984 ohci_dump_tds(sc, data); 2985 } 2986 #endif 2987 2988 /* Insert ED in schedule */ 2989 s = splusb(); 2990 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2991 tdp->xfer = xfer; 2992 } 2993 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2994 opipe->tail.td = tail; 2995 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2996 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2999 if (xfer->timeout && !sc->sc_bus.use_polling) { 3000 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3001 ohci_timeout, xfer); 3002 } 3003 3004 #if 0 3005 /* This goes wrong if we are too slow. */ 3006 if (ohcidebug > 10) { 3007 delay(10000); 3008 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3009 OREAD4(sc, OHCI_COMMAND_STATUS))); 3010 ohci_dump_ed(sc, sed); 3011 ohci_dump_tds(sc, data); 3012 } 3013 #endif 3014 3015 splx(s); 3016 3017 return (USBD_IN_PROGRESS); 3018 } 3019 3020 Static void 3021 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3022 { 3023 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3024 ohci_abort_xfer(xfer, USBD_CANCELLED); 3025 } 3026 3027 /* 3028 * Close a device bulk pipe. 3029 */ 3030 Static void 3031 ohci_device_bulk_close(usbd_pipe_handle pipe) 3032 { 3033 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3034 ohci_softc_t *sc = pipe->device->bus->hci_private; 3035 3036 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3037 ohci_close_pipe(pipe, sc->sc_bulk_head); 3038 ohci_free_std(sc, opipe->tail.td); 3039 } 3040 3041 /************************/ 3042 3043 Static usbd_status 3044 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3045 { 3046 usbd_status err; 3047 3048 /* Insert last in queue. */ 3049 err = usb_insert_transfer(xfer); 3050 if (err) 3051 return (err); 3052 3053 /* Pipe isn't running, start first */ 3054 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3055 } 3056 3057 Static usbd_status 3058 ohci_device_intr_start(usbd_xfer_handle xfer) 3059 { 3060 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3061 usbd_device_handle dev = opipe->pipe.device; 3062 ohci_softc_t *sc = dev->bus->hci_private; 3063 ohci_soft_ed_t *sed = opipe->sed; 3064 ohci_soft_td_t *data, *tail; 3065 int s, len, isread, endpt; 3066 3067 if (sc->sc_dying) 3068 return (USBD_IOERROR); 3069 3070 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3071 "flags=%d priv=%p\n", 3072 xfer, xfer->length, xfer->flags, xfer->priv)); 3073 3074 #ifdef DIAGNOSTIC 3075 if (xfer->rqflags & URQ_REQUEST) 3076 panic("ohci_device_intr_transfer: a request"); 3077 #endif 3078 3079 len = xfer->length; 3080 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3081 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3082 3083 data = opipe->tail.td; 3084 tail = ohci_alloc_std(sc); 3085 if (tail == NULL) 3086 return (USBD_NOMEM); 3087 tail->xfer = NULL; 3088 3089 data->td.td_flags = HTOO32( 3090 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3091 OHCI_TD_NOCC | 3092 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3093 if (xfer->flags & USBD_SHORT_XFER_OK) 3094 data->td.td_flags |= HTOO32(OHCI_TD_R); 3095 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3096 data->nexttd = tail; 3097 data->td.td_nexttd = HTOO32(tail->physaddr); 3098 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3099 data->len = len; 3100 data->xfer = xfer; 3101 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3102 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3104 xfer->hcpriv = data; 3105 3106 #ifdef OHCI_DEBUG 3107 if (ohcidebug > 5) { 3108 DPRINTF(("ohci_device_intr_transfer:\n")); 3109 ohci_dump_ed(sc, sed); 3110 ohci_dump_tds(sc, data); 3111 } 3112 #endif 3113 3114 /* Insert ED in schedule */ 3115 s = splusb(); 3116 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3117 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3118 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3119 opipe->tail.td = tail; 3120 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3121 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3123 3124 #if 0 3125 /* 3126 * This goes horribly wrong, printing thousands of descriptors, 3127 * because false references are followed due to the fact that the 3128 * TD is gone. 3129 */ 3130 if (ohcidebug > 5) { 3131 usb_delay_ms(&sc->sc_bus, 5); 3132 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3133 OREAD4(sc, OHCI_COMMAND_STATUS))); 3134 ohci_dump_ed(sc, sed); 3135 ohci_dump_tds(sc, data); 3136 } 3137 #endif 3138 splx(s); 3139 3140 return (USBD_IN_PROGRESS); 3141 } 3142 3143 /* Abort a device control request. */ 3144 Static void 3145 ohci_device_intr_abort(usbd_xfer_handle xfer) 3146 { 3147 if (xfer->pipe->intrxfer == xfer) { 3148 DPRINTF(("ohci_device_intr_abort: remove\n")); 3149 xfer->pipe->intrxfer = NULL; 3150 } 3151 ohci_abort_xfer(xfer, USBD_CANCELLED); 3152 } 3153 3154 /* Close a device interrupt pipe. */ 3155 Static void 3156 ohci_device_intr_close(usbd_pipe_handle pipe) 3157 { 3158 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3159 ohci_softc_t *sc = pipe->device->bus->hci_private; 3160 int nslots = opipe->u.intr.nslots; 3161 int pos = opipe->u.intr.pos; 3162 int j; 3163 ohci_soft_ed_t *p, *sed = opipe->sed; 3164 int s; 3165 3166 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3167 pipe, nslots, pos)); 3168 s = splusb(); 3169 usb_syncmem(&sed->dma, sed->offs, 3170 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3171 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3172 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3173 sizeof(sed->ed.ed_flags), 3174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3175 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3176 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3177 usb_delay_ms(&sc->sc_bus, 2); 3178 3179 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3180 continue; 3181 #ifdef DIAGNOSTIC 3182 if (p == NULL) 3183 panic("ohci_device_intr_close: ED not found"); 3184 #endif 3185 p->next = sed->next; 3186 p->ed.ed_nexted = sed->ed.ed_nexted; 3187 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3188 sizeof(p->ed.ed_nexted), 3189 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3190 splx(s); 3191 3192 for (j = 0; j < nslots; j++) 3193 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3194 3195 ohci_free_std(sc, opipe->tail.td); 3196 ohci_free_sed(sc, opipe->sed); 3197 } 3198 3199 Static usbd_status 3200 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3201 { 3202 int i, j, s, best; 3203 u_int npoll, slow, shigh, nslots; 3204 u_int bestbw, bw; 3205 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3206 3207 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3208 if (ival == 0) { 3209 printf("ohci_setintr: 0 interval\n"); 3210 return (USBD_INVAL); 3211 } 3212 3213 npoll = OHCI_NO_INTRS; 3214 while (npoll > ival) 3215 npoll /= 2; 3216 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3217 3218 /* 3219 * We now know which level in the tree the ED must go into. 3220 * Figure out which slot has most bandwidth left over. 3221 * Slots to examine: 3222 * npoll 3223 * 1 0 3224 * 2 1 2 3225 * 4 3 4 5 6 3226 * 8 7 8 9 10 11 12 13 14 3227 * N (N-1) .. (N-1+N-1) 3228 */ 3229 slow = npoll-1; 3230 shigh = slow + npoll; 3231 nslots = OHCI_NO_INTRS / npoll; 3232 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3233 bw = 0; 3234 for (j = 0; j < nslots; j++) 3235 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3236 if (bw < bestbw) { 3237 best = i; 3238 bestbw = bw; 3239 } 3240 } 3241 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3242 best, slow, shigh, bestbw)); 3243 3244 s = splusb(); 3245 hsed = sc->sc_eds[best]; 3246 sed->next = hsed->next; 3247 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3248 sizeof(hsed->ed.ed_flags), 3249 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3250 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3251 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3252 sizeof(sed->ed.ed_flags), 3253 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3254 hsed->next = sed; 3255 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3256 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3257 sizeof(hsed->ed.ed_flags), 3258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3259 splx(s); 3260 3261 for (j = 0; j < nslots; j++) 3262 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3263 opipe->u.intr.nslots = nslots; 3264 opipe->u.intr.pos = best; 3265 3266 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3267 return (USBD_NORMAL_COMPLETION); 3268 } 3269 3270 /***********************/ 3271 3272 usbd_status 3273 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3274 { 3275 usbd_status err; 3276 3277 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3278 3279 /* Put it on our queue, */ 3280 err = usb_insert_transfer(xfer); 3281 3282 /* bail out on error, */ 3283 if (err && err != USBD_IN_PROGRESS) 3284 return (err); 3285 3286 /* XXX should check inuse here */ 3287 3288 /* insert into schedule, */ 3289 ohci_device_isoc_enter(xfer); 3290 3291 /* and start if the pipe wasn't running */ 3292 if (!err) 3293 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3294 3295 return (err); 3296 } 3297 3298 void 3299 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3300 { 3301 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3302 usbd_device_handle dev = opipe->pipe.device; 3303 ohci_softc_t *sc = dev->bus->hci_private; 3304 ohci_soft_ed_t *sed = opipe->sed; 3305 struct iso *iso = &opipe->u.iso; 3306 ohci_soft_itd_t *sitd, *nsitd; 3307 ohci_physaddr_t buf, offs, noffs, bp0; 3308 int i, ncur, nframes; 3309 int s; 3310 3311 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3312 "nframes=%d\n", 3313 iso->inuse, iso->next, xfer, xfer->nframes)); 3314 3315 if (sc->sc_dying) 3316 return; 3317 3318 if (iso->next == -1) { 3319 /* Not in use yet, schedule it a few frames ahead. */ 3320 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3321 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3322 iso->next)); 3323 } 3324 3325 sitd = opipe->tail.itd; 3326 buf = DMAADDR(&xfer->dmabuf, 0); 3327 bp0 = OHCI_PAGE(buf); 3328 offs = OHCI_PAGE_OFFSET(buf); 3329 nframes = xfer->nframes; 3330 xfer->hcpriv = sitd; 3331 for (i = ncur = 0; i < nframes; i++, ncur++) { 3332 noffs = offs + xfer->frlengths[i]; 3333 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3334 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3335 3336 /* Allocate next ITD */ 3337 nsitd = ohci_alloc_sitd(sc); 3338 if (nsitd == NULL) { 3339 /* XXX what now? */ 3340 printf("%s: isoc TD alloc failed\n", 3341 device_xname(sc->sc_dev)); 3342 return; 3343 } 3344 3345 /* Fill current ITD */ 3346 sitd->itd.itd_flags = HTOO32( 3347 OHCI_ITD_NOCC | 3348 OHCI_ITD_SET_SF(iso->next) | 3349 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3350 OHCI_ITD_SET_FC(ncur)); 3351 sitd->itd.itd_bp0 = HTOO32(bp0); 3352 sitd->nextitd = nsitd; 3353 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3354 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3355 sitd->xfer = xfer; 3356 sitd->flags = 0; 3357 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 3360 sitd = nsitd; 3361 iso->next = iso->next + ncur; 3362 bp0 = OHCI_PAGE(buf + offs); 3363 ncur = 0; 3364 } 3365 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3366 offs = noffs; 3367 } 3368 nsitd = ohci_alloc_sitd(sc); 3369 if (nsitd == NULL) { 3370 /* XXX what now? */ 3371 printf("%s: isoc TD alloc failed\n", 3372 device_xname(sc->sc_dev)); 3373 return; 3374 } 3375 /* Fixup last used ITD */ 3376 sitd->itd.itd_flags = HTOO32( 3377 OHCI_ITD_NOCC | 3378 OHCI_ITD_SET_SF(iso->next) | 3379 OHCI_ITD_SET_DI(0) | 3380 OHCI_ITD_SET_FC(ncur)); 3381 sitd->itd.itd_bp0 = HTOO32(bp0); 3382 sitd->nextitd = nsitd; 3383 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3384 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3385 sitd->xfer = xfer; 3386 sitd->flags = OHCI_CALL_DONE; 3387 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3388 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3389 3390 iso->next = iso->next + ncur; 3391 iso->inuse += nframes; 3392 3393 xfer->actlen = offs; /* XXX pretend we did it all */ 3394 3395 xfer->status = USBD_IN_PROGRESS; 3396 3397 #ifdef OHCI_DEBUG 3398 if (ohcidebug > 5) { 3399 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3400 O32TOH(sc->sc_hcca->hcca_frame_number))); 3401 ohci_dump_itds(sc, xfer->hcpriv); 3402 ohci_dump_ed(sc, sed); 3403 } 3404 #endif 3405 3406 s = splusb(); 3407 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3408 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3409 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3410 opipe->tail.itd = nsitd; 3411 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3412 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3413 sizeof(sed->ed.ed_flags), 3414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3415 splx(s); 3416 3417 #ifdef OHCI_DEBUG 3418 if (ohcidebug > 5) { 3419 delay(150000); 3420 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3421 O32TOH(sc->sc_hcca->hcca_frame_number))); 3422 ohci_dump_itds(sc, xfer->hcpriv); 3423 ohci_dump_ed(sc, sed); 3424 } 3425 #endif 3426 } 3427 3428 usbd_status 3429 ohci_device_isoc_start(usbd_xfer_handle xfer) 3430 { 3431 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3432 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3433 3434 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3435 3436 if (sc->sc_dying) 3437 return (USBD_IOERROR); 3438 3439 #ifdef DIAGNOSTIC 3440 if (xfer->status != USBD_IN_PROGRESS) 3441 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3442 #endif 3443 3444 /* XXX anything to do? */ 3445 3446 return (USBD_IN_PROGRESS); 3447 } 3448 3449 void 3450 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3451 { 3452 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3453 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3454 ohci_soft_ed_t *sed; 3455 ohci_soft_itd_t *sitd; 3456 int s; 3457 3458 s = splusb(); 3459 3460 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3461 3462 /* Transfer is already done. */ 3463 if (xfer->status != USBD_NOT_STARTED && 3464 xfer->status != USBD_IN_PROGRESS) { 3465 splx(s); 3466 printf("ohci_device_isoc_abort: early return\n"); 3467 return; 3468 } 3469 3470 /* Give xfer the requested abort code. */ 3471 xfer->status = USBD_CANCELLED; 3472 3473 sed = opipe->sed; 3474 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3475 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3476 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3477 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3478 sizeof(sed->ed.ed_flags), 3479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3480 3481 sitd = xfer->hcpriv; 3482 #ifdef DIAGNOSTIC 3483 if (sitd == NULL) { 3484 splx(s); 3485 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3486 return; 3487 } 3488 #endif 3489 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3490 #ifdef DIAGNOSTIC 3491 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3492 sitd->isdone = 1; 3493 #endif 3494 } 3495 3496 splx(s); 3497 3498 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3499 3500 s = splusb(); 3501 3502 /* Run callback. */ 3503 usb_transfer_complete(xfer); 3504 3505 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3506 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3507 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3508 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3509 3510 splx(s); 3511 } 3512 3513 void 3514 ohci_device_isoc_done(usbd_xfer_handle xfer) 3515 { 3516 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3517 } 3518 3519 usbd_status 3520 ohci_setup_isoc(usbd_pipe_handle pipe) 3521 { 3522 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3523 ohci_softc_t *sc = pipe->device->bus->hci_private; 3524 struct iso *iso = &opipe->u.iso; 3525 int s; 3526 3527 iso->next = -1; 3528 iso->inuse = 0; 3529 3530 s = splusb(); 3531 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3532 splx(s); 3533 3534 return (USBD_NORMAL_COMPLETION); 3535 } 3536 3537 void 3538 ohci_device_isoc_close(usbd_pipe_handle pipe) 3539 { 3540 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3541 ohci_softc_t *sc = pipe->device->bus->hci_private; 3542 3543 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3544 ohci_close_pipe(pipe, sc->sc_isoc_head); 3545 #ifdef DIAGNOSTIC 3546 opipe->tail.itd->isdone = 1; 3547 #endif 3548 ohci_free_sitd(sc, opipe->tail.itd); 3549 } 3550
Indexes created Fri Oct 03 02:09:57 GMT 2025