ohci.c revision 1.212.2.1
1 /* $NetBSD: ohci.c,v 1.212.2.1 2011/06/06 09:08:41 jruoho Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.212.2.1 2011/06/06 09:08:41 jruoho Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/malloc.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 55 #include <sys/bus.h> 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 #if 0 102 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 103 ohci_soft_td_t *); 104 #endif 105 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 106 ohci_softc_t *, int, int, usbd_xfer_handle, 107 ohci_soft_td_t *, ohci_soft_td_t **); 108 109 Static usbd_status ohci_open(usbd_pipe_handle); 110 Static void ohci_poll(struct usbd_bus *); 111 Static void ohci_softintr(void *); 112 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 113 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 114 115 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 116 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 117 ohci_soft_ed_t *); 118 119 Static void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 136 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 137 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 138 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 139 Static void ohci_root_ctrl_close(usbd_pipe_handle); 140 Static void ohci_root_ctrl_done(usbd_xfer_handle); 141 142 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 143 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 144 Static void ohci_root_intr_abort(usbd_xfer_handle); 145 Static void ohci_root_intr_close(usbd_pipe_handle); 146 Static void ohci_root_intr_done(usbd_xfer_handle); 147 148 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 149 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 150 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 151 Static void ohci_device_ctrl_close(usbd_pipe_handle); 152 Static void ohci_device_ctrl_done(usbd_xfer_handle); 153 154 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 155 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 156 Static void ohci_device_bulk_abort(usbd_xfer_handle); 157 Static void ohci_device_bulk_close(usbd_pipe_handle); 158 Static void ohci_device_bulk_done(usbd_xfer_handle); 159 160 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 161 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 162 Static void ohci_device_intr_abort(usbd_xfer_handle); 163 Static void ohci_device_intr_close(usbd_pipe_handle); 164 Static void ohci_device_intr_done(usbd_xfer_handle); 165 166 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 167 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 168 Static void ohci_device_isoc_abort(usbd_xfer_handle); 169 Static void ohci_device_isoc_close(usbd_pipe_handle); 170 Static void ohci_device_isoc_done(usbd_xfer_handle); 171 172 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 173 struct ohci_pipe *pipe, int ival); 174 175 Static void ohci_timeout(void *); 176 Static void ohci_timeout_task(void *); 177 Static void ohci_rhsc_enable(void *); 178 179 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 180 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 181 182 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 183 Static void ohci_noop(usbd_pipe_handle pipe); 184 185 #ifdef OHCI_DEBUG 186 Static void ohci_dumpregs(ohci_softc_t *); 187 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 188 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 190 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 191 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 192 #endif 193 194 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 195 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 196 #define OWRITE1(sc, r, x) \ 197 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 198 #define OWRITE2(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 #define OWRITE4(sc, r, x) \ 201 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 202 static __inline uint8_t 203 OREAD1(ohci_softc_t *sc, bus_size_t r) 204 { 205 206 OBARR(sc); 207 return bus_space_read_1(sc->iot, sc->ioh, r); 208 } 209 210 static __inline uint16_t 211 OREAD2(ohci_softc_t *sc, bus_size_t r) 212 { 213 214 OBARR(sc); 215 return bus_space_read_2(sc->iot, sc->ioh, r); 216 } 217 218 static __inline uint32_t 219 OREAD4(ohci_softc_t *sc, bus_size_t r) 220 { 221 222 OBARR(sc); 223 return bus_space_read_4(sc->iot, sc->ioh, r); 224 } 225 226 /* Reverse the bits in a value 0 .. 31 */ 227 Static u_int8_t revbits[OHCI_NO_INTRS] = 228 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 229 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 230 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 231 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 232 233 struct ohci_pipe { 234 struct usbd_pipe pipe; 235 ohci_soft_ed_t *sed; 236 union { 237 ohci_soft_td_t *td; 238 ohci_soft_itd_t *itd; 239 } tail; 240 /* Info needed for different pipe kinds. */ 241 union { 242 /* Control pipe */ 243 struct { 244 usb_dma_t reqdma; 245 u_int length; 246 ohci_soft_td_t *setup, *data, *stat; 247 } ctl; 248 /* Interrupt pipe */ 249 struct { 250 int nslots; 251 int pos; 252 } intr; 253 /* Bulk pipe */ 254 struct { 255 u_int length; 256 int isread; 257 } bulk; 258 /* Iso pipe */ 259 struct iso { 260 int next, inuse; 261 } iso; 262 } u; 263 }; 264 265 #define OHCI_INTR_ENDPT 1 266 267 Static const struct usbd_bus_methods ohci_bus_methods = { 268 ohci_open, 269 ohci_softintr, 270 ohci_poll, 271 ohci_allocm, 272 ohci_freem, 273 ohci_allocx, 274 ohci_freex, 275 }; 276 277 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 278 ohci_root_ctrl_transfer, 279 ohci_root_ctrl_start, 280 ohci_root_ctrl_abort, 281 ohci_root_ctrl_close, 282 ohci_noop, 283 ohci_root_ctrl_done, 284 }; 285 286 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 287 ohci_root_intr_transfer, 288 ohci_root_intr_start, 289 ohci_root_intr_abort, 290 ohci_root_intr_close, 291 ohci_noop, 292 ohci_root_intr_done, 293 }; 294 295 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 296 ohci_device_ctrl_transfer, 297 ohci_device_ctrl_start, 298 ohci_device_ctrl_abort, 299 ohci_device_ctrl_close, 300 ohci_noop, 301 ohci_device_ctrl_done, 302 }; 303 304 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 305 ohci_device_intr_transfer, 306 ohci_device_intr_start, 307 ohci_device_intr_abort, 308 ohci_device_intr_close, 309 ohci_device_clear_toggle, 310 ohci_device_intr_done, 311 }; 312 313 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 314 ohci_device_bulk_transfer, 315 ohci_device_bulk_start, 316 ohci_device_bulk_abort, 317 ohci_device_bulk_close, 318 ohci_device_clear_toggle, 319 ohci_device_bulk_done, 320 }; 321 322 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 323 ohci_device_isoc_transfer, 324 ohci_device_isoc_start, 325 ohci_device_isoc_abort, 326 ohci_device_isoc_close, 327 ohci_noop, 328 ohci_device_isoc_done, 329 }; 330 331 int 332 ohci_activate(device_t self, enum devact act) 333 { 334 struct ohci_softc *sc = device_private(self); 335 336 switch (act) { 337 case DVACT_DEACTIVATE: 338 sc->sc_dying = 1; 339 return 0; 340 default: 341 return EOPNOTSUPP; 342 } 343 } 344 345 void 346 ohci_childdet(device_t self, device_t child) 347 { 348 struct ohci_softc *sc = device_private(self); 349 350 KASSERT(sc->sc_child == child); 351 sc->sc_child = NULL; 352 } 353 354 int 355 ohci_detach(struct ohci_softc *sc, int flags) 356 { 357 int rv = 0; 358 usbd_xfer_handle xfer; 359 360 if (sc->sc_child != NULL) 361 rv = config_detach(sc->sc_child, flags); 362 363 if (rv != 0) 364 return (rv); 365 366 callout_stop(&sc->sc_tmo_rhsc); 367 368 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 369 callout_destroy(&sc->sc_tmo_rhsc); 370 371 if (sc->sc_hcca != NULL) 372 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 373 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 374 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 375 free(xfer, M_USB); 376 } 377 378 return (rv); 379 } 380 381 ohci_soft_ed_t * 382 ohci_alloc_sed(ohci_softc_t *sc) 383 { 384 ohci_soft_ed_t *sed; 385 usbd_status err; 386 int i, offs; 387 usb_dma_t dma; 388 389 if (sc->sc_freeeds == NULL) { 390 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 391 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 392 OHCI_ED_ALIGN, &dma); 393 if (err) 394 return (0); 395 for(i = 0; i < OHCI_SED_CHUNK; i++) { 396 offs = i * OHCI_SED_SIZE; 397 sed = KERNADDR(&dma, offs); 398 sed->physaddr = DMAADDR(&dma, offs); 399 sed->dma = dma; 400 sed->offs = offs; 401 sed->next = sc->sc_freeeds; 402 sc->sc_freeeds = sed; 403 } 404 } 405 sed = sc->sc_freeeds; 406 sc->sc_freeeds = sed->next; 407 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 408 sed->next = 0; 409 return (sed); 410 } 411 412 void 413 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 414 { 415 sed->next = sc->sc_freeeds; 416 sc->sc_freeeds = sed; 417 } 418 419 ohci_soft_td_t * 420 ohci_alloc_std(ohci_softc_t *sc) 421 { 422 ohci_soft_td_t *std; 423 usbd_status err; 424 int i, offs; 425 usb_dma_t dma; 426 int s; 427 428 if (sc->sc_freetds == NULL) { 429 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 430 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 431 OHCI_TD_ALIGN, &dma); 432 if (err) 433 return (NULL); 434 s = splusb(); 435 for(i = 0; i < OHCI_STD_CHUNK; i++) { 436 offs = i * OHCI_STD_SIZE; 437 std = KERNADDR(&dma, offs); 438 std->physaddr = DMAADDR(&dma, offs); 439 std->dma = dma; 440 std->offs = offs; 441 std->nexttd = sc->sc_freetds; 442 sc->sc_freetds = std; 443 } 444 splx(s); 445 } 446 447 s = splusb(); 448 std = sc->sc_freetds; 449 sc->sc_freetds = std->nexttd; 450 memset(&std->td, 0, sizeof(ohci_td_t)); 451 std->nexttd = NULL; 452 std->xfer = NULL; 453 ohci_hash_add_td(sc, std); 454 splx(s); 455 456 return (std); 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 int s; 463 464 s = splusb(); 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 splx(s); 469 } 470 471 usbd_status 472 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 473 int alen, int rd, usbd_xfer_handle xfer, 474 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 475 { 476 ohci_soft_td_t *next, *cur; 477 ohci_physaddr_t dataphys, dataphysend; 478 u_int32_t tdflags; 479 int len, curlen; 480 usb_dma_t *dma = &xfer->dmabuf; 481 u_int16_t flags = xfer->flags; 482 483 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 484 485 len = alen; 486 cur = sp; 487 dataphys = DMAADDR(dma, 0); 488 dataphysend = OHCI_PAGE(dataphys + len - 1); 489 usb_syncmem(dma, 0, len, 490 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 491 tdflags = HTOO32( 492 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 493 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 494 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 495 496 for (;;) { 497 next = ohci_alloc_std(sc); 498 if (next == NULL) 499 goto nomem; 500 501 /* The OHCI hardware can handle at most one page crossing. */ 502 if (OHCI_PAGE(dataphys) == dataphysend || 503 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 504 /* we can handle it in this TD */ 505 curlen = len; 506 } else { 507 /* must use multiple TDs, fill as much as possible. */ 508 curlen = 2 * OHCI_PAGE_SIZE - 509 (dataphys & (OHCI_PAGE_SIZE-1)); 510 /* the length must be a multiple of the max size */ 511 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 512 #ifdef DIAGNOSTIC 513 if (curlen == 0) 514 panic("ohci_alloc_std: curlen == 0"); 515 #endif 516 } 517 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 518 "dataphysend=0x%08x len=%d curlen=%d\n", 519 dataphys, dataphysend, 520 len, curlen)); 521 len -= curlen; 522 523 cur->td.td_flags = tdflags; 524 cur->td.td_cbp = HTOO32(dataphys); 525 cur->nexttd = next; 526 cur->td.td_nexttd = HTOO32(next->physaddr); 527 cur->td.td_be = HTOO32(dataphys + curlen - 1); 528 cur->len = curlen; 529 cur->flags = OHCI_ADD_LEN; 530 cur->xfer = xfer; 531 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 532 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 533 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 534 dataphys, dataphys + curlen - 1)); 535 if (len == 0) 536 break; 537 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 538 dataphys += curlen; 539 cur = next; 540 } 541 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 542 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 543 /* Force a 0 length transfer at the end. */ 544 545 cur = next; 546 next = ohci_alloc_std(sc); 547 if (next == NULL) 548 goto nomem; 549 550 cur->td.td_flags = tdflags; 551 cur->td.td_cbp = 0; /* indicate 0 length packet */ 552 cur->nexttd = next; 553 cur->td.td_nexttd = HTOO32(next->physaddr); 554 cur->td.td_be = ~0; 555 cur->len = 0; 556 cur->flags = 0; 557 cur->xfer = xfer; 558 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 560 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 561 } 562 *ep = cur; 563 564 return (USBD_NORMAL_COMPLETION); 565 566 nomem: 567 /* XXX free chain */ 568 return (USBD_NOMEM); 569 } 570 571 #if 0 572 Static void 573 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 574 ohci_soft_td_t *stdend) 575 { 576 ohci_soft_td_t *p; 577 578 for (; std != stdend; std = p) { 579 p = std->nexttd; 580 ohci_free_std(sc, std); 581 } 582 } 583 #endif 584 585 ohci_soft_itd_t * 586 ohci_alloc_sitd(ohci_softc_t *sc) 587 { 588 ohci_soft_itd_t *sitd; 589 usbd_status err; 590 int i, s, offs; 591 usb_dma_t dma; 592 593 if (sc->sc_freeitds == NULL) { 594 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 595 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 596 OHCI_ITD_ALIGN, &dma); 597 if (err) 598 return (NULL); 599 s = splusb(); 600 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 601 offs = i * OHCI_SITD_SIZE; 602 sitd = KERNADDR(&dma, offs); 603 sitd->physaddr = DMAADDR(&dma, offs); 604 sitd->dma = dma; 605 sitd->offs = offs; 606 sitd->nextitd = sc->sc_freeitds; 607 sc->sc_freeitds = sitd; 608 } 609 splx(s); 610 } 611 612 s = splusb(); 613 sitd = sc->sc_freeitds; 614 sc->sc_freeitds = sitd->nextitd; 615 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 616 sitd->nextitd = NULL; 617 sitd->xfer = NULL; 618 ohci_hash_add_itd(sc, sitd); 619 splx(s); 620 621 #ifdef DIAGNOSTIC 622 sitd->isdone = 0; 623 #endif 624 625 return (sitd); 626 } 627 628 void 629 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 630 { 631 int s; 632 633 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 634 635 #ifdef DIAGNOSTIC 636 if (!sitd->isdone) { 637 panic("ohci_free_sitd: sitd=%p not done", sitd); 638 return; 639 } 640 /* Warn double free */ 641 sitd->isdone = 0; 642 #endif 643 644 s = splusb(); 645 ohci_hash_rem_itd(sc, sitd); 646 sitd->nextitd = sc->sc_freeitds; 647 sc->sc_freeitds = sitd; 648 splx(s); 649 } 650 651 usbd_status 652 ohci_init(ohci_softc_t *sc) 653 { 654 ohci_soft_ed_t *sed, *psed; 655 usbd_status err; 656 int i; 657 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 658 659 DPRINTF(("ohci_init: start\n")); 660 aprint_normal_dev(sc->sc_dev, ""); 661 662 sc->sc_hcca = NULL; 663 callout_init(&sc->sc_tmo_rhsc, 0); 664 665 for (i = 0; i < OHCI_HASH_SIZE; i++) 666 LIST_INIT(&sc->sc_hash_tds[i]); 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_itds[i]); 669 670 SIMPLEQ_INIT(&sc->sc_free_xfers); 671 672 rev = OREAD4(sc, OHCI_REVISION); 673 aprint_normal("OHCI version %d.%d%s\n", 674 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 675 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 676 677 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 678 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 679 sc->sc_bus.usbrev = USBREV_UNKNOWN; 680 return (USBD_INVAL); 681 } 682 sc->sc_bus.usbrev = USBREV_1_0; 683 684 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 685 USB_MEM_RESERVE); 686 687 /* XXX determine alignment by R/W */ 688 /* Allocate the HCCA area. */ 689 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 690 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 691 if (err) { 692 sc->sc_hcca = NULL; 693 return err; 694 } 695 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 696 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 697 698 sc->sc_eintrs = OHCI_NORMAL_INTRS; 699 700 /* Allocate dummy ED that starts the control list. */ 701 sc->sc_ctrl_head = ohci_alloc_sed(sc); 702 if (sc->sc_ctrl_head == NULL) { 703 err = USBD_NOMEM; 704 goto bad1; 705 } 706 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 707 708 /* Allocate dummy ED that starts the bulk list. */ 709 sc->sc_bulk_head = ohci_alloc_sed(sc); 710 if (sc->sc_bulk_head == NULL) { 711 err = USBD_NOMEM; 712 goto bad2; 713 } 714 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 715 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 716 sizeof(sc->sc_bulk_head->ed), 717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 718 719 /* Allocate dummy ED that starts the isochronous list. */ 720 sc->sc_isoc_head = ohci_alloc_sed(sc); 721 if (sc->sc_isoc_head == NULL) { 722 err = USBD_NOMEM; 723 goto bad3; 724 } 725 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 726 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 727 sizeof(sc->sc_isoc_head->ed), 728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 729 730 /* Allocate all the dummy EDs that make up the interrupt tree. */ 731 for (i = 0; i < OHCI_NO_EDS; i++) { 732 sed = ohci_alloc_sed(sc); 733 if (sed == NULL) { 734 while (--i >= 0) 735 ohci_free_sed(sc, sc->sc_eds[i]); 736 err = USBD_NOMEM; 737 goto bad4; 738 } 739 /* All ED fields are set to 0. */ 740 sc->sc_eds[i] = sed; 741 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 742 if (i != 0) 743 psed = sc->sc_eds[(i-1) / 2]; 744 else 745 psed= sc->sc_isoc_head; 746 sed->next = psed; 747 sed->ed.ed_nexted = HTOO32(psed->physaddr); 748 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 750 } 751 /* 752 * Fill HCCA interrupt table. The bit reversal is to get 753 * the tree set up properly to spread the interrupts. 754 */ 755 for (i = 0; i < OHCI_NO_INTRS; i++) 756 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 757 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 758 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 760 761 #ifdef OHCI_DEBUG 762 if (ohcidebug > 15) { 763 for (i = 0; i < OHCI_NO_EDS; i++) { 764 printf("ed#%d ", i); 765 ohci_dump_ed(sc, sc->sc_eds[i]); 766 } 767 printf("iso "); 768 ohci_dump_ed(sc, sc->sc_isoc_head); 769 } 770 #endif 771 772 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 773 ctl = OREAD4(sc, OHCI_CONTROL); 774 rwc = ctl & OHCI_RWC; 775 fm = OREAD4(sc, OHCI_FM_INTERVAL); 776 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 777 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 778 779 /* Determine in what context we are running. */ 780 if (ctl & OHCI_IR) { 781 /* SMM active, request change */ 782 DPRINTF(("ohci_init: SMM active, request owner change\n")); 783 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 784 (OHCI_OC | OHCI_MIE)) 785 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 786 s = OREAD4(sc, OHCI_COMMAND_STATUS); 787 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 788 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 789 usb_delay_ms(&sc->sc_bus, 1); 790 ctl = OREAD4(sc, OHCI_CONTROL); 791 } 792 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 793 if ((ctl & OHCI_IR) == 0) { 794 aprint_error_dev(sc->sc_dev, 795 "SMM does not respond, resetting\n"); 796 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 797 goto reset; 798 } 799 #if 0 800 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 801 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 802 /* BIOS started controller. */ 803 DPRINTF(("ohci_init: BIOS active\n")); 804 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 806 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 807 } 808 #endif 809 } else { 810 DPRINTF(("ohci_init: cold started\n")); 811 reset: 812 /* Controller was cold started. */ 813 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 814 } 815 816 /* 817 * This reset should not be necessary according to the OHCI spec, but 818 * without it some controllers do not start. 819 */ 820 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 821 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 822 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 823 824 /* We now own the host controller and the bus has been reset. */ 825 826 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 827 /* Nominal time for a reset is 10 us. */ 828 for (i = 0; i < 10; i++) { 829 delay(10); 830 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 831 if (!hcr) 832 break; 833 } 834 if (hcr) { 835 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 836 err = USBD_IOERROR; 837 goto bad5; 838 } 839 #ifdef OHCI_DEBUG 840 if (ohcidebug > 15) 841 ohci_dumpregs(sc); 842 #endif 843 844 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 845 846 /* Set up HC registers. */ 847 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 848 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 849 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 850 /* disable all interrupts and then switch on all desired interrupts */ 851 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 852 /* switch on desired functional features */ 853 ctl = OREAD4(sc, OHCI_CONTROL); 854 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 855 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 856 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 857 /* And finally start it! */ 858 OWRITE4(sc, OHCI_CONTROL, ctl); 859 860 /* 861 * The controller is now OPERATIONAL. Set a some final 862 * registers that should be set earlier, but that the 863 * controller ignores when in the SUSPEND state. 864 */ 865 ival = OHCI_GET_IVAL(fm); 866 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 867 fm |= OHCI_FSMPS(ival) | ival; 868 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 869 per = OHCI_PERIODIC(ival); /* 90% periodic */ 870 OWRITE4(sc, OHCI_PERIODIC_START, per); 871 872 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 873 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 874 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 875 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 876 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 877 878 /* 879 * The AMD756 requires a delay before re-reading the register, 880 * otherwise it will occasionally report 0 ports. 881 */ 882 sc->sc_noport = 0; 883 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 884 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 885 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 886 } 887 888 #ifdef OHCI_DEBUG 889 if (ohcidebug > 5) 890 ohci_dumpregs(sc); 891 #endif 892 893 /* Set up the bus struct. */ 894 sc->sc_bus.methods = &ohci_bus_methods; 895 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 896 897 sc->sc_control = sc->sc_intre = 0; 898 899 /* Finally, turn on interrupts. */ 900 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 901 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 902 903 return (USBD_NORMAL_COMPLETION); 904 905 bad5: 906 for (i = 0; i < OHCI_NO_EDS; i++) 907 ohci_free_sed(sc, sc->sc_eds[i]); 908 bad4: 909 ohci_free_sed(sc, sc->sc_isoc_head); 910 bad3: 911 ohci_free_sed(sc, sc->sc_bulk_head); 912 bad2: 913 ohci_free_sed(sc, sc->sc_ctrl_head); 914 bad1: 915 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 916 sc->sc_hcca = NULL; 917 return (err); 918 } 919 920 usbd_status 921 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 922 { 923 struct ohci_softc *sc = bus->hci_private; 924 usbd_status status; 925 926 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 927 if (status == USBD_NOMEM) 928 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 929 return status; 930 } 931 932 void 933 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 934 { 935 struct ohci_softc *sc = bus->hci_private; 936 if (dma->block->flags & USB_DMA_RESERVE) { 937 usb_reserve_freem(&sc->sc_dma_reserve, dma); 938 return; 939 } 940 usb_freemem(&sc->sc_bus, dma); 941 } 942 943 usbd_xfer_handle 944 ohci_allocx(struct usbd_bus *bus) 945 { 946 struct ohci_softc *sc = bus->hci_private; 947 usbd_xfer_handle xfer; 948 949 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 950 if (xfer != NULL) { 951 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 952 #ifdef DIAGNOSTIC 953 if (xfer->busy_free != XFER_FREE) { 954 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 955 xfer->busy_free); 956 } 957 #endif 958 } else { 959 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 960 } 961 if (xfer != NULL) { 962 memset(xfer, 0, sizeof (struct ohci_xfer)); 963 #ifdef DIAGNOSTIC 964 xfer->busy_free = XFER_BUSY; 965 #endif 966 } 967 return (xfer); 968 } 969 970 void 971 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 972 { 973 struct ohci_softc *sc = bus->hci_private; 974 975 #ifdef DIAGNOSTIC 976 if (xfer->busy_free != XFER_BUSY) { 977 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 978 xfer->busy_free); 979 } 980 xfer->busy_free = XFER_FREE; 981 #endif 982 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 983 } 984 985 /* 986 * Shut down the controller when the system is going down. 987 */ 988 bool 989 ohci_shutdown(device_t self, int flags) 990 { 991 ohci_softc_t *sc = device_private(self); 992 993 DPRINTF(("ohci_shutdown: stopping the HC\n")); 994 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 995 return true; 996 } 997 998 bool 999 ohci_resume(device_t dv, const pmf_qual_t *qual) 1000 { 1001 ohci_softc_t *sc = device_private(dv); 1002 uint32_t ctl; 1003 int s; 1004 1005 s = splhardusb(); 1006 sc->sc_bus.use_polling++; 1007 /* Some broken BIOSes do not recover these values */ 1008 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1009 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1010 sc->sc_ctrl_head->physaddr); 1011 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1012 sc->sc_bulk_head->physaddr); 1013 if (sc->sc_intre) 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1015 (OHCI_ALL_INTRS | OHCI_MIE)); 1016 if (sc->sc_control) 1017 ctl = sc->sc_control; 1018 else 1019 ctl = OREAD4(sc, OHCI_CONTROL); 1020 ctl |= OHCI_HCFS_RESUME; 1021 OWRITE4(sc, OHCI_CONTROL, ctl); 1022 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1023 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1024 OWRITE4(sc, OHCI_CONTROL, ctl); 1025 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1026 sc->sc_control = sc->sc_intre = 0; 1027 sc->sc_bus.use_polling--; 1028 splx(s); 1029 1030 return true; 1031 } 1032 1033 bool 1034 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1035 { 1036 ohci_softc_t *sc = device_private(dv); 1037 uint32_t ctl; 1038 int s; 1039 1040 s = splhardusb(); 1041 sc->sc_bus.use_polling++; 1042 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1043 if (sc->sc_control == 0) { 1044 /* 1045 * Preserve register values, in case that BIOS 1046 * does not recover them. 1047 */ 1048 sc->sc_control = ctl; 1049 sc->sc_intre = OREAD4(sc, 1050 OHCI_INTERRUPT_ENABLE); 1051 } 1052 ctl |= OHCI_HCFS_SUSPEND; 1053 OWRITE4(sc, OHCI_CONTROL, ctl); 1054 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1055 sc->sc_bus.use_polling--; 1056 splx(s); 1057 1058 return true; 1059 } 1060 1061 #ifdef OHCI_DEBUG 1062 void 1063 ohci_dumpregs(ohci_softc_t *sc) 1064 { 1065 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1066 OREAD4(sc, OHCI_REVISION), 1067 OREAD4(sc, OHCI_CONTROL), 1068 OREAD4(sc, OHCI_COMMAND_STATUS))); 1069 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1070 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1071 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1072 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1073 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1074 OREAD4(sc, OHCI_HCCA), 1075 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1076 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1077 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1078 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1079 OREAD4(sc, OHCI_BULK_HEAD_ED), 1080 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1081 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1082 OREAD4(sc, OHCI_DONE_HEAD), 1083 OREAD4(sc, OHCI_FM_INTERVAL), 1084 OREAD4(sc, OHCI_FM_REMAINING))); 1085 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1086 OREAD4(sc, OHCI_FM_NUMBER), 1087 OREAD4(sc, OHCI_PERIODIC_START), 1088 OREAD4(sc, OHCI_LS_THRESHOLD))); 1089 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1090 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1091 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1092 OREAD4(sc, OHCI_RH_STATUS))); 1093 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1094 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1095 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1096 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1097 O32TOH(sc->sc_hcca->hcca_frame_number), 1098 O32TOH(sc->sc_hcca->hcca_done_head))); 1099 } 1100 #endif 1101 1102 Static int ohci_intr1(ohci_softc_t *); 1103 1104 int 1105 ohci_intr(void *p) 1106 { 1107 ohci_softc_t *sc = p; 1108 1109 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 1110 return (0); 1111 1112 /* If we get an interrupt while polling, then just ignore it. */ 1113 if (sc->sc_bus.use_polling) { 1114 #ifdef DIAGNOSTIC 1115 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1116 #endif 1117 /* for level triggered intrs, should do something to ack */ 1118 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1119 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1120 1121 return (0); 1122 } 1123 1124 return (ohci_intr1(sc)); 1125 } 1126 1127 Static int 1128 ohci_intr1(ohci_softc_t *sc) 1129 { 1130 u_int32_t intrs, eintrs; 1131 1132 DPRINTFN(14,("ohci_intr1: enter\n")); 1133 1134 /* In case the interrupt occurs before initialization has completed. */ 1135 if (sc == NULL || sc->sc_hcca == NULL) { 1136 #ifdef DIAGNOSTIC 1137 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1138 #endif 1139 return (0); 1140 } 1141 1142 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1143 if (!intrs) 1144 return (0); 1145 1146 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1147 eintrs = intrs & sc->sc_eintrs; 1148 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1149 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1150 (u_int)eintrs, sc->sc_eintrs)); 1151 1152 if (!eintrs) { 1153 return (0); 1154 } 1155 1156 sc->sc_bus.intr_context++; 1157 sc->sc_bus.no_intrs++; 1158 if (eintrs & OHCI_SO) { 1159 sc->sc_overrun_cnt++; 1160 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1161 printf("%s: %u scheduling overruns\n", 1162 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1163 sc->sc_overrun_cnt = 0; 1164 } 1165 /* XXX do what */ 1166 eintrs &= ~OHCI_SO; 1167 } 1168 if (eintrs & OHCI_WDH) { 1169 /* 1170 * We block the interrupt below, and reenable it later from 1171 * ohci_softintr(). 1172 */ 1173 usb_schedsoftintr(&sc->sc_bus); 1174 } 1175 if (eintrs & OHCI_RD) { 1176 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1177 /* XXX process resume detect */ 1178 } 1179 if (eintrs & OHCI_UE) { 1180 printf("%s: unrecoverable error, controller halted\n", 1181 device_xname(sc->sc_dev)); 1182 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1183 /* XXX what else */ 1184 } 1185 if (eintrs & OHCI_RHSC) { 1186 /* 1187 * We block the interrupt below, and reenable it later from 1188 * a timeout. 1189 */ 1190 ohci_rhsc(sc, sc->sc_intrxfer); 1191 /* Do not allow RHSC interrupts > 1 per second */ 1192 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1193 } 1194 1195 sc->sc_bus.intr_context--; 1196 1197 if (eintrs != 0) { 1198 /* Block unprocessed interrupts. */ 1199 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1200 sc->sc_eintrs &= ~eintrs; 1201 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1202 device_xname(sc->sc_dev), eintrs)); 1203 } 1204 1205 return (1); 1206 } 1207 1208 void 1209 ohci_rhsc_enable(void *v_sc) 1210 { 1211 ohci_softc_t *sc = v_sc; 1212 int s; 1213 1214 s = splhardusb(); 1215 sc->sc_eintrs |= OHCI_RHSC; 1216 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1217 splx(s); 1218 } 1219 1220 #ifdef OHCI_DEBUG 1221 const char *ohci_cc_strs[] = { 1222 "NO_ERROR", 1223 "CRC", 1224 "BIT_STUFFING", 1225 "DATA_TOGGLE_MISMATCH", 1226 "STALL", 1227 "DEVICE_NOT_RESPONDING", 1228 "PID_CHECK_FAILURE", 1229 "UNEXPECTED_PID", 1230 "DATA_OVERRUN", 1231 "DATA_UNDERRUN", 1232 "BUFFER_OVERRUN", 1233 "BUFFER_UNDERRUN", 1234 "reserved", 1235 "reserved", 1236 "NOT_ACCESSED", 1237 "NOT_ACCESSED", 1238 }; 1239 #endif 1240 1241 void 1242 ohci_softintr(void *v) 1243 { 1244 struct usbd_bus *bus = v; 1245 ohci_softc_t *sc = bus->hci_private; 1246 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1247 ohci_soft_td_t *std, *sdone, *stdnext; 1248 usbd_xfer_handle xfer; 1249 struct ohci_pipe *opipe; 1250 int len, cc, s; 1251 int i, j, actlen, iframes, uedir; 1252 ohci_physaddr_t done; 1253 1254 DPRINTFN(10,("ohci_softintr: enter\n")); 1255 1256 sc->sc_bus.intr_context++; 1257 1258 s = splhardusb(); 1259 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1260 sizeof(sc->sc_hcca->hcca_done_head), 1261 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1262 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1263 sc->sc_hcca->hcca_done_head = 0; 1264 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1265 sizeof(sc->sc_hcca->hcca_done_head), 1266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1267 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1268 sc->sc_eintrs |= OHCI_WDH; 1269 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1270 splx(s); 1271 1272 /* Reverse the done list. */ 1273 for (sdone = NULL, sidone = NULL; done != 0; ) { 1274 std = ohci_hash_find_td(sc, done); 1275 if (std != NULL) { 1276 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1277 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1278 std->dnext = sdone; 1279 done = O32TOH(std->td.td_nexttd); 1280 sdone = std; 1281 DPRINTFN(10,("add TD %p\n", std)); 1282 continue; 1283 } 1284 sitd = ohci_hash_find_itd(sc, done); 1285 if (sitd != NULL) { 1286 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1288 sitd->dnext = sidone; 1289 done = O32TOH(sitd->itd.itd_nextitd); 1290 sidone = sitd; 1291 DPRINTFN(5,("add ITD %p\n", sitd)); 1292 continue; 1293 } 1294 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1295 } 1296 1297 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1298 1299 #ifdef OHCI_DEBUG 1300 if (ohcidebug > 10) { 1301 DPRINTF(("ohci_process_done: TD done:\n")); 1302 ohci_dump_tds(sc, sdone); 1303 } 1304 #endif 1305 1306 for (std = sdone; std; std = stdnext) { 1307 xfer = std->xfer; 1308 stdnext = std->dnext; 1309 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1310 std, xfer, xfer ? xfer->hcpriv : 0)); 1311 if (xfer == NULL) { 1312 /* 1313 * xfer == NULL: There seems to be no xfer associated 1314 * with this TD. It is tailp that happened to end up on 1315 * the done queue. 1316 * Shouldn't happen, but some chips are broken(?). 1317 */ 1318 continue; 1319 } 1320 if (xfer->status == USBD_CANCELLED || 1321 xfer->status == USBD_TIMEOUT) { 1322 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1323 xfer)); 1324 /* Handled by abort routine. */ 1325 continue; 1326 } 1327 callout_stop(&xfer->timeout_handle); 1328 1329 len = std->len; 1330 if (std->td.td_cbp != 0) 1331 len -= O32TOH(std->td.td_be) - 1332 O32TOH(std->td.td_cbp) + 1; 1333 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1334 std->flags)); 1335 if (std->flags & OHCI_ADD_LEN) 1336 xfer->actlen += len; 1337 1338 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1339 if (cc == OHCI_CC_NO_ERROR) { 1340 if (std->flags & OHCI_CALL_DONE) { 1341 xfer->status = USBD_NORMAL_COMPLETION; 1342 s = splusb(); 1343 usb_transfer_complete(xfer); 1344 splx(s); 1345 } 1346 ohci_free_std(sc, std); 1347 } else { 1348 /* 1349 * Endpoint is halted. First unlink all the TDs 1350 * belonging to the failed transfer, and then restart 1351 * the endpoint. 1352 */ 1353 ohci_soft_td_t *p, *n; 1354 opipe = (struct ohci_pipe *)xfer->pipe; 1355 1356 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1357 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1358 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1359 1360 /* remove TDs */ 1361 for (p = std; p->xfer == xfer; p = n) { 1362 n = p->nexttd; 1363 ohci_free_std(sc, p); 1364 } 1365 1366 /* clear halt */ 1367 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1368 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1369 1370 if (cc == OHCI_CC_STALL) 1371 xfer->status = USBD_STALLED; 1372 else 1373 xfer->status = USBD_IOERROR; 1374 s = splusb(); 1375 usb_transfer_complete(xfer); 1376 splx(s); 1377 } 1378 } 1379 1380 #ifdef OHCI_DEBUG 1381 if (ohcidebug > 10) { 1382 DPRINTF(("ohci_softintr: ITD done:\n")); 1383 ohci_dump_itds(sc, sidone); 1384 } 1385 #endif 1386 1387 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1388 xfer = sitd->xfer; 1389 sitdnext = sitd->dnext; 1390 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1391 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1392 if (xfer == NULL) 1393 continue; 1394 if (xfer->status == USBD_CANCELLED || 1395 xfer->status == USBD_TIMEOUT) { 1396 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1397 xfer)); 1398 /* Handled by abort routine. */ 1399 continue; 1400 } 1401 #ifdef DIAGNOSTIC 1402 if (sitd->isdone) 1403 printf("ohci_softintr: sitd=%p is done\n", sitd); 1404 sitd->isdone = 1; 1405 #endif 1406 if (sitd->flags & OHCI_CALL_DONE) { 1407 ohci_soft_itd_t *next; 1408 1409 opipe = (struct ohci_pipe *)xfer->pipe; 1410 opipe->u.iso.inuse -= xfer->nframes; 1411 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1412 bEndpointAddress); 1413 xfer->status = USBD_NORMAL_COMPLETION; 1414 actlen = 0; 1415 for (i = 0, sitd = xfer->hcpriv;; 1416 sitd = next) { 1417 next = sitd->nextitd; 1418 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1419 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1420 xfer->status = USBD_IOERROR; 1421 /* For input, update frlengths with actual */ 1422 /* XXX anything necessary for output? */ 1423 if (uedir == UE_DIR_IN && 1424 xfer->status == USBD_NORMAL_COMPLETION) { 1425 iframes = OHCI_ITD_GET_FC(O32TOH( 1426 sitd->itd.itd_flags)); 1427 for (j = 0; j < iframes; i++, j++) { 1428 len = O16TOH(sitd-> 1429 itd.itd_offset[j]); 1430 if ((OHCI_ITD_PSW_GET_CC(len) & 1431 OHCI_CC_NOT_ACCESSED_MASK) 1432 == OHCI_CC_NOT_ACCESSED) 1433 len = 0; 1434 else 1435 len = OHCI_ITD_PSW_LENGTH(len); 1436 xfer->frlengths[i] = len; 1437 actlen += len; 1438 } 1439 } 1440 if (sitd->flags & OHCI_CALL_DONE) 1441 break; 1442 ohci_free_sitd(sc, sitd); 1443 } 1444 ohci_free_sitd(sc, sitd); 1445 if (uedir == UE_DIR_IN && 1446 xfer->status == USBD_NORMAL_COMPLETION) 1447 xfer->actlen = actlen; 1448 xfer->hcpriv = NULL; 1449 1450 s = splusb(); 1451 usb_transfer_complete(xfer); 1452 splx(s); 1453 } 1454 } 1455 1456 #ifdef USB_USE_SOFTINTR 1457 if (sc->sc_softwake) { 1458 sc->sc_softwake = 0; 1459 wakeup(&sc->sc_softwake); 1460 } 1461 #endif /* USB_USE_SOFTINTR */ 1462 1463 sc->sc_bus.intr_context--; 1464 DPRINTFN(10,("ohci_softintr: done:\n")); 1465 } 1466 1467 void 1468 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1469 { 1470 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1471 int len = UGETW(xfer->request.wLength); 1472 int isread = (xfer->request.bmRequestType & UT_READ); 1473 1474 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1475 1476 #ifdef DIAGNOSTIC 1477 if (!(xfer->rqflags & URQ_REQUEST)) { 1478 panic("ohci_device_ctrl_done: not a request"); 1479 } 1480 #endif 1481 if (len) 1482 usb_syncmem(&xfer->dmabuf, 0, len, 1483 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1484 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1485 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1486 } 1487 1488 void 1489 ohci_device_intr_done(usbd_xfer_handle xfer) 1490 { 1491 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1492 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1493 ohci_soft_ed_t *sed = opipe->sed; 1494 ohci_soft_td_t *data, *tail; 1495 int isread = 1496 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1497 1498 1499 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1500 xfer, xfer->actlen)); 1501 1502 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1503 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1504 if (xfer->pipe->repeat) { 1505 data = opipe->tail.td; 1506 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1507 if (tail == NULL) { 1508 xfer->status = USBD_NOMEM; 1509 return; 1510 } 1511 tail->xfer = NULL; 1512 1513 data->td.td_flags = HTOO32( 1514 OHCI_TD_IN | OHCI_TD_NOCC | 1515 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1516 if (xfer->flags & USBD_SHORT_XFER_OK) 1517 data->td.td_flags |= HTOO32(OHCI_TD_R); 1518 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1519 data->nexttd = tail; 1520 data->td.td_nexttd = HTOO32(tail->physaddr); 1521 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1522 xfer->length - 1); 1523 data->len = xfer->length; 1524 data->xfer = xfer; 1525 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1526 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1528 xfer->hcpriv = data; 1529 xfer->actlen = 0; 1530 1531 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1532 usb_syncmem(&sed->dma, 1533 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1534 sizeof(sed->ed.ed_tailp), 1535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1536 opipe->tail.td = tail; 1537 } 1538 } 1539 1540 void 1541 ohci_device_bulk_done(usbd_xfer_handle xfer) 1542 { 1543 int isread = 1544 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1545 1546 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1547 xfer, xfer->actlen)); 1548 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1549 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1550 } 1551 1552 void 1553 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1554 { 1555 usbd_pipe_handle pipe; 1556 u_char *p; 1557 int i, m; 1558 int hstatus; 1559 1560 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1561 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1562 sc, xfer, hstatus)); 1563 1564 if (xfer == NULL) { 1565 /* Just ignore the change. */ 1566 return; 1567 } 1568 1569 pipe = xfer->pipe; 1570 1571 p = KERNADDR(&xfer->dmabuf, 0); 1572 m = min(sc->sc_noport, xfer->length * 8 - 1); 1573 memset(p, 0, xfer->length); 1574 for (i = 1; i <= m; i++) { 1575 /* Pick out CHANGE bits from the status reg. */ 1576 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1577 p[i/8] |= 1 << (i%8); 1578 } 1579 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1580 xfer->actlen = xfer->length; 1581 xfer->status = USBD_NORMAL_COMPLETION; 1582 1583 usb_transfer_complete(xfer); 1584 } 1585 1586 void 1587 ohci_root_intr_done(usbd_xfer_handle xfer) 1588 { 1589 } 1590 1591 void 1592 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1593 { 1594 } 1595 1596 /* 1597 * Wait here until controller claims to have an interrupt. 1598 * Then call ohci_intr and return. Use timeout to avoid waiting 1599 * too long. 1600 */ 1601 void 1602 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1603 { 1604 int timo; 1605 u_int32_t intrs; 1606 1607 xfer->status = USBD_IN_PROGRESS; 1608 for (timo = xfer->timeout; timo >= 0; timo--) { 1609 usb_delay_ms(&sc->sc_bus, 1); 1610 if (sc->sc_dying) 1611 break; 1612 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1613 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1614 #ifdef OHCI_DEBUG 1615 if (ohcidebug > 15) 1616 ohci_dumpregs(sc); 1617 #endif 1618 if (intrs) { 1619 ohci_intr1(sc); 1620 if (xfer->status != USBD_IN_PROGRESS) 1621 return; 1622 } 1623 } 1624 1625 /* Timeout */ 1626 DPRINTF(("ohci_waitintr: timeout\n")); 1627 xfer->status = USBD_TIMEOUT; 1628 usb_transfer_complete(xfer); 1629 /* XXX should free TD */ 1630 } 1631 1632 void 1633 ohci_poll(struct usbd_bus *bus) 1634 { 1635 ohci_softc_t *sc = bus->hci_private; 1636 #ifdef OHCI_DEBUG 1637 static int last; 1638 int new; 1639 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1640 if (new != last) { 1641 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1642 last = new; 1643 } 1644 #endif 1645 1646 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1647 ohci_intr1(sc); 1648 } 1649 1650 usbd_status 1651 ohci_device_request(usbd_xfer_handle xfer) 1652 { 1653 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1654 usb_device_request_t *req = &xfer->request; 1655 usbd_device_handle dev = opipe->pipe.device; 1656 ohci_softc_t *sc = dev->bus->hci_private; 1657 int addr = dev->address; 1658 ohci_soft_td_t *setup, *stat, *next, *tail; 1659 ohci_soft_ed_t *sed; 1660 int isread; 1661 int len; 1662 usbd_status err; 1663 int s; 1664 1665 isread = req->bmRequestType & UT_READ; 1666 len = UGETW(req->wLength); 1667 1668 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1669 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1670 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1671 UGETW(req->wIndex), len, addr, 1672 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1673 1674 setup = opipe->tail.td; 1675 stat = ohci_alloc_std(sc); 1676 if (stat == NULL) { 1677 err = USBD_NOMEM; 1678 goto bad1; 1679 } 1680 tail = ohci_alloc_std(sc); 1681 if (tail == NULL) { 1682 err = USBD_NOMEM; 1683 goto bad2; 1684 } 1685 tail->xfer = NULL; 1686 1687 sed = opipe->sed; 1688 opipe->u.ctl.length = len; 1689 1690 /* Update device address and length since they may have changed 1691 during the setup of the control pipe in usbd_new_device(). */ 1692 /* XXX This only needs to be done once, but it's too early in open. */ 1693 /* XXXX Should not touch ED here! */ 1694 1695 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1696 sizeof(sed->ed.ed_flags), 1697 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1698 sed->ed.ed_flags = HTOO32( 1699 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1700 OHCI_ED_SET_FA(addr) | 1701 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1702 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1703 sizeof(sed->ed.ed_flags), 1704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1705 1706 next = stat; 1707 1708 /* Set up data transaction */ 1709 if (len != 0) { 1710 ohci_soft_td_t *std = stat; 1711 1712 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1713 std, &stat); 1714 stat = stat->nexttd; /* point at free TD */ 1715 if (err) 1716 goto bad3; 1717 /* Start toggle at 1 and then use the carried toggle. */ 1718 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1719 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1720 usb_syncmem(&std->dma, 1721 std->offs + offsetof(ohci_td_t, td_flags), 1722 sizeof(std->td.td_flags), 1723 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1724 } 1725 1726 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1727 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1728 1729 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1730 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1731 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1732 setup->nexttd = next; 1733 setup->td.td_nexttd = HTOO32(next->physaddr); 1734 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1735 setup->len = 0; 1736 setup->xfer = xfer; 1737 setup->flags = 0; 1738 xfer->hcpriv = setup; 1739 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1740 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1741 1742 stat->td.td_flags = HTOO32( 1743 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1744 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1745 stat->td.td_cbp = 0; 1746 stat->nexttd = tail; 1747 stat->td.td_nexttd = HTOO32(tail->physaddr); 1748 stat->td.td_be = 0; 1749 stat->flags = OHCI_CALL_DONE; 1750 stat->len = 0; 1751 stat->xfer = xfer; 1752 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1753 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1754 1755 #ifdef OHCI_DEBUG 1756 if (ohcidebug > 5) { 1757 DPRINTF(("ohci_device_request:\n")); 1758 ohci_dump_ed(sc, sed); 1759 ohci_dump_tds(sc, setup); 1760 } 1761 #endif 1762 1763 /* Insert ED in schedule */ 1764 s = splusb(); 1765 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1766 usb_syncmem(&sed->dma, 1767 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1768 sizeof(sed->ed.ed_tailp), 1769 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1770 opipe->tail.td = tail; 1771 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1772 if (xfer->timeout && !sc->sc_bus.use_polling) { 1773 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1774 ohci_timeout, xfer); 1775 } 1776 splx(s); 1777 1778 #ifdef OHCI_DEBUG 1779 if (ohcidebug > 20) { 1780 delay(10000); 1781 DPRINTF(("ohci_device_request: status=%x\n", 1782 OREAD4(sc, OHCI_COMMAND_STATUS))); 1783 ohci_dumpregs(sc); 1784 printf("ctrl head:\n"); 1785 ohci_dump_ed(sc, sc->sc_ctrl_head); 1786 printf("sed:\n"); 1787 ohci_dump_ed(sc, sed); 1788 ohci_dump_tds(sc, setup); 1789 } 1790 #endif 1791 1792 return (USBD_NORMAL_COMPLETION); 1793 1794 bad3: 1795 ohci_free_std(sc, tail); 1796 bad2: 1797 ohci_free_std(sc, stat); 1798 bad1: 1799 return (err); 1800 } 1801 1802 /* 1803 * Add an ED to the schedule. Called at splusb(). 1804 */ 1805 void 1806 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1807 { 1808 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1809 1810 SPLUSBCHECK; 1811 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1812 sizeof(head->ed.ed_nexted), 1813 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1814 sed->next = head->next; 1815 sed->ed.ed_nexted = head->ed.ed_nexted; 1816 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1817 sizeof(sed->ed.ed_nexted), 1818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1819 head->next = sed; 1820 head->ed.ed_nexted = HTOO32(sed->physaddr); 1821 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1822 sizeof(head->ed.ed_nexted), 1823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1824 } 1825 1826 /* 1827 * Remove an ED from the schedule. Called at splusb(). 1828 */ 1829 void 1830 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1831 { 1832 ohci_soft_ed_t *p; 1833 1834 SPLUSBCHECK; 1835 1836 /* XXX */ 1837 for (p = head; p != NULL && p->next != sed; p = p->next) 1838 ; 1839 if (p == NULL) 1840 panic("ohci_rem_ed: ED not found"); 1841 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1842 sizeof(sed->ed.ed_nexted), 1843 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1844 p->next = sed->next; 1845 p->ed.ed_nexted = sed->ed.ed_nexted; 1846 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1847 sizeof(p->ed.ed_nexted), 1848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1849 } 1850 1851 /* 1852 * When a transfer is completed the TD is added to the done queue by 1853 * the host controller. This queue is the processed by software. 1854 * Unfortunately the queue contains the physical address of the TD 1855 * and we have no simple way to translate this back to a kernel address. 1856 * To make the translation possible (and fast) we use a hash table of 1857 * TDs currently in the schedule. The physical address is used as the 1858 * hash value. 1859 */ 1860 1861 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1862 /* Called at splusb() */ 1863 void 1864 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1865 { 1866 int h = HASH(std->physaddr); 1867 1868 SPLUSBCHECK; 1869 1870 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1871 } 1872 1873 /* Called at splusb() */ 1874 void 1875 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1876 { 1877 SPLUSBCHECK; 1878 1879 LIST_REMOVE(std, hnext); 1880 } 1881 1882 ohci_soft_td_t * 1883 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1884 { 1885 int h = HASH(a); 1886 ohci_soft_td_t *std; 1887 1888 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1889 std != NULL; 1890 std = LIST_NEXT(std, hnext)) 1891 if (std->physaddr == a) 1892 return (std); 1893 return (NULL); 1894 } 1895 1896 /* Called at splusb() */ 1897 void 1898 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1899 { 1900 int h = HASH(sitd->physaddr); 1901 1902 SPLUSBCHECK; 1903 1904 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1905 sitd, (u_long)sitd->physaddr)); 1906 1907 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1908 } 1909 1910 /* Called at splusb() */ 1911 void 1912 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1913 { 1914 SPLUSBCHECK; 1915 1916 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1917 sitd, (u_long)sitd->physaddr)); 1918 1919 LIST_REMOVE(sitd, hnext); 1920 } 1921 1922 ohci_soft_itd_t * 1923 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1924 { 1925 int h = HASH(a); 1926 ohci_soft_itd_t *sitd; 1927 1928 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1929 sitd != NULL; 1930 sitd = LIST_NEXT(sitd, hnext)) 1931 if (sitd->physaddr == a) 1932 return (sitd); 1933 return (NULL); 1934 } 1935 1936 void 1937 ohci_timeout(void *addr) 1938 { 1939 struct ohci_xfer *oxfer = addr; 1940 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1941 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1942 1943 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1944 1945 if (sc->sc_dying) { 1946 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1947 return; 1948 } 1949 1950 /* Execute the abort in a process context. */ 1951 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1952 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1953 USB_TASKQ_HC); 1954 } 1955 1956 void 1957 ohci_timeout_task(void *addr) 1958 { 1959 usbd_xfer_handle xfer = addr; 1960 int s; 1961 1962 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1963 1964 s = splusb(); 1965 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1966 splx(s); 1967 } 1968 1969 #ifdef OHCI_DEBUG 1970 void 1971 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1972 { 1973 for (; std; std = std->nexttd) 1974 ohci_dump_td(sc, std); 1975 } 1976 1977 void 1978 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1979 { 1980 char sbuf[128]; 1981 1982 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1983 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1984 snprintb(sbuf, sizeof(sbuf), 1985 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1986 (u_int32_t)O32TOH(std->td.td_flags)); 1987 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1988 "nexttd=0x%08lx be=0x%08lx\n", 1989 std, (u_long)std->physaddr, sbuf, 1990 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 1991 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 1992 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1993 (u_long)O32TOH(std->td.td_cbp), 1994 (u_long)O32TOH(std->td.td_nexttd), 1995 (u_long)O32TOH(std->td.td_be)); 1996 } 1997 1998 void 1999 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2000 { 2001 int i; 2002 2003 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2004 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2005 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2006 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2007 sitd, (u_long)sitd->physaddr, 2008 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2009 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2010 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2011 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2012 (u_long)O32TOH(sitd->itd.itd_bp0), 2013 (u_long)O32TOH(sitd->itd.itd_nextitd), 2014 (u_long)O32TOH(sitd->itd.itd_be)); 2015 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2016 printf("offs[%d]=0x%04x ", i, 2017 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2018 printf("\n"); 2019 } 2020 2021 void 2022 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2023 { 2024 for (; sitd; sitd = sitd->nextitd) 2025 ohci_dump_itd(sc, sitd); 2026 } 2027 2028 void 2029 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2030 { 2031 char sbuf[128], sbuf2[128]; 2032 2033 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2035 snprintb(sbuf, sizeof(sbuf), 2036 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2037 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2038 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2039 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2040 2041 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2042 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2043 sed, (u_long)sed->physaddr, 2044 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2045 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2046 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2047 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2048 (u_long)O32TOH(sed->ed.ed_headp), 2049 (u_long)O32TOH(sed->ed.ed_nexted)); 2050 } 2051 #endif 2052 2053 usbd_status 2054 ohci_open(usbd_pipe_handle pipe) 2055 { 2056 usbd_device_handle dev = pipe->device; 2057 ohci_softc_t *sc = dev->bus->hci_private; 2058 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2059 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2060 u_int8_t addr = dev->address; 2061 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2062 ohci_soft_ed_t *sed; 2063 ohci_soft_td_t *std; 2064 ohci_soft_itd_t *sitd; 2065 ohci_physaddr_t tdphys; 2066 u_int32_t fmt; 2067 usbd_status err; 2068 int s; 2069 int ival; 2070 2071 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2072 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2073 2074 if (sc->sc_dying) 2075 return (USBD_IOERROR); 2076 2077 std = NULL; 2078 sed = NULL; 2079 2080 if (addr == sc->sc_addr) { 2081 switch (ed->bEndpointAddress) { 2082 case USB_CONTROL_ENDPOINT: 2083 pipe->methods = &ohci_root_ctrl_methods; 2084 break; 2085 case UE_DIR_IN | OHCI_INTR_ENDPT: 2086 pipe->methods = &ohci_root_intr_methods; 2087 break; 2088 default: 2089 return (USBD_INVAL); 2090 } 2091 } else { 2092 sed = ohci_alloc_sed(sc); 2093 if (sed == NULL) 2094 goto bad0; 2095 opipe->sed = sed; 2096 if (xfertype == UE_ISOCHRONOUS) { 2097 sitd = ohci_alloc_sitd(sc); 2098 if (sitd == NULL) 2099 goto bad1; 2100 opipe->tail.itd = sitd; 2101 tdphys = sitd->physaddr; 2102 fmt = OHCI_ED_FORMAT_ISO; 2103 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2104 fmt |= OHCI_ED_DIR_IN; 2105 else 2106 fmt |= OHCI_ED_DIR_OUT; 2107 } else { 2108 std = ohci_alloc_std(sc); 2109 if (std == NULL) 2110 goto bad1; 2111 opipe->tail.td = std; 2112 tdphys = std->physaddr; 2113 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2114 } 2115 sed->ed.ed_flags = HTOO32( 2116 OHCI_ED_SET_FA(addr) | 2117 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2118 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2119 fmt | 2120 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2121 sed->ed.ed_headp = HTOO32(tdphys | 2122 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2123 sed->ed.ed_tailp = HTOO32(tdphys); 2124 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2125 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2126 2127 switch (xfertype) { 2128 case UE_CONTROL: 2129 pipe->methods = &ohci_device_ctrl_methods; 2130 err = usb_allocmem(&sc->sc_bus, 2131 sizeof(usb_device_request_t), 2132 0, &opipe->u.ctl.reqdma); 2133 if (err) 2134 goto bad; 2135 s = splusb(); 2136 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2137 splx(s); 2138 break; 2139 case UE_INTERRUPT: 2140 pipe->methods = &ohci_device_intr_methods; 2141 ival = pipe->interval; 2142 if (ival == USBD_DEFAULT_INTERVAL) 2143 ival = ed->bInterval; 2144 return (ohci_device_setintr(sc, opipe, ival)); 2145 case UE_ISOCHRONOUS: 2146 pipe->methods = &ohci_device_isoc_methods; 2147 return (ohci_setup_isoc(pipe)); 2148 case UE_BULK: 2149 pipe->methods = &ohci_device_bulk_methods; 2150 s = splusb(); 2151 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2152 splx(s); 2153 break; 2154 } 2155 } 2156 return (USBD_NORMAL_COMPLETION); 2157 2158 bad: 2159 if (std != NULL) 2160 ohci_free_std(sc, std); 2161 bad1: 2162 if (sed != NULL) 2163 ohci_free_sed(sc, sed); 2164 bad0: 2165 return (USBD_NOMEM); 2166 2167 } 2168 2169 /* 2170 * Close a reqular pipe. 2171 * Assumes that there are no pending transactions. 2172 */ 2173 void 2174 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2175 { 2176 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2177 ohci_softc_t *sc = pipe->device->bus->hci_private; 2178 ohci_soft_ed_t *sed = opipe->sed; 2179 int s; 2180 2181 s = splusb(); 2182 #ifdef DIAGNOSTIC 2183 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2184 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2185 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2186 ohci_soft_td_t *std; 2187 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2188 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2189 "tl=0x%x pipe=%p, std=%p\n", sed, 2190 (int)O32TOH(sed->ed.ed_headp), 2191 (int)O32TOH(sed->ed.ed_tailp), 2192 pipe, std); 2193 #ifdef USB_DEBUG 2194 usbd_dump_pipe(&opipe->pipe); 2195 #endif 2196 #ifdef OHCI_DEBUG 2197 ohci_dump_ed(sc, sed); 2198 if (std) 2199 ohci_dump_td(sc, std); 2200 #endif 2201 usb_delay_ms(&sc->sc_bus, 2); 2202 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2203 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2204 printf("ohci_close_pipe: pipe still not empty\n"); 2205 } 2206 #endif 2207 ohci_rem_ed(sed, head); 2208 /* Make sure the host controller is not touching this ED */ 2209 usb_delay_ms(&sc->sc_bus, 1); 2210 pipe->endpoint->datatoggle = 2211 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2212 splx(s); 2213 ohci_free_sed(sc, opipe->sed); 2214 } 2215 2216 /* 2217 * Abort a device request. 2218 * If this routine is called at splusb() it guarantees that the request 2219 * will be removed from the hardware scheduling and that the callback 2220 * for it will be called with USBD_CANCELLED status. 2221 * It's impossible to guarantee that the requested transfer will not 2222 * have happened since the hardware runs concurrently. 2223 * If the transaction has already happened we rely on the ordinary 2224 * interrupt processing to process it. 2225 */ 2226 void 2227 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2228 { 2229 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2230 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2231 ohci_soft_ed_t *sed = opipe->sed; 2232 ohci_soft_td_t *p, *n; 2233 ohci_physaddr_t headp; 2234 int s, hit; 2235 int wake; 2236 2237 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2238 2239 if (sc->sc_dying) { 2240 /* If we're dying, just do the software part. */ 2241 s = splusb(); 2242 xfer->status = status; /* make software ignore it */ 2243 callout_stop(&xfer->timeout_handle); 2244 usb_transfer_complete(xfer); 2245 splx(s); 2246 return; 2247 } 2248 2249 if (xfer->device->bus->intr_context || !curproc) 2250 panic("ohci_abort_xfer: not in process context"); 2251 2252 /* 2253 * If an abort is already in progress then just wait for it to 2254 * complete and return. 2255 */ 2256 if (xfer->hcflags & UXFER_ABORTING) { 2257 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2258 #ifdef DIAGNOSTIC 2259 if (status == USBD_TIMEOUT) 2260 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2261 #endif 2262 /* Override the status which might be USBD_TIMEOUT. */ 2263 xfer->status = status; 2264 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2265 xfer->hcflags |= UXFER_ABORTWAIT; 2266 while (xfer->hcflags & UXFER_ABORTING) 2267 tsleep(&xfer->hcflags, PZERO, "ohciaw", 0); 2268 return; 2269 } 2270 xfer->hcflags |= UXFER_ABORTING; 2271 2272 /* 2273 * Step 1: Make interrupt routine and hardware ignore xfer. 2274 */ 2275 s = splusb(); 2276 xfer->status = status; /* make software ignore it */ 2277 callout_stop(&xfer->timeout_handle); 2278 splx(s); 2279 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2280 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2281 sizeof(sed->ed.ed_flags), 2282 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2283 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2284 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2285 sizeof(sed->ed.ed_flags), 2286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2287 2288 /* 2289 * Step 2: Wait until we know hardware has finished any possible 2290 * use of the xfer. Also make sure the soft interrupt routine 2291 * has run. 2292 */ 2293 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2294 s = splusb(); 2295 #ifdef USB_USE_SOFTINTR 2296 sc->sc_softwake = 1; 2297 #endif /* USB_USE_SOFTINTR */ 2298 usb_schedsoftintr(&sc->sc_bus); 2299 #ifdef USB_USE_SOFTINTR 2300 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2301 #endif /* USB_USE_SOFTINTR */ 2302 splx(s); 2303 2304 /* 2305 * Step 3: Remove any vestiges of the xfer from the hardware. 2306 * The complication here is that the hardware may have executed 2307 * beyond the xfer we're trying to abort. So as we're scanning 2308 * the TDs of this xfer we check if the hardware points to 2309 * any of them. 2310 */ 2311 s = splusb(); /* XXX why? */ 2312 p = xfer->hcpriv; 2313 #ifdef DIAGNOSTIC 2314 if (p == NULL) { 2315 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2316 splx(s); 2317 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2318 return; 2319 } 2320 #endif 2321 #ifdef OHCI_DEBUG 2322 if (ohcidebug > 1) { 2323 DPRINTF(("ohci_abort_xfer: sed=\n")); 2324 ohci_dump_ed(sc, sed); 2325 ohci_dump_tds(sc, p); 2326 } 2327 #endif 2328 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2329 hit = 0; 2330 for (; p->xfer == xfer; p = n) { 2331 hit |= headp == p->physaddr; 2332 n = p->nexttd; 2333 ohci_free_std(sc, p); 2334 } 2335 /* Zap headp register if hardware pointed inside the xfer. */ 2336 if (hit) { 2337 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2338 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2339 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2340 usb_syncmem(&sed->dma, 2341 sed->offs + offsetof(ohci_ed_t, ed_headp), 2342 sizeof(sed->ed.ed_headp), 2343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2344 } else { 2345 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2346 } 2347 2348 /* 2349 * Step 4: Turn on hardware again. 2350 */ 2351 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2352 sizeof(sed->ed.ed_flags), 2353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2354 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2355 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2356 sizeof(sed->ed.ed_flags), 2357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2358 2359 /* 2360 * Step 5: Execute callback. 2361 */ 2362 wake = xfer->hcflags & UXFER_ABORTWAIT; 2363 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2364 usb_transfer_complete(xfer); 2365 if (wake) 2366 wakeup(&xfer->hcflags); 2367 2368 splx(s); 2369 } 2370 2371 /* 2372 * Data structures and routines to emulate the root hub. 2373 */ 2374 Static usb_device_descriptor_t ohci_devd = { 2375 USB_DEVICE_DESCRIPTOR_SIZE, 2376 UDESC_DEVICE, /* type */ 2377 {0x00, 0x01}, /* USB version */ 2378 UDCLASS_HUB, /* class */ 2379 UDSUBCLASS_HUB, /* subclass */ 2380 UDPROTO_FSHUB, /* protocol */ 2381 64, /* max packet */ 2382 {0},{0},{0x00,0x01}, /* device id */ 2383 1,2,0, /* string indicies */ 2384 1 /* # of configurations */ 2385 }; 2386 2387 Static const usb_config_descriptor_t ohci_confd = { 2388 USB_CONFIG_DESCRIPTOR_SIZE, 2389 UDESC_CONFIG, 2390 {USB_CONFIG_DESCRIPTOR_SIZE + 2391 USB_INTERFACE_DESCRIPTOR_SIZE + 2392 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2393 1, 2394 1, 2395 0, 2396 UC_ATTR_MBO | UC_SELF_POWERED, 2397 0 /* max power */ 2398 }; 2399 2400 Static const usb_interface_descriptor_t ohci_ifcd = { 2401 USB_INTERFACE_DESCRIPTOR_SIZE, 2402 UDESC_INTERFACE, 2403 0, 2404 0, 2405 1, 2406 UICLASS_HUB, 2407 UISUBCLASS_HUB, 2408 UIPROTO_FSHUB, 2409 0 2410 }; 2411 2412 Static const usb_endpoint_descriptor_t ohci_endpd = { 2413 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2414 .bDescriptorType = UDESC_ENDPOINT, 2415 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2416 .bmAttributes = UE_INTERRUPT, 2417 .wMaxPacketSize = {8, 0}, /* max packet */ 2418 .bInterval = 255, 2419 }; 2420 2421 Static const usb_hub_descriptor_t ohci_hubd = { 2422 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2423 .bDescriptorType = UDESC_HUB, 2424 }; 2425 2426 /* 2427 * Simulate a hardware hub by handling all the necessary requests. 2428 */ 2429 Static usbd_status 2430 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2431 { 2432 usbd_status err; 2433 2434 /* Insert last in queue. */ 2435 err = usb_insert_transfer(xfer); 2436 if (err) 2437 return (err); 2438 2439 /* Pipe isn't running, start first */ 2440 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2441 } 2442 2443 Static usbd_status 2444 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2445 { 2446 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2447 usb_device_request_t *req; 2448 void *buf = NULL; 2449 int port, i; 2450 int s, len, value, index, l, totlen = 0; 2451 usb_port_status_t ps; 2452 usb_hub_descriptor_t hubd; 2453 usbd_status err; 2454 u_int32_t v; 2455 2456 if (sc->sc_dying) 2457 return (USBD_IOERROR); 2458 2459 #ifdef DIAGNOSTIC 2460 if (!(xfer->rqflags & URQ_REQUEST)) 2461 /* XXX panic */ 2462 return (USBD_INVAL); 2463 #endif 2464 req = &xfer->request; 2465 2466 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2467 req->bmRequestType, req->bRequest)); 2468 2469 len = UGETW(req->wLength); 2470 value = UGETW(req->wValue); 2471 index = UGETW(req->wIndex); 2472 2473 if (len != 0) 2474 buf = KERNADDR(&xfer->dmabuf, 0); 2475 2476 #define C(x,y) ((x) | ((y) << 8)) 2477 switch(C(req->bRequest, req->bmRequestType)) { 2478 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2479 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2480 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2481 /* 2482 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2483 * for the integrated root hub. 2484 */ 2485 break; 2486 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2487 if (len > 0) { 2488 *(u_int8_t *)buf = sc->sc_conf; 2489 totlen = 1; 2490 } 2491 break; 2492 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2493 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2494 if (len == 0) 2495 break; 2496 switch(value >> 8) { 2497 case UDESC_DEVICE: 2498 if ((value & 0xff) != 0) { 2499 err = USBD_IOERROR; 2500 goto ret; 2501 } 2502 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2503 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2504 memcpy(buf, &ohci_devd, l); 2505 break; 2506 case UDESC_CONFIG: 2507 if ((value & 0xff) != 0) { 2508 err = USBD_IOERROR; 2509 goto ret; 2510 } 2511 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2512 memcpy(buf, &ohci_confd, l); 2513 buf = (char *)buf + l; 2514 len -= l; 2515 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2516 totlen += l; 2517 memcpy(buf, &ohci_ifcd, l); 2518 buf = (char *)buf + l; 2519 len -= l; 2520 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2521 totlen += l; 2522 memcpy(buf, &ohci_endpd, l); 2523 break; 2524 case UDESC_STRING: 2525 #define sd ((usb_string_descriptor_t *)buf) 2526 switch (value & 0xff) { 2527 case 0: /* Language table */ 2528 totlen = usb_makelangtbl(sd, len); 2529 break; 2530 case 1: /* Vendor */ 2531 totlen = usb_makestrdesc(sd, len, 2532 sc->sc_vendor); 2533 break; 2534 case 2: /* Product */ 2535 totlen = usb_makestrdesc(sd, len, 2536 "OHCI root hub"); 2537 break; 2538 } 2539 #undef sd 2540 break; 2541 default: 2542 err = USBD_IOERROR; 2543 goto ret; 2544 } 2545 break; 2546 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2547 if (len > 0) { 2548 *(u_int8_t *)buf = 0; 2549 totlen = 1; 2550 } 2551 break; 2552 case C(UR_GET_STATUS, UT_READ_DEVICE): 2553 if (len > 1) { 2554 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2555 totlen = 2; 2556 } 2557 break; 2558 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2559 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2560 if (len > 1) { 2561 USETW(((usb_status_t *)buf)->wStatus, 0); 2562 totlen = 2; 2563 } 2564 break; 2565 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2566 if (value >= USB_MAX_DEVICES) { 2567 err = USBD_IOERROR; 2568 goto ret; 2569 } 2570 sc->sc_addr = value; 2571 break; 2572 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2573 if (value != 0 && value != 1) { 2574 err = USBD_IOERROR; 2575 goto ret; 2576 } 2577 sc->sc_conf = value; 2578 break; 2579 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2580 break; 2581 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2582 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2583 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2584 err = USBD_IOERROR; 2585 goto ret; 2586 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2587 break; 2588 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2589 break; 2590 /* Hub requests */ 2591 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2592 break; 2593 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2594 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2595 "port=%d feature=%d\n", 2596 index, value)); 2597 if (index < 1 || index > sc->sc_noport) { 2598 err = USBD_IOERROR; 2599 goto ret; 2600 } 2601 port = OHCI_RH_PORT_STATUS(index); 2602 switch(value) { 2603 case UHF_PORT_ENABLE: 2604 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2605 break; 2606 case UHF_PORT_SUSPEND: 2607 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2608 break; 2609 case UHF_PORT_POWER: 2610 /* Yes, writing to the LOW_SPEED bit clears power. */ 2611 OWRITE4(sc, port, UPS_LOW_SPEED); 2612 break; 2613 case UHF_C_PORT_CONNECTION: 2614 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2615 break; 2616 case UHF_C_PORT_ENABLE: 2617 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2618 break; 2619 case UHF_C_PORT_SUSPEND: 2620 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2621 break; 2622 case UHF_C_PORT_OVER_CURRENT: 2623 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2624 break; 2625 case UHF_C_PORT_RESET: 2626 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2627 break; 2628 default: 2629 err = USBD_IOERROR; 2630 goto ret; 2631 } 2632 switch(value) { 2633 case UHF_C_PORT_CONNECTION: 2634 case UHF_C_PORT_ENABLE: 2635 case UHF_C_PORT_SUSPEND: 2636 case UHF_C_PORT_OVER_CURRENT: 2637 case UHF_C_PORT_RESET: 2638 /* Enable RHSC interrupt if condition is cleared. */ 2639 if ((OREAD4(sc, port) >> 16) == 0) 2640 ohci_rhsc_enable(sc); 2641 break; 2642 default: 2643 break; 2644 } 2645 break; 2646 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2647 if (len == 0) 2648 break; 2649 if ((value & 0xff) != 0) { 2650 err = USBD_IOERROR; 2651 goto ret; 2652 } 2653 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2654 hubd = ohci_hubd; 2655 hubd.bNbrPorts = sc->sc_noport; 2656 USETW(hubd.wHubCharacteristics, 2657 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2658 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2659 /* XXX overcurrent */ 2660 ); 2661 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2662 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2663 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2664 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2665 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2666 l = min(len, hubd.bDescLength); 2667 totlen = l; 2668 memcpy(buf, &hubd, l); 2669 break; 2670 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2671 if (len != 4) { 2672 err = USBD_IOERROR; 2673 goto ret; 2674 } 2675 memset(buf, 0, len); /* ? XXX */ 2676 totlen = len; 2677 break; 2678 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2679 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2680 index)); 2681 if (index < 1 || index > sc->sc_noport) { 2682 err = USBD_IOERROR; 2683 goto ret; 2684 } 2685 if (len != 4) { 2686 err = USBD_IOERROR; 2687 goto ret; 2688 } 2689 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2690 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2691 v)); 2692 USETW(ps.wPortStatus, v); 2693 USETW(ps.wPortChange, v >> 16); 2694 l = min(len, sizeof ps); 2695 memcpy(buf, &ps, l); 2696 totlen = l; 2697 break; 2698 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2699 err = USBD_IOERROR; 2700 goto ret; 2701 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2702 break; 2703 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2704 if (index < 1 || index > sc->sc_noport) { 2705 err = USBD_IOERROR; 2706 goto ret; 2707 } 2708 port = OHCI_RH_PORT_STATUS(index); 2709 switch(value) { 2710 case UHF_PORT_ENABLE: 2711 OWRITE4(sc, port, UPS_PORT_ENABLED); 2712 break; 2713 case UHF_PORT_SUSPEND: 2714 OWRITE4(sc, port, UPS_SUSPEND); 2715 break; 2716 case UHF_PORT_RESET: 2717 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2718 index)); 2719 OWRITE4(sc, port, UPS_RESET); 2720 for (i = 0; i < 5; i++) { 2721 usb_delay_ms(&sc->sc_bus, 2722 USB_PORT_ROOT_RESET_DELAY); 2723 if (sc->sc_dying) { 2724 err = USBD_IOERROR; 2725 goto ret; 2726 } 2727 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2728 break; 2729 } 2730 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2731 index, OREAD4(sc, port))); 2732 break; 2733 case UHF_PORT_POWER: 2734 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2735 "%d\n", index)); 2736 OWRITE4(sc, port, UPS_PORT_POWER); 2737 break; 2738 default: 2739 err = USBD_IOERROR; 2740 goto ret; 2741 } 2742 break; 2743 default: 2744 err = USBD_IOERROR; 2745 goto ret; 2746 } 2747 xfer->actlen = totlen; 2748 err = USBD_NORMAL_COMPLETION; 2749 ret: 2750 xfer->status = err; 2751 s = splusb(); 2752 usb_transfer_complete(xfer); 2753 splx(s); 2754 return (USBD_IN_PROGRESS); 2755 } 2756 2757 /* Abort a root control request. */ 2758 Static void 2759 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2760 { 2761 /* Nothing to do, all transfers are synchronous. */ 2762 } 2763 2764 /* Close the root pipe. */ 2765 Static void 2766 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2767 { 2768 DPRINTF(("ohci_root_ctrl_close\n")); 2769 /* Nothing to do. */ 2770 } 2771 2772 Static usbd_status 2773 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2774 { 2775 usbd_status err; 2776 2777 /* Insert last in queue. */ 2778 err = usb_insert_transfer(xfer); 2779 if (err) 2780 return (err); 2781 2782 /* Pipe isn't running, start first */ 2783 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2784 } 2785 2786 Static usbd_status 2787 ohci_root_intr_start(usbd_xfer_handle xfer) 2788 { 2789 usbd_pipe_handle pipe = xfer->pipe; 2790 ohci_softc_t *sc = pipe->device->bus->hci_private; 2791 2792 if (sc->sc_dying) 2793 return (USBD_IOERROR); 2794 2795 sc->sc_intrxfer = xfer; 2796 2797 return (USBD_IN_PROGRESS); 2798 } 2799 2800 /* Abort a root interrupt request. */ 2801 Static void 2802 ohci_root_intr_abort(usbd_xfer_handle xfer) 2803 { 2804 int s; 2805 2806 if (xfer->pipe->intrxfer == xfer) { 2807 DPRINTF(("ohci_root_intr_abort: remove\n")); 2808 xfer->pipe->intrxfer = NULL; 2809 } 2810 xfer->status = USBD_CANCELLED; 2811 s = splusb(); 2812 usb_transfer_complete(xfer); 2813 splx(s); 2814 } 2815 2816 /* Close the root pipe. */ 2817 Static void 2818 ohci_root_intr_close(usbd_pipe_handle pipe) 2819 { 2820 ohci_softc_t *sc = pipe->device->bus->hci_private; 2821 2822 DPRINTF(("ohci_root_intr_close\n")); 2823 2824 sc->sc_intrxfer = NULL; 2825 } 2826 2827 /************************/ 2828 2829 Static usbd_status 2830 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2831 { 2832 usbd_status err; 2833 2834 /* Insert last in queue. */ 2835 err = usb_insert_transfer(xfer); 2836 if (err) 2837 return (err); 2838 2839 /* Pipe isn't running, start first */ 2840 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2841 } 2842 2843 Static usbd_status 2844 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2845 { 2846 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2847 usbd_status err; 2848 2849 if (sc->sc_dying) 2850 return (USBD_IOERROR); 2851 2852 #ifdef DIAGNOSTIC 2853 if (!(xfer->rqflags & URQ_REQUEST)) { 2854 /* XXX panic */ 2855 printf("ohci_device_ctrl_transfer: not a request\n"); 2856 return (USBD_INVAL); 2857 } 2858 #endif 2859 2860 err = ohci_device_request(xfer); 2861 if (err) 2862 return (err); 2863 2864 if (sc->sc_bus.use_polling) 2865 ohci_waitintr(sc, xfer); 2866 return (USBD_IN_PROGRESS); 2867 } 2868 2869 /* Abort a device control request. */ 2870 Static void 2871 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2872 { 2873 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2874 ohci_abort_xfer(xfer, USBD_CANCELLED); 2875 } 2876 2877 /* Close a device control pipe. */ 2878 Static void 2879 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2880 { 2881 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2882 ohci_softc_t *sc = pipe->device->bus->hci_private; 2883 2884 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2885 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2886 ohci_free_std(sc, opipe->tail.td); 2887 } 2888 2889 /************************/ 2890 2891 Static void 2892 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2893 { 2894 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2895 ohci_softc_t *sc = pipe->device->bus->hci_private; 2896 2897 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2898 } 2899 2900 Static void 2901 ohci_noop(usbd_pipe_handle pipe) 2902 { 2903 } 2904 2905 Static usbd_status 2906 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2907 { 2908 usbd_status err; 2909 2910 /* Insert last in queue. */ 2911 err = usb_insert_transfer(xfer); 2912 if (err) 2913 return (err); 2914 2915 /* Pipe isn't running, start first */ 2916 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2917 } 2918 2919 Static usbd_status 2920 ohci_device_bulk_start(usbd_xfer_handle xfer) 2921 { 2922 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2923 usbd_device_handle dev = opipe->pipe.device; 2924 ohci_softc_t *sc = dev->bus->hci_private; 2925 int addr = dev->address; 2926 ohci_soft_td_t *data, *tail, *tdp; 2927 ohci_soft_ed_t *sed; 2928 int s, len, isread, endpt; 2929 usbd_status err; 2930 2931 if (sc->sc_dying) 2932 return (USBD_IOERROR); 2933 2934 #ifdef DIAGNOSTIC 2935 if (xfer->rqflags & URQ_REQUEST) { 2936 /* XXX panic */ 2937 printf("ohci_device_bulk_start: a request\n"); 2938 return (USBD_INVAL); 2939 } 2940 #endif 2941 2942 len = xfer->length; 2943 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2944 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2945 sed = opipe->sed; 2946 2947 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2948 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2949 endpt)); 2950 2951 opipe->u.bulk.isread = isread; 2952 opipe->u.bulk.length = len; 2953 2954 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2956 /* Update device address */ 2957 sed->ed.ed_flags = HTOO32( 2958 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2959 OHCI_ED_SET_FA(addr)); 2960 2961 /* Allocate a chain of new TDs (including a new tail). */ 2962 data = opipe->tail.td; 2963 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2964 data, &tail); 2965 /* We want interrupt at the end of the transfer. */ 2966 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2967 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2968 tail->flags |= OHCI_CALL_DONE; 2969 tail = tail->nexttd; /* point at sentinel */ 2970 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2971 sizeof(tail->td.td_flags), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 if (err) 2974 return (err); 2975 2976 tail->xfer = NULL; 2977 xfer->hcpriv = data; 2978 2979 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2980 "td_cbp=0x%08x td_be=0x%08x\n", 2981 (int)O32TOH(sed->ed.ed_flags), 2982 (int)O32TOH(data->td.td_flags), 2983 (int)O32TOH(data->td.td_cbp), 2984 (int)O32TOH(data->td.td_be))); 2985 2986 #ifdef OHCI_DEBUG 2987 if (ohcidebug > 5) { 2988 ohci_dump_ed(sc, sed); 2989 ohci_dump_tds(sc, data); 2990 } 2991 #endif 2992 2993 /* Insert ED in schedule */ 2994 s = splusb(); 2995 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2996 tdp->xfer = xfer; 2997 } 2998 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2999 opipe->tail.td = tail; 3000 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3001 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3002 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3003 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3004 if (xfer->timeout && !sc->sc_bus.use_polling) { 3005 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3006 ohci_timeout, xfer); 3007 } 3008 3009 #if 0 3010 /* This goes wrong if we are too slow. */ 3011 if (ohcidebug > 10) { 3012 delay(10000); 3013 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3014 OREAD4(sc, OHCI_COMMAND_STATUS))); 3015 ohci_dump_ed(sc, sed); 3016 ohci_dump_tds(sc, data); 3017 } 3018 #endif 3019 3020 splx(s); 3021 3022 return (USBD_IN_PROGRESS); 3023 } 3024 3025 Static void 3026 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3027 { 3028 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3029 ohci_abort_xfer(xfer, USBD_CANCELLED); 3030 } 3031 3032 /* 3033 * Close a device bulk pipe. 3034 */ 3035 Static void 3036 ohci_device_bulk_close(usbd_pipe_handle pipe) 3037 { 3038 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3039 ohci_softc_t *sc = pipe->device->bus->hci_private; 3040 3041 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3042 ohci_close_pipe(pipe, sc->sc_bulk_head); 3043 ohci_free_std(sc, opipe->tail.td); 3044 } 3045 3046 /************************/ 3047 3048 Static usbd_status 3049 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3050 { 3051 usbd_status err; 3052 3053 /* Insert last in queue. */ 3054 err = usb_insert_transfer(xfer); 3055 if (err) 3056 return (err); 3057 3058 /* Pipe isn't running, start first */ 3059 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3060 } 3061 3062 Static usbd_status 3063 ohci_device_intr_start(usbd_xfer_handle xfer) 3064 { 3065 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3066 usbd_device_handle dev = opipe->pipe.device; 3067 ohci_softc_t *sc = dev->bus->hci_private; 3068 ohci_soft_ed_t *sed = opipe->sed; 3069 ohci_soft_td_t *data, *tail; 3070 int s, len, isread, endpt; 3071 3072 if (sc->sc_dying) 3073 return (USBD_IOERROR); 3074 3075 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3076 "flags=%d priv=%p\n", 3077 xfer, xfer->length, xfer->flags, xfer->priv)); 3078 3079 #ifdef DIAGNOSTIC 3080 if (xfer->rqflags & URQ_REQUEST) 3081 panic("ohci_device_intr_transfer: a request"); 3082 #endif 3083 3084 len = xfer->length; 3085 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3086 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3087 3088 data = opipe->tail.td; 3089 tail = ohci_alloc_std(sc); 3090 if (tail == NULL) 3091 return (USBD_NOMEM); 3092 tail->xfer = NULL; 3093 3094 data->td.td_flags = HTOO32( 3095 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3096 OHCI_TD_NOCC | 3097 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3098 if (xfer->flags & USBD_SHORT_XFER_OK) 3099 data->td.td_flags |= HTOO32(OHCI_TD_R); 3100 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3101 data->nexttd = tail; 3102 data->td.td_nexttd = HTOO32(tail->physaddr); 3103 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3104 data->len = len; 3105 data->xfer = xfer; 3106 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3107 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 xfer->hcpriv = data; 3110 3111 #ifdef OHCI_DEBUG 3112 if (ohcidebug > 5) { 3113 DPRINTF(("ohci_device_intr_transfer:\n")); 3114 ohci_dump_ed(sc, sed); 3115 ohci_dump_tds(sc, data); 3116 } 3117 #endif 3118 3119 /* Insert ED in schedule */ 3120 s = splusb(); 3121 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3122 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3123 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3124 opipe->tail.td = tail; 3125 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3126 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3127 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3128 3129 #if 0 3130 /* 3131 * This goes horribly wrong, printing thousands of descriptors, 3132 * because false references are followed due to the fact that the 3133 * TD is gone. 3134 */ 3135 if (ohcidebug > 5) { 3136 usb_delay_ms(&sc->sc_bus, 5); 3137 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3138 OREAD4(sc, OHCI_COMMAND_STATUS))); 3139 ohci_dump_ed(sc, sed); 3140 ohci_dump_tds(sc, data); 3141 } 3142 #endif 3143 splx(s); 3144 3145 return (USBD_IN_PROGRESS); 3146 } 3147 3148 /* Abort a device control request. */ 3149 Static void 3150 ohci_device_intr_abort(usbd_xfer_handle xfer) 3151 { 3152 if (xfer->pipe->intrxfer == xfer) { 3153 DPRINTF(("ohci_device_intr_abort: remove\n")); 3154 xfer->pipe->intrxfer = NULL; 3155 } 3156 ohci_abort_xfer(xfer, USBD_CANCELLED); 3157 } 3158 3159 /* Close a device interrupt pipe. */ 3160 Static void 3161 ohci_device_intr_close(usbd_pipe_handle pipe) 3162 { 3163 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3164 ohci_softc_t *sc = pipe->device->bus->hci_private; 3165 int nslots = opipe->u.intr.nslots; 3166 int pos = opipe->u.intr.pos; 3167 int j; 3168 ohci_soft_ed_t *p, *sed = opipe->sed; 3169 int s; 3170 3171 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3172 pipe, nslots, pos)); 3173 s = splusb(); 3174 usb_syncmem(&sed->dma, sed->offs, 3175 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3176 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3177 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3178 sizeof(sed->ed.ed_flags), 3179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3180 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3181 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3182 usb_delay_ms(&sc->sc_bus, 2); 3183 3184 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3185 continue; 3186 #ifdef DIAGNOSTIC 3187 if (p == NULL) 3188 panic("ohci_device_intr_close: ED not found"); 3189 #endif 3190 p->next = sed->next; 3191 p->ed.ed_nexted = sed->ed.ed_nexted; 3192 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3193 sizeof(p->ed.ed_nexted), 3194 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3195 splx(s); 3196 3197 for (j = 0; j < nslots; j++) 3198 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3199 3200 ohci_free_std(sc, opipe->tail.td); 3201 ohci_free_sed(sc, opipe->sed); 3202 } 3203 3204 Static usbd_status 3205 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3206 { 3207 int i, j, s, best; 3208 u_int npoll, slow, shigh, nslots; 3209 u_int bestbw, bw; 3210 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3211 3212 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3213 if (ival == 0) { 3214 printf("ohci_setintr: 0 interval\n"); 3215 return (USBD_INVAL); 3216 } 3217 3218 npoll = OHCI_NO_INTRS; 3219 while (npoll > ival) 3220 npoll /= 2; 3221 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3222 3223 /* 3224 * We now know which level in the tree the ED must go into. 3225 * Figure out which slot has most bandwidth left over. 3226 * Slots to examine: 3227 * npoll 3228 * 1 0 3229 * 2 1 2 3230 * 4 3 4 5 6 3231 * 8 7 8 9 10 11 12 13 14 3232 * N (N-1) .. (N-1+N-1) 3233 */ 3234 slow = npoll-1; 3235 shigh = slow + npoll; 3236 nslots = OHCI_NO_INTRS / npoll; 3237 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3238 bw = 0; 3239 for (j = 0; j < nslots; j++) 3240 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3241 if (bw < bestbw) { 3242 best = i; 3243 bestbw = bw; 3244 } 3245 } 3246 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3247 best, slow, shigh, bestbw)); 3248 3249 s = splusb(); 3250 hsed = sc->sc_eds[best]; 3251 sed->next = hsed->next; 3252 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3253 sizeof(hsed->ed.ed_flags), 3254 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3255 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3256 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3257 sizeof(sed->ed.ed_flags), 3258 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3259 hsed->next = sed; 3260 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3261 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3262 sizeof(hsed->ed.ed_flags), 3263 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3264 splx(s); 3265 3266 for (j = 0; j < nslots; j++) 3267 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3268 opipe->u.intr.nslots = nslots; 3269 opipe->u.intr.pos = best; 3270 3271 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3272 return (USBD_NORMAL_COMPLETION); 3273 } 3274 3275 /***********************/ 3276 3277 usbd_status 3278 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3279 { 3280 usbd_status err; 3281 3282 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3283 3284 /* Put it on our queue, */ 3285 err = usb_insert_transfer(xfer); 3286 3287 /* bail out on error, */ 3288 if (err && err != USBD_IN_PROGRESS) 3289 return (err); 3290 3291 /* XXX should check inuse here */ 3292 3293 /* insert into schedule, */ 3294 ohci_device_isoc_enter(xfer); 3295 3296 /* and start if the pipe wasn't running */ 3297 if (!err) 3298 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3299 3300 return (err); 3301 } 3302 3303 void 3304 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3305 { 3306 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3307 usbd_device_handle dev = opipe->pipe.device; 3308 ohci_softc_t *sc = dev->bus->hci_private; 3309 ohci_soft_ed_t *sed = opipe->sed; 3310 struct iso *iso = &opipe->u.iso; 3311 ohci_soft_itd_t *sitd, *nsitd; 3312 ohci_physaddr_t buf, offs, noffs, bp0; 3313 int i, ncur, nframes; 3314 int s; 3315 3316 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3317 "nframes=%d\n", 3318 iso->inuse, iso->next, xfer, xfer->nframes)); 3319 3320 if (sc->sc_dying) 3321 return; 3322 3323 if (iso->next == -1) { 3324 /* Not in use yet, schedule it a few frames ahead. */ 3325 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3326 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3327 iso->next)); 3328 } 3329 3330 sitd = opipe->tail.itd; 3331 buf = DMAADDR(&xfer->dmabuf, 0); 3332 bp0 = OHCI_PAGE(buf); 3333 offs = OHCI_PAGE_OFFSET(buf); 3334 nframes = xfer->nframes; 3335 xfer->hcpriv = sitd; 3336 for (i = ncur = 0; i < nframes; i++, ncur++) { 3337 noffs = offs + xfer->frlengths[i]; 3338 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3339 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3340 3341 /* Allocate next ITD */ 3342 nsitd = ohci_alloc_sitd(sc); 3343 if (nsitd == NULL) { 3344 /* XXX what now? */ 3345 printf("%s: isoc TD alloc failed\n", 3346 device_xname(sc->sc_dev)); 3347 return; 3348 } 3349 3350 /* Fill current ITD */ 3351 sitd->itd.itd_flags = HTOO32( 3352 OHCI_ITD_NOCC | 3353 OHCI_ITD_SET_SF(iso->next) | 3354 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3355 OHCI_ITD_SET_FC(ncur)); 3356 sitd->itd.itd_bp0 = HTOO32(bp0); 3357 sitd->nextitd = nsitd; 3358 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3359 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3360 sitd->xfer = xfer; 3361 sitd->flags = 0; 3362 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3363 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3364 3365 sitd = nsitd; 3366 iso->next = iso->next + ncur; 3367 bp0 = OHCI_PAGE(buf + offs); 3368 ncur = 0; 3369 } 3370 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3371 offs = noffs; 3372 } 3373 nsitd = ohci_alloc_sitd(sc); 3374 if (nsitd == NULL) { 3375 /* XXX what now? */ 3376 printf("%s: isoc TD alloc failed\n", 3377 device_xname(sc->sc_dev)); 3378 return; 3379 } 3380 /* Fixup last used ITD */ 3381 sitd->itd.itd_flags = HTOO32( 3382 OHCI_ITD_NOCC | 3383 OHCI_ITD_SET_SF(iso->next) | 3384 OHCI_ITD_SET_DI(0) | 3385 OHCI_ITD_SET_FC(ncur)); 3386 sitd->itd.itd_bp0 = HTOO32(bp0); 3387 sitd->nextitd = nsitd; 3388 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3389 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3390 sitd->xfer = xfer; 3391 sitd->flags = OHCI_CALL_DONE; 3392 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3394 3395 iso->next = iso->next + ncur; 3396 iso->inuse += nframes; 3397 3398 xfer->actlen = offs; /* XXX pretend we did it all */ 3399 3400 xfer->status = USBD_IN_PROGRESS; 3401 3402 #ifdef OHCI_DEBUG 3403 if (ohcidebug > 5) { 3404 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3405 O32TOH(sc->sc_hcca->hcca_frame_number))); 3406 ohci_dump_itds(sc, xfer->hcpriv); 3407 ohci_dump_ed(sc, sed); 3408 } 3409 #endif 3410 3411 s = splusb(); 3412 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3413 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3414 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3415 opipe->tail.itd = nsitd; 3416 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3417 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3418 sizeof(sed->ed.ed_flags), 3419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3420 splx(s); 3421 3422 #ifdef OHCI_DEBUG 3423 if (ohcidebug > 5) { 3424 delay(150000); 3425 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3426 O32TOH(sc->sc_hcca->hcca_frame_number))); 3427 ohci_dump_itds(sc, xfer->hcpriv); 3428 ohci_dump_ed(sc, sed); 3429 } 3430 #endif 3431 } 3432 3433 usbd_status 3434 ohci_device_isoc_start(usbd_xfer_handle xfer) 3435 { 3436 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3437 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3438 3439 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3440 3441 if (sc->sc_dying) 3442 return (USBD_IOERROR); 3443 3444 #ifdef DIAGNOSTIC 3445 if (xfer->status != USBD_IN_PROGRESS) 3446 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3447 #endif 3448 3449 /* XXX anything to do? */ 3450 3451 return (USBD_IN_PROGRESS); 3452 } 3453 3454 void 3455 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3456 { 3457 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3458 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3459 ohci_soft_ed_t *sed; 3460 ohci_soft_itd_t *sitd; 3461 int s; 3462 3463 s = splusb(); 3464 3465 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3466 3467 /* Transfer is already done. */ 3468 if (xfer->status != USBD_NOT_STARTED && 3469 xfer->status != USBD_IN_PROGRESS) { 3470 splx(s); 3471 printf("ohci_device_isoc_abort: early return\n"); 3472 return; 3473 } 3474 3475 /* Give xfer the requested abort code. */ 3476 xfer->status = USBD_CANCELLED; 3477 3478 sed = opipe->sed; 3479 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3480 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3481 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3482 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3483 sizeof(sed->ed.ed_flags), 3484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3485 3486 sitd = xfer->hcpriv; 3487 #ifdef DIAGNOSTIC 3488 if (sitd == NULL) { 3489 splx(s); 3490 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3491 return; 3492 } 3493 #endif 3494 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3495 #ifdef DIAGNOSTIC 3496 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3497 sitd->isdone = 1; 3498 #endif 3499 } 3500 3501 splx(s); 3502 3503 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3504 3505 s = splusb(); 3506 3507 /* Run callback. */ 3508 usb_transfer_complete(xfer); 3509 3510 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3511 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3512 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3513 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3514 3515 splx(s); 3516 } 3517 3518 void 3519 ohci_device_isoc_done(usbd_xfer_handle xfer) 3520 { 3521 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3522 } 3523 3524 usbd_status 3525 ohci_setup_isoc(usbd_pipe_handle pipe) 3526 { 3527 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3528 ohci_softc_t *sc = pipe->device->bus->hci_private; 3529 struct iso *iso = &opipe->u.iso; 3530 int s; 3531 3532 iso->next = -1; 3533 iso->inuse = 0; 3534 3535 s = splusb(); 3536 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3537 splx(s); 3538 3539 return (USBD_NORMAL_COMPLETION); 3540 } 3541 3542 void 3543 ohci_device_isoc_close(usbd_pipe_handle pipe) 3544 { 3545 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3546 ohci_softc_t *sc = pipe->device->bus->hci_private; 3547 3548 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3549 ohci_close_pipe(pipe, sc->sc_isoc_head); 3550 #ifdef DIAGNOSTIC 3551 opipe->tail.itd->isdone = 1; 3552 #endif 3553 ohci_free_sitd(sc, opipe->tail.itd); 3554 } 3555
Indexes created Fri Oct 03 02:09:57 GMT 2025