ohci.c revision 1.217
1 /* $NetBSD: ohci.c,v 1.217 2011/07/30 20:05:36 jmcneill Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology. 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.217 2011/07/30 20:05:36 jmcneill Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/device.h> 53 #include <sys/select.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 57 #include <sys/bus.h> 58 #include <machine/endian.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/ohcireg.h> 67 #include <dev/usb/ohcivar.h> 68 #include <dev/usb/usbroothub_subr.h> 69 70 71 72 #ifdef OHCI_DEBUG 73 #define DPRINTF(x) if (ohcidebug) printf x 74 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 75 int ohcidebug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n,x) 79 #endif 80 81 #if BYTE_ORDER == BIG_ENDIAN 82 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 83 #else 84 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 85 #endif 86 87 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 88 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 89 #define HTOO16(val) O16TOH(val) 90 #define HTOO32(val) O32TOH(val) 91 92 struct ohci_pipe; 93 94 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 95 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 96 97 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 98 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 99 100 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 101 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 102 103 #if 0 104 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 105 ohci_soft_td_t *); 106 #endif 107 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 108 ohci_softc_t *, int, int, usbd_xfer_handle, 109 ohci_soft_td_t *, ohci_soft_td_t **); 110 111 Static usbd_status ohci_open(usbd_pipe_handle); 112 Static void ohci_poll(struct usbd_bus *); 113 Static void ohci_softintr(void *); 114 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 115 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 116 117 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 118 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 121 Static void ohci_rem_ed(ohci_soft_ed_t *, ohci_soft_ed_t *); 122 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 123 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 124 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 125 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 126 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 127 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 128 129 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 130 Static void ohci_device_isoc_enter(usbd_xfer_handle); 131 132 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 133 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 134 135 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 136 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 137 138 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 139 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 140 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 141 Static void ohci_root_ctrl_close(usbd_pipe_handle); 142 Static void ohci_root_ctrl_done(usbd_xfer_handle); 143 144 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 145 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 146 Static void ohci_root_intr_abort(usbd_xfer_handle); 147 Static void ohci_root_intr_close(usbd_pipe_handle); 148 Static void ohci_root_intr_done(usbd_xfer_handle); 149 150 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 151 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 152 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 153 Static void ohci_device_ctrl_close(usbd_pipe_handle); 154 Static void ohci_device_ctrl_done(usbd_xfer_handle); 155 156 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 157 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 158 Static void ohci_device_bulk_abort(usbd_xfer_handle); 159 Static void ohci_device_bulk_close(usbd_pipe_handle); 160 Static void ohci_device_bulk_done(usbd_xfer_handle); 161 162 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 164 Static void ohci_device_intr_abort(usbd_xfer_handle); 165 Static void ohci_device_intr_close(usbd_pipe_handle); 166 Static void ohci_device_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 169 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 170 Static void ohci_device_isoc_abort(usbd_xfer_handle); 171 Static void ohci_device_isoc_close(usbd_pipe_handle); 172 Static void ohci_device_isoc_done(usbd_xfer_handle); 173 174 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 175 struct ohci_pipe *pipe, int ival); 176 177 Static void ohci_timeout(void *); 178 Static void ohci_timeout_task(void *); 179 Static void ohci_rhsc_enable(void *); 180 181 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 182 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 183 184 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 185 Static void ohci_noop(usbd_pipe_handle pipe); 186 187 #ifdef OHCI_DEBUG 188 Static void ohci_dumpregs(ohci_softc_t *); 189 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 191 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 192 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 193 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 194 #endif 195 196 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 197 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 198 #define OWRITE1(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 #define OWRITE2(sc, r, x) \ 201 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 202 #define OWRITE4(sc, r, x) \ 203 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 204 static __inline uint8_t 205 OREAD1(ohci_softc_t *sc, bus_size_t r) 206 { 207 208 OBARR(sc); 209 return bus_space_read_1(sc->iot, sc->ioh, r); 210 } 211 212 static __inline uint16_t 213 OREAD2(ohci_softc_t *sc, bus_size_t r) 214 { 215 216 OBARR(sc); 217 return bus_space_read_2(sc->iot, sc->ioh, r); 218 } 219 220 static __inline uint32_t 221 OREAD4(ohci_softc_t *sc, bus_size_t r) 222 { 223 224 OBARR(sc); 225 return bus_space_read_4(sc->iot, sc->ioh, r); 226 } 227 228 /* Reverse the bits in a value 0 .. 31 */ 229 Static u_int8_t revbits[OHCI_NO_INTRS] = 230 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 231 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 232 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 233 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 234 235 struct ohci_pipe { 236 struct usbd_pipe pipe; 237 ohci_soft_ed_t *sed; 238 union { 239 ohci_soft_td_t *td; 240 ohci_soft_itd_t *itd; 241 } tail; 242 /* Info needed for different pipe kinds. */ 243 union { 244 /* Control pipe */ 245 struct { 246 usb_dma_t reqdma; 247 u_int length; 248 ohci_soft_td_t *setup, *data, *stat; 249 } ctl; 250 /* Interrupt pipe */ 251 struct { 252 int nslots; 253 int pos; 254 } intr; 255 /* Bulk pipe */ 256 struct { 257 u_int length; 258 int isread; 259 } bulk; 260 /* Iso pipe */ 261 struct iso { 262 int next, inuse; 263 } iso; 264 } u; 265 }; 266 267 #define OHCI_INTR_ENDPT 1 268 269 Static const struct usbd_bus_methods ohci_bus_methods = { 270 ohci_open, 271 ohci_softintr, 272 ohci_poll, 273 ohci_allocm, 274 ohci_freem, 275 ohci_allocx, 276 ohci_freex, 277 }; 278 279 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 280 ohci_root_ctrl_transfer, 281 ohci_root_ctrl_start, 282 ohci_root_ctrl_abort, 283 ohci_root_ctrl_close, 284 ohci_noop, 285 ohci_root_ctrl_done, 286 }; 287 288 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 289 ohci_root_intr_transfer, 290 ohci_root_intr_start, 291 ohci_root_intr_abort, 292 ohci_root_intr_close, 293 ohci_noop, 294 ohci_root_intr_done, 295 }; 296 297 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 298 ohci_device_ctrl_transfer, 299 ohci_device_ctrl_start, 300 ohci_device_ctrl_abort, 301 ohci_device_ctrl_close, 302 ohci_noop, 303 ohci_device_ctrl_done, 304 }; 305 306 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 307 ohci_device_intr_transfer, 308 ohci_device_intr_start, 309 ohci_device_intr_abort, 310 ohci_device_intr_close, 311 ohci_device_clear_toggle, 312 ohci_device_intr_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 316 ohci_device_bulk_transfer, 317 ohci_device_bulk_start, 318 ohci_device_bulk_abort, 319 ohci_device_bulk_close, 320 ohci_device_clear_toggle, 321 ohci_device_bulk_done, 322 }; 323 324 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 325 ohci_device_isoc_transfer, 326 ohci_device_isoc_start, 327 ohci_device_isoc_abort, 328 ohci_device_isoc_close, 329 ohci_noop, 330 ohci_device_isoc_done, 331 }; 332 333 int 334 ohci_activate(device_t self, enum devact act) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 switch (act) { 339 case DVACT_DEACTIVATE: 340 sc->sc_dying = 1; 341 return 0; 342 default: 343 return EOPNOTSUPP; 344 } 345 } 346 347 void 348 ohci_childdet(device_t self, device_t child) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 KASSERT(sc->sc_child == child); 353 sc->sc_child = NULL; 354 } 355 356 int 357 ohci_detach(struct ohci_softc *sc, int flags) 358 { 359 int rv = 0; 360 usbd_xfer_handle xfer; 361 362 if (sc->sc_child != NULL) 363 rv = config_detach(sc->sc_child, flags); 364 365 if (rv != 0) 366 return (rv); 367 368 callout_stop(&sc->sc_tmo_rhsc); 369 370 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 371 callout_destroy(&sc->sc_tmo_rhsc); 372 373 if (sc->sc_hcca != NULL) 374 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 375 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 376 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 377 free(xfer, M_USB); 378 } 379 380 return (rv); 381 } 382 383 ohci_soft_ed_t * 384 ohci_alloc_sed(ohci_softc_t *sc) 385 { 386 ohci_soft_ed_t *sed; 387 usbd_status err; 388 int i, offs; 389 usb_dma_t dma; 390 391 if (sc->sc_freeeds == NULL) { 392 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 393 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 394 OHCI_ED_ALIGN, &dma); 395 if (err) 396 return (0); 397 for(i = 0; i < OHCI_SED_CHUNK; i++) { 398 offs = i * OHCI_SED_SIZE; 399 sed = KERNADDR(&dma, offs); 400 sed->physaddr = DMAADDR(&dma, offs); 401 sed->dma = dma; 402 sed->offs = offs; 403 sed->next = sc->sc_freeeds; 404 sc->sc_freeeds = sed; 405 } 406 } 407 sed = sc->sc_freeeds; 408 sc->sc_freeeds = sed->next; 409 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 410 sed->next = 0; 411 return (sed); 412 } 413 414 void 415 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 416 { 417 sed->next = sc->sc_freeeds; 418 sc->sc_freeeds = sed; 419 } 420 421 ohci_soft_td_t * 422 ohci_alloc_std(ohci_softc_t *sc) 423 { 424 ohci_soft_td_t *std; 425 usbd_status err; 426 int i, offs; 427 usb_dma_t dma; 428 int s; 429 430 if (sc->sc_freetds == NULL) { 431 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 432 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 433 OHCI_TD_ALIGN, &dma); 434 if (err) 435 return (NULL); 436 s = splusb(); 437 for(i = 0; i < OHCI_STD_CHUNK; i++) { 438 offs = i * OHCI_STD_SIZE; 439 std = KERNADDR(&dma, offs); 440 std->physaddr = DMAADDR(&dma, offs); 441 std->dma = dma; 442 std->offs = offs; 443 std->nexttd = sc->sc_freetds; 444 sc->sc_freetds = std; 445 } 446 splx(s); 447 } 448 449 s = splusb(); 450 std = sc->sc_freetds; 451 sc->sc_freetds = std->nexttd; 452 memset(&std->td, 0, sizeof(ohci_td_t)); 453 std->nexttd = NULL; 454 std->xfer = NULL; 455 ohci_hash_add_td(sc, std); 456 splx(s); 457 458 return (std); 459 } 460 461 void 462 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 463 { 464 int s; 465 466 s = splusb(); 467 ohci_hash_rem_td(sc, std); 468 std->nexttd = sc->sc_freetds; 469 sc->sc_freetds = std; 470 splx(s); 471 } 472 473 usbd_status 474 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 475 int alen, int rd, usbd_xfer_handle xfer, 476 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 477 { 478 ohci_soft_td_t *next, *cur; 479 ohci_physaddr_t dataphys, dataphysend; 480 u_int32_t tdflags; 481 int len, curlen; 482 usb_dma_t *dma = &xfer->dmabuf; 483 u_int16_t flags = xfer->flags; 484 485 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 486 487 len = alen; 488 cur = sp; 489 dataphys = DMAADDR(dma, 0); 490 dataphysend = OHCI_PAGE(dataphys + len - 1); 491 usb_syncmem(dma, 0, len, 492 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 493 tdflags = HTOO32( 494 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 495 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 496 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 497 498 for (;;) { 499 next = ohci_alloc_std(sc); 500 if (next == NULL) 501 goto nomem; 502 503 /* The OHCI hardware can handle at most one page crossing. */ 504 if (OHCI_PAGE(dataphys) == dataphysend || 505 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 506 /* we can handle it in this TD */ 507 curlen = len; 508 } else { 509 /* must use multiple TDs, fill as much as possible. */ 510 curlen = 2 * OHCI_PAGE_SIZE - 511 (dataphys & (OHCI_PAGE_SIZE-1)); 512 /* the length must be a multiple of the max size */ 513 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 514 #ifdef DIAGNOSTIC 515 if (curlen == 0) 516 panic("ohci_alloc_std: curlen == 0"); 517 #endif 518 } 519 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 520 "dataphysend=0x%08x len=%d curlen=%d\n", 521 dataphys, dataphysend, 522 len, curlen)); 523 len -= curlen; 524 525 cur->td.td_flags = tdflags; 526 cur->td.td_cbp = HTOO32(dataphys); 527 cur->nexttd = next; 528 cur->td.td_nexttd = HTOO32(next->physaddr); 529 cur->td.td_be = HTOO32(dataphys + curlen - 1); 530 cur->len = curlen; 531 cur->flags = OHCI_ADD_LEN; 532 cur->xfer = xfer; 533 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 536 dataphys, dataphys + curlen - 1)); 537 if (len == 0) 538 break; 539 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 540 dataphys += curlen; 541 cur = next; 542 } 543 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 544 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 545 /* Force a 0 length transfer at the end. */ 546 547 cur = next; 548 next = ohci_alloc_std(sc); 549 if (next == NULL) 550 goto nomem; 551 552 cur->td.td_flags = tdflags; 553 cur->td.td_cbp = 0; /* indicate 0 length packet */ 554 cur->nexttd = next; 555 cur->td.td_nexttd = HTOO32(next->physaddr); 556 cur->td.td_be = ~0; 557 cur->len = 0; 558 cur->flags = 0; 559 cur->xfer = xfer; 560 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 563 } 564 *ep = cur; 565 566 return (USBD_NORMAL_COMPLETION); 567 568 nomem: 569 /* XXX free chain */ 570 return (USBD_NOMEM); 571 } 572 573 #if 0 574 Static void 575 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 576 ohci_soft_td_t *stdend) 577 { 578 ohci_soft_td_t *p; 579 580 for (; std != stdend; std = p) { 581 p = std->nexttd; 582 ohci_free_std(sc, std); 583 } 584 } 585 #endif 586 587 ohci_soft_itd_t * 588 ohci_alloc_sitd(ohci_softc_t *sc) 589 { 590 ohci_soft_itd_t *sitd; 591 usbd_status err; 592 int i, s, offs; 593 usb_dma_t dma; 594 595 if (sc->sc_freeitds == NULL) { 596 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 597 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 598 OHCI_ITD_ALIGN, &dma); 599 if (err) 600 return (NULL); 601 s = splusb(); 602 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 603 offs = i * OHCI_SITD_SIZE; 604 sitd = KERNADDR(&dma, offs); 605 sitd->physaddr = DMAADDR(&dma, offs); 606 sitd->dma = dma; 607 sitd->offs = offs; 608 sitd->nextitd = sc->sc_freeitds; 609 sc->sc_freeitds = sitd; 610 } 611 splx(s); 612 } 613 614 s = splusb(); 615 sitd = sc->sc_freeitds; 616 sc->sc_freeitds = sitd->nextitd; 617 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 618 sitd->nextitd = NULL; 619 sitd->xfer = NULL; 620 ohci_hash_add_itd(sc, sitd); 621 splx(s); 622 623 #ifdef DIAGNOSTIC 624 sitd->isdone = 0; 625 #endif 626 627 return (sitd); 628 } 629 630 void 631 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 632 { 633 int s; 634 635 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 636 637 #ifdef DIAGNOSTIC 638 if (!sitd->isdone) { 639 panic("ohci_free_sitd: sitd=%p not done", sitd); 640 return; 641 } 642 /* Warn double free */ 643 sitd->isdone = 0; 644 #endif 645 646 s = splusb(); 647 ohci_hash_rem_itd(sc, sitd); 648 sitd->nextitd = sc->sc_freeitds; 649 sc->sc_freeitds = sitd; 650 splx(s); 651 } 652 653 usbd_status 654 ohci_init(ohci_softc_t *sc) 655 { 656 ohci_soft_ed_t *sed, *psed; 657 usbd_status err; 658 int i; 659 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 660 661 DPRINTF(("ohci_init: start\n")); 662 aprint_normal_dev(sc->sc_dev, ""); 663 664 sc->sc_hcca = NULL; 665 callout_init(&sc->sc_tmo_rhsc, 0); 666 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_tds[i]); 669 for (i = 0; i < OHCI_HASH_SIZE; i++) 670 LIST_INIT(&sc->sc_hash_itds[i]); 671 672 SIMPLEQ_INIT(&sc->sc_free_xfers); 673 674 rev = OREAD4(sc, OHCI_REVISION); 675 aprint_normal("OHCI version %d.%d%s\n", 676 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 677 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 678 679 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 680 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 681 sc->sc_bus.usbrev = USBREV_UNKNOWN; 682 return (USBD_INVAL); 683 } 684 sc->sc_bus.usbrev = USBREV_1_0; 685 686 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 687 USB_MEM_RESERVE); 688 689 /* XXX determine alignment by R/W */ 690 /* Allocate the HCCA area. */ 691 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 692 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 693 if (err) { 694 sc->sc_hcca = NULL; 695 return err; 696 } 697 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 698 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 699 700 sc->sc_eintrs = OHCI_NORMAL_INTRS; 701 702 /* Allocate dummy ED that starts the control list. */ 703 sc->sc_ctrl_head = ohci_alloc_sed(sc); 704 if (sc->sc_ctrl_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad1; 707 } 708 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 709 710 /* Allocate dummy ED that starts the bulk list. */ 711 sc->sc_bulk_head = ohci_alloc_sed(sc); 712 if (sc->sc_bulk_head == NULL) { 713 err = USBD_NOMEM; 714 goto bad2; 715 } 716 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 717 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 718 sizeof(sc->sc_bulk_head->ed), 719 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 720 721 /* Allocate dummy ED that starts the isochronous list. */ 722 sc->sc_isoc_head = ohci_alloc_sed(sc); 723 if (sc->sc_isoc_head == NULL) { 724 err = USBD_NOMEM; 725 goto bad3; 726 } 727 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 728 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 729 sizeof(sc->sc_isoc_head->ed), 730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 731 732 /* Allocate all the dummy EDs that make up the interrupt tree. */ 733 for (i = 0; i < OHCI_NO_EDS; i++) { 734 sed = ohci_alloc_sed(sc); 735 if (sed == NULL) { 736 while (--i >= 0) 737 ohci_free_sed(sc, sc->sc_eds[i]); 738 err = USBD_NOMEM; 739 goto bad4; 740 } 741 /* All ED fields are set to 0. */ 742 sc->sc_eds[i] = sed; 743 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 744 if (i != 0) 745 psed = sc->sc_eds[(i-1) / 2]; 746 else 747 psed= sc->sc_isoc_head; 748 sed->next = psed; 749 sed->ed.ed_nexted = HTOO32(psed->physaddr); 750 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 } 753 /* 754 * Fill HCCA interrupt table. The bit reversal is to get 755 * the tree set up properly to spread the interrupts. 756 */ 757 for (i = 0; i < OHCI_NO_INTRS; i++) 758 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 759 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 760 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 761 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 762 763 #ifdef OHCI_DEBUG 764 if (ohcidebug > 15) { 765 for (i = 0; i < OHCI_NO_EDS; i++) { 766 printf("ed#%d ", i); 767 ohci_dump_ed(sc, sc->sc_eds[i]); 768 } 769 printf("iso "); 770 ohci_dump_ed(sc, sc->sc_isoc_head); 771 } 772 #endif 773 774 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 775 ctl = OREAD4(sc, OHCI_CONTROL); 776 rwc = ctl & OHCI_RWC; 777 fm = OREAD4(sc, OHCI_FM_INTERVAL); 778 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 779 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 780 781 /* Determine in what context we are running. */ 782 if (ctl & OHCI_IR) { 783 /* SMM active, request change */ 784 DPRINTF(("ohci_init: SMM active, request owner change\n")); 785 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 786 (OHCI_OC | OHCI_MIE)) 787 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 788 s = OREAD4(sc, OHCI_COMMAND_STATUS); 789 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 790 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 791 usb_delay_ms(&sc->sc_bus, 1); 792 ctl = OREAD4(sc, OHCI_CONTROL); 793 } 794 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 795 if ((ctl & OHCI_IR) == 0) { 796 aprint_error_dev(sc->sc_dev, 797 "SMM does not respond, resetting\n"); 798 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 799 goto reset; 800 } 801 #if 0 802 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 803 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 804 /* BIOS started controller. */ 805 DPRINTF(("ohci_init: BIOS active\n")); 806 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 807 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 808 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 809 } 810 #endif 811 } else { 812 DPRINTF(("ohci_init: cold started\n")); 813 reset: 814 /* Controller was cold started. */ 815 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 816 } 817 818 /* 819 * This reset should not be necessary according to the OHCI spec, but 820 * without it some controllers do not start. 821 */ 822 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 823 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 824 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 825 826 /* We now own the host controller and the bus has been reset. */ 827 828 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 829 /* Nominal time for a reset is 10 us. */ 830 for (i = 0; i < 10; i++) { 831 delay(10); 832 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 833 if (!hcr) 834 break; 835 } 836 if (hcr) { 837 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 838 err = USBD_IOERROR; 839 goto bad5; 840 } 841 #ifdef OHCI_DEBUG 842 if (ohcidebug > 15) 843 ohci_dumpregs(sc); 844 #endif 845 846 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 847 848 /* Set up HC registers. */ 849 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 850 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 851 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 852 /* disable all interrupts and then switch on all desired interrupts */ 853 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 854 /* switch on desired functional features */ 855 ctl = OREAD4(sc, OHCI_CONTROL); 856 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 857 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 858 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 859 /* And finally start it! */ 860 OWRITE4(sc, OHCI_CONTROL, ctl); 861 862 /* 863 * The controller is now OPERATIONAL. Set a some final 864 * registers that should be set earlier, but that the 865 * controller ignores when in the SUSPEND state. 866 */ 867 ival = OHCI_GET_IVAL(fm); 868 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 869 fm |= OHCI_FSMPS(ival) | ival; 870 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 871 per = OHCI_PERIODIC(ival); /* 90% periodic */ 872 OWRITE4(sc, OHCI_PERIODIC_START, per); 873 874 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 875 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 876 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 877 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 878 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 879 880 /* 881 * The AMD756 requires a delay before re-reading the register, 882 * otherwise it will occasionally report 0 ports. 883 */ 884 sc->sc_noport = 0; 885 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 886 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 887 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 888 } 889 890 #ifdef OHCI_DEBUG 891 if (ohcidebug > 5) 892 ohci_dumpregs(sc); 893 #endif 894 895 /* Set up the bus struct. */ 896 sc->sc_bus.methods = &ohci_bus_methods; 897 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 898 899 sc->sc_control = sc->sc_intre = 0; 900 901 /* Finally, turn on interrupts. */ 902 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 903 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 904 905 return (USBD_NORMAL_COMPLETION); 906 907 bad5: 908 for (i = 0; i < OHCI_NO_EDS; i++) 909 ohci_free_sed(sc, sc->sc_eds[i]); 910 bad4: 911 ohci_free_sed(sc, sc->sc_isoc_head); 912 bad3: 913 ohci_free_sed(sc, sc->sc_bulk_head); 914 bad2: 915 ohci_free_sed(sc, sc->sc_ctrl_head); 916 bad1: 917 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 918 sc->sc_hcca = NULL; 919 return (err); 920 } 921 922 usbd_status 923 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 924 { 925 struct ohci_softc *sc = bus->hci_private; 926 usbd_status status; 927 928 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 929 if (status == USBD_NOMEM) 930 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 931 return status; 932 } 933 934 void 935 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 936 { 937 struct ohci_softc *sc = bus->hci_private; 938 if (dma->block->flags & USB_DMA_RESERVE) { 939 usb_reserve_freem(&sc->sc_dma_reserve, dma); 940 return; 941 } 942 usb_freemem(&sc->sc_bus, dma); 943 } 944 945 usbd_xfer_handle 946 ohci_allocx(struct usbd_bus *bus) 947 { 948 struct ohci_softc *sc = bus->hci_private; 949 usbd_xfer_handle xfer; 950 951 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 952 if (xfer != NULL) { 953 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 954 #ifdef DIAGNOSTIC 955 if (xfer->busy_free != XFER_FREE) { 956 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 957 xfer->busy_free); 958 } 959 #endif 960 } else { 961 xfer = malloc(sizeof(struct ohci_xfer), M_USB, M_NOWAIT); 962 } 963 if (xfer != NULL) { 964 memset(xfer, 0, sizeof (struct ohci_xfer)); 965 #ifdef DIAGNOSTIC 966 xfer->busy_free = XFER_BUSY; 967 #endif 968 } 969 return (xfer); 970 } 971 972 void 973 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 974 { 975 struct ohci_softc *sc = bus->hci_private; 976 977 #ifdef DIAGNOSTIC 978 if (xfer->busy_free != XFER_BUSY) { 979 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 980 xfer->busy_free); 981 } 982 xfer->busy_free = XFER_FREE; 983 #endif 984 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 985 } 986 987 /* 988 * Shut down the controller when the system is going down. 989 */ 990 bool 991 ohci_shutdown(device_t self, int flags) 992 { 993 ohci_softc_t *sc = device_private(self); 994 995 DPRINTF(("ohci_shutdown: stopping the HC\n")); 996 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 997 return true; 998 } 999 1000 bool 1001 ohci_resume(device_t dv, const pmf_qual_t *qual) 1002 { 1003 ohci_softc_t *sc = device_private(dv); 1004 uint32_t ctl; 1005 int s; 1006 1007 s = splhardusb(); 1008 sc->sc_bus.use_polling++; 1009 /* Some broken BIOSes do not recover these values */ 1010 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1011 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1012 sc->sc_ctrl_head->physaddr); 1013 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1014 sc->sc_bulk_head->physaddr); 1015 if (sc->sc_intre) 1016 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1017 (OHCI_ALL_INTRS | OHCI_MIE)); 1018 if (sc->sc_control) 1019 ctl = sc->sc_control; 1020 else 1021 ctl = OREAD4(sc, OHCI_CONTROL); 1022 ctl |= OHCI_HCFS_RESUME; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1025 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1026 OWRITE4(sc, OHCI_CONTROL, ctl); 1027 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1028 sc->sc_control = sc->sc_intre = 0; 1029 sc->sc_bus.use_polling--; 1030 splx(s); 1031 1032 return true; 1033 } 1034 1035 bool 1036 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1037 { 1038 ohci_softc_t *sc = device_private(dv); 1039 uint32_t ctl; 1040 int s; 1041 1042 s = splhardusb(); 1043 sc->sc_bus.use_polling++; 1044 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1045 if (sc->sc_control == 0) { 1046 /* 1047 * Preserve register values, in case that BIOS 1048 * does not recover them. 1049 */ 1050 sc->sc_control = ctl; 1051 sc->sc_intre = OREAD4(sc, 1052 OHCI_INTERRUPT_ENABLE); 1053 } 1054 ctl |= OHCI_HCFS_SUSPEND; 1055 OWRITE4(sc, OHCI_CONTROL, ctl); 1056 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1057 sc->sc_bus.use_polling--; 1058 splx(s); 1059 1060 return true; 1061 } 1062 1063 #ifdef OHCI_DEBUG 1064 void 1065 ohci_dumpregs(ohci_softc_t *sc) 1066 { 1067 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1068 OREAD4(sc, OHCI_REVISION), 1069 OREAD4(sc, OHCI_CONTROL), 1070 OREAD4(sc, OHCI_COMMAND_STATUS))); 1071 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1072 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1073 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1074 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1075 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1076 OREAD4(sc, OHCI_HCCA), 1077 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1078 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1079 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1080 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1081 OREAD4(sc, OHCI_BULK_HEAD_ED), 1082 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1083 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1084 OREAD4(sc, OHCI_DONE_HEAD), 1085 OREAD4(sc, OHCI_FM_INTERVAL), 1086 OREAD4(sc, OHCI_FM_REMAINING))); 1087 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1088 OREAD4(sc, OHCI_FM_NUMBER), 1089 OREAD4(sc, OHCI_PERIODIC_START), 1090 OREAD4(sc, OHCI_LS_THRESHOLD))); 1091 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1092 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1093 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1094 OREAD4(sc, OHCI_RH_STATUS))); 1095 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1096 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1097 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1098 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1099 O32TOH(sc->sc_hcca->hcca_frame_number), 1100 O32TOH(sc->sc_hcca->hcca_done_head))); 1101 } 1102 #endif 1103 1104 Static int ohci_intr1(ohci_softc_t *); 1105 1106 int 1107 ohci_intr(void *p) 1108 { 1109 ohci_softc_t *sc = p; 1110 1111 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 1112 return (0); 1113 1114 /* If we get an interrupt while polling, then just ignore it. */ 1115 if (sc->sc_bus.use_polling) { 1116 #ifdef DIAGNOSTIC 1117 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1118 #endif 1119 /* for level triggered intrs, should do something to ack */ 1120 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1121 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1122 1123 return (0); 1124 } 1125 1126 return (ohci_intr1(sc)); 1127 } 1128 1129 Static int 1130 ohci_intr1(ohci_softc_t *sc) 1131 { 1132 u_int32_t intrs, eintrs; 1133 1134 DPRINTFN(14,("ohci_intr1: enter\n")); 1135 1136 /* In case the interrupt occurs before initialization has completed. */ 1137 if (sc == NULL || sc->sc_hcca == NULL) { 1138 #ifdef DIAGNOSTIC 1139 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1140 #endif 1141 return (0); 1142 } 1143 1144 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1145 if (!intrs) 1146 return (0); 1147 1148 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1149 eintrs = intrs & sc->sc_eintrs; 1150 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1151 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1152 (u_int)eintrs, sc->sc_eintrs)); 1153 1154 if (!eintrs) { 1155 return (0); 1156 } 1157 1158 sc->sc_bus.intr_context++; 1159 sc->sc_bus.no_intrs++; 1160 if (eintrs & OHCI_SO) { 1161 sc->sc_overrun_cnt++; 1162 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1163 printf("%s: %u scheduling overruns\n", 1164 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1165 sc->sc_overrun_cnt = 0; 1166 } 1167 /* XXX do what */ 1168 eintrs &= ~OHCI_SO; 1169 } 1170 if (eintrs & OHCI_WDH) { 1171 /* 1172 * We block the interrupt below, and reenable it later from 1173 * ohci_softintr(). 1174 */ 1175 usb_schedsoftintr(&sc->sc_bus); 1176 } 1177 if (eintrs & OHCI_RD) { 1178 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1179 /* XXX process resume detect */ 1180 } 1181 if (eintrs & OHCI_UE) { 1182 printf("%s: unrecoverable error, controller halted\n", 1183 device_xname(sc->sc_dev)); 1184 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1185 /* XXX what else */ 1186 } 1187 if (eintrs & OHCI_RHSC) { 1188 /* 1189 * We block the interrupt below, and reenable it later from 1190 * a timeout. 1191 */ 1192 ohci_rhsc(sc, sc->sc_intrxfer); 1193 /* Do not allow RHSC interrupts > 1 per second */ 1194 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1195 } 1196 1197 sc->sc_bus.intr_context--; 1198 1199 if (eintrs != 0) { 1200 /* Block unprocessed interrupts. */ 1201 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1202 sc->sc_eintrs &= ~eintrs; 1203 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1204 device_xname(sc->sc_dev), eintrs)); 1205 } 1206 1207 return (1); 1208 } 1209 1210 void 1211 ohci_rhsc_enable(void *v_sc) 1212 { 1213 ohci_softc_t *sc = v_sc; 1214 int s; 1215 1216 s = splhardusb(); 1217 sc->sc_eintrs |= OHCI_RHSC; 1218 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1219 splx(s); 1220 } 1221 1222 #ifdef OHCI_DEBUG 1223 const char *ohci_cc_strs[] = { 1224 "NO_ERROR", 1225 "CRC", 1226 "BIT_STUFFING", 1227 "DATA_TOGGLE_MISMATCH", 1228 "STALL", 1229 "DEVICE_NOT_RESPONDING", 1230 "PID_CHECK_FAILURE", 1231 "UNEXPECTED_PID", 1232 "DATA_OVERRUN", 1233 "DATA_UNDERRUN", 1234 "BUFFER_OVERRUN", 1235 "BUFFER_UNDERRUN", 1236 "reserved", 1237 "reserved", 1238 "NOT_ACCESSED", 1239 "NOT_ACCESSED", 1240 }; 1241 #endif 1242 1243 void 1244 ohci_softintr(void *v) 1245 { 1246 struct usbd_bus *bus = v; 1247 ohci_softc_t *sc = bus->hci_private; 1248 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1249 ohci_soft_td_t *std, *sdone, *stdnext; 1250 usbd_xfer_handle xfer; 1251 struct ohci_pipe *opipe; 1252 int len, cc, s; 1253 int i, j, actlen, iframes, uedir; 1254 ohci_physaddr_t done; 1255 1256 DPRINTFN(10,("ohci_softintr: enter\n")); 1257 1258 sc->sc_bus.intr_context++; 1259 1260 s = splhardusb(); 1261 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1262 sizeof(sc->sc_hcca->hcca_done_head), 1263 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1264 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1265 sc->sc_hcca->hcca_done_head = 0; 1266 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1267 sizeof(sc->sc_hcca->hcca_done_head), 1268 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1269 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1270 sc->sc_eintrs |= OHCI_WDH; 1271 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1272 splx(s); 1273 1274 /* Reverse the done list. */ 1275 for (sdone = NULL, sidone = NULL; done != 0; ) { 1276 std = ohci_hash_find_td(sc, done); 1277 if (std != NULL) { 1278 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1279 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1280 std->dnext = sdone; 1281 done = O32TOH(std->td.td_nexttd); 1282 sdone = std; 1283 DPRINTFN(10,("add TD %p\n", std)); 1284 continue; 1285 } 1286 sitd = ohci_hash_find_itd(sc, done); 1287 if (sitd != NULL) { 1288 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1289 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1290 sitd->dnext = sidone; 1291 done = O32TOH(sitd->itd.itd_nextitd); 1292 sidone = sitd; 1293 DPRINTFN(5,("add ITD %p\n", sitd)); 1294 continue; 1295 } 1296 panic("ohci_softintr: addr 0x%08lx not found", (u_long)done); 1297 } 1298 1299 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1300 1301 #ifdef OHCI_DEBUG 1302 if (ohcidebug > 10) { 1303 DPRINTF(("ohci_process_done: TD done:\n")); 1304 ohci_dump_tds(sc, sdone); 1305 } 1306 #endif 1307 1308 for (std = sdone; std; std = stdnext) { 1309 xfer = std->xfer; 1310 stdnext = std->dnext; 1311 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1312 std, xfer, xfer ? xfer->hcpriv : 0)); 1313 if (xfer == NULL) { 1314 /* 1315 * xfer == NULL: There seems to be no xfer associated 1316 * with this TD. It is tailp that happened to end up on 1317 * the done queue. 1318 * Shouldn't happen, but some chips are broken(?). 1319 */ 1320 continue; 1321 } 1322 if (xfer->status == USBD_CANCELLED || 1323 xfer->status == USBD_TIMEOUT) { 1324 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1325 xfer)); 1326 /* Handled by abort routine. */ 1327 continue; 1328 } 1329 callout_stop(&xfer->timeout_handle); 1330 1331 len = std->len; 1332 if (std->td.td_cbp != 0) 1333 len -= O32TOH(std->td.td_be) - 1334 O32TOH(std->td.td_cbp) + 1; 1335 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1336 std->flags)); 1337 if (std->flags & OHCI_ADD_LEN) 1338 xfer->actlen += len; 1339 1340 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1341 if (cc == OHCI_CC_NO_ERROR) { 1342 if (std->flags & OHCI_CALL_DONE) { 1343 xfer->status = USBD_NORMAL_COMPLETION; 1344 s = splusb(); 1345 usb_transfer_complete(xfer); 1346 splx(s); 1347 } 1348 ohci_free_std(sc, std); 1349 } else { 1350 /* 1351 * Endpoint is halted. First unlink all the TDs 1352 * belonging to the failed transfer, and then restart 1353 * the endpoint. 1354 */ 1355 ohci_soft_td_t *p, *n; 1356 opipe = (struct ohci_pipe *)xfer->pipe; 1357 1358 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1359 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1360 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1361 1362 /* remove TDs */ 1363 for (p = std; p->xfer == xfer; p = n) { 1364 n = p->nexttd; 1365 ohci_free_std(sc, p); 1366 } 1367 1368 /* clear halt */ 1369 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1370 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1371 1372 if (cc == OHCI_CC_STALL) 1373 xfer->status = USBD_STALLED; 1374 else 1375 xfer->status = USBD_IOERROR; 1376 s = splusb(); 1377 usb_transfer_complete(xfer); 1378 splx(s); 1379 } 1380 } 1381 1382 #ifdef OHCI_DEBUG 1383 if (ohcidebug > 10) { 1384 DPRINTF(("ohci_softintr: ITD done:\n")); 1385 ohci_dump_itds(sc, sidone); 1386 } 1387 #endif 1388 1389 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1390 xfer = sitd->xfer; 1391 sitdnext = sitd->dnext; 1392 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1393 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1394 if (xfer == NULL) 1395 continue; 1396 if (xfer->status == USBD_CANCELLED || 1397 xfer->status == USBD_TIMEOUT) { 1398 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1399 xfer)); 1400 /* Handled by abort routine. */ 1401 continue; 1402 } 1403 #ifdef DIAGNOSTIC 1404 if (sitd->isdone) 1405 printf("ohci_softintr: sitd=%p is done\n", sitd); 1406 sitd->isdone = 1; 1407 #endif 1408 if (sitd->flags & OHCI_CALL_DONE) { 1409 ohci_soft_itd_t *next; 1410 1411 opipe = (struct ohci_pipe *)xfer->pipe; 1412 opipe->u.iso.inuse -= xfer->nframes; 1413 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1414 bEndpointAddress); 1415 xfer->status = USBD_NORMAL_COMPLETION; 1416 actlen = 0; 1417 for (i = 0, sitd = xfer->hcpriv;; 1418 sitd = next) { 1419 next = sitd->nextitd; 1420 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1421 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1422 xfer->status = USBD_IOERROR; 1423 /* For input, update frlengths with actual */ 1424 /* XXX anything necessary for output? */ 1425 if (uedir == UE_DIR_IN && 1426 xfer->status == USBD_NORMAL_COMPLETION) { 1427 iframes = OHCI_ITD_GET_FC(O32TOH( 1428 sitd->itd.itd_flags)); 1429 for (j = 0; j < iframes; i++, j++) { 1430 len = O16TOH(sitd-> 1431 itd.itd_offset[j]); 1432 if ((OHCI_ITD_PSW_GET_CC(len) & 1433 OHCI_CC_NOT_ACCESSED_MASK) 1434 == OHCI_CC_NOT_ACCESSED) 1435 len = 0; 1436 else 1437 len = OHCI_ITD_PSW_LENGTH(len); 1438 xfer->frlengths[i] = len; 1439 actlen += len; 1440 } 1441 } 1442 if (sitd->flags & OHCI_CALL_DONE) 1443 break; 1444 ohci_free_sitd(sc, sitd); 1445 } 1446 ohci_free_sitd(sc, sitd); 1447 if (uedir == UE_DIR_IN && 1448 xfer->status == USBD_NORMAL_COMPLETION) 1449 xfer->actlen = actlen; 1450 xfer->hcpriv = NULL; 1451 1452 s = splusb(); 1453 usb_transfer_complete(xfer); 1454 splx(s); 1455 } 1456 } 1457 1458 #ifdef USB_USE_SOFTINTR 1459 if (sc->sc_softwake) { 1460 sc->sc_softwake = 0; 1461 wakeup(&sc->sc_softwake); 1462 } 1463 #endif /* USB_USE_SOFTINTR */ 1464 1465 sc->sc_bus.intr_context--; 1466 DPRINTFN(10,("ohci_softintr: done:\n")); 1467 } 1468 1469 void 1470 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1471 { 1472 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1473 int len = UGETW(xfer->request.wLength); 1474 int isread = (xfer->request.bmRequestType & UT_READ); 1475 1476 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1477 1478 #ifdef DIAGNOSTIC 1479 if (!(xfer->rqflags & URQ_REQUEST)) { 1480 panic("ohci_device_ctrl_done: not a request"); 1481 } 1482 #endif 1483 if (len) 1484 usb_syncmem(&xfer->dmabuf, 0, len, 1485 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1486 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1487 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1488 } 1489 1490 void 1491 ohci_device_intr_done(usbd_xfer_handle xfer) 1492 { 1493 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1494 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1495 ohci_soft_ed_t *sed = opipe->sed; 1496 ohci_soft_td_t *data, *tail; 1497 int isread = 1498 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1499 1500 1501 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1502 xfer, xfer->actlen)); 1503 1504 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1505 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1506 if (xfer->pipe->repeat) { 1507 data = opipe->tail.td; 1508 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1509 if (tail == NULL) { 1510 xfer->status = USBD_NOMEM; 1511 return; 1512 } 1513 tail->xfer = NULL; 1514 1515 data->td.td_flags = HTOO32( 1516 OHCI_TD_IN | OHCI_TD_NOCC | 1517 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1518 if (xfer->flags & USBD_SHORT_XFER_OK) 1519 data->td.td_flags |= HTOO32(OHCI_TD_R); 1520 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1521 data->nexttd = tail; 1522 data->td.td_nexttd = HTOO32(tail->physaddr); 1523 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1524 xfer->length - 1); 1525 data->len = xfer->length; 1526 data->xfer = xfer; 1527 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1528 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1530 xfer->hcpriv = data; 1531 xfer->actlen = 0; 1532 1533 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1534 usb_syncmem(&sed->dma, 1535 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1536 sizeof(sed->ed.ed_tailp), 1537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1538 opipe->tail.td = tail; 1539 } 1540 } 1541 1542 void 1543 ohci_device_bulk_done(usbd_xfer_handle xfer) 1544 { 1545 int isread = 1546 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1547 1548 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1549 xfer, xfer->actlen)); 1550 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1551 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1552 } 1553 1554 void 1555 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1556 { 1557 usbd_pipe_handle pipe; 1558 u_char *p; 1559 int i, m; 1560 int hstatus; 1561 1562 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1563 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1564 sc, xfer, hstatus)); 1565 1566 if (xfer == NULL) { 1567 /* Just ignore the change. */ 1568 return; 1569 } 1570 1571 pipe = xfer->pipe; 1572 1573 p = KERNADDR(&xfer->dmabuf, 0); 1574 m = min(sc->sc_noport, xfer->length * 8 - 1); 1575 memset(p, 0, xfer->length); 1576 for (i = 1; i <= m; i++) { 1577 /* Pick out CHANGE bits from the status reg. */ 1578 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1579 p[i/8] |= 1 << (i%8); 1580 } 1581 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1582 xfer->actlen = xfer->length; 1583 xfer->status = USBD_NORMAL_COMPLETION; 1584 1585 usb_transfer_complete(xfer); 1586 } 1587 1588 void 1589 ohci_root_intr_done(usbd_xfer_handle xfer) 1590 { 1591 } 1592 1593 void 1594 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1595 { 1596 } 1597 1598 /* 1599 * Wait here until controller claims to have an interrupt. 1600 * Then call ohci_intr and return. Use timeout to avoid waiting 1601 * too long. 1602 */ 1603 void 1604 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1605 { 1606 int timo; 1607 u_int32_t intrs; 1608 1609 xfer->status = USBD_IN_PROGRESS; 1610 for (timo = xfer->timeout; timo >= 0; timo--) { 1611 usb_delay_ms(&sc->sc_bus, 1); 1612 if (sc->sc_dying) 1613 break; 1614 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1615 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1616 #ifdef OHCI_DEBUG 1617 if (ohcidebug > 15) 1618 ohci_dumpregs(sc); 1619 #endif 1620 if (intrs) { 1621 ohci_intr1(sc); 1622 if (xfer->status != USBD_IN_PROGRESS) 1623 return; 1624 } 1625 } 1626 1627 /* Timeout */ 1628 DPRINTF(("ohci_waitintr: timeout\n")); 1629 xfer->status = USBD_TIMEOUT; 1630 usb_transfer_complete(xfer); 1631 /* XXX should free TD */ 1632 } 1633 1634 void 1635 ohci_poll(struct usbd_bus *bus) 1636 { 1637 ohci_softc_t *sc = bus->hci_private; 1638 #ifdef OHCI_DEBUG 1639 static int last; 1640 int new; 1641 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1642 if (new != last) { 1643 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1644 last = new; 1645 } 1646 #endif 1647 1648 sc->sc_eintrs |= OHCI_WDH; 1649 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) 1650 ohci_intr1(sc); 1651 } 1652 1653 usbd_status 1654 ohci_device_request(usbd_xfer_handle xfer) 1655 { 1656 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1657 usb_device_request_t *req = &xfer->request; 1658 usbd_device_handle dev = opipe->pipe.device; 1659 ohci_softc_t *sc = dev->bus->hci_private; 1660 int addr = dev->address; 1661 ohci_soft_td_t *setup, *stat, *next, *tail; 1662 ohci_soft_ed_t *sed; 1663 int isread; 1664 int len; 1665 usbd_status err; 1666 int s; 1667 1668 isread = req->bmRequestType & UT_READ; 1669 len = UGETW(req->wLength); 1670 1671 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1672 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1673 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1674 UGETW(req->wIndex), len, addr, 1675 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1676 1677 setup = opipe->tail.td; 1678 stat = ohci_alloc_std(sc); 1679 if (stat == NULL) { 1680 err = USBD_NOMEM; 1681 goto bad1; 1682 } 1683 tail = ohci_alloc_std(sc); 1684 if (tail == NULL) { 1685 err = USBD_NOMEM; 1686 goto bad2; 1687 } 1688 tail->xfer = NULL; 1689 1690 sed = opipe->sed; 1691 opipe->u.ctl.length = len; 1692 1693 /* Update device address and length since they may have changed 1694 during the setup of the control pipe in usbd_new_device(). */ 1695 /* XXX This only needs to be done once, but it's too early in open. */ 1696 /* XXXX Should not touch ED here! */ 1697 1698 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1699 sizeof(sed->ed.ed_flags), 1700 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1701 sed->ed.ed_flags = HTOO32( 1702 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1703 OHCI_ED_SET_FA(addr) | 1704 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1705 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1706 sizeof(sed->ed.ed_flags), 1707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1708 1709 next = stat; 1710 1711 /* Set up data transaction */ 1712 if (len != 0) { 1713 ohci_soft_td_t *std = stat; 1714 1715 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1716 std, &stat); 1717 stat = stat->nexttd; /* point at free TD */ 1718 if (err) 1719 goto bad3; 1720 /* Start toggle at 1 and then use the carried toggle. */ 1721 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1722 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1723 usb_syncmem(&std->dma, 1724 std->offs + offsetof(ohci_td_t, td_flags), 1725 sizeof(std->td.td_flags), 1726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1727 } 1728 1729 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1730 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1731 1732 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1733 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1734 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1735 setup->nexttd = next; 1736 setup->td.td_nexttd = HTOO32(next->physaddr); 1737 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1738 setup->len = 0; 1739 setup->xfer = xfer; 1740 setup->flags = 0; 1741 xfer->hcpriv = setup; 1742 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1744 1745 stat->td.td_flags = HTOO32( 1746 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1747 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1748 stat->td.td_cbp = 0; 1749 stat->nexttd = tail; 1750 stat->td.td_nexttd = HTOO32(tail->physaddr); 1751 stat->td.td_be = 0; 1752 stat->flags = OHCI_CALL_DONE; 1753 stat->len = 0; 1754 stat->xfer = xfer; 1755 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1756 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1757 1758 #ifdef OHCI_DEBUG 1759 if (ohcidebug > 5) { 1760 DPRINTF(("ohci_device_request:\n")); 1761 ohci_dump_ed(sc, sed); 1762 ohci_dump_tds(sc, setup); 1763 } 1764 #endif 1765 1766 /* Insert ED in schedule */ 1767 s = splusb(); 1768 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1769 usb_syncmem(&sed->dma, 1770 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1771 sizeof(sed->ed.ed_tailp), 1772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1773 opipe->tail.td = tail; 1774 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1775 if (xfer->timeout && !sc->sc_bus.use_polling) { 1776 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1777 ohci_timeout, xfer); 1778 } 1779 splx(s); 1780 1781 #ifdef OHCI_DEBUG 1782 if (ohcidebug > 20) { 1783 delay(10000); 1784 DPRINTF(("ohci_device_request: status=%x\n", 1785 OREAD4(sc, OHCI_COMMAND_STATUS))); 1786 ohci_dumpregs(sc); 1787 printf("ctrl head:\n"); 1788 ohci_dump_ed(sc, sc->sc_ctrl_head); 1789 printf("sed:\n"); 1790 ohci_dump_ed(sc, sed); 1791 ohci_dump_tds(sc, setup); 1792 } 1793 #endif 1794 1795 return (USBD_NORMAL_COMPLETION); 1796 1797 bad3: 1798 ohci_free_std(sc, tail); 1799 bad2: 1800 ohci_free_std(sc, stat); 1801 bad1: 1802 return (err); 1803 } 1804 1805 /* 1806 * Add an ED to the schedule. Called at splusb(). 1807 */ 1808 void 1809 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1810 { 1811 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1812 1813 SPLUSBCHECK; 1814 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1815 sizeof(head->ed.ed_nexted), 1816 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1817 sed->next = head->next; 1818 sed->ed.ed_nexted = head->ed.ed_nexted; 1819 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1820 sizeof(sed->ed.ed_nexted), 1821 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1822 head->next = sed; 1823 head->ed.ed_nexted = HTOO32(sed->physaddr); 1824 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1825 sizeof(head->ed.ed_nexted), 1826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1827 } 1828 1829 /* 1830 * Remove an ED from the schedule. Called at splusb(). 1831 */ 1832 void 1833 ohci_rem_ed(ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1834 { 1835 ohci_soft_ed_t *p; 1836 1837 SPLUSBCHECK; 1838 1839 /* XXX */ 1840 for (p = head; p != NULL && p->next != sed; p = p->next) 1841 ; 1842 if (p == NULL) 1843 panic("ohci_rem_ed: ED not found"); 1844 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1845 sizeof(sed->ed.ed_nexted), 1846 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1847 p->next = sed->next; 1848 p->ed.ed_nexted = sed->ed.ed_nexted; 1849 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1850 sizeof(p->ed.ed_nexted), 1851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1852 } 1853 1854 /* 1855 * When a transfer is completed the TD is added to the done queue by 1856 * the host controller. This queue is the processed by software. 1857 * Unfortunately the queue contains the physical address of the TD 1858 * and we have no simple way to translate this back to a kernel address. 1859 * To make the translation possible (and fast) we use a hash table of 1860 * TDs currently in the schedule. The physical address is used as the 1861 * hash value. 1862 */ 1863 1864 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1865 /* Called at splusb() */ 1866 void 1867 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1868 { 1869 int h = HASH(std->physaddr); 1870 1871 SPLUSBCHECK; 1872 1873 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1874 } 1875 1876 /* Called at splusb() */ 1877 void 1878 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1879 { 1880 SPLUSBCHECK; 1881 1882 LIST_REMOVE(std, hnext); 1883 } 1884 1885 ohci_soft_td_t * 1886 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1887 { 1888 int h = HASH(a); 1889 ohci_soft_td_t *std; 1890 1891 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1892 std != NULL; 1893 std = LIST_NEXT(std, hnext)) 1894 if (std->physaddr == a) 1895 return (std); 1896 return (NULL); 1897 } 1898 1899 /* Called at splusb() */ 1900 void 1901 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1902 { 1903 int h = HASH(sitd->physaddr); 1904 1905 SPLUSBCHECK; 1906 1907 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1908 sitd, (u_long)sitd->physaddr)); 1909 1910 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1911 } 1912 1913 /* Called at splusb() */ 1914 void 1915 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1916 { 1917 SPLUSBCHECK; 1918 1919 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1920 sitd, (u_long)sitd->physaddr)); 1921 1922 LIST_REMOVE(sitd, hnext); 1923 } 1924 1925 ohci_soft_itd_t * 1926 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1927 { 1928 int h = HASH(a); 1929 ohci_soft_itd_t *sitd; 1930 1931 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1932 sitd != NULL; 1933 sitd = LIST_NEXT(sitd, hnext)) 1934 if (sitd->physaddr == a) 1935 return (sitd); 1936 return (NULL); 1937 } 1938 1939 void 1940 ohci_timeout(void *addr) 1941 { 1942 struct ohci_xfer *oxfer = addr; 1943 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1944 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1945 1946 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1947 1948 if (sc->sc_dying) { 1949 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1950 return; 1951 } 1952 1953 /* Execute the abort in a process context. */ 1954 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 1955 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1956 USB_TASKQ_HC); 1957 } 1958 1959 void 1960 ohci_timeout_task(void *addr) 1961 { 1962 usbd_xfer_handle xfer = addr; 1963 int s; 1964 1965 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1966 1967 s = splusb(); 1968 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1969 splx(s); 1970 } 1971 1972 #ifdef OHCI_DEBUG 1973 void 1974 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1975 { 1976 for (; std; std = std->nexttd) 1977 ohci_dump_td(sc, std); 1978 } 1979 1980 void 1981 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1982 { 1983 char sbuf[128]; 1984 1985 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1986 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1987 snprintb(sbuf, sizeof(sbuf), 1988 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 1989 (u_int32_t)O32TOH(std->td.td_flags)); 1990 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 1991 "nexttd=0x%08lx be=0x%08lx\n", 1992 std, (u_long)std->physaddr, sbuf, 1993 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 1994 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 1995 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1996 (u_long)O32TOH(std->td.td_cbp), 1997 (u_long)O32TOH(std->td.td_nexttd), 1998 (u_long)O32TOH(std->td.td_be)); 1999 } 2000 2001 void 2002 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2003 { 2004 int i; 2005 2006 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2007 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2008 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2009 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2010 sitd, (u_long)sitd->physaddr, 2011 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2012 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2013 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2014 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2015 (u_long)O32TOH(sitd->itd.itd_bp0), 2016 (u_long)O32TOH(sitd->itd.itd_nextitd), 2017 (u_long)O32TOH(sitd->itd.itd_be)); 2018 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2019 printf("offs[%d]=0x%04x ", i, 2020 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2021 printf("\n"); 2022 } 2023 2024 void 2025 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2026 { 2027 for (; sitd; sitd = sitd->nextitd) 2028 ohci_dump_itd(sc, sitd); 2029 } 2030 2031 void 2032 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2033 { 2034 char sbuf[128], sbuf2[128]; 2035 2036 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2038 snprintb(sbuf, sizeof(sbuf), 2039 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2040 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2041 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2042 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2043 2044 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2045 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2046 sed, (u_long)sed->physaddr, 2047 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2048 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2049 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2050 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2051 (u_long)O32TOH(sed->ed.ed_headp), 2052 (u_long)O32TOH(sed->ed.ed_nexted)); 2053 } 2054 #endif 2055 2056 usbd_status 2057 ohci_open(usbd_pipe_handle pipe) 2058 { 2059 usbd_device_handle dev = pipe->device; 2060 ohci_softc_t *sc = dev->bus->hci_private; 2061 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2062 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2063 u_int8_t addr = dev->address; 2064 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2065 ohci_soft_ed_t *sed; 2066 ohci_soft_td_t *std; 2067 ohci_soft_itd_t *sitd; 2068 ohci_physaddr_t tdphys; 2069 u_int32_t fmt; 2070 usbd_status err; 2071 int s; 2072 int ival; 2073 2074 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2075 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2076 2077 if (sc->sc_dying) 2078 return (USBD_IOERROR); 2079 2080 std = NULL; 2081 sed = NULL; 2082 2083 if (addr == sc->sc_addr) { 2084 switch (ed->bEndpointAddress) { 2085 case USB_CONTROL_ENDPOINT: 2086 pipe->methods = &ohci_root_ctrl_methods; 2087 break; 2088 case UE_DIR_IN | OHCI_INTR_ENDPT: 2089 pipe->methods = &ohci_root_intr_methods; 2090 break; 2091 default: 2092 return (USBD_INVAL); 2093 } 2094 } else { 2095 sed = ohci_alloc_sed(sc); 2096 if (sed == NULL) 2097 goto bad0; 2098 opipe->sed = sed; 2099 if (xfertype == UE_ISOCHRONOUS) { 2100 sitd = ohci_alloc_sitd(sc); 2101 if (sitd == NULL) 2102 goto bad1; 2103 opipe->tail.itd = sitd; 2104 tdphys = sitd->physaddr; 2105 fmt = OHCI_ED_FORMAT_ISO; 2106 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2107 fmt |= OHCI_ED_DIR_IN; 2108 else 2109 fmt |= OHCI_ED_DIR_OUT; 2110 } else { 2111 std = ohci_alloc_std(sc); 2112 if (std == NULL) 2113 goto bad1; 2114 opipe->tail.td = std; 2115 tdphys = std->physaddr; 2116 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2117 } 2118 sed->ed.ed_flags = HTOO32( 2119 OHCI_ED_SET_FA(addr) | 2120 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2121 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2122 fmt | 2123 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2124 sed->ed.ed_headp = HTOO32(tdphys | 2125 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2126 sed->ed.ed_tailp = HTOO32(tdphys); 2127 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2129 2130 switch (xfertype) { 2131 case UE_CONTROL: 2132 pipe->methods = &ohci_device_ctrl_methods; 2133 err = usb_allocmem(&sc->sc_bus, 2134 sizeof(usb_device_request_t), 2135 0, &opipe->u.ctl.reqdma); 2136 if (err) 2137 goto bad; 2138 s = splusb(); 2139 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2140 splx(s); 2141 break; 2142 case UE_INTERRUPT: 2143 pipe->methods = &ohci_device_intr_methods; 2144 ival = pipe->interval; 2145 if (ival == USBD_DEFAULT_INTERVAL) 2146 ival = ed->bInterval; 2147 return (ohci_device_setintr(sc, opipe, ival)); 2148 case UE_ISOCHRONOUS: 2149 pipe->methods = &ohci_device_isoc_methods; 2150 return (ohci_setup_isoc(pipe)); 2151 case UE_BULK: 2152 pipe->methods = &ohci_device_bulk_methods; 2153 s = splusb(); 2154 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2155 splx(s); 2156 break; 2157 } 2158 } 2159 return (USBD_NORMAL_COMPLETION); 2160 2161 bad: 2162 if (std != NULL) 2163 ohci_free_std(sc, std); 2164 bad1: 2165 if (sed != NULL) 2166 ohci_free_sed(sc, sed); 2167 bad0: 2168 return (USBD_NOMEM); 2169 2170 } 2171 2172 /* 2173 * Close a reqular pipe. 2174 * Assumes that there are no pending transactions. 2175 */ 2176 void 2177 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2178 { 2179 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2180 ohci_softc_t *sc = pipe->device->bus->hci_private; 2181 ohci_soft_ed_t *sed = opipe->sed; 2182 int s; 2183 2184 s = splusb(); 2185 #ifdef DIAGNOSTIC 2186 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2187 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2188 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2189 ohci_soft_td_t *std; 2190 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2191 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2192 "tl=0x%x pipe=%p, std=%p\n", sed, 2193 (int)O32TOH(sed->ed.ed_headp), 2194 (int)O32TOH(sed->ed.ed_tailp), 2195 pipe, std); 2196 #ifdef USB_DEBUG 2197 usbd_dump_pipe(&opipe->pipe); 2198 #endif 2199 #ifdef OHCI_DEBUG 2200 ohci_dump_ed(sc, sed); 2201 if (std) 2202 ohci_dump_td(sc, std); 2203 #endif 2204 usb_delay_ms(&sc->sc_bus, 2); 2205 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2206 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2207 printf("ohci_close_pipe: pipe still not empty\n"); 2208 } 2209 #endif 2210 ohci_rem_ed(sed, head); 2211 /* Make sure the host controller is not touching this ED */ 2212 usb_delay_ms(&sc->sc_bus, 1); 2213 pipe->endpoint->datatoggle = 2214 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2215 splx(s); 2216 ohci_free_sed(sc, opipe->sed); 2217 } 2218 2219 /* 2220 * Abort a device request. 2221 * If this routine is called at splusb() it guarantees that the request 2222 * will be removed from the hardware scheduling and that the callback 2223 * for it will be called with USBD_CANCELLED status. 2224 * It's impossible to guarantee that the requested transfer will not 2225 * have happened since the hardware runs concurrently. 2226 * If the transaction has already happened we rely on the ordinary 2227 * interrupt processing to process it. 2228 */ 2229 void 2230 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2231 { 2232 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2233 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2234 ohci_soft_ed_t *sed = opipe->sed; 2235 ohci_soft_td_t *p, *n; 2236 ohci_physaddr_t headp; 2237 int s, hit; 2238 int wake; 2239 2240 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2241 2242 if (sc->sc_dying) { 2243 /* If we're dying, just do the software part. */ 2244 s = splusb(); 2245 xfer->status = status; /* make software ignore it */ 2246 callout_stop(&xfer->timeout_handle); 2247 usb_transfer_complete(xfer); 2248 splx(s); 2249 return; 2250 } 2251 2252 if (xfer->device->bus->intr_context || !curproc) 2253 panic("ohci_abort_xfer: not in process context"); 2254 2255 /* 2256 * If an abort is already in progress then just wait for it to 2257 * complete and return. 2258 */ 2259 if (xfer->hcflags & UXFER_ABORTING) { 2260 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2261 #ifdef DIAGNOSTIC 2262 if (status == USBD_TIMEOUT) 2263 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2264 #endif 2265 /* Override the status which might be USBD_TIMEOUT. */ 2266 xfer->status = status; 2267 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2268 xfer->hcflags |= UXFER_ABORTWAIT; 2269 while (xfer->hcflags & UXFER_ABORTING) 2270 tsleep(&xfer->hcflags, PZERO, "ohciaw", 0); 2271 return; 2272 } 2273 xfer->hcflags |= UXFER_ABORTING; 2274 2275 /* 2276 * Step 1: Make interrupt routine and hardware ignore xfer. 2277 */ 2278 s = splusb(); 2279 xfer->status = status; /* make software ignore it */ 2280 callout_stop(&xfer->timeout_handle); 2281 splx(s); 2282 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2283 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2284 sizeof(sed->ed.ed_flags), 2285 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2286 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2287 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2288 sizeof(sed->ed.ed_flags), 2289 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2290 2291 /* 2292 * Step 2: Wait until we know hardware has finished any possible 2293 * use of the xfer. Also make sure the soft interrupt routine 2294 * has run. 2295 */ 2296 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2297 s = splusb(); 2298 #ifdef USB_USE_SOFTINTR 2299 sc->sc_softwake = 1; 2300 #endif /* USB_USE_SOFTINTR */ 2301 usb_schedsoftintr(&sc->sc_bus); 2302 #ifdef USB_USE_SOFTINTR 2303 tsleep(&sc->sc_softwake, PZERO, "ohciab", 0); 2304 #endif /* USB_USE_SOFTINTR */ 2305 splx(s); 2306 2307 /* 2308 * Step 3: Remove any vestiges of the xfer from the hardware. 2309 * The complication here is that the hardware may have executed 2310 * beyond the xfer we're trying to abort. So as we're scanning 2311 * the TDs of this xfer we check if the hardware points to 2312 * any of them. 2313 */ 2314 s = splusb(); /* XXX why? */ 2315 p = xfer->hcpriv; 2316 #ifdef DIAGNOSTIC 2317 if (p == NULL) { 2318 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2319 splx(s); 2320 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2321 return; 2322 } 2323 #endif 2324 #ifdef OHCI_DEBUG 2325 if (ohcidebug > 1) { 2326 DPRINTF(("ohci_abort_xfer: sed=\n")); 2327 ohci_dump_ed(sc, sed); 2328 ohci_dump_tds(sc, p); 2329 } 2330 #endif 2331 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2332 hit = 0; 2333 for (; p->xfer == xfer; p = n) { 2334 hit |= headp == p->physaddr; 2335 n = p->nexttd; 2336 ohci_free_std(sc, p); 2337 } 2338 /* Zap headp register if hardware pointed inside the xfer. */ 2339 if (hit) { 2340 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2341 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2342 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2343 usb_syncmem(&sed->dma, 2344 sed->offs + offsetof(ohci_ed_t, ed_headp), 2345 sizeof(sed->ed.ed_headp), 2346 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2347 } else { 2348 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2349 } 2350 2351 /* 2352 * Step 4: Turn on hardware again. 2353 */ 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2357 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2358 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2359 sizeof(sed->ed.ed_flags), 2360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2361 2362 /* 2363 * Step 5: Execute callback. 2364 */ 2365 wake = xfer->hcflags & UXFER_ABORTWAIT; 2366 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2367 usb_transfer_complete(xfer); 2368 if (wake) 2369 wakeup(&xfer->hcflags); 2370 2371 splx(s); 2372 } 2373 2374 /* 2375 * Data structures and routines to emulate the root hub. 2376 */ 2377 Static usb_device_descriptor_t ohci_devd = { 2378 USB_DEVICE_DESCRIPTOR_SIZE, 2379 UDESC_DEVICE, /* type */ 2380 {0x00, 0x01}, /* USB version */ 2381 UDCLASS_HUB, /* class */ 2382 UDSUBCLASS_HUB, /* subclass */ 2383 UDPROTO_FSHUB, /* protocol */ 2384 64, /* max packet */ 2385 {0},{0},{0x00,0x01}, /* device id */ 2386 1,2,0, /* string indicies */ 2387 1 /* # of configurations */ 2388 }; 2389 2390 Static const usb_config_descriptor_t ohci_confd = { 2391 USB_CONFIG_DESCRIPTOR_SIZE, 2392 UDESC_CONFIG, 2393 {USB_CONFIG_DESCRIPTOR_SIZE + 2394 USB_INTERFACE_DESCRIPTOR_SIZE + 2395 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2396 1, 2397 1, 2398 0, 2399 UC_ATTR_MBO | UC_SELF_POWERED, 2400 0 /* max power */ 2401 }; 2402 2403 Static const usb_interface_descriptor_t ohci_ifcd = { 2404 USB_INTERFACE_DESCRIPTOR_SIZE, 2405 UDESC_INTERFACE, 2406 0, 2407 0, 2408 1, 2409 UICLASS_HUB, 2410 UISUBCLASS_HUB, 2411 UIPROTO_FSHUB, 2412 0 2413 }; 2414 2415 Static const usb_endpoint_descriptor_t ohci_endpd = { 2416 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2417 .bDescriptorType = UDESC_ENDPOINT, 2418 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2419 .bmAttributes = UE_INTERRUPT, 2420 .wMaxPacketSize = {8, 0}, /* max packet */ 2421 .bInterval = 255, 2422 }; 2423 2424 Static const usb_hub_descriptor_t ohci_hubd = { 2425 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2426 .bDescriptorType = UDESC_HUB, 2427 }; 2428 2429 /* 2430 * Simulate a hardware hub by handling all the necessary requests. 2431 */ 2432 Static usbd_status 2433 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2434 { 2435 usbd_status err; 2436 2437 /* Insert last in queue. */ 2438 err = usb_insert_transfer(xfer); 2439 if (err) 2440 return (err); 2441 2442 /* Pipe isn't running, start first */ 2443 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2444 } 2445 2446 Static usbd_status 2447 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2448 { 2449 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2450 usb_device_request_t *req; 2451 void *buf = NULL; 2452 int port, i; 2453 int s, len, value, index, l, totlen = 0; 2454 usb_port_status_t ps; 2455 usb_hub_descriptor_t hubd; 2456 usbd_status err; 2457 u_int32_t v; 2458 2459 if (sc->sc_dying) 2460 return (USBD_IOERROR); 2461 2462 #ifdef DIAGNOSTIC 2463 if (!(xfer->rqflags & URQ_REQUEST)) 2464 /* XXX panic */ 2465 return (USBD_INVAL); 2466 #endif 2467 req = &xfer->request; 2468 2469 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2470 req->bmRequestType, req->bRequest)); 2471 2472 len = UGETW(req->wLength); 2473 value = UGETW(req->wValue); 2474 index = UGETW(req->wIndex); 2475 2476 if (len != 0) 2477 buf = KERNADDR(&xfer->dmabuf, 0); 2478 2479 #define C(x,y) ((x) | ((y) << 8)) 2480 switch(C(req->bRequest, req->bmRequestType)) { 2481 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2482 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2483 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2484 /* 2485 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2486 * for the integrated root hub. 2487 */ 2488 break; 2489 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2490 if (len > 0) { 2491 *(u_int8_t *)buf = sc->sc_conf; 2492 totlen = 1; 2493 } 2494 break; 2495 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2496 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2497 if (len == 0) 2498 break; 2499 switch(value >> 8) { 2500 case UDESC_DEVICE: 2501 if ((value & 0xff) != 0) { 2502 err = USBD_IOERROR; 2503 goto ret; 2504 } 2505 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2506 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2507 memcpy(buf, &ohci_devd, l); 2508 break; 2509 case UDESC_CONFIG: 2510 if ((value & 0xff) != 0) { 2511 err = USBD_IOERROR; 2512 goto ret; 2513 } 2514 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2515 memcpy(buf, &ohci_confd, l); 2516 buf = (char *)buf + l; 2517 len -= l; 2518 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2519 totlen += l; 2520 memcpy(buf, &ohci_ifcd, l); 2521 buf = (char *)buf + l; 2522 len -= l; 2523 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2524 totlen += l; 2525 memcpy(buf, &ohci_endpd, l); 2526 break; 2527 case UDESC_STRING: 2528 #define sd ((usb_string_descriptor_t *)buf) 2529 switch (value & 0xff) { 2530 case 0: /* Language table */ 2531 totlen = usb_makelangtbl(sd, len); 2532 break; 2533 case 1: /* Vendor */ 2534 totlen = usb_makestrdesc(sd, len, 2535 sc->sc_vendor); 2536 break; 2537 case 2: /* Product */ 2538 totlen = usb_makestrdesc(sd, len, 2539 "OHCI root hub"); 2540 break; 2541 } 2542 #undef sd 2543 break; 2544 default: 2545 err = USBD_IOERROR; 2546 goto ret; 2547 } 2548 break; 2549 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2550 if (len > 0) { 2551 *(u_int8_t *)buf = 0; 2552 totlen = 1; 2553 } 2554 break; 2555 case C(UR_GET_STATUS, UT_READ_DEVICE): 2556 if (len > 1) { 2557 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2558 totlen = 2; 2559 } 2560 break; 2561 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2562 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2563 if (len > 1) { 2564 USETW(((usb_status_t *)buf)->wStatus, 0); 2565 totlen = 2; 2566 } 2567 break; 2568 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2569 if (value >= USB_MAX_DEVICES) { 2570 err = USBD_IOERROR; 2571 goto ret; 2572 } 2573 sc->sc_addr = value; 2574 break; 2575 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2576 if (value != 0 && value != 1) { 2577 err = USBD_IOERROR; 2578 goto ret; 2579 } 2580 sc->sc_conf = value; 2581 break; 2582 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2583 break; 2584 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2585 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2586 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2587 err = USBD_IOERROR; 2588 goto ret; 2589 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2590 break; 2591 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2592 break; 2593 /* Hub requests */ 2594 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2595 break; 2596 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2597 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2598 "port=%d feature=%d\n", 2599 index, value)); 2600 if (index < 1 || index > sc->sc_noport) { 2601 err = USBD_IOERROR; 2602 goto ret; 2603 } 2604 port = OHCI_RH_PORT_STATUS(index); 2605 switch(value) { 2606 case UHF_PORT_ENABLE: 2607 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2608 break; 2609 case UHF_PORT_SUSPEND: 2610 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2611 break; 2612 case UHF_PORT_POWER: 2613 /* Yes, writing to the LOW_SPEED bit clears power. */ 2614 OWRITE4(sc, port, UPS_LOW_SPEED); 2615 break; 2616 case UHF_C_PORT_CONNECTION: 2617 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2618 break; 2619 case UHF_C_PORT_ENABLE: 2620 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2621 break; 2622 case UHF_C_PORT_SUSPEND: 2623 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2624 break; 2625 case UHF_C_PORT_OVER_CURRENT: 2626 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2627 break; 2628 case UHF_C_PORT_RESET: 2629 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2630 break; 2631 default: 2632 err = USBD_IOERROR; 2633 goto ret; 2634 } 2635 switch(value) { 2636 case UHF_C_PORT_CONNECTION: 2637 case UHF_C_PORT_ENABLE: 2638 case UHF_C_PORT_SUSPEND: 2639 case UHF_C_PORT_OVER_CURRENT: 2640 case UHF_C_PORT_RESET: 2641 /* Enable RHSC interrupt if condition is cleared. */ 2642 if ((OREAD4(sc, port) >> 16) == 0) 2643 ohci_rhsc_enable(sc); 2644 break; 2645 default: 2646 break; 2647 } 2648 break; 2649 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2650 if (len == 0) 2651 break; 2652 if ((value & 0xff) != 0) { 2653 err = USBD_IOERROR; 2654 goto ret; 2655 } 2656 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2657 hubd = ohci_hubd; 2658 hubd.bNbrPorts = sc->sc_noport; 2659 USETW(hubd.wHubCharacteristics, 2660 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2661 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2662 /* XXX overcurrent */ 2663 ); 2664 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2665 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2666 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2667 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2668 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2669 l = min(len, hubd.bDescLength); 2670 totlen = l; 2671 memcpy(buf, &hubd, l); 2672 break; 2673 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2674 if (len != 4) { 2675 err = USBD_IOERROR; 2676 goto ret; 2677 } 2678 memset(buf, 0, len); /* ? XXX */ 2679 totlen = len; 2680 break; 2681 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2682 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2683 index)); 2684 if (index < 1 || index > sc->sc_noport) { 2685 err = USBD_IOERROR; 2686 goto ret; 2687 } 2688 if (len != 4) { 2689 err = USBD_IOERROR; 2690 goto ret; 2691 } 2692 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2693 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2694 v)); 2695 USETW(ps.wPortStatus, v); 2696 USETW(ps.wPortChange, v >> 16); 2697 l = min(len, sizeof ps); 2698 memcpy(buf, &ps, l); 2699 totlen = l; 2700 break; 2701 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2702 err = USBD_IOERROR; 2703 goto ret; 2704 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2705 break; 2706 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2707 if (index < 1 || index > sc->sc_noport) { 2708 err = USBD_IOERROR; 2709 goto ret; 2710 } 2711 port = OHCI_RH_PORT_STATUS(index); 2712 switch(value) { 2713 case UHF_PORT_ENABLE: 2714 OWRITE4(sc, port, UPS_PORT_ENABLED); 2715 break; 2716 case UHF_PORT_SUSPEND: 2717 OWRITE4(sc, port, UPS_SUSPEND); 2718 break; 2719 case UHF_PORT_RESET: 2720 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2721 index)); 2722 OWRITE4(sc, port, UPS_RESET); 2723 for (i = 0; i < 5; i++) { 2724 usb_delay_ms(&sc->sc_bus, 2725 USB_PORT_ROOT_RESET_DELAY); 2726 if (sc->sc_dying) { 2727 err = USBD_IOERROR; 2728 goto ret; 2729 } 2730 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2731 break; 2732 } 2733 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2734 index, OREAD4(sc, port))); 2735 break; 2736 case UHF_PORT_POWER: 2737 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2738 "%d\n", index)); 2739 OWRITE4(sc, port, UPS_PORT_POWER); 2740 break; 2741 default: 2742 err = USBD_IOERROR; 2743 goto ret; 2744 } 2745 break; 2746 default: 2747 err = USBD_IOERROR; 2748 goto ret; 2749 } 2750 xfer->actlen = totlen; 2751 err = USBD_NORMAL_COMPLETION; 2752 ret: 2753 xfer->status = err; 2754 s = splusb(); 2755 usb_transfer_complete(xfer); 2756 splx(s); 2757 return (USBD_IN_PROGRESS); 2758 } 2759 2760 /* Abort a root control request. */ 2761 Static void 2762 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2763 { 2764 /* Nothing to do, all transfers are synchronous. */ 2765 } 2766 2767 /* Close the root pipe. */ 2768 Static void 2769 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2770 { 2771 DPRINTF(("ohci_root_ctrl_close\n")); 2772 /* Nothing to do. */ 2773 } 2774 2775 Static usbd_status 2776 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2777 { 2778 usbd_status err; 2779 2780 /* Insert last in queue. */ 2781 err = usb_insert_transfer(xfer); 2782 if (err) 2783 return (err); 2784 2785 /* Pipe isn't running, start first */ 2786 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2787 } 2788 2789 Static usbd_status 2790 ohci_root_intr_start(usbd_xfer_handle xfer) 2791 { 2792 usbd_pipe_handle pipe = xfer->pipe; 2793 ohci_softc_t *sc = pipe->device->bus->hci_private; 2794 2795 if (sc->sc_dying) 2796 return (USBD_IOERROR); 2797 2798 sc->sc_intrxfer = xfer; 2799 2800 return (USBD_IN_PROGRESS); 2801 } 2802 2803 /* Abort a root interrupt request. */ 2804 Static void 2805 ohci_root_intr_abort(usbd_xfer_handle xfer) 2806 { 2807 int s; 2808 2809 if (xfer->pipe->intrxfer == xfer) { 2810 DPRINTF(("ohci_root_intr_abort: remove\n")); 2811 xfer->pipe->intrxfer = NULL; 2812 } 2813 xfer->status = USBD_CANCELLED; 2814 s = splusb(); 2815 usb_transfer_complete(xfer); 2816 splx(s); 2817 } 2818 2819 /* Close the root pipe. */ 2820 Static void 2821 ohci_root_intr_close(usbd_pipe_handle pipe) 2822 { 2823 ohci_softc_t *sc = pipe->device->bus->hci_private; 2824 2825 DPRINTF(("ohci_root_intr_close\n")); 2826 2827 sc->sc_intrxfer = NULL; 2828 } 2829 2830 /************************/ 2831 2832 Static usbd_status 2833 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2834 { 2835 usbd_status err; 2836 2837 /* Insert last in queue. */ 2838 err = usb_insert_transfer(xfer); 2839 if (err) 2840 return (err); 2841 2842 /* Pipe isn't running, start first */ 2843 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2844 } 2845 2846 Static usbd_status 2847 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2848 { 2849 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2850 usbd_status err; 2851 2852 if (sc->sc_dying) 2853 return (USBD_IOERROR); 2854 2855 #ifdef DIAGNOSTIC 2856 if (!(xfer->rqflags & URQ_REQUEST)) { 2857 /* XXX panic */ 2858 printf("ohci_device_ctrl_transfer: not a request\n"); 2859 return (USBD_INVAL); 2860 } 2861 #endif 2862 2863 err = ohci_device_request(xfer); 2864 if (err) 2865 return (err); 2866 2867 if (sc->sc_bus.use_polling) 2868 ohci_waitintr(sc, xfer); 2869 return (USBD_IN_PROGRESS); 2870 } 2871 2872 /* Abort a device control request. */ 2873 Static void 2874 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2875 { 2876 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2877 ohci_abort_xfer(xfer, USBD_CANCELLED); 2878 } 2879 2880 /* Close a device control pipe. */ 2881 Static void 2882 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2883 { 2884 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2885 ohci_softc_t *sc = pipe->device->bus->hci_private; 2886 2887 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2888 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2889 ohci_free_std(sc, opipe->tail.td); 2890 } 2891 2892 /************************/ 2893 2894 Static void 2895 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2896 { 2897 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2898 ohci_softc_t *sc = pipe->device->bus->hci_private; 2899 2900 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2901 } 2902 2903 Static void 2904 ohci_noop(usbd_pipe_handle pipe) 2905 { 2906 } 2907 2908 Static usbd_status 2909 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2910 { 2911 usbd_status err; 2912 2913 /* Insert last in queue. */ 2914 err = usb_insert_transfer(xfer); 2915 if (err) 2916 return (err); 2917 2918 /* Pipe isn't running, start first */ 2919 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2920 } 2921 2922 Static usbd_status 2923 ohci_device_bulk_start(usbd_xfer_handle xfer) 2924 { 2925 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2926 usbd_device_handle dev = opipe->pipe.device; 2927 ohci_softc_t *sc = dev->bus->hci_private; 2928 int addr = dev->address; 2929 ohci_soft_td_t *data, *tail, *tdp; 2930 ohci_soft_ed_t *sed; 2931 int s, len, isread, endpt; 2932 usbd_status err; 2933 2934 if (sc->sc_dying) 2935 return (USBD_IOERROR); 2936 2937 #ifdef DIAGNOSTIC 2938 if (xfer->rqflags & URQ_REQUEST) { 2939 /* XXX panic */ 2940 printf("ohci_device_bulk_start: a request\n"); 2941 return (USBD_INVAL); 2942 } 2943 #endif 2944 2945 len = xfer->length; 2946 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 2947 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2948 sed = opipe->sed; 2949 2950 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2951 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 2952 endpt)); 2953 2954 opipe->u.bulk.isread = isread; 2955 opipe->u.bulk.length = len; 2956 2957 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2958 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2959 /* Update device address */ 2960 sed->ed.ed_flags = HTOO32( 2961 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2962 OHCI_ED_SET_FA(addr)); 2963 2964 /* Allocate a chain of new TDs (including a new tail). */ 2965 data = opipe->tail.td; 2966 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2967 data, &tail); 2968 /* We want interrupt at the end of the transfer. */ 2969 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2970 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2971 tail->flags |= OHCI_CALL_DONE; 2972 tail = tail->nexttd; /* point at sentinel */ 2973 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2974 sizeof(tail->td.td_flags), 2975 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2976 if (err) 2977 return (err); 2978 2979 tail->xfer = NULL; 2980 xfer->hcpriv = data; 2981 2982 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2983 "td_cbp=0x%08x td_be=0x%08x\n", 2984 (int)O32TOH(sed->ed.ed_flags), 2985 (int)O32TOH(data->td.td_flags), 2986 (int)O32TOH(data->td.td_cbp), 2987 (int)O32TOH(data->td.td_be))); 2988 2989 #ifdef OHCI_DEBUG 2990 if (ohcidebug > 5) { 2991 ohci_dump_ed(sc, sed); 2992 ohci_dump_tds(sc, data); 2993 } 2994 #endif 2995 2996 /* Insert ED in schedule */ 2997 s = splusb(); 2998 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2999 tdp->xfer = xfer; 3000 } 3001 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3002 opipe->tail.td = tail; 3003 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3004 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3005 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3006 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3007 if (xfer->timeout && !sc->sc_bus.use_polling) { 3008 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3009 ohci_timeout, xfer); 3010 } 3011 3012 #if 0 3013 /* This goes wrong if we are too slow. */ 3014 if (ohcidebug > 10) { 3015 delay(10000); 3016 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3017 OREAD4(sc, OHCI_COMMAND_STATUS))); 3018 ohci_dump_ed(sc, sed); 3019 ohci_dump_tds(sc, data); 3020 } 3021 #endif 3022 3023 splx(s); 3024 3025 return (USBD_IN_PROGRESS); 3026 } 3027 3028 Static void 3029 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3030 { 3031 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3032 ohci_abort_xfer(xfer, USBD_CANCELLED); 3033 } 3034 3035 /* 3036 * Close a device bulk pipe. 3037 */ 3038 Static void 3039 ohci_device_bulk_close(usbd_pipe_handle pipe) 3040 { 3041 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3042 ohci_softc_t *sc = pipe->device->bus->hci_private; 3043 3044 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3045 ohci_close_pipe(pipe, sc->sc_bulk_head); 3046 ohci_free_std(sc, opipe->tail.td); 3047 } 3048 3049 /************************/ 3050 3051 Static usbd_status 3052 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3053 { 3054 usbd_status err; 3055 3056 /* Insert last in queue. */ 3057 err = usb_insert_transfer(xfer); 3058 if (err) 3059 return (err); 3060 3061 /* Pipe isn't running, start first */ 3062 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3063 } 3064 3065 Static usbd_status 3066 ohci_device_intr_start(usbd_xfer_handle xfer) 3067 { 3068 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3069 usbd_device_handle dev = opipe->pipe.device; 3070 ohci_softc_t *sc = dev->bus->hci_private; 3071 ohci_soft_ed_t *sed = opipe->sed; 3072 ohci_soft_td_t *data, *tail; 3073 int s, len, isread, endpt; 3074 3075 if (sc->sc_dying) 3076 return (USBD_IOERROR); 3077 3078 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3079 "flags=%d priv=%p\n", 3080 xfer, xfer->length, xfer->flags, xfer->priv)); 3081 3082 #ifdef DIAGNOSTIC 3083 if (xfer->rqflags & URQ_REQUEST) 3084 panic("ohci_device_intr_transfer: a request"); 3085 #endif 3086 3087 len = xfer->length; 3088 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3089 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3090 3091 data = opipe->tail.td; 3092 tail = ohci_alloc_std(sc); 3093 if (tail == NULL) 3094 return (USBD_NOMEM); 3095 tail->xfer = NULL; 3096 3097 data->td.td_flags = HTOO32( 3098 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3099 OHCI_TD_NOCC | 3100 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3101 if (xfer->flags & USBD_SHORT_XFER_OK) 3102 data->td.td_flags |= HTOO32(OHCI_TD_R); 3103 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3104 data->nexttd = tail; 3105 data->td.td_nexttd = HTOO32(tail->physaddr); 3106 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3107 data->len = len; 3108 data->xfer = xfer; 3109 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3110 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3111 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3112 xfer->hcpriv = data; 3113 3114 #ifdef OHCI_DEBUG 3115 if (ohcidebug > 5) { 3116 DPRINTF(("ohci_device_intr_transfer:\n")); 3117 ohci_dump_ed(sc, sed); 3118 ohci_dump_tds(sc, data); 3119 } 3120 #endif 3121 3122 /* Insert ED in schedule */ 3123 s = splusb(); 3124 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3125 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3126 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3127 opipe->tail.td = tail; 3128 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3129 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3130 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3131 3132 #if 0 3133 /* 3134 * This goes horribly wrong, printing thousands of descriptors, 3135 * because false references are followed due to the fact that the 3136 * TD is gone. 3137 */ 3138 if (ohcidebug > 5) { 3139 usb_delay_ms(&sc->sc_bus, 5); 3140 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3141 OREAD4(sc, OHCI_COMMAND_STATUS))); 3142 ohci_dump_ed(sc, sed); 3143 ohci_dump_tds(sc, data); 3144 } 3145 #endif 3146 splx(s); 3147 3148 return (USBD_IN_PROGRESS); 3149 } 3150 3151 /* Abort a device control request. */ 3152 Static void 3153 ohci_device_intr_abort(usbd_xfer_handle xfer) 3154 { 3155 if (xfer->pipe->intrxfer == xfer) { 3156 DPRINTF(("ohci_device_intr_abort: remove\n")); 3157 xfer->pipe->intrxfer = NULL; 3158 } 3159 ohci_abort_xfer(xfer, USBD_CANCELLED); 3160 } 3161 3162 /* Close a device interrupt pipe. */ 3163 Static void 3164 ohci_device_intr_close(usbd_pipe_handle pipe) 3165 { 3166 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3167 ohci_softc_t *sc = pipe->device->bus->hci_private; 3168 int nslots = opipe->u.intr.nslots; 3169 int pos = opipe->u.intr.pos; 3170 int j; 3171 ohci_soft_ed_t *p, *sed = opipe->sed; 3172 int s; 3173 3174 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3175 pipe, nslots, pos)); 3176 s = splusb(); 3177 usb_syncmem(&sed->dma, sed->offs, 3178 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3179 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3180 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3181 sizeof(sed->ed.ed_flags), 3182 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3183 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3184 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3185 usb_delay_ms(&sc->sc_bus, 2); 3186 3187 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3188 continue; 3189 #ifdef DIAGNOSTIC 3190 if (p == NULL) 3191 panic("ohci_device_intr_close: ED not found"); 3192 #endif 3193 p->next = sed->next; 3194 p->ed.ed_nexted = sed->ed.ed_nexted; 3195 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3196 sizeof(p->ed.ed_nexted), 3197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3198 splx(s); 3199 3200 for (j = 0; j < nslots; j++) 3201 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3202 3203 ohci_free_std(sc, opipe->tail.td); 3204 ohci_free_sed(sc, opipe->sed); 3205 } 3206 3207 Static usbd_status 3208 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3209 { 3210 int i, j, s, best; 3211 u_int npoll, slow, shigh, nslots; 3212 u_int bestbw, bw; 3213 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3214 3215 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3216 if (ival == 0) { 3217 printf("ohci_setintr: 0 interval\n"); 3218 return (USBD_INVAL); 3219 } 3220 3221 npoll = OHCI_NO_INTRS; 3222 while (npoll > ival) 3223 npoll /= 2; 3224 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3225 3226 /* 3227 * We now know which level in the tree the ED must go into. 3228 * Figure out which slot has most bandwidth left over. 3229 * Slots to examine: 3230 * npoll 3231 * 1 0 3232 * 2 1 2 3233 * 4 3 4 5 6 3234 * 8 7 8 9 10 11 12 13 14 3235 * N (N-1) .. (N-1+N-1) 3236 */ 3237 slow = npoll-1; 3238 shigh = slow + npoll; 3239 nslots = OHCI_NO_INTRS / npoll; 3240 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3241 bw = 0; 3242 for (j = 0; j < nslots; j++) 3243 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3244 if (bw < bestbw) { 3245 best = i; 3246 bestbw = bw; 3247 } 3248 } 3249 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3250 best, slow, shigh, bestbw)); 3251 3252 s = splusb(); 3253 hsed = sc->sc_eds[best]; 3254 sed->next = hsed->next; 3255 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3256 sizeof(hsed->ed.ed_flags), 3257 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3258 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3259 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3260 sizeof(sed->ed.ed_flags), 3261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3262 hsed->next = sed; 3263 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3264 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3265 sizeof(hsed->ed.ed_flags), 3266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3267 splx(s); 3268 3269 for (j = 0; j < nslots; j++) 3270 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3271 opipe->u.intr.nslots = nslots; 3272 opipe->u.intr.pos = best; 3273 3274 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3275 return (USBD_NORMAL_COMPLETION); 3276 } 3277 3278 /***********************/ 3279 3280 usbd_status 3281 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3282 { 3283 usbd_status err; 3284 3285 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3286 3287 /* Put it on our queue, */ 3288 err = usb_insert_transfer(xfer); 3289 3290 /* bail out on error, */ 3291 if (err && err != USBD_IN_PROGRESS) 3292 return (err); 3293 3294 /* XXX should check inuse here */ 3295 3296 /* insert into schedule, */ 3297 ohci_device_isoc_enter(xfer); 3298 3299 /* and start if the pipe wasn't running */ 3300 if (!err) 3301 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3302 3303 return (err); 3304 } 3305 3306 void 3307 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3308 { 3309 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3310 usbd_device_handle dev = opipe->pipe.device; 3311 ohci_softc_t *sc = dev->bus->hci_private; 3312 ohci_soft_ed_t *sed = opipe->sed; 3313 struct iso *iso = &opipe->u.iso; 3314 ohci_soft_itd_t *sitd, *nsitd; 3315 ohci_physaddr_t buf, offs, noffs, bp0; 3316 int i, ncur, nframes; 3317 int s; 3318 3319 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3320 "nframes=%d\n", 3321 iso->inuse, iso->next, xfer, xfer->nframes)); 3322 3323 if (sc->sc_dying) 3324 return; 3325 3326 if (iso->next == -1) { 3327 /* Not in use yet, schedule it a few frames ahead. */ 3328 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3329 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3330 iso->next)); 3331 } 3332 3333 sitd = opipe->tail.itd; 3334 buf = DMAADDR(&xfer->dmabuf, 0); 3335 bp0 = OHCI_PAGE(buf); 3336 offs = OHCI_PAGE_OFFSET(buf); 3337 nframes = xfer->nframes; 3338 xfer->hcpriv = sitd; 3339 for (i = ncur = 0; i < nframes; i++, ncur++) { 3340 noffs = offs + xfer->frlengths[i]; 3341 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3342 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3343 3344 /* Allocate next ITD */ 3345 nsitd = ohci_alloc_sitd(sc); 3346 if (nsitd == NULL) { 3347 /* XXX what now? */ 3348 printf("%s: isoc TD alloc failed\n", 3349 device_xname(sc->sc_dev)); 3350 return; 3351 } 3352 3353 /* Fill current ITD */ 3354 sitd->itd.itd_flags = HTOO32( 3355 OHCI_ITD_NOCC | 3356 OHCI_ITD_SET_SF(iso->next) | 3357 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3358 OHCI_ITD_SET_FC(ncur)); 3359 sitd->itd.itd_bp0 = HTOO32(bp0); 3360 sitd->nextitd = nsitd; 3361 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3362 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3363 sitd->xfer = xfer; 3364 sitd->flags = 0; 3365 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 3368 sitd = nsitd; 3369 iso->next = iso->next + ncur; 3370 bp0 = OHCI_PAGE(buf + offs); 3371 ncur = 0; 3372 } 3373 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3374 offs = noffs; 3375 } 3376 nsitd = ohci_alloc_sitd(sc); 3377 if (nsitd == NULL) { 3378 /* XXX what now? */ 3379 printf("%s: isoc TD alloc failed\n", 3380 device_xname(sc->sc_dev)); 3381 return; 3382 } 3383 /* Fixup last used ITD */ 3384 sitd->itd.itd_flags = HTOO32( 3385 OHCI_ITD_NOCC | 3386 OHCI_ITD_SET_SF(iso->next) | 3387 OHCI_ITD_SET_DI(0) | 3388 OHCI_ITD_SET_FC(ncur)); 3389 sitd->itd.itd_bp0 = HTOO32(bp0); 3390 sitd->nextitd = nsitd; 3391 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3392 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3393 sitd->xfer = xfer; 3394 sitd->flags = OHCI_CALL_DONE; 3395 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3396 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3397 3398 iso->next = iso->next + ncur; 3399 iso->inuse += nframes; 3400 3401 xfer->actlen = offs; /* XXX pretend we did it all */ 3402 3403 xfer->status = USBD_IN_PROGRESS; 3404 3405 #ifdef OHCI_DEBUG 3406 if (ohcidebug > 5) { 3407 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3408 O32TOH(sc->sc_hcca->hcca_frame_number))); 3409 ohci_dump_itds(sc, xfer->hcpriv); 3410 ohci_dump_ed(sc, sed); 3411 } 3412 #endif 3413 3414 s = splusb(); 3415 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3416 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3417 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3418 opipe->tail.itd = nsitd; 3419 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3420 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3421 sizeof(sed->ed.ed_flags), 3422 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3423 splx(s); 3424 3425 #ifdef OHCI_DEBUG 3426 if (ohcidebug > 5) { 3427 delay(150000); 3428 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3429 O32TOH(sc->sc_hcca->hcca_frame_number))); 3430 ohci_dump_itds(sc, xfer->hcpriv); 3431 ohci_dump_ed(sc, sed); 3432 } 3433 #endif 3434 } 3435 3436 usbd_status 3437 ohci_device_isoc_start(usbd_xfer_handle xfer) 3438 { 3439 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3440 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3441 3442 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3443 3444 if (sc->sc_dying) 3445 return (USBD_IOERROR); 3446 3447 #ifdef DIAGNOSTIC 3448 if (xfer->status != USBD_IN_PROGRESS) 3449 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3450 #endif 3451 3452 /* XXX anything to do? */ 3453 3454 return (USBD_IN_PROGRESS); 3455 } 3456 3457 void 3458 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3459 { 3460 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3461 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3462 ohci_soft_ed_t *sed; 3463 ohci_soft_itd_t *sitd; 3464 int s; 3465 3466 s = splusb(); 3467 3468 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p\n", xfer)); 3469 3470 /* Transfer is already done. */ 3471 if (xfer->status != USBD_NOT_STARTED && 3472 xfer->status != USBD_IN_PROGRESS) { 3473 splx(s); 3474 printf("ohci_device_isoc_abort: early return\n"); 3475 return; 3476 } 3477 3478 /* Give xfer the requested abort code. */ 3479 xfer->status = USBD_CANCELLED; 3480 3481 sed = opipe->sed; 3482 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3483 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3484 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3485 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3486 sizeof(sed->ed.ed_flags), 3487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3488 3489 sitd = xfer->hcpriv; 3490 #ifdef DIAGNOSTIC 3491 if (sitd == NULL) { 3492 splx(s); 3493 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3494 return; 3495 } 3496 #endif 3497 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3498 #ifdef DIAGNOSTIC 3499 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3500 sitd->isdone = 1; 3501 #endif 3502 } 3503 3504 splx(s); 3505 3506 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3507 3508 s = splusb(); 3509 3510 /* Run callback. */ 3511 usb_transfer_complete(xfer); 3512 3513 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3514 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3515 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3517 3518 splx(s); 3519 } 3520 3521 void 3522 ohci_device_isoc_done(usbd_xfer_handle xfer) 3523 { 3524 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3525 } 3526 3527 usbd_status 3528 ohci_setup_isoc(usbd_pipe_handle pipe) 3529 { 3530 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3531 ohci_softc_t *sc = pipe->device->bus->hci_private; 3532 struct iso *iso = &opipe->u.iso; 3533 int s; 3534 3535 iso->next = -1; 3536 iso->inuse = 0; 3537 3538 s = splusb(); 3539 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3540 splx(s); 3541 3542 return (USBD_NORMAL_COMPLETION); 3543 } 3544 3545 void 3546 ohci_device_isoc_close(usbd_pipe_handle pipe) 3547 { 3548 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3549 ohci_softc_t *sc = pipe->device->bus->hci_private; 3550 3551 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3552 ohci_close_pipe(pipe, sc->sc_isoc_head); 3553 #ifdef DIAGNOSTIC 3554 opipe->tail.itd->isdone = 1; 3555 #endif 3556 ohci_free_sitd(sc, opipe->tail.itd); 3557 } 3558
Indexes created Thu Sep 25 15:09:46 GMT 2025