ohci.c revision 1.218.2.4
1 /* $NetBSD: ohci.c,v 1.218.2.4 2013/01/23 00:06:12 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.218.2.4 2013/01/23 00:06:12 yamt Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 #if 0 102 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 103 ohci_soft_td_t *); 104 #endif 105 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 106 ohci_softc_t *, int, int, usbd_xfer_handle, 107 ohci_soft_td_t *, ohci_soft_td_t **); 108 109 Static usbd_status ohci_open(usbd_pipe_handle); 110 Static void ohci_poll(struct usbd_bus *); 111 Static void ohci_softintr(void *); 112 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 113 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 114 Static void ohci_rhsc_softint(void *arg); 115 116 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 117 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 118 ohci_soft_ed_t *); 119 120 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 121 ohci_soft_ed_t *); 122 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 123 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 124 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 125 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 126 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 127 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 128 129 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 130 Static void ohci_device_isoc_enter(usbd_xfer_handle); 131 132 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 133 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 134 135 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 136 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 137 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 138 139 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 140 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 141 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 142 Static void ohci_root_ctrl_close(usbd_pipe_handle); 143 Static void ohci_root_ctrl_done(usbd_xfer_handle); 144 145 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 146 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 147 Static void ohci_root_intr_abort(usbd_xfer_handle); 148 Static void ohci_root_intr_close(usbd_pipe_handle); 149 Static void ohci_root_intr_done(usbd_xfer_handle); 150 151 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 152 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 153 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 154 Static void ohci_device_ctrl_close(usbd_pipe_handle); 155 Static void ohci_device_ctrl_done(usbd_xfer_handle); 156 157 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 158 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 159 Static void ohci_device_bulk_abort(usbd_xfer_handle); 160 Static void ohci_device_bulk_close(usbd_pipe_handle); 161 Static void ohci_device_bulk_done(usbd_xfer_handle); 162 163 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 164 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 165 Static void ohci_device_intr_abort(usbd_xfer_handle); 166 Static void ohci_device_intr_close(usbd_pipe_handle); 167 Static void ohci_device_intr_done(usbd_xfer_handle); 168 169 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 170 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 171 Static void ohci_device_isoc_abort(usbd_xfer_handle); 172 Static void ohci_device_isoc_close(usbd_pipe_handle); 173 Static void ohci_device_isoc_done(usbd_xfer_handle); 174 175 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 176 struct ohci_pipe *pipe, int ival); 177 178 Static void ohci_timeout(void *); 179 Static void ohci_timeout_task(void *); 180 Static void ohci_rhsc_enable(void *); 181 182 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 183 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 184 185 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 186 Static void ohci_noop(usbd_pipe_handle pipe); 187 188 #ifdef OHCI_DEBUG 189 Static void ohci_dumpregs(ohci_softc_t *); 190 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 191 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 192 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 193 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 194 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 195 #endif 196 197 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 198 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 199 #define OWRITE1(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE2(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 #define OWRITE4(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 static __inline uint8_t 206 OREAD1(ohci_softc_t *sc, bus_size_t r) 207 { 208 209 OBARR(sc); 210 return bus_space_read_1(sc->iot, sc->ioh, r); 211 } 212 213 static __inline uint16_t 214 OREAD2(ohci_softc_t *sc, bus_size_t r) 215 { 216 217 OBARR(sc); 218 return bus_space_read_2(sc->iot, sc->ioh, r); 219 } 220 221 static __inline uint32_t 222 OREAD4(ohci_softc_t *sc, bus_size_t r) 223 { 224 225 OBARR(sc); 226 return bus_space_read_4(sc->iot, sc->ioh, r); 227 } 228 229 /* Reverse the bits in a value 0 .. 31 */ 230 Static u_int8_t revbits[OHCI_NO_INTRS] = 231 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 232 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 233 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 234 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 235 236 struct ohci_pipe { 237 struct usbd_pipe pipe; 238 ohci_soft_ed_t *sed; 239 union { 240 ohci_soft_td_t *td; 241 ohci_soft_itd_t *itd; 242 } tail; 243 /* Info needed for different pipe kinds. */ 244 union { 245 /* Control pipe */ 246 struct { 247 usb_dma_t reqdma; 248 u_int length; 249 ohci_soft_td_t *setup, *data, *stat; 250 } ctl; 251 /* Interrupt pipe */ 252 struct { 253 int nslots; 254 int pos; 255 } intr; 256 /* Bulk pipe */ 257 struct { 258 u_int length; 259 int isread; 260 } bulk; 261 /* Iso pipe */ 262 struct iso { 263 int next, inuse; 264 } iso; 265 } u; 266 }; 267 268 #define OHCI_INTR_ENDPT 1 269 270 Static const struct usbd_bus_methods ohci_bus_methods = { 271 .open_pipe = ohci_open, 272 .soft_intr = ohci_softintr, 273 .do_poll = ohci_poll, 274 .allocm = ohci_allocm, 275 .freem = ohci_freem, 276 .allocx = ohci_allocx, 277 .freex = ohci_freex, 278 .get_lock = ohci_get_lock, 279 }; 280 281 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 282 .transfer = ohci_root_ctrl_transfer, 283 .start = ohci_root_ctrl_start, 284 .abort = ohci_root_ctrl_abort, 285 .close = ohci_root_ctrl_close, 286 .cleartoggle = ohci_noop, 287 .done = ohci_root_ctrl_done, 288 }; 289 290 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 291 .transfer = ohci_root_intr_transfer, 292 .start = ohci_root_intr_start, 293 .abort = ohci_root_intr_abort, 294 .close = ohci_root_intr_close, 295 .cleartoggle = ohci_noop, 296 .done = ohci_root_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 300 .transfer = ohci_device_ctrl_transfer, 301 .start = ohci_device_ctrl_start, 302 .abort = ohci_device_ctrl_abort, 303 .close = ohci_device_ctrl_close, 304 .cleartoggle = ohci_noop, 305 .done = ohci_device_ctrl_done, 306 }; 307 308 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 309 .transfer = ohci_device_intr_transfer, 310 .start = ohci_device_intr_start, 311 .abort = ohci_device_intr_abort, 312 .close = ohci_device_intr_close, 313 .cleartoggle = ohci_device_clear_toggle, 314 .done = ohci_device_intr_done, 315 }; 316 317 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 318 .transfer = ohci_device_bulk_transfer, 319 .start = ohci_device_bulk_start, 320 .abort = ohci_device_bulk_abort, 321 .close = ohci_device_bulk_close, 322 .cleartoggle = ohci_device_clear_toggle, 323 .done = ohci_device_bulk_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 327 .transfer = ohci_device_isoc_transfer, 328 .start = ohci_device_isoc_start, 329 .abort = ohci_device_isoc_abort, 330 .close = ohci_device_isoc_close, 331 .cleartoggle = ohci_noop, 332 .done = ohci_device_isoc_done, 333 }; 334 335 int 336 ohci_activate(device_t self, enum devact act) 337 { 338 struct ohci_softc *sc = device_private(self); 339 340 switch (act) { 341 case DVACT_DEACTIVATE: 342 sc->sc_dying = 1; 343 return 0; 344 default: 345 return EOPNOTSUPP; 346 } 347 } 348 349 void 350 ohci_childdet(device_t self, device_t child) 351 { 352 struct ohci_softc *sc = device_private(self); 353 354 KASSERT(sc->sc_child == child); 355 sc->sc_child = NULL; 356 } 357 358 int 359 ohci_detach(struct ohci_softc *sc, int flags) 360 { 361 int rv = 0; 362 usbd_xfer_handle xfer; 363 364 if (sc->sc_child != NULL) 365 rv = config_detach(sc->sc_child, flags); 366 367 if (rv != 0) 368 return (rv); 369 370 callout_stop(&sc->sc_tmo_rhsc); 371 372 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 373 callout_destroy(&sc->sc_tmo_rhsc); 374 375 softint_disestablish(sc->sc_rhsc_si); 376 377 cv_destroy(&sc->sc_softwake_cv); 378 379 mutex_destroy(&sc->sc_lock); 380 mutex_destroy(&sc->sc_intr_lock); 381 382 if (sc->sc_hcca != NULL) 383 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 384 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 385 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 386 kmem_free(xfer, sizeof(struct ohci_xfer)); 387 } 388 389 return (rv); 390 } 391 392 ohci_soft_ed_t * 393 ohci_alloc_sed(ohci_softc_t *sc) 394 { 395 ohci_soft_ed_t *sed; 396 usbd_status err; 397 int i, offs; 398 usb_dma_t dma; 399 400 if (sc->sc_freeeds == NULL) { 401 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 402 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 403 OHCI_ED_ALIGN, &dma); 404 if (err) 405 return (0); 406 for (i = 0; i < OHCI_SED_CHUNK; i++) { 407 offs = i * OHCI_SED_SIZE; 408 sed = KERNADDR(&dma, offs); 409 sed->physaddr = DMAADDR(&dma, offs); 410 sed->dma = dma; 411 sed->offs = offs; 412 sed->next = sc->sc_freeeds; 413 sc->sc_freeeds = sed; 414 } 415 } 416 sed = sc->sc_freeeds; 417 sc->sc_freeeds = sed->next; 418 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 419 sed->next = 0; 420 return (sed); 421 } 422 423 void 424 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 425 { 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 430 ohci_soft_td_t * 431 ohci_alloc_std(ohci_softc_t *sc) 432 { 433 ohci_soft_td_t *std; 434 usbd_status err; 435 int i, offs; 436 usb_dma_t dma; 437 438 if (sc->sc_freetds == NULL) { 439 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 440 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 441 OHCI_TD_ALIGN, &dma); 442 if (err) 443 return (NULL); 444 for(i = 0; i < OHCI_STD_CHUNK; i++) { 445 offs = i * OHCI_STD_SIZE; 446 std = KERNADDR(&dma, offs); 447 std->physaddr = DMAADDR(&dma, offs); 448 std->dma = dma; 449 std->offs = offs; 450 std->nexttd = sc->sc_freetds; 451 sc->sc_freetds = std; 452 } 453 } 454 455 std = sc->sc_freetds; 456 sc->sc_freetds = std->nexttd; 457 memset(&std->td, 0, sizeof(ohci_td_t)); 458 std->nexttd = NULL; 459 std->xfer = NULL; 460 ohci_hash_add_td(sc, std); 461 462 return (std); 463 } 464 465 void 466 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 467 { 468 469 ohci_hash_rem_td(sc, std); 470 std->nexttd = sc->sc_freetds; 471 sc->sc_freetds = std; 472 } 473 474 usbd_status 475 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 476 int alen, int rd, usbd_xfer_handle xfer, 477 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 478 { 479 ohci_soft_td_t *next, *cur; 480 ohci_physaddr_t dataphys, dataphysend; 481 u_int32_t tdflags; 482 int len, curlen; 483 usb_dma_t *dma = &xfer->dmabuf; 484 u_int16_t flags = xfer->flags; 485 486 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 487 488 KASSERT(mutex_owned(&sc->sc_lock)); 489 490 len = alen; 491 cur = sp; 492 dataphys = DMAADDR(dma, 0); 493 dataphysend = OHCI_PAGE(dataphys + len - 1); 494 usb_syncmem(dma, 0, len, 495 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 496 tdflags = HTOO32( 497 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 498 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 499 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 500 501 for (;;) { 502 next = ohci_alloc_std(sc); 503 if (next == NULL) 504 goto nomem; 505 506 /* The OHCI hardware can handle at most one page crossing. */ 507 if (OHCI_PAGE(dataphys) == dataphysend || 508 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 509 /* we can handle it in this TD */ 510 curlen = len; 511 } else { 512 /* must use multiple TDs, fill as much as possible. */ 513 curlen = 2 * OHCI_PAGE_SIZE - 514 (dataphys & (OHCI_PAGE_SIZE-1)); 515 /* the length must be a multiple of the max size */ 516 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 517 #ifdef DIAGNOSTIC 518 if (curlen == 0) 519 panic("ohci_alloc_std: curlen == 0"); 520 #endif 521 } 522 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 523 "dataphysend=0x%08x len=%d curlen=%d\n", 524 dataphys, dataphysend, 525 len, curlen)); 526 len -= curlen; 527 528 cur->td.td_flags = tdflags; 529 cur->td.td_cbp = HTOO32(dataphys); 530 cur->nexttd = next; 531 cur->td.td_nexttd = HTOO32(next->physaddr); 532 cur->td.td_be = HTOO32(dataphys + curlen - 1); 533 cur->len = curlen; 534 cur->flags = OHCI_ADD_LEN; 535 cur->xfer = xfer; 536 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 538 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 539 dataphys, dataphys + curlen - 1)); 540 if (len == 0) 541 break; 542 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 543 dataphys += curlen; 544 cur = next; 545 } 546 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 547 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 548 /* Force a 0 length transfer at the end. */ 549 550 cur = next; 551 next = ohci_alloc_std(sc); 552 if (next == NULL) 553 goto nomem; 554 555 cur->td.td_flags = tdflags; 556 cur->td.td_cbp = 0; /* indicate 0 length packet */ 557 cur->nexttd = next; 558 cur->td.td_nexttd = HTOO32(next->physaddr); 559 cur->td.td_be = ~0; 560 cur->len = 0; 561 cur->flags = 0; 562 cur->xfer = xfer; 563 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 566 } 567 *ep = cur; 568 569 return (USBD_NORMAL_COMPLETION); 570 571 nomem: 572 /* XXX free chain */ 573 return (USBD_NOMEM); 574 } 575 576 #if 0 577 Static void 578 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 579 ohci_soft_td_t *stdend) 580 { 581 ohci_soft_td_t *p; 582 583 for (; std != stdend; std = p) { 584 p = std->nexttd; 585 ohci_free_std(sc, std); 586 } 587 } 588 #endif 589 590 ohci_soft_itd_t * 591 ohci_alloc_sitd(ohci_softc_t *sc) 592 { 593 ohci_soft_itd_t *sitd; 594 usbd_status err; 595 int i, offs; 596 usb_dma_t dma; 597 598 if (sc->sc_freeitds == NULL) { 599 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 600 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 601 OHCI_ITD_ALIGN, &dma); 602 if (err) 603 return (NULL); 604 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 605 offs = i * OHCI_SITD_SIZE; 606 sitd = KERNADDR(&dma, offs); 607 sitd->physaddr = DMAADDR(&dma, offs); 608 sitd->dma = dma; 609 sitd->offs = offs; 610 sitd->nextitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd; 612 } 613 } 614 615 sitd = sc->sc_freeitds; 616 sc->sc_freeitds = sitd->nextitd; 617 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 618 sitd->nextitd = NULL; 619 sitd->xfer = NULL; 620 ohci_hash_add_itd(sc, sitd); 621 622 #ifdef DIAGNOSTIC 623 sitd->isdone = 0; 624 #endif 625 626 return (sitd); 627 } 628 629 void 630 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 631 { 632 633 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 634 635 #ifdef DIAGNOSTIC 636 if (!sitd->isdone) { 637 panic("ohci_free_sitd: sitd=%p not done", sitd); 638 return; 639 } 640 /* Warn double free */ 641 sitd->isdone = 0; 642 #endif 643 644 ohci_hash_rem_itd(sc, sitd); 645 sitd->nextitd = sc->sc_freeitds; 646 sc->sc_freeitds = sitd; 647 } 648 649 usbd_status 650 ohci_init(ohci_softc_t *sc) 651 { 652 ohci_soft_ed_t *sed, *psed; 653 usbd_status err; 654 int i; 655 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 656 657 DPRINTF(("ohci_init: start\n")); 658 aprint_normal_dev(sc->sc_dev, ""); 659 660 sc->sc_hcca = NULL; 661 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 662 663 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 664 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 665 cv_init(&sc->sc_softwake_cv, "ohciab"); 666 667 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 668 ohci_rhsc_softint, sc); 669 670 for (i = 0; i < OHCI_HASH_SIZE; i++) 671 LIST_INIT(&sc->sc_hash_tds[i]); 672 for (i = 0; i < OHCI_HASH_SIZE; i++) 673 LIST_INIT(&sc->sc_hash_itds[i]); 674 675 SIMPLEQ_INIT(&sc->sc_free_xfers); 676 677 rev = OREAD4(sc, OHCI_REVISION); 678 aprint_normal("OHCI version %d.%d%s\n", 679 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 680 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 681 682 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 683 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 684 sc->sc_bus.usbrev = USBREV_UNKNOWN; 685 return (USBD_INVAL); 686 } 687 sc->sc_bus.usbrev = USBREV_1_0; 688 689 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 690 USB_MEM_RESERVE); 691 692 /* XXX determine alignment by R/W */ 693 /* Allocate the HCCA area. */ 694 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 695 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 696 if (err) { 697 sc->sc_hcca = NULL; 698 return err; 699 } 700 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 701 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 702 703 sc->sc_eintrs = OHCI_NORMAL_INTRS; 704 705 /* Allocate dummy ED that starts the control list. */ 706 sc->sc_ctrl_head = ohci_alloc_sed(sc); 707 if (sc->sc_ctrl_head == NULL) { 708 err = USBD_NOMEM; 709 goto bad1; 710 } 711 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 712 713 /* Allocate dummy ED that starts the bulk list. */ 714 sc->sc_bulk_head = ohci_alloc_sed(sc); 715 if (sc->sc_bulk_head == NULL) { 716 err = USBD_NOMEM; 717 goto bad2; 718 } 719 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 720 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 721 sizeof(sc->sc_bulk_head->ed), 722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 723 724 /* Allocate dummy ED that starts the isochronous list. */ 725 sc->sc_isoc_head = ohci_alloc_sed(sc); 726 if (sc->sc_isoc_head == NULL) { 727 err = USBD_NOMEM; 728 goto bad3; 729 } 730 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 731 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 732 sizeof(sc->sc_isoc_head->ed), 733 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 734 735 /* Allocate all the dummy EDs that make up the interrupt tree. */ 736 for (i = 0; i < OHCI_NO_EDS; i++) { 737 sed = ohci_alloc_sed(sc); 738 if (sed == NULL) { 739 while (--i >= 0) 740 ohci_free_sed(sc, sc->sc_eds[i]); 741 err = USBD_NOMEM; 742 goto bad4; 743 } 744 /* All ED fields are set to 0. */ 745 sc->sc_eds[i] = sed; 746 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 747 if (i != 0) 748 psed = sc->sc_eds[(i-1) / 2]; 749 else 750 psed= sc->sc_isoc_head; 751 sed->next = psed; 752 sed->ed.ed_nexted = HTOO32(psed->physaddr); 753 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 754 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 755 } 756 /* 757 * Fill HCCA interrupt table. The bit reversal is to get 758 * the tree set up properly to spread the interrupts. 759 */ 760 for (i = 0; i < OHCI_NO_INTRS; i++) 761 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 762 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 763 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 764 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 765 766 #ifdef OHCI_DEBUG 767 if (ohcidebug > 15) { 768 for (i = 0; i < OHCI_NO_EDS; i++) { 769 printf("ed#%d ", i); 770 ohci_dump_ed(sc, sc->sc_eds[i]); 771 } 772 printf("iso "); 773 ohci_dump_ed(sc, sc->sc_isoc_head); 774 } 775 #endif 776 777 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 778 ctl = OREAD4(sc, OHCI_CONTROL); 779 rwc = ctl & OHCI_RWC; 780 fm = OREAD4(sc, OHCI_FM_INTERVAL); 781 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 782 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 783 784 /* Determine in what context we are running. */ 785 if (ctl & OHCI_IR) { 786 /* SMM active, request change */ 787 DPRINTF(("ohci_init: SMM active, request owner change\n")); 788 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 789 (OHCI_OC | OHCI_MIE)) 790 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 791 s = OREAD4(sc, OHCI_COMMAND_STATUS); 792 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 793 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 794 usb_delay_ms(&sc->sc_bus, 1); 795 ctl = OREAD4(sc, OHCI_CONTROL); 796 } 797 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 798 if ((ctl & OHCI_IR) == 0) { 799 aprint_error_dev(sc->sc_dev, 800 "SMM does not respond, resetting\n"); 801 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 802 goto reset; 803 } 804 #if 0 805 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 806 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 807 /* BIOS started controller. */ 808 DPRINTF(("ohci_init: BIOS active\n")); 809 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 810 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 811 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 812 } 813 #endif 814 } else { 815 DPRINTF(("ohci_init: cold started\n")); 816 reset: 817 /* Controller was cold started. */ 818 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 819 } 820 821 /* 822 * This reset should not be necessary according to the OHCI spec, but 823 * without it some controllers do not start. 824 */ 825 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 826 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 827 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 828 829 /* We now own the host controller and the bus has been reset. */ 830 831 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 832 /* Nominal time for a reset is 10 us. */ 833 for (i = 0; i < 10; i++) { 834 delay(10); 835 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 836 if (!hcr) 837 break; 838 } 839 if (hcr) { 840 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 841 err = USBD_IOERROR; 842 goto bad5; 843 } 844 #ifdef OHCI_DEBUG 845 if (ohcidebug > 15) 846 ohci_dumpregs(sc); 847 #endif 848 849 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 850 851 /* Set up HC registers. */ 852 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 853 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 854 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 855 /* disable all interrupts and then switch on all desired interrupts */ 856 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 857 /* switch on desired functional features */ 858 ctl = OREAD4(sc, OHCI_CONTROL); 859 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 860 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 861 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 862 /* And finally start it! */ 863 OWRITE4(sc, OHCI_CONTROL, ctl); 864 865 /* 866 * The controller is now OPERATIONAL. Set a some final 867 * registers that should be set earlier, but that the 868 * controller ignores when in the SUSPEND state. 869 */ 870 ival = OHCI_GET_IVAL(fm); 871 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 872 fm |= OHCI_FSMPS(ival) | ival; 873 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 874 per = OHCI_PERIODIC(ival); /* 90% periodic */ 875 OWRITE4(sc, OHCI_PERIODIC_START, per); 876 877 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 878 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 879 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 880 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 881 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 882 883 /* 884 * The AMD756 requires a delay before re-reading the register, 885 * otherwise it will occasionally report 0 ports. 886 */ 887 sc->sc_noport = 0; 888 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 889 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 890 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 891 } 892 893 #ifdef OHCI_DEBUG 894 if (ohcidebug > 5) 895 ohci_dumpregs(sc); 896 #endif 897 898 /* Set up the bus struct. */ 899 sc->sc_bus.methods = &ohci_bus_methods; 900 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 901 902 sc->sc_control = sc->sc_intre = 0; 903 904 /* Finally, turn on interrupts. */ 905 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 906 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 907 908 return (USBD_NORMAL_COMPLETION); 909 910 bad5: 911 for (i = 0; i < OHCI_NO_EDS; i++) 912 ohci_free_sed(sc, sc->sc_eds[i]); 913 bad4: 914 ohci_free_sed(sc, sc->sc_isoc_head); 915 bad3: 916 ohci_free_sed(sc, sc->sc_bulk_head); 917 bad2: 918 ohci_free_sed(sc, sc->sc_ctrl_head); 919 bad1: 920 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 921 sc->sc_hcca = NULL; 922 return (err); 923 } 924 925 usbd_status 926 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 927 { 928 struct ohci_softc *sc = bus->hci_private; 929 usbd_status status; 930 931 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 932 if (status == USBD_NOMEM) 933 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 934 return status; 935 } 936 937 void 938 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 939 { 940 struct ohci_softc *sc = bus->hci_private; 941 if (dma->block->flags & USB_DMA_RESERVE) { 942 usb_reserve_freem(&sc->sc_dma_reserve, dma); 943 return; 944 } 945 usb_freemem(&sc->sc_bus, dma); 946 } 947 948 usbd_xfer_handle 949 ohci_allocx(struct usbd_bus *bus) 950 { 951 struct ohci_softc *sc = bus->hci_private; 952 usbd_xfer_handle xfer; 953 954 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 955 if (xfer != NULL) { 956 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 957 #ifdef DIAGNOSTIC 958 if (xfer->busy_free != XFER_FREE) { 959 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 960 xfer->busy_free); 961 } 962 #endif 963 } else { 964 xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP); 965 } 966 if (xfer != NULL) { 967 memset(xfer, 0, sizeof (struct ohci_xfer)); 968 #ifdef DIAGNOSTIC 969 xfer->busy_free = XFER_BUSY; 970 #endif 971 } 972 return (xfer); 973 } 974 975 void 976 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 977 { 978 struct ohci_softc *sc = bus->hci_private; 979 980 #ifdef DIAGNOSTIC 981 if (xfer->busy_free != XFER_BUSY) { 982 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 983 xfer->busy_free); 984 } 985 xfer->busy_free = XFER_FREE; 986 #endif 987 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 988 } 989 990 Static void 991 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 992 { 993 struct ohci_softc *sc = bus->hci_private; 994 995 *lock = &sc->sc_lock; 996 } 997 998 /* 999 * Shut down the controller when the system is going down. 1000 */ 1001 bool 1002 ohci_shutdown(device_t self, int flags) 1003 { 1004 ohci_softc_t *sc = device_private(self); 1005 1006 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1007 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1008 return true; 1009 } 1010 1011 bool 1012 ohci_resume(device_t dv, const pmf_qual_t *qual) 1013 { 1014 ohci_softc_t *sc = device_private(dv); 1015 uint32_t ctl; 1016 1017 mutex_spin_enter(&sc->sc_intr_lock); 1018 sc->sc_bus.use_polling++; 1019 mutex_spin_exit(&sc->sc_intr_lock); 1020 1021 /* Some broken BIOSes do not recover these values */ 1022 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1023 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1024 sc->sc_ctrl_head->physaddr); 1025 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1026 sc->sc_bulk_head->physaddr); 1027 if (sc->sc_intre) 1028 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1029 (OHCI_ALL_INTRS | OHCI_MIE)); 1030 if (sc->sc_control) 1031 ctl = sc->sc_control; 1032 else 1033 ctl = OREAD4(sc, OHCI_CONTROL); 1034 ctl |= OHCI_HCFS_RESUME; 1035 OWRITE4(sc, OHCI_CONTROL, ctl); 1036 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1037 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1038 OWRITE4(sc, OHCI_CONTROL, ctl); 1039 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1040 sc->sc_control = sc->sc_intre = 0; 1041 1042 mutex_spin_enter(&sc->sc_intr_lock); 1043 sc->sc_bus.use_polling--; 1044 mutex_spin_exit(&sc->sc_intr_lock); 1045 1046 return true; 1047 } 1048 1049 bool 1050 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1051 { 1052 ohci_softc_t *sc = device_private(dv); 1053 uint32_t ctl; 1054 1055 mutex_spin_enter(&sc->sc_intr_lock); 1056 sc->sc_bus.use_polling++; 1057 mutex_spin_exit(&sc->sc_intr_lock); 1058 1059 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1060 if (sc->sc_control == 0) { 1061 /* 1062 * Preserve register values, in case that BIOS 1063 * does not recover them. 1064 */ 1065 sc->sc_control = ctl; 1066 sc->sc_intre = OREAD4(sc, 1067 OHCI_INTERRUPT_ENABLE); 1068 } 1069 ctl |= OHCI_HCFS_SUSPEND; 1070 OWRITE4(sc, OHCI_CONTROL, ctl); 1071 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1072 1073 mutex_spin_enter(&sc->sc_intr_lock); 1074 sc->sc_bus.use_polling--; 1075 mutex_spin_exit(&sc->sc_intr_lock); 1076 1077 return true; 1078 } 1079 1080 #ifdef OHCI_DEBUG 1081 void 1082 ohci_dumpregs(ohci_softc_t *sc) 1083 { 1084 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1085 OREAD4(sc, OHCI_REVISION), 1086 OREAD4(sc, OHCI_CONTROL), 1087 OREAD4(sc, OHCI_COMMAND_STATUS))); 1088 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1089 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1090 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1091 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1092 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1093 OREAD4(sc, OHCI_HCCA), 1094 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1095 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1096 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1097 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1098 OREAD4(sc, OHCI_BULK_HEAD_ED), 1099 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1100 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1101 OREAD4(sc, OHCI_DONE_HEAD), 1102 OREAD4(sc, OHCI_FM_INTERVAL), 1103 OREAD4(sc, OHCI_FM_REMAINING))); 1104 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1105 OREAD4(sc, OHCI_FM_NUMBER), 1106 OREAD4(sc, OHCI_PERIODIC_START), 1107 OREAD4(sc, OHCI_LS_THRESHOLD))); 1108 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1109 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1110 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1111 OREAD4(sc, OHCI_RH_STATUS))); 1112 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1113 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1114 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1115 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1116 O32TOH(sc->sc_hcca->hcca_frame_number), 1117 O32TOH(sc->sc_hcca->hcca_done_head))); 1118 } 1119 #endif 1120 1121 Static int ohci_intr1(ohci_softc_t *); 1122 1123 int 1124 ohci_intr(void *p) 1125 { 1126 ohci_softc_t *sc = p; 1127 int ret = 0; 1128 1129 if (sc == NULL) 1130 return (0); 1131 1132 mutex_spin_enter(&sc->sc_intr_lock); 1133 1134 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1135 goto done; 1136 1137 /* If we get an interrupt while polling, then just ignore it. */ 1138 if (sc->sc_bus.use_polling) { 1139 #ifdef DIAGNOSTIC 1140 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1141 #endif 1142 /* for level triggered intrs, should do something to ack */ 1143 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1144 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1145 1146 goto done; 1147 } 1148 1149 ret = ohci_intr1(sc); 1150 1151 done: 1152 mutex_spin_exit(&sc->sc_intr_lock); 1153 return ret; 1154 } 1155 1156 Static int 1157 ohci_intr1(ohci_softc_t *sc) 1158 { 1159 u_int32_t intrs, eintrs; 1160 1161 DPRINTFN(14,("ohci_intr1: enter\n")); 1162 1163 /* In case the interrupt occurs before initialization has completed. */ 1164 if (sc == NULL || sc->sc_hcca == NULL) { 1165 #ifdef DIAGNOSTIC 1166 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1167 #endif 1168 return (0); 1169 } 1170 1171 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1172 1173 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1174 if (!intrs) 1175 return (0); 1176 1177 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1178 eintrs = intrs & sc->sc_eintrs; 1179 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1180 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1181 (u_int)eintrs, sc->sc_eintrs)); 1182 1183 if (!eintrs) { 1184 return (0); 1185 } 1186 1187 sc->sc_bus.no_intrs++; 1188 if (eintrs & OHCI_SO) { 1189 sc->sc_overrun_cnt++; 1190 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1191 printf("%s: %u scheduling overruns\n", 1192 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1193 sc->sc_overrun_cnt = 0; 1194 } 1195 /* XXX do what */ 1196 eintrs &= ~OHCI_SO; 1197 } 1198 if (eintrs & OHCI_WDH) { 1199 /* 1200 * We block the interrupt below, and reenable it later from 1201 * ohci_softintr(). 1202 */ 1203 usb_schedsoftintr(&sc->sc_bus); 1204 } 1205 if (eintrs & OHCI_RD) { 1206 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1207 /* XXX process resume detect */ 1208 } 1209 if (eintrs & OHCI_UE) { 1210 printf("%s: unrecoverable error, controller halted\n", 1211 device_xname(sc->sc_dev)); 1212 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1213 /* XXX what else */ 1214 } 1215 if (eintrs & OHCI_RHSC) { 1216 /* 1217 * We block the interrupt below, and reenable it later from 1218 * a timeout. 1219 */ 1220 softint_schedule(sc->sc_rhsc_si); 1221 } 1222 1223 if (eintrs != 0) { 1224 /* Block unprocessed interrupts. */ 1225 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1226 sc->sc_eintrs &= ~eintrs; 1227 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1228 device_xname(sc->sc_dev), eintrs)); 1229 } 1230 1231 return (1); 1232 } 1233 1234 void 1235 ohci_rhsc_enable(void *v_sc) 1236 { 1237 ohci_softc_t *sc = v_sc; 1238 1239 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1240 mutex_spin_enter(&sc->sc_intr_lock); 1241 sc->sc_eintrs |= OHCI_RHSC; 1242 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1243 mutex_spin_exit(&sc->sc_intr_lock); 1244 } 1245 1246 #ifdef OHCI_DEBUG 1247 const char *ohci_cc_strs[] = { 1248 "NO_ERROR", 1249 "CRC", 1250 "BIT_STUFFING", 1251 "DATA_TOGGLE_MISMATCH", 1252 "STALL", 1253 "DEVICE_NOT_RESPONDING", 1254 "PID_CHECK_FAILURE", 1255 "UNEXPECTED_PID", 1256 "DATA_OVERRUN", 1257 "DATA_UNDERRUN", 1258 "BUFFER_OVERRUN", 1259 "BUFFER_UNDERRUN", 1260 "reserved", 1261 "reserved", 1262 "NOT_ACCESSED", 1263 "NOT_ACCESSED", 1264 }; 1265 #endif 1266 1267 void 1268 ohci_softintr(void *v) 1269 { 1270 struct usbd_bus *bus = v; 1271 ohci_softc_t *sc = bus->hci_private; 1272 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1273 ohci_soft_td_t *std, *sdone, *stdnext; 1274 usbd_xfer_handle xfer; 1275 struct ohci_pipe *opipe; 1276 int len, cc; 1277 int i, j, actlen, iframes, uedir; 1278 ohci_physaddr_t done; 1279 1280 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1281 1282 DPRINTFN(10,("ohci_softintr: enter\n")); 1283 1284 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1285 sizeof(sc->sc_hcca->hcca_done_head), 1286 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1287 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1288 sc->sc_hcca->hcca_done_head = 0; 1289 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1290 sizeof(sc->sc_hcca->hcca_done_head), 1291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1292 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1293 sc->sc_eintrs |= OHCI_WDH; 1294 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1295 1296 /* Reverse the done list. */ 1297 for (sdone = NULL, sidone = NULL; done != 0; ) { 1298 std = ohci_hash_find_td(sc, done); 1299 if (std != NULL) { 1300 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1301 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1302 std->dnext = sdone; 1303 done = O32TOH(std->td.td_nexttd); 1304 sdone = std; 1305 DPRINTFN(10,("add TD %p\n", std)); 1306 continue; 1307 } 1308 sitd = ohci_hash_find_itd(sc, done); 1309 if (sitd != NULL) { 1310 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1312 sitd->dnext = sidone; 1313 done = O32TOH(sitd->itd.itd_nextitd); 1314 sidone = sitd; 1315 DPRINTFN(5,("add ITD %p\n", sitd)); 1316 continue; 1317 } 1318 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1319 (u_long)done); 1320 break; 1321 } 1322 1323 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1324 1325 #ifdef OHCI_DEBUG 1326 if (ohcidebug > 10) { 1327 DPRINTF(("ohci_process_done: TD done:\n")); 1328 ohci_dump_tds(sc, sdone); 1329 } 1330 #endif 1331 1332 for (std = sdone; std; std = stdnext) { 1333 xfer = std->xfer; 1334 stdnext = std->dnext; 1335 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1336 std, xfer, xfer ? xfer->hcpriv : 0)); 1337 if (xfer == NULL) { 1338 /* 1339 * xfer == NULL: There seems to be no xfer associated 1340 * with this TD. It is tailp that happened to end up on 1341 * the done queue. 1342 * Shouldn't happen, but some chips are broken(?). 1343 */ 1344 continue; 1345 } 1346 if (xfer->status == USBD_CANCELLED || 1347 xfer->status == USBD_TIMEOUT) { 1348 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1349 xfer)); 1350 /* Handled by abort routine. */ 1351 continue; 1352 } 1353 callout_stop(&xfer->timeout_handle); 1354 1355 len = std->len; 1356 if (std->td.td_cbp != 0) 1357 len -= O32TOH(std->td.td_be) - 1358 O32TOH(std->td.td_cbp) + 1; 1359 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1360 std->flags)); 1361 if (std->flags & OHCI_ADD_LEN) 1362 xfer->actlen += len; 1363 1364 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1365 if (cc == OHCI_CC_NO_ERROR) { 1366 if (std->flags & OHCI_CALL_DONE) { 1367 xfer->status = USBD_NORMAL_COMPLETION; 1368 usb_transfer_complete(xfer); 1369 } 1370 ohci_free_std(sc, std); 1371 } else { 1372 /* 1373 * Endpoint is halted. First unlink all the TDs 1374 * belonging to the failed transfer, and then restart 1375 * the endpoint. 1376 */ 1377 ohci_soft_td_t *p, *n; 1378 opipe = (struct ohci_pipe *)xfer->pipe; 1379 1380 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1381 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1382 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1383 1384 /* remove TDs */ 1385 for (p = std; p->xfer == xfer; p = n) { 1386 n = p->nexttd; 1387 ohci_free_std(sc, p); 1388 } 1389 1390 /* clear halt */ 1391 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1392 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1393 1394 if (cc == OHCI_CC_STALL) 1395 xfer->status = USBD_STALLED; 1396 else 1397 xfer->status = USBD_IOERROR; 1398 usb_transfer_complete(xfer); 1399 } 1400 } 1401 1402 #ifdef OHCI_DEBUG 1403 if (ohcidebug > 10) { 1404 DPRINTF(("ohci_softintr: ITD done:\n")); 1405 ohci_dump_itds(sc, sidone); 1406 } 1407 #endif 1408 1409 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1410 xfer = sitd->xfer; 1411 sitdnext = sitd->dnext; 1412 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1413 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1414 if (xfer == NULL) 1415 continue; 1416 if (xfer->status == USBD_CANCELLED || 1417 xfer->status == USBD_TIMEOUT) { 1418 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1419 xfer)); 1420 /* Handled by abort routine. */ 1421 continue; 1422 } 1423 #ifdef DIAGNOSTIC 1424 if (sitd->isdone) 1425 printf("ohci_softintr: sitd=%p is done\n", sitd); 1426 sitd->isdone = 1; 1427 #endif 1428 if (sitd->flags & OHCI_CALL_DONE) { 1429 ohci_soft_itd_t *next; 1430 1431 opipe = (struct ohci_pipe *)xfer->pipe; 1432 opipe->u.iso.inuse -= xfer->nframes; 1433 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1434 bEndpointAddress); 1435 xfer->status = USBD_NORMAL_COMPLETION; 1436 actlen = 0; 1437 for (i = 0, sitd = xfer->hcpriv;; 1438 sitd = next) { 1439 next = sitd->nextitd; 1440 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1441 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1442 xfer->status = USBD_IOERROR; 1443 /* For input, update frlengths with actual */ 1444 /* XXX anything necessary for output? */ 1445 if (uedir == UE_DIR_IN && 1446 xfer->status == USBD_NORMAL_COMPLETION) { 1447 iframes = OHCI_ITD_GET_FC(O32TOH( 1448 sitd->itd.itd_flags)); 1449 for (j = 0; j < iframes; i++, j++) { 1450 len = O16TOH(sitd-> 1451 itd.itd_offset[j]); 1452 if ((OHCI_ITD_PSW_GET_CC(len) & 1453 OHCI_CC_NOT_ACCESSED_MASK) 1454 == OHCI_CC_NOT_ACCESSED) 1455 len = 0; 1456 else 1457 len = OHCI_ITD_PSW_LENGTH(len); 1458 xfer->frlengths[i] = len; 1459 actlen += len; 1460 } 1461 } 1462 if (sitd->flags & OHCI_CALL_DONE) 1463 break; 1464 ohci_free_sitd(sc, sitd); 1465 } 1466 ohci_free_sitd(sc, sitd); 1467 if (uedir == UE_DIR_IN && 1468 xfer->status == USBD_NORMAL_COMPLETION) 1469 xfer->actlen = actlen; 1470 xfer->hcpriv = NULL; 1471 1472 usb_transfer_complete(xfer); 1473 } 1474 } 1475 1476 if (sc->sc_softwake) { 1477 sc->sc_softwake = 0; 1478 cv_broadcast(&sc->sc_softwake_cv); 1479 } 1480 1481 DPRINTFN(10,("ohci_softintr: done:\n")); 1482 } 1483 1484 void 1485 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1486 { 1487 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1488 #ifdef DIAGNOSTIC 1489 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1490 #endif 1491 int len = UGETW(xfer->request.wLength); 1492 int isread = (xfer->request.bmRequestType & UT_READ); 1493 1494 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1495 1496 KASSERT(mutex_owned(&sc->sc_lock)); 1497 1498 #ifdef DIAGNOSTIC 1499 if (!(xfer->rqflags & URQ_REQUEST)) { 1500 panic("ohci_device_ctrl_done: not a request"); 1501 } 1502 #endif 1503 if (len) 1504 usb_syncmem(&xfer->dmabuf, 0, len, 1505 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1506 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1507 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1508 } 1509 1510 void 1511 ohci_device_intr_done(usbd_xfer_handle xfer) 1512 { 1513 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1514 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1515 ohci_soft_ed_t *sed = opipe->sed; 1516 ohci_soft_td_t *data, *tail; 1517 int isread = 1518 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1519 1520 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1521 xfer, xfer->actlen)); 1522 1523 KASSERT(mutex_owned(&sc->sc_lock)); 1524 1525 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1526 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1527 if (xfer->pipe->repeat) { 1528 data = opipe->tail.td; 1529 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1530 if (tail == NULL) { 1531 xfer->status = USBD_NOMEM; 1532 return; 1533 } 1534 tail->xfer = NULL; 1535 1536 data->td.td_flags = HTOO32( 1537 OHCI_TD_IN | OHCI_TD_NOCC | 1538 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1539 if (xfer->flags & USBD_SHORT_XFER_OK) 1540 data->td.td_flags |= HTOO32(OHCI_TD_R); 1541 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1542 data->nexttd = tail; 1543 data->td.td_nexttd = HTOO32(tail->physaddr); 1544 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1545 xfer->length - 1); 1546 data->len = xfer->length; 1547 data->xfer = xfer; 1548 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1549 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1550 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1551 xfer->hcpriv = data; 1552 xfer->actlen = 0; 1553 1554 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1555 usb_syncmem(&sed->dma, 1556 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1557 sizeof(sed->ed.ed_tailp), 1558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1559 opipe->tail.td = tail; 1560 } 1561 } 1562 1563 void 1564 ohci_device_bulk_done(usbd_xfer_handle xfer) 1565 { 1566 #ifdef DIAGNOSTIC 1567 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1568 #endif 1569 int isread = 1570 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1571 1572 KASSERT(mutex_owned(&sc->sc_lock)); 1573 1574 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1575 xfer, xfer->actlen)); 1576 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1577 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1578 } 1579 1580 Static void 1581 ohci_rhsc_softint(void *arg) 1582 { 1583 ohci_softc_t *sc = arg; 1584 1585 mutex_enter(&sc->sc_lock); 1586 1587 ohci_rhsc(sc, sc->sc_intrxfer); 1588 1589 /* Do not allow RHSC interrupts > 1 per second */ 1590 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1591 1592 mutex_exit(&sc->sc_lock); 1593 } 1594 1595 void 1596 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1597 { 1598 usbd_pipe_handle pipe; 1599 u_char *p; 1600 int i, m; 1601 int hstatus; 1602 1603 KASSERT(mutex_owned(&sc->sc_lock)); 1604 1605 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1606 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1607 sc, xfer, hstatus)); 1608 1609 if (xfer == NULL) { 1610 /* Just ignore the change. */ 1611 return; 1612 } 1613 1614 pipe = xfer->pipe; 1615 1616 p = KERNADDR(&xfer->dmabuf, 0); 1617 m = min(sc->sc_noport, xfer->length * 8 - 1); 1618 memset(p, 0, xfer->length); 1619 for (i = 1; i <= m; i++) { 1620 /* Pick out CHANGE bits from the status reg. */ 1621 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1622 p[i/8] |= 1 << (i%8); 1623 } 1624 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1625 xfer->actlen = xfer->length; 1626 xfer->status = USBD_NORMAL_COMPLETION; 1627 1628 usb_transfer_complete(xfer); 1629 } 1630 1631 void 1632 ohci_root_intr_done(usbd_xfer_handle xfer) 1633 { 1634 } 1635 1636 void 1637 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1638 { 1639 } 1640 1641 /* 1642 * Wait here until controller claims to have an interrupt. 1643 * Then call ohci_intr and return. Use timeout to avoid waiting 1644 * too long. 1645 */ 1646 void 1647 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1648 { 1649 int timo; 1650 u_int32_t intrs; 1651 1652 mutex_enter(&sc->sc_lock); 1653 1654 xfer->status = USBD_IN_PROGRESS; 1655 for (timo = xfer->timeout; timo >= 0; timo--) { 1656 usb_delay_ms(&sc->sc_bus, 1); 1657 if (sc->sc_dying) 1658 break; 1659 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1660 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1661 #ifdef OHCI_DEBUG 1662 if (ohcidebug > 15) 1663 ohci_dumpregs(sc); 1664 #endif 1665 if (intrs) { 1666 mutex_spin_enter(&sc->sc_intr_lock); 1667 ohci_intr1(sc); 1668 mutex_spin_exit(&sc->sc_intr_lock); 1669 if (xfer->status != USBD_IN_PROGRESS) 1670 goto done; 1671 } 1672 } 1673 1674 /* Timeout */ 1675 DPRINTF(("ohci_waitintr: timeout\n")); 1676 xfer->status = USBD_TIMEOUT; 1677 usb_transfer_complete(xfer); 1678 1679 /* XXX should free TD */ 1680 1681 done: 1682 mutex_exit(&sc->sc_lock); 1683 } 1684 1685 void 1686 ohci_poll(struct usbd_bus *bus) 1687 { 1688 ohci_softc_t *sc = bus->hci_private; 1689 #ifdef OHCI_DEBUG 1690 static int last; 1691 int new; 1692 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1693 if (new != last) { 1694 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1695 last = new; 1696 } 1697 #endif 1698 1699 sc->sc_eintrs |= OHCI_WDH; 1700 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1701 mutex_spin_enter(&sc->sc_intr_lock); 1702 ohci_intr1(sc); 1703 mutex_spin_exit(&sc->sc_intr_lock); 1704 } 1705 } 1706 1707 usbd_status 1708 ohci_device_request(usbd_xfer_handle xfer) 1709 { 1710 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1711 usb_device_request_t *req = &xfer->request; 1712 usbd_device_handle dev = opipe->pipe.device; 1713 ohci_softc_t *sc = dev->bus->hci_private; 1714 int addr = dev->address; 1715 ohci_soft_td_t *setup, *stat, *next, *tail; 1716 ohci_soft_ed_t *sed; 1717 int isread; 1718 int len; 1719 usbd_status err; 1720 1721 KASSERT(mutex_owned(&sc->sc_lock)); 1722 1723 isread = req->bmRequestType & UT_READ; 1724 len = UGETW(req->wLength); 1725 1726 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1727 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1728 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1729 UGETW(req->wIndex), len, addr, 1730 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1731 1732 setup = opipe->tail.td; 1733 stat = ohci_alloc_std(sc); 1734 if (stat == NULL) { 1735 err = USBD_NOMEM; 1736 goto bad1; 1737 } 1738 tail = ohci_alloc_std(sc); 1739 if (tail == NULL) { 1740 err = USBD_NOMEM; 1741 goto bad2; 1742 } 1743 tail->xfer = NULL; 1744 1745 sed = opipe->sed; 1746 opipe->u.ctl.length = len; 1747 1748 /* Update device address and length since they may have changed 1749 during the setup of the control pipe in usbd_new_device(). */ 1750 /* XXX This only needs to be done once, but it's too early in open. */ 1751 /* XXXX Should not touch ED here! */ 1752 1753 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1754 sizeof(sed->ed.ed_flags), 1755 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1756 sed->ed.ed_flags = HTOO32( 1757 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1758 OHCI_ED_SET_FA(addr) | 1759 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1760 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1761 sizeof(sed->ed.ed_flags), 1762 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1763 1764 next = stat; 1765 1766 /* Set up data transaction */ 1767 if (len != 0) { 1768 ohci_soft_td_t *std = stat; 1769 1770 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1771 std, &stat); 1772 stat = stat->nexttd; /* point at free TD */ 1773 if (err) 1774 goto bad3; 1775 /* Start toggle at 1 and then use the carried toggle. */ 1776 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1777 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1778 usb_syncmem(&std->dma, 1779 std->offs + offsetof(ohci_td_t, td_flags), 1780 sizeof(std->td.td_flags), 1781 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1782 } 1783 1784 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1785 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1786 1787 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1788 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1789 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1790 setup->nexttd = next; 1791 setup->td.td_nexttd = HTOO32(next->physaddr); 1792 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1793 setup->len = 0; 1794 setup->xfer = xfer; 1795 setup->flags = 0; 1796 xfer->hcpriv = setup; 1797 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1798 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1799 1800 stat->td.td_flags = HTOO32( 1801 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1802 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1803 stat->td.td_cbp = 0; 1804 stat->nexttd = tail; 1805 stat->td.td_nexttd = HTOO32(tail->physaddr); 1806 stat->td.td_be = 0; 1807 stat->flags = OHCI_CALL_DONE; 1808 stat->len = 0; 1809 stat->xfer = xfer; 1810 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1811 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1812 1813 #ifdef OHCI_DEBUG 1814 if (ohcidebug > 5) { 1815 DPRINTF(("ohci_device_request:\n")); 1816 ohci_dump_ed(sc, sed); 1817 ohci_dump_tds(sc, setup); 1818 } 1819 #endif 1820 1821 /* Insert ED in schedule */ 1822 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1823 usb_syncmem(&sed->dma, 1824 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1825 sizeof(sed->ed.ed_tailp), 1826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1827 opipe->tail.td = tail; 1828 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1829 if (xfer->timeout && !sc->sc_bus.use_polling) { 1830 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1831 ohci_timeout, xfer); 1832 } 1833 1834 #ifdef OHCI_DEBUG 1835 if (ohcidebug > 20) { 1836 delay(10000); 1837 DPRINTF(("ohci_device_request: status=%x\n", 1838 OREAD4(sc, OHCI_COMMAND_STATUS))); 1839 ohci_dumpregs(sc); 1840 printf("ctrl head:\n"); 1841 ohci_dump_ed(sc, sc->sc_ctrl_head); 1842 printf("sed:\n"); 1843 ohci_dump_ed(sc, sed); 1844 ohci_dump_tds(sc, setup); 1845 } 1846 #endif 1847 1848 return (USBD_NORMAL_COMPLETION); 1849 1850 bad3: 1851 ohci_free_std(sc, tail); 1852 bad2: 1853 ohci_free_std(sc, stat); 1854 bad1: 1855 return (err); 1856 } 1857 1858 /* 1859 * Add an ED to the schedule. Called with USB lock held. 1860 */ 1861 Static void 1862 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1863 { 1864 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1865 1866 KASSERT(mutex_owned(&sc->sc_lock)); 1867 1868 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1869 sizeof(head->ed.ed_nexted), 1870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1871 sed->next = head->next; 1872 sed->ed.ed_nexted = head->ed.ed_nexted; 1873 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1874 sizeof(sed->ed.ed_nexted), 1875 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1876 head->next = sed; 1877 head->ed.ed_nexted = HTOO32(sed->physaddr); 1878 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1879 sizeof(head->ed.ed_nexted), 1880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1881 } 1882 1883 /* 1884 * Remove an ED from the schedule. Called with USB lock held. 1885 */ 1886 Static void 1887 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1888 { 1889 ohci_soft_ed_t *p; 1890 1891 KASSERT(mutex_owned(&sc->sc_lock)); 1892 1893 /* XXX */ 1894 for (p = head; p != NULL && p->next != sed; p = p->next) 1895 ; 1896 if (p == NULL) 1897 panic("ohci_rem_ed: ED not found"); 1898 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1899 sizeof(sed->ed.ed_nexted), 1900 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1901 p->next = sed->next; 1902 p->ed.ed_nexted = sed->ed.ed_nexted; 1903 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1904 sizeof(p->ed.ed_nexted), 1905 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1906 } 1907 1908 /* 1909 * When a transfer is completed the TD is added to the done queue by 1910 * the host controller. This queue is the processed by software. 1911 * Unfortunately the queue contains the physical address of the TD 1912 * and we have no simple way to translate this back to a kernel address. 1913 * To make the translation possible (and fast) we use a hash table of 1914 * TDs currently in the schedule. The physical address is used as the 1915 * hash value. 1916 */ 1917 1918 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1919 /* Called with USB lock held. */ 1920 void 1921 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1922 { 1923 int h = HASH(std->physaddr); 1924 1925 KASSERT(mutex_owned(&sc->sc_lock)); 1926 1927 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1928 } 1929 1930 /* Called with USB lock held. */ 1931 void 1932 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1933 { 1934 1935 KASSERT(mutex_owned(&sc->sc_lock)); 1936 1937 LIST_REMOVE(std, hnext); 1938 } 1939 1940 ohci_soft_td_t * 1941 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1942 { 1943 int h = HASH(a); 1944 ohci_soft_td_t *std; 1945 1946 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1947 std != NULL; 1948 std = LIST_NEXT(std, hnext)) 1949 if (std->physaddr == a) 1950 return (std); 1951 return (NULL); 1952 } 1953 1954 /* Called with USB lock held. */ 1955 void 1956 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1957 { 1958 int h = HASH(sitd->physaddr); 1959 1960 KASSERT(mutex_owned(&sc->sc_lock)); 1961 1962 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1963 sitd, (u_long)sitd->physaddr)); 1964 1965 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1966 } 1967 1968 /* Called with USB lock held. */ 1969 void 1970 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1971 { 1972 1973 KASSERT(mutex_owned(&sc->sc_lock)); 1974 1975 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1976 sitd, (u_long)sitd->physaddr)); 1977 1978 LIST_REMOVE(sitd, hnext); 1979 } 1980 1981 ohci_soft_itd_t * 1982 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1983 { 1984 int h = HASH(a); 1985 ohci_soft_itd_t *sitd; 1986 1987 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1988 sitd != NULL; 1989 sitd = LIST_NEXT(sitd, hnext)) 1990 if (sitd->physaddr == a) 1991 return (sitd); 1992 return (NULL); 1993 } 1994 1995 void 1996 ohci_timeout(void *addr) 1997 { 1998 struct ohci_xfer *oxfer = addr; 1999 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2000 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2001 2002 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2003 2004 if (sc->sc_dying) { 2005 mutex_enter(&sc->sc_lock); 2006 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2007 mutex_exit(&sc->sc_lock); 2008 return; 2009 } 2010 2011 /* Execute the abort in a process context. */ 2012 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2013 USB_TASKQ_MPSAFE); 2014 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2015 USB_TASKQ_HC); 2016 } 2017 2018 void 2019 ohci_timeout_task(void *addr) 2020 { 2021 usbd_xfer_handle xfer = addr; 2022 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2023 2024 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2025 2026 mutex_enter(&sc->sc_lock); 2027 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2028 mutex_exit(&sc->sc_lock); 2029 } 2030 2031 #ifdef OHCI_DEBUG 2032 void 2033 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2034 { 2035 for (; std; std = std->nexttd) 2036 ohci_dump_td(sc, std); 2037 } 2038 2039 void 2040 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2041 { 2042 char sbuf[128]; 2043 2044 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2046 snprintb(sbuf, sizeof(sbuf), 2047 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2048 (u_int32_t)O32TOH(std->td.td_flags)); 2049 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2050 "nexttd=0x%08lx be=0x%08lx\n", 2051 std, (u_long)std->physaddr, sbuf, 2052 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2053 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2054 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2055 (u_long)O32TOH(std->td.td_cbp), 2056 (u_long)O32TOH(std->td.td_nexttd), 2057 (u_long)O32TOH(std->td.td_be)); 2058 } 2059 2060 void 2061 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2062 { 2063 int i; 2064 2065 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2066 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2067 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2068 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2069 sitd, (u_long)sitd->physaddr, 2070 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2071 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2072 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2073 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2074 (u_long)O32TOH(sitd->itd.itd_bp0), 2075 (u_long)O32TOH(sitd->itd.itd_nextitd), 2076 (u_long)O32TOH(sitd->itd.itd_be)); 2077 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2078 printf("offs[%d]=0x%04x ", i, 2079 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2080 printf("\n"); 2081 } 2082 2083 void 2084 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2085 { 2086 for (; sitd; sitd = sitd->nextitd) 2087 ohci_dump_itd(sc, sitd); 2088 } 2089 2090 void 2091 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2092 { 2093 char sbuf[128], sbuf2[128]; 2094 2095 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2097 snprintb(sbuf, sizeof(sbuf), 2098 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2099 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2100 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2101 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2102 2103 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2104 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2105 sed, (u_long)sed->physaddr, 2106 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2107 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2108 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2109 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2110 (u_long)O32TOH(sed->ed.ed_headp), 2111 (u_long)O32TOH(sed->ed.ed_nexted)); 2112 } 2113 #endif 2114 2115 usbd_status 2116 ohci_open(usbd_pipe_handle pipe) 2117 { 2118 usbd_device_handle dev = pipe->device; 2119 ohci_softc_t *sc = dev->bus->hci_private; 2120 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2121 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2122 u_int8_t addr = dev->address; 2123 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2124 ohci_soft_ed_t *sed; 2125 ohci_soft_td_t *std; 2126 ohci_soft_itd_t *sitd; 2127 ohci_physaddr_t tdphys; 2128 u_int32_t fmt; 2129 usbd_status err = USBD_NOMEM; 2130 int ival; 2131 2132 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2133 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2134 2135 if (sc->sc_dying) { 2136 err = USBD_IOERROR; 2137 goto bad0; 2138 } 2139 2140 std = NULL; 2141 sed = NULL; 2142 2143 if (addr == sc->sc_addr) { 2144 switch (ed->bEndpointAddress) { 2145 case USB_CONTROL_ENDPOINT: 2146 pipe->methods = &ohci_root_ctrl_methods; 2147 break; 2148 case UE_DIR_IN | OHCI_INTR_ENDPT: 2149 pipe->methods = &ohci_root_intr_methods; 2150 break; 2151 default: 2152 err = USBD_INVAL; 2153 goto bad0; 2154 } 2155 } else { 2156 sed = ohci_alloc_sed(sc); 2157 if (sed == NULL) 2158 goto bad0; 2159 opipe->sed = sed; 2160 if (xfertype == UE_ISOCHRONOUS) { 2161 mutex_enter(&sc->sc_lock); 2162 sitd = ohci_alloc_sitd(sc); 2163 mutex_exit(&sc->sc_lock); 2164 if (sitd == NULL) 2165 goto bad1; 2166 opipe->tail.itd = sitd; 2167 tdphys = sitd->physaddr; 2168 fmt = OHCI_ED_FORMAT_ISO; 2169 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2170 fmt |= OHCI_ED_DIR_IN; 2171 else 2172 fmt |= OHCI_ED_DIR_OUT; 2173 } else { 2174 mutex_enter(&sc->sc_lock); 2175 std = ohci_alloc_std(sc); 2176 mutex_exit(&sc->sc_lock); 2177 if (std == NULL) 2178 goto bad1; 2179 opipe->tail.td = std; 2180 tdphys = std->physaddr; 2181 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2182 } 2183 sed->ed.ed_flags = HTOO32( 2184 OHCI_ED_SET_FA(addr) | 2185 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2186 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2187 fmt | 2188 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2189 sed->ed.ed_headp = HTOO32(tdphys | 2190 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2191 sed->ed.ed_tailp = HTOO32(tdphys); 2192 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2194 2195 switch (xfertype) { 2196 case UE_CONTROL: 2197 pipe->methods = &ohci_device_ctrl_methods; 2198 err = usb_allocmem(&sc->sc_bus, 2199 sizeof(usb_device_request_t), 2200 0, &opipe->u.ctl.reqdma); 2201 if (err) 2202 goto bad; 2203 mutex_enter(&sc->sc_lock); 2204 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2205 mutex_exit(&sc->sc_lock); 2206 break; 2207 case UE_INTERRUPT: 2208 pipe->methods = &ohci_device_intr_methods; 2209 ival = pipe->interval; 2210 if (ival == USBD_DEFAULT_INTERVAL) 2211 ival = ed->bInterval; 2212 err = ohci_device_setintr(sc, opipe, ival); 2213 if (err) 2214 goto bad; 2215 break; 2216 case UE_ISOCHRONOUS: 2217 pipe->methods = &ohci_device_isoc_methods; 2218 return (ohci_setup_isoc(pipe)); 2219 case UE_BULK: 2220 pipe->methods = &ohci_device_bulk_methods; 2221 mutex_enter(&sc->sc_lock); 2222 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2223 mutex_exit(&sc->sc_lock); 2224 break; 2225 } 2226 } 2227 2228 return USBD_NORMAL_COMPLETION; 2229 2230 bad: 2231 if (std != NULL) 2232 ohci_free_std(sc, std); 2233 bad1: 2234 if (sed != NULL) 2235 ohci_free_sed(sc, sed); 2236 bad0: 2237 return err; 2238 2239 } 2240 2241 /* 2242 * Close a reqular pipe. 2243 * Assumes that there are no pending transactions. 2244 */ 2245 void 2246 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2247 { 2248 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2249 ohci_softc_t *sc = pipe->device->bus->hci_private; 2250 ohci_soft_ed_t *sed = opipe->sed; 2251 2252 KASSERT(mutex_owned(&sc->sc_lock)); 2253 2254 #ifdef DIAGNOSTIC 2255 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2256 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2257 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2258 ohci_soft_td_t *std; 2259 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2260 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2261 "tl=0x%x pipe=%p, std=%p\n", sed, 2262 (int)O32TOH(sed->ed.ed_headp), 2263 (int)O32TOH(sed->ed.ed_tailp), 2264 pipe, std); 2265 #ifdef OHCI_DEBUG 2266 usbd_dump_pipe(&opipe->pipe); 2267 ohci_dump_ed(sc, sed); 2268 if (std) 2269 ohci_dump_td(sc, std); 2270 #endif 2271 usb_delay_ms(&sc->sc_bus, 2); 2272 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2273 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2274 printf("ohci_close_pipe: pipe still not empty\n"); 2275 } 2276 #endif 2277 ohci_rem_ed(sc, sed, head); 2278 /* Make sure the host controller is not touching this ED */ 2279 usb_delay_ms(&sc->sc_bus, 1); 2280 pipe->endpoint->datatoggle = 2281 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2282 ohci_free_sed(sc, opipe->sed); 2283 } 2284 2285 /* 2286 * Abort a device request. 2287 * If this routine is called at splusb() it guarantees that the request 2288 * will be removed from the hardware scheduling and that the callback 2289 * for it will be called with USBD_CANCELLED status. 2290 * It's impossible to guarantee that the requested transfer will not 2291 * have happened since the hardware runs concurrently. 2292 * If the transaction has already happened we rely on the ordinary 2293 * interrupt processing to process it. 2294 * XXX This is most probably wrong. 2295 * XXXMRG this doesn't make sense anymore. 2296 */ 2297 void 2298 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2299 { 2300 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2301 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2302 ohci_soft_ed_t *sed = opipe->sed; 2303 ohci_soft_td_t *p, *n; 2304 ohci_physaddr_t headp; 2305 int hit; 2306 int wake; 2307 2308 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2309 2310 KASSERT(mutex_owned(&sc->sc_lock)); 2311 2312 if (sc->sc_dying) { 2313 /* If we're dying, just do the software part. */ 2314 xfer->status = status; /* make software ignore it */ 2315 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2316 usb_transfer_complete(xfer); 2317 return; 2318 } 2319 2320 if (cpu_intr_p() || cpu_softintr_p()) 2321 panic("ohci_abort_xfer: not in process context"); 2322 2323 /* 2324 * If an abort is already in progress then just wait for it to 2325 * complete and return. 2326 */ 2327 if (xfer->hcflags & UXFER_ABORTING) { 2328 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2329 #ifdef DIAGNOSTIC 2330 if (status == USBD_TIMEOUT) 2331 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2332 #endif 2333 /* Override the status which might be USBD_TIMEOUT. */ 2334 xfer->status = status; 2335 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2336 xfer->hcflags |= UXFER_ABORTWAIT; 2337 while (xfer->hcflags & UXFER_ABORTING) 2338 cv_wait(&xfer->hccv, &sc->sc_lock); 2339 goto done; 2340 return; 2341 } 2342 xfer->hcflags |= UXFER_ABORTING; 2343 2344 /* 2345 * Step 1: Make interrupt routine and hardware ignore xfer. 2346 */ 2347 xfer->status = status; /* make software ignore it */ 2348 callout_stop(&xfer->timeout_handle); 2349 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2350 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2351 sizeof(sed->ed.ed_flags), 2352 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2353 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2357 2358 /* 2359 * Step 2: Wait until we know hardware has finished any possible 2360 * use of the xfer. Also make sure the soft interrupt routine 2361 * has run. 2362 */ 2363 /* Hardware finishes in 1ms */ 2364 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2365 sc->sc_softwake = 1; 2366 usb_schedsoftintr(&sc->sc_bus); 2367 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2368 2369 /* 2370 * Step 3: Remove any vestiges of the xfer from the hardware. 2371 * The complication here is that the hardware may have executed 2372 * beyond the xfer we're trying to abort. So as we're scanning 2373 * the TDs of this xfer we check if the hardware points to 2374 * any of them. 2375 */ 2376 p = xfer->hcpriv; 2377 #ifdef DIAGNOSTIC 2378 if (p == NULL) { 2379 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2380 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2381 goto done; 2382 } 2383 #endif 2384 #ifdef OHCI_DEBUG 2385 if (ohcidebug > 1) { 2386 DPRINTF(("ohci_abort_xfer: sed=\n")); 2387 ohci_dump_ed(sc, sed); 2388 ohci_dump_tds(sc, p); 2389 } 2390 #endif 2391 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2392 hit = 0; 2393 for (; p->xfer == xfer; p = n) { 2394 hit |= headp == p->physaddr; 2395 n = p->nexttd; 2396 ohci_free_std(sc, p); 2397 } 2398 /* Zap headp register if hardware pointed inside the xfer. */ 2399 if (hit) { 2400 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2401 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2402 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2403 usb_syncmem(&sed->dma, 2404 sed->offs + offsetof(ohci_ed_t, ed_headp), 2405 sizeof(sed->ed.ed_headp), 2406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2407 } else { 2408 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2409 } 2410 2411 /* 2412 * Step 4: Turn on hardware again. 2413 */ 2414 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2415 sizeof(sed->ed.ed_flags), 2416 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2417 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2418 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2419 sizeof(sed->ed.ed_flags), 2420 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2421 2422 /* 2423 * Step 5: Execute callback. 2424 */ 2425 wake = xfer->hcflags & UXFER_ABORTWAIT; 2426 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2427 usb_transfer_complete(xfer); 2428 if (wake) 2429 cv_broadcast(&xfer->hccv); 2430 2431 done: 2432 KASSERT(mutex_owned(&sc->sc_lock)); 2433 } 2434 2435 /* 2436 * Data structures and routines to emulate the root hub. 2437 */ 2438 Static usb_device_descriptor_t ohci_devd = { 2439 USB_DEVICE_DESCRIPTOR_SIZE, 2440 UDESC_DEVICE, /* type */ 2441 {0x00, 0x01}, /* USB version */ 2442 UDCLASS_HUB, /* class */ 2443 UDSUBCLASS_HUB, /* subclass */ 2444 UDPROTO_FSHUB, /* protocol */ 2445 64, /* max packet */ 2446 {0},{0},{0x00,0x01}, /* device id */ 2447 1,2,0, /* string indicies */ 2448 1 /* # of configurations */ 2449 }; 2450 2451 Static const usb_config_descriptor_t ohci_confd = { 2452 USB_CONFIG_DESCRIPTOR_SIZE, 2453 UDESC_CONFIG, 2454 {USB_CONFIG_DESCRIPTOR_SIZE + 2455 USB_INTERFACE_DESCRIPTOR_SIZE + 2456 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2457 1, 2458 1, 2459 0, 2460 UC_ATTR_MBO | UC_SELF_POWERED, 2461 0 /* max power */ 2462 }; 2463 2464 Static const usb_interface_descriptor_t ohci_ifcd = { 2465 USB_INTERFACE_DESCRIPTOR_SIZE, 2466 UDESC_INTERFACE, 2467 0, 2468 0, 2469 1, 2470 UICLASS_HUB, 2471 UISUBCLASS_HUB, 2472 UIPROTO_FSHUB, 2473 0 2474 }; 2475 2476 Static const usb_endpoint_descriptor_t ohci_endpd = { 2477 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2478 .bDescriptorType = UDESC_ENDPOINT, 2479 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2480 .bmAttributes = UE_INTERRUPT, 2481 .wMaxPacketSize = {8, 0}, /* max packet */ 2482 .bInterval = 255, 2483 }; 2484 2485 Static const usb_hub_descriptor_t ohci_hubd = { 2486 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2487 .bDescriptorType = UDESC_HUB, 2488 }; 2489 2490 /* 2491 * Simulate a hardware hub by handling all the necessary requests. 2492 */ 2493 Static usbd_status 2494 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2495 { 2496 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2497 usbd_status err; 2498 2499 /* Insert last in queue. */ 2500 mutex_enter(&sc->sc_lock); 2501 err = usb_insert_transfer(xfer); 2502 mutex_exit(&sc->sc_lock); 2503 if (err) 2504 return (err); 2505 2506 /* Pipe isn't running, start first */ 2507 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2508 } 2509 2510 Static usbd_status 2511 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2512 { 2513 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2514 usb_device_request_t *req; 2515 void *buf = NULL; 2516 int port, i; 2517 int len, value, index, l, totlen = 0; 2518 usb_port_status_t ps; 2519 usb_hub_descriptor_t hubd; 2520 usbd_status err; 2521 u_int32_t v; 2522 2523 if (sc->sc_dying) 2524 return (USBD_IOERROR); 2525 2526 #ifdef DIAGNOSTIC 2527 if (!(xfer->rqflags & URQ_REQUEST)) 2528 /* XXX panic */ 2529 return (USBD_INVAL); 2530 #endif 2531 req = &xfer->request; 2532 2533 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2534 req->bmRequestType, req->bRequest)); 2535 2536 len = UGETW(req->wLength); 2537 value = UGETW(req->wValue); 2538 index = UGETW(req->wIndex); 2539 2540 if (len != 0) 2541 buf = KERNADDR(&xfer->dmabuf, 0); 2542 2543 #define C(x,y) ((x) | ((y) << 8)) 2544 switch(C(req->bRequest, req->bmRequestType)) { 2545 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2546 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2547 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2548 /* 2549 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2550 * for the integrated root hub. 2551 */ 2552 break; 2553 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2554 if (len > 0) { 2555 *(u_int8_t *)buf = sc->sc_conf; 2556 totlen = 1; 2557 } 2558 break; 2559 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2560 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2561 if (len == 0) 2562 break; 2563 switch(value >> 8) { 2564 case UDESC_DEVICE: 2565 if ((value & 0xff) != 0) { 2566 err = USBD_IOERROR; 2567 goto ret; 2568 } 2569 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2570 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2571 memcpy(buf, &ohci_devd, l); 2572 break; 2573 case UDESC_CONFIG: 2574 if ((value & 0xff) != 0) { 2575 err = USBD_IOERROR; 2576 goto ret; 2577 } 2578 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2579 memcpy(buf, &ohci_confd, l); 2580 buf = (char *)buf + l; 2581 len -= l; 2582 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2583 totlen += l; 2584 memcpy(buf, &ohci_ifcd, l); 2585 buf = (char *)buf + l; 2586 len -= l; 2587 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2588 totlen += l; 2589 memcpy(buf, &ohci_endpd, l); 2590 break; 2591 case UDESC_STRING: 2592 #define sd ((usb_string_descriptor_t *)buf) 2593 switch (value & 0xff) { 2594 case 0: /* Language table */ 2595 totlen = usb_makelangtbl(sd, len); 2596 break; 2597 case 1: /* Vendor */ 2598 totlen = usb_makestrdesc(sd, len, 2599 sc->sc_vendor); 2600 break; 2601 case 2: /* Product */ 2602 totlen = usb_makestrdesc(sd, len, 2603 "OHCI root hub"); 2604 break; 2605 } 2606 #undef sd 2607 break; 2608 default: 2609 err = USBD_IOERROR; 2610 goto ret; 2611 } 2612 break; 2613 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2614 if (len > 0) { 2615 *(u_int8_t *)buf = 0; 2616 totlen = 1; 2617 } 2618 break; 2619 case C(UR_GET_STATUS, UT_READ_DEVICE): 2620 if (len > 1) { 2621 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2622 totlen = 2; 2623 } 2624 break; 2625 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2626 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2627 if (len > 1) { 2628 USETW(((usb_status_t *)buf)->wStatus, 0); 2629 totlen = 2; 2630 } 2631 break; 2632 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2633 if (value >= USB_MAX_DEVICES) { 2634 err = USBD_IOERROR; 2635 goto ret; 2636 } 2637 sc->sc_addr = value; 2638 break; 2639 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2640 if (value != 0 && value != 1) { 2641 err = USBD_IOERROR; 2642 goto ret; 2643 } 2644 sc->sc_conf = value; 2645 break; 2646 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2647 break; 2648 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2649 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2650 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2651 err = USBD_IOERROR; 2652 goto ret; 2653 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2654 break; 2655 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2656 break; 2657 /* Hub requests */ 2658 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2659 break; 2660 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2661 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2662 "port=%d feature=%d\n", 2663 index, value)); 2664 if (index < 1 || index > sc->sc_noport) { 2665 err = USBD_IOERROR; 2666 goto ret; 2667 } 2668 port = OHCI_RH_PORT_STATUS(index); 2669 switch(value) { 2670 case UHF_PORT_ENABLE: 2671 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2672 break; 2673 case UHF_PORT_SUSPEND: 2674 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2675 break; 2676 case UHF_PORT_POWER: 2677 /* Yes, writing to the LOW_SPEED bit clears power. */ 2678 OWRITE4(sc, port, UPS_LOW_SPEED); 2679 break; 2680 case UHF_C_PORT_CONNECTION: 2681 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2682 break; 2683 case UHF_C_PORT_ENABLE: 2684 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2685 break; 2686 case UHF_C_PORT_SUSPEND: 2687 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2688 break; 2689 case UHF_C_PORT_OVER_CURRENT: 2690 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2691 break; 2692 case UHF_C_PORT_RESET: 2693 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2694 break; 2695 default: 2696 err = USBD_IOERROR; 2697 goto ret; 2698 } 2699 switch(value) { 2700 case UHF_C_PORT_CONNECTION: 2701 case UHF_C_PORT_ENABLE: 2702 case UHF_C_PORT_SUSPEND: 2703 case UHF_C_PORT_OVER_CURRENT: 2704 case UHF_C_PORT_RESET: 2705 /* Enable RHSC interrupt if condition is cleared. */ 2706 if ((OREAD4(sc, port) >> 16) == 0) 2707 ohci_rhsc_enable(sc); 2708 break; 2709 default: 2710 break; 2711 } 2712 break; 2713 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2714 if (len == 0) 2715 break; 2716 if ((value & 0xff) != 0) { 2717 err = USBD_IOERROR; 2718 goto ret; 2719 } 2720 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2721 hubd = ohci_hubd; 2722 hubd.bNbrPorts = sc->sc_noport; 2723 USETW(hubd.wHubCharacteristics, 2724 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2725 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2726 /* XXX overcurrent */ 2727 ); 2728 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2729 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2730 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2731 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2732 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2733 l = min(len, hubd.bDescLength); 2734 totlen = l; 2735 memcpy(buf, &hubd, l); 2736 break; 2737 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2738 if (len != 4) { 2739 err = USBD_IOERROR; 2740 goto ret; 2741 } 2742 memset(buf, 0, len); /* ? XXX */ 2743 totlen = len; 2744 break; 2745 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2746 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2747 index)); 2748 if (index < 1 || index > sc->sc_noport) { 2749 err = USBD_IOERROR; 2750 goto ret; 2751 } 2752 if (len != 4) { 2753 err = USBD_IOERROR; 2754 goto ret; 2755 } 2756 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2757 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2758 v)); 2759 USETW(ps.wPortStatus, v); 2760 USETW(ps.wPortChange, v >> 16); 2761 l = min(len, sizeof ps); 2762 memcpy(buf, &ps, l); 2763 totlen = l; 2764 break; 2765 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2766 err = USBD_IOERROR; 2767 goto ret; 2768 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2769 break; 2770 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2771 if (index < 1 || index > sc->sc_noport) { 2772 err = USBD_IOERROR; 2773 goto ret; 2774 } 2775 port = OHCI_RH_PORT_STATUS(index); 2776 switch(value) { 2777 case UHF_PORT_ENABLE: 2778 OWRITE4(sc, port, UPS_PORT_ENABLED); 2779 break; 2780 case UHF_PORT_SUSPEND: 2781 OWRITE4(sc, port, UPS_SUSPEND); 2782 break; 2783 case UHF_PORT_RESET: 2784 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2785 index)); 2786 OWRITE4(sc, port, UPS_RESET); 2787 for (i = 0; i < 5; i++) { 2788 usb_delay_ms(&sc->sc_bus, 2789 USB_PORT_ROOT_RESET_DELAY); 2790 if (sc->sc_dying) { 2791 err = USBD_IOERROR; 2792 goto ret; 2793 } 2794 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2795 break; 2796 } 2797 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2798 index, OREAD4(sc, port))); 2799 break; 2800 case UHF_PORT_POWER: 2801 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2802 "%d\n", index)); 2803 OWRITE4(sc, port, UPS_PORT_POWER); 2804 break; 2805 default: 2806 err = USBD_IOERROR; 2807 goto ret; 2808 } 2809 break; 2810 default: 2811 err = USBD_IOERROR; 2812 goto ret; 2813 } 2814 xfer->actlen = totlen; 2815 err = USBD_NORMAL_COMPLETION; 2816 ret: 2817 xfer->status = err; 2818 mutex_enter(&sc->sc_lock); 2819 usb_transfer_complete(xfer); 2820 mutex_exit(&sc->sc_lock); 2821 return (USBD_IN_PROGRESS); 2822 } 2823 2824 /* Abort a root control request. */ 2825 Static void 2826 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2827 { 2828 /* Nothing to do, all transfers are synchronous. */ 2829 } 2830 2831 /* Close the root pipe. */ 2832 Static void 2833 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2834 { 2835 DPRINTF(("ohci_root_ctrl_close\n")); 2836 /* Nothing to do. */ 2837 } 2838 2839 Static usbd_status 2840 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2841 { 2842 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2843 usbd_status err; 2844 2845 /* Insert last in queue. */ 2846 mutex_enter(&sc->sc_lock); 2847 err = usb_insert_transfer(xfer); 2848 mutex_exit(&sc->sc_lock); 2849 if (err) 2850 return (err); 2851 2852 /* Pipe isn't running, start first */ 2853 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2854 } 2855 2856 Static usbd_status 2857 ohci_root_intr_start(usbd_xfer_handle xfer) 2858 { 2859 usbd_pipe_handle pipe = xfer->pipe; 2860 ohci_softc_t *sc = pipe->device->bus->hci_private; 2861 2862 if (sc->sc_dying) 2863 return (USBD_IOERROR); 2864 2865 mutex_enter(&sc->sc_lock); 2866 KASSERT(sc->sc_intrxfer == NULL); 2867 sc->sc_intrxfer = xfer; 2868 mutex_exit(&sc->sc_lock); 2869 2870 return (USBD_IN_PROGRESS); 2871 } 2872 2873 /* Abort a root interrupt request. */ 2874 Static void 2875 ohci_root_intr_abort(usbd_xfer_handle xfer) 2876 { 2877 #ifdef DIAGNOSTIC 2878 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2879 #endif 2880 2881 KASSERT(mutex_owned(&sc->sc_lock)); 2882 2883 if (xfer->pipe->intrxfer == xfer) { 2884 DPRINTF(("ohci_root_intr_abort: remove\n")); 2885 xfer->pipe->intrxfer = NULL; 2886 } 2887 xfer->status = USBD_CANCELLED; 2888 usb_transfer_complete(xfer); 2889 } 2890 2891 /* Close the root pipe. */ 2892 Static void 2893 ohci_root_intr_close(usbd_pipe_handle pipe) 2894 { 2895 ohci_softc_t *sc = pipe->device->bus->hci_private; 2896 2897 KASSERT(mutex_owned(&sc->sc_lock)); 2898 2899 DPRINTF(("ohci_root_intr_close\n")); 2900 2901 sc->sc_intrxfer = NULL; 2902 } 2903 2904 /************************/ 2905 2906 Static usbd_status 2907 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2908 { 2909 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2910 usbd_status err; 2911 2912 /* Insert last in queue. */ 2913 mutex_enter(&sc->sc_lock); 2914 err = usb_insert_transfer(xfer); 2915 mutex_exit(&sc->sc_lock); 2916 if (err) 2917 return (err); 2918 2919 /* Pipe isn't running, start first */ 2920 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2921 } 2922 2923 Static usbd_status 2924 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2925 { 2926 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2927 usbd_status err; 2928 2929 if (sc->sc_dying) 2930 return (USBD_IOERROR); 2931 2932 #ifdef DIAGNOSTIC 2933 if (!(xfer->rqflags & URQ_REQUEST)) { 2934 /* XXX panic */ 2935 printf("ohci_device_ctrl_transfer: not a request\n"); 2936 return (USBD_INVAL); 2937 } 2938 #endif 2939 2940 mutex_enter(&sc->sc_lock); 2941 err = ohci_device_request(xfer); 2942 mutex_exit(&sc->sc_lock); 2943 if (err) 2944 return (err); 2945 2946 if (sc->sc_bus.use_polling) 2947 ohci_waitintr(sc, xfer); 2948 return (USBD_IN_PROGRESS); 2949 } 2950 2951 /* Abort a device control request. */ 2952 Static void 2953 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2954 { 2955 #ifdef DIAGNOSTIC 2956 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2957 #endif 2958 2959 KASSERT(mutex_owned(&sc->sc_lock)); 2960 2961 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2962 ohci_abort_xfer(xfer, USBD_CANCELLED); 2963 } 2964 2965 /* Close a device control pipe. */ 2966 Static void 2967 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2968 { 2969 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2970 ohci_softc_t *sc = pipe->device->bus->hci_private; 2971 2972 KASSERT(mutex_owned(&sc->sc_lock)); 2973 2974 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2975 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2976 ohci_free_std(sc, opipe->tail.td); 2977 } 2978 2979 /************************/ 2980 2981 Static void 2982 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2983 { 2984 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2985 ohci_softc_t *sc = pipe->device->bus->hci_private; 2986 2987 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2988 } 2989 2990 Static void 2991 ohci_noop(usbd_pipe_handle pipe) 2992 { 2993 } 2994 2995 Static usbd_status 2996 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2997 { 2998 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2999 usbd_status err; 3000 3001 /* Insert last in queue. */ 3002 mutex_enter(&sc->sc_lock); 3003 err = usb_insert_transfer(xfer); 3004 mutex_exit(&sc->sc_lock); 3005 if (err) 3006 return (err); 3007 3008 /* Pipe isn't running, start first */ 3009 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3010 } 3011 3012 Static usbd_status 3013 ohci_device_bulk_start(usbd_xfer_handle xfer) 3014 { 3015 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3016 usbd_device_handle dev = opipe->pipe.device; 3017 ohci_softc_t *sc = dev->bus->hci_private; 3018 int addr = dev->address; 3019 ohci_soft_td_t *data, *tail, *tdp; 3020 ohci_soft_ed_t *sed; 3021 int len, isread, endpt; 3022 usbd_status err; 3023 3024 if (sc->sc_dying) 3025 return (USBD_IOERROR); 3026 3027 #ifdef DIAGNOSTIC 3028 if (xfer->rqflags & URQ_REQUEST) { 3029 /* XXX panic */ 3030 printf("ohci_device_bulk_start: a request\n"); 3031 return (USBD_INVAL); 3032 } 3033 #endif 3034 3035 mutex_enter(&sc->sc_lock); 3036 3037 len = xfer->length; 3038 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3039 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3040 sed = opipe->sed; 3041 3042 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3043 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3044 endpt)); 3045 3046 opipe->u.bulk.isread = isread; 3047 opipe->u.bulk.length = len; 3048 3049 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3050 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3051 /* Update device address */ 3052 sed->ed.ed_flags = HTOO32( 3053 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3054 OHCI_ED_SET_FA(addr)); 3055 3056 /* Allocate a chain of new TDs (including a new tail). */ 3057 data = opipe->tail.td; 3058 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3059 data, &tail); 3060 /* We want interrupt at the end of the transfer. */ 3061 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3062 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3063 tail->flags |= OHCI_CALL_DONE; 3064 tail = tail->nexttd; /* point at sentinel */ 3065 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3066 sizeof(tail->td.td_flags), 3067 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3068 if (err) { 3069 mutex_exit(&sc->sc_lock); 3070 return (err); 3071 } 3072 3073 tail->xfer = NULL; 3074 xfer->hcpriv = data; 3075 3076 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3077 "td_cbp=0x%08x td_be=0x%08x\n", 3078 (int)O32TOH(sed->ed.ed_flags), 3079 (int)O32TOH(data->td.td_flags), 3080 (int)O32TOH(data->td.td_cbp), 3081 (int)O32TOH(data->td.td_be))); 3082 3083 #ifdef OHCI_DEBUG 3084 if (ohcidebug > 5) { 3085 ohci_dump_ed(sc, sed); 3086 ohci_dump_tds(sc, data); 3087 } 3088 #endif 3089 3090 /* Insert ED in schedule */ 3091 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3092 tdp->xfer = xfer; 3093 } 3094 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3095 opipe->tail.td = tail; 3096 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3097 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3098 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3099 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3100 if (xfer->timeout && !sc->sc_bus.use_polling) { 3101 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3102 ohci_timeout, xfer); 3103 } 3104 mutex_exit(&sc->sc_lock); 3105 3106 #if 0 3107 /* This goes wrong if we are too slow. */ 3108 if (ohcidebug > 10) { 3109 delay(10000); 3110 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3111 OREAD4(sc, OHCI_COMMAND_STATUS))); 3112 ohci_dump_ed(sc, sed); 3113 ohci_dump_tds(sc, data); 3114 } 3115 #endif 3116 3117 return (USBD_IN_PROGRESS); 3118 } 3119 3120 Static void 3121 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3122 { 3123 #ifdef DIAGNOSTIC 3124 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3125 #endif 3126 3127 KASSERT(mutex_owned(&sc->sc_lock)); 3128 3129 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3130 ohci_abort_xfer(xfer, USBD_CANCELLED); 3131 } 3132 3133 /* 3134 * Close a device bulk pipe. 3135 */ 3136 Static void 3137 ohci_device_bulk_close(usbd_pipe_handle pipe) 3138 { 3139 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3140 ohci_softc_t *sc = pipe->device->bus->hci_private; 3141 3142 KASSERT(mutex_owned(&sc->sc_lock)); 3143 3144 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3145 ohci_close_pipe(pipe, sc->sc_bulk_head); 3146 ohci_free_std(sc, opipe->tail.td); 3147 } 3148 3149 /************************/ 3150 3151 Static usbd_status 3152 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3153 { 3154 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3155 usbd_status err; 3156 3157 /* Insert last in queue. */ 3158 mutex_enter(&sc->sc_lock); 3159 err = usb_insert_transfer(xfer); 3160 mutex_exit(&sc->sc_lock); 3161 if (err) 3162 return (err); 3163 3164 /* Pipe isn't running, start first */ 3165 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3166 } 3167 3168 Static usbd_status 3169 ohci_device_intr_start(usbd_xfer_handle xfer) 3170 { 3171 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3172 usbd_device_handle dev = opipe->pipe.device; 3173 ohci_softc_t *sc = dev->bus->hci_private; 3174 ohci_soft_ed_t *sed = opipe->sed; 3175 ohci_soft_td_t *data, *tail; 3176 int len, isread, endpt; 3177 3178 if (sc->sc_dying) 3179 return (USBD_IOERROR); 3180 3181 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3182 "flags=%d priv=%p\n", 3183 xfer, xfer->length, xfer->flags, xfer->priv)); 3184 3185 #ifdef DIAGNOSTIC 3186 if (xfer->rqflags & URQ_REQUEST) 3187 panic("ohci_device_intr_transfer: a request"); 3188 #endif 3189 3190 len = xfer->length; 3191 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3192 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3193 3194 data = opipe->tail.td; 3195 mutex_enter(&sc->sc_lock); 3196 tail = ohci_alloc_std(sc); 3197 mutex_exit(&sc->sc_lock); 3198 if (tail == NULL) 3199 return (USBD_NOMEM); 3200 tail->xfer = NULL; 3201 3202 data->td.td_flags = HTOO32( 3203 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3204 OHCI_TD_NOCC | 3205 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3206 if (xfer->flags & USBD_SHORT_XFER_OK) 3207 data->td.td_flags |= HTOO32(OHCI_TD_R); 3208 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3209 data->nexttd = tail; 3210 data->td.td_nexttd = HTOO32(tail->physaddr); 3211 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3212 data->len = len; 3213 data->xfer = xfer; 3214 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3215 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3216 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3217 xfer->hcpriv = data; 3218 3219 #ifdef OHCI_DEBUG 3220 if (ohcidebug > 5) { 3221 DPRINTF(("ohci_device_intr_transfer:\n")); 3222 ohci_dump_ed(sc, sed); 3223 ohci_dump_tds(sc, data); 3224 } 3225 #endif 3226 3227 /* Insert ED in schedule */ 3228 mutex_enter(&sc->sc_lock); 3229 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3230 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3231 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3232 opipe->tail.td = tail; 3233 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3234 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3236 3237 #if 0 3238 /* 3239 * This goes horribly wrong, printing thousands of descriptors, 3240 * because false references are followed due to the fact that the 3241 * TD is gone. 3242 */ 3243 if (ohcidebug > 5) { 3244 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3245 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3246 OREAD4(sc, OHCI_COMMAND_STATUS))); 3247 ohci_dump_ed(sc, sed); 3248 ohci_dump_tds(sc, data); 3249 } 3250 #endif 3251 mutex_exit(&sc->sc_lock); 3252 3253 return (USBD_IN_PROGRESS); 3254 } 3255 3256 /* Abort a device interrupt request. */ 3257 Static void 3258 ohci_device_intr_abort(usbd_xfer_handle xfer) 3259 { 3260 #ifdef DIAGNOSTIC 3261 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3262 #endif 3263 3264 KASSERT(mutex_owned(&sc->sc_lock)); 3265 3266 if (xfer->pipe->intrxfer == xfer) { 3267 DPRINTF(("ohci_device_intr_abort: remove\n")); 3268 xfer->pipe->intrxfer = NULL; 3269 } 3270 ohci_abort_xfer(xfer, USBD_CANCELLED); 3271 } 3272 3273 /* Close a device interrupt pipe. */ 3274 Static void 3275 ohci_device_intr_close(usbd_pipe_handle pipe) 3276 { 3277 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3278 ohci_softc_t *sc = pipe->device->bus->hci_private; 3279 int nslots = opipe->u.intr.nslots; 3280 int pos = opipe->u.intr.pos; 3281 int j; 3282 ohci_soft_ed_t *p, *sed = opipe->sed; 3283 3284 KASSERT(mutex_owned(&sc->sc_lock)); 3285 3286 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3287 pipe, nslots, pos)); 3288 usb_syncmem(&sed->dma, sed->offs, 3289 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3290 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3291 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3292 sizeof(sed->ed.ed_flags), 3293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3294 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3295 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3296 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3297 3298 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3299 continue; 3300 #ifdef DIAGNOSTIC 3301 if (p == NULL) 3302 panic("ohci_device_intr_close: ED not found"); 3303 #endif 3304 p->next = sed->next; 3305 p->ed.ed_nexted = sed->ed.ed_nexted; 3306 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3307 sizeof(p->ed.ed_nexted), 3308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3309 3310 for (j = 0; j < nslots; j++) 3311 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3312 3313 ohci_free_std(sc, opipe->tail.td); 3314 ohci_free_sed(sc, opipe->sed); 3315 } 3316 3317 Static usbd_status 3318 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3319 { 3320 int i, j, best; 3321 u_int npoll, slow, shigh, nslots; 3322 u_int bestbw, bw; 3323 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3324 3325 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3326 if (ival == 0) { 3327 printf("ohci_setintr: 0 interval\n"); 3328 return (USBD_INVAL); 3329 } 3330 3331 npoll = OHCI_NO_INTRS; 3332 while (npoll > ival) 3333 npoll /= 2; 3334 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3335 3336 /* 3337 * We now know which level in the tree the ED must go into. 3338 * Figure out which slot has most bandwidth left over. 3339 * Slots to examine: 3340 * npoll 3341 * 1 0 3342 * 2 1 2 3343 * 4 3 4 5 6 3344 * 8 7 8 9 10 11 12 13 14 3345 * N (N-1) .. (N-1+N-1) 3346 */ 3347 slow = npoll-1; 3348 shigh = slow + npoll; 3349 nslots = OHCI_NO_INTRS / npoll; 3350 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3351 bw = 0; 3352 for (j = 0; j < nslots; j++) 3353 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3354 if (bw < bestbw) { 3355 best = i; 3356 bestbw = bw; 3357 } 3358 } 3359 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3360 best, slow, shigh, bestbw)); 3361 3362 mutex_enter(&sc->sc_lock); 3363 hsed = sc->sc_eds[best]; 3364 sed->next = hsed->next; 3365 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3366 sizeof(hsed->ed.ed_flags), 3367 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3368 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3369 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3370 sizeof(sed->ed.ed_flags), 3371 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3372 hsed->next = sed; 3373 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3374 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3375 sizeof(hsed->ed.ed_flags), 3376 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3377 mutex_exit(&sc->sc_lock); 3378 3379 for (j = 0; j < nslots; j++) 3380 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3381 opipe->u.intr.nslots = nslots; 3382 opipe->u.intr.pos = best; 3383 3384 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3385 return (USBD_NORMAL_COMPLETION); 3386 } 3387 3388 /***********************/ 3389 3390 usbd_status 3391 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3392 { 3393 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3394 usbd_status err; 3395 3396 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3397 3398 /* Put it on our queue, */ 3399 mutex_enter(&sc->sc_lock); 3400 err = usb_insert_transfer(xfer); 3401 mutex_exit(&sc->sc_lock); 3402 3403 /* bail out on error, */ 3404 if (err && err != USBD_IN_PROGRESS) 3405 return (err); 3406 3407 /* XXX should check inuse here */ 3408 3409 /* insert into schedule, */ 3410 ohci_device_isoc_enter(xfer); 3411 3412 /* and start if the pipe wasn't running */ 3413 if (!err) 3414 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3415 3416 return (err); 3417 } 3418 3419 void 3420 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3421 { 3422 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3423 usbd_device_handle dev = opipe->pipe.device; 3424 ohci_softc_t *sc = dev->bus->hci_private; 3425 ohci_soft_ed_t *sed = opipe->sed; 3426 struct iso *iso = &opipe->u.iso; 3427 ohci_soft_itd_t *sitd, *nsitd; 3428 ohci_physaddr_t buf, offs, noffs, bp0; 3429 int i, ncur, nframes; 3430 3431 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3432 "nframes=%d\n", 3433 iso->inuse, iso->next, xfer, xfer->nframes)); 3434 3435 if (sc->sc_dying) 3436 return; 3437 3438 if (iso->next == -1) { 3439 /* Not in use yet, schedule it a few frames ahead. */ 3440 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3441 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3442 iso->next)); 3443 } 3444 3445 sitd = opipe->tail.itd; 3446 buf = DMAADDR(&xfer->dmabuf, 0); 3447 bp0 = OHCI_PAGE(buf); 3448 offs = OHCI_PAGE_OFFSET(buf); 3449 nframes = xfer->nframes; 3450 xfer->hcpriv = sitd; 3451 for (i = ncur = 0; i < nframes; i++, ncur++) { 3452 noffs = offs + xfer->frlengths[i]; 3453 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3454 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3455 3456 /* Allocate next ITD */ 3457 mutex_enter(&sc->sc_lock); 3458 nsitd = ohci_alloc_sitd(sc); 3459 mutex_exit(&sc->sc_lock); 3460 if (nsitd == NULL) { 3461 /* XXX what now? */ 3462 printf("%s: isoc TD alloc failed\n", 3463 device_xname(sc->sc_dev)); 3464 return; 3465 } 3466 3467 /* Fill current ITD */ 3468 sitd->itd.itd_flags = HTOO32( 3469 OHCI_ITD_NOCC | 3470 OHCI_ITD_SET_SF(iso->next) | 3471 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3472 OHCI_ITD_SET_FC(ncur)); 3473 sitd->itd.itd_bp0 = HTOO32(bp0); 3474 sitd->nextitd = nsitd; 3475 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3476 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3477 sitd->xfer = xfer; 3478 sitd->flags = 0; 3479 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3481 3482 sitd = nsitd; 3483 iso->next = iso->next + ncur; 3484 bp0 = OHCI_PAGE(buf + offs); 3485 ncur = 0; 3486 } 3487 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3488 offs = noffs; 3489 } 3490 mutex_enter(&sc->sc_lock); 3491 nsitd = ohci_alloc_sitd(sc); 3492 mutex_exit(&sc->sc_lock); 3493 if (nsitd == NULL) { 3494 /* XXX what now? */ 3495 printf("%s: isoc TD alloc failed\n", 3496 device_xname(sc->sc_dev)); 3497 return; 3498 } 3499 /* Fixup last used ITD */ 3500 sitd->itd.itd_flags = HTOO32( 3501 OHCI_ITD_NOCC | 3502 OHCI_ITD_SET_SF(iso->next) | 3503 OHCI_ITD_SET_DI(0) | 3504 OHCI_ITD_SET_FC(ncur)); 3505 sitd->itd.itd_bp0 = HTOO32(bp0); 3506 sitd->nextitd = nsitd; 3507 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3508 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3509 sitd->xfer = xfer; 3510 sitd->flags = OHCI_CALL_DONE; 3511 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3512 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3513 3514 iso->next = iso->next + ncur; 3515 iso->inuse += nframes; 3516 3517 xfer->actlen = offs; /* XXX pretend we did it all */ 3518 3519 xfer->status = USBD_IN_PROGRESS; 3520 3521 #ifdef OHCI_DEBUG 3522 if (ohcidebug > 5) { 3523 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3524 O32TOH(sc->sc_hcca->hcca_frame_number))); 3525 ohci_dump_itds(sc, xfer->hcpriv); 3526 ohci_dump_ed(sc, sed); 3527 } 3528 #endif 3529 3530 mutex_enter(&sc->sc_lock); 3531 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3532 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3533 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3534 opipe->tail.itd = nsitd; 3535 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3536 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3537 sizeof(sed->ed.ed_flags), 3538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3539 mutex_exit(&sc->sc_lock); 3540 3541 #ifdef OHCI_DEBUG 3542 if (ohcidebug > 5) { 3543 delay(150000); 3544 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3545 O32TOH(sc->sc_hcca->hcca_frame_number))); 3546 ohci_dump_itds(sc, xfer->hcpriv); 3547 ohci_dump_ed(sc, sed); 3548 } 3549 #endif 3550 } 3551 3552 usbd_status 3553 ohci_device_isoc_start(usbd_xfer_handle xfer) 3554 { 3555 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3556 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3557 3558 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3559 3560 mutex_enter(&sc->sc_lock); 3561 3562 if (sc->sc_dying) { 3563 mutex_exit(&sc->sc_lock); 3564 return (USBD_IOERROR); 3565 } 3566 3567 #ifdef DIAGNOSTIC 3568 if (xfer->status != USBD_IN_PROGRESS) 3569 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3570 #endif 3571 3572 /* XXX anything to do? */ 3573 3574 mutex_exit(&sc->sc_lock); 3575 3576 return (USBD_IN_PROGRESS); 3577 } 3578 3579 void 3580 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3581 { 3582 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3583 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3584 ohci_soft_ed_t *sed; 3585 ohci_soft_itd_t *sitd; 3586 3587 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3588 3589 KASSERT(mutex_owned(&sc->sc_lock)); 3590 3591 /* Transfer is already done. */ 3592 if (xfer->status != USBD_NOT_STARTED && 3593 xfer->status != USBD_IN_PROGRESS) { 3594 printf("ohci_device_isoc_abort: early return\n"); 3595 goto done; 3596 } 3597 3598 /* Give xfer the requested abort code. */ 3599 xfer->status = USBD_CANCELLED; 3600 3601 sed = opipe->sed; 3602 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3603 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3604 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3605 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3606 sizeof(sed->ed.ed_flags), 3607 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3608 3609 sitd = xfer->hcpriv; 3610 #ifdef DIAGNOSTIC 3611 if (sitd == NULL) { 3612 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3613 goto done; 3614 } 3615 #endif 3616 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3617 #ifdef DIAGNOSTIC 3618 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3619 sitd->isdone = 1; 3620 #endif 3621 } 3622 3623 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3624 3625 /* Run callback. */ 3626 usb_transfer_complete(xfer); 3627 3628 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3629 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3630 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3631 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3632 3633 done: 3634 KASSERT(mutex_owned(&sc->sc_lock)); 3635 } 3636 3637 void 3638 ohci_device_isoc_done(usbd_xfer_handle xfer) 3639 { 3640 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3641 } 3642 3643 usbd_status 3644 ohci_setup_isoc(usbd_pipe_handle pipe) 3645 { 3646 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3647 ohci_softc_t *sc = pipe->device->bus->hci_private; 3648 struct iso *iso = &opipe->u.iso; 3649 3650 iso->next = -1; 3651 iso->inuse = 0; 3652 3653 mutex_enter(&sc->sc_lock); 3654 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3655 mutex_exit(&sc->sc_lock); 3656 3657 return (USBD_NORMAL_COMPLETION); 3658 } 3659 3660 void 3661 ohci_device_isoc_close(usbd_pipe_handle pipe) 3662 { 3663 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3664 ohci_softc_t *sc = pipe->device->bus->hci_private; 3665 3666 KASSERT(mutex_owned(&sc->sc_lock)); 3667 3668 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3669 ohci_close_pipe(pipe, sc->sc_isoc_head); 3670 #ifdef DIAGNOSTIC 3671 opipe->tail.itd->isdone = 1; 3672 #endif 3673 ohci_free_sitd(sc, opipe->tail.itd); 3674 } 3675
Indexes created Fri Oct 03 02:09:57 GMT 2025