ohci.c revision 1.218.6.16
1 /* $NetBSD: ohci.c,v 1.218.6.16 2012/02/26 05:05:44 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green (mrg (at) eterna.com.au). 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.218.6.16 2012/02/26 05:05:44 mrg Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kmem.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 #include <sys/cpu.h> 58 59 #include <sys/bus.h> 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub_subr.h> 71 72 73 74 #ifdef OHCI_DEBUG 75 #define DPRINTF(x) if (ohcidebug) printf x 76 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 77 int ohcidebug = 0; 78 #else 79 #define DPRINTF(x) 80 #define DPRINTFN(n,x) 81 #endif 82 83 #if BYTE_ORDER == BIG_ENDIAN 84 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 85 #else 86 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 87 #endif 88 89 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 90 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 91 #define HTOO16(val) O16TOH(val) 92 #define HTOO32(val) O32TOH(val) 93 94 struct ohci_pipe; 95 96 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 97 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 98 99 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 100 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 101 102 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 103 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 104 105 #if 0 106 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 107 ohci_soft_td_t *); 108 #endif 109 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 110 ohci_softc_t *, int, int, usbd_xfer_handle, 111 ohci_soft_td_t *, ohci_soft_td_t **); 112 113 Static usbd_status ohci_open(usbd_pipe_handle); 114 Static void ohci_poll(struct usbd_bus *); 115 Static void ohci_softintr(void *); 116 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 117 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 118 Static void ohci_rhsc_softint(void *arg); 119 120 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 121 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 122 ohci_soft_ed_t *); 123 124 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 125 ohci_soft_ed_t *); 126 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 127 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 128 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 129 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 130 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 131 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 132 133 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 134 Static void ohci_device_isoc_enter(usbd_xfer_handle); 135 136 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 137 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 138 139 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 140 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 141 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 142 143 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 145 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 146 Static void ohci_root_ctrl_close(usbd_pipe_handle); 147 Static void ohci_root_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 151 Static void ohci_root_intr_abort(usbd_xfer_handle); 152 Static void ohci_root_intr_close(usbd_pipe_handle); 153 Static void ohci_root_intr_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 157 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 158 Static void ohci_device_ctrl_close(usbd_pipe_handle); 159 Static void ohci_device_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 163 Static void ohci_device_bulk_abort(usbd_xfer_handle); 164 Static void ohci_device_bulk_close(usbd_pipe_handle); 165 Static void ohci_device_bulk_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 169 Static void ohci_device_intr_abort(usbd_xfer_handle); 170 Static void ohci_device_intr_close(usbd_pipe_handle); 171 Static void ohci_device_intr_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 174 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 175 Static void ohci_device_isoc_abort(usbd_xfer_handle); 176 Static void ohci_device_isoc_close(usbd_pipe_handle); 177 Static void ohci_device_isoc_done(usbd_xfer_handle); 178 179 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 180 struct ohci_pipe *pipe, int ival); 181 182 Static void ohci_timeout(void *); 183 Static void ohci_timeout_task(void *); 184 Static void ohci_rhsc_enable(void *); 185 186 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 187 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 188 189 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 190 Static void ohci_noop(usbd_pipe_handle pipe); 191 192 #ifdef OHCI_DEBUG 193 Static void ohci_dumpregs(ohci_softc_t *); 194 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 195 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 196 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 197 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 198 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 199 #endif 200 201 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 202 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 203 #define OWRITE1(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 #define OWRITE2(sc, r, x) \ 206 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 207 #define OWRITE4(sc, r, x) \ 208 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 209 static __inline uint8_t 210 OREAD1(ohci_softc_t *sc, bus_size_t r) 211 { 212 213 OBARR(sc); 214 return bus_space_read_1(sc->iot, sc->ioh, r); 215 } 216 217 static __inline uint16_t 218 OREAD2(ohci_softc_t *sc, bus_size_t r) 219 { 220 221 OBARR(sc); 222 return bus_space_read_2(sc->iot, sc->ioh, r); 223 } 224 225 static __inline uint32_t 226 OREAD4(ohci_softc_t *sc, bus_size_t r) 227 { 228 229 OBARR(sc); 230 return bus_space_read_4(sc->iot, sc->ioh, r); 231 } 232 233 /* Reverse the bits in a value 0 .. 31 */ 234 Static u_int8_t revbits[OHCI_NO_INTRS] = 235 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 236 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 237 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 238 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 239 240 struct ohci_pipe { 241 struct usbd_pipe pipe; 242 ohci_soft_ed_t *sed; 243 union { 244 ohci_soft_td_t *td; 245 ohci_soft_itd_t *itd; 246 } tail; 247 /* Info needed for different pipe kinds. */ 248 union { 249 /* Control pipe */ 250 struct { 251 usb_dma_t reqdma; 252 u_int length; 253 ohci_soft_td_t *setup, *data, *stat; 254 } ctl; 255 /* Interrupt pipe */ 256 struct { 257 int nslots; 258 int pos; 259 } intr; 260 /* Bulk pipe */ 261 struct { 262 u_int length; 263 int isread; 264 } bulk; 265 /* Iso pipe */ 266 struct iso { 267 int next, inuse; 268 } iso; 269 } u; 270 }; 271 272 #define OHCI_INTR_ENDPT 1 273 274 Static const struct usbd_bus_methods ohci_bus_methods = { 275 .open_pipe = ohci_open, 276 .soft_intr = ohci_softintr, 277 .do_poll = ohci_poll, 278 .allocm = ohci_allocm, 279 .freem = ohci_freem, 280 .allocx = ohci_allocx, 281 .freex = ohci_freex, 282 .get_lock = ohci_get_lock, 283 }; 284 285 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 286 .transfer = ohci_root_ctrl_transfer, 287 .start = ohci_root_ctrl_start, 288 .abort = ohci_root_ctrl_abort, 289 .close = ohci_root_ctrl_close, 290 .cleartoggle = ohci_noop, 291 .done = ohci_root_ctrl_done, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .transfer = ohci_root_intr_transfer, 296 .start = ohci_root_intr_start, 297 .abort = ohci_root_intr_abort, 298 .close = ohci_root_intr_close, 299 .cleartoggle = ohci_noop, 300 .done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .transfer = ohci_device_ctrl_transfer, 305 .start = ohci_device_ctrl_start, 306 .abort = ohci_device_ctrl_abort, 307 .close = ohci_device_ctrl_close, 308 .cleartoggle = ohci_noop, 309 .done = ohci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 313 .transfer = ohci_device_intr_transfer, 314 .start = ohci_device_intr_start, 315 .abort = ohci_device_intr_abort, 316 .close = ohci_device_intr_close, 317 .cleartoggle = ohci_device_clear_toggle, 318 .done = ohci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 322 .transfer = ohci_device_bulk_transfer, 323 .start = ohci_device_bulk_start, 324 .abort = ohci_device_bulk_abort, 325 .close = ohci_device_bulk_close, 326 .cleartoggle = ohci_device_clear_toggle, 327 .done = ohci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 331 .transfer = ohci_device_isoc_transfer, 332 .start = ohci_device_isoc_start, 333 .abort = ohci_device_isoc_abort, 334 .close = ohci_device_isoc_close, 335 .cleartoggle = ohci_noop, 336 .done = ohci_device_isoc_done, 337 }; 338 339 int 340 ohci_activate(device_t self, enum devact act) 341 { 342 struct ohci_softc *sc = device_private(self); 343 344 switch (act) { 345 case DVACT_DEACTIVATE: 346 sc->sc_dying = 1; 347 return 0; 348 default: 349 return EOPNOTSUPP; 350 } 351 } 352 353 void 354 ohci_childdet(device_t self, device_t child) 355 { 356 struct ohci_softc *sc = device_private(self); 357 358 KASSERT(sc->sc_child == child); 359 sc->sc_child = NULL; 360 } 361 362 int 363 ohci_detach(struct ohci_softc *sc, int flags) 364 { 365 int rv = 0; 366 usbd_xfer_handle xfer; 367 368 if (sc->sc_child != NULL) 369 rv = config_detach(sc->sc_child, flags); 370 371 if (rv != 0) 372 return (rv); 373 374 callout_stop(&sc->sc_tmo_rhsc); 375 376 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 377 callout_destroy(&sc->sc_tmo_rhsc); 378 379 softint_disestablish(sc->sc_rhsc_si); 380 381 cv_destroy(&sc->sc_softwake_cv); 382 383 mutex_destroy(&sc->sc_lock); 384 mutex_destroy(&sc->sc_intr_lock); 385 386 if (sc->sc_hcca != NULL) 387 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 388 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 389 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 390 kmem_free(xfer, sizeof(struct ohci_xfer)); 391 } 392 393 return (rv); 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 if (sc->sc_freeeds == NULL) { 405 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 406 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 407 OHCI_ED_ALIGN, &dma); 408 if (err) 409 return (0); 410 for(i = 0; i < OHCI_SED_CHUNK; i++) { 411 offs = i * OHCI_SED_SIZE; 412 sed = KERNADDR(&dma, offs); 413 sed->physaddr = DMAADDR(&dma, offs); 414 sed->dma = dma; 415 sed->offs = offs; 416 sed->next = sc->sc_freeeds; 417 sc->sc_freeeds = sed; 418 } 419 } 420 sed = sc->sc_freeeds; 421 sc->sc_freeeds = sed->next; 422 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 423 sed->next = 0; 424 return (sed); 425 } 426 427 void 428 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 429 { 430 sed->next = sc->sc_freeeds; 431 sc->sc_freeeds = sed; 432 } 433 434 ohci_soft_td_t * 435 ohci_alloc_std(ohci_softc_t *sc) 436 { 437 ohci_soft_td_t *std; 438 usbd_status err; 439 int i, offs; 440 usb_dma_t dma; 441 442 if (sc->sc_freetds == NULL) { 443 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 444 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 445 OHCI_TD_ALIGN, &dma); 446 if (err) 447 return (NULL); 448 for(i = 0; i < OHCI_STD_CHUNK; i++) { 449 offs = i * OHCI_STD_SIZE; 450 std = KERNADDR(&dma, offs); 451 std->physaddr = DMAADDR(&dma, offs); 452 std->dma = dma; 453 std->offs = offs; 454 std->nexttd = sc->sc_freetds; 455 sc->sc_freetds = std; 456 } 457 } 458 459 std = sc->sc_freetds; 460 sc->sc_freetds = std->nexttd; 461 memset(&std->td, 0, sizeof(ohci_td_t)); 462 std->nexttd = NULL; 463 std->xfer = NULL; 464 ohci_hash_add_td(sc, std); 465 466 return (std); 467 } 468 469 void 470 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 471 { 472 473 ohci_hash_rem_td(sc, std); 474 std->nexttd = sc->sc_freetds; 475 sc->sc_freetds = std; 476 } 477 478 usbd_status 479 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 480 int alen, int rd, usbd_xfer_handle xfer, 481 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 482 { 483 ohci_soft_td_t *next, *cur; 484 ohci_physaddr_t dataphys, dataphysend; 485 u_int32_t tdflags; 486 int len, curlen; 487 usb_dma_t *dma = &xfer->dmabuf; 488 u_int16_t flags = xfer->flags; 489 490 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 491 492 KASSERT(mutex_owned(&sc->sc_lock)); 493 494 len = alen; 495 cur = sp; 496 dataphys = DMAADDR(dma, 0); 497 dataphysend = OHCI_PAGE(dataphys + len - 1); 498 usb_syncmem(dma, 0, len, 499 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 500 tdflags = HTOO32( 501 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 502 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 503 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 504 505 for (;;) { 506 next = ohci_alloc_std(sc); 507 if (next == NULL) 508 goto nomem; 509 510 /* The OHCI hardware can handle at most one page crossing. */ 511 if (OHCI_PAGE(dataphys) == dataphysend || 512 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 513 /* we can handle it in this TD */ 514 curlen = len; 515 } else { 516 /* must use multiple TDs, fill as much as possible. */ 517 curlen = 2 * OHCI_PAGE_SIZE - 518 (dataphys & (OHCI_PAGE_SIZE-1)); 519 /* the length must be a multiple of the max size */ 520 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 521 #ifdef DIAGNOSTIC 522 if (curlen == 0) 523 panic("ohci_alloc_std: curlen == 0"); 524 #endif 525 } 526 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 527 "dataphysend=0x%08x len=%d curlen=%d\n", 528 dataphys, dataphysend, 529 len, curlen)); 530 len -= curlen; 531 532 cur->td.td_flags = tdflags; 533 cur->td.td_cbp = HTOO32(dataphys); 534 cur->nexttd = next; 535 cur->td.td_nexttd = HTOO32(next->physaddr); 536 cur->td.td_be = HTOO32(dataphys + curlen - 1); 537 cur->len = curlen; 538 cur->flags = OHCI_ADD_LEN; 539 cur->xfer = xfer; 540 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 541 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 542 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 543 dataphys, dataphys + curlen - 1)); 544 if (len == 0) 545 break; 546 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 547 dataphys += curlen; 548 cur = next; 549 } 550 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 551 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 552 /* Force a 0 length transfer at the end. */ 553 554 cur = next; 555 next = ohci_alloc_std(sc); 556 if (next == NULL) 557 goto nomem; 558 559 cur->td.td_flags = tdflags; 560 cur->td.td_cbp = 0; /* indicate 0 length packet */ 561 cur->nexttd = next; 562 cur->td.td_nexttd = HTOO32(next->physaddr); 563 cur->td.td_be = ~0; 564 cur->len = 0; 565 cur->flags = 0; 566 cur->xfer = xfer; 567 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 569 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 570 } 571 *ep = cur; 572 573 return (USBD_NORMAL_COMPLETION); 574 575 nomem: 576 /* XXX free chain */ 577 return (USBD_NOMEM); 578 } 579 580 #if 0 581 Static void 582 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 583 ohci_soft_td_t *stdend) 584 { 585 ohci_soft_td_t *p; 586 587 for (; std != stdend; std = p) { 588 p = std->nexttd; 589 ohci_free_std(sc, std); 590 } 591 } 592 #endif 593 594 ohci_soft_itd_t * 595 ohci_alloc_sitd(ohci_softc_t *sc) 596 { 597 ohci_soft_itd_t *sitd; 598 usbd_status err; 599 int i, offs; 600 usb_dma_t dma; 601 602 if (sc->sc_freeitds == NULL) { 603 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 604 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 605 OHCI_ITD_ALIGN, &dma); 606 if (err) 607 return (NULL); 608 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 609 offs = i * OHCI_SITD_SIZE; 610 sitd = KERNADDR(&dma, offs); 611 sitd->physaddr = DMAADDR(&dma, offs); 612 sitd->dma = dma; 613 sitd->offs = offs; 614 sitd->nextitd = sc->sc_freeitds; 615 sc->sc_freeitds = sitd; 616 } 617 } 618 619 sitd = sc->sc_freeitds; 620 sc->sc_freeitds = sitd->nextitd; 621 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 622 sitd->nextitd = NULL; 623 sitd->xfer = NULL; 624 ohci_hash_add_itd(sc, sitd); 625 626 #ifdef DIAGNOSTIC 627 sitd->isdone = 0; 628 #endif 629 630 return (sitd); 631 } 632 633 void 634 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 635 { 636 637 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 638 639 #ifdef DIAGNOSTIC 640 if (!sitd->isdone) { 641 panic("ohci_free_sitd: sitd=%p not done", sitd); 642 return; 643 } 644 /* Warn double free */ 645 sitd->isdone = 0; 646 #endif 647 648 ohci_hash_rem_itd(sc, sitd); 649 sitd->nextitd = sc->sc_freeitds; 650 sc->sc_freeitds = sitd; 651 } 652 653 usbd_status 654 ohci_init(ohci_softc_t *sc) 655 { 656 ohci_soft_ed_t *sed, *psed; 657 usbd_status err; 658 int i; 659 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 660 661 DPRINTF(("ohci_init: start\n")); 662 aprint_normal_dev(sc->sc_dev, ""); 663 664 sc->sc_hcca = NULL; 665 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 666 667 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 668 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 669 cv_init(&sc->sc_softwake_cv, "ohciab"); 670 671 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 672 ohci_rhsc_softint, sc); 673 674 for (i = 0; i < OHCI_HASH_SIZE; i++) 675 LIST_INIT(&sc->sc_hash_tds[i]); 676 for (i = 0; i < OHCI_HASH_SIZE; i++) 677 LIST_INIT(&sc->sc_hash_itds[i]); 678 679 SIMPLEQ_INIT(&sc->sc_free_xfers); 680 681 rev = OREAD4(sc, OHCI_REVISION); 682 aprint_normal("OHCI version %d.%d%s\n", 683 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 684 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 685 686 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 687 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 688 sc->sc_bus.usbrev = USBREV_UNKNOWN; 689 return (USBD_INVAL); 690 } 691 sc->sc_bus.usbrev = USBREV_1_0; 692 693 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 694 USB_MEM_RESERVE); 695 696 /* XXX determine alignment by R/W */ 697 /* Allocate the HCCA area. */ 698 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 699 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 700 if (err) { 701 sc->sc_hcca = NULL; 702 return err; 703 } 704 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 705 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 706 707 sc->sc_eintrs = OHCI_NORMAL_INTRS; 708 709 /* Allocate dummy ED that starts the control list. */ 710 sc->sc_ctrl_head = ohci_alloc_sed(sc); 711 if (sc->sc_ctrl_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad1; 714 } 715 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 717 /* Allocate dummy ED that starts the bulk list. */ 718 sc->sc_bulk_head = ohci_alloc_sed(sc); 719 if (sc->sc_bulk_head == NULL) { 720 err = USBD_NOMEM; 721 goto bad2; 722 } 723 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 724 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 725 sizeof(sc->sc_bulk_head->ed), 726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 727 728 /* Allocate dummy ED that starts the isochronous list. */ 729 sc->sc_isoc_head = ohci_alloc_sed(sc); 730 if (sc->sc_isoc_head == NULL) { 731 err = USBD_NOMEM; 732 goto bad3; 733 } 734 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 735 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 736 sizeof(sc->sc_isoc_head->ed), 737 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 738 739 /* Allocate all the dummy EDs that make up the interrupt tree. */ 740 for (i = 0; i < OHCI_NO_EDS; i++) { 741 sed = ohci_alloc_sed(sc); 742 if (sed == NULL) { 743 while (--i >= 0) 744 ohci_free_sed(sc, sc->sc_eds[i]); 745 err = USBD_NOMEM; 746 goto bad4; 747 } 748 /* All ED fields are set to 0. */ 749 sc->sc_eds[i] = sed; 750 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 751 if (i != 0) 752 psed = sc->sc_eds[(i-1) / 2]; 753 else 754 psed= sc->sc_isoc_head; 755 sed->next = psed; 756 sed->ed.ed_nexted = HTOO32(psed->physaddr); 757 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 758 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 759 } 760 /* 761 * Fill HCCA interrupt table. The bit reversal is to get 762 * the tree set up properly to spread the interrupts. 763 */ 764 for (i = 0; i < OHCI_NO_INTRS; i++) 765 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 766 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 767 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 769 770 #ifdef OHCI_DEBUG 771 if (ohcidebug > 15) { 772 for (i = 0; i < OHCI_NO_EDS; i++) { 773 printf("ed#%d ", i); 774 ohci_dump_ed(sc, sc->sc_eds[i]); 775 } 776 printf("iso "); 777 ohci_dump_ed(sc, sc->sc_isoc_head); 778 } 779 #endif 780 781 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 782 ctl = OREAD4(sc, OHCI_CONTROL); 783 rwc = ctl & OHCI_RWC; 784 fm = OREAD4(sc, OHCI_FM_INTERVAL); 785 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 786 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 787 788 /* Determine in what context we are running. */ 789 if (ctl & OHCI_IR) { 790 /* SMM active, request change */ 791 DPRINTF(("ohci_init: SMM active, request owner change\n")); 792 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 793 (OHCI_OC | OHCI_MIE)) 794 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 795 s = OREAD4(sc, OHCI_COMMAND_STATUS); 796 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 797 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 798 usb_delay_ms(&sc->sc_bus, 1); 799 ctl = OREAD4(sc, OHCI_CONTROL); 800 } 801 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 802 if ((ctl & OHCI_IR) == 0) { 803 aprint_error_dev(sc->sc_dev, 804 "SMM does not respond, resetting\n"); 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 806 goto reset; 807 } 808 #if 0 809 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 810 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 811 /* BIOS started controller. */ 812 DPRINTF(("ohci_init: BIOS active\n")); 813 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 814 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 815 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 816 } 817 #endif 818 } else { 819 DPRINTF(("ohci_init: cold started\n")); 820 reset: 821 /* Controller was cold started. */ 822 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 823 } 824 825 /* 826 * This reset should not be necessary according to the OHCI spec, but 827 * without it some controllers do not start. 828 */ 829 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 830 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 831 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 832 833 /* We now own the host controller and the bus has been reset. */ 834 835 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 836 /* Nominal time for a reset is 10 us. */ 837 for (i = 0; i < 10; i++) { 838 delay(10); 839 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 840 if (!hcr) 841 break; 842 } 843 if (hcr) { 844 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 845 err = USBD_IOERROR; 846 goto bad5; 847 } 848 #ifdef OHCI_DEBUG 849 if (ohcidebug > 15) 850 ohci_dumpregs(sc); 851 #endif 852 853 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 854 855 /* Set up HC registers. */ 856 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 857 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 858 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 859 /* disable all interrupts and then switch on all desired interrupts */ 860 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 861 /* switch on desired functional features */ 862 ctl = OREAD4(sc, OHCI_CONTROL); 863 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 864 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 865 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 866 /* And finally start it! */ 867 OWRITE4(sc, OHCI_CONTROL, ctl); 868 869 /* 870 * The controller is now OPERATIONAL. Set a some final 871 * registers that should be set earlier, but that the 872 * controller ignores when in the SUSPEND state. 873 */ 874 ival = OHCI_GET_IVAL(fm); 875 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 876 fm |= OHCI_FSMPS(ival) | ival; 877 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 878 per = OHCI_PERIODIC(ival); /* 90% periodic */ 879 OWRITE4(sc, OHCI_PERIODIC_START, per); 880 881 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 882 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 883 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 884 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 885 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 886 887 /* 888 * The AMD756 requires a delay before re-reading the register, 889 * otherwise it will occasionally report 0 ports. 890 */ 891 sc->sc_noport = 0; 892 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 893 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 894 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 895 } 896 897 #ifdef OHCI_DEBUG 898 if (ohcidebug > 5) 899 ohci_dumpregs(sc); 900 #endif 901 902 /* Set up the bus struct. */ 903 sc->sc_bus.methods = &ohci_bus_methods; 904 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 905 906 sc->sc_control = sc->sc_intre = 0; 907 908 /* Finally, turn on interrupts. */ 909 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 910 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 911 912 return (USBD_NORMAL_COMPLETION); 913 914 bad5: 915 for (i = 0; i < OHCI_NO_EDS; i++) 916 ohci_free_sed(sc, sc->sc_eds[i]); 917 bad4: 918 ohci_free_sed(sc, sc->sc_isoc_head); 919 bad3: 920 ohci_free_sed(sc, sc->sc_bulk_head); 921 bad2: 922 ohci_free_sed(sc, sc->sc_ctrl_head); 923 bad1: 924 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 925 sc->sc_hcca = NULL; 926 return (err); 927 } 928 929 usbd_status 930 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 931 { 932 struct ohci_softc *sc = bus->hci_private; 933 usbd_status status; 934 935 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 936 if (status == USBD_NOMEM) 937 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 938 return status; 939 } 940 941 void 942 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 943 { 944 struct ohci_softc *sc = bus->hci_private; 945 if (dma->block->flags & USB_DMA_RESERVE) { 946 usb_reserve_freem(&sc->sc_dma_reserve, dma); 947 return; 948 } 949 usb_freemem(&sc->sc_bus, dma); 950 } 951 952 usbd_xfer_handle 953 ohci_allocx(struct usbd_bus *bus) 954 { 955 struct ohci_softc *sc = bus->hci_private; 956 usbd_xfer_handle xfer; 957 958 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 959 if (xfer != NULL) { 960 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 961 #ifdef DIAGNOSTIC 962 if (xfer->busy_free != XFER_FREE) { 963 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 964 xfer->busy_free); 965 } 966 #endif 967 } else { 968 xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP); 969 } 970 if (xfer != NULL) { 971 memset(xfer, 0, sizeof (struct ohci_xfer)); 972 #ifdef DIAGNOSTIC 973 xfer->busy_free = XFER_BUSY; 974 #endif 975 } 976 return (xfer); 977 } 978 979 void 980 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 981 { 982 struct ohci_softc *sc = bus->hci_private; 983 984 #ifdef DIAGNOSTIC 985 if (xfer->busy_free != XFER_BUSY) { 986 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 987 xfer->busy_free); 988 } 989 xfer->busy_free = XFER_FREE; 990 #endif 991 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 992 } 993 994 Static void 995 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 996 { 997 struct ohci_softc *sc = bus->hci_private; 998 999 *lock = &sc->sc_lock; 1000 } 1001 1002 /* 1003 * Shut down the controller when the system is going down. 1004 */ 1005 bool 1006 ohci_shutdown(device_t self, int flags) 1007 { 1008 ohci_softc_t *sc = device_private(self); 1009 1010 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1011 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1012 return true; 1013 } 1014 1015 bool 1016 ohci_resume(device_t dv, const pmf_qual_t *qual) 1017 { 1018 ohci_softc_t *sc = device_private(dv); 1019 uint32_t ctl; 1020 1021 mutex_spin_enter(&sc->sc_intr_lock); 1022 sc->sc_bus.use_polling++; 1023 mutex_spin_exit(&sc->sc_intr_lock); 1024 1025 /* Some broken BIOSes do not recover these values */ 1026 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1027 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1028 sc->sc_ctrl_head->physaddr); 1029 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1030 sc->sc_bulk_head->physaddr); 1031 if (sc->sc_intre) 1032 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1033 (OHCI_ALL_INTRS | OHCI_MIE)); 1034 if (sc->sc_control) 1035 ctl = sc->sc_control; 1036 else 1037 ctl = OREAD4(sc, OHCI_CONTROL); 1038 ctl |= OHCI_HCFS_RESUME; 1039 OWRITE4(sc, OHCI_CONTROL, ctl); 1040 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1041 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1042 OWRITE4(sc, OHCI_CONTROL, ctl); 1043 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1044 sc->sc_control = sc->sc_intre = 0; 1045 1046 mutex_spin_enter(&sc->sc_intr_lock); 1047 sc->sc_bus.use_polling--; 1048 mutex_spin_exit(&sc->sc_intr_lock); 1049 1050 return true; 1051 } 1052 1053 bool 1054 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1055 { 1056 ohci_softc_t *sc = device_private(dv); 1057 uint32_t ctl; 1058 1059 mutex_spin_enter(&sc->sc_intr_lock); 1060 sc->sc_bus.use_polling++; 1061 mutex_spin_exit(&sc->sc_intr_lock); 1062 1063 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1064 if (sc->sc_control == 0) { 1065 /* 1066 * Preserve register values, in case that BIOS 1067 * does not recover them. 1068 */ 1069 sc->sc_control = ctl; 1070 sc->sc_intre = OREAD4(sc, 1071 OHCI_INTERRUPT_ENABLE); 1072 } 1073 ctl |= OHCI_HCFS_SUSPEND; 1074 OWRITE4(sc, OHCI_CONTROL, ctl); 1075 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1076 1077 mutex_spin_enter(&sc->sc_intr_lock); 1078 sc->sc_bus.use_polling--; 1079 mutex_spin_exit(&sc->sc_intr_lock); 1080 1081 return true; 1082 } 1083 1084 #ifdef OHCI_DEBUG 1085 void 1086 ohci_dumpregs(ohci_softc_t *sc) 1087 { 1088 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1089 OREAD4(sc, OHCI_REVISION), 1090 OREAD4(sc, OHCI_CONTROL), 1091 OREAD4(sc, OHCI_COMMAND_STATUS))); 1092 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1093 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1094 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1095 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1096 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1097 OREAD4(sc, OHCI_HCCA), 1098 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1099 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1100 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1101 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1102 OREAD4(sc, OHCI_BULK_HEAD_ED), 1103 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1104 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1105 OREAD4(sc, OHCI_DONE_HEAD), 1106 OREAD4(sc, OHCI_FM_INTERVAL), 1107 OREAD4(sc, OHCI_FM_REMAINING))); 1108 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1109 OREAD4(sc, OHCI_FM_NUMBER), 1110 OREAD4(sc, OHCI_PERIODIC_START), 1111 OREAD4(sc, OHCI_LS_THRESHOLD))); 1112 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1113 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1114 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1115 OREAD4(sc, OHCI_RH_STATUS))); 1116 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1117 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1118 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1119 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1120 O32TOH(sc->sc_hcca->hcca_frame_number), 1121 O32TOH(sc->sc_hcca->hcca_done_head))); 1122 } 1123 #endif 1124 1125 Static int ohci_intr1(ohci_softc_t *); 1126 1127 int 1128 ohci_intr(void *p) 1129 { 1130 ohci_softc_t *sc = p; 1131 int ret = 0; 1132 1133 if (sc == NULL) 1134 return (0); 1135 1136 mutex_spin_enter(&sc->sc_intr_lock); 1137 1138 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1139 goto done; 1140 1141 /* If we get an interrupt while polling, then just ignore it. */ 1142 if (sc->sc_bus.use_polling) { 1143 #ifdef DIAGNOSTIC 1144 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1145 #endif 1146 /* for level triggered intrs, should do something to ack */ 1147 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1148 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1149 1150 goto done; 1151 } 1152 1153 ret = ohci_intr1(sc); 1154 1155 done: 1156 mutex_spin_exit(&sc->sc_intr_lock); 1157 return ret; 1158 } 1159 1160 Static int 1161 ohci_intr1(ohci_softc_t *sc) 1162 { 1163 u_int32_t intrs, eintrs; 1164 1165 DPRINTFN(14,("ohci_intr1: enter\n")); 1166 1167 /* In case the interrupt occurs before initialization has completed. */ 1168 if (sc == NULL || sc->sc_hcca == NULL) { 1169 #ifdef DIAGNOSTIC 1170 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1171 #endif 1172 return (0); 1173 } 1174 1175 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1176 1177 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1178 if (!intrs) 1179 return (0); 1180 1181 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1182 eintrs = intrs & sc->sc_eintrs; 1183 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1184 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1185 (u_int)eintrs, sc->sc_eintrs)); 1186 1187 if (!eintrs) { 1188 return (0); 1189 } 1190 1191 sc->sc_bus.no_intrs++; 1192 if (eintrs & OHCI_SO) { 1193 sc->sc_overrun_cnt++; 1194 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1195 printf("%s: %u scheduling overruns\n", 1196 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1197 sc->sc_overrun_cnt = 0; 1198 } 1199 /* XXX do what */ 1200 eintrs &= ~OHCI_SO; 1201 } 1202 if (eintrs & OHCI_WDH) { 1203 /* 1204 * We block the interrupt below, and reenable it later from 1205 * ohci_softintr(). 1206 */ 1207 usb_schedsoftintr(&sc->sc_bus); 1208 } 1209 if (eintrs & OHCI_RD) { 1210 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1211 /* XXX process resume detect */ 1212 } 1213 if (eintrs & OHCI_UE) { 1214 printf("%s: unrecoverable error, controller halted\n", 1215 device_xname(sc->sc_dev)); 1216 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1217 /* XXX what else */ 1218 } 1219 if (eintrs & OHCI_RHSC) { 1220 /* 1221 * We block the interrupt below, and reenable it later from 1222 * a timeout. 1223 */ 1224 softint_schedule(sc->sc_rhsc_si); 1225 } 1226 1227 if (eintrs != 0) { 1228 /* Block unprocessed interrupts. */ 1229 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1230 sc->sc_eintrs &= ~eintrs; 1231 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1232 device_xname(sc->sc_dev), eintrs)); 1233 } 1234 1235 return (1); 1236 } 1237 1238 void 1239 ohci_rhsc_enable(void *v_sc) 1240 { 1241 ohci_softc_t *sc = v_sc; 1242 1243 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1244 mutex_spin_enter(&sc->sc_intr_lock); 1245 sc->sc_eintrs |= OHCI_RHSC; 1246 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1247 mutex_spin_exit(&sc->sc_intr_lock); 1248 } 1249 1250 #ifdef OHCI_DEBUG 1251 const char *ohci_cc_strs[] = { 1252 "NO_ERROR", 1253 "CRC", 1254 "BIT_STUFFING", 1255 "DATA_TOGGLE_MISMATCH", 1256 "STALL", 1257 "DEVICE_NOT_RESPONDING", 1258 "PID_CHECK_FAILURE", 1259 "UNEXPECTED_PID", 1260 "DATA_OVERRUN", 1261 "DATA_UNDERRUN", 1262 "BUFFER_OVERRUN", 1263 "BUFFER_UNDERRUN", 1264 "reserved", 1265 "reserved", 1266 "NOT_ACCESSED", 1267 "NOT_ACCESSED", 1268 }; 1269 #endif 1270 1271 void 1272 ohci_softintr(void *v) 1273 { 1274 struct usbd_bus *bus = v; 1275 ohci_softc_t *sc = bus->hci_private; 1276 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1277 ohci_soft_td_t *std, *sdone, *stdnext; 1278 usbd_xfer_handle xfer; 1279 struct ohci_pipe *opipe; 1280 int len, cc; 1281 int i, j, actlen, iframes, uedir; 1282 ohci_physaddr_t done; 1283 1284 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1285 1286 DPRINTFN(10,("ohci_softintr: enter\n")); 1287 1288 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1289 sizeof(sc->sc_hcca->hcca_done_head), 1290 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1291 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1292 sc->sc_hcca->hcca_done_head = 0; 1293 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1294 sizeof(sc->sc_hcca->hcca_done_head), 1295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1296 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1297 sc->sc_eintrs |= OHCI_WDH; 1298 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1299 1300 /* Reverse the done list. */ 1301 for (sdone = NULL, sidone = NULL; done != 0; ) { 1302 std = ohci_hash_find_td(sc, done); 1303 if (std != NULL) { 1304 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1305 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1306 std->dnext = sdone; 1307 done = O32TOH(std->td.td_nexttd); 1308 sdone = std; 1309 DPRINTFN(10,("add TD %p\n", std)); 1310 continue; 1311 } 1312 sitd = ohci_hash_find_itd(sc, done); 1313 if (sitd != NULL) { 1314 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1315 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1316 sitd->dnext = sidone; 1317 done = O32TOH(sitd->itd.itd_nextitd); 1318 sidone = sitd; 1319 DPRINTFN(5,("add ITD %p\n", sitd)); 1320 continue; 1321 } 1322 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1323 (u_long)done); 1324 break; 1325 } 1326 1327 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1328 1329 #ifdef OHCI_DEBUG 1330 if (ohcidebug > 10) { 1331 DPRINTF(("ohci_process_done: TD done:\n")); 1332 ohci_dump_tds(sc, sdone); 1333 } 1334 #endif 1335 1336 for (std = sdone; std; std = stdnext) { 1337 xfer = std->xfer; 1338 stdnext = std->dnext; 1339 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1340 std, xfer, xfer ? xfer->hcpriv : 0)); 1341 if (xfer == NULL) { 1342 /* 1343 * xfer == NULL: There seems to be no xfer associated 1344 * with this TD. It is tailp that happened to end up on 1345 * the done queue. 1346 * Shouldn't happen, but some chips are broken(?). 1347 */ 1348 continue; 1349 } 1350 if (xfer->status == USBD_CANCELLED || 1351 xfer->status == USBD_TIMEOUT) { 1352 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1353 xfer)); 1354 /* Handled by abort routine. */ 1355 continue; 1356 } 1357 callout_stop(&xfer->timeout_handle); 1358 1359 len = std->len; 1360 if (std->td.td_cbp != 0) 1361 len -= O32TOH(std->td.td_be) - 1362 O32TOH(std->td.td_cbp) + 1; 1363 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1364 std->flags)); 1365 if (std->flags & OHCI_ADD_LEN) 1366 xfer->actlen += len; 1367 1368 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1369 if (cc == OHCI_CC_NO_ERROR) { 1370 if (std->flags & OHCI_CALL_DONE) { 1371 xfer->status = USBD_NORMAL_COMPLETION; 1372 usb_transfer_complete(xfer); 1373 } 1374 ohci_free_std(sc, std); 1375 } else { 1376 /* 1377 * Endpoint is halted. First unlink all the TDs 1378 * belonging to the failed transfer, and then restart 1379 * the endpoint. 1380 */ 1381 ohci_soft_td_t *p, *n; 1382 opipe = (struct ohci_pipe *)xfer->pipe; 1383 1384 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1385 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1386 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1387 1388 /* remove TDs */ 1389 for (p = std; p->xfer == xfer; p = n) { 1390 n = p->nexttd; 1391 ohci_free_std(sc, p); 1392 } 1393 1394 /* clear halt */ 1395 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1396 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1397 1398 if (cc == OHCI_CC_STALL) 1399 xfer->status = USBD_STALLED; 1400 else 1401 xfer->status = USBD_IOERROR; 1402 usb_transfer_complete(xfer); 1403 } 1404 } 1405 1406 #ifdef OHCI_DEBUG 1407 if (ohcidebug > 10) { 1408 DPRINTF(("ohci_softintr: ITD done:\n")); 1409 ohci_dump_itds(sc, sidone); 1410 } 1411 #endif 1412 1413 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1414 xfer = sitd->xfer; 1415 sitdnext = sitd->dnext; 1416 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1417 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1418 if (xfer == NULL) 1419 continue; 1420 if (xfer->status == USBD_CANCELLED || 1421 xfer->status == USBD_TIMEOUT) { 1422 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1423 xfer)); 1424 /* Handled by abort routine. */ 1425 continue; 1426 } 1427 #ifdef DIAGNOSTIC 1428 if (sitd->isdone) 1429 printf("ohci_softintr: sitd=%p is done\n", sitd); 1430 sitd->isdone = 1; 1431 #endif 1432 if (sitd->flags & OHCI_CALL_DONE) { 1433 ohci_soft_itd_t *next; 1434 1435 opipe = (struct ohci_pipe *)xfer->pipe; 1436 opipe->u.iso.inuse -= xfer->nframes; 1437 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1438 bEndpointAddress); 1439 xfer->status = USBD_NORMAL_COMPLETION; 1440 actlen = 0; 1441 for (i = 0, sitd = xfer->hcpriv;; 1442 sitd = next) { 1443 next = sitd->nextitd; 1444 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1445 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1446 xfer->status = USBD_IOERROR; 1447 /* For input, update frlengths with actual */ 1448 /* XXX anything necessary for output? */ 1449 if (uedir == UE_DIR_IN && 1450 xfer->status == USBD_NORMAL_COMPLETION) { 1451 iframes = OHCI_ITD_GET_FC(O32TOH( 1452 sitd->itd.itd_flags)); 1453 for (j = 0; j < iframes; i++, j++) { 1454 len = O16TOH(sitd-> 1455 itd.itd_offset[j]); 1456 if ((OHCI_ITD_PSW_GET_CC(len) & 1457 OHCI_CC_NOT_ACCESSED_MASK) 1458 == OHCI_CC_NOT_ACCESSED) 1459 len = 0; 1460 else 1461 len = OHCI_ITD_PSW_LENGTH(len); 1462 xfer->frlengths[i] = len; 1463 actlen += len; 1464 } 1465 } 1466 if (sitd->flags & OHCI_CALL_DONE) 1467 break; 1468 ohci_free_sitd(sc, sitd); 1469 } 1470 ohci_free_sitd(sc, sitd); 1471 if (uedir == UE_DIR_IN && 1472 xfer->status == USBD_NORMAL_COMPLETION) 1473 xfer->actlen = actlen; 1474 xfer->hcpriv = NULL; 1475 1476 usb_transfer_complete(xfer); 1477 } 1478 } 1479 1480 if (sc->sc_softwake) { 1481 sc->sc_softwake = 0; 1482 cv_broadcast(&sc->sc_softwake_cv); 1483 } 1484 1485 DPRINTFN(10,("ohci_softintr: done:\n")); 1486 } 1487 1488 void 1489 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1490 { 1491 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1492 #ifdef DIAGNOSTIC 1493 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1494 #endif 1495 int len = UGETW(xfer->request.wLength); 1496 int isread = (xfer->request.bmRequestType & UT_READ); 1497 1498 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1499 1500 KASSERT(mutex_owned(&sc->sc_lock)); 1501 1502 #ifdef DIAGNOSTIC 1503 if (!(xfer->rqflags & URQ_REQUEST)) { 1504 panic("ohci_device_ctrl_done: not a request"); 1505 } 1506 #endif 1507 if (len) 1508 usb_syncmem(&xfer->dmabuf, 0, len, 1509 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1510 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1511 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1512 } 1513 1514 void 1515 ohci_device_intr_done(usbd_xfer_handle xfer) 1516 { 1517 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1518 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1519 ohci_soft_ed_t *sed = opipe->sed; 1520 ohci_soft_td_t *data, *tail; 1521 int isread = 1522 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1523 1524 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1525 xfer, xfer->actlen)); 1526 1527 KASSERT(mutex_owned(&sc->sc_lock)); 1528 1529 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1530 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1531 if (xfer->pipe->repeat) { 1532 data = opipe->tail.td; 1533 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1534 if (tail == NULL) { 1535 xfer->status = USBD_NOMEM; 1536 return; 1537 } 1538 tail->xfer = NULL; 1539 1540 data->td.td_flags = HTOO32( 1541 OHCI_TD_IN | OHCI_TD_NOCC | 1542 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1543 if (xfer->flags & USBD_SHORT_XFER_OK) 1544 data->td.td_flags |= HTOO32(OHCI_TD_R); 1545 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1546 data->nexttd = tail; 1547 data->td.td_nexttd = HTOO32(tail->physaddr); 1548 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1549 xfer->length - 1); 1550 data->len = xfer->length; 1551 data->xfer = xfer; 1552 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1553 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1554 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1555 xfer->hcpriv = data; 1556 xfer->actlen = 0; 1557 1558 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1559 usb_syncmem(&sed->dma, 1560 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1561 sizeof(sed->ed.ed_tailp), 1562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1563 opipe->tail.td = tail; 1564 } 1565 } 1566 1567 void 1568 ohci_device_bulk_done(usbd_xfer_handle xfer) 1569 { 1570 #ifdef DIAGNOSTIC 1571 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1572 #endif 1573 int isread = 1574 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1575 1576 KASSERT(mutex_owned(&sc->sc_lock)); 1577 1578 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1579 xfer, xfer->actlen)); 1580 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1581 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1582 } 1583 1584 Static void 1585 ohci_rhsc_softint(void *arg) 1586 { 1587 ohci_softc_t *sc = arg; 1588 1589 mutex_enter(&sc->sc_lock); 1590 1591 ohci_rhsc(sc, sc->sc_intrxfer); 1592 1593 /* Do not allow RHSC interrupts > 1 per second */ 1594 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1595 1596 mutex_exit(&sc->sc_lock); 1597 } 1598 1599 void 1600 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1601 { 1602 usbd_pipe_handle pipe; 1603 u_char *p; 1604 int i, m; 1605 int hstatus; 1606 1607 KASSERT(mutex_owned(&sc->sc_lock)); 1608 1609 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1610 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1611 sc, xfer, hstatus)); 1612 1613 if (xfer == NULL) { 1614 /* Just ignore the change. */ 1615 return; 1616 } 1617 1618 pipe = xfer->pipe; 1619 1620 p = KERNADDR(&xfer->dmabuf, 0); 1621 m = min(sc->sc_noport, xfer->length * 8 - 1); 1622 memset(p, 0, xfer->length); 1623 for (i = 1; i <= m; i++) { 1624 /* Pick out CHANGE bits from the status reg. */ 1625 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1626 p[i/8] |= 1 << (i%8); 1627 } 1628 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1629 xfer->actlen = xfer->length; 1630 xfer->status = USBD_NORMAL_COMPLETION; 1631 1632 usb_transfer_complete(xfer); 1633 } 1634 1635 void 1636 ohci_root_intr_done(usbd_xfer_handle xfer) 1637 { 1638 } 1639 1640 void 1641 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1642 { 1643 } 1644 1645 /* 1646 * Wait here until controller claims to have an interrupt. 1647 * Then call ohci_intr and return. Use timeout to avoid waiting 1648 * too long. 1649 */ 1650 void 1651 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1652 { 1653 int timo; 1654 u_int32_t intrs; 1655 1656 mutex_enter(&sc->sc_lock); 1657 1658 xfer->status = USBD_IN_PROGRESS; 1659 for (timo = xfer->timeout; timo >= 0; timo--) { 1660 usb_delay_ms(&sc->sc_bus, 1); 1661 if (sc->sc_dying) 1662 break; 1663 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1664 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1665 #ifdef OHCI_DEBUG 1666 if (ohcidebug > 15) 1667 ohci_dumpregs(sc); 1668 #endif 1669 if (intrs) { 1670 mutex_spin_enter(&sc->sc_intr_lock); 1671 ohci_intr1(sc); 1672 mutex_spin_exit(&sc->sc_intr_lock); 1673 if (xfer->status != USBD_IN_PROGRESS) 1674 return; 1675 } 1676 } 1677 1678 /* Timeout */ 1679 DPRINTF(("ohci_waitintr: timeout\n")); 1680 xfer->status = USBD_TIMEOUT; 1681 usb_transfer_complete(xfer); 1682 1683 /* XXX should free TD */ 1684 1685 mutex_exit(&sc->sc_lock); 1686 } 1687 1688 void 1689 ohci_poll(struct usbd_bus *bus) 1690 { 1691 ohci_softc_t *sc = bus->hci_private; 1692 #ifdef OHCI_DEBUG 1693 static int last; 1694 int new; 1695 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1696 if (new != last) { 1697 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1698 last = new; 1699 } 1700 #endif 1701 1702 sc->sc_eintrs |= OHCI_WDH; 1703 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1704 mutex_spin_enter(&sc->sc_intr_lock); 1705 ohci_intr1(sc); 1706 mutex_spin_exit(&sc->sc_intr_lock); 1707 } 1708 } 1709 1710 usbd_status 1711 ohci_device_request(usbd_xfer_handle xfer) 1712 { 1713 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1714 usb_device_request_t *req = &xfer->request; 1715 usbd_device_handle dev = opipe->pipe.device; 1716 ohci_softc_t *sc = dev->bus->hci_private; 1717 int addr = dev->address; 1718 ohci_soft_td_t *setup, *stat, *next, *tail; 1719 ohci_soft_ed_t *sed; 1720 int isread; 1721 int len; 1722 usbd_status err; 1723 1724 KASSERT(mutex_owned(&sc->sc_lock)); 1725 1726 isread = req->bmRequestType & UT_READ; 1727 len = UGETW(req->wLength); 1728 1729 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1730 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1731 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1732 UGETW(req->wIndex), len, addr, 1733 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1734 1735 setup = opipe->tail.td; 1736 stat = ohci_alloc_std(sc); 1737 if (stat == NULL) { 1738 err = USBD_NOMEM; 1739 goto bad1; 1740 } 1741 tail = ohci_alloc_std(sc); 1742 if (tail == NULL) { 1743 err = USBD_NOMEM; 1744 goto bad2; 1745 } 1746 tail->xfer = NULL; 1747 1748 sed = opipe->sed; 1749 opipe->u.ctl.length = len; 1750 1751 /* Update device address and length since they may have changed 1752 during the setup of the control pipe in usbd_new_device(). */ 1753 /* XXX This only needs to be done once, but it's too early in open. */ 1754 /* XXXX Should not touch ED here! */ 1755 1756 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1757 sizeof(sed->ed.ed_flags), 1758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1759 sed->ed.ed_flags = HTOO32( 1760 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1761 OHCI_ED_SET_FA(addr) | 1762 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1763 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1764 sizeof(sed->ed.ed_flags), 1765 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1766 1767 next = stat; 1768 1769 /* Set up data transaction */ 1770 if (len != 0) { 1771 ohci_soft_td_t *std = stat; 1772 1773 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1774 std, &stat); 1775 stat = stat->nexttd; /* point at free TD */ 1776 if (err) 1777 goto bad3; 1778 /* Start toggle at 1 and then use the carried toggle. */ 1779 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1780 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1781 usb_syncmem(&std->dma, 1782 std->offs + offsetof(ohci_td_t, td_flags), 1783 sizeof(std->td.td_flags), 1784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1785 } 1786 1787 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1788 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1789 1790 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1791 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1792 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1793 setup->nexttd = next; 1794 setup->td.td_nexttd = HTOO32(next->physaddr); 1795 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1796 setup->len = 0; 1797 setup->xfer = xfer; 1798 setup->flags = 0; 1799 xfer->hcpriv = setup; 1800 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1801 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1802 1803 stat->td.td_flags = HTOO32( 1804 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1805 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1806 stat->td.td_cbp = 0; 1807 stat->nexttd = tail; 1808 stat->td.td_nexttd = HTOO32(tail->physaddr); 1809 stat->td.td_be = 0; 1810 stat->flags = OHCI_CALL_DONE; 1811 stat->len = 0; 1812 stat->xfer = xfer; 1813 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1814 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1815 1816 #ifdef OHCI_DEBUG 1817 if (ohcidebug > 5) { 1818 DPRINTF(("ohci_device_request:\n")); 1819 ohci_dump_ed(sc, sed); 1820 ohci_dump_tds(sc, setup); 1821 } 1822 #endif 1823 1824 /* Insert ED in schedule */ 1825 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1826 usb_syncmem(&sed->dma, 1827 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1828 sizeof(sed->ed.ed_tailp), 1829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1830 opipe->tail.td = tail; 1831 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1832 if (xfer->timeout && !sc->sc_bus.use_polling) { 1833 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1834 ohci_timeout, xfer); 1835 } 1836 1837 #ifdef OHCI_DEBUG 1838 if (ohcidebug > 20) { 1839 delay(10000); 1840 DPRINTF(("ohci_device_request: status=%x\n", 1841 OREAD4(sc, OHCI_COMMAND_STATUS))); 1842 ohci_dumpregs(sc); 1843 printf("ctrl head:\n"); 1844 ohci_dump_ed(sc, sc->sc_ctrl_head); 1845 printf("sed:\n"); 1846 ohci_dump_ed(sc, sed); 1847 ohci_dump_tds(sc, setup); 1848 } 1849 #endif 1850 1851 return (USBD_NORMAL_COMPLETION); 1852 1853 bad3: 1854 ohci_free_std(sc, tail); 1855 bad2: 1856 ohci_free_std(sc, stat); 1857 bad1: 1858 return (err); 1859 } 1860 1861 /* 1862 * Add an ED to the schedule. Called with USB lock held. 1863 */ 1864 Static void 1865 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1866 { 1867 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1868 1869 KASSERT(mutex_owned(&sc->sc_lock)); 1870 1871 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1872 sizeof(head->ed.ed_nexted), 1873 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1874 sed->next = head->next; 1875 sed->ed.ed_nexted = head->ed.ed_nexted; 1876 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1877 sizeof(sed->ed.ed_nexted), 1878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1879 head->next = sed; 1880 head->ed.ed_nexted = HTOO32(sed->physaddr); 1881 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1882 sizeof(head->ed.ed_nexted), 1883 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1884 } 1885 1886 /* 1887 * Remove an ED from the schedule. Called with USB lock held. 1888 */ 1889 Static void 1890 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1891 { 1892 ohci_soft_ed_t *p; 1893 1894 KASSERT(mutex_owned(&sc->sc_lock)); 1895 1896 /* XXX */ 1897 for (p = head; p != NULL && p->next != sed; p = p->next) 1898 ; 1899 if (p == NULL) 1900 panic("ohci_rem_ed: ED not found"); 1901 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1902 sizeof(sed->ed.ed_nexted), 1903 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1904 p->next = sed->next; 1905 p->ed.ed_nexted = sed->ed.ed_nexted; 1906 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1907 sizeof(p->ed.ed_nexted), 1908 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1909 } 1910 1911 /* 1912 * When a transfer is completed the TD is added to the done queue by 1913 * the host controller. This queue is the processed by software. 1914 * Unfortunately the queue contains the physical address of the TD 1915 * and we have no simple way to translate this back to a kernel address. 1916 * To make the translation possible (and fast) we use a hash table of 1917 * TDs currently in the schedule. The physical address is used as the 1918 * hash value. 1919 */ 1920 1921 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1922 /* Called with USB lock held. */ 1923 void 1924 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1925 { 1926 int h = HASH(std->physaddr); 1927 1928 KASSERT(mutex_owned(&sc->sc_lock)); 1929 1930 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1931 } 1932 1933 /* Called with USB lock held. */ 1934 void 1935 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1936 { 1937 1938 KASSERT(mutex_owned(&sc->sc_lock)); 1939 1940 LIST_REMOVE(std, hnext); 1941 } 1942 1943 ohci_soft_td_t * 1944 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1945 { 1946 int h = HASH(a); 1947 ohci_soft_td_t *std; 1948 1949 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1950 std != NULL; 1951 std = LIST_NEXT(std, hnext)) 1952 if (std->physaddr == a) 1953 return (std); 1954 return (NULL); 1955 } 1956 1957 /* Called with USB lock held. */ 1958 void 1959 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1960 { 1961 int h = HASH(sitd->physaddr); 1962 1963 KASSERT(mutex_owned(&sc->sc_lock)); 1964 1965 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1966 sitd, (u_long)sitd->physaddr)); 1967 1968 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1969 } 1970 1971 /* Called with USB lock held. */ 1972 void 1973 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1974 { 1975 KASSERT(mutex_owned(&sc->sc_lock)); 1976 1977 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1978 sitd, (u_long)sitd->physaddr)); 1979 1980 LIST_REMOVE(sitd, hnext); 1981 } 1982 1983 ohci_soft_itd_t * 1984 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1985 { 1986 int h = HASH(a); 1987 ohci_soft_itd_t *sitd; 1988 1989 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1990 sitd != NULL; 1991 sitd = LIST_NEXT(sitd, hnext)) 1992 if (sitd->physaddr == a) 1993 return (sitd); 1994 return (NULL); 1995 } 1996 1997 void 1998 ohci_timeout(void *addr) 1999 { 2000 struct ohci_xfer *oxfer = addr; 2001 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2002 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2003 2004 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2005 2006 if (sc->sc_dying) { 2007 mutex_enter(&sc->sc_lock); 2008 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2009 mutex_exit(&sc->sc_lock); 2010 return; 2011 } 2012 2013 /* Execute the abort in a process context. */ 2014 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 2015 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2016 USB_TASKQ_HC); 2017 } 2018 2019 void 2020 ohci_timeout_task(void *addr) 2021 { 2022 usbd_xfer_handle xfer = addr; 2023 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2024 2025 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2026 2027 mutex_enter(&sc->sc_lock); 2028 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2029 mutex_exit(&sc->sc_lock); 2030 } 2031 2032 #ifdef OHCI_DEBUG 2033 void 2034 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2035 { 2036 for (; std; std = std->nexttd) 2037 ohci_dump_td(sc, std); 2038 } 2039 2040 void 2041 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2042 { 2043 char sbuf[128]; 2044 2045 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2046 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2047 snprintb(sbuf, sizeof(sbuf), 2048 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2049 (u_int32_t)O32TOH(std->td.td_flags)); 2050 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2051 "nexttd=0x%08lx be=0x%08lx\n", 2052 std, (u_long)std->physaddr, sbuf, 2053 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2054 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2055 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2056 (u_long)O32TOH(std->td.td_cbp), 2057 (u_long)O32TOH(std->td.td_nexttd), 2058 (u_long)O32TOH(std->td.td_be)); 2059 } 2060 2061 void 2062 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2063 { 2064 int i; 2065 2066 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2067 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2068 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2069 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2070 sitd, (u_long)sitd->physaddr, 2071 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2072 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2073 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2074 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2075 (u_long)O32TOH(sitd->itd.itd_bp0), 2076 (u_long)O32TOH(sitd->itd.itd_nextitd), 2077 (u_long)O32TOH(sitd->itd.itd_be)); 2078 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2079 printf("offs[%d]=0x%04x ", i, 2080 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2081 printf("\n"); 2082 } 2083 2084 void 2085 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2086 { 2087 for (; sitd; sitd = sitd->nextitd) 2088 ohci_dump_itd(sc, sitd); 2089 } 2090 2091 void 2092 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2093 { 2094 char sbuf[128], sbuf2[128]; 2095 2096 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2097 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2098 snprintb(sbuf, sizeof(sbuf), 2099 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2100 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2101 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2102 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2103 2104 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2105 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2106 sed, (u_long)sed->physaddr, 2107 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2108 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2109 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2110 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2111 (u_long)O32TOH(sed->ed.ed_headp), 2112 (u_long)O32TOH(sed->ed.ed_nexted)); 2113 } 2114 #endif 2115 2116 usbd_status 2117 ohci_open(usbd_pipe_handle pipe) 2118 { 2119 usbd_device_handle dev = pipe->device; 2120 ohci_softc_t *sc = dev->bus->hci_private; 2121 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2122 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2123 u_int8_t addr = dev->address; 2124 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2125 ohci_soft_ed_t *sed; 2126 ohci_soft_td_t *std; 2127 ohci_soft_itd_t *sitd; 2128 ohci_physaddr_t tdphys; 2129 u_int32_t fmt; 2130 usbd_status err = USBD_NOMEM; 2131 int ival; 2132 2133 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2134 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2135 2136 if (sc->sc_dying) { 2137 err = USBD_IOERROR; 2138 goto bad0; 2139 } 2140 2141 std = NULL; 2142 sed = NULL; 2143 2144 if (addr == sc->sc_addr) { 2145 switch (ed->bEndpointAddress) { 2146 case USB_CONTROL_ENDPOINT: 2147 pipe->methods = &ohci_root_ctrl_methods; 2148 break; 2149 case UE_DIR_IN | OHCI_INTR_ENDPT: 2150 pipe->methods = &ohci_root_intr_methods; 2151 break; 2152 default: 2153 err = USBD_INVAL; 2154 goto bad0; 2155 } 2156 } else { 2157 sed = ohci_alloc_sed(sc); 2158 if (sed == NULL) 2159 goto bad0; 2160 opipe->sed = sed; 2161 if (xfertype == UE_ISOCHRONOUS) { 2162 mutex_enter(&sc->sc_lock); 2163 sitd = ohci_alloc_sitd(sc); 2164 mutex_exit(&sc->sc_lock); 2165 if (sitd == NULL) 2166 goto bad1; 2167 opipe->tail.itd = sitd; 2168 tdphys = sitd->physaddr; 2169 fmt = OHCI_ED_FORMAT_ISO; 2170 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2171 fmt |= OHCI_ED_DIR_IN; 2172 else 2173 fmt |= OHCI_ED_DIR_OUT; 2174 } else { 2175 mutex_enter(&sc->sc_lock); 2176 std = ohci_alloc_std(sc); 2177 mutex_exit(&sc->sc_lock); 2178 if (std == NULL) 2179 goto bad1; 2180 opipe->tail.td = std; 2181 tdphys = std->physaddr; 2182 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2183 } 2184 sed->ed.ed_flags = HTOO32( 2185 OHCI_ED_SET_FA(addr) | 2186 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2187 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2188 fmt | 2189 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2190 sed->ed.ed_headp = HTOO32(tdphys | 2191 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2192 sed->ed.ed_tailp = HTOO32(tdphys); 2193 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2194 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2195 2196 switch (xfertype) { 2197 case UE_CONTROL: 2198 pipe->methods = &ohci_device_ctrl_methods; 2199 err = usb_allocmem(&sc->sc_bus, 2200 sizeof(usb_device_request_t), 2201 0, &opipe->u.ctl.reqdma); 2202 if (err) 2203 goto bad; 2204 mutex_enter(&sc->sc_lock); 2205 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2206 mutex_exit(&sc->sc_lock); 2207 break; 2208 case UE_INTERRUPT: 2209 pipe->methods = &ohci_device_intr_methods; 2210 ival = pipe->interval; 2211 if (ival == USBD_DEFAULT_INTERVAL) 2212 ival = ed->bInterval; 2213 return (ohci_device_setintr(sc, opipe, ival)); 2214 case UE_ISOCHRONOUS: 2215 pipe->methods = &ohci_device_isoc_methods; 2216 return (ohci_setup_isoc(pipe)); 2217 case UE_BULK: 2218 pipe->methods = &ohci_device_bulk_methods; 2219 mutex_enter(&sc->sc_lock); 2220 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2221 mutex_exit(&sc->sc_lock); 2222 break; 2223 } 2224 } 2225 2226 return USBD_NORMAL_COMPLETION; 2227 2228 bad: 2229 if (std != NULL) 2230 ohci_free_std(sc, std); 2231 bad1: 2232 if (sed != NULL) 2233 ohci_free_sed(sc, sed); 2234 bad0: 2235 return err; 2236 2237 } 2238 2239 /* 2240 * Close a reqular pipe. 2241 * Assumes that there are no pending transactions. 2242 */ 2243 void 2244 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2245 { 2246 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2247 ohci_softc_t *sc = pipe->device->bus->hci_private; 2248 ohci_soft_ed_t *sed = opipe->sed; 2249 2250 KASSERT(mutex_owned(&sc->sc_lock)); 2251 2252 #ifdef DIAGNOSTIC 2253 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2254 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2255 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2256 ohci_soft_td_t *std; 2257 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2258 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2259 "tl=0x%x pipe=%p, std=%p\n", sed, 2260 (int)O32TOH(sed->ed.ed_headp), 2261 (int)O32TOH(sed->ed.ed_tailp), 2262 pipe, std); 2263 #ifdef USB_DEBUG 2264 usbd_dump_pipe(&opipe->pipe); 2265 #endif 2266 #ifdef OHCI_DEBUG 2267 ohci_dump_ed(sc, sed); 2268 if (std) 2269 ohci_dump_td(sc, std); 2270 #endif 2271 usb_delay_ms(&sc->sc_bus, 2); 2272 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2273 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2274 printf("ohci_close_pipe: pipe still not empty\n"); 2275 } 2276 #endif 2277 ohci_rem_ed(sc, sed, head); 2278 /* Make sure the host controller is not touching this ED */ 2279 usb_delay_ms(&sc->sc_bus, 1); 2280 pipe->endpoint->datatoggle = 2281 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2282 ohci_free_sed(sc, opipe->sed); 2283 } 2284 2285 /* 2286 * Abort a device request. 2287 * If this routine is called at splusb() it guarantees that the request 2288 * will be removed from the hardware scheduling and that the callback 2289 * for it will be called with USBD_CANCELLED status. 2290 * It's impossible to guarantee that the requested transfer will not 2291 * have happened since the hardware runs concurrently. 2292 * If the transaction has already happened we rely on the ordinary 2293 * interrupt processing to process it. 2294 * XXX This is most probably wrong. 2295 * XXXMRG this doesn't make sense anymore. 2296 */ 2297 void 2298 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2299 { 2300 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2301 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2302 ohci_soft_ed_t *sed = opipe->sed; 2303 ohci_soft_td_t *p, *n; 2304 ohci_physaddr_t headp; 2305 int hit; 2306 int wake; 2307 2308 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2309 2310 KASSERT(mutex_owned(&sc->sc_lock)); 2311 2312 if (sc->sc_dying) { 2313 /* If we're dying, just do the software part. */ 2314 xfer->status = status; /* make software ignore it */ 2315 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2316 usb_transfer_complete(xfer); 2317 return; 2318 } 2319 2320 if (cpu_intr_p() || cpu_softintr_p()) 2321 panic("ohci_abort_xfer: not in process context"); 2322 2323 /* 2324 * If an abort is already in progress then just wait for it to 2325 * complete and return. 2326 */ 2327 if (xfer->hcflags & UXFER_ABORTING) { 2328 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2329 #ifdef DIAGNOSTIC 2330 if (status == USBD_TIMEOUT) 2331 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2332 #endif 2333 /* Override the status which might be USBD_TIMEOUT. */ 2334 xfer->status = status; 2335 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2336 xfer->hcflags |= UXFER_ABORTWAIT; 2337 while (xfer->hcflags & UXFER_ABORTING) 2338 cv_wait(&xfer->hccv, &sc->sc_lock); 2339 goto done; 2340 return; 2341 } 2342 xfer->hcflags |= UXFER_ABORTING; 2343 2344 /* 2345 * Step 1: Make interrupt routine and hardware ignore xfer. 2346 */ 2347 xfer->status = status; /* make software ignore it */ 2348 callout_stop(&xfer->timeout_handle); 2349 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2350 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2351 sizeof(sed->ed.ed_flags), 2352 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2353 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2357 2358 /* 2359 * Step 2: Wait until we know hardware has finished any possible 2360 * use of the xfer. Also make sure the soft interrupt routine 2361 * has run. 2362 */ 2363 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2364 sc->sc_softwake = 1; 2365 usb_schedsoftintr(&sc->sc_bus); 2366 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2367 2368 /* 2369 * Step 3: Remove any vestiges of the xfer from the hardware. 2370 * The complication here is that the hardware may have executed 2371 * beyond the xfer we're trying to abort. So as we're scanning 2372 * the TDs of this xfer we check if the hardware points to 2373 * any of them. 2374 */ 2375 p = xfer->hcpriv; 2376 #ifdef DIAGNOSTIC 2377 if (p == NULL) { 2378 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2379 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2380 goto done; 2381 } 2382 #endif 2383 #ifdef OHCI_DEBUG 2384 if (ohcidebug > 1) { 2385 DPRINTF(("ohci_abort_xfer: sed=\n")); 2386 ohci_dump_ed(sc, sed); 2387 ohci_dump_tds(sc, p); 2388 } 2389 #endif 2390 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2391 hit = 0; 2392 for (; p->xfer == xfer; p = n) { 2393 hit |= headp == p->physaddr; 2394 n = p->nexttd; 2395 ohci_free_std(sc, p); 2396 } 2397 /* Zap headp register if hardware pointed inside the xfer. */ 2398 if (hit) { 2399 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2400 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2401 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2402 usb_syncmem(&sed->dma, 2403 sed->offs + offsetof(ohci_ed_t, ed_headp), 2404 sizeof(sed->ed.ed_headp), 2405 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2406 } else { 2407 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2408 } 2409 2410 /* 2411 * Step 4: Turn on hardware again. 2412 */ 2413 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2414 sizeof(sed->ed.ed_flags), 2415 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2416 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2417 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2418 sizeof(sed->ed.ed_flags), 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 2421 /* 2422 * Step 5: Execute callback. 2423 */ 2424 wake = xfer->hcflags & UXFER_ABORTWAIT; 2425 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2426 usb_transfer_complete(xfer); 2427 if (wake) 2428 cv_broadcast(&xfer->hccv); 2429 2430 done: 2431 KASSERT(mutex_owned(&sc->sc_lock)); 2432 } 2433 2434 /* 2435 * Data structures and routines to emulate the root hub. 2436 */ 2437 Static usb_device_descriptor_t ohci_devd = { 2438 USB_DEVICE_DESCRIPTOR_SIZE, 2439 UDESC_DEVICE, /* type */ 2440 {0x00, 0x01}, /* USB version */ 2441 UDCLASS_HUB, /* class */ 2442 UDSUBCLASS_HUB, /* subclass */ 2443 UDPROTO_FSHUB, /* protocol */ 2444 64, /* max packet */ 2445 {0},{0},{0x00,0x01}, /* device id */ 2446 1,2,0, /* string indicies */ 2447 1 /* # of configurations */ 2448 }; 2449 2450 Static const usb_config_descriptor_t ohci_confd = { 2451 USB_CONFIG_DESCRIPTOR_SIZE, 2452 UDESC_CONFIG, 2453 {USB_CONFIG_DESCRIPTOR_SIZE + 2454 USB_INTERFACE_DESCRIPTOR_SIZE + 2455 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2456 1, 2457 1, 2458 0, 2459 UC_ATTR_MBO | UC_SELF_POWERED, 2460 0 /* max power */ 2461 }; 2462 2463 Static const usb_interface_descriptor_t ohci_ifcd = { 2464 USB_INTERFACE_DESCRIPTOR_SIZE, 2465 UDESC_INTERFACE, 2466 0, 2467 0, 2468 1, 2469 UICLASS_HUB, 2470 UISUBCLASS_HUB, 2471 UIPROTO_FSHUB, 2472 0 2473 }; 2474 2475 Static const usb_endpoint_descriptor_t ohci_endpd = { 2476 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2477 .bDescriptorType = UDESC_ENDPOINT, 2478 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2479 .bmAttributes = UE_INTERRUPT, 2480 .wMaxPacketSize = {8, 0}, /* max packet */ 2481 .bInterval = 255, 2482 }; 2483 2484 Static const usb_hub_descriptor_t ohci_hubd = { 2485 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2486 .bDescriptorType = UDESC_HUB, 2487 }; 2488 2489 /* 2490 * Simulate a hardware hub by handling all the necessary requests. 2491 */ 2492 Static usbd_status 2493 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2494 { 2495 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2496 usbd_status err; 2497 2498 /* Insert last in queue. */ 2499 mutex_enter(&sc->sc_lock); 2500 err = usb_insert_transfer(xfer); 2501 mutex_exit(&sc->sc_lock); 2502 if (err) 2503 return (err); 2504 2505 /* Pipe isn't running, start first */ 2506 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2507 } 2508 2509 Static usbd_status 2510 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2511 { 2512 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2513 usb_device_request_t *req; 2514 void *buf = NULL; 2515 int port, i; 2516 int len, value, index, l, totlen = 0; 2517 usb_port_status_t ps; 2518 usb_hub_descriptor_t hubd; 2519 usbd_status err; 2520 u_int32_t v; 2521 2522 if (sc->sc_dying) 2523 return (USBD_IOERROR); 2524 2525 #ifdef DIAGNOSTIC 2526 if (!(xfer->rqflags & URQ_REQUEST)) 2527 /* XXX panic */ 2528 return (USBD_INVAL); 2529 #endif 2530 req = &xfer->request; 2531 2532 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2533 req->bmRequestType, req->bRequest)); 2534 2535 len = UGETW(req->wLength); 2536 value = UGETW(req->wValue); 2537 index = UGETW(req->wIndex); 2538 2539 if (len != 0) 2540 buf = KERNADDR(&xfer->dmabuf, 0); 2541 2542 #define C(x,y) ((x) | ((y) << 8)) 2543 switch(C(req->bRequest, req->bmRequestType)) { 2544 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2545 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2546 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2547 /* 2548 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2549 * for the integrated root hub. 2550 */ 2551 break; 2552 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2553 if (len > 0) { 2554 *(u_int8_t *)buf = sc->sc_conf; 2555 totlen = 1; 2556 } 2557 break; 2558 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2559 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2560 if (len == 0) 2561 break; 2562 switch(value >> 8) { 2563 case UDESC_DEVICE: 2564 if ((value & 0xff) != 0) { 2565 err = USBD_IOERROR; 2566 goto ret; 2567 } 2568 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2569 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2570 memcpy(buf, &ohci_devd, l); 2571 break; 2572 case UDESC_CONFIG: 2573 if ((value & 0xff) != 0) { 2574 err = USBD_IOERROR; 2575 goto ret; 2576 } 2577 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2578 memcpy(buf, &ohci_confd, l); 2579 buf = (char *)buf + l; 2580 len -= l; 2581 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2582 totlen += l; 2583 memcpy(buf, &ohci_ifcd, l); 2584 buf = (char *)buf + l; 2585 len -= l; 2586 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2587 totlen += l; 2588 memcpy(buf, &ohci_endpd, l); 2589 break; 2590 case UDESC_STRING: 2591 #define sd ((usb_string_descriptor_t *)buf) 2592 switch (value & 0xff) { 2593 case 0: /* Language table */ 2594 totlen = usb_makelangtbl(sd, len); 2595 break; 2596 case 1: /* Vendor */ 2597 totlen = usb_makestrdesc(sd, len, 2598 sc->sc_vendor); 2599 break; 2600 case 2: /* Product */ 2601 totlen = usb_makestrdesc(sd, len, 2602 "OHCI root hub"); 2603 break; 2604 } 2605 #undef sd 2606 break; 2607 default: 2608 err = USBD_IOERROR; 2609 goto ret; 2610 } 2611 break; 2612 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2613 if (len > 0) { 2614 *(u_int8_t *)buf = 0; 2615 totlen = 1; 2616 } 2617 break; 2618 case C(UR_GET_STATUS, UT_READ_DEVICE): 2619 if (len > 1) { 2620 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2621 totlen = 2; 2622 } 2623 break; 2624 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2625 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2626 if (len > 1) { 2627 USETW(((usb_status_t *)buf)->wStatus, 0); 2628 totlen = 2; 2629 } 2630 break; 2631 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2632 if (value >= USB_MAX_DEVICES) { 2633 err = USBD_IOERROR; 2634 goto ret; 2635 } 2636 sc->sc_addr = value; 2637 break; 2638 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2639 if (value != 0 && value != 1) { 2640 err = USBD_IOERROR; 2641 goto ret; 2642 } 2643 sc->sc_conf = value; 2644 break; 2645 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2646 break; 2647 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2648 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2649 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2650 err = USBD_IOERROR; 2651 goto ret; 2652 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2653 break; 2654 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2655 break; 2656 /* Hub requests */ 2657 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2658 break; 2659 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2660 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2661 "port=%d feature=%d\n", 2662 index, value)); 2663 if (index < 1 || index > sc->sc_noport) { 2664 err = USBD_IOERROR; 2665 goto ret; 2666 } 2667 port = OHCI_RH_PORT_STATUS(index); 2668 switch(value) { 2669 case UHF_PORT_ENABLE: 2670 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2671 break; 2672 case UHF_PORT_SUSPEND: 2673 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2674 break; 2675 case UHF_PORT_POWER: 2676 /* Yes, writing to the LOW_SPEED bit clears power. */ 2677 OWRITE4(sc, port, UPS_LOW_SPEED); 2678 break; 2679 case UHF_C_PORT_CONNECTION: 2680 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2681 break; 2682 case UHF_C_PORT_ENABLE: 2683 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2684 break; 2685 case UHF_C_PORT_SUSPEND: 2686 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2687 break; 2688 case UHF_C_PORT_OVER_CURRENT: 2689 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2690 break; 2691 case UHF_C_PORT_RESET: 2692 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2693 break; 2694 default: 2695 err = USBD_IOERROR; 2696 goto ret; 2697 } 2698 switch(value) { 2699 case UHF_C_PORT_CONNECTION: 2700 case UHF_C_PORT_ENABLE: 2701 case UHF_C_PORT_SUSPEND: 2702 case UHF_C_PORT_OVER_CURRENT: 2703 case UHF_C_PORT_RESET: 2704 /* Enable RHSC interrupt if condition is cleared. */ 2705 if ((OREAD4(sc, port) >> 16) == 0) 2706 ohci_rhsc_enable(sc); 2707 break; 2708 default: 2709 break; 2710 } 2711 break; 2712 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2713 if (len == 0) 2714 break; 2715 if ((value & 0xff) != 0) { 2716 err = USBD_IOERROR; 2717 goto ret; 2718 } 2719 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2720 hubd = ohci_hubd; 2721 hubd.bNbrPorts = sc->sc_noport; 2722 USETW(hubd.wHubCharacteristics, 2723 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2724 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2725 /* XXX overcurrent */ 2726 ); 2727 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2728 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2729 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2730 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2731 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2732 l = min(len, hubd.bDescLength); 2733 totlen = l; 2734 memcpy(buf, &hubd, l); 2735 break; 2736 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2737 if (len != 4) { 2738 err = USBD_IOERROR; 2739 goto ret; 2740 } 2741 memset(buf, 0, len); /* ? XXX */ 2742 totlen = len; 2743 break; 2744 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2745 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2746 index)); 2747 if (index < 1 || index > sc->sc_noport) { 2748 err = USBD_IOERROR; 2749 goto ret; 2750 } 2751 if (len != 4) { 2752 err = USBD_IOERROR; 2753 goto ret; 2754 } 2755 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2756 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2757 v)); 2758 USETW(ps.wPortStatus, v); 2759 USETW(ps.wPortChange, v >> 16); 2760 l = min(len, sizeof ps); 2761 memcpy(buf, &ps, l); 2762 totlen = l; 2763 break; 2764 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2765 err = USBD_IOERROR; 2766 goto ret; 2767 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2768 break; 2769 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2770 if (index < 1 || index > sc->sc_noport) { 2771 err = USBD_IOERROR; 2772 goto ret; 2773 } 2774 port = OHCI_RH_PORT_STATUS(index); 2775 switch(value) { 2776 case UHF_PORT_ENABLE: 2777 OWRITE4(sc, port, UPS_PORT_ENABLED); 2778 break; 2779 case UHF_PORT_SUSPEND: 2780 OWRITE4(sc, port, UPS_SUSPEND); 2781 break; 2782 case UHF_PORT_RESET: 2783 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2784 index)); 2785 OWRITE4(sc, port, UPS_RESET); 2786 for (i = 0; i < 5; i++) { 2787 usb_delay_ms(&sc->sc_bus, 2788 USB_PORT_ROOT_RESET_DELAY); 2789 if (sc->sc_dying) { 2790 err = USBD_IOERROR; 2791 goto ret; 2792 } 2793 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2794 break; 2795 } 2796 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2797 index, OREAD4(sc, port))); 2798 break; 2799 case UHF_PORT_POWER: 2800 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2801 "%d\n", index)); 2802 OWRITE4(sc, port, UPS_PORT_POWER); 2803 break; 2804 default: 2805 err = USBD_IOERROR; 2806 goto ret; 2807 } 2808 break; 2809 default: 2810 err = USBD_IOERROR; 2811 goto ret; 2812 } 2813 xfer->actlen = totlen; 2814 err = USBD_NORMAL_COMPLETION; 2815 ret: 2816 xfer->status = err; 2817 mutex_enter(&sc->sc_lock); 2818 usb_transfer_complete(xfer); 2819 mutex_exit(&sc->sc_lock); 2820 return (USBD_IN_PROGRESS); 2821 } 2822 2823 /* Abort a root control request. */ 2824 Static void 2825 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2826 { 2827 /* Nothing to do, all transfers are synchronous. */ 2828 } 2829 2830 /* Close the root pipe. */ 2831 Static void 2832 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2833 { 2834 DPRINTF(("ohci_root_ctrl_close\n")); 2835 /* Nothing to do. */ 2836 } 2837 2838 Static usbd_status 2839 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2840 { 2841 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2842 usbd_status err; 2843 2844 /* Insert last in queue. */ 2845 mutex_enter(&sc->sc_lock); 2846 err = usb_insert_transfer(xfer); 2847 mutex_exit(&sc->sc_lock); 2848 if (err) 2849 return (err); 2850 2851 /* Pipe isn't running, start first */ 2852 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2853 } 2854 2855 Static usbd_status 2856 ohci_root_intr_start(usbd_xfer_handle xfer) 2857 { 2858 usbd_pipe_handle pipe = xfer->pipe; 2859 ohci_softc_t *sc = pipe->device->bus->hci_private; 2860 2861 if (sc->sc_dying) 2862 return (USBD_IOERROR); 2863 2864 mutex_enter(&sc->sc_lock); 2865 KASSERT(sc->sc_intrxfer == NULL); 2866 sc->sc_intrxfer = xfer; 2867 mutex_exit(&sc->sc_lock); 2868 2869 return (USBD_IN_PROGRESS); 2870 } 2871 2872 /* Abort a root interrupt request. */ 2873 Static void 2874 ohci_root_intr_abort(usbd_xfer_handle xfer) 2875 { 2876 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2877 2878 KASSERT(mutex_owned(&sc->sc_lock)); 2879 2880 if (xfer->pipe->intrxfer == xfer) { 2881 DPRINTF(("ohci_root_intr_abort: remove\n")); 2882 xfer->pipe->intrxfer = NULL; 2883 } 2884 xfer->status = USBD_CANCELLED; 2885 usb_transfer_complete(xfer); 2886 } 2887 2888 /* Close the root pipe. */ 2889 Static void 2890 ohci_root_intr_close(usbd_pipe_handle pipe) 2891 { 2892 ohci_softc_t *sc = pipe->device->bus->hci_private; 2893 2894 KASSERT(mutex_owned(&sc->sc_lock)); 2895 2896 DPRINTF(("ohci_root_intr_close\n")); 2897 2898 sc->sc_intrxfer = NULL; 2899 } 2900 2901 /************************/ 2902 2903 Static usbd_status 2904 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2905 { 2906 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2907 usbd_status err; 2908 2909 /* Insert last in queue. */ 2910 mutex_enter(&sc->sc_lock); 2911 err = usb_insert_transfer(xfer); 2912 mutex_exit(&sc->sc_lock); 2913 if (err) 2914 return (err); 2915 2916 /* Pipe isn't running, start first */ 2917 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2918 } 2919 2920 Static usbd_status 2921 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2922 { 2923 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2924 usbd_status err; 2925 2926 if (sc->sc_dying) 2927 return (USBD_IOERROR); 2928 2929 #ifdef DIAGNOSTIC 2930 if (!(xfer->rqflags & URQ_REQUEST)) { 2931 /* XXX panic */ 2932 printf("ohci_device_ctrl_transfer: not a request\n"); 2933 return (USBD_INVAL); 2934 } 2935 #endif 2936 2937 mutex_enter(&sc->sc_lock); 2938 err = ohci_device_request(xfer); 2939 mutex_exit(&sc->sc_lock); 2940 if (err) 2941 return (err); 2942 2943 if (sc->sc_bus.use_polling) 2944 ohci_waitintr(sc, xfer); 2945 return (USBD_IN_PROGRESS); 2946 } 2947 2948 /* Abort a device control request. */ 2949 Static void 2950 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2951 { 2952 #ifdef DIAGNOSTIC 2953 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2954 #endif 2955 2956 KASSERT(mutex_owned(&sc->sc_lock)); 2957 2958 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2959 ohci_abort_xfer(xfer, USBD_CANCELLED); 2960 } 2961 2962 /* Close a device control pipe. */ 2963 Static void 2964 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2965 { 2966 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2967 ohci_softc_t *sc = pipe->device->bus->hci_private; 2968 2969 KASSERT(mutex_owned(&sc->sc_lock)); 2970 2971 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2972 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2973 ohci_free_std(sc, opipe->tail.td); 2974 } 2975 2976 /************************/ 2977 2978 Static void 2979 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2980 { 2981 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2982 ohci_softc_t *sc = pipe->device->bus->hci_private; 2983 2984 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2985 } 2986 2987 Static void 2988 ohci_noop(usbd_pipe_handle pipe) 2989 { 2990 } 2991 2992 Static usbd_status 2993 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2994 { 2995 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2996 usbd_status err; 2997 2998 /* Insert last in queue. */ 2999 mutex_enter(&sc->sc_lock); 3000 err = usb_insert_transfer(xfer); 3001 mutex_exit(&sc->sc_lock); 3002 if (err) 3003 return (err); 3004 3005 /* Pipe isn't running, start first */ 3006 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3007 } 3008 3009 Static usbd_status 3010 ohci_device_bulk_start(usbd_xfer_handle xfer) 3011 { 3012 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3013 usbd_device_handle dev = opipe->pipe.device; 3014 ohci_softc_t *sc = dev->bus->hci_private; 3015 int addr = dev->address; 3016 ohci_soft_td_t *data, *tail, *tdp; 3017 ohci_soft_ed_t *sed; 3018 int len, isread, endpt; 3019 usbd_status err; 3020 3021 if (sc->sc_dying) 3022 return (USBD_IOERROR); 3023 3024 #ifdef DIAGNOSTIC 3025 if (xfer->rqflags & URQ_REQUEST) { 3026 /* XXX panic */ 3027 printf("ohci_device_bulk_start: a request\n"); 3028 return (USBD_INVAL); 3029 } 3030 #endif 3031 3032 mutex_enter(&sc->sc_lock); 3033 3034 len = xfer->length; 3035 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3036 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3037 sed = opipe->sed; 3038 3039 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3040 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3041 endpt)); 3042 3043 opipe->u.bulk.isread = isread; 3044 opipe->u.bulk.length = len; 3045 3046 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3047 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3048 /* Update device address */ 3049 sed->ed.ed_flags = HTOO32( 3050 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3051 OHCI_ED_SET_FA(addr)); 3052 3053 /* Allocate a chain of new TDs (including a new tail). */ 3054 data = opipe->tail.td; 3055 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3056 data, &tail); 3057 /* We want interrupt at the end of the transfer. */ 3058 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3059 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3060 tail->flags |= OHCI_CALL_DONE; 3061 tail = tail->nexttd; /* point at sentinel */ 3062 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3063 sizeof(tail->td.td_flags), 3064 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3065 if (err) { 3066 mutex_exit(&sc->sc_lock); 3067 return (err); 3068 } 3069 3070 tail->xfer = NULL; 3071 xfer->hcpriv = data; 3072 3073 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3074 "td_cbp=0x%08x td_be=0x%08x\n", 3075 (int)O32TOH(sed->ed.ed_flags), 3076 (int)O32TOH(data->td.td_flags), 3077 (int)O32TOH(data->td.td_cbp), 3078 (int)O32TOH(data->td.td_be))); 3079 3080 #ifdef OHCI_DEBUG 3081 if (ohcidebug > 5) { 3082 ohci_dump_ed(sc, sed); 3083 ohci_dump_tds(sc, data); 3084 } 3085 #endif 3086 3087 /* Insert ED in schedule */ 3088 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3089 tdp->xfer = xfer; 3090 } 3091 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3092 opipe->tail.td = tail; 3093 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3094 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3095 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3096 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3097 if (xfer->timeout && !sc->sc_bus.use_polling) { 3098 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3099 ohci_timeout, xfer); 3100 } 3101 mutex_exit(&sc->sc_lock); 3102 3103 #if 0 3104 /* This goes wrong if we are too slow. */ 3105 if (ohcidebug > 10) { 3106 delay(10000); 3107 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3108 OREAD4(sc, OHCI_COMMAND_STATUS))); 3109 ohci_dump_ed(sc, sed); 3110 ohci_dump_tds(sc, data); 3111 } 3112 #endif 3113 3114 return (USBD_IN_PROGRESS); 3115 } 3116 3117 Static void 3118 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3119 { 3120 #ifdef DIAGNOSTIC 3121 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3122 #endif 3123 3124 KASSERT(mutex_owned(&sc->sc_lock)); 3125 3126 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3127 ohci_abort_xfer(xfer, USBD_CANCELLED); 3128 } 3129 3130 /* 3131 * Close a device bulk pipe. 3132 */ 3133 Static void 3134 ohci_device_bulk_close(usbd_pipe_handle pipe) 3135 { 3136 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3137 ohci_softc_t *sc = pipe->device->bus->hci_private; 3138 3139 KASSERT(mutex_owned(&sc->sc_lock)); 3140 3141 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3142 ohci_close_pipe(pipe, sc->sc_bulk_head); 3143 ohci_free_std(sc, opipe->tail.td); 3144 } 3145 3146 /************************/ 3147 3148 Static usbd_status 3149 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3150 { 3151 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3152 usbd_status err; 3153 3154 /* Insert last in queue. */ 3155 mutex_enter(&sc->sc_lock); 3156 err = usb_insert_transfer(xfer); 3157 mutex_exit(&sc->sc_lock); 3158 if (err) 3159 return (err); 3160 3161 /* Pipe isn't running, start first */ 3162 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3163 } 3164 3165 Static usbd_status 3166 ohci_device_intr_start(usbd_xfer_handle xfer) 3167 { 3168 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3169 usbd_device_handle dev = opipe->pipe.device; 3170 ohci_softc_t *sc = dev->bus->hci_private; 3171 ohci_soft_ed_t *sed = opipe->sed; 3172 ohci_soft_td_t *data, *tail; 3173 int len, isread, endpt; 3174 3175 if (sc->sc_dying) 3176 return (USBD_IOERROR); 3177 3178 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3179 "flags=%d priv=%p\n", 3180 xfer, xfer->length, xfer->flags, xfer->priv)); 3181 3182 #ifdef DIAGNOSTIC 3183 if (xfer->rqflags & URQ_REQUEST) 3184 panic("ohci_device_intr_transfer: a request"); 3185 #endif 3186 3187 len = xfer->length; 3188 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3189 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3190 3191 data = opipe->tail.td; 3192 mutex_enter(&sc->sc_lock); 3193 tail = ohci_alloc_std(sc); 3194 mutex_exit(&sc->sc_lock); 3195 if (tail == NULL) 3196 return (USBD_NOMEM); 3197 tail->xfer = NULL; 3198 3199 data->td.td_flags = HTOO32( 3200 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3201 OHCI_TD_NOCC | 3202 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3203 if (xfer->flags & USBD_SHORT_XFER_OK) 3204 data->td.td_flags |= HTOO32(OHCI_TD_R); 3205 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3206 data->nexttd = tail; 3207 data->td.td_nexttd = HTOO32(tail->physaddr); 3208 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3209 data->len = len; 3210 data->xfer = xfer; 3211 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3212 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3213 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3214 xfer->hcpriv = data; 3215 3216 #ifdef OHCI_DEBUG 3217 if (ohcidebug > 5) { 3218 DPRINTF(("ohci_device_intr_transfer:\n")); 3219 ohci_dump_ed(sc, sed); 3220 ohci_dump_tds(sc, data); 3221 } 3222 #endif 3223 3224 /* Insert ED in schedule */ 3225 mutex_enter(&sc->sc_lock); 3226 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3228 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3229 opipe->tail.td = tail; 3230 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3231 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 3234 #if 0 3235 /* 3236 * This goes horribly wrong, printing thousands of descriptors, 3237 * because false references are followed due to the fact that the 3238 * TD is gone. 3239 */ 3240 if (ohcidebug > 5) { 3241 usb_delay_ms(&sc->sc_bus, 5); 3242 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3243 OREAD4(sc, OHCI_COMMAND_STATUS))); 3244 ohci_dump_ed(sc, sed); 3245 ohci_dump_tds(sc, data); 3246 } 3247 #endif 3248 mutex_exit(&sc->sc_lock); 3249 3250 return (USBD_IN_PROGRESS); 3251 } 3252 3253 /* Abort a device control request. */ 3254 Static void 3255 ohci_device_intr_abort(usbd_xfer_handle xfer) 3256 { 3257 #ifdef DIAGNOSTIC 3258 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3259 #endif 3260 3261 KASSERT(mutex_owned(&sc->sc_lock)); 3262 3263 if (xfer->pipe->intrxfer == xfer) { 3264 DPRINTF(("ohci_device_intr_abort: remove\n")); 3265 xfer->pipe->intrxfer = NULL; 3266 } 3267 ohci_abort_xfer(xfer, USBD_CANCELLED); 3268 } 3269 3270 /* Close a device interrupt pipe. */ 3271 Static void 3272 ohci_device_intr_close(usbd_pipe_handle pipe) 3273 { 3274 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3275 ohci_softc_t *sc = pipe->device->bus->hci_private; 3276 int nslots = opipe->u.intr.nslots; 3277 int pos = opipe->u.intr.pos; 3278 int j; 3279 ohci_soft_ed_t *p, *sed = opipe->sed; 3280 3281 KASSERT(mutex_owned(&sc->sc_lock)); 3282 3283 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3284 pipe, nslots, pos)); 3285 usb_syncmem(&sed->dma, sed->offs, 3286 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3287 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3288 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3289 sizeof(sed->ed.ed_flags), 3290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3291 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3292 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3293 usb_delay_ms(&sc->sc_bus, 2); 3294 3295 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3296 continue; 3297 #ifdef DIAGNOSTIC 3298 if (p == NULL) 3299 panic("ohci_device_intr_close: ED not found"); 3300 #endif 3301 p->next = sed->next; 3302 p->ed.ed_nexted = sed->ed.ed_nexted; 3303 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3304 sizeof(p->ed.ed_nexted), 3305 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3306 3307 for (j = 0; j < nslots; j++) 3308 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3309 3310 ohci_free_std(sc, opipe->tail.td); 3311 ohci_free_sed(sc, opipe->sed); 3312 } 3313 3314 Static usbd_status 3315 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3316 { 3317 int i, j, best; 3318 u_int npoll, slow, shigh, nslots; 3319 u_int bestbw, bw; 3320 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3321 3322 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3323 if (ival == 0) { 3324 printf("ohci_setintr: 0 interval\n"); 3325 return (USBD_INVAL); 3326 } 3327 3328 npoll = OHCI_NO_INTRS; 3329 while (npoll > ival) 3330 npoll /= 2; 3331 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3332 3333 /* 3334 * We now know which level in the tree the ED must go into. 3335 * Figure out which slot has most bandwidth left over. 3336 * Slots to examine: 3337 * npoll 3338 * 1 0 3339 * 2 1 2 3340 * 4 3 4 5 6 3341 * 8 7 8 9 10 11 12 13 14 3342 * N (N-1) .. (N-1+N-1) 3343 */ 3344 slow = npoll-1; 3345 shigh = slow + npoll; 3346 nslots = OHCI_NO_INTRS / npoll; 3347 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3348 bw = 0; 3349 for (j = 0; j < nslots; j++) 3350 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3351 if (bw < bestbw) { 3352 best = i; 3353 bestbw = bw; 3354 } 3355 } 3356 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3357 best, slow, shigh, bestbw)); 3358 3359 mutex_enter(&sc->sc_lock); 3360 hsed = sc->sc_eds[best]; 3361 sed->next = hsed->next; 3362 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3363 sizeof(hsed->ed.ed_flags), 3364 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3365 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3366 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3367 sizeof(sed->ed.ed_flags), 3368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3369 hsed->next = sed; 3370 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3371 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3372 sizeof(hsed->ed.ed_flags), 3373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3374 mutex_exit(&sc->sc_lock); 3375 3376 for (j = 0; j < nslots; j++) 3377 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3378 opipe->u.intr.nslots = nslots; 3379 opipe->u.intr.pos = best; 3380 3381 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3382 return (USBD_NORMAL_COMPLETION); 3383 } 3384 3385 /***********************/ 3386 3387 usbd_status 3388 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3389 { 3390 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3391 usbd_status err; 3392 3393 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3394 3395 /* Put it on our queue, */ 3396 mutex_enter(&sc->sc_lock); 3397 err = usb_insert_transfer(xfer); 3398 mutex_exit(&sc->sc_lock); 3399 3400 /* bail out on error, */ 3401 if (err && err != USBD_IN_PROGRESS) 3402 return (err); 3403 3404 /* XXX should check inuse here */ 3405 3406 /* insert into schedule, */ 3407 ohci_device_isoc_enter(xfer); 3408 3409 /* and start if the pipe wasn't running */ 3410 if (!err) 3411 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3412 3413 return (err); 3414 } 3415 3416 void 3417 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3418 { 3419 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3420 usbd_device_handle dev = opipe->pipe.device; 3421 ohci_softc_t *sc = dev->bus->hci_private; 3422 ohci_soft_ed_t *sed = opipe->sed; 3423 struct iso *iso = &opipe->u.iso; 3424 ohci_soft_itd_t *sitd, *nsitd; 3425 ohci_physaddr_t buf, offs, noffs, bp0; 3426 int i, ncur, nframes; 3427 3428 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3429 "nframes=%d\n", 3430 iso->inuse, iso->next, xfer, xfer->nframes)); 3431 3432 if (sc->sc_dying) 3433 return; 3434 3435 if (iso->next == -1) { 3436 /* Not in use yet, schedule it a few frames ahead. */ 3437 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3438 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3439 iso->next)); 3440 } 3441 3442 sitd = opipe->tail.itd; 3443 buf = DMAADDR(&xfer->dmabuf, 0); 3444 bp0 = OHCI_PAGE(buf); 3445 offs = OHCI_PAGE_OFFSET(buf); 3446 nframes = xfer->nframes; 3447 xfer->hcpriv = sitd; 3448 for (i = ncur = 0; i < nframes; i++, ncur++) { 3449 noffs = offs + xfer->frlengths[i]; 3450 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3451 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3452 3453 /* Allocate next ITD */ 3454 mutex_enter(&sc->sc_lock); 3455 nsitd = ohci_alloc_sitd(sc); 3456 mutex_exit(&sc->sc_lock); 3457 if (nsitd == NULL) { 3458 /* XXX what now? */ 3459 printf("%s: isoc TD alloc failed\n", 3460 device_xname(sc->sc_dev)); 3461 return; 3462 } 3463 3464 /* Fill current ITD */ 3465 sitd->itd.itd_flags = HTOO32( 3466 OHCI_ITD_NOCC | 3467 OHCI_ITD_SET_SF(iso->next) | 3468 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3469 OHCI_ITD_SET_FC(ncur)); 3470 sitd->itd.itd_bp0 = HTOO32(bp0); 3471 sitd->nextitd = nsitd; 3472 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3473 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3474 sitd->xfer = xfer; 3475 sitd->flags = 0; 3476 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3477 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3478 3479 sitd = nsitd; 3480 iso->next = iso->next + ncur; 3481 bp0 = OHCI_PAGE(buf + offs); 3482 ncur = 0; 3483 } 3484 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3485 offs = noffs; 3486 } 3487 mutex_enter(&sc->sc_lock); 3488 nsitd = ohci_alloc_sitd(sc); 3489 mutex_exit(&sc->sc_lock); 3490 if (nsitd == NULL) { 3491 /* XXX what now? */ 3492 printf("%s: isoc TD alloc failed\n", 3493 device_xname(sc->sc_dev)); 3494 return; 3495 } 3496 /* Fixup last used ITD */ 3497 sitd->itd.itd_flags = HTOO32( 3498 OHCI_ITD_NOCC | 3499 OHCI_ITD_SET_SF(iso->next) | 3500 OHCI_ITD_SET_DI(0) | 3501 OHCI_ITD_SET_FC(ncur)); 3502 sitd->itd.itd_bp0 = HTOO32(bp0); 3503 sitd->nextitd = nsitd; 3504 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3505 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3506 sitd->xfer = xfer; 3507 sitd->flags = OHCI_CALL_DONE; 3508 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3510 3511 iso->next = iso->next + ncur; 3512 iso->inuse += nframes; 3513 3514 xfer->actlen = offs; /* XXX pretend we did it all */ 3515 3516 xfer->status = USBD_IN_PROGRESS; 3517 3518 #ifdef OHCI_DEBUG 3519 if (ohcidebug > 5) { 3520 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3521 O32TOH(sc->sc_hcca->hcca_frame_number))); 3522 ohci_dump_itds(sc, xfer->hcpriv); 3523 ohci_dump_ed(sc, sed); 3524 } 3525 #endif 3526 3527 mutex_enter(&sc->sc_lock); 3528 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3529 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3530 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3531 opipe->tail.itd = nsitd; 3532 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3533 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3534 sizeof(sed->ed.ed_flags), 3535 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3536 mutex_exit(&sc->sc_lock); 3537 3538 #ifdef OHCI_DEBUG 3539 if (ohcidebug > 5) { 3540 delay(150000); 3541 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3542 O32TOH(sc->sc_hcca->hcca_frame_number))); 3543 ohci_dump_itds(sc, xfer->hcpriv); 3544 ohci_dump_ed(sc, sed); 3545 } 3546 #endif 3547 } 3548 3549 usbd_status 3550 ohci_device_isoc_start(usbd_xfer_handle xfer) 3551 { 3552 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3553 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3554 3555 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3556 3557 mutex_enter(&sc->sc_lock); 3558 3559 if (sc->sc_dying) { 3560 mutex_exit(&sc->sc_lock); 3561 return (USBD_IOERROR); 3562 } 3563 3564 #ifdef DIAGNOSTIC 3565 if (xfer->status != USBD_IN_PROGRESS) 3566 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3567 #endif 3568 3569 /* XXX anything to do? */ 3570 3571 mutex_exit(&sc->sc_lock); 3572 3573 return (USBD_IN_PROGRESS); 3574 } 3575 3576 void 3577 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3578 { 3579 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3580 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3581 ohci_soft_ed_t *sed; 3582 ohci_soft_itd_t *sitd; 3583 3584 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3585 3586 KASSERT(mutex_owned(&sc->sc_lock)); 3587 3588 /* Transfer is already done. */ 3589 if (xfer->status != USBD_NOT_STARTED && 3590 xfer->status != USBD_IN_PROGRESS) { 3591 printf("ohci_device_isoc_abort: early return\n"); 3592 goto done; 3593 } 3594 3595 /* Give xfer the requested abort code. */ 3596 xfer->status = USBD_CANCELLED; 3597 3598 sed = opipe->sed; 3599 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3600 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3601 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3602 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3603 sizeof(sed->ed.ed_flags), 3604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3605 3606 sitd = xfer->hcpriv; 3607 #ifdef DIAGNOSTIC 3608 if (sitd == NULL) { 3609 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3610 goto done; 3611 } 3612 #endif 3613 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3614 #ifdef DIAGNOSTIC 3615 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3616 sitd->isdone = 1; 3617 #endif 3618 } 3619 3620 /* XXXMRG is this ok? */ 3621 mutex_exit(&sc->sc_lock); 3622 3623 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3624 3625 mutex_enter(&sc->sc_lock); 3626 3627 /* Run callback. */ 3628 usb_transfer_complete(xfer); 3629 3630 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3631 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3632 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3633 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3634 3635 done: 3636 KASSERT(mutex_owned(&sc->sc_lock)); 3637 } 3638 3639 void 3640 ohci_device_isoc_done(usbd_xfer_handle xfer) 3641 { 3642 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3643 } 3644 3645 usbd_status 3646 ohci_setup_isoc(usbd_pipe_handle pipe) 3647 { 3648 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3649 ohci_softc_t *sc = pipe->device->bus->hci_private; 3650 struct iso *iso = &opipe->u.iso; 3651 3652 iso->next = -1; 3653 iso->inuse = 0; 3654 3655 mutex_enter(&sc->sc_lock); 3656 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3657 mutex_exit(&sc->sc_lock); 3658 3659 return (USBD_NORMAL_COMPLETION); 3660 } 3661 3662 void 3663 ohci_device_isoc_close(usbd_pipe_handle pipe) 3664 { 3665 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3666 ohci_softc_t *sc = pipe->device->bus->hci_private; 3667 3668 KASSERT(mutex_owned(&sc->sc_lock)); 3669 3670 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3671 ohci_close_pipe(pipe, sc->sc_isoc_head); 3672 #ifdef DIAGNOSTIC 3673 opipe->tail.itd->isdone = 1; 3674 #endif 3675 ohci_free_sitd(sc, opipe->tail.itd); 3676 } 3677
Indexes created Fri Oct 03 02:09:57 GMT 2025