ohci.c revision 1.218.6.2.2.5
1 /* $NetBSD: ohci.c,v 1.218.6.2.2.5 2011/12/08 09:36:49 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005, 2011 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green. 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.218.6.2.2.5 2011/12/08 09:36:49 mrg Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kmem.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 58 #include <sys/bus.h> 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/ohcireg.h> 68 #include <dev/usb/ohcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 72 73 #ifdef OHCI_DEBUG 74 #define DPRINTF(x) if (ohcidebug) printf x 75 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 76 int ohcidebug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n,x) 80 #endif 81 82 #if BYTE_ORDER == BIG_ENDIAN 83 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 84 #else 85 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 86 #endif 87 88 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 89 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 90 #define HTOO16(val) O16TOH(val) 91 #define HTOO32(val) O32TOH(val) 92 93 struct ohci_pipe; 94 95 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 96 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 97 98 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 99 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 100 101 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 102 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 103 104 #if 0 105 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 106 ohci_soft_td_t *); 107 #endif 108 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 109 ohci_softc_t *, int, int, usbd_xfer_handle, 110 ohci_soft_td_t *, ohci_soft_td_t **); 111 112 Static usbd_status ohci_open(usbd_pipe_handle); 113 Static void ohci_poll(struct usbd_bus *); 114 Static void ohci_softintr(void *); 115 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 116 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 117 Static void ohci_rhsc_softint(void *arg); 118 119 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 120 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 121 ohci_soft_ed_t *); 122 123 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 124 ohci_soft_ed_t *); 125 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 126 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 127 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 128 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 129 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 130 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 131 132 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 133 Static void ohci_device_isoc_enter(usbd_xfer_handle); 134 135 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 136 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 137 138 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 139 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 140 Static void ohci_get_locks(struct usbd_bus *, kmutex_t **, 141 kmutex_t **); 142 143 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 145 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 146 Static void ohci_root_ctrl_close(usbd_pipe_handle); 147 Static void ohci_root_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 151 Static void ohci_root_intr_abort(usbd_xfer_handle); 152 Static void ohci_root_intr_close(usbd_pipe_handle); 153 Static void ohci_root_intr_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 157 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 158 Static void ohci_device_ctrl_close(usbd_pipe_handle); 159 Static void ohci_device_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 163 Static void ohci_device_bulk_abort(usbd_xfer_handle); 164 Static void ohci_device_bulk_close(usbd_pipe_handle); 165 Static void ohci_device_bulk_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 169 Static void ohci_device_intr_abort(usbd_xfer_handle); 170 Static void ohci_device_intr_close(usbd_pipe_handle); 171 Static void ohci_device_intr_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 174 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 175 Static void ohci_device_isoc_abort(usbd_xfer_handle); 176 Static void ohci_device_isoc_close(usbd_pipe_handle); 177 Static void ohci_device_isoc_done(usbd_xfer_handle); 178 179 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 180 struct ohci_pipe *pipe, int ival); 181 182 Static void ohci_timeout(void *); 183 Static void ohci_timeout_task(void *); 184 Static void ohci_rhsc_enable(void *); 185 186 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 187 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 188 189 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 190 Static void ohci_noop(usbd_pipe_handle pipe); 191 192 #ifdef OHCI_DEBUG 193 Static void ohci_dumpregs(ohci_softc_t *); 194 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 195 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 196 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 197 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 198 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 199 #endif 200 201 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 202 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 203 #define OWRITE1(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 #define OWRITE2(sc, r, x) \ 206 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 207 #define OWRITE4(sc, r, x) \ 208 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 209 static __inline uint8_t 210 OREAD1(ohci_softc_t *sc, bus_size_t r) 211 { 212 213 OBARR(sc); 214 return bus_space_read_1(sc->iot, sc->ioh, r); 215 } 216 217 static __inline uint16_t 218 OREAD2(ohci_softc_t *sc, bus_size_t r) 219 { 220 221 OBARR(sc); 222 return bus_space_read_2(sc->iot, sc->ioh, r); 223 } 224 225 static __inline uint32_t 226 OREAD4(ohci_softc_t *sc, bus_size_t r) 227 { 228 229 OBARR(sc); 230 return bus_space_read_4(sc->iot, sc->ioh, r); 231 } 232 233 /* Reverse the bits in a value 0 .. 31 */ 234 Static u_int8_t revbits[OHCI_NO_INTRS] = 235 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 236 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 237 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 238 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 239 240 struct ohci_pipe { 241 struct usbd_pipe pipe; 242 ohci_soft_ed_t *sed; 243 union { 244 ohci_soft_td_t *td; 245 ohci_soft_itd_t *itd; 246 } tail; 247 /* Info needed for different pipe kinds. */ 248 union { 249 /* Control pipe */ 250 struct { 251 usb_dma_t reqdma; 252 u_int length; 253 ohci_soft_td_t *setup, *data, *stat; 254 } ctl; 255 /* Interrupt pipe */ 256 struct { 257 int nslots; 258 int pos; 259 } intr; 260 /* Bulk pipe */ 261 struct { 262 u_int length; 263 int isread; 264 } bulk; 265 /* Iso pipe */ 266 struct iso { 267 int next, inuse; 268 } iso; 269 } u; 270 }; 271 272 #define OHCI_INTR_ENDPT 1 273 274 Static const struct usbd_bus_methods ohci_bus_methods = { 275 .open_pipe = ohci_open, 276 .soft_intr = ohci_softintr, 277 .do_poll = ohci_poll, 278 .allocm = ohci_allocm, 279 .freem = ohci_freem, 280 .allocx = ohci_allocx, 281 .freex = ohci_freex, 282 .get_locks = ohci_get_locks, 283 }; 284 285 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 286 .transfer = ohci_root_ctrl_transfer, 287 .start = ohci_root_ctrl_start, 288 .abort = ohci_root_ctrl_abort, 289 .close = ohci_root_ctrl_close, 290 .cleartoggle = ohci_noop, 291 .done = ohci_root_ctrl_done, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .transfer = ohci_root_intr_transfer, 296 .start = ohci_root_intr_start, 297 .abort = ohci_root_intr_abort, 298 .close = ohci_root_intr_close, 299 .cleartoggle = ohci_noop, 300 .done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .transfer = ohci_device_ctrl_transfer, 305 .start = ohci_device_ctrl_start, 306 .abort = ohci_device_ctrl_abort, 307 .close = ohci_device_ctrl_close, 308 .cleartoggle = ohci_noop, 309 .done = ohci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 313 .transfer = ohci_device_intr_transfer, 314 .start = ohci_device_intr_start, 315 .abort = ohci_device_intr_abort, 316 .close = ohci_device_intr_close, 317 .cleartoggle = ohci_device_clear_toggle, 318 .done = ohci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 322 .transfer = ohci_device_bulk_transfer, 323 .start = ohci_device_bulk_start, 324 .abort = ohci_device_bulk_abort, 325 .close = ohci_device_bulk_close, 326 .cleartoggle = ohci_device_clear_toggle, 327 .done = ohci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 331 .transfer = ohci_device_isoc_transfer, 332 .start = ohci_device_isoc_start, 333 .abort = ohci_device_isoc_abort, 334 .close = ohci_device_isoc_close, 335 .cleartoggle = ohci_noop, 336 .done = ohci_device_isoc_done, 337 }; 338 339 int 340 ohci_activate(device_t self, enum devact act) 341 { 342 struct ohci_softc *sc = device_private(self); 343 344 switch (act) { 345 case DVACT_DEACTIVATE: 346 sc->sc_dying = 1; 347 return 0; 348 default: 349 return EOPNOTSUPP; 350 } 351 } 352 353 void 354 ohci_childdet(device_t self, device_t child) 355 { 356 struct ohci_softc *sc = device_private(self); 357 358 KASSERT(sc->sc_child == child); 359 sc->sc_child = NULL; 360 } 361 362 int 363 ohci_detach(struct ohci_softc *sc, int flags) 364 { 365 int rv = 0; 366 usbd_xfer_handle xfer; 367 368 if (sc->sc_child != NULL) 369 rv = config_detach(sc->sc_child, flags); 370 371 if (rv != 0) 372 return (rv); 373 374 callout_stop(&sc->sc_tmo_rhsc); 375 376 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 377 callout_destroy(&sc->sc_tmo_rhsc); 378 379 softint_disestablish(sc->sc_rhsc_si); 380 381 cv_destroy(&sc->sc_softwake_cv); 382 383 mutex_destroy(&sc->sc_lock); 384 mutex_destroy(&sc->sc_intr_lock); 385 386 if (sc->sc_hcca != NULL) 387 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 388 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 389 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 390 kmem_free(xfer, sizeof(struct ohci_xfer)); 391 } 392 393 return (rv); 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 if (sc->sc_freeeds == NULL) { 405 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 406 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 407 OHCI_ED_ALIGN, &dma); 408 if (err) 409 return (0); 410 for(i = 0; i < OHCI_SED_CHUNK; i++) { 411 offs = i * OHCI_SED_SIZE; 412 sed = KERNADDR(&dma, offs); 413 sed->physaddr = DMAADDR(&dma, offs); 414 sed->dma = dma; 415 sed->offs = offs; 416 sed->next = sc->sc_freeeds; 417 sc->sc_freeeds = sed; 418 } 419 } 420 sed = sc->sc_freeeds; 421 sc->sc_freeeds = sed->next; 422 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 423 sed->next = 0; 424 return (sed); 425 } 426 427 void 428 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 429 { 430 sed->next = sc->sc_freeeds; 431 sc->sc_freeeds = sed; 432 } 433 434 ohci_soft_td_t * 435 ohci_alloc_std(ohci_softc_t *sc) 436 { 437 ohci_soft_td_t *std; 438 usbd_status err; 439 int i, offs; 440 usb_dma_t dma; 441 442 if (sc->sc_freetds == NULL) { 443 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 444 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 445 OHCI_TD_ALIGN, &dma); 446 if (err) 447 return (NULL); 448 for(i = 0; i < OHCI_STD_CHUNK; i++) { 449 offs = i * OHCI_STD_SIZE; 450 std = KERNADDR(&dma, offs); 451 std->physaddr = DMAADDR(&dma, offs); 452 std->dma = dma; 453 std->offs = offs; 454 std->nexttd = sc->sc_freetds; 455 sc->sc_freetds = std; 456 } 457 } 458 459 std = sc->sc_freetds; 460 sc->sc_freetds = std->nexttd; 461 memset(&std->td, 0, sizeof(ohci_td_t)); 462 std->nexttd = NULL; 463 std->xfer = NULL; 464 ohci_hash_add_td(sc, std); 465 466 return (std); 467 } 468 469 void 470 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 471 { 472 473 ohci_hash_rem_td(sc, std); 474 std->nexttd = sc->sc_freetds; 475 sc->sc_freetds = std; 476 } 477 478 usbd_status 479 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 480 int alen, int rd, usbd_xfer_handle xfer, 481 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 482 { 483 ohci_soft_td_t *next, *cur; 484 ohci_physaddr_t dataphys, dataphysend; 485 u_int32_t tdflags; 486 int len, curlen; 487 usb_dma_t *dma = &xfer->dmabuf; 488 u_int16_t flags = xfer->flags; 489 490 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 491 492 KASSERT(mutex_owned(&sc->sc_lock)); 493 494 len = alen; 495 cur = sp; 496 dataphys = DMAADDR(dma, 0); 497 dataphysend = OHCI_PAGE(dataphys + len - 1); 498 usb_syncmem(dma, 0, len, 499 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 500 tdflags = HTOO32( 501 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 502 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 503 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 504 505 for (;;) { 506 next = ohci_alloc_std(sc); 507 if (next == NULL) 508 goto nomem; 509 510 /* The OHCI hardware can handle at most one page crossing. */ 511 if (OHCI_PAGE(dataphys) == dataphysend || 512 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 513 /* we can handle it in this TD */ 514 curlen = len; 515 } else { 516 /* must use multiple TDs, fill as much as possible. */ 517 curlen = 2 * OHCI_PAGE_SIZE - 518 (dataphys & (OHCI_PAGE_SIZE-1)); 519 /* the length must be a multiple of the max size */ 520 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 521 #ifdef DIAGNOSTIC 522 if (curlen == 0) 523 panic("ohci_alloc_std: curlen == 0"); 524 #endif 525 } 526 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 527 "dataphysend=0x%08x len=%d curlen=%d\n", 528 dataphys, dataphysend, 529 len, curlen)); 530 len -= curlen; 531 532 cur->td.td_flags = tdflags; 533 cur->td.td_cbp = HTOO32(dataphys); 534 cur->nexttd = next; 535 cur->td.td_nexttd = HTOO32(next->physaddr); 536 cur->td.td_be = HTOO32(dataphys + curlen - 1); 537 cur->len = curlen; 538 cur->flags = OHCI_ADD_LEN; 539 cur->xfer = xfer; 540 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 541 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 542 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 543 dataphys, dataphys + curlen - 1)); 544 if (len == 0) 545 break; 546 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 547 dataphys += curlen; 548 cur = next; 549 } 550 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 551 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 552 /* Force a 0 length transfer at the end. */ 553 554 cur = next; 555 next = ohci_alloc_std(sc); 556 if (next == NULL) 557 goto nomem; 558 559 cur->td.td_flags = tdflags; 560 cur->td.td_cbp = 0; /* indicate 0 length packet */ 561 cur->nexttd = next; 562 cur->td.td_nexttd = HTOO32(next->physaddr); 563 cur->td.td_be = ~0; 564 cur->len = 0; 565 cur->flags = 0; 566 cur->xfer = xfer; 567 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 569 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 570 } 571 *ep = cur; 572 573 return (USBD_NORMAL_COMPLETION); 574 575 nomem: 576 /* XXX free chain */ 577 return (USBD_NOMEM); 578 } 579 580 #if 0 581 Static void 582 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 583 ohci_soft_td_t *stdend) 584 { 585 ohci_soft_td_t *p; 586 587 for (; std != stdend; std = p) { 588 p = std->nexttd; 589 ohci_free_std(sc, std); 590 } 591 } 592 #endif 593 594 ohci_soft_itd_t * 595 ohci_alloc_sitd(ohci_softc_t *sc) 596 { 597 ohci_soft_itd_t *sitd; 598 usbd_status err; 599 int i, offs; 600 usb_dma_t dma; 601 602 if (sc->sc_freeitds == NULL) { 603 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 604 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 605 OHCI_ITD_ALIGN, &dma); 606 if (err) 607 return (NULL); 608 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 609 offs = i * OHCI_SITD_SIZE; 610 sitd = KERNADDR(&dma, offs); 611 sitd->physaddr = DMAADDR(&dma, offs); 612 sitd->dma = dma; 613 sitd->offs = offs; 614 sitd->nextitd = sc->sc_freeitds; 615 sc->sc_freeitds = sitd; 616 } 617 } 618 619 sitd = sc->sc_freeitds; 620 sc->sc_freeitds = sitd->nextitd; 621 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 622 sitd->nextitd = NULL; 623 sitd->xfer = NULL; 624 ohci_hash_add_itd(sc, sitd); 625 626 #ifdef DIAGNOSTIC 627 sitd->isdone = 0; 628 #endif 629 630 return (sitd); 631 } 632 633 void 634 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 635 { 636 637 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 638 639 #ifdef DIAGNOSTIC 640 if (!sitd->isdone) { 641 panic("ohci_free_sitd: sitd=%p not done", sitd); 642 return; 643 } 644 /* Warn double free */ 645 sitd->isdone = 0; 646 #endif 647 648 ohci_hash_rem_itd(sc, sitd); 649 sitd->nextitd = sc->sc_freeitds; 650 sc->sc_freeitds = sitd; 651 } 652 653 usbd_status 654 ohci_init(ohci_softc_t *sc) 655 { 656 ohci_soft_ed_t *sed, *psed; 657 usbd_status err; 658 int i; 659 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 660 661 DPRINTF(("ohci_init: start\n")); 662 aprint_normal_dev(sc->sc_dev, ""); 663 664 sc->sc_hcca = NULL; 665 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 666 667 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 668 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 669 cv_init(&sc->sc_softwake_cv, "ohciab"); 670 671 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 672 ohci_rhsc_softint, sc); 673 674 for (i = 0; i < OHCI_HASH_SIZE; i++) 675 LIST_INIT(&sc->sc_hash_tds[i]); 676 for (i = 0; i < OHCI_HASH_SIZE; i++) 677 LIST_INIT(&sc->sc_hash_itds[i]); 678 679 SIMPLEQ_INIT(&sc->sc_free_xfers); 680 681 rev = OREAD4(sc, OHCI_REVISION); 682 aprint_normal("OHCI version %d.%d%s\n", 683 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 684 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 685 686 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 687 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 688 sc->sc_bus.usbrev = USBREV_UNKNOWN; 689 return (USBD_INVAL); 690 } 691 sc->sc_bus.usbrev = USBREV_1_0; 692 693 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 694 USB_MEM_RESERVE); 695 696 /* XXX determine alignment by R/W */ 697 /* Allocate the HCCA area. */ 698 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 699 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 700 if (err) { 701 sc->sc_hcca = NULL; 702 return err; 703 } 704 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 705 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 706 707 sc->sc_eintrs = OHCI_NORMAL_INTRS; 708 709 /* Allocate dummy ED that starts the control list. */ 710 sc->sc_ctrl_head = ohci_alloc_sed(sc); 711 if (sc->sc_ctrl_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad1; 714 } 715 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 717 /* Allocate dummy ED that starts the bulk list. */ 718 sc->sc_bulk_head = ohci_alloc_sed(sc); 719 if (sc->sc_bulk_head == NULL) { 720 err = USBD_NOMEM; 721 goto bad2; 722 } 723 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 724 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 725 sizeof(sc->sc_bulk_head->ed), 726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 727 728 /* Allocate dummy ED that starts the isochronous list. */ 729 sc->sc_isoc_head = ohci_alloc_sed(sc); 730 if (sc->sc_isoc_head == NULL) { 731 err = USBD_NOMEM; 732 goto bad3; 733 } 734 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 735 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 736 sizeof(sc->sc_isoc_head->ed), 737 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 738 739 /* Allocate all the dummy EDs that make up the interrupt tree. */ 740 for (i = 0; i < OHCI_NO_EDS; i++) { 741 sed = ohci_alloc_sed(sc); 742 if (sed == NULL) { 743 while (--i >= 0) 744 ohci_free_sed(sc, sc->sc_eds[i]); 745 err = USBD_NOMEM; 746 goto bad4; 747 } 748 /* All ED fields are set to 0. */ 749 sc->sc_eds[i] = sed; 750 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 751 if (i != 0) 752 psed = sc->sc_eds[(i-1) / 2]; 753 else 754 psed= sc->sc_isoc_head; 755 sed->next = psed; 756 sed->ed.ed_nexted = HTOO32(psed->physaddr); 757 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 758 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 759 } 760 /* 761 * Fill HCCA interrupt table. The bit reversal is to get 762 * the tree set up properly to spread the interrupts. 763 */ 764 for (i = 0; i < OHCI_NO_INTRS; i++) 765 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 766 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 767 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 769 770 #ifdef OHCI_DEBUG 771 if (ohcidebug > 15) { 772 for (i = 0; i < OHCI_NO_EDS; i++) { 773 printf("ed#%d ", i); 774 ohci_dump_ed(sc, sc->sc_eds[i]); 775 } 776 printf("iso "); 777 ohci_dump_ed(sc, sc->sc_isoc_head); 778 } 779 #endif 780 781 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 782 ctl = OREAD4(sc, OHCI_CONTROL); 783 rwc = ctl & OHCI_RWC; 784 fm = OREAD4(sc, OHCI_FM_INTERVAL); 785 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 786 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 787 788 /* Determine in what context we are running. */ 789 if (ctl & OHCI_IR) { 790 /* SMM active, request change */ 791 DPRINTF(("ohci_init: SMM active, request owner change\n")); 792 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 793 (OHCI_OC | OHCI_MIE)) 794 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 795 s = OREAD4(sc, OHCI_COMMAND_STATUS); 796 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 797 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 798 usb_delay_ms(&sc->sc_bus, 1); 799 ctl = OREAD4(sc, OHCI_CONTROL); 800 } 801 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 802 if ((ctl & OHCI_IR) == 0) { 803 aprint_error_dev(sc->sc_dev, 804 "SMM does not respond, resetting\n"); 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 806 goto reset; 807 } 808 #if 0 809 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 810 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 811 /* BIOS started controller. */ 812 DPRINTF(("ohci_init: BIOS active\n")); 813 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 814 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 815 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 816 } 817 #endif 818 } else { 819 DPRINTF(("ohci_init: cold started\n")); 820 reset: 821 /* Controller was cold started. */ 822 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 823 } 824 825 /* 826 * This reset should not be necessary according to the OHCI spec, but 827 * without it some controllers do not start. 828 */ 829 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 830 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 831 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 832 833 /* We now own the host controller and the bus has been reset. */ 834 835 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 836 /* Nominal time for a reset is 10 us. */ 837 for (i = 0; i < 10; i++) { 838 delay(10); 839 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 840 if (!hcr) 841 break; 842 } 843 if (hcr) { 844 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 845 err = USBD_IOERROR; 846 goto bad5; 847 } 848 #ifdef OHCI_DEBUG 849 if (ohcidebug > 15) 850 ohci_dumpregs(sc); 851 #endif 852 853 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 854 855 /* Set up HC registers. */ 856 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 857 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 858 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 859 /* disable all interrupts and then switch on all desired interrupts */ 860 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 861 /* switch on desired functional features */ 862 ctl = OREAD4(sc, OHCI_CONTROL); 863 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 864 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 865 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 866 /* And finally start it! */ 867 OWRITE4(sc, OHCI_CONTROL, ctl); 868 869 /* 870 * The controller is now OPERATIONAL. Set a some final 871 * registers that should be set earlier, but that the 872 * controller ignores when in the SUSPEND state. 873 */ 874 ival = OHCI_GET_IVAL(fm); 875 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 876 fm |= OHCI_FSMPS(ival) | ival; 877 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 878 per = OHCI_PERIODIC(ival); /* 90% periodic */ 879 OWRITE4(sc, OHCI_PERIODIC_START, per); 880 881 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 882 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 883 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 884 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 885 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 886 887 /* 888 * The AMD756 requires a delay before re-reading the register, 889 * otherwise it will occasionally report 0 ports. 890 */ 891 sc->sc_noport = 0; 892 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 893 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 894 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 895 } 896 897 #ifdef OHCI_DEBUG 898 if (ohcidebug > 5) 899 ohci_dumpregs(sc); 900 #endif 901 902 /* Set up the bus struct. */ 903 sc->sc_bus.methods = &ohci_bus_methods; 904 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 905 906 sc->sc_control = sc->sc_intre = 0; 907 908 /* Finally, turn on interrupts. */ 909 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 910 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 911 912 return (USBD_NORMAL_COMPLETION); 913 914 bad5: 915 for (i = 0; i < OHCI_NO_EDS; i++) 916 ohci_free_sed(sc, sc->sc_eds[i]); 917 bad4: 918 ohci_free_sed(sc, sc->sc_isoc_head); 919 bad3: 920 ohci_free_sed(sc, sc->sc_bulk_head); 921 bad2: 922 ohci_free_sed(sc, sc->sc_ctrl_head); 923 bad1: 924 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 925 sc->sc_hcca = NULL; 926 return (err); 927 } 928 929 usbd_status 930 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 931 { 932 struct ohci_softc *sc = bus->hci_private; 933 usbd_status status; 934 935 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 936 if (status == USBD_NOMEM) 937 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 938 return status; 939 } 940 941 void 942 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 943 { 944 struct ohci_softc *sc = bus->hci_private; 945 if (dma->block->flags & USB_DMA_RESERVE) { 946 usb_reserve_freem(&sc->sc_dma_reserve, dma); 947 return; 948 } 949 usb_freemem(&sc->sc_bus, dma); 950 } 951 952 usbd_xfer_handle 953 ohci_allocx(struct usbd_bus *bus) 954 { 955 struct ohci_softc *sc = bus->hci_private; 956 usbd_xfer_handle xfer; 957 958 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 959 if (xfer != NULL) { 960 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 961 #ifdef DIAGNOSTIC 962 if (xfer->busy_free != XFER_FREE) { 963 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 964 xfer->busy_free); 965 } 966 #endif 967 } else { 968 xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP); 969 } 970 if (xfer != NULL) { 971 memset(xfer, 0, sizeof (struct ohci_xfer)); 972 #ifdef DIAGNOSTIC 973 xfer->busy_free = XFER_BUSY; 974 #endif 975 } 976 return (xfer); 977 } 978 979 void 980 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 981 { 982 struct ohci_softc *sc = bus->hci_private; 983 984 #ifdef DIAGNOSTIC 985 if (xfer->busy_free != XFER_BUSY) { 986 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 987 xfer->busy_free); 988 } 989 xfer->busy_free = XFER_FREE; 990 #endif 991 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 992 } 993 994 Static void 995 ohci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread) 996 { 997 struct ohci_softc *sc = bus->hci_private; 998 999 *intr = &sc->sc_intr_lock; 1000 *thread = &sc->sc_lock; 1001 } 1002 1003 /* 1004 * Shut down the controller when the system is going down. 1005 */ 1006 bool 1007 ohci_shutdown(device_t self, int flags) 1008 { 1009 ohci_softc_t *sc = device_private(self); 1010 1011 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1012 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1013 return true; 1014 } 1015 1016 bool 1017 ohci_resume(device_t dv, const pmf_qual_t *qual) 1018 { 1019 ohci_softc_t *sc = device_private(dv); 1020 uint32_t ctl; 1021 1022 mutex_spin_enter(&sc->sc_intr_lock); 1023 sc->sc_bus.use_polling++; 1024 mutex_spin_exit(&sc->sc_intr_lock); 1025 1026 /* Some broken BIOSes do not recover these values */ 1027 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1028 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1029 sc->sc_ctrl_head->physaddr); 1030 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1031 sc->sc_bulk_head->physaddr); 1032 if (sc->sc_intre) 1033 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1034 (OHCI_ALL_INTRS | OHCI_MIE)); 1035 if (sc->sc_control) 1036 ctl = sc->sc_control; 1037 else 1038 ctl = OREAD4(sc, OHCI_CONTROL); 1039 ctl |= OHCI_HCFS_RESUME; 1040 OWRITE4(sc, OHCI_CONTROL, ctl); 1041 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1042 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1043 OWRITE4(sc, OHCI_CONTROL, ctl); 1044 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1045 sc->sc_control = sc->sc_intre = 0; 1046 1047 mutex_spin_enter(&sc->sc_intr_lock); 1048 sc->sc_bus.use_polling--; 1049 mutex_spin_exit(&sc->sc_intr_lock); 1050 1051 return true; 1052 } 1053 1054 bool 1055 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1056 { 1057 ohci_softc_t *sc = device_private(dv); 1058 uint32_t ctl; 1059 1060 mutex_spin_enter(&sc->sc_intr_lock); 1061 sc->sc_bus.use_polling++; 1062 mutex_spin_exit(&sc->sc_intr_lock); 1063 1064 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1065 if (sc->sc_control == 0) { 1066 /* 1067 * Preserve register values, in case that BIOS 1068 * does not recover them. 1069 */ 1070 sc->sc_control = ctl; 1071 sc->sc_intre = OREAD4(sc, 1072 OHCI_INTERRUPT_ENABLE); 1073 } 1074 ctl |= OHCI_HCFS_SUSPEND; 1075 OWRITE4(sc, OHCI_CONTROL, ctl); 1076 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1077 1078 mutex_spin_enter(&sc->sc_intr_lock); 1079 sc->sc_bus.use_polling--; 1080 mutex_spin_exit(&sc->sc_intr_lock); 1081 1082 return true; 1083 } 1084 1085 #ifdef OHCI_DEBUG 1086 void 1087 ohci_dumpregs(ohci_softc_t *sc) 1088 { 1089 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1090 OREAD4(sc, OHCI_REVISION), 1091 OREAD4(sc, OHCI_CONTROL), 1092 OREAD4(sc, OHCI_COMMAND_STATUS))); 1093 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1094 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1095 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1096 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1097 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1098 OREAD4(sc, OHCI_HCCA), 1099 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1100 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1101 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1102 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1103 OREAD4(sc, OHCI_BULK_HEAD_ED), 1104 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1105 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1106 OREAD4(sc, OHCI_DONE_HEAD), 1107 OREAD4(sc, OHCI_FM_INTERVAL), 1108 OREAD4(sc, OHCI_FM_REMAINING))); 1109 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1110 OREAD4(sc, OHCI_FM_NUMBER), 1111 OREAD4(sc, OHCI_PERIODIC_START), 1112 OREAD4(sc, OHCI_LS_THRESHOLD))); 1113 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1114 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1115 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1116 OREAD4(sc, OHCI_RH_STATUS))); 1117 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1118 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1119 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1120 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1121 O32TOH(sc->sc_hcca->hcca_frame_number), 1122 O32TOH(sc->sc_hcca->hcca_done_head))); 1123 } 1124 #endif 1125 1126 Static int ohci_intr1(ohci_softc_t *); 1127 1128 int 1129 ohci_intr(void *p) 1130 { 1131 ohci_softc_t *sc = p; 1132 int ret = 0; 1133 1134 if (sc == NULL) 1135 return (0); 1136 1137 mutex_spin_enter(&sc->sc_intr_lock); 1138 1139 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1140 goto done; 1141 1142 /* If we get an interrupt while polling, then just ignore it. */ 1143 if (sc->sc_bus.use_polling) { 1144 #ifdef DIAGNOSTIC 1145 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1146 #endif 1147 /* for level triggered intrs, should do something to ack */ 1148 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1149 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1150 1151 goto done; 1152 } 1153 1154 ret = ohci_intr1(sc); 1155 1156 done: 1157 mutex_spin_exit(&sc->sc_intr_lock); 1158 return ret; 1159 } 1160 1161 Static int 1162 ohci_intr1(ohci_softc_t *sc) 1163 { 1164 u_int32_t intrs, eintrs; 1165 1166 DPRINTFN(14,("ohci_intr1: enter\n")); 1167 1168 /* In case the interrupt occurs before initialization has completed. */ 1169 if (sc == NULL || sc->sc_hcca == NULL) { 1170 #ifdef DIAGNOSTIC 1171 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1172 #endif 1173 return (0); 1174 } 1175 1176 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1177 1178 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1179 if (!intrs) 1180 return (0); 1181 1182 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1183 eintrs = intrs & sc->sc_eintrs; 1184 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1185 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1186 (u_int)eintrs, sc->sc_eintrs)); 1187 1188 if (!eintrs) { 1189 return (0); 1190 } 1191 1192 sc->sc_bus.intr_context++; 1193 sc->sc_bus.no_intrs++; 1194 if (eintrs & OHCI_SO) { 1195 sc->sc_overrun_cnt++; 1196 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1197 printf("%s: %u scheduling overruns\n", 1198 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1199 sc->sc_overrun_cnt = 0; 1200 } 1201 /* XXX do what */ 1202 eintrs &= ~OHCI_SO; 1203 } 1204 if (eintrs & OHCI_WDH) { 1205 /* 1206 * We block the interrupt below, and reenable it later from 1207 * ohci_softintr(). 1208 */ 1209 usb_schedsoftintr(&sc->sc_bus); 1210 } 1211 if (eintrs & OHCI_RD) { 1212 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1213 /* XXX process resume detect */ 1214 } 1215 if (eintrs & OHCI_UE) { 1216 printf("%s: unrecoverable error, controller halted\n", 1217 device_xname(sc->sc_dev)); 1218 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1219 /* XXX what else */ 1220 } 1221 if (eintrs & OHCI_RHSC) { 1222 /* 1223 * We block the interrupt below, and reenable it later from 1224 * a timeout. 1225 */ 1226 softint_schedule(sc->sc_rhsc_si); 1227 } 1228 1229 sc->sc_bus.intr_context--; 1230 1231 if (eintrs != 0) { 1232 /* Block unprocessed interrupts. */ 1233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1234 sc->sc_eintrs &= ~eintrs; 1235 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1236 device_xname(sc->sc_dev), eintrs)); 1237 } 1238 1239 return (1); 1240 } 1241 1242 void 1243 ohci_rhsc_enable(void *v_sc) 1244 { 1245 ohci_softc_t *sc = v_sc; 1246 1247 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1248 mutex_spin_enter(&sc->sc_intr_lock); 1249 sc->sc_eintrs |= OHCI_RHSC; 1250 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1251 mutex_spin_exit(&sc->sc_intr_lock); 1252 } 1253 1254 #ifdef OHCI_DEBUG 1255 const char *ohci_cc_strs[] = { 1256 "NO_ERROR", 1257 "CRC", 1258 "BIT_STUFFING", 1259 "DATA_TOGGLE_MISMATCH", 1260 "STALL", 1261 "DEVICE_NOT_RESPONDING", 1262 "PID_CHECK_FAILURE", 1263 "UNEXPECTED_PID", 1264 "DATA_OVERRUN", 1265 "DATA_UNDERRUN", 1266 "BUFFER_OVERRUN", 1267 "BUFFER_UNDERRUN", 1268 "reserved", 1269 "reserved", 1270 "NOT_ACCESSED", 1271 "NOT_ACCESSED", 1272 }; 1273 #endif 1274 1275 void 1276 ohci_softintr(void *v) 1277 { 1278 struct usbd_bus *bus = v; 1279 ohci_softc_t *sc = bus->hci_private; 1280 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1281 ohci_soft_td_t *std, *sdone, *stdnext; 1282 usbd_xfer_handle xfer; 1283 struct ohci_pipe *opipe; 1284 int len, cc; 1285 int i, j, actlen, iframes, uedir; 1286 ohci_physaddr_t done; 1287 1288 DPRINTFN(10,("ohci_softintr: enter\n")); 1289 1290 mutex_enter(&sc->sc_lock); 1291 1292 sc->sc_bus.intr_context++; 1293 1294 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1295 sizeof(sc->sc_hcca->hcca_done_head), 1296 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1297 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1298 sc->sc_hcca->hcca_done_head = 0; 1299 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1300 sizeof(sc->sc_hcca->hcca_done_head), 1301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1302 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1303 sc->sc_eintrs |= OHCI_WDH; 1304 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1305 1306 /* Reverse the done list. */ 1307 for (sdone = NULL, sidone = NULL; done != 0; ) { 1308 std = ohci_hash_find_td(sc, done); 1309 if (std != NULL) { 1310 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1312 std->dnext = sdone; 1313 done = O32TOH(std->td.td_nexttd); 1314 sdone = std; 1315 DPRINTFN(10,("add TD %p\n", std)); 1316 continue; 1317 } 1318 sitd = ohci_hash_find_itd(sc, done); 1319 if (sitd != NULL) { 1320 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1322 sitd->dnext = sidone; 1323 done = O32TOH(sitd->itd.itd_nextitd); 1324 sidone = sitd; 1325 DPRINTFN(5,("add ITD %p\n", sitd)); 1326 continue; 1327 } 1328 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1329 (u_long)done); 1330 break; 1331 } 1332 1333 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1334 1335 #ifdef OHCI_DEBUG 1336 if (ohcidebug > 10) { 1337 DPRINTF(("ohci_process_done: TD done:\n")); 1338 ohci_dump_tds(sc, sdone); 1339 } 1340 #endif 1341 1342 for (std = sdone; std; std = stdnext) { 1343 xfer = std->xfer; 1344 stdnext = std->dnext; 1345 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1346 std, xfer, xfer ? xfer->hcpriv : 0)); 1347 if (xfer == NULL) { 1348 /* 1349 * xfer == NULL: There seems to be no xfer associated 1350 * with this TD. It is tailp that happened to end up on 1351 * the done queue. 1352 * Shouldn't happen, but some chips are broken(?). 1353 */ 1354 continue; 1355 } 1356 if (xfer->status == USBD_CANCELLED || 1357 xfer->status == USBD_TIMEOUT) { 1358 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1359 xfer)); 1360 /* Handled by abort routine. */ 1361 continue; 1362 } 1363 callout_stop(&xfer->timeout_handle); 1364 1365 len = std->len; 1366 if (std->td.td_cbp != 0) 1367 len -= O32TOH(std->td.td_be) - 1368 O32TOH(std->td.td_cbp) + 1; 1369 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1370 std->flags)); 1371 if (std->flags & OHCI_ADD_LEN) 1372 xfer->actlen += len; 1373 1374 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1375 if (cc == OHCI_CC_NO_ERROR) { 1376 if (std->flags & OHCI_CALL_DONE) { 1377 xfer->status = USBD_NORMAL_COMPLETION; 1378 usb_transfer_complete(xfer); 1379 } 1380 ohci_free_std(sc, std); 1381 } else { 1382 /* 1383 * Endpoint is halted. First unlink all the TDs 1384 * belonging to the failed transfer, and then restart 1385 * the endpoint. 1386 */ 1387 ohci_soft_td_t *p, *n; 1388 opipe = (struct ohci_pipe *)xfer->pipe; 1389 1390 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1391 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1392 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1393 1394 /* remove TDs */ 1395 for (p = std; p->xfer == xfer; p = n) { 1396 n = p->nexttd; 1397 ohci_free_std(sc, p); 1398 } 1399 1400 /* clear halt */ 1401 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1402 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1403 1404 if (cc == OHCI_CC_STALL) 1405 xfer->status = USBD_STALLED; 1406 else 1407 xfer->status = USBD_IOERROR; 1408 usb_transfer_complete(xfer); 1409 } 1410 } 1411 1412 #ifdef OHCI_DEBUG 1413 if (ohcidebug > 10) { 1414 DPRINTF(("ohci_softintr: ITD done:\n")); 1415 ohci_dump_itds(sc, sidone); 1416 } 1417 #endif 1418 1419 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1420 xfer = sitd->xfer; 1421 sitdnext = sitd->dnext; 1422 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1423 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1424 if (xfer == NULL) 1425 continue; 1426 if (xfer->status == USBD_CANCELLED || 1427 xfer->status == USBD_TIMEOUT) { 1428 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1429 xfer)); 1430 /* Handled by abort routine. */ 1431 continue; 1432 } 1433 #ifdef DIAGNOSTIC 1434 if (sitd->isdone) 1435 printf("ohci_softintr: sitd=%p is done\n", sitd); 1436 sitd->isdone = 1; 1437 #endif 1438 if (sitd->flags & OHCI_CALL_DONE) { 1439 ohci_soft_itd_t *next; 1440 1441 opipe = (struct ohci_pipe *)xfer->pipe; 1442 opipe->u.iso.inuse -= xfer->nframes; 1443 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1444 bEndpointAddress); 1445 xfer->status = USBD_NORMAL_COMPLETION; 1446 actlen = 0; 1447 for (i = 0, sitd = xfer->hcpriv;; 1448 sitd = next) { 1449 next = sitd->nextitd; 1450 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1451 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1452 xfer->status = USBD_IOERROR; 1453 /* For input, update frlengths with actual */ 1454 /* XXX anything necessary for output? */ 1455 if (uedir == UE_DIR_IN && 1456 xfer->status == USBD_NORMAL_COMPLETION) { 1457 iframes = OHCI_ITD_GET_FC(O32TOH( 1458 sitd->itd.itd_flags)); 1459 for (j = 0; j < iframes; i++, j++) { 1460 len = O16TOH(sitd-> 1461 itd.itd_offset[j]); 1462 if ((OHCI_ITD_PSW_GET_CC(len) & 1463 OHCI_CC_NOT_ACCESSED_MASK) 1464 == OHCI_CC_NOT_ACCESSED) 1465 len = 0; 1466 else 1467 len = OHCI_ITD_PSW_LENGTH(len); 1468 xfer->frlengths[i] = len; 1469 actlen += len; 1470 } 1471 } 1472 if (sitd->flags & OHCI_CALL_DONE) 1473 break; 1474 ohci_free_sitd(sc, sitd); 1475 } 1476 ohci_free_sitd(sc, sitd); 1477 if (uedir == UE_DIR_IN && 1478 xfer->status == USBD_NORMAL_COMPLETION) 1479 xfer->actlen = actlen; 1480 xfer->hcpriv = NULL; 1481 1482 usb_transfer_complete(xfer); 1483 } 1484 } 1485 1486 if (sc->sc_softwake) { 1487 sc->sc_softwake = 0; 1488 cv_broadcast(&sc->sc_softwake_cv); 1489 } 1490 1491 sc->sc_bus.intr_context--; 1492 mutex_exit(&sc->sc_lock); 1493 1494 DPRINTFN(10,("ohci_softintr: done:\n")); 1495 } 1496 1497 void 1498 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1499 { 1500 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1501 #ifdef DIAGNOSTIC 1502 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1503 #endif 1504 int len = UGETW(xfer->request.wLength); 1505 int isread = (xfer->request.bmRequestType & UT_READ); 1506 1507 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1508 1509 KASSERT(mutex_owned(&sc->sc_lock)); 1510 1511 #ifdef DIAGNOSTIC 1512 if (!(xfer->rqflags & URQ_REQUEST)) { 1513 panic("ohci_device_ctrl_done: not a request"); 1514 } 1515 #endif 1516 if (len) 1517 usb_syncmem(&xfer->dmabuf, 0, len, 1518 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1519 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1520 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1521 } 1522 1523 void 1524 ohci_device_intr_done(usbd_xfer_handle xfer) 1525 { 1526 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1527 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1528 ohci_soft_ed_t *sed = opipe->sed; 1529 ohci_soft_td_t *data, *tail; 1530 int isread = 1531 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1532 1533 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1534 xfer, xfer->actlen)); 1535 1536 KASSERT(mutex_owned(&sc->sc_lock)); 1537 1538 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1539 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1540 if (xfer->pipe->repeat) { 1541 data = opipe->tail.td; 1542 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1543 if (tail == NULL) { 1544 xfer->status = USBD_NOMEM; 1545 return; 1546 } 1547 tail->xfer = NULL; 1548 1549 data->td.td_flags = HTOO32( 1550 OHCI_TD_IN | OHCI_TD_NOCC | 1551 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1552 if (xfer->flags & USBD_SHORT_XFER_OK) 1553 data->td.td_flags |= HTOO32(OHCI_TD_R); 1554 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1555 data->nexttd = tail; 1556 data->td.td_nexttd = HTOO32(tail->physaddr); 1557 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1558 xfer->length - 1); 1559 data->len = xfer->length; 1560 data->xfer = xfer; 1561 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1562 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1564 xfer->hcpriv = data; 1565 xfer->actlen = 0; 1566 1567 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1568 usb_syncmem(&sed->dma, 1569 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1570 sizeof(sed->ed.ed_tailp), 1571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1572 opipe->tail.td = tail; 1573 } 1574 } 1575 1576 void 1577 ohci_device_bulk_done(usbd_xfer_handle xfer) 1578 { 1579 #ifdef DIAGNOSTIC 1580 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1581 #endif 1582 int isread = 1583 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1584 1585 KASSERT(mutex_owned(&sc->sc_lock)); 1586 1587 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1588 xfer, xfer->actlen)); 1589 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1590 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1591 } 1592 1593 Static void 1594 ohci_rhsc_softint(void *arg) 1595 { 1596 ohci_softc_t *sc = arg; 1597 1598 mutex_enter(&sc->sc_lock); 1599 1600 ohci_rhsc(sc, sc->sc_intrxfer); 1601 1602 /* Do not allow RHSC interrupts > 1 per second */ 1603 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1604 1605 mutex_exit(&sc->sc_lock); 1606 } 1607 1608 void 1609 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1610 { 1611 usbd_pipe_handle pipe; 1612 u_char *p; 1613 int i, m; 1614 int hstatus; 1615 1616 KASSERT(mutex_owned(&sc->sc_lock)); 1617 1618 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1619 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1620 sc, xfer, hstatus)); 1621 1622 if (xfer == NULL) { 1623 /* Just ignore the change. */ 1624 return; 1625 } 1626 1627 pipe = xfer->pipe; 1628 1629 p = KERNADDR(&xfer->dmabuf, 0); 1630 m = min(sc->sc_noport, xfer->length * 8 - 1); 1631 memset(p, 0, xfer->length); 1632 for (i = 1; i <= m; i++) { 1633 /* Pick out CHANGE bits from the status reg. */ 1634 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1635 p[i/8] |= 1 << (i%8); 1636 } 1637 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1638 xfer->actlen = xfer->length; 1639 xfer->status = USBD_NORMAL_COMPLETION; 1640 1641 usb_transfer_complete(xfer); 1642 } 1643 1644 void 1645 ohci_root_intr_done(usbd_xfer_handle xfer) 1646 { 1647 } 1648 1649 void 1650 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1651 { 1652 } 1653 1654 /* 1655 * Wait here until controller claims to have an interrupt. 1656 * Then call ohci_intr and return. Use timeout to avoid waiting 1657 * too long. 1658 */ 1659 void 1660 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1661 { 1662 int timo; 1663 u_int32_t intrs; 1664 1665 mutex_enter(&sc->sc_lock); 1666 1667 xfer->status = USBD_IN_PROGRESS; 1668 for (timo = xfer->timeout; timo >= 0; timo--) { 1669 usb_delay_ms(&sc->sc_bus, 1); 1670 if (sc->sc_dying) 1671 break; 1672 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1673 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1674 #ifdef OHCI_DEBUG 1675 if (ohcidebug > 15) 1676 ohci_dumpregs(sc); 1677 #endif 1678 if (intrs) { 1679 mutex_spin_enter(&sc->sc_intr_lock); 1680 ohci_intr1(sc); 1681 mutex_spin_exit(&sc->sc_intr_lock); 1682 if (xfer->status != USBD_IN_PROGRESS) 1683 return; 1684 } 1685 } 1686 1687 /* Timeout */ 1688 DPRINTF(("ohci_waitintr: timeout\n")); 1689 xfer->status = USBD_TIMEOUT; 1690 usb_transfer_complete(xfer); 1691 1692 /* XXX should free TD */ 1693 1694 mutex_exit(&sc->sc_lock); 1695 } 1696 1697 void 1698 ohci_poll(struct usbd_bus *bus) 1699 { 1700 ohci_softc_t *sc = bus->hci_private; 1701 #ifdef OHCI_DEBUG 1702 static int last; 1703 int new; 1704 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1705 if (new != last) { 1706 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1707 last = new; 1708 } 1709 #endif 1710 1711 sc->sc_eintrs |= OHCI_WDH; 1712 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1713 mutex_spin_enter(&sc->sc_intr_lock); 1714 ohci_intr1(sc); 1715 mutex_spin_exit(&sc->sc_intr_lock); 1716 } 1717 } 1718 1719 usbd_status 1720 ohci_device_request(usbd_xfer_handle xfer) 1721 { 1722 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1723 usb_device_request_t *req = &xfer->request; 1724 usbd_device_handle dev = opipe->pipe.device; 1725 ohci_softc_t *sc = dev->bus->hci_private; 1726 int addr = dev->address; 1727 ohci_soft_td_t *setup, *stat, *next, *tail; 1728 ohci_soft_ed_t *sed; 1729 int isread; 1730 int len; 1731 usbd_status err; 1732 1733 KASSERT(mutex_owned(&sc->sc_lock)); 1734 1735 isread = req->bmRequestType & UT_READ; 1736 len = UGETW(req->wLength); 1737 1738 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1739 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1740 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1741 UGETW(req->wIndex), len, addr, 1742 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1743 1744 setup = opipe->tail.td; 1745 stat = ohci_alloc_std(sc); 1746 if (stat == NULL) { 1747 err = USBD_NOMEM; 1748 goto bad1; 1749 } 1750 tail = ohci_alloc_std(sc); 1751 if (tail == NULL) { 1752 err = USBD_NOMEM; 1753 goto bad2; 1754 } 1755 tail->xfer = NULL; 1756 1757 sed = opipe->sed; 1758 opipe->u.ctl.length = len; 1759 1760 /* Update device address and length since they may have changed 1761 during the setup of the control pipe in usbd_new_device(). */ 1762 /* XXX This only needs to be done once, but it's too early in open. */ 1763 /* XXXX Should not touch ED here! */ 1764 1765 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1766 sizeof(sed->ed.ed_flags), 1767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1768 sed->ed.ed_flags = HTOO32( 1769 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1770 OHCI_ED_SET_FA(addr) | 1771 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1772 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1773 sizeof(sed->ed.ed_flags), 1774 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1775 1776 next = stat; 1777 1778 /* Set up data transaction */ 1779 if (len != 0) { 1780 ohci_soft_td_t *std = stat; 1781 1782 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1783 std, &stat); 1784 stat = stat->nexttd; /* point at free TD */ 1785 if (err) 1786 goto bad3; 1787 /* Start toggle at 1 and then use the carried toggle. */ 1788 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1789 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1790 usb_syncmem(&std->dma, 1791 std->offs + offsetof(ohci_td_t, td_flags), 1792 sizeof(std->td.td_flags), 1793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1794 } 1795 1796 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1797 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1798 1799 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1800 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1801 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1802 setup->nexttd = next; 1803 setup->td.td_nexttd = HTOO32(next->physaddr); 1804 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1805 setup->len = 0; 1806 setup->xfer = xfer; 1807 setup->flags = 0; 1808 xfer->hcpriv = setup; 1809 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1811 1812 stat->td.td_flags = HTOO32( 1813 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1814 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1815 stat->td.td_cbp = 0; 1816 stat->nexttd = tail; 1817 stat->td.td_nexttd = HTOO32(tail->physaddr); 1818 stat->td.td_be = 0; 1819 stat->flags = OHCI_CALL_DONE; 1820 stat->len = 0; 1821 stat->xfer = xfer; 1822 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1823 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1824 1825 #ifdef OHCI_DEBUG 1826 if (ohcidebug > 5) { 1827 DPRINTF(("ohci_device_request:\n")); 1828 ohci_dump_ed(sc, sed); 1829 ohci_dump_tds(sc, setup); 1830 } 1831 #endif 1832 1833 /* Insert ED in schedule */ 1834 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1835 usb_syncmem(&sed->dma, 1836 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1837 sizeof(sed->ed.ed_tailp), 1838 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1839 opipe->tail.td = tail; 1840 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1841 if (xfer->timeout && !sc->sc_bus.use_polling) { 1842 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1843 ohci_timeout, xfer); 1844 } 1845 1846 #ifdef OHCI_DEBUG 1847 if (ohcidebug > 20) { 1848 delay(10000); 1849 DPRINTF(("ohci_device_request: status=%x\n", 1850 OREAD4(sc, OHCI_COMMAND_STATUS))); 1851 ohci_dumpregs(sc); 1852 printf("ctrl head:\n"); 1853 ohci_dump_ed(sc, sc->sc_ctrl_head); 1854 printf("sed:\n"); 1855 ohci_dump_ed(sc, sed); 1856 ohci_dump_tds(sc, setup); 1857 } 1858 #endif 1859 1860 return (USBD_NORMAL_COMPLETION); 1861 1862 bad3: 1863 ohci_free_std(sc, tail); 1864 bad2: 1865 ohci_free_std(sc, stat); 1866 bad1: 1867 return (err); 1868 } 1869 1870 /* 1871 * Add an ED to the schedule. Called at splusb(). 1872 */ 1873 Static void 1874 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1875 { 1876 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1877 1878 KASSERT(mutex_owned(&sc->sc_lock)); 1879 1880 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1881 sizeof(head->ed.ed_nexted), 1882 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1883 sed->next = head->next; 1884 sed->ed.ed_nexted = head->ed.ed_nexted; 1885 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1886 sizeof(sed->ed.ed_nexted), 1887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1888 head->next = sed; 1889 head->ed.ed_nexted = HTOO32(sed->physaddr); 1890 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1891 sizeof(head->ed.ed_nexted), 1892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1893 } 1894 1895 /* 1896 * Remove an ED from the schedule. Called at splusb(). 1897 */ 1898 Static void 1899 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1900 { 1901 ohci_soft_ed_t *p; 1902 1903 KASSERT(mutex_owned(&sc->sc_lock)); 1904 1905 /* XXX */ 1906 for (p = head; p != NULL && p->next != sed; p = p->next) 1907 ; 1908 if (p == NULL) 1909 panic("ohci_rem_ed: ED not found"); 1910 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1911 sizeof(sed->ed.ed_nexted), 1912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1913 p->next = sed->next; 1914 p->ed.ed_nexted = sed->ed.ed_nexted; 1915 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1916 sizeof(p->ed.ed_nexted), 1917 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1918 } 1919 1920 /* 1921 * When a transfer is completed the TD is added to the done queue by 1922 * the host controller. This queue is the processed by software. 1923 * Unfortunately the queue contains the physical address of the TD 1924 * and we have no simple way to translate this back to a kernel address. 1925 * To make the translation possible (and fast) we use a hash table of 1926 * TDs currently in the schedule. The physical address is used as the 1927 * hash value. 1928 */ 1929 1930 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1931 /* Called at splusb() */ 1932 void 1933 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1934 { 1935 int h = HASH(std->physaddr); 1936 1937 KASSERT(mutex_owned(&sc->sc_lock)); 1938 1939 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1940 } 1941 1942 /* Called at splusb() */ 1943 void 1944 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1945 { 1946 1947 KASSERT(mutex_owned(&sc->sc_lock)); 1948 1949 LIST_REMOVE(std, hnext); 1950 } 1951 1952 ohci_soft_td_t * 1953 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1954 { 1955 int h = HASH(a); 1956 ohci_soft_td_t *std; 1957 1958 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1959 std != NULL; 1960 std = LIST_NEXT(std, hnext)) 1961 if (std->physaddr == a) 1962 return (std); 1963 return (NULL); 1964 } 1965 1966 /* Called at splusb() */ 1967 void 1968 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1969 { 1970 int h = HASH(sitd->physaddr); 1971 1972 KASSERT(1 || mutex_owned(&sc->sc_lock)); 1973 1974 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1975 sitd, (u_long)sitd->physaddr)); 1976 1977 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1978 } 1979 1980 /* Called at splusb() */ 1981 void 1982 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1983 { 1984 KASSERT(1 || mutex_owned(&sc->sc_lock)); 1985 1986 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1987 sitd, (u_long)sitd->physaddr)); 1988 1989 LIST_REMOVE(sitd, hnext); 1990 } 1991 1992 ohci_soft_itd_t * 1993 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1994 { 1995 int h = HASH(a); 1996 ohci_soft_itd_t *sitd; 1997 1998 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1999 sitd != NULL; 2000 sitd = LIST_NEXT(sitd, hnext)) 2001 if (sitd->physaddr == a) 2002 return (sitd); 2003 return (NULL); 2004 } 2005 2006 void 2007 ohci_timeout(void *addr) 2008 { 2009 struct ohci_xfer *oxfer = addr; 2010 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2011 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2012 2013 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2014 2015 if (sc->sc_dying) { 2016 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2017 return; 2018 } 2019 2020 /* Execute the abort in a process context. */ 2021 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 2022 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2023 USB_TASKQ_HC); 2024 } 2025 2026 void 2027 ohci_timeout_task(void *addr) 2028 { 2029 usbd_xfer_handle xfer = addr; 2030 2031 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2032 2033 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2034 } 2035 2036 #ifdef OHCI_DEBUG 2037 void 2038 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2039 { 2040 for (; std; std = std->nexttd) 2041 ohci_dump_td(sc, std); 2042 } 2043 2044 void 2045 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2046 { 2047 char sbuf[128]; 2048 2049 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2050 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2051 snprintb(sbuf, sizeof(sbuf), 2052 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2053 (u_int32_t)O32TOH(std->td.td_flags)); 2054 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2055 "nexttd=0x%08lx be=0x%08lx\n", 2056 std, (u_long)std->physaddr, sbuf, 2057 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2058 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2059 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2060 (u_long)O32TOH(std->td.td_cbp), 2061 (u_long)O32TOH(std->td.td_nexttd), 2062 (u_long)O32TOH(std->td.td_be)); 2063 } 2064 2065 void 2066 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2067 { 2068 int i; 2069 2070 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2071 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2072 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2073 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2074 sitd, (u_long)sitd->physaddr, 2075 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2076 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2077 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2078 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2079 (u_long)O32TOH(sitd->itd.itd_bp0), 2080 (u_long)O32TOH(sitd->itd.itd_nextitd), 2081 (u_long)O32TOH(sitd->itd.itd_be)); 2082 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2083 printf("offs[%d]=0x%04x ", i, 2084 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2085 printf("\n"); 2086 } 2087 2088 void 2089 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2090 { 2091 for (; sitd; sitd = sitd->nextitd) 2092 ohci_dump_itd(sc, sitd); 2093 } 2094 2095 void 2096 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2097 { 2098 char sbuf[128], sbuf2[128]; 2099 2100 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2101 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2102 snprintb(sbuf, sizeof(sbuf), 2103 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2104 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2105 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2106 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2107 2108 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2109 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2110 sed, (u_long)sed->physaddr, 2111 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2112 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2113 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2114 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2115 (u_long)O32TOH(sed->ed.ed_headp), 2116 (u_long)O32TOH(sed->ed.ed_nexted)); 2117 } 2118 #endif 2119 2120 usbd_status 2121 ohci_open(usbd_pipe_handle pipe) 2122 { 2123 usbd_device_handle dev = pipe->device; 2124 ohci_softc_t *sc = dev->bus->hci_private; 2125 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2126 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2127 u_int8_t addr = dev->address; 2128 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2129 ohci_soft_ed_t *sed; 2130 ohci_soft_td_t *std; 2131 ohci_soft_itd_t *sitd; 2132 ohci_physaddr_t tdphys; 2133 u_int32_t fmt; 2134 usbd_status err = USBD_NOMEM; 2135 int ival; 2136 2137 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2138 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2139 2140 if (sc->sc_dying) { 2141 err = USBD_IOERROR; 2142 goto bad0; 2143 } 2144 2145 std = NULL; 2146 sed = NULL; 2147 2148 if (addr == sc->sc_addr) { 2149 switch (ed->bEndpointAddress) { 2150 case USB_CONTROL_ENDPOINT: 2151 pipe->methods = &ohci_root_ctrl_methods; 2152 break; 2153 case UE_DIR_IN | OHCI_INTR_ENDPT: 2154 pipe->methods = &ohci_root_intr_methods; 2155 break; 2156 default: 2157 err = USBD_INVAL; 2158 goto bad0; 2159 } 2160 } else { 2161 sed = ohci_alloc_sed(sc); 2162 if (sed == NULL) 2163 goto bad0; 2164 opipe->sed = sed; 2165 if (xfertype == UE_ISOCHRONOUS) { 2166 sitd = ohci_alloc_sitd(sc); 2167 if (sitd == NULL) 2168 goto bad1; 2169 opipe->tail.itd = sitd; 2170 tdphys = sitd->physaddr; 2171 fmt = OHCI_ED_FORMAT_ISO; 2172 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2173 fmt |= OHCI_ED_DIR_IN; 2174 else 2175 fmt |= OHCI_ED_DIR_OUT; 2176 } else { 2177 mutex_enter(&sc->sc_lock); 2178 std = ohci_alloc_std(sc); 2179 mutex_exit(&sc->sc_lock); 2180 if (std == NULL) 2181 goto bad1; 2182 opipe->tail.td = std; 2183 tdphys = std->physaddr; 2184 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2185 } 2186 sed->ed.ed_flags = HTOO32( 2187 OHCI_ED_SET_FA(addr) | 2188 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2189 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2190 fmt | 2191 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2192 sed->ed.ed_headp = HTOO32(tdphys | 2193 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2194 sed->ed.ed_tailp = HTOO32(tdphys); 2195 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2196 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2197 2198 switch (xfertype) { 2199 case UE_CONTROL: 2200 pipe->methods = &ohci_device_ctrl_methods; 2201 err = usb_allocmem(&sc->sc_bus, 2202 sizeof(usb_device_request_t), 2203 0, &opipe->u.ctl.reqdma); 2204 if (err) 2205 goto bad; 2206 mutex_enter(&sc->sc_lock); 2207 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2208 mutex_exit(&sc->sc_lock); 2209 break; 2210 case UE_INTERRUPT: 2211 pipe->methods = &ohci_device_intr_methods; 2212 ival = pipe->interval; 2213 if (ival == USBD_DEFAULT_INTERVAL) 2214 ival = ed->bInterval; 2215 return (ohci_device_setintr(sc, opipe, ival)); 2216 case UE_ISOCHRONOUS: 2217 pipe->methods = &ohci_device_isoc_methods; 2218 return (ohci_setup_isoc(pipe)); 2219 case UE_BULK: 2220 pipe->methods = &ohci_device_bulk_methods; 2221 mutex_enter(&sc->sc_lock); 2222 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2223 mutex_exit(&sc->sc_lock); 2224 break; 2225 } 2226 } 2227 2228 return USBD_NORMAL_COMPLETION; 2229 2230 bad: 2231 if (std != NULL) 2232 ohci_free_std(sc, std); 2233 bad1: 2234 if (sed != NULL) 2235 ohci_free_sed(sc, sed); 2236 bad0: 2237 return err; 2238 2239 } 2240 2241 /* 2242 * Close a reqular pipe. 2243 * Assumes that there are no pending transactions. 2244 */ 2245 void 2246 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2247 { 2248 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2249 ohci_softc_t *sc = pipe->device->bus->hci_private; 2250 ohci_soft_ed_t *sed = opipe->sed; 2251 2252 KASSERT(mutex_owned(&sc->sc_lock)); 2253 2254 #ifdef DIAGNOSTIC 2255 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2256 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2257 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2258 ohci_soft_td_t *std; 2259 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2260 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2261 "tl=0x%x pipe=%p, std=%p\n", sed, 2262 (int)O32TOH(sed->ed.ed_headp), 2263 (int)O32TOH(sed->ed.ed_tailp), 2264 pipe, std); 2265 #ifdef USB_DEBUG 2266 usbd_dump_pipe(&opipe->pipe); 2267 #endif 2268 #ifdef OHCI_DEBUG 2269 ohci_dump_ed(sc, sed); 2270 if (std) 2271 ohci_dump_td(sc, std); 2272 #endif 2273 usb_delay_ms(&sc->sc_bus, 2); 2274 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2275 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2276 printf("ohci_close_pipe: pipe still not empty\n"); 2277 } 2278 #endif 2279 ohci_rem_ed(sc, sed, head); 2280 /* Make sure the host controller is not touching this ED */ 2281 usb_delay_ms(&sc->sc_bus, 1); 2282 pipe->endpoint->datatoggle = 2283 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2284 ohci_free_sed(sc, opipe->sed); 2285 } 2286 2287 /* 2288 * Abort a device request. 2289 * If this routine is called at splusb() it guarantees that the request 2290 * will be removed from the hardware scheduling and that the callback 2291 * for it will be called with USBD_CANCELLED status. 2292 * It's impossible to guarantee that the requested transfer will not 2293 * have happened since the hardware runs concurrently. 2294 * If the transaction has already happened we rely on the ordinary 2295 * interrupt processing to process it. 2296 */ 2297 void 2298 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2299 { 2300 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2301 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2302 ohci_soft_ed_t *sed = opipe->sed; 2303 ohci_soft_td_t *p, *n; 2304 ohci_physaddr_t headp; 2305 int hit; 2306 int wake; 2307 2308 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2309 2310 if (sc->sc_dying) { 2311 /* If we're dying, just do the software part. */ 2312 mutex_enter(&sc->sc_lock); 2313 xfer->status = status; /* make software ignore it */ 2314 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2315 usb_transfer_complete(xfer); 2316 mutex_exit(&sc->sc_lock); 2317 return; 2318 } 2319 2320 if (xfer->device->bus->intr_context || !curproc) 2321 panic("ohci_abort_xfer: not in process context"); 2322 2323 mutex_enter(&sc->sc_lock); 2324 2325 /* 2326 * If an abort is already in progress then just wait for it to 2327 * complete and return. 2328 */ 2329 if (xfer->hcflags & UXFER_ABORTING) { 2330 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2331 #ifdef DIAGNOSTIC 2332 if (status == USBD_TIMEOUT) 2333 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2334 #endif 2335 /* Override the status which might be USBD_TIMEOUT. */ 2336 xfer->status = status; 2337 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2338 xfer->hcflags |= UXFER_ABORTWAIT; 2339 while (xfer->hcflags & UXFER_ABORTING) 2340 cv_wait(&xfer->hccv, &sc->sc_lock); 2341 goto done; 2342 return; 2343 } 2344 xfer->hcflags |= UXFER_ABORTING; 2345 2346 /* 2347 * Step 1: Make interrupt routine and hardware ignore xfer. 2348 */ 2349 xfer->status = status; /* make software ignore it */ 2350 callout_stop(&xfer->timeout_handle); 2351 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2352 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2353 sizeof(sed->ed.ed_flags), 2354 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2355 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2356 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2357 sizeof(sed->ed.ed_flags), 2358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2359 2360 /* 2361 * Step 2: Wait until we know hardware has finished any possible 2362 * use of the xfer. Also make sure the soft interrupt routine 2363 * has run. 2364 */ 2365 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2366 sc->sc_softwake = 1; 2367 usb_schedsoftintr(&sc->sc_bus); 2368 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2369 2370 /* 2371 * Step 3: Remove any vestiges of the xfer from the hardware. 2372 * The complication here is that the hardware may have executed 2373 * beyond the xfer we're trying to abort. So as we're scanning 2374 * the TDs of this xfer we check if the hardware points to 2375 * any of them. 2376 */ 2377 p = xfer->hcpriv; 2378 #ifdef DIAGNOSTIC 2379 if (p == NULL) { 2380 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2381 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2382 goto done; 2383 } 2384 #endif 2385 #ifdef OHCI_DEBUG 2386 if (ohcidebug > 1) { 2387 DPRINTF(("ohci_abort_xfer: sed=\n")); 2388 ohci_dump_ed(sc, sed); 2389 ohci_dump_tds(sc, p); 2390 } 2391 #endif 2392 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2393 hit = 0; 2394 for (; p->xfer == xfer; p = n) { 2395 hit |= headp == p->physaddr; 2396 n = p->nexttd; 2397 ohci_free_std(sc, p); 2398 } 2399 /* Zap headp register if hardware pointed inside the xfer. */ 2400 if (hit) { 2401 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2402 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2403 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2404 usb_syncmem(&sed->dma, 2405 sed->offs + offsetof(ohci_ed_t, ed_headp), 2406 sizeof(sed->ed.ed_headp), 2407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2408 } else { 2409 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2410 } 2411 2412 /* 2413 * Step 4: Turn on hardware again. 2414 */ 2415 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2416 sizeof(sed->ed.ed_flags), 2417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2418 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2419 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2420 sizeof(sed->ed.ed_flags), 2421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2422 2423 /* 2424 * Step 5: Execute callback. 2425 */ 2426 wake = xfer->hcflags & UXFER_ABORTWAIT; 2427 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2428 usb_transfer_complete(xfer); 2429 if (wake) 2430 cv_broadcast(&xfer->hccv); 2431 2432 done: 2433 mutex_exit(&sc->sc_lock); 2434 } 2435 2436 /* 2437 * Data structures and routines to emulate the root hub. 2438 */ 2439 Static usb_device_descriptor_t ohci_devd = { 2440 USB_DEVICE_DESCRIPTOR_SIZE, 2441 UDESC_DEVICE, /* type */ 2442 {0x00, 0x01}, /* USB version */ 2443 UDCLASS_HUB, /* class */ 2444 UDSUBCLASS_HUB, /* subclass */ 2445 UDPROTO_FSHUB, /* protocol */ 2446 64, /* max packet */ 2447 {0},{0},{0x00,0x01}, /* device id */ 2448 1,2,0, /* string indicies */ 2449 1 /* # of configurations */ 2450 }; 2451 2452 Static const usb_config_descriptor_t ohci_confd = { 2453 USB_CONFIG_DESCRIPTOR_SIZE, 2454 UDESC_CONFIG, 2455 {USB_CONFIG_DESCRIPTOR_SIZE + 2456 USB_INTERFACE_DESCRIPTOR_SIZE + 2457 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2458 1, 2459 1, 2460 0, 2461 UC_ATTR_MBO | UC_SELF_POWERED, 2462 0 /* max power */ 2463 }; 2464 2465 Static const usb_interface_descriptor_t ohci_ifcd = { 2466 USB_INTERFACE_DESCRIPTOR_SIZE, 2467 UDESC_INTERFACE, 2468 0, 2469 0, 2470 1, 2471 UICLASS_HUB, 2472 UISUBCLASS_HUB, 2473 UIPROTO_FSHUB, 2474 0 2475 }; 2476 2477 Static const usb_endpoint_descriptor_t ohci_endpd = { 2478 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2479 .bDescriptorType = UDESC_ENDPOINT, 2480 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2481 .bmAttributes = UE_INTERRUPT, 2482 .wMaxPacketSize = {8, 0}, /* max packet */ 2483 .bInterval = 255, 2484 }; 2485 2486 Static const usb_hub_descriptor_t ohci_hubd = { 2487 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2488 .bDescriptorType = UDESC_HUB, 2489 }; 2490 2491 /* 2492 * Simulate a hardware hub by handling all the necessary requests. 2493 */ 2494 Static usbd_status 2495 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2496 { 2497 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2498 usbd_status err; 2499 2500 /* Insert last in queue. */ 2501 mutex_enter(&sc->sc_lock); 2502 err = usb_insert_transfer(xfer); 2503 mutex_exit(&sc->sc_lock); 2504 if (err) 2505 return (err); 2506 2507 /* Pipe isn't running, start first */ 2508 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2509 } 2510 2511 Static usbd_status 2512 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2513 { 2514 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2515 usb_device_request_t *req; 2516 void *buf = NULL; 2517 int port, i; 2518 int len, value, index, l, totlen = 0; 2519 usb_port_status_t ps; 2520 usb_hub_descriptor_t hubd; 2521 usbd_status err; 2522 u_int32_t v; 2523 2524 if (sc->sc_dying) 2525 return (USBD_IOERROR); 2526 2527 #ifdef DIAGNOSTIC 2528 if (!(xfer->rqflags & URQ_REQUEST)) 2529 /* XXX panic */ 2530 return (USBD_INVAL); 2531 #endif 2532 req = &xfer->request; 2533 2534 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2535 req->bmRequestType, req->bRequest)); 2536 2537 len = UGETW(req->wLength); 2538 value = UGETW(req->wValue); 2539 index = UGETW(req->wIndex); 2540 2541 if (len != 0) 2542 buf = KERNADDR(&xfer->dmabuf, 0); 2543 2544 #define C(x,y) ((x) | ((y) << 8)) 2545 switch(C(req->bRequest, req->bmRequestType)) { 2546 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2547 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2548 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2549 /* 2550 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2551 * for the integrated root hub. 2552 */ 2553 break; 2554 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2555 if (len > 0) { 2556 *(u_int8_t *)buf = sc->sc_conf; 2557 totlen = 1; 2558 } 2559 break; 2560 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2561 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2562 if (len == 0) 2563 break; 2564 switch(value >> 8) { 2565 case UDESC_DEVICE: 2566 if ((value & 0xff) != 0) { 2567 err = USBD_IOERROR; 2568 goto ret; 2569 } 2570 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2571 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2572 memcpy(buf, &ohci_devd, l); 2573 break; 2574 case UDESC_CONFIG: 2575 if ((value & 0xff) != 0) { 2576 err = USBD_IOERROR; 2577 goto ret; 2578 } 2579 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2580 memcpy(buf, &ohci_confd, l); 2581 buf = (char *)buf + l; 2582 len -= l; 2583 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2584 totlen += l; 2585 memcpy(buf, &ohci_ifcd, l); 2586 buf = (char *)buf + l; 2587 len -= l; 2588 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2589 totlen += l; 2590 memcpy(buf, &ohci_endpd, l); 2591 break; 2592 case UDESC_STRING: 2593 #define sd ((usb_string_descriptor_t *)buf) 2594 switch (value & 0xff) { 2595 case 0: /* Language table */ 2596 totlen = usb_makelangtbl(sd, len); 2597 break; 2598 case 1: /* Vendor */ 2599 totlen = usb_makestrdesc(sd, len, 2600 sc->sc_vendor); 2601 break; 2602 case 2: /* Product */ 2603 totlen = usb_makestrdesc(sd, len, 2604 "OHCI root hub"); 2605 break; 2606 } 2607 #undef sd 2608 break; 2609 default: 2610 err = USBD_IOERROR; 2611 goto ret; 2612 } 2613 break; 2614 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2615 if (len > 0) { 2616 *(u_int8_t *)buf = 0; 2617 totlen = 1; 2618 } 2619 break; 2620 case C(UR_GET_STATUS, UT_READ_DEVICE): 2621 if (len > 1) { 2622 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2623 totlen = 2; 2624 } 2625 break; 2626 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2627 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2628 if (len > 1) { 2629 USETW(((usb_status_t *)buf)->wStatus, 0); 2630 totlen = 2; 2631 } 2632 break; 2633 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2634 if (value >= USB_MAX_DEVICES) { 2635 err = USBD_IOERROR; 2636 goto ret; 2637 } 2638 sc->sc_addr = value; 2639 break; 2640 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2641 if (value != 0 && value != 1) { 2642 err = USBD_IOERROR; 2643 goto ret; 2644 } 2645 sc->sc_conf = value; 2646 break; 2647 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2648 break; 2649 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2650 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2651 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2652 err = USBD_IOERROR; 2653 goto ret; 2654 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2655 break; 2656 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2657 break; 2658 /* Hub requests */ 2659 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2660 break; 2661 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2662 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2663 "port=%d feature=%d\n", 2664 index, value)); 2665 if (index < 1 || index > sc->sc_noport) { 2666 err = USBD_IOERROR; 2667 goto ret; 2668 } 2669 port = OHCI_RH_PORT_STATUS(index); 2670 switch(value) { 2671 case UHF_PORT_ENABLE: 2672 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2673 break; 2674 case UHF_PORT_SUSPEND: 2675 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2676 break; 2677 case UHF_PORT_POWER: 2678 /* Yes, writing to the LOW_SPEED bit clears power. */ 2679 OWRITE4(sc, port, UPS_LOW_SPEED); 2680 break; 2681 case UHF_C_PORT_CONNECTION: 2682 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2683 break; 2684 case UHF_C_PORT_ENABLE: 2685 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2686 break; 2687 case UHF_C_PORT_SUSPEND: 2688 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2689 break; 2690 case UHF_C_PORT_OVER_CURRENT: 2691 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2692 break; 2693 case UHF_C_PORT_RESET: 2694 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2695 break; 2696 default: 2697 err = USBD_IOERROR; 2698 goto ret; 2699 } 2700 switch(value) { 2701 case UHF_C_PORT_CONNECTION: 2702 case UHF_C_PORT_ENABLE: 2703 case UHF_C_PORT_SUSPEND: 2704 case UHF_C_PORT_OVER_CURRENT: 2705 case UHF_C_PORT_RESET: 2706 /* Enable RHSC interrupt if condition is cleared. */ 2707 if ((OREAD4(sc, port) >> 16) == 0) 2708 ohci_rhsc_enable(sc); 2709 break; 2710 default: 2711 break; 2712 } 2713 break; 2714 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2715 if (len == 0) 2716 break; 2717 if ((value & 0xff) != 0) { 2718 err = USBD_IOERROR; 2719 goto ret; 2720 } 2721 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2722 hubd = ohci_hubd; 2723 hubd.bNbrPorts = sc->sc_noport; 2724 USETW(hubd.wHubCharacteristics, 2725 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2726 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2727 /* XXX overcurrent */ 2728 ); 2729 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2730 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2731 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2732 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2733 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2734 l = min(len, hubd.bDescLength); 2735 totlen = l; 2736 memcpy(buf, &hubd, l); 2737 break; 2738 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2739 if (len != 4) { 2740 err = USBD_IOERROR; 2741 goto ret; 2742 } 2743 memset(buf, 0, len); /* ? XXX */ 2744 totlen = len; 2745 break; 2746 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2747 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2748 index)); 2749 if (index < 1 || index > sc->sc_noport) { 2750 err = USBD_IOERROR; 2751 goto ret; 2752 } 2753 if (len != 4) { 2754 err = USBD_IOERROR; 2755 goto ret; 2756 } 2757 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2758 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2759 v)); 2760 USETW(ps.wPortStatus, v); 2761 USETW(ps.wPortChange, v >> 16); 2762 l = min(len, sizeof ps); 2763 memcpy(buf, &ps, l); 2764 totlen = l; 2765 break; 2766 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2767 err = USBD_IOERROR; 2768 goto ret; 2769 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2770 break; 2771 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2772 if (index < 1 || index > sc->sc_noport) { 2773 err = USBD_IOERROR; 2774 goto ret; 2775 } 2776 port = OHCI_RH_PORT_STATUS(index); 2777 switch(value) { 2778 case UHF_PORT_ENABLE: 2779 OWRITE4(sc, port, UPS_PORT_ENABLED); 2780 break; 2781 case UHF_PORT_SUSPEND: 2782 OWRITE4(sc, port, UPS_SUSPEND); 2783 break; 2784 case UHF_PORT_RESET: 2785 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2786 index)); 2787 OWRITE4(sc, port, UPS_RESET); 2788 for (i = 0; i < 5; i++) { 2789 usb_delay_ms(&sc->sc_bus, 2790 USB_PORT_ROOT_RESET_DELAY); 2791 if (sc->sc_dying) { 2792 err = USBD_IOERROR; 2793 goto ret; 2794 } 2795 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2796 break; 2797 } 2798 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2799 index, OREAD4(sc, port))); 2800 break; 2801 case UHF_PORT_POWER: 2802 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2803 "%d\n", index)); 2804 OWRITE4(sc, port, UPS_PORT_POWER); 2805 break; 2806 default: 2807 err = USBD_IOERROR; 2808 goto ret; 2809 } 2810 break; 2811 default: 2812 err = USBD_IOERROR; 2813 goto ret; 2814 } 2815 xfer->actlen = totlen; 2816 err = USBD_NORMAL_COMPLETION; 2817 ret: 2818 xfer->status = err; 2819 mutex_enter(&sc->sc_lock); 2820 usb_transfer_complete(xfer); 2821 mutex_exit(&sc->sc_lock); 2822 return (USBD_IN_PROGRESS); 2823 } 2824 2825 /* Abort a root control request. */ 2826 Static void 2827 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2828 { 2829 /* Nothing to do, all transfers are synchronous. */ 2830 } 2831 2832 /* Close the root pipe. */ 2833 Static void 2834 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2835 { 2836 DPRINTF(("ohci_root_ctrl_close\n")); 2837 /* Nothing to do. */ 2838 } 2839 2840 Static usbd_status 2841 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2842 { 2843 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2844 usbd_status err; 2845 2846 /* Insert last in queue. */ 2847 mutex_enter(&sc->sc_lock); 2848 err = usb_insert_transfer(xfer); 2849 mutex_exit(&sc->sc_lock); 2850 if (err) 2851 return (err); 2852 2853 /* Pipe isn't running, start first */ 2854 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2855 } 2856 2857 Static usbd_status 2858 ohci_root_intr_start(usbd_xfer_handle xfer) 2859 { 2860 usbd_pipe_handle pipe = xfer->pipe; 2861 ohci_softc_t *sc = pipe->device->bus->hci_private; 2862 2863 if (sc->sc_dying) 2864 return (USBD_IOERROR); 2865 2866 mutex_enter(&sc->sc_lock); 2867 KASSERT(sc->sc_intrxfer == NULL); 2868 sc->sc_intrxfer = xfer; 2869 mutex_exit(&sc->sc_lock); 2870 2871 return (USBD_IN_PROGRESS); 2872 } 2873 2874 /* Abort a root interrupt request. */ 2875 Static void 2876 ohci_root_intr_abort(usbd_xfer_handle xfer) 2877 { 2878 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2879 2880 if (xfer->pipe->intrxfer == xfer) { 2881 DPRINTF(("ohci_root_intr_abort: remove\n")); 2882 xfer->pipe->intrxfer = NULL; 2883 } 2884 xfer->status = USBD_CANCELLED; 2885 mutex_enter(&sc->sc_lock); 2886 usb_transfer_complete(xfer); 2887 mutex_exit(&sc->sc_lock); 2888 } 2889 2890 /* Close the root pipe. */ 2891 Static void 2892 ohci_root_intr_close(usbd_pipe_handle pipe) 2893 { 2894 ohci_softc_t *sc = pipe->device->bus->hci_private; 2895 2896 DPRINTF(("ohci_root_intr_close\n")); 2897 2898 sc->sc_intrxfer = NULL; 2899 } 2900 2901 /************************/ 2902 2903 Static usbd_status 2904 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2905 { 2906 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2907 usbd_status err; 2908 2909 /* Insert last in queue. */ 2910 mutex_enter(&sc->sc_lock); 2911 err = usb_insert_transfer(xfer); 2912 mutex_exit(&sc->sc_lock); 2913 if (err) 2914 return (err); 2915 2916 /* Pipe isn't running, start first */ 2917 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2918 } 2919 2920 Static usbd_status 2921 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2922 { 2923 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2924 usbd_status err; 2925 2926 if (sc->sc_dying) 2927 return (USBD_IOERROR); 2928 2929 #ifdef DIAGNOSTIC 2930 if (!(xfer->rqflags & URQ_REQUEST)) { 2931 /* XXX panic */ 2932 printf("ohci_device_ctrl_transfer: not a request\n"); 2933 return (USBD_INVAL); 2934 } 2935 #endif 2936 2937 mutex_enter(&sc->sc_lock); 2938 err = ohci_device_request(xfer); 2939 mutex_exit(&sc->sc_lock); 2940 if (err) 2941 return (err); 2942 2943 if (sc->sc_bus.use_polling) 2944 ohci_waitintr(sc, xfer); 2945 return (USBD_IN_PROGRESS); 2946 } 2947 2948 /* Abort a device control request. */ 2949 Static void 2950 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2951 { 2952 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2953 ohci_abort_xfer(xfer, USBD_CANCELLED); 2954 } 2955 2956 /* Close a device control pipe. */ 2957 Static void 2958 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2959 { 2960 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2961 ohci_softc_t *sc = pipe->device->bus->hci_private; 2962 2963 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2964 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2965 ohci_free_std(sc, opipe->tail.td); 2966 } 2967 2968 /************************/ 2969 2970 Static void 2971 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2972 { 2973 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2974 ohci_softc_t *sc = pipe->device->bus->hci_private; 2975 2976 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2977 } 2978 2979 Static void 2980 ohci_noop(usbd_pipe_handle pipe) 2981 { 2982 } 2983 2984 Static usbd_status 2985 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2986 { 2987 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2988 usbd_status err; 2989 2990 /* Insert last in queue. */ 2991 mutex_enter(&sc->sc_lock); 2992 err = usb_insert_transfer(xfer); 2993 mutex_exit(&sc->sc_lock); 2994 if (err) 2995 return (err); 2996 2997 /* Pipe isn't running, start first */ 2998 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2999 } 3000 3001 Static usbd_status 3002 ohci_device_bulk_start(usbd_xfer_handle xfer) 3003 { 3004 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3005 usbd_device_handle dev = opipe->pipe.device; 3006 ohci_softc_t *sc = dev->bus->hci_private; 3007 int addr = dev->address; 3008 ohci_soft_td_t *data, *tail, *tdp; 3009 ohci_soft_ed_t *sed; 3010 int len, isread, endpt; 3011 usbd_status err; 3012 3013 if (sc->sc_dying) 3014 return (USBD_IOERROR); 3015 3016 #ifdef DIAGNOSTIC 3017 if (xfer->rqflags & URQ_REQUEST) { 3018 /* XXX panic */ 3019 printf("ohci_device_bulk_start: a request\n"); 3020 return (USBD_INVAL); 3021 } 3022 #endif 3023 3024 mutex_enter(&sc->sc_lock); 3025 3026 len = xfer->length; 3027 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3028 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3029 sed = opipe->sed; 3030 3031 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3032 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3033 endpt)); 3034 3035 opipe->u.bulk.isread = isread; 3036 opipe->u.bulk.length = len; 3037 3038 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3039 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3040 /* Update device address */ 3041 sed->ed.ed_flags = HTOO32( 3042 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3043 OHCI_ED_SET_FA(addr)); 3044 3045 /* Allocate a chain of new TDs (including a new tail). */ 3046 data = opipe->tail.td; 3047 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3048 data, &tail); 3049 /* We want interrupt at the end of the transfer. */ 3050 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3051 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3052 tail->flags |= OHCI_CALL_DONE; 3053 tail = tail->nexttd; /* point at sentinel */ 3054 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3055 sizeof(tail->td.td_flags), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 if (err) { 3058 mutex_exit(&sc->sc_lock); 3059 return (err); 3060 } 3061 3062 tail->xfer = NULL; 3063 xfer->hcpriv = data; 3064 3065 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3066 "td_cbp=0x%08x td_be=0x%08x\n", 3067 (int)O32TOH(sed->ed.ed_flags), 3068 (int)O32TOH(data->td.td_flags), 3069 (int)O32TOH(data->td.td_cbp), 3070 (int)O32TOH(data->td.td_be))); 3071 3072 #ifdef OHCI_DEBUG 3073 if (ohcidebug > 5) { 3074 ohci_dump_ed(sc, sed); 3075 ohci_dump_tds(sc, data); 3076 } 3077 #endif 3078 3079 /* Insert ED in schedule */ 3080 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3081 tdp->xfer = xfer; 3082 } 3083 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3084 opipe->tail.td = tail; 3085 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3086 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3088 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3089 if (xfer->timeout && !sc->sc_bus.use_polling) { 3090 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3091 ohci_timeout, xfer); 3092 } 3093 mutex_exit(&sc->sc_lock); 3094 3095 #if 0 3096 /* This goes wrong if we are too slow. */ 3097 if (ohcidebug > 10) { 3098 delay(10000); 3099 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3100 OREAD4(sc, OHCI_COMMAND_STATUS))); 3101 ohci_dump_ed(sc, sed); 3102 ohci_dump_tds(sc, data); 3103 } 3104 #endif 3105 3106 return (USBD_IN_PROGRESS); 3107 } 3108 3109 Static void 3110 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3111 { 3112 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3113 ohci_abort_xfer(xfer, USBD_CANCELLED); 3114 } 3115 3116 /* 3117 * Close a device bulk pipe. 3118 */ 3119 Static void 3120 ohci_device_bulk_close(usbd_pipe_handle pipe) 3121 { 3122 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3123 ohci_softc_t *sc = pipe->device->bus->hci_private; 3124 3125 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3126 mutex_enter(&sc->sc_lock); 3127 ohci_close_pipe(pipe, sc->sc_bulk_head); 3128 mutex_exit(&sc->sc_lock); 3129 ohci_free_std(sc, opipe->tail.td); 3130 } 3131 3132 /************************/ 3133 3134 Static usbd_status 3135 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3136 { 3137 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3138 usbd_status err; 3139 3140 /* Insert last in queue. */ 3141 mutex_enter(&sc->sc_lock); 3142 err = usb_insert_transfer(xfer); 3143 mutex_exit(&sc->sc_lock); 3144 if (err) 3145 return (err); 3146 3147 /* Pipe isn't running, start first */ 3148 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3149 } 3150 3151 Static usbd_status 3152 ohci_device_intr_start(usbd_xfer_handle xfer) 3153 { 3154 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3155 usbd_device_handle dev = opipe->pipe.device; 3156 ohci_softc_t *sc = dev->bus->hci_private; 3157 ohci_soft_ed_t *sed = opipe->sed; 3158 ohci_soft_td_t *data, *tail; 3159 int len, isread, endpt; 3160 3161 if (sc->sc_dying) 3162 return (USBD_IOERROR); 3163 3164 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3165 "flags=%d priv=%p\n", 3166 xfer, xfer->length, xfer->flags, xfer->priv)); 3167 3168 #ifdef DIAGNOSTIC 3169 if (xfer->rqflags & URQ_REQUEST) 3170 panic("ohci_device_intr_transfer: a request"); 3171 #endif 3172 3173 len = xfer->length; 3174 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3175 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3176 3177 data = opipe->tail.td; 3178 mutex_enter(&sc->sc_lock); 3179 tail = ohci_alloc_std(sc); 3180 mutex_exit(&sc->sc_lock); 3181 if (tail == NULL) 3182 return (USBD_NOMEM); 3183 tail->xfer = NULL; 3184 3185 data->td.td_flags = HTOO32( 3186 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3187 OHCI_TD_NOCC | 3188 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3189 if (xfer->flags & USBD_SHORT_XFER_OK) 3190 data->td.td_flags |= HTOO32(OHCI_TD_R); 3191 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3192 data->nexttd = tail; 3193 data->td.td_nexttd = HTOO32(tail->physaddr); 3194 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3195 data->len = len; 3196 data->xfer = xfer; 3197 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3198 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3200 xfer->hcpriv = data; 3201 3202 #ifdef OHCI_DEBUG 3203 if (ohcidebug > 5) { 3204 DPRINTF(("ohci_device_intr_transfer:\n")); 3205 ohci_dump_ed(sc, sed); 3206 ohci_dump_tds(sc, data); 3207 } 3208 #endif 3209 3210 /* Insert ED in schedule */ 3211 mutex_enter(&sc->sc_lock); 3212 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3213 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3214 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3215 opipe->tail.td = tail; 3216 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3217 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3218 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3219 3220 #if 0 3221 /* 3222 * This goes horribly wrong, printing thousands of descriptors, 3223 * because false references are followed due to the fact that the 3224 * TD is gone. 3225 */ 3226 if (ohcidebug > 5) { 3227 usb_delay_ms(&sc->sc_bus, 5); 3228 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3229 OREAD4(sc, OHCI_COMMAND_STATUS))); 3230 ohci_dump_ed(sc, sed); 3231 ohci_dump_tds(sc, data); 3232 } 3233 #endif 3234 mutex_exit(&sc->sc_lock); 3235 3236 return (USBD_IN_PROGRESS); 3237 } 3238 3239 /* Abort a device control request. */ 3240 Static void 3241 ohci_device_intr_abort(usbd_xfer_handle xfer) 3242 { 3243 if (xfer->pipe->intrxfer == xfer) { 3244 DPRINTF(("ohci_device_intr_abort: remove\n")); 3245 xfer->pipe->intrxfer = NULL; 3246 } 3247 ohci_abort_xfer(xfer, USBD_CANCELLED); 3248 } 3249 3250 /* Close a device interrupt pipe. */ 3251 Static void 3252 ohci_device_intr_close(usbd_pipe_handle pipe) 3253 { 3254 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3255 ohci_softc_t *sc = pipe->device->bus->hci_private; 3256 int nslots = opipe->u.intr.nslots; 3257 int pos = opipe->u.intr.pos; 3258 int j; 3259 ohci_soft_ed_t *p, *sed = opipe->sed; 3260 3261 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3262 pipe, nslots, pos)); 3263 mutex_enter(&sc->sc_lock); 3264 usb_syncmem(&sed->dma, sed->offs, 3265 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3266 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3267 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3268 sizeof(sed->ed.ed_flags), 3269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3270 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3271 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3272 usb_delay_ms(&sc->sc_bus, 2); 3273 3274 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3275 continue; 3276 #ifdef DIAGNOSTIC 3277 if (p == NULL) 3278 panic("ohci_device_intr_close: ED not found"); 3279 #endif 3280 p->next = sed->next; 3281 p->ed.ed_nexted = sed->ed.ed_nexted; 3282 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3283 sizeof(p->ed.ed_nexted), 3284 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3285 mutex_exit(&sc->sc_lock); 3286 3287 for (j = 0; j < nslots; j++) 3288 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3289 3290 ohci_free_std(sc, opipe->tail.td); 3291 ohci_free_sed(sc, opipe->sed); 3292 } 3293 3294 Static usbd_status 3295 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3296 { 3297 int i, j, best; 3298 u_int npoll, slow, shigh, nslots; 3299 u_int bestbw, bw; 3300 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3301 3302 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3303 if (ival == 0) { 3304 printf("ohci_setintr: 0 interval\n"); 3305 return (USBD_INVAL); 3306 } 3307 3308 npoll = OHCI_NO_INTRS; 3309 while (npoll > ival) 3310 npoll /= 2; 3311 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3312 3313 /* 3314 * We now know which level in the tree the ED must go into. 3315 * Figure out which slot has most bandwidth left over. 3316 * Slots to examine: 3317 * npoll 3318 * 1 0 3319 * 2 1 2 3320 * 4 3 4 5 6 3321 * 8 7 8 9 10 11 12 13 14 3322 * N (N-1) .. (N-1+N-1) 3323 */ 3324 slow = npoll-1; 3325 shigh = slow + npoll; 3326 nslots = OHCI_NO_INTRS / npoll; 3327 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3328 bw = 0; 3329 for (j = 0; j < nslots; j++) 3330 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3331 if (bw < bestbw) { 3332 best = i; 3333 bestbw = bw; 3334 } 3335 } 3336 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3337 best, slow, shigh, bestbw)); 3338 3339 mutex_enter(&sc->sc_lock); 3340 hsed = sc->sc_eds[best]; 3341 sed->next = hsed->next; 3342 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3343 sizeof(hsed->ed.ed_flags), 3344 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3345 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3346 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3347 sizeof(sed->ed.ed_flags), 3348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3349 hsed->next = sed; 3350 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3351 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3352 sizeof(hsed->ed.ed_flags), 3353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3354 mutex_exit(&sc->sc_lock); 3355 3356 for (j = 0; j < nslots; j++) 3357 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3358 opipe->u.intr.nslots = nslots; 3359 opipe->u.intr.pos = best; 3360 3361 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3362 return (USBD_NORMAL_COMPLETION); 3363 } 3364 3365 /***********************/ 3366 3367 usbd_status 3368 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3369 { 3370 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3371 usbd_status err; 3372 3373 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3374 3375 /* Put it on our queue, */ 3376 mutex_enter(&sc->sc_lock); 3377 err = usb_insert_transfer(xfer); 3378 mutex_exit(&sc->sc_lock); 3379 3380 /* bail out on error, */ 3381 if (err && err != USBD_IN_PROGRESS) 3382 return (err); 3383 3384 /* XXX should check inuse here */ 3385 3386 /* insert into schedule, */ 3387 ohci_device_isoc_enter(xfer); 3388 3389 /* and start if the pipe wasn't running */ 3390 if (!err) 3391 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3392 3393 return (err); 3394 } 3395 3396 void 3397 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3398 { 3399 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3400 usbd_device_handle dev = opipe->pipe.device; 3401 ohci_softc_t *sc = dev->bus->hci_private; 3402 ohci_soft_ed_t *sed = opipe->sed; 3403 struct iso *iso = &opipe->u.iso; 3404 ohci_soft_itd_t *sitd, *nsitd; 3405 ohci_physaddr_t buf, offs, noffs, bp0; 3406 int i, ncur, nframes; 3407 3408 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3409 "nframes=%d\n", 3410 iso->inuse, iso->next, xfer, xfer->nframes)); 3411 3412 if (sc->sc_dying) 3413 return; 3414 3415 if (iso->next == -1) { 3416 /* Not in use yet, schedule it a few frames ahead. */ 3417 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3418 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3419 iso->next)); 3420 } 3421 3422 sitd = opipe->tail.itd; 3423 buf = DMAADDR(&xfer->dmabuf, 0); 3424 bp0 = OHCI_PAGE(buf); 3425 offs = OHCI_PAGE_OFFSET(buf); 3426 nframes = xfer->nframes; 3427 xfer->hcpriv = sitd; 3428 for (i = ncur = 0; i < nframes; i++, ncur++) { 3429 noffs = offs + xfer->frlengths[i]; 3430 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3431 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3432 3433 /* Allocate next ITD */ 3434 nsitd = ohci_alloc_sitd(sc); 3435 if (nsitd == NULL) { 3436 /* XXX what now? */ 3437 printf("%s: isoc TD alloc failed\n", 3438 device_xname(sc->sc_dev)); 3439 return; 3440 } 3441 3442 /* Fill current ITD */ 3443 sitd->itd.itd_flags = HTOO32( 3444 OHCI_ITD_NOCC | 3445 OHCI_ITD_SET_SF(iso->next) | 3446 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3447 OHCI_ITD_SET_FC(ncur)); 3448 sitd->itd.itd_bp0 = HTOO32(bp0); 3449 sitd->nextitd = nsitd; 3450 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3451 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3452 sitd->xfer = xfer; 3453 sitd->flags = 0; 3454 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3456 3457 sitd = nsitd; 3458 iso->next = iso->next + ncur; 3459 bp0 = OHCI_PAGE(buf + offs); 3460 ncur = 0; 3461 } 3462 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3463 offs = noffs; 3464 } 3465 nsitd = ohci_alloc_sitd(sc); 3466 if (nsitd == NULL) { 3467 /* XXX what now? */ 3468 printf("%s: isoc TD alloc failed\n", 3469 device_xname(sc->sc_dev)); 3470 return; 3471 } 3472 /* Fixup last used ITD */ 3473 sitd->itd.itd_flags = HTOO32( 3474 OHCI_ITD_NOCC | 3475 OHCI_ITD_SET_SF(iso->next) | 3476 OHCI_ITD_SET_DI(0) | 3477 OHCI_ITD_SET_FC(ncur)); 3478 sitd->itd.itd_bp0 = HTOO32(bp0); 3479 sitd->nextitd = nsitd; 3480 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3481 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3482 sitd->xfer = xfer; 3483 sitd->flags = OHCI_CALL_DONE; 3484 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3485 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3486 3487 iso->next = iso->next + ncur; 3488 iso->inuse += nframes; 3489 3490 xfer->actlen = offs; /* XXX pretend we did it all */ 3491 3492 xfer->status = USBD_IN_PROGRESS; 3493 3494 #ifdef OHCI_DEBUG 3495 if (ohcidebug > 5) { 3496 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3497 O32TOH(sc->sc_hcca->hcca_frame_number))); 3498 ohci_dump_itds(sc, xfer->hcpriv); 3499 ohci_dump_ed(sc, sed); 3500 } 3501 #endif 3502 3503 mutex_enter(&sc->sc_lock); 3504 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3505 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3506 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3507 opipe->tail.itd = nsitd; 3508 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3509 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3510 sizeof(sed->ed.ed_flags), 3511 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3512 mutex_exit(&sc->sc_lock); 3513 3514 #ifdef OHCI_DEBUG 3515 if (ohcidebug > 5) { 3516 delay(150000); 3517 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3518 O32TOH(sc->sc_hcca->hcca_frame_number))); 3519 ohci_dump_itds(sc, xfer->hcpriv); 3520 ohci_dump_ed(sc, sed); 3521 } 3522 #endif 3523 } 3524 3525 usbd_status 3526 ohci_device_isoc_start(usbd_xfer_handle xfer) 3527 { 3528 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3529 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3530 3531 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3532 3533 mutex_enter(&sc->sc_lock); 3534 3535 if (sc->sc_dying) { 3536 mutex_exit(&sc->sc_lock); 3537 return (USBD_IOERROR); 3538 } 3539 3540 #ifdef DIAGNOSTIC 3541 if (xfer->status != USBD_IN_PROGRESS) 3542 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3543 #endif 3544 3545 /* XXX anything to do? */ 3546 3547 mutex_exit(&sc->sc_lock); 3548 3549 return (USBD_IN_PROGRESS); 3550 } 3551 3552 void 3553 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3554 { 3555 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3556 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3557 ohci_soft_ed_t *sed; 3558 ohci_soft_itd_t *sitd; 3559 3560 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3561 3562 mutex_enter(&sc->sc_lock); 3563 3564 /* Transfer is already done. */ 3565 if (xfer->status != USBD_NOT_STARTED && 3566 xfer->status != USBD_IN_PROGRESS) { 3567 printf("ohci_device_isoc_abort: early return\n"); 3568 goto done; 3569 } 3570 3571 /* Give xfer the requested abort code. */ 3572 xfer->status = USBD_CANCELLED; 3573 3574 sed = opipe->sed; 3575 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3576 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3577 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3578 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3579 sizeof(sed->ed.ed_flags), 3580 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3581 3582 sitd = xfer->hcpriv; 3583 #ifdef DIAGNOSTIC 3584 if (sitd == NULL) { 3585 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3586 goto done; 3587 } 3588 #endif 3589 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3590 #ifdef DIAGNOSTIC 3591 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3592 sitd->isdone = 1; 3593 #endif 3594 } 3595 3596 mutex_exit(&sc->sc_lock); 3597 3598 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3599 3600 mutex_enter(&sc->sc_lock); 3601 3602 /* Run callback. */ 3603 usb_transfer_complete(xfer); 3604 3605 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3606 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3607 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3608 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3609 3610 done: 3611 mutex_exit(&sc->sc_lock); 3612 } 3613 3614 void 3615 ohci_device_isoc_done(usbd_xfer_handle xfer) 3616 { 3617 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3618 } 3619 3620 usbd_status 3621 ohci_setup_isoc(usbd_pipe_handle pipe) 3622 { 3623 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3624 ohci_softc_t *sc = pipe->device->bus->hci_private; 3625 struct iso *iso = &opipe->u.iso; 3626 3627 iso->next = -1; 3628 iso->inuse = 0; 3629 3630 mutex_enter(&sc->sc_lock); 3631 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3632 mutex_exit(&sc->sc_lock); 3633 3634 return (USBD_NORMAL_COMPLETION); 3635 } 3636 3637 void 3638 ohci_device_isoc_close(usbd_pipe_handle pipe) 3639 { 3640 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3641 ohci_softc_t *sc = pipe->device->bus->hci_private; 3642 3643 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3644 mutex_enter(&sc->sc_lock); 3645 ohci_close_pipe(pipe, sc->sc_isoc_head); 3646 #ifdef DIAGNOSTIC 3647 opipe->tail.itd->isdone = 1; 3648 #endif 3649 mutex_exit(&sc->sc_lock); 3650 ohci_free_sitd(sc, opipe->tail.itd); 3651 } 3652
Indexes created Fri Oct 03 02:09:57 GMT 2025