ohci.c revision 1.218.6.9
1 /* $NetBSD: ohci.c,v 1.218.6.9 2012/02/20 02:12:24 mrg Exp $ */ 2 /* $FreeBSD: src/sys/dev/usb/ohci.c,v 1.22 1999/11/17 22:33:40 n_hibma Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2004, 2005, 2011 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) at 10 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 11 * and Matthew R. Green. 12 * This code is derived from software contributed to The NetBSD Foundation 13 * by Charles M. Hannum. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 34 * POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * USB Open Host Controller driver. 39 * 40 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 41 * USB spec: http://www.usb.org/developers/docs/ 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.218.6.9 2012/02/20 02:12:24 mrg Exp $"); 46 47 #include "opt_usb.h" 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/kmem.h> 52 #include <sys/kernel.h> 53 #include <sys/device.h> 54 #include <sys/select.h> 55 #include <sys/proc.h> 56 #include <sys/queue.h> 57 58 #include <sys/bus.h> 59 #include <machine/endian.h> 60 61 #include <dev/usb/usb.h> 62 #include <dev/usb/usbdi.h> 63 #include <dev/usb/usbdivar.h> 64 #include <dev/usb/usb_mem.h> 65 #include <dev/usb/usb_quirks.h> 66 67 #include <dev/usb/ohcireg.h> 68 #include <dev/usb/ohcivar.h> 69 #include <dev/usb/usbroothub_subr.h> 70 71 72 73 #ifdef OHCI_DEBUG 74 #define DPRINTF(x) if (ohcidebug) printf x 75 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 76 int ohcidebug = 0; 77 #else 78 #define DPRINTF(x) 79 #define DPRINTFN(n,x) 80 #endif 81 82 #if BYTE_ORDER == BIG_ENDIAN 83 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 84 #else 85 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 86 #endif 87 88 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 89 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 90 #define HTOO16(val) O16TOH(val) 91 #define HTOO32(val) O32TOH(val) 92 93 struct ohci_pipe; 94 95 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 96 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 97 98 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 99 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 100 101 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 102 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 103 104 #if 0 105 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 106 ohci_soft_td_t *); 107 #endif 108 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 109 ohci_softc_t *, int, int, usbd_xfer_handle, 110 ohci_soft_td_t *, ohci_soft_td_t **); 111 112 Static usbd_status ohci_open(usbd_pipe_handle); 113 Static void ohci_poll(struct usbd_bus *); 114 Static void ohci_softintr(void *); 115 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 116 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 117 Static void ohci_rhsc_softint(void *arg); 118 119 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 120 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 121 ohci_soft_ed_t *); 122 123 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 124 ohci_soft_ed_t *); 125 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 126 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 127 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 128 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 129 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 130 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 131 132 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 133 Static void ohci_device_isoc_enter(usbd_xfer_handle); 134 135 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 136 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 137 138 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 139 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 140 Static void ohci_get_locks(struct usbd_bus *, kmutex_t **, 141 kmutex_t **); 142 143 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 145 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 146 Static void ohci_root_ctrl_close(usbd_pipe_handle); 147 Static void ohci_root_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 151 Static void ohci_root_intr_abort(usbd_xfer_handle); 152 Static void ohci_root_intr_close(usbd_pipe_handle); 153 Static void ohci_root_intr_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 157 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 158 Static void ohci_device_ctrl_close(usbd_pipe_handle); 159 Static void ohci_device_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 163 Static void ohci_device_bulk_abort(usbd_xfer_handle); 164 Static void ohci_device_bulk_close(usbd_pipe_handle); 165 Static void ohci_device_bulk_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 169 Static void ohci_device_intr_abort(usbd_xfer_handle); 170 Static void ohci_device_intr_close(usbd_pipe_handle); 171 Static void ohci_device_intr_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 174 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 175 Static void ohci_device_isoc_abort(usbd_xfer_handle); 176 Static void ohci_device_isoc_close(usbd_pipe_handle); 177 Static void ohci_device_isoc_done(usbd_xfer_handle); 178 179 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 180 struct ohci_pipe *pipe, int ival); 181 182 Static void ohci_timeout(void *); 183 Static void ohci_timeout_task(void *); 184 Static void ohci_rhsc_enable(void *); 185 186 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 187 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 188 189 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 190 Static void ohci_noop(usbd_pipe_handle pipe); 191 192 #ifdef OHCI_DEBUG 193 Static void ohci_dumpregs(ohci_softc_t *); 194 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 195 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 196 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 197 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 198 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 199 #endif 200 201 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 202 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 203 #define OWRITE1(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 #define OWRITE2(sc, r, x) \ 206 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 207 #define OWRITE4(sc, r, x) \ 208 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 209 static __inline uint8_t 210 OREAD1(ohci_softc_t *sc, bus_size_t r) 211 { 212 213 OBARR(sc); 214 return bus_space_read_1(sc->iot, sc->ioh, r); 215 } 216 217 static __inline uint16_t 218 OREAD2(ohci_softc_t *sc, bus_size_t r) 219 { 220 221 OBARR(sc); 222 return bus_space_read_2(sc->iot, sc->ioh, r); 223 } 224 225 static __inline uint32_t 226 OREAD4(ohci_softc_t *sc, bus_size_t r) 227 { 228 229 OBARR(sc); 230 return bus_space_read_4(sc->iot, sc->ioh, r); 231 } 232 233 /* Reverse the bits in a value 0 .. 31 */ 234 Static u_int8_t revbits[OHCI_NO_INTRS] = 235 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 236 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 237 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 238 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 239 240 struct ohci_pipe { 241 struct usbd_pipe pipe; 242 ohci_soft_ed_t *sed; 243 union { 244 ohci_soft_td_t *td; 245 ohci_soft_itd_t *itd; 246 } tail; 247 /* Info needed for different pipe kinds. */ 248 union { 249 /* Control pipe */ 250 struct { 251 usb_dma_t reqdma; 252 u_int length; 253 ohci_soft_td_t *setup, *data, *stat; 254 } ctl; 255 /* Interrupt pipe */ 256 struct { 257 int nslots; 258 int pos; 259 } intr; 260 /* Bulk pipe */ 261 struct { 262 u_int length; 263 int isread; 264 } bulk; 265 /* Iso pipe */ 266 struct iso { 267 int next, inuse; 268 } iso; 269 } u; 270 }; 271 272 #define OHCI_INTR_ENDPT 1 273 274 Static const struct usbd_bus_methods ohci_bus_methods = { 275 .open_pipe = ohci_open, 276 .soft_intr = ohci_softintr, 277 .do_poll = ohci_poll, 278 .allocm = ohci_allocm, 279 .freem = ohci_freem, 280 .allocx = ohci_allocx, 281 .freex = ohci_freex, 282 .get_locks = ohci_get_locks, 283 }; 284 285 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 286 .transfer = ohci_root_ctrl_transfer, 287 .start = ohci_root_ctrl_start, 288 .abort = ohci_root_ctrl_abort, 289 .close = ohci_root_ctrl_close, 290 .cleartoggle = ohci_noop, 291 .done = ohci_root_ctrl_done, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .transfer = ohci_root_intr_transfer, 296 .start = ohci_root_intr_start, 297 .abort = ohci_root_intr_abort, 298 .close = ohci_root_intr_close, 299 .cleartoggle = ohci_noop, 300 .done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .transfer = ohci_device_ctrl_transfer, 305 .start = ohci_device_ctrl_start, 306 .abort = ohci_device_ctrl_abort, 307 .close = ohci_device_ctrl_close, 308 .cleartoggle = ohci_noop, 309 .done = ohci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 313 .transfer = ohci_device_intr_transfer, 314 .start = ohci_device_intr_start, 315 .abort = ohci_device_intr_abort, 316 .close = ohci_device_intr_close, 317 .cleartoggle = ohci_device_clear_toggle, 318 .done = ohci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 322 .transfer = ohci_device_bulk_transfer, 323 .start = ohci_device_bulk_start, 324 .abort = ohci_device_bulk_abort, 325 .close = ohci_device_bulk_close, 326 .cleartoggle = ohci_device_clear_toggle, 327 .done = ohci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 331 .transfer = ohci_device_isoc_transfer, 332 .start = ohci_device_isoc_start, 333 .abort = ohci_device_isoc_abort, 334 .close = ohci_device_isoc_close, 335 .cleartoggle = ohci_noop, 336 .done = ohci_device_isoc_done, 337 }; 338 339 int 340 ohci_activate(device_t self, enum devact act) 341 { 342 struct ohci_softc *sc = device_private(self); 343 344 switch (act) { 345 case DVACT_DEACTIVATE: 346 sc->sc_dying = 1; 347 return 0; 348 default: 349 return EOPNOTSUPP; 350 } 351 } 352 353 void 354 ohci_childdet(device_t self, device_t child) 355 { 356 struct ohci_softc *sc = device_private(self); 357 358 KASSERT(sc->sc_child == child); 359 sc->sc_child = NULL; 360 } 361 362 int 363 ohci_detach(struct ohci_softc *sc, int flags) 364 { 365 int rv = 0; 366 usbd_xfer_handle xfer; 367 368 if (sc->sc_child != NULL) 369 rv = config_detach(sc->sc_child, flags); 370 371 if (rv != 0) 372 return (rv); 373 374 callout_stop(&sc->sc_tmo_rhsc); 375 376 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 377 callout_destroy(&sc->sc_tmo_rhsc); 378 379 softint_disestablish(sc->sc_rhsc_si); 380 381 cv_destroy(&sc->sc_softwake_cv); 382 383 mutex_destroy(&sc->sc_lock); 384 mutex_destroy(&sc->sc_intr_lock); 385 386 if (sc->sc_hcca != NULL) 387 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 388 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 389 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 390 kmem_free(xfer, sizeof(struct ohci_xfer)); 391 } 392 393 return (rv); 394 } 395 396 ohci_soft_ed_t * 397 ohci_alloc_sed(ohci_softc_t *sc) 398 { 399 ohci_soft_ed_t *sed; 400 usbd_status err; 401 int i, offs; 402 usb_dma_t dma; 403 404 if (sc->sc_freeeds == NULL) { 405 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 406 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 407 OHCI_ED_ALIGN, &dma); 408 if (err) 409 return (0); 410 for(i = 0; i < OHCI_SED_CHUNK; i++) { 411 offs = i * OHCI_SED_SIZE; 412 sed = KERNADDR(&dma, offs); 413 sed->physaddr = DMAADDR(&dma, offs); 414 sed->dma = dma; 415 sed->offs = offs; 416 sed->next = sc->sc_freeeds; 417 sc->sc_freeeds = sed; 418 } 419 } 420 sed = sc->sc_freeeds; 421 sc->sc_freeeds = sed->next; 422 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 423 sed->next = 0; 424 return (sed); 425 } 426 427 void 428 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 429 { 430 sed->next = sc->sc_freeeds; 431 sc->sc_freeeds = sed; 432 } 433 434 ohci_soft_td_t * 435 ohci_alloc_std(ohci_softc_t *sc) 436 { 437 ohci_soft_td_t *std; 438 usbd_status err; 439 int i, offs; 440 usb_dma_t dma; 441 442 if (sc->sc_freetds == NULL) { 443 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 444 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 445 OHCI_TD_ALIGN, &dma); 446 if (err) 447 return (NULL); 448 for(i = 0; i < OHCI_STD_CHUNK; i++) { 449 offs = i * OHCI_STD_SIZE; 450 std = KERNADDR(&dma, offs); 451 std->physaddr = DMAADDR(&dma, offs); 452 std->dma = dma; 453 std->offs = offs; 454 std->nexttd = sc->sc_freetds; 455 sc->sc_freetds = std; 456 } 457 } 458 459 std = sc->sc_freetds; 460 sc->sc_freetds = std->nexttd; 461 memset(&std->td, 0, sizeof(ohci_td_t)); 462 std->nexttd = NULL; 463 std->xfer = NULL; 464 ohci_hash_add_td(sc, std); 465 466 return (std); 467 } 468 469 void 470 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 471 { 472 473 ohci_hash_rem_td(sc, std); 474 std->nexttd = sc->sc_freetds; 475 sc->sc_freetds = std; 476 } 477 478 usbd_status 479 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 480 int alen, int rd, usbd_xfer_handle xfer, 481 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 482 { 483 ohci_soft_td_t *next, *cur; 484 ohci_physaddr_t dataphys, dataphysend; 485 u_int32_t tdflags; 486 int len, curlen; 487 usb_dma_t *dma = &xfer->dmabuf; 488 u_int16_t flags = xfer->flags; 489 490 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 491 492 KASSERT(mutex_owned(&sc->sc_lock)); 493 494 len = alen; 495 cur = sp; 496 dataphys = DMAADDR(dma, 0); 497 dataphysend = OHCI_PAGE(dataphys + len - 1); 498 usb_syncmem(dma, 0, len, 499 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 500 tdflags = HTOO32( 501 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 502 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 503 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 504 505 for (;;) { 506 next = ohci_alloc_std(sc); 507 if (next == NULL) 508 goto nomem; 509 510 /* The OHCI hardware can handle at most one page crossing. */ 511 if (OHCI_PAGE(dataphys) == dataphysend || 512 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 513 /* we can handle it in this TD */ 514 curlen = len; 515 } else { 516 /* must use multiple TDs, fill as much as possible. */ 517 curlen = 2 * OHCI_PAGE_SIZE - 518 (dataphys & (OHCI_PAGE_SIZE-1)); 519 /* the length must be a multiple of the max size */ 520 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 521 #ifdef DIAGNOSTIC 522 if (curlen == 0) 523 panic("ohci_alloc_std: curlen == 0"); 524 #endif 525 } 526 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 527 "dataphysend=0x%08x len=%d curlen=%d\n", 528 dataphys, dataphysend, 529 len, curlen)); 530 len -= curlen; 531 532 cur->td.td_flags = tdflags; 533 cur->td.td_cbp = HTOO32(dataphys); 534 cur->nexttd = next; 535 cur->td.td_nexttd = HTOO32(next->physaddr); 536 cur->td.td_be = HTOO32(dataphys + curlen - 1); 537 cur->len = curlen; 538 cur->flags = OHCI_ADD_LEN; 539 cur->xfer = xfer; 540 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 541 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 542 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 543 dataphys, dataphys + curlen - 1)); 544 if (len == 0) 545 break; 546 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 547 dataphys += curlen; 548 cur = next; 549 } 550 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 551 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 552 /* Force a 0 length transfer at the end. */ 553 554 cur = next; 555 next = ohci_alloc_std(sc); 556 if (next == NULL) 557 goto nomem; 558 559 cur->td.td_flags = tdflags; 560 cur->td.td_cbp = 0; /* indicate 0 length packet */ 561 cur->nexttd = next; 562 cur->td.td_nexttd = HTOO32(next->physaddr); 563 cur->td.td_be = ~0; 564 cur->len = 0; 565 cur->flags = 0; 566 cur->xfer = xfer; 567 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 569 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 570 } 571 *ep = cur; 572 573 return (USBD_NORMAL_COMPLETION); 574 575 nomem: 576 /* XXX free chain */ 577 return (USBD_NOMEM); 578 } 579 580 #if 0 581 Static void 582 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 583 ohci_soft_td_t *stdend) 584 { 585 ohci_soft_td_t *p; 586 587 for (; std != stdend; std = p) { 588 p = std->nexttd; 589 ohci_free_std(sc, std); 590 } 591 } 592 #endif 593 594 ohci_soft_itd_t * 595 ohci_alloc_sitd(ohci_softc_t *sc) 596 { 597 ohci_soft_itd_t *sitd; 598 usbd_status err; 599 int i, offs; 600 usb_dma_t dma; 601 602 if (sc->sc_freeitds == NULL) { 603 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 604 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 605 OHCI_ITD_ALIGN, &dma); 606 if (err) 607 return (NULL); 608 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 609 offs = i * OHCI_SITD_SIZE; 610 sitd = KERNADDR(&dma, offs); 611 sitd->physaddr = DMAADDR(&dma, offs); 612 sitd->dma = dma; 613 sitd->offs = offs; 614 sitd->nextitd = sc->sc_freeitds; 615 sc->sc_freeitds = sitd; 616 } 617 } 618 619 sitd = sc->sc_freeitds; 620 sc->sc_freeitds = sitd->nextitd; 621 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 622 sitd->nextitd = NULL; 623 sitd->xfer = NULL; 624 ohci_hash_add_itd(sc, sitd); 625 626 #ifdef DIAGNOSTIC 627 sitd->isdone = 0; 628 #endif 629 630 return (sitd); 631 } 632 633 void 634 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 635 { 636 637 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 638 639 #ifdef DIAGNOSTIC 640 if (!sitd->isdone) { 641 panic("ohci_free_sitd: sitd=%p not done", sitd); 642 return; 643 } 644 /* Warn double free */ 645 sitd->isdone = 0; 646 #endif 647 648 ohci_hash_rem_itd(sc, sitd); 649 sitd->nextitd = sc->sc_freeitds; 650 sc->sc_freeitds = sitd; 651 } 652 653 usbd_status 654 ohci_init(ohci_softc_t *sc) 655 { 656 ohci_soft_ed_t *sed, *psed; 657 usbd_status err; 658 int i; 659 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 660 661 DPRINTF(("ohci_init: start\n")); 662 aprint_normal_dev(sc->sc_dev, ""); 663 664 sc->sc_hcca = NULL; 665 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 666 667 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 668 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 669 cv_init(&sc->sc_softwake_cv, "ohciab"); 670 671 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 672 ohci_rhsc_softint, sc); 673 674 for (i = 0; i < OHCI_HASH_SIZE; i++) 675 LIST_INIT(&sc->sc_hash_tds[i]); 676 for (i = 0; i < OHCI_HASH_SIZE; i++) 677 LIST_INIT(&sc->sc_hash_itds[i]); 678 679 SIMPLEQ_INIT(&sc->sc_free_xfers); 680 681 rev = OREAD4(sc, OHCI_REVISION); 682 aprint_normal("OHCI version %d.%d%s\n", 683 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 684 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 685 686 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 687 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 688 sc->sc_bus.usbrev = USBREV_UNKNOWN; 689 return (USBD_INVAL); 690 } 691 sc->sc_bus.usbrev = USBREV_1_0; 692 693 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 694 USB_MEM_RESERVE); 695 696 /* XXX determine alignment by R/W */ 697 /* Allocate the HCCA area. */ 698 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 699 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 700 if (err) { 701 sc->sc_hcca = NULL; 702 return err; 703 } 704 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 705 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 706 707 sc->sc_eintrs = OHCI_NORMAL_INTRS; 708 709 /* Allocate dummy ED that starts the control list. */ 710 sc->sc_ctrl_head = ohci_alloc_sed(sc); 711 if (sc->sc_ctrl_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad1; 714 } 715 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 717 /* Allocate dummy ED that starts the bulk list. */ 718 sc->sc_bulk_head = ohci_alloc_sed(sc); 719 if (sc->sc_bulk_head == NULL) { 720 err = USBD_NOMEM; 721 goto bad2; 722 } 723 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 724 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 725 sizeof(sc->sc_bulk_head->ed), 726 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 727 728 /* Allocate dummy ED that starts the isochronous list. */ 729 sc->sc_isoc_head = ohci_alloc_sed(sc); 730 if (sc->sc_isoc_head == NULL) { 731 err = USBD_NOMEM; 732 goto bad3; 733 } 734 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 735 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 736 sizeof(sc->sc_isoc_head->ed), 737 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 738 739 /* Allocate all the dummy EDs that make up the interrupt tree. */ 740 for (i = 0; i < OHCI_NO_EDS; i++) { 741 sed = ohci_alloc_sed(sc); 742 if (sed == NULL) { 743 while (--i >= 0) 744 ohci_free_sed(sc, sc->sc_eds[i]); 745 err = USBD_NOMEM; 746 goto bad4; 747 } 748 /* All ED fields are set to 0. */ 749 sc->sc_eds[i] = sed; 750 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 751 if (i != 0) 752 psed = sc->sc_eds[(i-1) / 2]; 753 else 754 psed= sc->sc_isoc_head; 755 sed->next = psed; 756 sed->ed.ed_nexted = HTOO32(psed->physaddr); 757 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 758 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 759 } 760 /* 761 * Fill HCCA interrupt table. The bit reversal is to get 762 * the tree set up properly to spread the interrupts. 763 */ 764 for (i = 0; i < OHCI_NO_INTRS; i++) 765 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 766 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 767 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 768 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 769 770 #ifdef OHCI_DEBUG 771 if (ohcidebug > 15) { 772 for (i = 0; i < OHCI_NO_EDS; i++) { 773 printf("ed#%d ", i); 774 ohci_dump_ed(sc, sc->sc_eds[i]); 775 } 776 printf("iso "); 777 ohci_dump_ed(sc, sc->sc_isoc_head); 778 } 779 #endif 780 781 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 782 ctl = OREAD4(sc, OHCI_CONTROL); 783 rwc = ctl & OHCI_RWC; 784 fm = OREAD4(sc, OHCI_FM_INTERVAL); 785 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 786 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 787 788 /* Determine in what context we are running. */ 789 if (ctl & OHCI_IR) { 790 /* SMM active, request change */ 791 DPRINTF(("ohci_init: SMM active, request owner change\n")); 792 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 793 (OHCI_OC | OHCI_MIE)) 794 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 795 s = OREAD4(sc, OHCI_COMMAND_STATUS); 796 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 797 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 798 usb_delay_ms(&sc->sc_bus, 1); 799 ctl = OREAD4(sc, OHCI_CONTROL); 800 } 801 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 802 if ((ctl & OHCI_IR) == 0) { 803 aprint_error_dev(sc->sc_dev, 804 "SMM does not respond, resetting\n"); 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 806 goto reset; 807 } 808 #if 0 809 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 810 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 811 /* BIOS started controller. */ 812 DPRINTF(("ohci_init: BIOS active\n")); 813 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 814 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 815 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 816 } 817 #endif 818 } else { 819 DPRINTF(("ohci_init: cold started\n")); 820 reset: 821 /* Controller was cold started. */ 822 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 823 } 824 825 /* 826 * This reset should not be necessary according to the OHCI spec, but 827 * without it some controllers do not start. 828 */ 829 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 830 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 831 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 832 833 /* We now own the host controller and the bus has been reset. */ 834 835 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 836 /* Nominal time for a reset is 10 us. */ 837 for (i = 0; i < 10; i++) { 838 delay(10); 839 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 840 if (!hcr) 841 break; 842 } 843 if (hcr) { 844 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 845 err = USBD_IOERROR; 846 goto bad5; 847 } 848 #ifdef OHCI_DEBUG 849 if (ohcidebug > 15) 850 ohci_dumpregs(sc); 851 #endif 852 853 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 854 855 /* Set up HC registers. */ 856 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 857 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 858 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 859 /* disable all interrupts and then switch on all desired interrupts */ 860 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 861 /* switch on desired functional features */ 862 ctl = OREAD4(sc, OHCI_CONTROL); 863 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 864 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 865 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 866 /* And finally start it! */ 867 OWRITE4(sc, OHCI_CONTROL, ctl); 868 869 /* 870 * The controller is now OPERATIONAL. Set a some final 871 * registers that should be set earlier, but that the 872 * controller ignores when in the SUSPEND state. 873 */ 874 ival = OHCI_GET_IVAL(fm); 875 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 876 fm |= OHCI_FSMPS(ival) | ival; 877 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 878 per = OHCI_PERIODIC(ival); /* 90% periodic */ 879 OWRITE4(sc, OHCI_PERIODIC_START, per); 880 881 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 882 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 883 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 884 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 885 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 886 887 /* 888 * The AMD756 requires a delay before re-reading the register, 889 * otherwise it will occasionally report 0 ports. 890 */ 891 sc->sc_noport = 0; 892 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 893 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 894 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 895 } 896 897 #ifdef OHCI_DEBUG 898 if (ohcidebug > 5) 899 ohci_dumpregs(sc); 900 #endif 901 902 /* Set up the bus struct. */ 903 sc->sc_bus.methods = &ohci_bus_methods; 904 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 905 906 sc->sc_control = sc->sc_intre = 0; 907 908 /* Finally, turn on interrupts. */ 909 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 910 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 911 912 return (USBD_NORMAL_COMPLETION); 913 914 bad5: 915 for (i = 0; i < OHCI_NO_EDS; i++) 916 ohci_free_sed(sc, sc->sc_eds[i]); 917 bad4: 918 ohci_free_sed(sc, sc->sc_isoc_head); 919 bad3: 920 ohci_free_sed(sc, sc->sc_bulk_head); 921 bad2: 922 ohci_free_sed(sc, sc->sc_ctrl_head); 923 bad1: 924 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 925 sc->sc_hcca = NULL; 926 return (err); 927 } 928 929 usbd_status 930 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 931 { 932 struct ohci_softc *sc = bus->hci_private; 933 usbd_status status; 934 935 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 936 if (status == USBD_NOMEM) 937 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 938 return status; 939 } 940 941 void 942 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 943 { 944 struct ohci_softc *sc = bus->hci_private; 945 if (dma->block->flags & USB_DMA_RESERVE) { 946 usb_reserve_freem(&sc->sc_dma_reserve, dma); 947 return; 948 } 949 usb_freemem(&sc->sc_bus, dma); 950 } 951 952 usbd_xfer_handle 953 ohci_allocx(struct usbd_bus *bus) 954 { 955 struct ohci_softc *sc = bus->hci_private; 956 usbd_xfer_handle xfer; 957 958 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 959 if (xfer != NULL) { 960 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 961 #ifdef DIAGNOSTIC 962 if (xfer->busy_free != XFER_FREE) { 963 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 964 xfer->busy_free); 965 } 966 #endif 967 } else { 968 xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP); 969 } 970 if (xfer != NULL) { 971 memset(xfer, 0, sizeof (struct ohci_xfer)); 972 #ifdef DIAGNOSTIC 973 xfer->busy_free = XFER_BUSY; 974 #endif 975 } 976 return (xfer); 977 } 978 979 void 980 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 981 { 982 struct ohci_softc *sc = bus->hci_private; 983 984 #ifdef DIAGNOSTIC 985 if (xfer->busy_free != XFER_BUSY) { 986 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 987 xfer->busy_free); 988 } 989 xfer->busy_free = XFER_FREE; 990 #endif 991 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 992 } 993 994 Static void 995 ohci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread) 996 { 997 struct ohci_softc *sc = bus->hci_private; 998 999 *intr = &sc->sc_intr_lock; 1000 *thread = &sc->sc_lock; 1001 } 1002 1003 /* 1004 * Shut down the controller when the system is going down. 1005 */ 1006 bool 1007 ohci_shutdown(device_t self, int flags) 1008 { 1009 ohci_softc_t *sc = device_private(self); 1010 1011 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1012 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1013 return true; 1014 } 1015 1016 bool 1017 ohci_resume(device_t dv, const pmf_qual_t *qual) 1018 { 1019 ohci_softc_t *sc = device_private(dv); 1020 uint32_t ctl; 1021 1022 mutex_spin_enter(&sc->sc_intr_lock); 1023 sc->sc_bus.use_polling++; 1024 mutex_spin_exit(&sc->sc_intr_lock); 1025 1026 /* Some broken BIOSes do not recover these values */ 1027 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1028 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1029 sc->sc_ctrl_head->physaddr); 1030 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1031 sc->sc_bulk_head->physaddr); 1032 if (sc->sc_intre) 1033 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1034 (OHCI_ALL_INTRS | OHCI_MIE)); 1035 if (sc->sc_control) 1036 ctl = sc->sc_control; 1037 else 1038 ctl = OREAD4(sc, OHCI_CONTROL); 1039 ctl |= OHCI_HCFS_RESUME; 1040 OWRITE4(sc, OHCI_CONTROL, ctl); 1041 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1042 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1043 OWRITE4(sc, OHCI_CONTROL, ctl); 1044 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1045 sc->sc_control = sc->sc_intre = 0; 1046 1047 mutex_spin_enter(&sc->sc_intr_lock); 1048 sc->sc_bus.use_polling--; 1049 mutex_spin_exit(&sc->sc_intr_lock); 1050 1051 return true; 1052 } 1053 1054 bool 1055 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1056 { 1057 ohci_softc_t *sc = device_private(dv); 1058 uint32_t ctl; 1059 1060 mutex_spin_enter(&sc->sc_intr_lock); 1061 sc->sc_bus.use_polling++; 1062 mutex_spin_exit(&sc->sc_intr_lock); 1063 1064 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1065 if (sc->sc_control == 0) { 1066 /* 1067 * Preserve register values, in case that BIOS 1068 * does not recover them. 1069 */ 1070 sc->sc_control = ctl; 1071 sc->sc_intre = OREAD4(sc, 1072 OHCI_INTERRUPT_ENABLE); 1073 } 1074 ctl |= OHCI_HCFS_SUSPEND; 1075 OWRITE4(sc, OHCI_CONTROL, ctl); 1076 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1077 1078 mutex_spin_enter(&sc->sc_intr_lock); 1079 sc->sc_bus.use_polling--; 1080 mutex_spin_exit(&sc->sc_intr_lock); 1081 1082 return true; 1083 } 1084 1085 #ifdef OHCI_DEBUG 1086 void 1087 ohci_dumpregs(ohci_softc_t *sc) 1088 { 1089 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1090 OREAD4(sc, OHCI_REVISION), 1091 OREAD4(sc, OHCI_CONTROL), 1092 OREAD4(sc, OHCI_COMMAND_STATUS))); 1093 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1094 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1095 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1096 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1097 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1098 OREAD4(sc, OHCI_HCCA), 1099 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1100 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1101 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1102 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1103 OREAD4(sc, OHCI_BULK_HEAD_ED), 1104 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1105 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1106 OREAD4(sc, OHCI_DONE_HEAD), 1107 OREAD4(sc, OHCI_FM_INTERVAL), 1108 OREAD4(sc, OHCI_FM_REMAINING))); 1109 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1110 OREAD4(sc, OHCI_FM_NUMBER), 1111 OREAD4(sc, OHCI_PERIODIC_START), 1112 OREAD4(sc, OHCI_LS_THRESHOLD))); 1113 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1114 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1115 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1116 OREAD4(sc, OHCI_RH_STATUS))); 1117 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1118 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1119 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1120 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1121 O32TOH(sc->sc_hcca->hcca_frame_number), 1122 O32TOH(sc->sc_hcca->hcca_done_head))); 1123 } 1124 #endif 1125 1126 Static int ohci_intr1(ohci_softc_t *); 1127 1128 int 1129 ohci_intr(void *p) 1130 { 1131 ohci_softc_t *sc = p; 1132 int ret = 0; 1133 1134 if (sc == NULL) 1135 return (0); 1136 1137 mutex_spin_enter(&sc->sc_intr_lock); 1138 1139 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1140 goto done; 1141 1142 /* If we get an interrupt while polling, then just ignore it. */ 1143 if (sc->sc_bus.use_polling) { 1144 #ifdef DIAGNOSTIC 1145 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1146 #endif 1147 /* for level triggered intrs, should do something to ack */ 1148 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1149 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1150 1151 goto done; 1152 } 1153 1154 ret = ohci_intr1(sc); 1155 1156 done: 1157 mutex_spin_exit(&sc->sc_intr_lock); 1158 return ret; 1159 } 1160 1161 Static int 1162 ohci_intr1(ohci_softc_t *sc) 1163 { 1164 u_int32_t intrs, eintrs; 1165 1166 DPRINTFN(14,("ohci_intr1: enter\n")); 1167 1168 /* In case the interrupt occurs before initialization has completed. */ 1169 if (sc == NULL || sc->sc_hcca == NULL) { 1170 #ifdef DIAGNOSTIC 1171 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1172 #endif 1173 return (0); 1174 } 1175 1176 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1177 1178 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1179 if (!intrs) 1180 return (0); 1181 1182 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1183 eintrs = intrs & sc->sc_eintrs; 1184 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1185 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1186 (u_int)eintrs, sc->sc_eintrs)); 1187 1188 if (!eintrs) { 1189 return (0); 1190 } 1191 1192 sc->sc_bus.intr_context++; 1193 sc->sc_bus.no_intrs++; 1194 if (eintrs & OHCI_SO) { 1195 sc->sc_overrun_cnt++; 1196 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1197 printf("%s: %u scheduling overruns\n", 1198 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1199 sc->sc_overrun_cnt = 0; 1200 } 1201 /* XXX do what */ 1202 eintrs &= ~OHCI_SO; 1203 } 1204 if (eintrs & OHCI_WDH) { 1205 /* 1206 * We block the interrupt below, and reenable it later from 1207 * ohci_softintr(). 1208 */ 1209 usb_schedsoftintr(&sc->sc_bus); 1210 } 1211 if (eintrs & OHCI_RD) { 1212 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1213 /* XXX process resume detect */ 1214 } 1215 if (eintrs & OHCI_UE) { 1216 printf("%s: unrecoverable error, controller halted\n", 1217 device_xname(sc->sc_dev)); 1218 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1219 /* XXX what else */ 1220 } 1221 if (eintrs & OHCI_RHSC) { 1222 /* 1223 * We block the interrupt below, and reenable it later from 1224 * a timeout. 1225 */ 1226 softint_schedule(sc->sc_rhsc_si); 1227 } 1228 1229 sc->sc_bus.intr_context--; 1230 1231 if (eintrs != 0) { 1232 /* Block unprocessed interrupts. */ 1233 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1234 sc->sc_eintrs &= ~eintrs; 1235 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1236 device_xname(sc->sc_dev), eintrs)); 1237 } 1238 1239 return (1); 1240 } 1241 1242 void 1243 ohci_rhsc_enable(void *v_sc) 1244 { 1245 ohci_softc_t *sc = v_sc; 1246 1247 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1248 mutex_spin_enter(&sc->sc_intr_lock); 1249 sc->sc_eintrs |= OHCI_RHSC; 1250 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1251 mutex_spin_exit(&sc->sc_intr_lock); 1252 } 1253 1254 #ifdef OHCI_DEBUG 1255 const char *ohci_cc_strs[] = { 1256 "NO_ERROR", 1257 "CRC", 1258 "BIT_STUFFING", 1259 "DATA_TOGGLE_MISMATCH", 1260 "STALL", 1261 "DEVICE_NOT_RESPONDING", 1262 "PID_CHECK_FAILURE", 1263 "UNEXPECTED_PID", 1264 "DATA_OVERRUN", 1265 "DATA_UNDERRUN", 1266 "BUFFER_OVERRUN", 1267 "BUFFER_UNDERRUN", 1268 "reserved", 1269 "reserved", 1270 "NOT_ACCESSED", 1271 "NOT_ACCESSED", 1272 }; 1273 #endif 1274 1275 void 1276 ohci_softintr(void *v) 1277 { 1278 struct usbd_bus *bus = v; 1279 ohci_softc_t *sc = bus->hci_private; 1280 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1281 ohci_soft_td_t *std, *sdone, *stdnext; 1282 usbd_xfer_handle xfer; 1283 struct ohci_pipe *opipe; 1284 int len, cc; 1285 int i, j, actlen, iframes, uedir; 1286 ohci_physaddr_t done; 1287 1288 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1289 1290 DPRINTFN(10,("ohci_softintr: enter\n")); 1291 1292 sc->sc_bus.intr_context++; 1293 1294 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1295 sizeof(sc->sc_hcca->hcca_done_head), 1296 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1297 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1298 sc->sc_hcca->hcca_done_head = 0; 1299 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1300 sizeof(sc->sc_hcca->hcca_done_head), 1301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1302 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1303 sc->sc_eintrs |= OHCI_WDH; 1304 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1305 1306 /* Reverse the done list. */ 1307 for (sdone = NULL, sidone = NULL; done != 0; ) { 1308 std = ohci_hash_find_td(sc, done); 1309 if (std != NULL) { 1310 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1312 std->dnext = sdone; 1313 done = O32TOH(std->td.td_nexttd); 1314 sdone = std; 1315 DPRINTFN(10,("add TD %p\n", std)); 1316 continue; 1317 } 1318 sitd = ohci_hash_find_itd(sc, done); 1319 if (sitd != NULL) { 1320 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1322 sitd->dnext = sidone; 1323 done = O32TOH(sitd->itd.itd_nextitd); 1324 sidone = sitd; 1325 DPRINTFN(5,("add ITD %p\n", sitd)); 1326 continue; 1327 } 1328 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1329 (u_long)done); 1330 break; 1331 } 1332 1333 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1334 1335 #ifdef OHCI_DEBUG 1336 if (ohcidebug > 10) { 1337 DPRINTF(("ohci_process_done: TD done:\n")); 1338 ohci_dump_tds(sc, sdone); 1339 } 1340 #endif 1341 1342 for (std = sdone; std; std = stdnext) { 1343 xfer = std->xfer; 1344 stdnext = std->dnext; 1345 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1346 std, xfer, xfer ? xfer->hcpriv : 0)); 1347 if (xfer == NULL) { 1348 /* 1349 * xfer == NULL: There seems to be no xfer associated 1350 * with this TD. It is tailp that happened to end up on 1351 * the done queue. 1352 * Shouldn't happen, but some chips are broken(?). 1353 */ 1354 continue; 1355 } 1356 if (xfer->status == USBD_CANCELLED || 1357 xfer->status == USBD_TIMEOUT) { 1358 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1359 xfer)); 1360 /* Handled by abort routine. */ 1361 continue; 1362 } 1363 callout_stop(&xfer->timeout_handle); 1364 1365 len = std->len; 1366 if (std->td.td_cbp != 0) 1367 len -= O32TOH(std->td.td_be) - 1368 O32TOH(std->td.td_cbp) + 1; 1369 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1370 std->flags)); 1371 if (std->flags & OHCI_ADD_LEN) 1372 xfer->actlen += len; 1373 1374 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1375 if (cc == OHCI_CC_NO_ERROR) { 1376 if (std->flags & OHCI_CALL_DONE) { 1377 xfer->status = USBD_NORMAL_COMPLETION; 1378 usb_transfer_complete(xfer); 1379 } 1380 ohci_free_std(sc, std); 1381 } else { 1382 /* 1383 * Endpoint is halted. First unlink all the TDs 1384 * belonging to the failed transfer, and then restart 1385 * the endpoint. 1386 */ 1387 ohci_soft_td_t *p, *n; 1388 opipe = (struct ohci_pipe *)xfer->pipe; 1389 1390 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1391 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1392 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1393 1394 /* remove TDs */ 1395 for (p = std; p->xfer == xfer; p = n) { 1396 n = p->nexttd; 1397 ohci_free_std(sc, p); 1398 } 1399 1400 /* clear halt */ 1401 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1402 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1403 1404 if (cc == OHCI_CC_STALL) 1405 xfer->status = USBD_STALLED; 1406 else 1407 xfer->status = USBD_IOERROR; 1408 usb_transfer_complete(xfer); 1409 } 1410 } 1411 1412 #ifdef OHCI_DEBUG 1413 if (ohcidebug > 10) { 1414 DPRINTF(("ohci_softintr: ITD done:\n")); 1415 ohci_dump_itds(sc, sidone); 1416 } 1417 #endif 1418 1419 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1420 xfer = sitd->xfer; 1421 sitdnext = sitd->dnext; 1422 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1423 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1424 if (xfer == NULL) 1425 continue; 1426 if (xfer->status == USBD_CANCELLED || 1427 xfer->status == USBD_TIMEOUT) { 1428 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1429 xfer)); 1430 /* Handled by abort routine. */ 1431 continue; 1432 } 1433 #ifdef DIAGNOSTIC 1434 if (sitd->isdone) 1435 printf("ohci_softintr: sitd=%p is done\n", sitd); 1436 sitd->isdone = 1; 1437 #endif 1438 if (sitd->flags & OHCI_CALL_DONE) { 1439 ohci_soft_itd_t *next; 1440 1441 opipe = (struct ohci_pipe *)xfer->pipe; 1442 opipe->u.iso.inuse -= xfer->nframes; 1443 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1444 bEndpointAddress); 1445 xfer->status = USBD_NORMAL_COMPLETION; 1446 actlen = 0; 1447 for (i = 0, sitd = xfer->hcpriv;; 1448 sitd = next) { 1449 next = sitd->nextitd; 1450 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1451 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1452 xfer->status = USBD_IOERROR; 1453 /* For input, update frlengths with actual */ 1454 /* XXX anything necessary for output? */ 1455 if (uedir == UE_DIR_IN && 1456 xfer->status == USBD_NORMAL_COMPLETION) { 1457 iframes = OHCI_ITD_GET_FC(O32TOH( 1458 sitd->itd.itd_flags)); 1459 for (j = 0; j < iframes; i++, j++) { 1460 len = O16TOH(sitd-> 1461 itd.itd_offset[j]); 1462 if ((OHCI_ITD_PSW_GET_CC(len) & 1463 OHCI_CC_NOT_ACCESSED_MASK) 1464 == OHCI_CC_NOT_ACCESSED) 1465 len = 0; 1466 else 1467 len = OHCI_ITD_PSW_LENGTH(len); 1468 xfer->frlengths[i] = len; 1469 actlen += len; 1470 } 1471 } 1472 if (sitd->flags & OHCI_CALL_DONE) 1473 break; 1474 ohci_free_sitd(sc, sitd); 1475 } 1476 ohci_free_sitd(sc, sitd); 1477 if (uedir == UE_DIR_IN && 1478 xfer->status == USBD_NORMAL_COMPLETION) 1479 xfer->actlen = actlen; 1480 xfer->hcpriv = NULL; 1481 1482 usb_transfer_complete(xfer); 1483 } 1484 } 1485 1486 if (sc->sc_softwake) { 1487 sc->sc_softwake = 0; 1488 cv_broadcast(&sc->sc_softwake_cv); 1489 } 1490 1491 sc->sc_bus.intr_context--; 1492 1493 DPRINTFN(10,("ohci_softintr: done:\n")); 1494 } 1495 1496 void 1497 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1498 { 1499 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1500 #ifdef DIAGNOSTIC 1501 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1502 #endif 1503 int len = UGETW(xfer->request.wLength); 1504 int isread = (xfer->request.bmRequestType & UT_READ); 1505 1506 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1507 1508 KASSERT(mutex_owned(&sc->sc_lock)); 1509 1510 #ifdef DIAGNOSTIC 1511 if (!(xfer->rqflags & URQ_REQUEST)) { 1512 panic("ohci_device_ctrl_done: not a request"); 1513 } 1514 #endif 1515 if (len) 1516 usb_syncmem(&xfer->dmabuf, 0, len, 1517 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1518 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1519 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1520 } 1521 1522 void 1523 ohci_device_intr_done(usbd_xfer_handle xfer) 1524 { 1525 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1526 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1527 ohci_soft_ed_t *sed = opipe->sed; 1528 ohci_soft_td_t *data, *tail; 1529 int isread = 1530 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1531 1532 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1533 xfer, xfer->actlen)); 1534 1535 KASSERT(mutex_owned(&sc->sc_lock)); 1536 1537 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1538 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1539 if (xfer->pipe->repeat) { 1540 data = opipe->tail.td; 1541 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1542 if (tail == NULL) { 1543 xfer->status = USBD_NOMEM; 1544 return; 1545 } 1546 tail->xfer = NULL; 1547 1548 data->td.td_flags = HTOO32( 1549 OHCI_TD_IN | OHCI_TD_NOCC | 1550 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1551 if (xfer->flags & USBD_SHORT_XFER_OK) 1552 data->td.td_flags |= HTOO32(OHCI_TD_R); 1553 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1554 data->nexttd = tail; 1555 data->td.td_nexttd = HTOO32(tail->physaddr); 1556 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1557 xfer->length - 1); 1558 data->len = xfer->length; 1559 data->xfer = xfer; 1560 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1561 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1563 xfer->hcpriv = data; 1564 xfer->actlen = 0; 1565 1566 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1567 usb_syncmem(&sed->dma, 1568 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1569 sizeof(sed->ed.ed_tailp), 1570 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1571 opipe->tail.td = tail; 1572 } 1573 } 1574 1575 void 1576 ohci_device_bulk_done(usbd_xfer_handle xfer) 1577 { 1578 #ifdef DIAGNOSTIC 1579 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1580 #endif 1581 int isread = 1582 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1583 1584 KASSERT(mutex_owned(&sc->sc_lock)); 1585 1586 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1587 xfer, xfer->actlen)); 1588 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1589 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1590 } 1591 1592 Static void 1593 ohci_rhsc_softint(void *arg) 1594 { 1595 ohci_softc_t *sc = arg; 1596 1597 mutex_enter(&sc->sc_lock); 1598 1599 ohci_rhsc(sc, sc->sc_intrxfer); 1600 1601 /* Do not allow RHSC interrupts > 1 per second */ 1602 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1603 1604 mutex_exit(&sc->sc_lock); 1605 } 1606 1607 void 1608 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1609 { 1610 usbd_pipe_handle pipe; 1611 u_char *p; 1612 int i, m; 1613 int hstatus; 1614 1615 KASSERT(mutex_owned(&sc->sc_lock)); 1616 1617 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1618 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1619 sc, xfer, hstatus)); 1620 1621 if (xfer == NULL) { 1622 /* Just ignore the change. */ 1623 return; 1624 } 1625 1626 pipe = xfer->pipe; 1627 1628 p = KERNADDR(&xfer->dmabuf, 0); 1629 m = min(sc->sc_noport, xfer->length * 8 - 1); 1630 memset(p, 0, xfer->length); 1631 for (i = 1; i <= m; i++) { 1632 /* Pick out CHANGE bits from the status reg. */ 1633 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1634 p[i/8] |= 1 << (i%8); 1635 } 1636 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1637 xfer->actlen = xfer->length; 1638 xfer->status = USBD_NORMAL_COMPLETION; 1639 1640 usb_transfer_complete(xfer); 1641 } 1642 1643 void 1644 ohci_root_intr_done(usbd_xfer_handle xfer) 1645 { 1646 } 1647 1648 void 1649 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1650 { 1651 } 1652 1653 /* 1654 * Wait here until controller claims to have an interrupt. 1655 * Then call ohci_intr and return. Use timeout to avoid waiting 1656 * too long. 1657 */ 1658 void 1659 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1660 { 1661 int timo; 1662 u_int32_t intrs; 1663 1664 mutex_enter(&sc->sc_lock); 1665 1666 xfer->status = USBD_IN_PROGRESS; 1667 for (timo = xfer->timeout; timo >= 0; timo--) { 1668 usb_delay_ms(&sc->sc_bus, 1); 1669 if (sc->sc_dying) 1670 break; 1671 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1672 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1673 #ifdef OHCI_DEBUG 1674 if (ohcidebug > 15) 1675 ohci_dumpregs(sc); 1676 #endif 1677 if (intrs) { 1678 mutex_spin_enter(&sc->sc_intr_lock); 1679 ohci_intr1(sc); 1680 mutex_spin_exit(&sc->sc_intr_lock); 1681 if (xfer->status != USBD_IN_PROGRESS) 1682 return; 1683 } 1684 } 1685 1686 /* Timeout */ 1687 DPRINTF(("ohci_waitintr: timeout\n")); 1688 xfer->status = USBD_TIMEOUT; 1689 usb_transfer_complete(xfer); 1690 1691 /* XXX should free TD */ 1692 1693 mutex_exit(&sc->sc_lock); 1694 } 1695 1696 void 1697 ohci_poll(struct usbd_bus *bus) 1698 { 1699 ohci_softc_t *sc = bus->hci_private; 1700 #ifdef OHCI_DEBUG 1701 static int last; 1702 int new; 1703 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1704 if (new != last) { 1705 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1706 last = new; 1707 } 1708 #endif 1709 1710 sc->sc_eintrs |= OHCI_WDH; 1711 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1712 mutex_spin_enter(&sc->sc_intr_lock); 1713 ohci_intr1(sc); 1714 mutex_spin_exit(&sc->sc_intr_lock); 1715 } 1716 } 1717 1718 usbd_status 1719 ohci_device_request(usbd_xfer_handle xfer) 1720 { 1721 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1722 usb_device_request_t *req = &xfer->request; 1723 usbd_device_handle dev = opipe->pipe.device; 1724 ohci_softc_t *sc = dev->bus->hci_private; 1725 int addr = dev->address; 1726 ohci_soft_td_t *setup, *stat, *next, *tail; 1727 ohci_soft_ed_t *sed; 1728 int isread; 1729 int len; 1730 usbd_status err; 1731 1732 KASSERT(mutex_owned(&sc->sc_lock)); 1733 1734 isread = req->bmRequestType & UT_READ; 1735 len = UGETW(req->wLength); 1736 1737 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1738 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1739 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1740 UGETW(req->wIndex), len, addr, 1741 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1742 1743 setup = opipe->tail.td; 1744 stat = ohci_alloc_std(sc); 1745 if (stat == NULL) { 1746 err = USBD_NOMEM; 1747 goto bad1; 1748 } 1749 tail = ohci_alloc_std(sc); 1750 if (tail == NULL) { 1751 err = USBD_NOMEM; 1752 goto bad2; 1753 } 1754 tail->xfer = NULL; 1755 1756 sed = opipe->sed; 1757 opipe->u.ctl.length = len; 1758 1759 /* Update device address and length since they may have changed 1760 during the setup of the control pipe in usbd_new_device(). */ 1761 /* XXX This only needs to be done once, but it's too early in open. */ 1762 /* XXXX Should not touch ED here! */ 1763 1764 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1765 sizeof(sed->ed.ed_flags), 1766 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1767 sed->ed.ed_flags = HTOO32( 1768 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1769 OHCI_ED_SET_FA(addr) | 1770 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1771 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1772 sizeof(sed->ed.ed_flags), 1773 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1774 1775 next = stat; 1776 1777 /* Set up data transaction */ 1778 if (len != 0) { 1779 ohci_soft_td_t *std = stat; 1780 1781 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1782 std, &stat); 1783 stat = stat->nexttd; /* point at free TD */ 1784 if (err) 1785 goto bad3; 1786 /* Start toggle at 1 and then use the carried toggle. */ 1787 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1788 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1789 usb_syncmem(&std->dma, 1790 std->offs + offsetof(ohci_td_t, td_flags), 1791 sizeof(std->td.td_flags), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 } 1794 1795 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1796 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1797 1798 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1799 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1800 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1801 setup->nexttd = next; 1802 setup->td.td_nexttd = HTOO32(next->physaddr); 1803 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1804 setup->len = 0; 1805 setup->xfer = xfer; 1806 setup->flags = 0; 1807 xfer->hcpriv = setup; 1808 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1810 1811 stat->td.td_flags = HTOO32( 1812 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1813 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1814 stat->td.td_cbp = 0; 1815 stat->nexttd = tail; 1816 stat->td.td_nexttd = HTOO32(tail->physaddr); 1817 stat->td.td_be = 0; 1818 stat->flags = OHCI_CALL_DONE; 1819 stat->len = 0; 1820 stat->xfer = xfer; 1821 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1823 1824 #ifdef OHCI_DEBUG 1825 if (ohcidebug > 5) { 1826 DPRINTF(("ohci_device_request:\n")); 1827 ohci_dump_ed(sc, sed); 1828 ohci_dump_tds(sc, setup); 1829 } 1830 #endif 1831 1832 /* Insert ED in schedule */ 1833 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1834 usb_syncmem(&sed->dma, 1835 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1836 sizeof(sed->ed.ed_tailp), 1837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1838 opipe->tail.td = tail; 1839 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1840 if (xfer->timeout && !sc->sc_bus.use_polling) { 1841 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1842 ohci_timeout, xfer); 1843 } 1844 1845 #ifdef OHCI_DEBUG 1846 if (ohcidebug > 20) { 1847 delay(10000); 1848 DPRINTF(("ohci_device_request: status=%x\n", 1849 OREAD4(sc, OHCI_COMMAND_STATUS))); 1850 ohci_dumpregs(sc); 1851 printf("ctrl head:\n"); 1852 ohci_dump_ed(sc, sc->sc_ctrl_head); 1853 printf("sed:\n"); 1854 ohci_dump_ed(sc, sed); 1855 ohci_dump_tds(sc, setup); 1856 } 1857 #endif 1858 1859 return (USBD_NORMAL_COMPLETION); 1860 1861 bad3: 1862 ohci_free_std(sc, tail); 1863 bad2: 1864 ohci_free_std(sc, stat); 1865 bad1: 1866 return (err); 1867 } 1868 1869 /* 1870 * Add an ED to the schedule. Called with USB thread lock held. 1871 */ 1872 Static void 1873 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1874 { 1875 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1876 1877 KASSERT(mutex_owned(&sc->sc_lock)); 1878 1879 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1880 sizeof(head->ed.ed_nexted), 1881 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1882 sed->next = head->next; 1883 sed->ed.ed_nexted = head->ed.ed_nexted; 1884 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1885 sizeof(sed->ed.ed_nexted), 1886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1887 head->next = sed; 1888 head->ed.ed_nexted = HTOO32(sed->physaddr); 1889 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1890 sizeof(head->ed.ed_nexted), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 } 1893 1894 /* 1895 * Remove an ED from the schedule. Called with USB thread lock held. 1896 */ 1897 Static void 1898 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1899 { 1900 ohci_soft_ed_t *p; 1901 1902 KASSERT(mutex_owned(&sc->sc_lock)); 1903 1904 /* XXX */ 1905 for (p = head; p != NULL && p->next != sed; p = p->next) 1906 ; 1907 if (p == NULL) 1908 panic("ohci_rem_ed: ED not found"); 1909 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1910 sizeof(sed->ed.ed_nexted), 1911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1912 p->next = sed->next; 1913 p->ed.ed_nexted = sed->ed.ed_nexted; 1914 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1915 sizeof(p->ed.ed_nexted), 1916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1917 } 1918 1919 /* 1920 * When a transfer is completed the TD is added to the done queue by 1921 * the host controller. This queue is the processed by software. 1922 * Unfortunately the queue contains the physical address of the TD 1923 * and we have no simple way to translate this back to a kernel address. 1924 * To make the translation possible (and fast) we use a hash table of 1925 * TDs currently in the schedule. The physical address is used as the 1926 * hash value. 1927 */ 1928 1929 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1930 /* Called with USB thread lock held. */ 1931 void 1932 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1933 { 1934 int h = HASH(std->physaddr); 1935 1936 KASSERT(mutex_owned(&sc->sc_lock)); 1937 1938 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1939 } 1940 1941 /* Called with USB thread lock held. */ 1942 void 1943 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1944 { 1945 1946 KASSERT(mutex_owned(&sc->sc_lock)); 1947 1948 LIST_REMOVE(std, hnext); 1949 } 1950 1951 ohci_soft_td_t * 1952 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1953 { 1954 int h = HASH(a); 1955 ohci_soft_td_t *std; 1956 1957 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1958 std != NULL; 1959 std = LIST_NEXT(std, hnext)) 1960 if (std->physaddr == a) 1961 return (std); 1962 return (NULL); 1963 } 1964 1965 /* Called with USB thread lock held. */ 1966 void 1967 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1968 { 1969 int h = HASH(sitd->physaddr); 1970 1971 KASSERT(mutex_owned(&sc->sc_lock)); 1972 1973 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1974 sitd, (u_long)sitd->physaddr)); 1975 1976 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1977 } 1978 1979 /* Called with USB thread lock held. */ 1980 void 1981 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1982 { 1983 KASSERT(mutex_owned(&sc->sc_lock)); 1984 1985 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1986 sitd, (u_long)sitd->physaddr)); 1987 1988 LIST_REMOVE(sitd, hnext); 1989 } 1990 1991 ohci_soft_itd_t * 1992 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1993 { 1994 int h = HASH(a); 1995 ohci_soft_itd_t *sitd; 1996 1997 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1998 sitd != NULL; 1999 sitd = LIST_NEXT(sitd, hnext)) 2000 if (sitd->physaddr == a) 2001 return (sitd); 2002 return (NULL); 2003 } 2004 2005 void 2006 ohci_timeout(void *addr) 2007 { 2008 struct ohci_xfer *oxfer = addr; 2009 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2010 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2011 2012 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2013 2014 if (sc->sc_dying) { 2015 mutex_enter(&sc->sc_lock); 2016 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2017 mutex_exit(&sc->sc_lock); 2018 return; 2019 } 2020 2021 /* Execute the abort in a process context. */ 2022 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 2023 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2024 USB_TASKQ_HC); 2025 } 2026 2027 void 2028 ohci_timeout_task(void *addr) 2029 { 2030 usbd_xfer_handle xfer = addr; 2031 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2032 2033 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2034 2035 mutex_enter(&sc->sc_lock); 2036 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2037 mutex_exit(&sc->sc_lock); 2038 } 2039 2040 #ifdef OHCI_DEBUG 2041 void 2042 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2043 { 2044 for (; std; std = std->nexttd) 2045 ohci_dump_td(sc, std); 2046 } 2047 2048 void 2049 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2050 { 2051 char sbuf[128]; 2052 2053 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2055 snprintb(sbuf, sizeof(sbuf), 2056 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2057 (u_int32_t)O32TOH(std->td.td_flags)); 2058 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2059 "nexttd=0x%08lx be=0x%08lx\n", 2060 std, (u_long)std->physaddr, sbuf, 2061 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2062 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2063 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2064 (u_long)O32TOH(std->td.td_cbp), 2065 (u_long)O32TOH(std->td.td_nexttd), 2066 (u_long)O32TOH(std->td.td_be)); 2067 } 2068 2069 void 2070 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2071 { 2072 int i; 2073 2074 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2075 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2076 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2077 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2078 sitd, (u_long)sitd->physaddr, 2079 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2080 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2081 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2082 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2083 (u_long)O32TOH(sitd->itd.itd_bp0), 2084 (u_long)O32TOH(sitd->itd.itd_nextitd), 2085 (u_long)O32TOH(sitd->itd.itd_be)); 2086 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2087 printf("offs[%d]=0x%04x ", i, 2088 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2089 printf("\n"); 2090 } 2091 2092 void 2093 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2094 { 2095 for (; sitd; sitd = sitd->nextitd) 2096 ohci_dump_itd(sc, sitd); 2097 } 2098 2099 void 2100 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2101 { 2102 char sbuf[128], sbuf2[128]; 2103 2104 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2105 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2106 snprintb(sbuf, sizeof(sbuf), 2107 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2108 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2109 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2110 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2111 2112 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2113 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2114 sed, (u_long)sed->physaddr, 2115 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2116 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2117 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2118 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2119 (u_long)O32TOH(sed->ed.ed_headp), 2120 (u_long)O32TOH(sed->ed.ed_nexted)); 2121 } 2122 #endif 2123 2124 usbd_status 2125 ohci_open(usbd_pipe_handle pipe) 2126 { 2127 usbd_device_handle dev = pipe->device; 2128 ohci_softc_t *sc = dev->bus->hci_private; 2129 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2130 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2131 u_int8_t addr = dev->address; 2132 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2133 ohci_soft_ed_t *sed; 2134 ohci_soft_td_t *std; 2135 ohci_soft_itd_t *sitd; 2136 ohci_physaddr_t tdphys; 2137 u_int32_t fmt; 2138 usbd_status err = USBD_NOMEM; 2139 int ival; 2140 2141 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2142 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2143 2144 if (sc->sc_dying) { 2145 err = USBD_IOERROR; 2146 goto bad0; 2147 } 2148 2149 std = NULL; 2150 sed = NULL; 2151 2152 if (addr == sc->sc_addr) { 2153 switch (ed->bEndpointAddress) { 2154 case USB_CONTROL_ENDPOINT: 2155 pipe->methods = &ohci_root_ctrl_methods; 2156 break; 2157 case UE_DIR_IN | OHCI_INTR_ENDPT: 2158 pipe->methods = &ohci_root_intr_methods; 2159 break; 2160 default: 2161 err = USBD_INVAL; 2162 goto bad0; 2163 } 2164 } else { 2165 sed = ohci_alloc_sed(sc); 2166 if (sed == NULL) 2167 goto bad0; 2168 opipe->sed = sed; 2169 if (xfertype == UE_ISOCHRONOUS) { 2170 mutex_enter(&sc->sc_lock); 2171 sitd = ohci_alloc_sitd(sc); 2172 mutex_exit(&sc->sc_lock); 2173 if (sitd == NULL) 2174 goto bad1; 2175 opipe->tail.itd = sitd; 2176 tdphys = sitd->physaddr; 2177 fmt = OHCI_ED_FORMAT_ISO; 2178 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2179 fmt |= OHCI_ED_DIR_IN; 2180 else 2181 fmt |= OHCI_ED_DIR_OUT; 2182 } else { 2183 mutex_enter(&sc->sc_lock); 2184 std = ohci_alloc_std(sc); 2185 mutex_exit(&sc->sc_lock); 2186 if (std == NULL) 2187 goto bad1; 2188 opipe->tail.td = std; 2189 tdphys = std->physaddr; 2190 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2191 } 2192 sed->ed.ed_flags = HTOO32( 2193 OHCI_ED_SET_FA(addr) | 2194 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2195 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2196 fmt | 2197 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2198 sed->ed.ed_headp = HTOO32(tdphys | 2199 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2200 sed->ed.ed_tailp = HTOO32(tdphys); 2201 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2202 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2203 2204 switch (xfertype) { 2205 case UE_CONTROL: 2206 pipe->methods = &ohci_device_ctrl_methods; 2207 err = usb_allocmem(&sc->sc_bus, 2208 sizeof(usb_device_request_t), 2209 0, &opipe->u.ctl.reqdma); 2210 if (err) 2211 goto bad; 2212 mutex_enter(&sc->sc_lock); 2213 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2214 mutex_exit(&sc->sc_lock); 2215 break; 2216 case UE_INTERRUPT: 2217 pipe->methods = &ohci_device_intr_methods; 2218 ival = pipe->interval; 2219 if (ival == USBD_DEFAULT_INTERVAL) 2220 ival = ed->bInterval; 2221 return (ohci_device_setintr(sc, opipe, ival)); 2222 case UE_ISOCHRONOUS: 2223 pipe->methods = &ohci_device_isoc_methods; 2224 return (ohci_setup_isoc(pipe)); 2225 case UE_BULK: 2226 pipe->methods = &ohci_device_bulk_methods; 2227 mutex_enter(&sc->sc_lock); 2228 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2229 mutex_exit(&sc->sc_lock); 2230 break; 2231 } 2232 } 2233 2234 return USBD_NORMAL_COMPLETION; 2235 2236 bad: 2237 if (std != NULL) 2238 ohci_free_std(sc, std); 2239 bad1: 2240 if (sed != NULL) 2241 ohci_free_sed(sc, sed); 2242 bad0: 2243 return err; 2244 2245 } 2246 2247 /* 2248 * Close a reqular pipe. 2249 * Assumes that there are no pending transactions. 2250 */ 2251 void 2252 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2253 { 2254 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2255 ohci_softc_t *sc = pipe->device->bus->hci_private; 2256 ohci_soft_ed_t *sed = opipe->sed; 2257 2258 KASSERT(mutex_owned(&sc->sc_lock)); 2259 2260 #ifdef DIAGNOSTIC 2261 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2262 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2263 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2264 ohci_soft_td_t *std; 2265 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2266 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2267 "tl=0x%x pipe=%p, std=%p\n", sed, 2268 (int)O32TOH(sed->ed.ed_headp), 2269 (int)O32TOH(sed->ed.ed_tailp), 2270 pipe, std); 2271 #ifdef USB_DEBUG 2272 usbd_dump_pipe(&opipe->pipe); 2273 #endif 2274 #ifdef OHCI_DEBUG 2275 ohci_dump_ed(sc, sed); 2276 if (std) 2277 ohci_dump_td(sc, std); 2278 #endif 2279 usb_delay_ms(&sc->sc_bus, 2); 2280 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2281 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2282 printf("ohci_close_pipe: pipe still not empty\n"); 2283 } 2284 #endif 2285 ohci_rem_ed(sc, sed, head); 2286 /* Make sure the host controller is not touching this ED */ 2287 usb_delay_ms(&sc->sc_bus, 1); 2288 pipe->endpoint->datatoggle = 2289 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2290 ohci_free_sed(sc, opipe->sed); 2291 } 2292 2293 /* 2294 * Abort a device request. 2295 * If this routine is called at splusb() it guarantees that the request 2296 * will be removed from the hardware scheduling and that the callback 2297 * for it will be called with USBD_CANCELLED status. 2298 * It's impossible to guarantee that the requested transfer will not 2299 * have happened since the hardware runs concurrently. 2300 * If the transaction has already happened we rely on the ordinary 2301 * interrupt processing to process it. 2302 */ 2303 void 2304 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2305 { 2306 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2307 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2308 ohci_soft_ed_t *sed = opipe->sed; 2309 ohci_soft_td_t *p, *n; 2310 ohci_physaddr_t headp; 2311 int hit; 2312 int wake; 2313 2314 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2315 2316 KASSERT(mutex_owned(&sc->sc_lock)); 2317 2318 if (sc->sc_dying) { 2319 /* If we're dying, just do the software part. */ 2320 xfer->status = status; /* make software ignore it */ 2321 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2322 usb_transfer_complete(xfer); 2323 return; 2324 } 2325 2326 if (xfer->device->bus->intr_context || !curproc) 2327 panic("ohci_abort_xfer: not in process context"); 2328 2329 /* 2330 * If an abort is already in progress then just wait for it to 2331 * complete and return. 2332 */ 2333 if (xfer->hcflags & UXFER_ABORTING) { 2334 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2335 #ifdef DIAGNOSTIC 2336 if (status == USBD_TIMEOUT) 2337 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2338 #endif 2339 /* Override the status which might be USBD_TIMEOUT. */ 2340 xfer->status = status; 2341 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2342 xfer->hcflags |= UXFER_ABORTWAIT; 2343 while (xfer->hcflags & UXFER_ABORTING) 2344 cv_wait(&xfer->hccv, &sc->sc_lock); 2345 goto done; 2346 return; 2347 } 2348 xfer->hcflags |= UXFER_ABORTING; 2349 2350 /* 2351 * Step 1: Make interrupt routine and hardware ignore xfer. 2352 */ 2353 xfer->status = status; /* make software ignore it */ 2354 callout_stop(&xfer->timeout_handle); 2355 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2356 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2357 sizeof(sed->ed.ed_flags), 2358 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2359 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2360 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2361 sizeof(sed->ed.ed_flags), 2362 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2363 2364 /* 2365 * Step 2: Wait until we know hardware has finished any possible 2366 * use of the xfer. Also make sure the soft interrupt routine 2367 * has run. 2368 */ 2369 usb_delay_ms(opipe->pipe.device->bus, 20); /* Hardware finishes in 1ms */ 2370 sc->sc_softwake = 1; 2371 usb_schedsoftintr(&sc->sc_bus); 2372 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2373 2374 /* 2375 * Step 3: Remove any vestiges of the xfer from the hardware. 2376 * The complication here is that the hardware may have executed 2377 * beyond the xfer we're trying to abort. So as we're scanning 2378 * the TDs of this xfer we check if the hardware points to 2379 * any of them. 2380 */ 2381 p = xfer->hcpriv; 2382 #ifdef DIAGNOSTIC 2383 if (p == NULL) { 2384 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2385 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2386 goto done; 2387 } 2388 #endif 2389 #ifdef OHCI_DEBUG 2390 if (ohcidebug > 1) { 2391 DPRINTF(("ohci_abort_xfer: sed=\n")); 2392 ohci_dump_ed(sc, sed); 2393 ohci_dump_tds(sc, p); 2394 } 2395 #endif 2396 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2397 hit = 0; 2398 for (; p->xfer == xfer; p = n) { 2399 hit |= headp == p->physaddr; 2400 n = p->nexttd; 2401 ohci_free_std(sc, p); 2402 } 2403 /* Zap headp register if hardware pointed inside the xfer. */ 2404 if (hit) { 2405 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2406 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2407 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2408 usb_syncmem(&sed->dma, 2409 sed->offs + offsetof(ohci_ed_t, ed_headp), 2410 sizeof(sed->ed.ed_headp), 2411 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2412 } else { 2413 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2414 } 2415 2416 /* 2417 * Step 4: Turn on hardware again. 2418 */ 2419 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2420 sizeof(sed->ed.ed_flags), 2421 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2422 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2423 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2424 sizeof(sed->ed.ed_flags), 2425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2426 2427 /* 2428 * Step 5: Execute callback. 2429 */ 2430 wake = xfer->hcflags & UXFER_ABORTWAIT; 2431 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2432 usb_transfer_complete(xfer); 2433 if (wake) 2434 cv_broadcast(&xfer->hccv); 2435 2436 done: 2437 KASSERT(mutex_owned(&sc->sc_lock)); 2438 } 2439 2440 /* 2441 * Data structures and routines to emulate the root hub. 2442 */ 2443 Static usb_device_descriptor_t ohci_devd = { 2444 USB_DEVICE_DESCRIPTOR_SIZE, 2445 UDESC_DEVICE, /* type */ 2446 {0x00, 0x01}, /* USB version */ 2447 UDCLASS_HUB, /* class */ 2448 UDSUBCLASS_HUB, /* subclass */ 2449 UDPROTO_FSHUB, /* protocol */ 2450 64, /* max packet */ 2451 {0},{0},{0x00,0x01}, /* device id */ 2452 1,2,0, /* string indicies */ 2453 1 /* # of configurations */ 2454 }; 2455 2456 Static const usb_config_descriptor_t ohci_confd = { 2457 USB_CONFIG_DESCRIPTOR_SIZE, 2458 UDESC_CONFIG, 2459 {USB_CONFIG_DESCRIPTOR_SIZE + 2460 USB_INTERFACE_DESCRIPTOR_SIZE + 2461 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2462 1, 2463 1, 2464 0, 2465 UC_ATTR_MBO | UC_SELF_POWERED, 2466 0 /* max power */ 2467 }; 2468 2469 Static const usb_interface_descriptor_t ohci_ifcd = { 2470 USB_INTERFACE_DESCRIPTOR_SIZE, 2471 UDESC_INTERFACE, 2472 0, 2473 0, 2474 1, 2475 UICLASS_HUB, 2476 UISUBCLASS_HUB, 2477 UIPROTO_FSHUB, 2478 0 2479 }; 2480 2481 Static const usb_endpoint_descriptor_t ohci_endpd = { 2482 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2483 .bDescriptorType = UDESC_ENDPOINT, 2484 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2485 .bmAttributes = UE_INTERRUPT, 2486 .wMaxPacketSize = {8, 0}, /* max packet */ 2487 .bInterval = 255, 2488 }; 2489 2490 Static const usb_hub_descriptor_t ohci_hubd = { 2491 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2492 .bDescriptorType = UDESC_HUB, 2493 }; 2494 2495 /* 2496 * Simulate a hardware hub by handling all the necessary requests. 2497 */ 2498 Static usbd_status 2499 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2500 { 2501 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2502 usbd_status err; 2503 2504 /* Insert last in queue. */ 2505 mutex_enter(&sc->sc_lock); 2506 err = usb_insert_transfer(xfer); 2507 mutex_exit(&sc->sc_lock); 2508 if (err) 2509 return (err); 2510 2511 /* Pipe isn't running, start first */ 2512 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2513 } 2514 2515 Static usbd_status 2516 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2517 { 2518 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2519 usb_device_request_t *req; 2520 void *buf = NULL; 2521 int port, i; 2522 int len, value, index, l, totlen = 0; 2523 usb_port_status_t ps; 2524 usb_hub_descriptor_t hubd; 2525 usbd_status err; 2526 u_int32_t v; 2527 2528 if (sc->sc_dying) 2529 return (USBD_IOERROR); 2530 2531 #ifdef DIAGNOSTIC 2532 if (!(xfer->rqflags & URQ_REQUEST)) 2533 /* XXX panic */ 2534 return (USBD_INVAL); 2535 #endif 2536 req = &xfer->request; 2537 2538 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2539 req->bmRequestType, req->bRequest)); 2540 2541 len = UGETW(req->wLength); 2542 value = UGETW(req->wValue); 2543 index = UGETW(req->wIndex); 2544 2545 if (len != 0) 2546 buf = KERNADDR(&xfer->dmabuf, 0); 2547 2548 #define C(x,y) ((x) | ((y) << 8)) 2549 switch(C(req->bRequest, req->bmRequestType)) { 2550 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2551 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2552 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2553 /* 2554 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2555 * for the integrated root hub. 2556 */ 2557 break; 2558 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2559 if (len > 0) { 2560 *(u_int8_t *)buf = sc->sc_conf; 2561 totlen = 1; 2562 } 2563 break; 2564 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2565 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2566 if (len == 0) 2567 break; 2568 switch(value >> 8) { 2569 case UDESC_DEVICE: 2570 if ((value & 0xff) != 0) { 2571 err = USBD_IOERROR; 2572 goto ret; 2573 } 2574 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2575 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2576 memcpy(buf, &ohci_devd, l); 2577 break; 2578 case UDESC_CONFIG: 2579 if ((value & 0xff) != 0) { 2580 err = USBD_IOERROR; 2581 goto ret; 2582 } 2583 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2584 memcpy(buf, &ohci_confd, l); 2585 buf = (char *)buf + l; 2586 len -= l; 2587 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2588 totlen += l; 2589 memcpy(buf, &ohci_ifcd, l); 2590 buf = (char *)buf + l; 2591 len -= l; 2592 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2593 totlen += l; 2594 memcpy(buf, &ohci_endpd, l); 2595 break; 2596 case UDESC_STRING: 2597 #define sd ((usb_string_descriptor_t *)buf) 2598 switch (value & 0xff) { 2599 case 0: /* Language table */ 2600 totlen = usb_makelangtbl(sd, len); 2601 break; 2602 case 1: /* Vendor */ 2603 totlen = usb_makestrdesc(sd, len, 2604 sc->sc_vendor); 2605 break; 2606 case 2: /* Product */ 2607 totlen = usb_makestrdesc(sd, len, 2608 "OHCI root hub"); 2609 break; 2610 } 2611 #undef sd 2612 break; 2613 default: 2614 err = USBD_IOERROR; 2615 goto ret; 2616 } 2617 break; 2618 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2619 if (len > 0) { 2620 *(u_int8_t *)buf = 0; 2621 totlen = 1; 2622 } 2623 break; 2624 case C(UR_GET_STATUS, UT_READ_DEVICE): 2625 if (len > 1) { 2626 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2627 totlen = 2; 2628 } 2629 break; 2630 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2631 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2632 if (len > 1) { 2633 USETW(((usb_status_t *)buf)->wStatus, 0); 2634 totlen = 2; 2635 } 2636 break; 2637 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2638 if (value >= USB_MAX_DEVICES) { 2639 err = USBD_IOERROR; 2640 goto ret; 2641 } 2642 sc->sc_addr = value; 2643 break; 2644 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2645 if (value != 0 && value != 1) { 2646 err = USBD_IOERROR; 2647 goto ret; 2648 } 2649 sc->sc_conf = value; 2650 break; 2651 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2652 break; 2653 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2654 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2655 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2656 err = USBD_IOERROR; 2657 goto ret; 2658 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2659 break; 2660 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2661 break; 2662 /* Hub requests */ 2663 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2664 break; 2665 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2666 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2667 "port=%d feature=%d\n", 2668 index, value)); 2669 if (index < 1 || index > sc->sc_noport) { 2670 err = USBD_IOERROR; 2671 goto ret; 2672 } 2673 port = OHCI_RH_PORT_STATUS(index); 2674 switch(value) { 2675 case UHF_PORT_ENABLE: 2676 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2677 break; 2678 case UHF_PORT_SUSPEND: 2679 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2680 break; 2681 case UHF_PORT_POWER: 2682 /* Yes, writing to the LOW_SPEED bit clears power. */ 2683 OWRITE4(sc, port, UPS_LOW_SPEED); 2684 break; 2685 case UHF_C_PORT_CONNECTION: 2686 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2687 break; 2688 case UHF_C_PORT_ENABLE: 2689 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2690 break; 2691 case UHF_C_PORT_SUSPEND: 2692 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2693 break; 2694 case UHF_C_PORT_OVER_CURRENT: 2695 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2696 break; 2697 case UHF_C_PORT_RESET: 2698 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2699 break; 2700 default: 2701 err = USBD_IOERROR; 2702 goto ret; 2703 } 2704 switch(value) { 2705 case UHF_C_PORT_CONNECTION: 2706 case UHF_C_PORT_ENABLE: 2707 case UHF_C_PORT_SUSPEND: 2708 case UHF_C_PORT_OVER_CURRENT: 2709 case UHF_C_PORT_RESET: 2710 /* Enable RHSC interrupt if condition is cleared. */ 2711 if ((OREAD4(sc, port) >> 16) == 0) 2712 ohci_rhsc_enable(sc); 2713 break; 2714 default: 2715 break; 2716 } 2717 break; 2718 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2719 if (len == 0) 2720 break; 2721 if ((value & 0xff) != 0) { 2722 err = USBD_IOERROR; 2723 goto ret; 2724 } 2725 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2726 hubd = ohci_hubd; 2727 hubd.bNbrPorts = sc->sc_noport; 2728 USETW(hubd.wHubCharacteristics, 2729 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2730 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2731 /* XXX overcurrent */ 2732 ); 2733 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2734 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2735 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2736 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2737 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2738 l = min(len, hubd.bDescLength); 2739 totlen = l; 2740 memcpy(buf, &hubd, l); 2741 break; 2742 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2743 if (len != 4) { 2744 err = USBD_IOERROR; 2745 goto ret; 2746 } 2747 memset(buf, 0, len); /* ? XXX */ 2748 totlen = len; 2749 break; 2750 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2751 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2752 index)); 2753 if (index < 1 || index > sc->sc_noport) { 2754 err = USBD_IOERROR; 2755 goto ret; 2756 } 2757 if (len != 4) { 2758 err = USBD_IOERROR; 2759 goto ret; 2760 } 2761 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2762 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2763 v)); 2764 USETW(ps.wPortStatus, v); 2765 USETW(ps.wPortChange, v >> 16); 2766 l = min(len, sizeof ps); 2767 memcpy(buf, &ps, l); 2768 totlen = l; 2769 break; 2770 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2771 err = USBD_IOERROR; 2772 goto ret; 2773 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2774 break; 2775 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2776 if (index < 1 || index > sc->sc_noport) { 2777 err = USBD_IOERROR; 2778 goto ret; 2779 } 2780 port = OHCI_RH_PORT_STATUS(index); 2781 switch(value) { 2782 case UHF_PORT_ENABLE: 2783 OWRITE4(sc, port, UPS_PORT_ENABLED); 2784 break; 2785 case UHF_PORT_SUSPEND: 2786 OWRITE4(sc, port, UPS_SUSPEND); 2787 break; 2788 case UHF_PORT_RESET: 2789 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2790 index)); 2791 OWRITE4(sc, port, UPS_RESET); 2792 for (i = 0; i < 5; i++) { 2793 usb_delay_ms(&sc->sc_bus, 2794 USB_PORT_ROOT_RESET_DELAY); 2795 if (sc->sc_dying) { 2796 err = USBD_IOERROR; 2797 goto ret; 2798 } 2799 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2800 break; 2801 } 2802 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2803 index, OREAD4(sc, port))); 2804 break; 2805 case UHF_PORT_POWER: 2806 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2807 "%d\n", index)); 2808 OWRITE4(sc, port, UPS_PORT_POWER); 2809 break; 2810 default: 2811 err = USBD_IOERROR; 2812 goto ret; 2813 } 2814 break; 2815 default: 2816 err = USBD_IOERROR; 2817 goto ret; 2818 } 2819 xfer->actlen = totlen; 2820 err = USBD_NORMAL_COMPLETION; 2821 ret: 2822 xfer->status = err; 2823 mutex_enter(&sc->sc_lock); 2824 usb_transfer_complete(xfer); 2825 mutex_exit(&sc->sc_lock); 2826 return (USBD_IN_PROGRESS); 2827 } 2828 2829 /* Abort a root control request. */ 2830 Static void 2831 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2832 { 2833 /* Nothing to do, all transfers are synchronous. */ 2834 } 2835 2836 /* Close the root pipe. */ 2837 Static void 2838 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2839 { 2840 DPRINTF(("ohci_root_ctrl_close\n")); 2841 /* Nothing to do. */ 2842 } 2843 2844 Static usbd_status 2845 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2846 { 2847 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2848 usbd_status err; 2849 2850 /* Insert last in queue. */ 2851 mutex_enter(&sc->sc_lock); 2852 err = usb_insert_transfer(xfer); 2853 mutex_exit(&sc->sc_lock); 2854 if (err) 2855 return (err); 2856 2857 /* Pipe isn't running, start first */ 2858 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2859 } 2860 2861 Static usbd_status 2862 ohci_root_intr_start(usbd_xfer_handle xfer) 2863 { 2864 usbd_pipe_handle pipe = xfer->pipe; 2865 ohci_softc_t *sc = pipe->device->bus->hci_private; 2866 2867 if (sc->sc_dying) 2868 return (USBD_IOERROR); 2869 2870 mutex_enter(&sc->sc_lock); 2871 KASSERT(sc->sc_intrxfer == NULL); 2872 sc->sc_intrxfer = xfer; 2873 mutex_exit(&sc->sc_lock); 2874 2875 return (USBD_IN_PROGRESS); 2876 } 2877 2878 /* Abort a root interrupt request. */ 2879 Static void 2880 ohci_root_intr_abort(usbd_xfer_handle xfer) 2881 { 2882 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2883 2884 KASSERT(mutex_owned(&sc->sc_lock)); 2885 2886 if (xfer->pipe->intrxfer == xfer) { 2887 DPRINTF(("ohci_root_intr_abort: remove\n")); 2888 xfer->pipe->intrxfer = NULL; 2889 } 2890 xfer->status = USBD_CANCELLED; 2891 usb_transfer_complete(xfer); 2892 } 2893 2894 /* Close the root pipe. */ 2895 Static void 2896 ohci_root_intr_close(usbd_pipe_handle pipe) 2897 { 2898 ohci_softc_t *sc = pipe->device->bus->hci_private; 2899 2900 KASSERT(mutex_owned(&sc->sc_lock)); 2901 2902 DPRINTF(("ohci_root_intr_close\n")); 2903 2904 sc->sc_intrxfer = NULL; 2905 } 2906 2907 /************************/ 2908 2909 Static usbd_status 2910 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2911 { 2912 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2913 usbd_status err; 2914 2915 /* Insert last in queue. */ 2916 mutex_enter(&sc->sc_lock); 2917 err = usb_insert_transfer(xfer); 2918 mutex_exit(&sc->sc_lock); 2919 if (err) 2920 return (err); 2921 2922 /* Pipe isn't running, start first */ 2923 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2924 } 2925 2926 Static usbd_status 2927 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2928 { 2929 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2930 usbd_status err; 2931 2932 if (sc->sc_dying) 2933 return (USBD_IOERROR); 2934 2935 #ifdef DIAGNOSTIC 2936 if (!(xfer->rqflags & URQ_REQUEST)) { 2937 /* XXX panic */ 2938 printf("ohci_device_ctrl_transfer: not a request\n"); 2939 return (USBD_INVAL); 2940 } 2941 #endif 2942 2943 mutex_enter(&sc->sc_lock); 2944 err = ohci_device_request(xfer); 2945 mutex_exit(&sc->sc_lock); 2946 if (err) 2947 return (err); 2948 2949 if (sc->sc_bus.use_polling) 2950 ohci_waitintr(sc, xfer); 2951 return (USBD_IN_PROGRESS); 2952 } 2953 2954 /* Abort a device control request. */ 2955 Static void 2956 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2957 { 2958 #ifdef DIAGNOSTIC 2959 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2960 #endif 2961 2962 KASSERT(mutex_owned(&sc->sc_lock)); 2963 2964 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2965 ohci_abort_xfer(xfer, USBD_CANCELLED); 2966 } 2967 2968 /* Close a device control pipe. */ 2969 Static void 2970 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2971 { 2972 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2973 ohci_softc_t *sc = pipe->device->bus->hci_private; 2974 2975 KASSERT(mutex_owned(&sc->sc_lock)); 2976 2977 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2978 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2979 ohci_free_std(sc, opipe->tail.td); 2980 } 2981 2982 /************************/ 2983 2984 Static void 2985 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2986 { 2987 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2988 ohci_softc_t *sc = pipe->device->bus->hci_private; 2989 2990 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2991 } 2992 2993 Static void 2994 ohci_noop(usbd_pipe_handle pipe) 2995 { 2996 } 2997 2998 Static usbd_status 2999 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 3000 { 3001 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3002 usbd_status err; 3003 3004 /* Insert last in queue. */ 3005 mutex_enter(&sc->sc_lock); 3006 err = usb_insert_transfer(xfer); 3007 mutex_exit(&sc->sc_lock); 3008 if (err) 3009 return (err); 3010 3011 /* Pipe isn't running, start first */ 3012 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3013 } 3014 3015 Static usbd_status 3016 ohci_device_bulk_start(usbd_xfer_handle xfer) 3017 { 3018 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3019 usbd_device_handle dev = opipe->pipe.device; 3020 ohci_softc_t *sc = dev->bus->hci_private; 3021 int addr = dev->address; 3022 ohci_soft_td_t *data, *tail, *tdp; 3023 ohci_soft_ed_t *sed; 3024 int len, isread, endpt; 3025 usbd_status err; 3026 3027 if (sc->sc_dying) 3028 return (USBD_IOERROR); 3029 3030 #ifdef DIAGNOSTIC 3031 if (xfer->rqflags & URQ_REQUEST) { 3032 /* XXX panic */ 3033 printf("ohci_device_bulk_start: a request\n"); 3034 return (USBD_INVAL); 3035 } 3036 #endif 3037 3038 mutex_enter(&sc->sc_lock); 3039 3040 len = xfer->length; 3041 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3042 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3043 sed = opipe->sed; 3044 3045 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3046 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3047 endpt)); 3048 3049 opipe->u.bulk.isread = isread; 3050 opipe->u.bulk.length = len; 3051 3052 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3053 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3054 /* Update device address */ 3055 sed->ed.ed_flags = HTOO32( 3056 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3057 OHCI_ED_SET_FA(addr)); 3058 3059 /* Allocate a chain of new TDs (including a new tail). */ 3060 data = opipe->tail.td; 3061 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3062 data, &tail); 3063 /* We want interrupt at the end of the transfer. */ 3064 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3065 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3066 tail->flags |= OHCI_CALL_DONE; 3067 tail = tail->nexttd; /* point at sentinel */ 3068 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3069 sizeof(tail->td.td_flags), 3070 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3071 if (err) { 3072 mutex_exit(&sc->sc_lock); 3073 return (err); 3074 } 3075 3076 tail->xfer = NULL; 3077 xfer->hcpriv = data; 3078 3079 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3080 "td_cbp=0x%08x td_be=0x%08x\n", 3081 (int)O32TOH(sed->ed.ed_flags), 3082 (int)O32TOH(data->td.td_flags), 3083 (int)O32TOH(data->td.td_cbp), 3084 (int)O32TOH(data->td.td_be))); 3085 3086 #ifdef OHCI_DEBUG 3087 if (ohcidebug > 5) { 3088 ohci_dump_ed(sc, sed); 3089 ohci_dump_tds(sc, data); 3090 } 3091 #endif 3092 3093 /* Insert ED in schedule */ 3094 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3095 tdp->xfer = xfer; 3096 } 3097 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3098 opipe->tail.td = tail; 3099 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3100 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3102 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3103 if (xfer->timeout && !sc->sc_bus.use_polling) { 3104 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3105 ohci_timeout, xfer); 3106 } 3107 mutex_exit(&sc->sc_lock); 3108 3109 #if 0 3110 /* This goes wrong if we are too slow. */ 3111 if (ohcidebug > 10) { 3112 delay(10000); 3113 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3114 OREAD4(sc, OHCI_COMMAND_STATUS))); 3115 ohci_dump_ed(sc, sed); 3116 ohci_dump_tds(sc, data); 3117 } 3118 #endif 3119 3120 return (USBD_IN_PROGRESS); 3121 } 3122 3123 Static void 3124 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3125 { 3126 #ifdef DIAGNOSTIC 3127 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3128 #endif 3129 3130 KASSERT(mutex_owned(&sc->sc_lock)); 3131 3132 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3133 ohci_abort_xfer(xfer, USBD_CANCELLED); 3134 } 3135 3136 /* 3137 * Close a device bulk pipe. 3138 */ 3139 Static void 3140 ohci_device_bulk_close(usbd_pipe_handle pipe) 3141 { 3142 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3143 ohci_softc_t *sc = pipe->device->bus->hci_private; 3144 3145 KASSERT(mutex_owned(&sc->sc_lock)); 3146 3147 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3148 ohci_close_pipe(pipe, sc->sc_bulk_head); 3149 ohci_free_std(sc, opipe->tail.td); 3150 } 3151 3152 /************************/ 3153 3154 Static usbd_status 3155 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3156 { 3157 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3158 usbd_status err; 3159 3160 /* Insert last in queue. */ 3161 mutex_enter(&sc->sc_lock); 3162 err = usb_insert_transfer(xfer); 3163 mutex_exit(&sc->sc_lock); 3164 if (err) 3165 return (err); 3166 3167 /* Pipe isn't running, start first */ 3168 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3169 } 3170 3171 Static usbd_status 3172 ohci_device_intr_start(usbd_xfer_handle xfer) 3173 { 3174 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3175 usbd_device_handle dev = opipe->pipe.device; 3176 ohci_softc_t *sc = dev->bus->hci_private; 3177 ohci_soft_ed_t *sed = opipe->sed; 3178 ohci_soft_td_t *data, *tail; 3179 int len, isread, endpt; 3180 3181 if (sc->sc_dying) 3182 return (USBD_IOERROR); 3183 3184 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3185 "flags=%d priv=%p\n", 3186 xfer, xfer->length, xfer->flags, xfer->priv)); 3187 3188 #ifdef DIAGNOSTIC 3189 if (xfer->rqflags & URQ_REQUEST) 3190 panic("ohci_device_intr_transfer: a request"); 3191 #endif 3192 3193 len = xfer->length; 3194 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3195 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3196 3197 data = opipe->tail.td; 3198 mutex_enter(&sc->sc_lock); 3199 tail = ohci_alloc_std(sc); 3200 mutex_exit(&sc->sc_lock); 3201 if (tail == NULL) 3202 return (USBD_NOMEM); 3203 tail->xfer = NULL; 3204 3205 data->td.td_flags = HTOO32( 3206 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3207 OHCI_TD_NOCC | 3208 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3209 if (xfer->flags & USBD_SHORT_XFER_OK) 3210 data->td.td_flags |= HTOO32(OHCI_TD_R); 3211 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3212 data->nexttd = tail; 3213 data->td.td_nexttd = HTOO32(tail->physaddr); 3214 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3215 data->len = len; 3216 data->xfer = xfer; 3217 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3218 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3220 xfer->hcpriv = data; 3221 3222 #ifdef OHCI_DEBUG 3223 if (ohcidebug > 5) { 3224 DPRINTF(("ohci_device_intr_transfer:\n")); 3225 ohci_dump_ed(sc, sed); 3226 ohci_dump_tds(sc, data); 3227 } 3228 #endif 3229 3230 /* Insert ED in schedule */ 3231 mutex_enter(&sc->sc_lock); 3232 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3233 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3234 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3235 opipe->tail.td = tail; 3236 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3237 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3238 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3239 3240 #if 0 3241 /* 3242 * This goes horribly wrong, printing thousands of descriptors, 3243 * because false references are followed due to the fact that the 3244 * TD is gone. 3245 */ 3246 if (ohcidebug > 5) { 3247 usb_delay_ms(&sc->sc_bus, 5); 3248 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3249 OREAD4(sc, OHCI_COMMAND_STATUS))); 3250 ohci_dump_ed(sc, sed); 3251 ohci_dump_tds(sc, data); 3252 } 3253 #endif 3254 mutex_exit(&sc->sc_lock); 3255 3256 return (USBD_IN_PROGRESS); 3257 } 3258 3259 /* Abort a device control request. */ 3260 Static void 3261 ohci_device_intr_abort(usbd_xfer_handle xfer) 3262 { 3263 #ifdef DIAGNOSTIC 3264 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3265 #endif 3266 3267 KASSERT(mutex_owned(&sc->sc_lock)); 3268 3269 if (xfer->pipe->intrxfer == xfer) { 3270 DPRINTF(("ohci_device_intr_abort: remove\n")); 3271 xfer->pipe->intrxfer = NULL; 3272 } 3273 ohci_abort_xfer(xfer, USBD_CANCELLED); 3274 } 3275 3276 /* Close a device interrupt pipe. */ 3277 Static void 3278 ohci_device_intr_close(usbd_pipe_handle pipe) 3279 { 3280 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3281 ohci_softc_t *sc = pipe->device->bus->hci_private; 3282 int nslots = opipe->u.intr.nslots; 3283 int pos = opipe->u.intr.pos; 3284 int j; 3285 ohci_soft_ed_t *p, *sed = opipe->sed; 3286 3287 KASSERT(mutex_owned(&sc->sc_lock)); 3288 3289 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3290 pipe, nslots, pos)); 3291 usb_syncmem(&sed->dma, sed->offs, 3292 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3293 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3294 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3295 sizeof(sed->ed.ed_flags), 3296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3297 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3298 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3299 usb_delay_ms(&sc->sc_bus, 2); 3300 3301 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3302 continue; 3303 #ifdef DIAGNOSTIC 3304 if (p == NULL) 3305 panic("ohci_device_intr_close: ED not found"); 3306 #endif 3307 p->next = sed->next; 3308 p->ed.ed_nexted = sed->ed.ed_nexted; 3309 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3310 sizeof(p->ed.ed_nexted), 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 3313 for (j = 0; j < nslots; j++) 3314 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3315 3316 ohci_free_std(sc, opipe->tail.td); 3317 ohci_free_sed(sc, opipe->sed); 3318 } 3319 3320 Static usbd_status 3321 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3322 { 3323 int i, j, best; 3324 u_int npoll, slow, shigh, nslots; 3325 u_int bestbw, bw; 3326 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3327 3328 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3329 if (ival == 0) { 3330 printf("ohci_setintr: 0 interval\n"); 3331 return (USBD_INVAL); 3332 } 3333 3334 npoll = OHCI_NO_INTRS; 3335 while (npoll > ival) 3336 npoll /= 2; 3337 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3338 3339 /* 3340 * We now know which level in the tree the ED must go into. 3341 * Figure out which slot has most bandwidth left over. 3342 * Slots to examine: 3343 * npoll 3344 * 1 0 3345 * 2 1 2 3346 * 4 3 4 5 6 3347 * 8 7 8 9 10 11 12 13 14 3348 * N (N-1) .. (N-1+N-1) 3349 */ 3350 slow = npoll-1; 3351 shigh = slow + npoll; 3352 nslots = OHCI_NO_INTRS / npoll; 3353 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3354 bw = 0; 3355 for (j = 0; j < nslots; j++) 3356 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3357 if (bw < bestbw) { 3358 best = i; 3359 bestbw = bw; 3360 } 3361 } 3362 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3363 best, slow, shigh, bestbw)); 3364 3365 mutex_enter(&sc->sc_lock); 3366 hsed = sc->sc_eds[best]; 3367 sed->next = hsed->next; 3368 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3369 sizeof(hsed->ed.ed_flags), 3370 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3371 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3372 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3373 sizeof(sed->ed.ed_flags), 3374 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3375 hsed->next = sed; 3376 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3377 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3378 sizeof(hsed->ed.ed_flags), 3379 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3380 mutex_exit(&sc->sc_lock); 3381 3382 for (j = 0; j < nslots; j++) 3383 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3384 opipe->u.intr.nslots = nslots; 3385 opipe->u.intr.pos = best; 3386 3387 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3388 return (USBD_NORMAL_COMPLETION); 3389 } 3390 3391 /***********************/ 3392 3393 usbd_status 3394 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3395 { 3396 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3397 usbd_status err; 3398 3399 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3400 3401 /* Put it on our queue, */ 3402 mutex_enter(&sc->sc_lock); 3403 err = usb_insert_transfer(xfer); 3404 mutex_exit(&sc->sc_lock); 3405 3406 /* bail out on error, */ 3407 if (err && err != USBD_IN_PROGRESS) 3408 return (err); 3409 3410 /* XXX should check inuse here */ 3411 3412 /* insert into schedule, */ 3413 ohci_device_isoc_enter(xfer); 3414 3415 /* and start if the pipe wasn't running */ 3416 if (!err) 3417 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3418 3419 return (err); 3420 } 3421 3422 void 3423 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3424 { 3425 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3426 usbd_device_handle dev = opipe->pipe.device; 3427 ohci_softc_t *sc = dev->bus->hci_private; 3428 ohci_soft_ed_t *sed = opipe->sed; 3429 struct iso *iso = &opipe->u.iso; 3430 ohci_soft_itd_t *sitd, *nsitd; 3431 ohci_physaddr_t buf, offs, noffs, bp0; 3432 int i, ncur, nframes; 3433 3434 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3435 "nframes=%d\n", 3436 iso->inuse, iso->next, xfer, xfer->nframes)); 3437 3438 if (sc->sc_dying) 3439 return; 3440 3441 if (iso->next == -1) { 3442 /* Not in use yet, schedule it a few frames ahead. */ 3443 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3444 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3445 iso->next)); 3446 } 3447 3448 sitd = opipe->tail.itd; 3449 buf = DMAADDR(&xfer->dmabuf, 0); 3450 bp0 = OHCI_PAGE(buf); 3451 offs = OHCI_PAGE_OFFSET(buf); 3452 nframes = xfer->nframes; 3453 xfer->hcpriv = sitd; 3454 for (i = ncur = 0; i < nframes; i++, ncur++) { 3455 noffs = offs + xfer->frlengths[i]; 3456 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3457 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3458 3459 /* Allocate next ITD */ 3460 mutex_enter(&sc->sc_lock); 3461 nsitd = ohci_alloc_sitd(sc); 3462 mutex_exit(&sc->sc_lock); 3463 if (nsitd == NULL) { 3464 /* XXX what now? */ 3465 printf("%s: isoc TD alloc failed\n", 3466 device_xname(sc->sc_dev)); 3467 return; 3468 } 3469 3470 /* Fill current ITD */ 3471 sitd->itd.itd_flags = HTOO32( 3472 OHCI_ITD_NOCC | 3473 OHCI_ITD_SET_SF(iso->next) | 3474 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3475 OHCI_ITD_SET_FC(ncur)); 3476 sitd->itd.itd_bp0 = HTOO32(bp0); 3477 sitd->nextitd = nsitd; 3478 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3479 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3480 sitd->xfer = xfer; 3481 sitd->flags = 0; 3482 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3483 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3484 3485 sitd = nsitd; 3486 iso->next = iso->next + ncur; 3487 bp0 = OHCI_PAGE(buf + offs); 3488 ncur = 0; 3489 } 3490 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3491 offs = noffs; 3492 } 3493 mutex_enter(&sc->sc_lock); 3494 nsitd = ohci_alloc_sitd(sc); 3495 mutex_exit(&sc->sc_lock); 3496 if (nsitd == NULL) { 3497 /* XXX what now? */ 3498 printf("%s: isoc TD alloc failed\n", 3499 device_xname(sc->sc_dev)); 3500 return; 3501 } 3502 /* Fixup last used ITD */ 3503 sitd->itd.itd_flags = HTOO32( 3504 OHCI_ITD_NOCC | 3505 OHCI_ITD_SET_SF(iso->next) | 3506 OHCI_ITD_SET_DI(0) | 3507 OHCI_ITD_SET_FC(ncur)); 3508 sitd->itd.itd_bp0 = HTOO32(bp0); 3509 sitd->nextitd = nsitd; 3510 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3511 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3512 sitd->xfer = xfer; 3513 sitd->flags = OHCI_CALL_DONE; 3514 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3515 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3516 3517 iso->next = iso->next + ncur; 3518 iso->inuse += nframes; 3519 3520 xfer->actlen = offs; /* XXX pretend we did it all */ 3521 3522 xfer->status = USBD_IN_PROGRESS; 3523 3524 #ifdef OHCI_DEBUG 3525 if (ohcidebug > 5) { 3526 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3527 O32TOH(sc->sc_hcca->hcca_frame_number))); 3528 ohci_dump_itds(sc, xfer->hcpriv); 3529 ohci_dump_ed(sc, sed); 3530 } 3531 #endif 3532 3533 mutex_enter(&sc->sc_lock); 3534 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3535 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3536 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3537 opipe->tail.itd = nsitd; 3538 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3539 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3540 sizeof(sed->ed.ed_flags), 3541 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3542 mutex_exit(&sc->sc_lock); 3543 3544 #ifdef OHCI_DEBUG 3545 if (ohcidebug > 5) { 3546 delay(150000); 3547 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3548 O32TOH(sc->sc_hcca->hcca_frame_number))); 3549 ohci_dump_itds(sc, xfer->hcpriv); 3550 ohci_dump_ed(sc, sed); 3551 } 3552 #endif 3553 } 3554 3555 usbd_status 3556 ohci_device_isoc_start(usbd_xfer_handle xfer) 3557 { 3558 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3559 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3560 3561 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3562 3563 mutex_enter(&sc->sc_lock); 3564 3565 if (sc->sc_dying) { 3566 mutex_exit(&sc->sc_lock); 3567 return (USBD_IOERROR); 3568 } 3569 3570 #ifdef DIAGNOSTIC 3571 if (xfer->status != USBD_IN_PROGRESS) 3572 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3573 #endif 3574 3575 /* XXX anything to do? */ 3576 3577 mutex_exit(&sc->sc_lock); 3578 3579 return (USBD_IN_PROGRESS); 3580 } 3581 3582 void 3583 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3584 { 3585 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3586 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3587 ohci_soft_ed_t *sed; 3588 ohci_soft_itd_t *sitd; 3589 3590 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3591 3592 KASSERT(mutex_owned(&sc->sc_lock)); 3593 3594 /* Transfer is already done. */ 3595 if (xfer->status != USBD_NOT_STARTED && 3596 xfer->status != USBD_IN_PROGRESS) { 3597 printf("ohci_device_isoc_abort: early return\n"); 3598 goto done; 3599 } 3600 3601 /* Give xfer the requested abort code. */ 3602 xfer->status = USBD_CANCELLED; 3603 3604 sed = opipe->sed; 3605 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3606 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3607 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3608 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3609 sizeof(sed->ed.ed_flags), 3610 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3611 3612 sitd = xfer->hcpriv; 3613 #ifdef DIAGNOSTIC 3614 if (sitd == NULL) { 3615 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3616 goto done; 3617 } 3618 #endif 3619 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3620 #ifdef DIAGNOSTIC 3621 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3622 sitd->isdone = 1; 3623 #endif 3624 } 3625 3626 /* XXXMRG is this ok? */ 3627 mutex_exit(&sc->sc_lock); 3628 3629 usb_delay_ms(&sc->sc_bus, OHCI_ITD_NOFFSET); 3630 3631 mutex_enter(&sc->sc_lock); 3632 3633 /* Run callback. */ 3634 usb_transfer_complete(xfer); 3635 3636 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3637 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3638 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3639 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3640 3641 done: 3642 KASSERT(mutex_owned(&sc->sc_lock)); 3643 } 3644 3645 void 3646 ohci_device_isoc_done(usbd_xfer_handle xfer) 3647 { 3648 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3649 } 3650 3651 usbd_status 3652 ohci_setup_isoc(usbd_pipe_handle pipe) 3653 { 3654 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3655 ohci_softc_t *sc = pipe->device->bus->hci_private; 3656 struct iso *iso = &opipe->u.iso; 3657 3658 iso->next = -1; 3659 iso->inuse = 0; 3660 3661 mutex_enter(&sc->sc_lock); 3662 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3663 mutex_exit(&sc->sc_lock); 3664 3665 return (USBD_NORMAL_COMPLETION); 3666 } 3667 3668 void 3669 ohci_device_isoc_close(usbd_pipe_handle pipe) 3670 { 3671 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3672 ohci_softc_t *sc = pipe->device->bus->hci_private; 3673 3674 KASSERT(mutex_owned(&sc->sc_lock)); 3675 3676 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3677 ohci_close_pipe(pipe, sc->sc_isoc_head); 3678 #ifdef DIAGNOSTIC 3679 opipe->tail.itd->isdone = 1; 3680 #endif 3681 ohci_free_sitd(sc, opipe->tail.itd); 3682 } 3683
Indexes created Fri Oct 03 02:09:57 GMT 2025