ohci.c revision 1.224.2.1
1 /* $NetBSD: ohci.c,v 1.224.2.1 2013/02/25 00:29:37 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.224.2.1 2013/02/25 00:29:37 tls Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 #if 0 102 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 103 ohci_soft_td_t *); 104 #endif 105 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 106 ohci_softc_t *, int, int, usbd_xfer_handle, 107 ohci_soft_td_t *, ohci_soft_td_t **); 108 109 Static usbd_status ohci_open(usbd_pipe_handle); 110 Static void ohci_poll(struct usbd_bus *); 111 Static void ohci_softintr(void *); 112 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 113 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 114 Static void ohci_rhsc_softint(void *arg); 115 116 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 117 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 118 ohci_soft_ed_t *); 119 120 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 121 ohci_soft_ed_t *); 122 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 123 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 124 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 125 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 126 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 127 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 128 129 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 130 Static void ohci_device_isoc_enter(usbd_xfer_handle); 131 132 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 133 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 134 135 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 136 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 137 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 138 139 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 140 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 141 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 142 Static void ohci_root_ctrl_close(usbd_pipe_handle); 143 Static void ohci_root_ctrl_done(usbd_xfer_handle); 144 145 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 146 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 147 Static void ohci_root_intr_abort(usbd_xfer_handle); 148 Static void ohci_root_intr_close(usbd_pipe_handle); 149 Static void ohci_root_intr_done(usbd_xfer_handle); 150 151 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 152 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 153 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 154 Static void ohci_device_ctrl_close(usbd_pipe_handle); 155 Static void ohci_device_ctrl_done(usbd_xfer_handle); 156 157 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 158 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 159 Static void ohci_device_bulk_abort(usbd_xfer_handle); 160 Static void ohci_device_bulk_close(usbd_pipe_handle); 161 Static void ohci_device_bulk_done(usbd_xfer_handle); 162 163 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 164 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 165 Static void ohci_device_intr_abort(usbd_xfer_handle); 166 Static void ohci_device_intr_close(usbd_pipe_handle); 167 Static void ohci_device_intr_done(usbd_xfer_handle); 168 169 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 170 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 171 Static void ohci_device_isoc_abort(usbd_xfer_handle); 172 Static void ohci_device_isoc_close(usbd_pipe_handle); 173 Static void ohci_device_isoc_done(usbd_xfer_handle); 174 175 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 176 struct ohci_pipe *pipe, int ival); 177 178 Static void ohci_timeout(void *); 179 Static void ohci_timeout_task(void *); 180 Static void ohci_rhsc_enable(void *); 181 182 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 183 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 184 185 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 186 Static void ohci_noop(usbd_pipe_handle pipe); 187 188 #ifdef OHCI_DEBUG 189 Static void ohci_dumpregs(ohci_softc_t *); 190 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 191 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 192 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 193 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 194 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 195 #endif 196 197 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 198 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 199 #define OWRITE1(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE2(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 #define OWRITE4(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 static __inline uint8_t 206 OREAD1(ohci_softc_t *sc, bus_size_t r) 207 { 208 209 OBARR(sc); 210 return bus_space_read_1(sc->iot, sc->ioh, r); 211 } 212 213 static __inline uint16_t 214 OREAD2(ohci_softc_t *sc, bus_size_t r) 215 { 216 217 OBARR(sc); 218 return bus_space_read_2(sc->iot, sc->ioh, r); 219 } 220 221 static __inline uint32_t 222 OREAD4(ohci_softc_t *sc, bus_size_t r) 223 { 224 225 OBARR(sc); 226 return bus_space_read_4(sc->iot, sc->ioh, r); 227 } 228 229 /* Reverse the bits in a value 0 .. 31 */ 230 Static u_int8_t revbits[OHCI_NO_INTRS] = 231 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 232 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 233 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 234 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 235 236 struct ohci_pipe { 237 struct usbd_pipe pipe; 238 ohci_soft_ed_t *sed; 239 union { 240 ohci_soft_td_t *td; 241 ohci_soft_itd_t *itd; 242 } tail; 243 /* Info needed for different pipe kinds. */ 244 union { 245 /* Control pipe */ 246 struct { 247 usb_dma_t reqdma; 248 u_int length; 249 ohci_soft_td_t *setup, *data, *stat; 250 } ctl; 251 /* Interrupt pipe */ 252 struct { 253 int nslots; 254 int pos; 255 } intr; 256 /* Bulk pipe */ 257 struct { 258 u_int length; 259 int isread; 260 } bulk; 261 /* Iso pipe */ 262 struct iso { 263 int next, inuse; 264 } iso; 265 } u; 266 }; 267 268 #define OHCI_INTR_ENDPT 1 269 270 Static const struct usbd_bus_methods ohci_bus_methods = { 271 .open_pipe = ohci_open, 272 .soft_intr = ohci_softintr, 273 .do_poll = ohci_poll, 274 .allocm = ohci_allocm, 275 .freem = ohci_freem, 276 .allocx = ohci_allocx, 277 .freex = ohci_freex, 278 .get_lock = ohci_get_lock, 279 }; 280 281 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 282 .transfer = ohci_root_ctrl_transfer, 283 .start = ohci_root_ctrl_start, 284 .abort = ohci_root_ctrl_abort, 285 .close = ohci_root_ctrl_close, 286 .cleartoggle = ohci_noop, 287 .done = ohci_root_ctrl_done, 288 }; 289 290 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 291 .transfer = ohci_root_intr_transfer, 292 .start = ohci_root_intr_start, 293 .abort = ohci_root_intr_abort, 294 .close = ohci_root_intr_close, 295 .cleartoggle = ohci_noop, 296 .done = ohci_root_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 300 .transfer = ohci_device_ctrl_transfer, 301 .start = ohci_device_ctrl_start, 302 .abort = ohci_device_ctrl_abort, 303 .close = ohci_device_ctrl_close, 304 .cleartoggle = ohci_noop, 305 .done = ohci_device_ctrl_done, 306 }; 307 308 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 309 .transfer = ohci_device_intr_transfer, 310 .start = ohci_device_intr_start, 311 .abort = ohci_device_intr_abort, 312 .close = ohci_device_intr_close, 313 .cleartoggle = ohci_device_clear_toggle, 314 .done = ohci_device_intr_done, 315 }; 316 317 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 318 .transfer = ohci_device_bulk_transfer, 319 .start = ohci_device_bulk_start, 320 .abort = ohci_device_bulk_abort, 321 .close = ohci_device_bulk_close, 322 .cleartoggle = ohci_device_clear_toggle, 323 .done = ohci_device_bulk_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 327 .transfer = ohci_device_isoc_transfer, 328 .start = ohci_device_isoc_start, 329 .abort = ohci_device_isoc_abort, 330 .close = ohci_device_isoc_close, 331 .cleartoggle = ohci_noop, 332 .done = ohci_device_isoc_done, 333 }; 334 335 int 336 ohci_activate(device_t self, enum devact act) 337 { 338 struct ohci_softc *sc = device_private(self); 339 340 switch (act) { 341 case DVACT_DEACTIVATE: 342 sc->sc_dying = 1; 343 return 0; 344 default: 345 return EOPNOTSUPP; 346 } 347 } 348 349 void 350 ohci_childdet(device_t self, device_t child) 351 { 352 struct ohci_softc *sc = device_private(self); 353 354 KASSERT(sc->sc_child == child); 355 sc->sc_child = NULL; 356 } 357 358 int 359 ohci_detach(struct ohci_softc *sc, int flags) 360 { 361 int rv = 0; 362 363 if (sc->sc_child != NULL) 364 rv = config_detach(sc->sc_child, flags); 365 366 if (rv != 0) 367 return (rv); 368 369 callout_stop(&sc->sc_tmo_rhsc); 370 371 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 372 callout_destroy(&sc->sc_tmo_rhsc); 373 374 softint_disestablish(sc->sc_rhsc_si); 375 376 cv_destroy(&sc->sc_softwake_cv); 377 378 mutex_destroy(&sc->sc_lock); 379 mutex_destroy(&sc->sc_intr_lock); 380 381 if (sc->sc_hcca != NULL) 382 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 383 pool_cache_destroy(sc->sc_xferpool); 384 385 return (rv); 386 } 387 388 ohci_soft_ed_t * 389 ohci_alloc_sed(ohci_softc_t *sc) 390 { 391 ohci_soft_ed_t *sed; 392 usbd_status err; 393 int i, offs; 394 usb_dma_t dma; 395 396 if (sc->sc_freeeds == NULL) { 397 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 398 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 399 OHCI_ED_ALIGN, &dma); 400 if (err) 401 return (0); 402 for (i = 0; i < OHCI_SED_CHUNK; i++) { 403 offs = i * OHCI_SED_SIZE; 404 sed = KERNADDR(&dma, offs); 405 sed->physaddr = DMAADDR(&dma, offs); 406 sed->dma = dma; 407 sed->offs = offs; 408 sed->next = sc->sc_freeeds; 409 sc->sc_freeeds = sed; 410 } 411 } 412 sed = sc->sc_freeeds; 413 sc->sc_freeeds = sed->next; 414 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 415 sed->next = 0; 416 return (sed); 417 } 418 419 void 420 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 421 { 422 sed->next = sc->sc_freeeds; 423 sc->sc_freeeds = sed; 424 } 425 426 ohci_soft_td_t * 427 ohci_alloc_std(ohci_softc_t *sc) 428 { 429 ohci_soft_td_t *std; 430 usbd_status err; 431 int i, offs; 432 usb_dma_t dma; 433 434 if (sc->sc_freetds == NULL) { 435 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 436 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 437 OHCI_TD_ALIGN, &dma); 438 if (err) 439 return (NULL); 440 for(i = 0; i < OHCI_STD_CHUNK; i++) { 441 offs = i * OHCI_STD_SIZE; 442 std = KERNADDR(&dma, offs); 443 std->physaddr = DMAADDR(&dma, offs); 444 std->dma = dma; 445 std->offs = offs; 446 std->nexttd = sc->sc_freetds; 447 sc->sc_freetds = std; 448 } 449 } 450 451 std = sc->sc_freetds; 452 sc->sc_freetds = std->nexttd; 453 memset(&std->td, 0, sizeof(ohci_td_t)); 454 std->nexttd = NULL; 455 std->xfer = NULL; 456 ohci_hash_add_td(sc, std); 457 458 return (std); 459 } 460 461 void 462 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 463 { 464 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 } 469 470 usbd_status 471 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 472 int alen, int rd, usbd_xfer_handle xfer, 473 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 474 { 475 ohci_soft_td_t *next, *cur; 476 ohci_physaddr_t dataphys, dataphysend; 477 u_int32_t tdflags; 478 int len, curlen; 479 usb_dma_t *dma = &xfer->dmabuf; 480 u_int16_t flags = xfer->flags; 481 482 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 483 484 KASSERT(mutex_owned(&sc->sc_lock)); 485 486 len = alen; 487 cur = sp; 488 dataphys = DMAADDR(dma, 0); 489 dataphysend = OHCI_PAGE(dataphys + len - 1); 490 usb_syncmem(dma, 0, len, 491 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 492 tdflags = HTOO32( 493 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 494 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 495 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 496 497 for (;;) { 498 next = ohci_alloc_std(sc); 499 if (next == NULL) 500 goto nomem; 501 502 /* The OHCI hardware can handle at most one page crossing. */ 503 if (OHCI_PAGE(dataphys) == dataphysend || 504 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 505 /* we can handle it in this TD */ 506 curlen = len; 507 } else { 508 /* must use multiple TDs, fill as much as possible. */ 509 curlen = 2 * OHCI_PAGE_SIZE - 510 (dataphys & (OHCI_PAGE_SIZE-1)); 511 /* the length must be a multiple of the max size */ 512 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 513 #ifdef DIAGNOSTIC 514 if (curlen == 0) 515 panic("ohci_alloc_std: curlen == 0"); 516 #endif 517 } 518 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 519 "dataphysend=0x%08x len=%d curlen=%d\n", 520 dataphys, dataphysend, 521 len, curlen)); 522 len -= curlen; 523 524 cur->td.td_flags = tdflags; 525 cur->td.td_cbp = HTOO32(dataphys); 526 cur->nexttd = next; 527 cur->td.td_nexttd = HTOO32(next->physaddr); 528 cur->td.td_be = HTOO32(dataphys + curlen - 1); 529 cur->len = curlen; 530 cur->flags = OHCI_ADD_LEN; 531 cur->xfer = xfer; 532 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 534 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 535 dataphys, dataphys + curlen - 1)); 536 if (len == 0) 537 break; 538 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 539 dataphys += curlen; 540 cur = next; 541 } 542 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 543 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 544 /* Force a 0 length transfer at the end. */ 545 546 cur = next; 547 next = ohci_alloc_std(sc); 548 if (next == NULL) 549 goto nomem; 550 551 cur->td.td_flags = tdflags; 552 cur->td.td_cbp = 0; /* indicate 0 length packet */ 553 cur->nexttd = next; 554 cur->td.td_nexttd = HTOO32(next->physaddr); 555 cur->td.td_be = ~0; 556 cur->len = 0; 557 cur->flags = 0; 558 cur->xfer = xfer; 559 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 561 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 562 } 563 *ep = cur; 564 565 return (USBD_NORMAL_COMPLETION); 566 567 nomem: 568 /* XXX free chain */ 569 return (USBD_NOMEM); 570 } 571 572 #if 0 573 Static void 574 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 575 ohci_soft_td_t *stdend) 576 { 577 ohci_soft_td_t *p; 578 579 for (; std != stdend; std = p) { 580 p = std->nexttd; 581 ohci_free_std(sc, std); 582 } 583 } 584 #endif 585 586 ohci_soft_itd_t * 587 ohci_alloc_sitd(ohci_softc_t *sc) 588 { 589 ohci_soft_itd_t *sitd; 590 usbd_status err; 591 int i, offs; 592 usb_dma_t dma; 593 594 if (sc->sc_freeitds == NULL) { 595 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 596 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 597 OHCI_ITD_ALIGN, &dma); 598 if (err) 599 return (NULL); 600 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 601 offs = i * OHCI_SITD_SIZE; 602 sitd = KERNADDR(&dma, offs); 603 sitd->physaddr = DMAADDR(&dma, offs); 604 sitd->dma = dma; 605 sitd->offs = offs; 606 sitd->nextitd = sc->sc_freeitds; 607 sc->sc_freeitds = sitd; 608 } 609 } 610 611 sitd = sc->sc_freeitds; 612 sc->sc_freeitds = sitd->nextitd; 613 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 614 sitd->nextitd = NULL; 615 sitd->xfer = NULL; 616 ohci_hash_add_itd(sc, sitd); 617 618 #ifdef DIAGNOSTIC 619 sitd->isdone = 0; 620 #endif 621 622 return (sitd); 623 } 624 625 void 626 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 627 { 628 629 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 630 631 #ifdef DIAGNOSTIC 632 if (!sitd->isdone) { 633 panic("ohci_free_sitd: sitd=%p not done", sitd); 634 return; 635 } 636 /* Warn double free */ 637 sitd->isdone = 0; 638 #endif 639 640 ohci_hash_rem_itd(sc, sitd); 641 sitd->nextitd = sc->sc_freeitds; 642 sc->sc_freeitds = sitd; 643 } 644 645 usbd_status 646 ohci_init(ohci_softc_t *sc) 647 { 648 ohci_soft_ed_t *sed, *psed; 649 usbd_status err; 650 int i; 651 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 652 653 DPRINTF(("ohci_init: start\n")); 654 aprint_normal_dev(sc->sc_dev, ""); 655 656 sc->sc_hcca = NULL; 657 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 658 659 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 660 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 661 cv_init(&sc->sc_softwake_cv, "ohciab"); 662 663 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 664 ohci_rhsc_softint, sc); 665 666 for (i = 0; i < OHCI_HASH_SIZE; i++) 667 LIST_INIT(&sc->sc_hash_tds[i]); 668 for (i = 0; i < OHCI_HASH_SIZE; i++) 669 LIST_INIT(&sc->sc_hash_itds[i]); 670 671 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 672 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 673 674 rev = OREAD4(sc, OHCI_REVISION); 675 aprint_normal("OHCI version %d.%d%s\n", 676 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 677 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 678 679 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 680 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 681 sc->sc_bus.usbrev = USBREV_UNKNOWN; 682 return (USBD_INVAL); 683 } 684 sc->sc_bus.usbrev = USBREV_1_0; 685 686 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 687 USB_MEM_RESERVE); 688 689 /* XXX determine alignment by R/W */ 690 /* Allocate the HCCA area. */ 691 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 692 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 693 if (err) { 694 sc->sc_hcca = NULL; 695 return err; 696 } 697 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 698 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 699 700 sc->sc_eintrs = OHCI_NORMAL_INTRS; 701 702 /* Allocate dummy ED that starts the control list. */ 703 sc->sc_ctrl_head = ohci_alloc_sed(sc); 704 if (sc->sc_ctrl_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad1; 707 } 708 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 709 710 /* Allocate dummy ED that starts the bulk list. */ 711 sc->sc_bulk_head = ohci_alloc_sed(sc); 712 if (sc->sc_bulk_head == NULL) { 713 err = USBD_NOMEM; 714 goto bad2; 715 } 716 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 717 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 718 sizeof(sc->sc_bulk_head->ed), 719 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 720 721 /* Allocate dummy ED that starts the isochronous list. */ 722 sc->sc_isoc_head = ohci_alloc_sed(sc); 723 if (sc->sc_isoc_head == NULL) { 724 err = USBD_NOMEM; 725 goto bad3; 726 } 727 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 728 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 729 sizeof(sc->sc_isoc_head->ed), 730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 731 732 /* Allocate all the dummy EDs that make up the interrupt tree. */ 733 for (i = 0; i < OHCI_NO_EDS; i++) { 734 sed = ohci_alloc_sed(sc); 735 if (sed == NULL) { 736 while (--i >= 0) 737 ohci_free_sed(sc, sc->sc_eds[i]); 738 err = USBD_NOMEM; 739 goto bad4; 740 } 741 /* All ED fields are set to 0. */ 742 sc->sc_eds[i] = sed; 743 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 744 if (i != 0) 745 psed = sc->sc_eds[(i-1) / 2]; 746 else 747 psed= sc->sc_isoc_head; 748 sed->next = psed; 749 sed->ed.ed_nexted = HTOO32(psed->physaddr); 750 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 } 753 /* 754 * Fill HCCA interrupt table. The bit reversal is to get 755 * the tree set up properly to spread the interrupts. 756 */ 757 for (i = 0; i < OHCI_NO_INTRS; i++) 758 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 759 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 760 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 761 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 762 763 #ifdef OHCI_DEBUG 764 if (ohcidebug > 15) { 765 for (i = 0; i < OHCI_NO_EDS; i++) { 766 printf("ed#%d ", i); 767 ohci_dump_ed(sc, sc->sc_eds[i]); 768 } 769 printf("iso "); 770 ohci_dump_ed(sc, sc->sc_isoc_head); 771 } 772 #endif 773 774 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 775 ctl = OREAD4(sc, OHCI_CONTROL); 776 rwc = ctl & OHCI_RWC; 777 fm = OREAD4(sc, OHCI_FM_INTERVAL); 778 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 779 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 780 781 /* Determine in what context we are running. */ 782 if (ctl & OHCI_IR) { 783 /* SMM active, request change */ 784 DPRINTF(("ohci_init: SMM active, request owner change\n")); 785 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 786 (OHCI_OC | OHCI_MIE)) 787 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 788 s = OREAD4(sc, OHCI_COMMAND_STATUS); 789 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 790 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 791 usb_delay_ms(&sc->sc_bus, 1); 792 ctl = OREAD4(sc, OHCI_CONTROL); 793 } 794 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 795 if ((ctl & OHCI_IR) == 0) { 796 aprint_error_dev(sc->sc_dev, 797 "SMM does not respond, resetting\n"); 798 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 799 goto reset; 800 } 801 #if 0 802 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 803 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 804 /* BIOS started controller. */ 805 DPRINTF(("ohci_init: BIOS active\n")); 806 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 807 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 808 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 809 } 810 #endif 811 } else { 812 DPRINTF(("ohci_init: cold started\n")); 813 reset: 814 /* Controller was cold started. */ 815 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 816 } 817 818 /* 819 * This reset should not be necessary according to the OHCI spec, but 820 * without it some controllers do not start. 821 */ 822 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 823 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 824 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 825 826 /* We now own the host controller and the bus has been reset. */ 827 828 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 829 /* Nominal time for a reset is 10 us. */ 830 for (i = 0; i < 10; i++) { 831 delay(10); 832 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 833 if (!hcr) 834 break; 835 } 836 if (hcr) { 837 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 838 err = USBD_IOERROR; 839 goto bad5; 840 } 841 #ifdef OHCI_DEBUG 842 if (ohcidebug > 15) 843 ohci_dumpregs(sc); 844 #endif 845 846 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 847 848 /* Set up HC registers. */ 849 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 850 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 851 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 852 /* disable all interrupts and then switch on all desired interrupts */ 853 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 854 /* switch on desired functional features */ 855 ctl = OREAD4(sc, OHCI_CONTROL); 856 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 857 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 858 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 859 /* And finally start it! */ 860 OWRITE4(sc, OHCI_CONTROL, ctl); 861 862 /* 863 * The controller is now OPERATIONAL. Set a some final 864 * registers that should be set earlier, but that the 865 * controller ignores when in the SUSPEND state. 866 */ 867 ival = OHCI_GET_IVAL(fm); 868 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 869 fm |= OHCI_FSMPS(ival) | ival; 870 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 871 per = OHCI_PERIODIC(ival); /* 90% periodic */ 872 OWRITE4(sc, OHCI_PERIODIC_START, per); 873 874 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 875 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 876 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 877 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 878 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 879 880 /* 881 * The AMD756 requires a delay before re-reading the register, 882 * otherwise it will occasionally report 0 ports. 883 */ 884 sc->sc_noport = 0; 885 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 886 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 887 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 888 } 889 890 #ifdef OHCI_DEBUG 891 if (ohcidebug > 5) 892 ohci_dumpregs(sc); 893 #endif 894 895 /* Set up the bus struct. */ 896 sc->sc_bus.methods = &ohci_bus_methods; 897 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 898 899 sc->sc_control = sc->sc_intre = 0; 900 901 /* Finally, turn on interrupts. */ 902 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 903 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 904 905 return (USBD_NORMAL_COMPLETION); 906 907 bad5: 908 for (i = 0; i < OHCI_NO_EDS; i++) 909 ohci_free_sed(sc, sc->sc_eds[i]); 910 bad4: 911 ohci_free_sed(sc, sc->sc_isoc_head); 912 bad3: 913 ohci_free_sed(sc, sc->sc_bulk_head); 914 bad2: 915 ohci_free_sed(sc, sc->sc_ctrl_head); 916 bad1: 917 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 918 sc->sc_hcca = NULL; 919 return (err); 920 } 921 922 usbd_status 923 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 924 { 925 struct ohci_softc *sc = bus->hci_private; 926 usbd_status status; 927 928 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 929 if (status == USBD_NOMEM) 930 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 931 return status; 932 } 933 934 void 935 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 936 { 937 struct ohci_softc *sc = bus->hci_private; 938 if (dma->block->flags & USB_DMA_RESERVE) { 939 usb_reserve_freem(&sc->sc_dma_reserve, dma); 940 return; 941 } 942 usb_freemem(&sc->sc_bus, dma); 943 } 944 945 usbd_xfer_handle 946 ohci_allocx(struct usbd_bus *bus) 947 { 948 struct ohci_softc *sc = bus->hci_private; 949 usbd_xfer_handle xfer; 950 951 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 952 if (xfer != NULL) { 953 memset(xfer, 0, sizeof(struct ohci_xfer)); 954 #ifdef DIAGNOSTIC 955 xfer->busy_free = XFER_BUSY; 956 #endif 957 } 958 return (xfer); 959 } 960 961 void 962 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 963 { 964 struct ohci_softc *sc = bus->hci_private; 965 966 #ifdef DIAGNOSTIC 967 if (xfer->busy_free != XFER_BUSY) { 968 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 969 xfer->busy_free); 970 } 971 xfer->busy_free = XFER_FREE; 972 #endif 973 pool_cache_put(sc->sc_xferpool, xfer); 974 } 975 976 Static void 977 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 978 { 979 struct ohci_softc *sc = bus->hci_private; 980 981 *lock = &sc->sc_lock; 982 } 983 984 /* 985 * Shut down the controller when the system is going down. 986 */ 987 bool 988 ohci_shutdown(device_t self, int flags) 989 { 990 ohci_softc_t *sc = device_private(self); 991 992 DPRINTF(("ohci_shutdown: stopping the HC\n")); 993 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 994 return true; 995 } 996 997 bool 998 ohci_resume(device_t dv, const pmf_qual_t *qual) 999 { 1000 ohci_softc_t *sc = device_private(dv); 1001 uint32_t ctl; 1002 1003 mutex_spin_enter(&sc->sc_intr_lock); 1004 sc->sc_bus.use_polling++; 1005 mutex_spin_exit(&sc->sc_intr_lock); 1006 1007 /* Some broken BIOSes do not recover these values */ 1008 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1009 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1010 sc->sc_ctrl_head->physaddr); 1011 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1012 sc->sc_bulk_head->physaddr); 1013 if (sc->sc_intre) 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1015 (OHCI_ALL_INTRS | OHCI_MIE)); 1016 if (sc->sc_control) 1017 ctl = sc->sc_control; 1018 else 1019 ctl = OREAD4(sc, OHCI_CONTROL); 1020 ctl |= OHCI_HCFS_RESUME; 1021 OWRITE4(sc, OHCI_CONTROL, ctl); 1022 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1023 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1024 OWRITE4(sc, OHCI_CONTROL, ctl); 1025 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1026 sc->sc_control = sc->sc_intre = 0; 1027 1028 mutex_spin_enter(&sc->sc_intr_lock); 1029 sc->sc_bus.use_polling--; 1030 mutex_spin_exit(&sc->sc_intr_lock); 1031 1032 return true; 1033 } 1034 1035 bool 1036 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1037 { 1038 ohci_softc_t *sc = device_private(dv); 1039 uint32_t ctl; 1040 1041 mutex_spin_enter(&sc->sc_intr_lock); 1042 sc->sc_bus.use_polling++; 1043 mutex_spin_exit(&sc->sc_intr_lock); 1044 1045 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1046 if (sc->sc_control == 0) { 1047 /* 1048 * Preserve register values, in case that BIOS 1049 * does not recover them. 1050 */ 1051 sc->sc_control = ctl; 1052 sc->sc_intre = OREAD4(sc, 1053 OHCI_INTERRUPT_ENABLE); 1054 } 1055 ctl |= OHCI_HCFS_SUSPEND; 1056 OWRITE4(sc, OHCI_CONTROL, ctl); 1057 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1058 1059 mutex_spin_enter(&sc->sc_intr_lock); 1060 sc->sc_bus.use_polling--; 1061 mutex_spin_exit(&sc->sc_intr_lock); 1062 1063 return true; 1064 } 1065 1066 #ifdef OHCI_DEBUG 1067 void 1068 ohci_dumpregs(ohci_softc_t *sc) 1069 { 1070 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1071 OREAD4(sc, OHCI_REVISION), 1072 OREAD4(sc, OHCI_CONTROL), 1073 OREAD4(sc, OHCI_COMMAND_STATUS))); 1074 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1075 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1076 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1077 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1078 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1079 OREAD4(sc, OHCI_HCCA), 1080 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1081 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1082 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1083 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1084 OREAD4(sc, OHCI_BULK_HEAD_ED), 1085 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1086 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1087 OREAD4(sc, OHCI_DONE_HEAD), 1088 OREAD4(sc, OHCI_FM_INTERVAL), 1089 OREAD4(sc, OHCI_FM_REMAINING))); 1090 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1091 OREAD4(sc, OHCI_FM_NUMBER), 1092 OREAD4(sc, OHCI_PERIODIC_START), 1093 OREAD4(sc, OHCI_LS_THRESHOLD))); 1094 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1095 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1096 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1097 OREAD4(sc, OHCI_RH_STATUS))); 1098 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1099 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1100 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1101 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1102 O32TOH(sc->sc_hcca->hcca_frame_number), 1103 O32TOH(sc->sc_hcca->hcca_done_head))); 1104 } 1105 #endif 1106 1107 Static int ohci_intr1(ohci_softc_t *); 1108 1109 int 1110 ohci_intr(void *p) 1111 { 1112 ohci_softc_t *sc = p; 1113 int ret = 0; 1114 1115 if (sc == NULL) 1116 return (0); 1117 1118 mutex_spin_enter(&sc->sc_intr_lock); 1119 1120 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1121 goto done; 1122 1123 /* If we get an interrupt while polling, then just ignore it. */ 1124 if (sc->sc_bus.use_polling) { 1125 #ifdef DIAGNOSTIC 1126 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1127 #endif 1128 /* for level triggered intrs, should do something to ack */ 1129 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1130 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1131 1132 goto done; 1133 } 1134 1135 ret = ohci_intr1(sc); 1136 1137 done: 1138 mutex_spin_exit(&sc->sc_intr_lock); 1139 return ret; 1140 } 1141 1142 Static int 1143 ohci_intr1(ohci_softc_t *sc) 1144 { 1145 u_int32_t intrs, eintrs; 1146 1147 DPRINTFN(14,("ohci_intr1: enter\n")); 1148 1149 /* In case the interrupt occurs before initialization has completed. */ 1150 if (sc == NULL || sc->sc_hcca == NULL) { 1151 #ifdef DIAGNOSTIC 1152 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1153 #endif 1154 return (0); 1155 } 1156 1157 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1158 1159 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1160 if (!intrs) 1161 return (0); 1162 1163 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1164 eintrs = intrs & sc->sc_eintrs; 1165 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1166 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1167 (u_int)eintrs, sc->sc_eintrs)); 1168 1169 if (!eintrs) { 1170 return (0); 1171 } 1172 1173 sc->sc_bus.no_intrs++; 1174 if (eintrs & OHCI_SO) { 1175 sc->sc_overrun_cnt++; 1176 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1177 printf("%s: %u scheduling overruns\n", 1178 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1179 sc->sc_overrun_cnt = 0; 1180 } 1181 /* XXX do what */ 1182 eintrs &= ~OHCI_SO; 1183 } 1184 if (eintrs & OHCI_WDH) { 1185 /* 1186 * We block the interrupt below, and reenable it later from 1187 * ohci_softintr(). 1188 */ 1189 usb_schedsoftintr(&sc->sc_bus); 1190 } 1191 if (eintrs & OHCI_RD) { 1192 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1193 /* XXX process resume detect */ 1194 } 1195 if (eintrs & OHCI_UE) { 1196 printf("%s: unrecoverable error, controller halted\n", 1197 device_xname(sc->sc_dev)); 1198 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1199 /* XXX what else */ 1200 } 1201 if (eintrs & OHCI_RHSC) { 1202 /* 1203 * We block the interrupt below, and reenable it later from 1204 * a timeout. 1205 */ 1206 softint_schedule(sc->sc_rhsc_si); 1207 } 1208 1209 if (eintrs != 0) { 1210 /* Block unprocessed interrupts. */ 1211 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1212 sc->sc_eintrs &= ~eintrs; 1213 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1214 device_xname(sc->sc_dev), eintrs)); 1215 } 1216 1217 return (1); 1218 } 1219 1220 void 1221 ohci_rhsc_enable(void *v_sc) 1222 { 1223 ohci_softc_t *sc = v_sc; 1224 1225 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1226 mutex_spin_enter(&sc->sc_intr_lock); 1227 sc->sc_eintrs |= OHCI_RHSC; 1228 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1229 mutex_spin_exit(&sc->sc_intr_lock); 1230 } 1231 1232 #ifdef OHCI_DEBUG 1233 const char *ohci_cc_strs[] = { 1234 "NO_ERROR", 1235 "CRC", 1236 "BIT_STUFFING", 1237 "DATA_TOGGLE_MISMATCH", 1238 "STALL", 1239 "DEVICE_NOT_RESPONDING", 1240 "PID_CHECK_FAILURE", 1241 "UNEXPECTED_PID", 1242 "DATA_OVERRUN", 1243 "DATA_UNDERRUN", 1244 "BUFFER_OVERRUN", 1245 "BUFFER_UNDERRUN", 1246 "reserved", 1247 "reserved", 1248 "NOT_ACCESSED", 1249 "NOT_ACCESSED", 1250 }; 1251 #endif 1252 1253 void 1254 ohci_softintr(void *v) 1255 { 1256 struct usbd_bus *bus = v; 1257 ohci_softc_t *sc = bus->hci_private; 1258 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1259 ohci_soft_td_t *std, *sdone, *stdnext; 1260 usbd_xfer_handle xfer; 1261 struct ohci_pipe *opipe; 1262 int len, cc; 1263 int i, j, actlen, iframes, uedir; 1264 ohci_physaddr_t done; 1265 1266 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1267 1268 DPRINTFN(10,("ohci_softintr: enter\n")); 1269 1270 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1271 sizeof(sc->sc_hcca->hcca_done_head), 1272 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1273 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1274 sc->sc_hcca->hcca_done_head = 0; 1275 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1276 sizeof(sc->sc_hcca->hcca_done_head), 1277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1278 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1279 sc->sc_eintrs |= OHCI_WDH; 1280 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1281 1282 /* Reverse the done list. */ 1283 for (sdone = NULL, sidone = NULL; done != 0; ) { 1284 std = ohci_hash_find_td(sc, done); 1285 if (std != NULL) { 1286 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1288 std->dnext = sdone; 1289 done = O32TOH(std->td.td_nexttd); 1290 sdone = std; 1291 DPRINTFN(10,("add TD %p\n", std)); 1292 continue; 1293 } 1294 sitd = ohci_hash_find_itd(sc, done); 1295 if (sitd != NULL) { 1296 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1297 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1298 sitd->dnext = sidone; 1299 done = O32TOH(sitd->itd.itd_nextitd); 1300 sidone = sitd; 1301 DPRINTFN(5,("add ITD %p\n", sitd)); 1302 continue; 1303 } 1304 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1305 (u_long)done); 1306 break; 1307 } 1308 1309 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1310 1311 #ifdef OHCI_DEBUG 1312 if (ohcidebug > 10) { 1313 DPRINTF(("ohci_process_done: TD done:\n")); 1314 ohci_dump_tds(sc, sdone); 1315 } 1316 #endif 1317 1318 for (std = sdone; std; std = stdnext) { 1319 xfer = std->xfer; 1320 stdnext = std->dnext; 1321 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1322 std, xfer, xfer ? xfer->hcpriv : 0)); 1323 if (xfer == NULL) { 1324 /* 1325 * xfer == NULL: There seems to be no xfer associated 1326 * with this TD. It is tailp that happened to end up on 1327 * the done queue. 1328 * Shouldn't happen, but some chips are broken(?). 1329 */ 1330 continue; 1331 } 1332 if (xfer->status == USBD_CANCELLED || 1333 xfer->status == USBD_TIMEOUT) { 1334 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1335 xfer)); 1336 /* Handled by abort routine. */ 1337 continue; 1338 } 1339 callout_stop(&xfer->timeout_handle); 1340 1341 len = std->len; 1342 if (std->td.td_cbp != 0) 1343 len -= O32TOH(std->td.td_be) - 1344 O32TOH(std->td.td_cbp) + 1; 1345 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1346 std->flags)); 1347 if (std->flags & OHCI_ADD_LEN) 1348 xfer->actlen += len; 1349 1350 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1351 if (cc == OHCI_CC_NO_ERROR) { 1352 if (std->flags & OHCI_CALL_DONE) { 1353 xfer->status = USBD_NORMAL_COMPLETION; 1354 usb_transfer_complete(xfer); 1355 } 1356 ohci_free_std(sc, std); 1357 } else { 1358 /* 1359 * Endpoint is halted. First unlink all the TDs 1360 * belonging to the failed transfer, and then restart 1361 * the endpoint. 1362 */ 1363 ohci_soft_td_t *p, *n; 1364 opipe = (struct ohci_pipe *)xfer->pipe; 1365 1366 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1367 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1368 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1369 1370 /* remove TDs */ 1371 for (p = std; p->xfer == xfer; p = n) { 1372 n = p->nexttd; 1373 ohci_free_std(sc, p); 1374 } 1375 1376 /* clear halt */ 1377 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1378 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1379 1380 if (cc == OHCI_CC_STALL) 1381 xfer->status = USBD_STALLED; 1382 else 1383 xfer->status = USBD_IOERROR; 1384 usb_transfer_complete(xfer); 1385 } 1386 } 1387 1388 #ifdef OHCI_DEBUG 1389 if (ohcidebug > 10) { 1390 DPRINTF(("ohci_softintr: ITD done:\n")); 1391 ohci_dump_itds(sc, sidone); 1392 } 1393 #endif 1394 1395 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1396 xfer = sitd->xfer; 1397 sitdnext = sitd->dnext; 1398 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1399 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1400 if (xfer == NULL) 1401 continue; 1402 if (xfer->status == USBD_CANCELLED || 1403 xfer->status == USBD_TIMEOUT) { 1404 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1405 xfer)); 1406 /* Handled by abort routine. */ 1407 continue; 1408 } 1409 #ifdef DIAGNOSTIC 1410 if (sitd->isdone) 1411 printf("ohci_softintr: sitd=%p is done\n", sitd); 1412 sitd->isdone = 1; 1413 #endif 1414 if (sitd->flags & OHCI_CALL_DONE) { 1415 ohci_soft_itd_t *next; 1416 1417 opipe = (struct ohci_pipe *)xfer->pipe; 1418 opipe->u.iso.inuse -= xfer->nframes; 1419 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1420 bEndpointAddress); 1421 xfer->status = USBD_NORMAL_COMPLETION; 1422 actlen = 0; 1423 for (i = 0, sitd = xfer->hcpriv;; 1424 sitd = next) { 1425 next = sitd->nextitd; 1426 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1427 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1428 xfer->status = USBD_IOERROR; 1429 /* For input, update frlengths with actual */ 1430 /* XXX anything necessary for output? */ 1431 if (uedir == UE_DIR_IN && 1432 xfer->status == USBD_NORMAL_COMPLETION) { 1433 iframes = OHCI_ITD_GET_FC(O32TOH( 1434 sitd->itd.itd_flags)); 1435 for (j = 0; j < iframes; i++, j++) { 1436 len = O16TOH(sitd-> 1437 itd.itd_offset[j]); 1438 if ((OHCI_ITD_PSW_GET_CC(len) & 1439 OHCI_CC_NOT_ACCESSED_MASK) 1440 == OHCI_CC_NOT_ACCESSED) 1441 len = 0; 1442 else 1443 len = OHCI_ITD_PSW_LENGTH(len); 1444 xfer->frlengths[i] = len; 1445 actlen += len; 1446 } 1447 } 1448 if (sitd->flags & OHCI_CALL_DONE) 1449 break; 1450 ohci_free_sitd(sc, sitd); 1451 } 1452 ohci_free_sitd(sc, sitd); 1453 if (uedir == UE_DIR_IN && 1454 xfer->status == USBD_NORMAL_COMPLETION) 1455 xfer->actlen = actlen; 1456 xfer->hcpriv = NULL; 1457 1458 usb_transfer_complete(xfer); 1459 } 1460 } 1461 1462 if (sc->sc_softwake) { 1463 sc->sc_softwake = 0; 1464 cv_broadcast(&sc->sc_softwake_cv); 1465 } 1466 1467 DPRINTFN(10,("ohci_softintr: done:\n")); 1468 } 1469 1470 void 1471 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1472 { 1473 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1474 #ifdef DIAGNOSTIC 1475 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1476 #endif 1477 int len = UGETW(xfer->request.wLength); 1478 int isread = (xfer->request.bmRequestType & UT_READ); 1479 1480 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1481 1482 KASSERT(mutex_owned(&sc->sc_lock)); 1483 1484 #ifdef DIAGNOSTIC 1485 if (!(xfer->rqflags & URQ_REQUEST)) { 1486 panic("ohci_device_ctrl_done: not a request"); 1487 } 1488 #endif 1489 if (len) 1490 usb_syncmem(&xfer->dmabuf, 0, len, 1491 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1492 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1493 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1494 } 1495 1496 void 1497 ohci_device_intr_done(usbd_xfer_handle xfer) 1498 { 1499 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1500 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1501 ohci_soft_ed_t *sed = opipe->sed; 1502 ohci_soft_td_t *data, *tail; 1503 int isread = 1504 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1505 1506 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1507 xfer, xfer->actlen)); 1508 1509 KASSERT(mutex_owned(&sc->sc_lock)); 1510 1511 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1512 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1513 if (xfer->pipe->repeat) { 1514 data = opipe->tail.td; 1515 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1516 if (tail == NULL) { 1517 xfer->status = USBD_NOMEM; 1518 return; 1519 } 1520 tail->xfer = NULL; 1521 1522 data->td.td_flags = HTOO32( 1523 OHCI_TD_IN | OHCI_TD_NOCC | 1524 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1525 if (xfer->flags & USBD_SHORT_XFER_OK) 1526 data->td.td_flags |= HTOO32(OHCI_TD_R); 1527 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1528 data->nexttd = tail; 1529 data->td.td_nexttd = HTOO32(tail->physaddr); 1530 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1531 xfer->length - 1); 1532 data->len = xfer->length; 1533 data->xfer = xfer; 1534 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1535 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1536 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1537 xfer->hcpriv = data; 1538 xfer->actlen = 0; 1539 1540 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1541 usb_syncmem(&sed->dma, 1542 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1543 sizeof(sed->ed.ed_tailp), 1544 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1545 opipe->tail.td = tail; 1546 } 1547 } 1548 1549 void 1550 ohci_device_bulk_done(usbd_xfer_handle xfer) 1551 { 1552 #ifdef DIAGNOSTIC 1553 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1554 #endif 1555 int isread = 1556 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1557 1558 KASSERT(mutex_owned(&sc->sc_lock)); 1559 1560 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1561 xfer, xfer->actlen)); 1562 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1563 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1564 } 1565 1566 Static void 1567 ohci_rhsc_softint(void *arg) 1568 { 1569 ohci_softc_t *sc = arg; 1570 1571 mutex_enter(&sc->sc_lock); 1572 1573 ohci_rhsc(sc, sc->sc_intrxfer); 1574 1575 /* Do not allow RHSC interrupts > 1 per second */ 1576 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1577 1578 mutex_exit(&sc->sc_lock); 1579 } 1580 1581 void 1582 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1583 { 1584 usbd_pipe_handle pipe; 1585 u_char *p; 1586 int i, m; 1587 int hstatus; 1588 1589 KASSERT(mutex_owned(&sc->sc_lock)); 1590 1591 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1592 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1593 sc, xfer, hstatus)); 1594 1595 if (xfer == NULL) { 1596 /* Just ignore the change. */ 1597 return; 1598 } 1599 1600 pipe = xfer->pipe; 1601 1602 p = KERNADDR(&xfer->dmabuf, 0); 1603 m = min(sc->sc_noport, xfer->length * 8 - 1); 1604 memset(p, 0, xfer->length); 1605 for (i = 1; i <= m; i++) { 1606 /* Pick out CHANGE bits from the status reg. */ 1607 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1608 p[i/8] |= 1 << (i%8); 1609 } 1610 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1611 xfer->actlen = xfer->length; 1612 xfer->status = USBD_NORMAL_COMPLETION; 1613 1614 usb_transfer_complete(xfer); 1615 } 1616 1617 void 1618 ohci_root_intr_done(usbd_xfer_handle xfer) 1619 { 1620 } 1621 1622 void 1623 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1624 { 1625 } 1626 1627 /* 1628 * Wait here until controller claims to have an interrupt. 1629 * Then call ohci_intr and return. Use timeout to avoid waiting 1630 * too long. 1631 */ 1632 void 1633 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1634 { 1635 int timo; 1636 u_int32_t intrs; 1637 1638 mutex_enter(&sc->sc_lock); 1639 1640 xfer->status = USBD_IN_PROGRESS; 1641 for (timo = xfer->timeout; timo >= 0; timo--) { 1642 usb_delay_ms(&sc->sc_bus, 1); 1643 if (sc->sc_dying) 1644 break; 1645 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1646 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1647 #ifdef OHCI_DEBUG 1648 if (ohcidebug > 15) 1649 ohci_dumpregs(sc); 1650 #endif 1651 if (intrs) { 1652 mutex_spin_enter(&sc->sc_intr_lock); 1653 ohci_intr1(sc); 1654 mutex_spin_exit(&sc->sc_intr_lock); 1655 if (xfer->status != USBD_IN_PROGRESS) 1656 goto done; 1657 } 1658 } 1659 1660 /* Timeout */ 1661 DPRINTF(("ohci_waitintr: timeout\n")); 1662 xfer->status = USBD_TIMEOUT; 1663 usb_transfer_complete(xfer); 1664 1665 /* XXX should free TD */ 1666 1667 done: 1668 mutex_exit(&sc->sc_lock); 1669 } 1670 1671 void 1672 ohci_poll(struct usbd_bus *bus) 1673 { 1674 ohci_softc_t *sc = bus->hci_private; 1675 #ifdef OHCI_DEBUG 1676 static int last; 1677 int new; 1678 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1679 if (new != last) { 1680 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1681 last = new; 1682 } 1683 #endif 1684 1685 sc->sc_eintrs |= OHCI_WDH; 1686 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1687 mutex_spin_enter(&sc->sc_intr_lock); 1688 ohci_intr1(sc); 1689 mutex_spin_exit(&sc->sc_intr_lock); 1690 } 1691 } 1692 1693 usbd_status 1694 ohci_device_request(usbd_xfer_handle xfer) 1695 { 1696 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1697 usb_device_request_t *req = &xfer->request; 1698 usbd_device_handle dev = opipe->pipe.device; 1699 ohci_softc_t *sc = dev->bus->hci_private; 1700 int addr = dev->address; 1701 ohci_soft_td_t *setup, *stat, *next, *tail; 1702 ohci_soft_ed_t *sed; 1703 int isread; 1704 int len; 1705 usbd_status err; 1706 1707 KASSERT(mutex_owned(&sc->sc_lock)); 1708 1709 isread = req->bmRequestType & UT_READ; 1710 len = UGETW(req->wLength); 1711 1712 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1713 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1714 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1715 UGETW(req->wIndex), len, addr, 1716 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1717 1718 setup = opipe->tail.td; 1719 stat = ohci_alloc_std(sc); 1720 if (stat == NULL) { 1721 err = USBD_NOMEM; 1722 goto bad1; 1723 } 1724 tail = ohci_alloc_std(sc); 1725 if (tail == NULL) { 1726 err = USBD_NOMEM; 1727 goto bad2; 1728 } 1729 tail->xfer = NULL; 1730 1731 sed = opipe->sed; 1732 opipe->u.ctl.length = len; 1733 1734 /* Update device address and length since they may have changed 1735 during the setup of the control pipe in usbd_new_device(). */ 1736 /* XXX This only needs to be done once, but it's too early in open. */ 1737 /* XXXX Should not touch ED here! */ 1738 1739 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1740 sizeof(sed->ed.ed_flags), 1741 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1742 sed->ed.ed_flags = HTOO32( 1743 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1744 OHCI_ED_SET_FA(addr) | 1745 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1746 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1747 sizeof(sed->ed.ed_flags), 1748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1749 1750 next = stat; 1751 1752 /* Set up data transaction */ 1753 if (len != 0) { 1754 ohci_soft_td_t *std = stat; 1755 1756 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1757 std, &stat); 1758 stat = stat->nexttd; /* point at free TD */ 1759 if (err) 1760 goto bad3; 1761 /* Start toggle at 1 and then use the carried toggle. */ 1762 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1763 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1764 usb_syncmem(&std->dma, 1765 std->offs + offsetof(ohci_td_t, td_flags), 1766 sizeof(std->td.td_flags), 1767 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1768 } 1769 1770 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1771 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1772 1773 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1774 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1775 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1776 setup->nexttd = next; 1777 setup->td.td_nexttd = HTOO32(next->physaddr); 1778 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1779 setup->len = 0; 1780 setup->xfer = xfer; 1781 setup->flags = 0; 1782 xfer->hcpriv = setup; 1783 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1785 1786 stat->td.td_flags = HTOO32( 1787 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1788 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1789 stat->td.td_cbp = 0; 1790 stat->nexttd = tail; 1791 stat->td.td_nexttd = HTOO32(tail->physaddr); 1792 stat->td.td_be = 0; 1793 stat->flags = OHCI_CALL_DONE; 1794 stat->len = 0; 1795 stat->xfer = xfer; 1796 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1797 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1798 1799 #ifdef OHCI_DEBUG 1800 if (ohcidebug > 5) { 1801 DPRINTF(("ohci_device_request:\n")); 1802 ohci_dump_ed(sc, sed); 1803 ohci_dump_tds(sc, setup); 1804 } 1805 #endif 1806 1807 /* Insert ED in schedule */ 1808 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1809 usb_syncmem(&sed->dma, 1810 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1811 sizeof(sed->ed.ed_tailp), 1812 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1813 opipe->tail.td = tail; 1814 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1815 if (xfer->timeout && !sc->sc_bus.use_polling) { 1816 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1817 ohci_timeout, xfer); 1818 } 1819 1820 #ifdef OHCI_DEBUG 1821 if (ohcidebug > 20) { 1822 delay(10000); 1823 DPRINTF(("ohci_device_request: status=%x\n", 1824 OREAD4(sc, OHCI_COMMAND_STATUS))); 1825 ohci_dumpregs(sc); 1826 printf("ctrl head:\n"); 1827 ohci_dump_ed(sc, sc->sc_ctrl_head); 1828 printf("sed:\n"); 1829 ohci_dump_ed(sc, sed); 1830 ohci_dump_tds(sc, setup); 1831 } 1832 #endif 1833 1834 return (USBD_NORMAL_COMPLETION); 1835 1836 bad3: 1837 ohci_free_std(sc, tail); 1838 bad2: 1839 ohci_free_std(sc, stat); 1840 bad1: 1841 return (err); 1842 } 1843 1844 /* 1845 * Add an ED to the schedule. Called with USB lock held. 1846 */ 1847 Static void 1848 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1849 { 1850 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1851 1852 KASSERT(mutex_owned(&sc->sc_lock)); 1853 1854 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1855 sizeof(head->ed.ed_nexted), 1856 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1857 sed->next = head->next; 1858 sed->ed.ed_nexted = head->ed.ed_nexted; 1859 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1860 sizeof(sed->ed.ed_nexted), 1861 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1862 head->next = sed; 1863 head->ed.ed_nexted = HTOO32(sed->physaddr); 1864 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1865 sizeof(head->ed.ed_nexted), 1866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1867 } 1868 1869 /* 1870 * Remove an ED from the schedule. Called with USB lock held. 1871 */ 1872 Static void 1873 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1874 { 1875 ohci_soft_ed_t *p; 1876 1877 KASSERT(mutex_owned(&sc->sc_lock)); 1878 1879 /* XXX */ 1880 for (p = head; p != NULL && p->next != sed; p = p->next) 1881 ; 1882 if (p == NULL) 1883 panic("ohci_rem_ed: ED not found"); 1884 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1885 sizeof(sed->ed.ed_nexted), 1886 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1887 p->next = sed->next; 1888 p->ed.ed_nexted = sed->ed.ed_nexted; 1889 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1890 sizeof(p->ed.ed_nexted), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 } 1893 1894 /* 1895 * When a transfer is completed the TD is added to the done queue by 1896 * the host controller. This queue is the processed by software. 1897 * Unfortunately the queue contains the physical address of the TD 1898 * and we have no simple way to translate this back to a kernel address. 1899 * To make the translation possible (and fast) we use a hash table of 1900 * TDs currently in the schedule. The physical address is used as the 1901 * hash value. 1902 */ 1903 1904 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1905 /* Called with USB lock held. */ 1906 void 1907 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1908 { 1909 int h = HASH(std->physaddr); 1910 1911 KASSERT(mutex_owned(&sc->sc_lock)); 1912 1913 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1914 } 1915 1916 /* Called with USB lock held. */ 1917 void 1918 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1919 { 1920 1921 KASSERT(mutex_owned(&sc->sc_lock)); 1922 1923 LIST_REMOVE(std, hnext); 1924 } 1925 1926 ohci_soft_td_t * 1927 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1928 { 1929 int h = HASH(a); 1930 ohci_soft_td_t *std; 1931 1932 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1933 std != NULL; 1934 std = LIST_NEXT(std, hnext)) 1935 if (std->physaddr == a) 1936 return (std); 1937 return (NULL); 1938 } 1939 1940 /* Called with USB lock held. */ 1941 void 1942 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1943 { 1944 int h = HASH(sitd->physaddr); 1945 1946 KASSERT(mutex_owned(&sc->sc_lock)); 1947 1948 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1949 sitd, (u_long)sitd->physaddr)); 1950 1951 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1952 } 1953 1954 /* Called with USB lock held. */ 1955 void 1956 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1957 { 1958 1959 KASSERT(mutex_owned(&sc->sc_lock)); 1960 1961 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1962 sitd, (u_long)sitd->physaddr)); 1963 1964 LIST_REMOVE(sitd, hnext); 1965 } 1966 1967 ohci_soft_itd_t * 1968 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1969 { 1970 int h = HASH(a); 1971 ohci_soft_itd_t *sitd; 1972 1973 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1974 sitd != NULL; 1975 sitd = LIST_NEXT(sitd, hnext)) 1976 if (sitd->physaddr == a) 1977 return (sitd); 1978 return (NULL); 1979 } 1980 1981 void 1982 ohci_timeout(void *addr) 1983 { 1984 struct ohci_xfer *oxfer = addr; 1985 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1986 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1987 1988 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1989 1990 if (sc->sc_dying) { 1991 mutex_enter(&sc->sc_lock); 1992 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1993 mutex_exit(&sc->sc_lock); 1994 return; 1995 } 1996 1997 /* Execute the abort in a process context. */ 1998 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1999 USB_TASKQ_MPSAFE); 2000 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2001 USB_TASKQ_HC); 2002 } 2003 2004 void 2005 ohci_timeout_task(void *addr) 2006 { 2007 usbd_xfer_handle xfer = addr; 2008 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2009 2010 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2011 2012 mutex_enter(&sc->sc_lock); 2013 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2014 mutex_exit(&sc->sc_lock); 2015 } 2016 2017 #ifdef OHCI_DEBUG 2018 void 2019 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2020 { 2021 for (; std; std = std->nexttd) 2022 ohci_dump_td(sc, std); 2023 } 2024 2025 void 2026 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2027 { 2028 char sbuf[128]; 2029 2030 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2031 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2032 snprintb(sbuf, sizeof(sbuf), 2033 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2034 (u_int32_t)O32TOH(std->td.td_flags)); 2035 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2036 "nexttd=0x%08lx be=0x%08lx\n", 2037 std, (u_long)std->physaddr, sbuf, 2038 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2039 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2040 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2041 (u_long)O32TOH(std->td.td_cbp), 2042 (u_long)O32TOH(std->td.td_nexttd), 2043 (u_long)O32TOH(std->td.td_be)); 2044 } 2045 2046 void 2047 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2048 { 2049 int i; 2050 2051 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2052 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2053 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2054 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2055 sitd, (u_long)sitd->physaddr, 2056 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2057 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2058 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2059 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2060 (u_long)O32TOH(sitd->itd.itd_bp0), 2061 (u_long)O32TOH(sitd->itd.itd_nextitd), 2062 (u_long)O32TOH(sitd->itd.itd_be)); 2063 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2064 printf("offs[%d]=0x%04x ", i, 2065 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2066 printf("\n"); 2067 } 2068 2069 void 2070 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2071 { 2072 for (; sitd; sitd = sitd->nextitd) 2073 ohci_dump_itd(sc, sitd); 2074 } 2075 2076 void 2077 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2078 { 2079 char sbuf[128], sbuf2[128]; 2080 2081 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2082 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2083 snprintb(sbuf, sizeof(sbuf), 2084 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2085 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2086 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2087 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2088 2089 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2090 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2091 sed, (u_long)sed->physaddr, 2092 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2093 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2094 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2095 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2096 (u_long)O32TOH(sed->ed.ed_headp), 2097 (u_long)O32TOH(sed->ed.ed_nexted)); 2098 } 2099 #endif 2100 2101 usbd_status 2102 ohci_open(usbd_pipe_handle pipe) 2103 { 2104 usbd_device_handle dev = pipe->device; 2105 ohci_softc_t *sc = dev->bus->hci_private; 2106 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2107 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2108 u_int8_t addr = dev->address; 2109 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2110 ohci_soft_ed_t *sed; 2111 ohci_soft_td_t *std; 2112 ohci_soft_itd_t *sitd; 2113 ohci_physaddr_t tdphys; 2114 u_int32_t fmt; 2115 usbd_status err = USBD_NOMEM; 2116 int ival; 2117 2118 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2119 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2120 2121 if (sc->sc_dying) { 2122 err = USBD_IOERROR; 2123 goto bad0; 2124 } 2125 2126 std = NULL; 2127 sed = NULL; 2128 2129 if (addr == sc->sc_addr) { 2130 switch (ed->bEndpointAddress) { 2131 case USB_CONTROL_ENDPOINT: 2132 pipe->methods = &ohci_root_ctrl_methods; 2133 break; 2134 case UE_DIR_IN | OHCI_INTR_ENDPT: 2135 pipe->methods = &ohci_root_intr_methods; 2136 break; 2137 default: 2138 err = USBD_INVAL; 2139 goto bad0; 2140 } 2141 } else { 2142 sed = ohci_alloc_sed(sc); 2143 if (sed == NULL) 2144 goto bad0; 2145 opipe->sed = sed; 2146 if (xfertype == UE_ISOCHRONOUS) { 2147 mutex_enter(&sc->sc_lock); 2148 sitd = ohci_alloc_sitd(sc); 2149 mutex_exit(&sc->sc_lock); 2150 if (sitd == NULL) 2151 goto bad1; 2152 opipe->tail.itd = sitd; 2153 tdphys = sitd->physaddr; 2154 fmt = OHCI_ED_FORMAT_ISO; 2155 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2156 fmt |= OHCI_ED_DIR_IN; 2157 else 2158 fmt |= OHCI_ED_DIR_OUT; 2159 } else { 2160 mutex_enter(&sc->sc_lock); 2161 std = ohci_alloc_std(sc); 2162 mutex_exit(&sc->sc_lock); 2163 if (std == NULL) 2164 goto bad1; 2165 opipe->tail.td = std; 2166 tdphys = std->physaddr; 2167 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2168 } 2169 sed->ed.ed_flags = HTOO32( 2170 OHCI_ED_SET_FA(addr) | 2171 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2172 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2173 fmt | 2174 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2175 sed->ed.ed_headp = HTOO32(tdphys | 2176 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2177 sed->ed.ed_tailp = HTOO32(tdphys); 2178 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2180 2181 switch (xfertype) { 2182 case UE_CONTROL: 2183 pipe->methods = &ohci_device_ctrl_methods; 2184 err = usb_allocmem(&sc->sc_bus, 2185 sizeof(usb_device_request_t), 2186 0, &opipe->u.ctl.reqdma); 2187 if (err) 2188 goto bad; 2189 mutex_enter(&sc->sc_lock); 2190 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2191 mutex_exit(&sc->sc_lock); 2192 break; 2193 case UE_INTERRUPT: 2194 pipe->methods = &ohci_device_intr_methods; 2195 ival = pipe->interval; 2196 if (ival == USBD_DEFAULT_INTERVAL) 2197 ival = ed->bInterval; 2198 err = ohci_device_setintr(sc, opipe, ival); 2199 if (err) 2200 goto bad; 2201 break; 2202 case UE_ISOCHRONOUS: 2203 pipe->methods = &ohci_device_isoc_methods; 2204 return (ohci_setup_isoc(pipe)); 2205 case UE_BULK: 2206 pipe->methods = &ohci_device_bulk_methods; 2207 mutex_enter(&sc->sc_lock); 2208 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2209 mutex_exit(&sc->sc_lock); 2210 break; 2211 } 2212 } 2213 2214 return USBD_NORMAL_COMPLETION; 2215 2216 bad: 2217 if (std != NULL) 2218 ohci_free_std(sc, std); 2219 bad1: 2220 if (sed != NULL) 2221 ohci_free_sed(sc, sed); 2222 bad0: 2223 return err; 2224 2225 } 2226 2227 /* 2228 * Close a reqular pipe. 2229 * Assumes that there are no pending transactions. 2230 */ 2231 void 2232 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2233 { 2234 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2235 ohci_softc_t *sc = pipe->device->bus->hci_private; 2236 ohci_soft_ed_t *sed = opipe->sed; 2237 2238 KASSERT(mutex_owned(&sc->sc_lock)); 2239 2240 #ifdef DIAGNOSTIC 2241 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2242 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2243 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2244 ohci_soft_td_t *std; 2245 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2246 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2247 "tl=0x%x pipe=%p, std=%p\n", sed, 2248 (int)O32TOH(sed->ed.ed_headp), 2249 (int)O32TOH(sed->ed.ed_tailp), 2250 pipe, std); 2251 #ifdef OHCI_DEBUG 2252 usbd_dump_pipe(&opipe->pipe); 2253 ohci_dump_ed(sc, sed); 2254 if (std) 2255 ohci_dump_td(sc, std); 2256 #endif 2257 usb_delay_ms(&sc->sc_bus, 2); 2258 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2259 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2260 printf("ohci_close_pipe: pipe still not empty\n"); 2261 } 2262 #endif 2263 ohci_rem_ed(sc, sed, head); 2264 /* Make sure the host controller is not touching this ED */ 2265 usb_delay_ms(&sc->sc_bus, 1); 2266 pipe->endpoint->datatoggle = 2267 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2268 ohci_free_sed(sc, opipe->sed); 2269 } 2270 2271 /* 2272 * Abort a device request. 2273 * If this routine is called at splusb() it guarantees that the request 2274 * will be removed from the hardware scheduling and that the callback 2275 * for it will be called with USBD_CANCELLED status. 2276 * It's impossible to guarantee that the requested transfer will not 2277 * have happened since the hardware runs concurrently. 2278 * If the transaction has already happened we rely on the ordinary 2279 * interrupt processing to process it. 2280 * XXX This is most probably wrong. 2281 * XXXMRG this doesn't make sense anymore. 2282 */ 2283 void 2284 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2285 { 2286 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2287 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2288 ohci_soft_ed_t *sed = opipe->sed; 2289 ohci_soft_td_t *p, *n; 2290 ohci_physaddr_t headp; 2291 int hit; 2292 int wake; 2293 2294 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2295 2296 KASSERT(mutex_owned(&sc->sc_lock)); 2297 2298 if (sc->sc_dying) { 2299 /* If we're dying, just do the software part. */ 2300 xfer->status = status; /* make software ignore it */ 2301 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2302 usb_transfer_complete(xfer); 2303 return; 2304 } 2305 2306 if (cpu_intr_p() || cpu_softintr_p()) 2307 panic("ohci_abort_xfer: not in process context"); 2308 2309 /* 2310 * If an abort is already in progress then just wait for it to 2311 * complete and return. 2312 */ 2313 if (xfer->hcflags & UXFER_ABORTING) { 2314 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2315 #ifdef DIAGNOSTIC 2316 if (status == USBD_TIMEOUT) 2317 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2318 #endif 2319 /* Override the status which might be USBD_TIMEOUT. */ 2320 xfer->status = status; 2321 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2322 xfer->hcflags |= UXFER_ABORTWAIT; 2323 while (xfer->hcflags & UXFER_ABORTING) 2324 cv_wait(&xfer->hccv, &sc->sc_lock); 2325 goto done; 2326 return; 2327 } 2328 xfer->hcflags |= UXFER_ABORTING; 2329 2330 /* 2331 * Step 1: Make interrupt routine and hardware ignore xfer. 2332 */ 2333 xfer->status = status; /* make software ignore it */ 2334 callout_stop(&xfer->timeout_handle); 2335 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2336 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2337 sizeof(sed->ed.ed_flags), 2338 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2339 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2340 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2341 sizeof(sed->ed.ed_flags), 2342 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2343 2344 /* 2345 * Step 2: Wait until we know hardware has finished any possible 2346 * use of the xfer. Also make sure the soft interrupt routine 2347 * has run. 2348 */ 2349 /* Hardware finishes in 1ms */ 2350 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2351 sc->sc_softwake = 1; 2352 usb_schedsoftintr(&sc->sc_bus); 2353 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2354 2355 /* 2356 * Step 3: Remove any vestiges of the xfer from the hardware. 2357 * The complication here is that the hardware may have executed 2358 * beyond the xfer we're trying to abort. So as we're scanning 2359 * the TDs of this xfer we check if the hardware points to 2360 * any of them. 2361 */ 2362 p = xfer->hcpriv; 2363 #ifdef DIAGNOSTIC 2364 if (p == NULL) { 2365 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2366 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2367 goto done; 2368 } 2369 #endif 2370 #ifdef OHCI_DEBUG 2371 if (ohcidebug > 1) { 2372 DPRINTF(("ohci_abort_xfer: sed=\n")); 2373 ohci_dump_ed(sc, sed); 2374 ohci_dump_tds(sc, p); 2375 } 2376 #endif 2377 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2378 hit = 0; 2379 for (; p->xfer == xfer; p = n) { 2380 hit |= headp == p->physaddr; 2381 n = p->nexttd; 2382 ohci_free_std(sc, p); 2383 } 2384 /* Zap headp register if hardware pointed inside the xfer. */ 2385 if (hit) { 2386 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2387 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2388 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2389 usb_syncmem(&sed->dma, 2390 sed->offs + offsetof(ohci_ed_t, ed_headp), 2391 sizeof(sed->ed.ed_headp), 2392 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2393 } else { 2394 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2395 } 2396 2397 /* 2398 * Step 4: Turn on hardware again. 2399 */ 2400 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2401 sizeof(sed->ed.ed_flags), 2402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2403 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2404 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2405 sizeof(sed->ed.ed_flags), 2406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2407 2408 /* 2409 * Step 5: Execute callback. 2410 */ 2411 wake = xfer->hcflags & UXFER_ABORTWAIT; 2412 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2413 usb_transfer_complete(xfer); 2414 if (wake) 2415 cv_broadcast(&xfer->hccv); 2416 2417 done: 2418 KASSERT(mutex_owned(&sc->sc_lock)); 2419 } 2420 2421 /* 2422 * Data structures and routines to emulate the root hub. 2423 */ 2424 Static usb_device_descriptor_t ohci_devd = { 2425 USB_DEVICE_DESCRIPTOR_SIZE, 2426 UDESC_DEVICE, /* type */ 2427 {0x00, 0x01}, /* USB version */ 2428 UDCLASS_HUB, /* class */ 2429 UDSUBCLASS_HUB, /* subclass */ 2430 UDPROTO_FSHUB, /* protocol */ 2431 64, /* max packet */ 2432 {0},{0},{0x00,0x01}, /* device id */ 2433 1,2,0, /* string indicies */ 2434 1 /* # of configurations */ 2435 }; 2436 2437 Static const usb_config_descriptor_t ohci_confd = { 2438 USB_CONFIG_DESCRIPTOR_SIZE, 2439 UDESC_CONFIG, 2440 {USB_CONFIG_DESCRIPTOR_SIZE + 2441 USB_INTERFACE_DESCRIPTOR_SIZE + 2442 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2443 1, 2444 1, 2445 0, 2446 UC_ATTR_MBO | UC_SELF_POWERED, 2447 0 /* max power */ 2448 }; 2449 2450 Static const usb_interface_descriptor_t ohci_ifcd = { 2451 USB_INTERFACE_DESCRIPTOR_SIZE, 2452 UDESC_INTERFACE, 2453 0, 2454 0, 2455 1, 2456 UICLASS_HUB, 2457 UISUBCLASS_HUB, 2458 UIPROTO_FSHUB, 2459 0 2460 }; 2461 2462 Static const usb_endpoint_descriptor_t ohci_endpd = { 2463 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2464 .bDescriptorType = UDESC_ENDPOINT, 2465 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2466 .bmAttributes = UE_INTERRUPT, 2467 .wMaxPacketSize = {8, 0}, /* max packet */ 2468 .bInterval = 255, 2469 }; 2470 2471 Static const usb_hub_descriptor_t ohci_hubd = { 2472 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2473 .bDescriptorType = UDESC_HUB, 2474 }; 2475 2476 /* 2477 * Simulate a hardware hub by handling all the necessary requests. 2478 */ 2479 Static usbd_status 2480 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2481 { 2482 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2483 usbd_status err; 2484 2485 /* Insert last in queue. */ 2486 mutex_enter(&sc->sc_lock); 2487 err = usb_insert_transfer(xfer); 2488 mutex_exit(&sc->sc_lock); 2489 if (err) 2490 return (err); 2491 2492 /* Pipe isn't running, start first */ 2493 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2494 } 2495 2496 Static usbd_status 2497 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2498 { 2499 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2500 usb_device_request_t *req; 2501 void *buf = NULL; 2502 int port, i; 2503 int len, value, index, l, totlen = 0; 2504 usb_port_status_t ps; 2505 usb_hub_descriptor_t hubd; 2506 usbd_status err; 2507 u_int32_t v; 2508 2509 if (sc->sc_dying) 2510 return (USBD_IOERROR); 2511 2512 #ifdef DIAGNOSTIC 2513 if (!(xfer->rqflags & URQ_REQUEST)) 2514 /* XXX panic */ 2515 return (USBD_INVAL); 2516 #endif 2517 req = &xfer->request; 2518 2519 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2520 req->bmRequestType, req->bRequest)); 2521 2522 len = UGETW(req->wLength); 2523 value = UGETW(req->wValue); 2524 index = UGETW(req->wIndex); 2525 2526 if (len != 0) 2527 buf = KERNADDR(&xfer->dmabuf, 0); 2528 2529 #define C(x,y) ((x) | ((y) << 8)) 2530 switch(C(req->bRequest, req->bmRequestType)) { 2531 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2532 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2533 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2534 /* 2535 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2536 * for the integrated root hub. 2537 */ 2538 break; 2539 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2540 if (len > 0) { 2541 *(u_int8_t *)buf = sc->sc_conf; 2542 totlen = 1; 2543 } 2544 break; 2545 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2546 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2547 if (len == 0) 2548 break; 2549 switch(value >> 8) { 2550 case UDESC_DEVICE: 2551 if ((value & 0xff) != 0) { 2552 err = USBD_IOERROR; 2553 goto ret; 2554 } 2555 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2556 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2557 memcpy(buf, &ohci_devd, l); 2558 break; 2559 case UDESC_CONFIG: 2560 if ((value & 0xff) != 0) { 2561 err = USBD_IOERROR; 2562 goto ret; 2563 } 2564 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2565 memcpy(buf, &ohci_confd, l); 2566 buf = (char *)buf + l; 2567 len -= l; 2568 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2569 totlen += l; 2570 memcpy(buf, &ohci_ifcd, l); 2571 buf = (char *)buf + l; 2572 len -= l; 2573 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2574 totlen += l; 2575 memcpy(buf, &ohci_endpd, l); 2576 break; 2577 case UDESC_STRING: 2578 #define sd ((usb_string_descriptor_t *)buf) 2579 switch (value & 0xff) { 2580 case 0: /* Language table */ 2581 totlen = usb_makelangtbl(sd, len); 2582 break; 2583 case 1: /* Vendor */ 2584 totlen = usb_makestrdesc(sd, len, 2585 sc->sc_vendor); 2586 break; 2587 case 2: /* Product */ 2588 totlen = usb_makestrdesc(sd, len, 2589 "OHCI root hub"); 2590 break; 2591 } 2592 #undef sd 2593 break; 2594 default: 2595 err = USBD_IOERROR; 2596 goto ret; 2597 } 2598 break; 2599 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2600 if (len > 0) { 2601 *(u_int8_t *)buf = 0; 2602 totlen = 1; 2603 } 2604 break; 2605 case C(UR_GET_STATUS, UT_READ_DEVICE): 2606 if (len > 1) { 2607 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2608 totlen = 2; 2609 } 2610 break; 2611 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2612 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2613 if (len > 1) { 2614 USETW(((usb_status_t *)buf)->wStatus, 0); 2615 totlen = 2; 2616 } 2617 break; 2618 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2619 if (value >= USB_MAX_DEVICES) { 2620 err = USBD_IOERROR; 2621 goto ret; 2622 } 2623 sc->sc_addr = value; 2624 break; 2625 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2626 if (value != 0 && value != 1) { 2627 err = USBD_IOERROR; 2628 goto ret; 2629 } 2630 sc->sc_conf = value; 2631 break; 2632 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2633 break; 2634 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2635 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2636 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2637 err = USBD_IOERROR; 2638 goto ret; 2639 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2640 break; 2641 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2642 break; 2643 /* Hub requests */ 2644 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2645 break; 2646 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2647 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2648 "port=%d feature=%d\n", 2649 index, value)); 2650 if (index < 1 || index > sc->sc_noport) { 2651 err = USBD_IOERROR; 2652 goto ret; 2653 } 2654 port = OHCI_RH_PORT_STATUS(index); 2655 switch(value) { 2656 case UHF_PORT_ENABLE: 2657 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2658 break; 2659 case UHF_PORT_SUSPEND: 2660 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2661 break; 2662 case UHF_PORT_POWER: 2663 /* Yes, writing to the LOW_SPEED bit clears power. */ 2664 OWRITE4(sc, port, UPS_LOW_SPEED); 2665 break; 2666 case UHF_C_PORT_CONNECTION: 2667 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2668 break; 2669 case UHF_C_PORT_ENABLE: 2670 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2671 break; 2672 case UHF_C_PORT_SUSPEND: 2673 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2674 break; 2675 case UHF_C_PORT_OVER_CURRENT: 2676 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2677 break; 2678 case UHF_C_PORT_RESET: 2679 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2680 break; 2681 default: 2682 err = USBD_IOERROR; 2683 goto ret; 2684 } 2685 switch(value) { 2686 case UHF_C_PORT_CONNECTION: 2687 case UHF_C_PORT_ENABLE: 2688 case UHF_C_PORT_SUSPEND: 2689 case UHF_C_PORT_OVER_CURRENT: 2690 case UHF_C_PORT_RESET: 2691 /* Enable RHSC interrupt if condition is cleared. */ 2692 if ((OREAD4(sc, port) >> 16) == 0) 2693 ohci_rhsc_enable(sc); 2694 break; 2695 default: 2696 break; 2697 } 2698 break; 2699 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2700 if (len == 0) 2701 break; 2702 if ((value & 0xff) != 0) { 2703 err = USBD_IOERROR; 2704 goto ret; 2705 } 2706 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2707 hubd = ohci_hubd; 2708 hubd.bNbrPorts = sc->sc_noport; 2709 USETW(hubd.wHubCharacteristics, 2710 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2711 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2712 /* XXX overcurrent */ 2713 ); 2714 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2715 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2716 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2717 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2718 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2719 l = min(len, hubd.bDescLength); 2720 totlen = l; 2721 memcpy(buf, &hubd, l); 2722 break; 2723 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2724 if (len != 4) { 2725 err = USBD_IOERROR; 2726 goto ret; 2727 } 2728 memset(buf, 0, len); /* ? XXX */ 2729 totlen = len; 2730 break; 2731 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2732 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2733 index)); 2734 if (index < 1 || index > sc->sc_noport) { 2735 err = USBD_IOERROR; 2736 goto ret; 2737 } 2738 if (len != 4) { 2739 err = USBD_IOERROR; 2740 goto ret; 2741 } 2742 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2743 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2744 v)); 2745 USETW(ps.wPortStatus, v); 2746 USETW(ps.wPortChange, v >> 16); 2747 l = min(len, sizeof ps); 2748 memcpy(buf, &ps, l); 2749 totlen = l; 2750 break; 2751 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2752 err = USBD_IOERROR; 2753 goto ret; 2754 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2755 break; 2756 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2757 if (index < 1 || index > sc->sc_noport) { 2758 err = USBD_IOERROR; 2759 goto ret; 2760 } 2761 port = OHCI_RH_PORT_STATUS(index); 2762 switch(value) { 2763 case UHF_PORT_ENABLE: 2764 OWRITE4(sc, port, UPS_PORT_ENABLED); 2765 break; 2766 case UHF_PORT_SUSPEND: 2767 OWRITE4(sc, port, UPS_SUSPEND); 2768 break; 2769 case UHF_PORT_RESET: 2770 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2771 index)); 2772 OWRITE4(sc, port, UPS_RESET); 2773 for (i = 0; i < 5; i++) { 2774 usb_delay_ms(&sc->sc_bus, 2775 USB_PORT_ROOT_RESET_DELAY); 2776 if (sc->sc_dying) { 2777 err = USBD_IOERROR; 2778 goto ret; 2779 } 2780 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2781 break; 2782 } 2783 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2784 index, OREAD4(sc, port))); 2785 break; 2786 case UHF_PORT_POWER: 2787 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2788 "%d\n", index)); 2789 OWRITE4(sc, port, UPS_PORT_POWER); 2790 break; 2791 default: 2792 err = USBD_IOERROR; 2793 goto ret; 2794 } 2795 break; 2796 default: 2797 err = USBD_IOERROR; 2798 goto ret; 2799 } 2800 xfer->actlen = totlen; 2801 err = USBD_NORMAL_COMPLETION; 2802 ret: 2803 xfer->status = err; 2804 mutex_enter(&sc->sc_lock); 2805 usb_transfer_complete(xfer); 2806 mutex_exit(&sc->sc_lock); 2807 return (USBD_IN_PROGRESS); 2808 } 2809 2810 /* Abort a root control request. */ 2811 Static void 2812 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2813 { 2814 /* Nothing to do, all transfers are synchronous. */ 2815 } 2816 2817 /* Close the root pipe. */ 2818 Static void 2819 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2820 { 2821 DPRINTF(("ohci_root_ctrl_close\n")); 2822 /* Nothing to do. */ 2823 } 2824 2825 Static usbd_status 2826 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2827 { 2828 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2829 usbd_status err; 2830 2831 /* Insert last in queue. */ 2832 mutex_enter(&sc->sc_lock); 2833 err = usb_insert_transfer(xfer); 2834 mutex_exit(&sc->sc_lock); 2835 if (err) 2836 return (err); 2837 2838 /* Pipe isn't running, start first */ 2839 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2840 } 2841 2842 Static usbd_status 2843 ohci_root_intr_start(usbd_xfer_handle xfer) 2844 { 2845 usbd_pipe_handle pipe = xfer->pipe; 2846 ohci_softc_t *sc = pipe->device->bus->hci_private; 2847 2848 if (sc->sc_dying) 2849 return (USBD_IOERROR); 2850 2851 mutex_enter(&sc->sc_lock); 2852 KASSERT(sc->sc_intrxfer == NULL); 2853 sc->sc_intrxfer = xfer; 2854 mutex_exit(&sc->sc_lock); 2855 2856 return (USBD_IN_PROGRESS); 2857 } 2858 2859 /* Abort a root interrupt request. */ 2860 Static void 2861 ohci_root_intr_abort(usbd_xfer_handle xfer) 2862 { 2863 #ifdef DIAGNOSTIC 2864 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2865 #endif 2866 2867 KASSERT(mutex_owned(&sc->sc_lock)); 2868 2869 if (xfer->pipe->intrxfer == xfer) { 2870 DPRINTF(("ohci_root_intr_abort: remove\n")); 2871 xfer->pipe->intrxfer = NULL; 2872 } 2873 xfer->status = USBD_CANCELLED; 2874 usb_transfer_complete(xfer); 2875 } 2876 2877 /* Close the root pipe. */ 2878 Static void 2879 ohci_root_intr_close(usbd_pipe_handle pipe) 2880 { 2881 ohci_softc_t *sc = pipe->device->bus->hci_private; 2882 2883 KASSERT(mutex_owned(&sc->sc_lock)); 2884 2885 DPRINTF(("ohci_root_intr_close\n")); 2886 2887 sc->sc_intrxfer = NULL; 2888 } 2889 2890 /************************/ 2891 2892 Static usbd_status 2893 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2894 { 2895 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2896 usbd_status err; 2897 2898 /* Insert last in queue. */ 2899 mutex_enter(&sc->sc_lock); 2900 err = usb_insert_transfer(xfer); 2901 mutex_exit(&sc->sc_lock); 2902 if (err) 2903 return (err); 2904 2905 /* Pipe isn't running, start first */ 2906 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2907 } 2908 2909 Static usbd_status 2910 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2911 { 2912 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2913 usbd_status err; 2914 2915 if (sc->sc_dying) 2916 return (USBD_IOERROR); 2917 2918 #ifdef DIAGNOSTIC 2919 if (!(xfer->rqflags & URQ_REQUEST)) { 2920 /* XXX panic */ 2921 printf("ohci_device_ctrl_transfer: not a request\n"); 2922 return (USBD_INVAL); 2923 } 2924 #endif 2925 2926 mutex_enter(&sc->sc_lock); 2927 err = ohci_device_request(xfer); 2928 mutex_exit(&sc->sc_lock); 2929 if (err) 2930 return (err); 2931 2932 if (sc->sc_bus.use_polling) 2933 ohci_waitintr(sc, xfer); 2934 return (USBD_IN_PROGRESS); 2935 } 2936 2937 /* Abort a device control request. */ 2938 Static void 2939 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2940 { 2941 #ifdef DIAGNOSTIC 2942 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2943 #endif 2944 2945 KASSERT(mutex_owned(&sc->sc_lock)); 2946 2947 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2948 ohci_abort_xfer(xfer, USBD_CANCELLED); 2949 } 2950 2951 /* Close a device control pipe. */ 2952 Static void 2953 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2954 { 2955 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2956 ohci_softc_t *sc = pipe->device->bus->hci_private; 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2961 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2962 ohci_free_std(sc, opipe->tail.td); 2963 } 2964 2965 /************************/ 2966 2967 Static void 2968 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2969 { 2970 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2971 ohci_softc_t *sc = pipe->device->bus->hci_private; 2972 2973 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2974 } 2975 2976 Static void 2977 ohci_noop(usbd_pipe_handle pipe) 2978 { 2979 } 2980 2981 Static usbd_status 2982 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2983 { 2984 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2985 usbd_status err; 2986 2987 /* Insert last in queue. */ 2988 mutex_enter(&sc->sc_lock); 2989 err = usb_insert_transfer(xfer); 2990 mutex_exit(&sc->sc_lock); 2991 if (err) 2992 return (err); 2993 2994 /* Pipe isn't running, start first */ 2995 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2996 } 2997 2998 Static usbd_status 2999 ohci_device_bulk_start(usbd_xfer_handle xfer) 3000 { 3001 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3002 usbd_device_handle dev = opipe->pipe.device; 3003 ohci_softc_t *sc = dev->bus->hci_private; 3004 int addr = dev->address; 3005 ohci_soft_td_t *data, *tail, *tdp; 3006 ohci_soft_ed_t *sed; 3007 int len, isread, endpt; 3008 usbd_status err; 3009 3010 if (sc->sc_dying) 3011 return (USBD_IOERROR); 3012 3013 #ifdef DIAGNOSTIC 3014 if (xfer->rqflags & URQ_REQUEST) { 3015 /* XXX panic */ 3016 printf("ohci_device_bulk_start: a request\n"); 3017 return (USBD_INVAL); 3018 } 3019 #endif 3020 3021 mutex_enter(&sc->sc_lock); 3022 3023 len = xfer->length; 3024 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3025 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3026 sed = opipe->sed; 3027 3028 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3029 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3030 endpt)); 3031 3032 opipe->u.bulk.isread = isread; 3033 opipe->u.bulk.length = len; 3034 3035 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3037 /* Update device address */ 3038 sed->ed.ed_flags = HTOO32( 3039 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3040 OHCI_ED_SET_FA(addr)); 3041 3042 /* Allocate a chain of new TDs (including a new tail). */ 3043 data = opipe->tail.td; 3044 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3045 data, &tail); 3046 /* We want interrupt at the end of the transfer. */ 3047 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3048 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3049 tail->flags |= OHCI_CALL_DONE; 3050 tail = tail->nexttd; /* point at sentinel */ 3051 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3052 sizeof(tail->td.td_flags), 3053 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3054 if (err) { 3055 mutex_exit(&sc->sc_lock); 3056 return (err); 3057 } 3058 3059 tail->xfer = NULL; 3060 xfer->hcpriv = data; 3061 3062 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3063 "td_cbp=0x%08x td_be=0x%08x\n", 3064 (int)O32TOH(sed->ed.ed_flags), 3065 (int)O32TOH(data->td.td_flags), 3066 (int)O32TOH(data->td.td_cbp), 3067 (int)O32TOH(data->td.td_be))); 3068 3069 #ifdef OHCI_DEBUG 3070 if (ohcidebug > 5) { 3071 ohci_dump_ed(sc, sed); 3072 ohci_dump_tds(sc, data); 3073 } 3074 #endif 3075 3076 /* Insert ED in schedule */ 3077 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3078 tdp->xfer = xfer; 3079 } 3080 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3081 opipe->tail.td = tail; 3082 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3083 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3084 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3085 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3086 if (xfer->timeout && !sc->sc_bus.use_polling) { 3087 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3088 ohci_timeout, xfer); 3089 } 3090 mutex_exit(&sc->sc_lock); 3091 3092 #if 0 3093 /* This goes wrong if we are too slow. */ 3094 if (ohcidebug > 10) { 3095 delay(10000); 3096 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3097 OREAD4(sc, OHCI_COMMAND_STATUS))); 3098 ohci_dump_ed(sc, sed); 3099 ohci_dump_tds(sc, data); 3100 } 3101 #endif 3102 3103 return (USBD_IN_PROGRESS); 3104 } 3105 3106 Static void 3107 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3108 { 3109 #ifdef DIAGNOSTIC 3110 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3111 #endif 3112 3113 KASSERT(mutex_owned(&sc->sc_lock)); 3114 3115 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3116 ohci_abort_xfer(xfer, USBD_CANCELLED); 3117 } 3118 3119 /* 3120 * Close a device bulk pipe. 3121 */ 3122 Static void 3123 ohci_device_bulk_close(usbd_pipe_handle pipe) 3124 { 3125 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3126 ohci_softc_t *sc = pipe->device->bus->hci_private; 3127 3128 KASSERT(mutex_owned(&sc->sc_lock)); 3129 3130 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3131 ohci_close_pipe(pipe, sc->sc_bulk_head); 3132 ohci_free_std(sc, opipe->tail.td); 3133 } 3134 3135 /************************/ 3136 3137 Static usbd_status 3138 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3139 { 3140 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3141 usbd_status err; 3142 3143 /* Insert last in queue. */ 3144 mutex_enter(&sc->sc_lock); 3145 err = usb_insert_transfer(xfer); 3146 mutex_exit(&sc->sc_lock); 3147 if (err) 3148 return (err); 3149 3150 /* Pipe isn't running, start first */ 3151 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3152 } 3153 3154 Static usbd_status 3155 ohci_device_intr_start(usbd_xfer_handle xfer) 3156 { 3157 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3158 usbd_device_handle dev = opipe->pipe.device; 3159 ohci_softc_t *sc = dev->bus->hci_private; 3160 ohci_soft_ed_t *sed = opipe->sed; 3161 ohci_soft_td_t *data, *tail; 3162 int len, isread, endpt; 3163 3164 if (sc->sc_dying) 3165 return (USBD_IOERROR); 3166 3167 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3168 "flags=%d priv=%p\n", 3169 xfer, xfer->length, xfer->flags, xfer->priv)); 3170 3171 #ifdef DIAGNOSTIC 3172 if (xfer->rqflags & URQ_REQUEST) 3173 panic("ohci_device_intr_transfer: a request"); 3174 #endif 3175 3176 len = xfer->length; 3177 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3178 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3179 3180 data = opipe->tail.td; 3181 mutex_enter(&sc->sc_lock); 3182 tail = ohci_alloc_std(sc); 3183 mutex_exit(&sc->sc_lock); 3184 if (tail == NULL) 3185 return (USBD_NOMEM); 3186 tail->xfer = NULL; 3187 3188 data->td.td_flags = HTOO32( 3189 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3190 OHCI_TD_NOCC | 3191 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3192 if (xfer->flags & USBD_SHORT_XFER_OK) 3193 data->td.td_flags |= HTOO32(OHCI_TD_R); 3194 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3195 data->nexttd = tail; 3196 data->td.td_nexttd = HTOO32(tail->physaddr); 3197 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3198 data->len = len; 3199 data->xfer = xfer; 3200 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3201 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3202 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3203 xfer->hcpriv = data; 3204 3205 #ifdef OHCI_DEBUG 3206 if (ohcidebug > 5) { 3207 DPRINTF(("ohci_device_intr_transfer:\n")); 3208 ohci_dump_ed(sc, sed); 3209 ohci_dump_tds(sc, data); 3210 } 3211 #endif 3212 3213 /* Insert ED in schedule */ 3214 mutex_enter(&sc->sc_lock); 3215 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3216 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3217 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3218 opipe->tail.td = tail; 3219 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3220 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3222 3223 #if 0 3224 /* 3225 * This goes horribly wrong, printing thousands of descriptors, 3226 * because false references are followed due to the fact that the 3227 * TD is gone. 3228 */ 3229 if (ohcidebug > 5) { 3230 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3231 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3232 OREAD4(sc, OHCI_COMMAND_STATUS))); 3233 ohci_dump_ed(sc, sed); 3234 ohci_dump_tds(sc, data); 3235 } 3236 #endif 3237 mutex_exit(&sc->sc_lock); 3238 3239 return (USBD_IN_PROGRESS); 3240 } 3241 3242 /* Abort a device interrupt request. */ 3243 Static void 3244 ohci_device_intr_abort(usbd_xfer_handle xfer) 3245 { 3246 #ifdef DIAGNOSTIC 3247 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3248 #endif 3249 3250 KASSERT(mutex_owned(&sc->sc_lock)); 3251 3252 if (xfer->pipe->intrxfer == xfer) { 3253 DPRINTF(("ohci_device_intr_abort: remove\n")); 3254 xfer->pipe->intrxfer = NULL; 3255 } 3256 ohci_abort_xfer(xfer, USBD_CANCELLED); 3257 } 3258 3259 /* Close a device interrupt pipe. */ 3260 Static void 3261 ohci_device_intr_close(usbd_pipe_handle pipe) 3262 { 3263 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3264 ohci_softc_t *sc = pipe->device->bus->hci_private; 3265 int nslots = opipe->u.intr.nslots; 3266 int pos = opipe->u.intr.pos; 3267 int j; 3268 ohci_soft_ed_t *p, *sed = opipe->sed; 3269 3270 KASSERT(mutex_owned(&sc->sc_lock)); 3271 3272 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3273 pipe, nslots, pos)); 3274 usb_syncmem(&sed->dma, sed->offs, 3275 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3276 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3277 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3278 sizeof(sed->ed.ed_flags), 3279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3280 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3281 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3282 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3283 3284 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3285 continue; 3286 #ifdef DIAGNOSTIC 3287 if (p == NULL) 3288 panic("ohci_device_intr_close: ED not found"); 3289 #endif 3290 p->next = sed->next; 3291 p->ed.ed_nexted = sed->ed.ed_nexted; 3292 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3293 sizeof(p->ed.ed_nexted), 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 3296 for (j = 0; j < nslots; j++) 3297 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3298 3299 ohci_free_std(sc, opipe->tail.td); 3300 ohci_free_sed(sc, opipe->sed); 3301 } 3302 3303 Static usbd_status 3304 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3305 { 3306 int i, j, best; 3307 u_int npoll, slow, shigh, nslots; 3308 u_int bestbw, bw; 3309 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3310 3311 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3312 if (ival == 0) { 3313 printf("ohci_setintr: 0 interval\n"); 3314 return (USBD_INVAL); 3315 } 3316 3317 npoll = OHCI_NO_INTRS; 3318 while (npoll > ival) 3319 npoll /= 2; 3320 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3321 3322 /* 3323 * We now know which level in the tree the ED must go into. 3324 * Figure out which slot has most bandwidth left over. 3325 * Slots to examine: 3326 * npoll 3327 * 1 0 3328 * 2 1 2 3329 * 4 3 4 5 6 3330 * 8 7 8 9 10 11 12 13 14 3331 * N (N-1) .. (N-1+N-1) 3332 */ 3333 slow = npoll-1; 3334 shigh = slow + npoll; 3335 nslots = OHCI_NO_INTRS / npoll; 3336 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3337 bw = 0; 3338 for (j = 0; j < nslots; j++) 3339 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3340 if (bw < bestbw) { 3341 best = i; 3342 bestbw = bw; 3343 } 3344 } 3345 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3346 best, slow, shigh, bestbw)); 3347 3348 mutex_enter(&sc->sc_lock); 3349 hsed = sc->sc_eds[best]; 3350 sed->next = hsed->next; 3351 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3352 sizeof(hsed->ed.ed_flags), 3353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3354 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3355 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3356 sizeof(sed->ed.ed_flags), 3357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3358 hsed->next = sed; 3359 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3360 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3361 sizeof(hsed->ed.ed_flags), 3362 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3363 mutex_exit(&sc->sc_lock); 3364 3365 for (j = 0; j < nslots; j++) 3366 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3367 opipe->u.intr.nslots = nslots; 3368 opipe->u.intr.pos = best; 3369 3370 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3371 return (USBD_NORMAL_COMPLETION); 3372 } 3373 3374 /***********************/ 3375 3376 usbd_status 3377 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3378 { 3379 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3380 usbd_status err; 3381 3382 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3383 3384 /* Put it on our queue, */ 3385 mutex_enter(&sc->sc_lock); 3386 err = usb_insert_transfer(xfer); 3387 mutex_exit(&sc->sc_lock); 3388 3389 /* bail out on error, */ 3390 if (err && err != USBD_IN_PROGRESS) 3391 return (err); 3392 3393 /* XXX should check inuse here */ 3394 3395 /* insert into schedule, */ 3396 ohci_device_isoc_enter(xfer); 3397 3398 /* and start if the pipe wasn't running */ 3399 if (!err) 3400 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3401 3402 return (err); 3403 } 3404 3405 void 3406 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3407 { 3408 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3409 usbd_device_handle dev = opipe->pipe.device; 3410 ohci_softc_t *sc = dev->bus->hci_private; 3411 ohci_soft_ed_t *sed = opipe->sed; 3412 struct iso *iso = &opipe->u.iso; 3413 ohci_soft_itd_t *sitd, *nsitd; 3414 ohci_physaddr_t buf, offs, noffs, bp0; 3415 int i, ncur, nframes; 3416 3417 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3418 "nframes=%d\n", 3419 iso->inuse, iso->next, xfer, xfer->nframes)); 3420 3421 if (sc->sc_dying) 3422 return; 3423 3424 if (iso->next == -1) { 3425 /* Not in use yet, schedule it a few frames ahead. */ 3426 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3427 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3428 iso->next)); 3429 } 3430 3431 sitd = opipe->tail.itd; 3432 buf = DMAADDR(&xfer->dmabuf, 0); 3433 bp0 = OHCI_PAGE(buf); 3434 offs = OHCI_PAGE_OFFSET(buf); 3435 nframes = xfer->nframes; 3436 xfer->hcpriv = sitd; 3437 for (i = ncur = 0; i < nframes; i++, ncur++) { 3438 noffs = offs + xfer->frlengths[i]; 3439 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3440 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3441 3442 /* Allocate next ITD */ 3443 mutex_enter(&sc->sc_lock); 3444 nsitd = ohci_alloc_sitd(sc); 3445 mutex_exit(&sc->sc_lock); 3446 if (nsitd == NULL) { 3447 /* XXX what now? */ 3448 printf("%s: isoc TD alloc failed\n", 3449 device_xname(sc->sc_dev)); 3450 return; 3451 } 3452 3453 /* Fill current ITD */ 3454 sitd->itd.itd_flags = HTOO32( 3455 OHCI_ITD_NOCC | 3456 OHCI_ITD_SET_SF(iso->next) | 3457 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3458 OHCI_ITD_SET_FC(ncur)); 3459 sitd->itd.itd_bp0 = HTOO32(bp0); 3460 sitd->nextitd = nsitd; 3461 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3462 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3463 sitd->xfer = xfer; 3464 sitd->flags = 0; 3465 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3467 3468 sitd = nsitd; 3469 iso->next = iso->next + ncur; 3470 bp0 = OHCI_PAGE(buf + offs); 3471 ncur = 0; 3472 } 3473 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3474 offs = noffs; 3475 } 3476 mutex_enter(&sc->sc_lock); 3477 nsitd = ohci_alloc_sitd(sc); 3478 mutex_exit(&sc->sc_lock); 3479 if (nsitd == NULL) { 3480 /* XXX what now? */ 3481 printf("%s: isoc TD alloc failed\n", 3482 device_xname(sc->sc_dev)); 3483 return; 3484 } 3485 /* Fixup last used ITD */ 3486 sitd->itd.itd_flags = HTOO32( 3487 OHCI_ITD_NOCC | 3488 OHCI_ITD_SET_SF(iso->next) | 3489 OHCI_ITD_SET_DI(0) | 3490 OHCI_ITD_SET_FC(ncur)); 3491 sitd->itd.itd_bp0 = HTOO32(bp0); 3492 sitd->nextitd = nsitd; 3493 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3494 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3495 sitd->xfer = xfer; 3496 sitd->flags = OHCI_CALL_DONE; 3497 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3498 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3499 3500 iso->next = iso->next + ncur; 3501 iso->inuse += nframes; 3502 3503 xfer->actlen = offs; /* XXX pretend we did it all */ 3504 3505 xfer->status = USBD_IN_PROGRESS; 3506 3507 #ifdef OHCI_DEBUG 3508 if (ohcidebug > 5) { 3509 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3510 O32TOH(sc->sc_hcca->hcca_frame_number))); 3511 ohci_dump_itds(sc, xfer->hcpriv); 3512 ohci_dump_ed(sc, sed); 3513 } 3514 #endif 3515 3516 mutex_enter(&sc->sc_lock); 3517 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3518 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3519 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3520 opipe->tail.itd = nsitd; 3521 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3522 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3523 sizeof(sed->ed.ed_flags), 3524 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3525 mutex_exit(&sc->sc_lock); 3526 3527 #ifdef OHCI_DEBUG 3528 if (ohcidebug > 5) { 3529 delay(150000); 3530 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3531 O32TOH(sc->sc_hcca->hcca_frame_number))); 3532 ohci_dump_itds(sc, xfer->hcpriv); 3533 ohci_dump_ed(sc, sed); 3534 } 3535 #endif 3536 } 3537 3538 usbd_status 3539 ohci_device_isoc_start(usbd_xfer_handle xfer) 3540 { 3541 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3542 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3543 3544 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3545 3546 mutex_enter(&sc->sc_lock); 3547 3548 if (sc->sc_dying) { 3549 mutex_exit(&sc->sc_lock); 3550 return (USBD_IOERROR); 3551 } 3552 3553 #ifdef DIAGNOSTIC 3554 if (xfer->status != USBD_IN_PROGRESS) 3555 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3556 #endif 3557 3558 /* XXX anything to do? */ 3559 3560 mutex_exit(&sc->sc_lock); 3561 3562 return (USBD_IN_PROGRESS); 3563 } 3564 3565 void 3566 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3567 { 3568 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3569 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3570 ohci_soft_ed_t *sed; 3571 ohci_soft_itd_t *sitd; 3572 3573 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3574 3575 KASSERT(mutex_owned(&sc->sc_lock)); 3576 3577 /* Transfer is already done. */ 3578 if (xfer->status != USBD_NOT_STARTED && 3579 xfer->status != USBD_IN_PROGRESS) { 3580 printf("ohci_device_isoc_abort: early return\n"); 3581 goto done; 3582 } 3583 3584 /* Give xfer the requested abort code. */ 3585 xfer->status = USBD_CANCELLED; 3586 3587 sed = opipe->sed; 3588 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3589 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3590 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3591 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3592 sizeof(sed->ed.ed_flags), 3593 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3594 3595 sitd = xfer->hcpriv; 3596 #ifdef DIAGNOSTIC 3597 if (sitd == NULL) { 3598 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3599 goto done; 3600 } 3601 #endif 3602 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3603 #ifdef DIAGNOSTIC 3604 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3605 sitd->isdone = 1; 3606 #endif 3607 } 3608 3609 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3610 3611 /* Run callback. */ 3612 usb_transfer_complete(xfer); 3613 3614 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3615 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3616 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3617 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3618 3619 done: 3620 KASSERT(mutex_owned(&sc->sc_lock)); 3621 } 3622 3623 void 3624 ohci_device_isoc_done(usbd_xfer_handle xfer) 3625 { 3626 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3627 } 3628 3629 usbd_status 3630 ohci_setup_isoc(usbd_pipe_handle pipe) 3631 { 3632 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3633 ohci_softc_t *sc = pipe->device->bus->hci_private; 3634 struct iso *iso = &opipe->u.iso; 3635 3636 iso->next = -1; 3637 iso->inuse = 0; 3638 3639 mutex_enter(&sc->sc_lock); 3640 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3641 mutex_exit(&sc->sc_lock); 3642 3643 return (USBD_NORMAL_COMPLETION); 3644 } 3645 3646 void 3647 ohci_device_isoc_close(usbd_pipe_handle pipe) 3648 { 3649 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3650 ohci_softc_t *sc = pipe->device->bus->hci_private; 3651 3652 KASSERT(mutex_owned(&sc->sc_lock)); 3653 3654 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3655 ohci_close_pipe(pipe, sc->sc_isoc_head); 3656 #ifdef DIAGNOSTIC 3657 opipe->tail.itd->isdone = 1; 3658 #endif 3659 ohci_free_sitd(sc, opipe->tail.itd); 3660 } 3661
Indexes created Fri Oct 03 02:09:57 GMT 2025