ohci.c revision 1.224.2.2
1 /* $NetBSD: ohci.c,v 1.224.2.2 2013/06/23 06:20:22 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.224.2.2 2013/06/23 06:20:22 tls Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 136 137 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 138 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 139 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 140 Static void ohci_root_ctrl_close(usbd_pipe_handle); 141 Static void ohci_root_ctrl_done(usbd_xfer_handle); 142 143 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 145 Static void ohci_root_intr_abort(usbd_xfer_handle); 146 Static void ohci_root_intr_close(usbd_pipe_handle); 147 Static void ohci_root_intr_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 151 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 152 Static void ohci_device_ctrl_close(usbd_pipe_handle); 153 Static void ohci_device_ctrl_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 157 Static void ohci_device_bulk_abort(usbd_xfer_handle); 158 Static void ohci_device_bulk_close(usbd_pipe_handle); 159 Static void ohci_device_bulk_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 163 Static void ohci_device_intr_abort(usbd_xfer_handle); 164 Static void ohci_device_intr_close(usbd_pipe_handle); 165 Static void ohci_device_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 169 Static void ohci_device_isoc_abort(usbd_xfer_handle); 170 Static void ohci_device_isoc_close(usbd_pipe_handle); 171 Static void ohci_device_isoc_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 174 struct ohci_pipe *pipe, int ival); 175 176 Static void ohci_timeout(void *); 177 Static void ohci_timeout_task(void *); 178 Static void ohci_rhsc_enable(void *); 179 180 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 181 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 182 183 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ohci_noop(usbd_pipe_handle pipe); 185 186 #ifdef OHCI_DEBUG 187 Static void ohci_dumpregs(ohci_softc_t *); 188 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 191 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 192 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 193 #endif 194 195 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 196 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 197 #define OWRITE1(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OWRITE2(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE4(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 static __inline uint8_t 204 OREAD1(ohci_softc_t *sc, bus_size_t r) 205 { 206 207 OBARR(sc); 208 return bus_space_read_1(sc->iot, sc->ioh, r); 209 } 210 211 static __inline uint16_t 212 OREAD2(ohci_softc_t *sc, bus_size_t r) 213 { 214 215 OBARR(sc); 216 return bus_space_read_2(sc->iot, sc->ioh, r); 217 } 218 219 static __inline uint32_t 220 OREAD4(ohci_softc_t *sc, bus_size_t r) 221 { 222 223 OBARR(sc); 224 return bus_space_read_4(sc->iot, sc->ioh, r); 225 } 226 227 /* Reverse the bits in a value 0 .. 31 */ 228 Static u_int8_t revbits[OHCI_NO_INTRS] = 229 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 230 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 231 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 232 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 233 234 struct ohci_pipe { 235 struct usbd_pipe pipe; 236 ohci_soft_ed_t *sed; 237 union { 238 ohci_soft_td_t *td; 239 ohci_soft_itd_t *itd; 240 } tail; 241 /* Info needed for different pipe kinds. */ 242 union { 243 /* Control pipe */ 244 struct { 245 usb_dma_t reqdma; 246 u_int length; 247 ohci_soft_td_t *setup, *data, *stat; 248 } ctl; 249 /* Interrupt pipe */ 250 struct { 251 int nslots; 252 int pos; 253 } intr; 254 /* Bulk pipe */ 255 struct { 256 u_int length; 257 int isread; 258 } bulk; 259 /* Iso pipe */ 260 struct iso { 261 int next, inuse; 262 } iso; 263 } u; 264 }; 265 266 #define OHCI_INTR_ENDPT 1 267 268 Static const struct usbd_bus_methods ohci_bus_methods = { 269 .open_pipe = ohci_open, 270 .soft_intr = ohci_softintr, 271 .do_poll = ohci_poll, 272 .allocm = ohci_allocm, 273 .freem = ohci_freem, 274 .allocx = ohci_allocx, 275 .freex = ohci_freex, 276 .get_lock = ohci_get_lock, 277 }; 278 279 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 280 .transfer = ohci_root_ctrl_transfer, 281 .start = ohci_root_ctrl_start, 282 .abort = ohci_root_ctrl_abort, 283 .close = ohci_root_ctrl_close, 284 .cleartoggle = ohci_noop, 285 .done = ohci_root_ctrl_done, 286 }; 287 288 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 289 .transfer = ohci_root_intr_transfer, 290 .start = ohci_root_intr_start, 291 .abort = ohci_root_intr_abort, 292 .close = ohci_root_intr_close, 293 .cleartoggle = ohci_noop, 294 .done = ohci_root_intr_done, 295 }; 296 297 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 298 .transfer = ohci_device_ctrl_transfer, 299 .start = ohci_device_ctrl_start, 300 .abort = ohci_device_ctrl_abort, 301 .close = ohci_device_ctrl_close, 302 .cleartoggle = ohci_noop, 303 .done = ohci_device_ctrl_done, 304 }; 305 306 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 307 .transfer = ohci_device_intr_transfer, 308 .start = ohci_device_intr_start, 309 .abort = ohci_device_intr_abort, 310 .close = ohci_device_intr_close, 311 .cleartoggle = ohci_device_clear_toggle, 312 .done = ohci_device_intr_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 316 .transfer = ohci_device_bulk_transfer, 317 .start = ohci_device_bulk_start, 318 .abort = ohci_device_bulk_abort, 319 .close = ohci_device_bulk_close, 320 .cleartoggle = ohci_device_clear_toggle, 321 .done = ohci_device_bulk_done, 322 }; 323 324 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 325 .transfer = ohci_device_isoc_transfer, 326 .start = ohci_device_isoc_start, 327 .abort = ohci_device_isoc_abort, 328 .close = ohci_device_isoc_close, 329 .cleartoggle = ohci_noop, 330 .done = ohci_device_isoc_done, 331 }; 332 333 int 334 ohci_activate(device_t self, enum devact act) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 switch (act) { 339 case DVACT_DEACTIVATE: 340 sc->sc_dying = 1; 341 return 0; 342 default: 343 return EOPNOTSUPP; 344 } 345 } 346 347 void 348 ohci_childdet(device_t self, device_t child) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 KASSERT(sc->sc_child == child); 353 sc->sc_child = NULL; 354 } 355 356 int 357 ohci_detach(struct ohci_softc *sc, int flags) 358 { 359 int rv = 0; 360 361 if (sc->sc_child != NULL) 362 rv = config_detach(sc->sc_child, flags); 363 364 if (rv != 0) 365 return (rv); 366 367 callout_stop(&sc->sc_tmo_rhsc); 368 369 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 370 callout_destroy(&sc->sc_tmo_rhsc); 371 372 softint_disestablish(sc->sc_rhsc_si); 373 374 cv_destroy(&sc->sc_softwake_cv); 375 376 mutex_destroy(&sc->sc_lock); 377 mutex_destroy(&sc->sc_intr_lock); 378 379 if (sc->sc_hcca != NULL) 380 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 381 pool_cache_destroy(sc->sc_xferpool); 382 383 return (rv); 384 } 385 386 ohci_soft_ed_t * 387 ohci_alloc_sed(ohci_softc_t *sc) 388 { 389 ohci_soft_ed_t *sed; 390 usbd_status err; 391 int i, offs; 392 usb_dma_t dma; 393 394 if (sc->sc_freeeds == NULL) { 395 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 396 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 397 OHCI_ED_ALIGN, &dma); 398 if (err) 399 return (0); 400 for (i = 0; i < OHCI_SED_CHUNK; i++) { 401 offs = i * OHCI_SED_SIZE; 402 sed = KERNADDR(&dma, offs); 403 sed->physaddr = DMAADDR(&dma, offs); 404 sed->dma = dma; 405 sed->offs = offs; 406 sed->next = sc->sc_freeeds; 407 sc->sc_freeeds = sed; 408 } 409 } 410 sed = sc->sc_freeeds; 411 sc->sc_freeeds = sed->next; 412 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 413 sed->next = 0; 414 return (sed); 415 } 416 417 void 418 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 419 { 420 sed->next = sc->sc_freeeds; 421 sc->sc_freeeds = sed; 422 } 423 424 ohci_soft_td_t * 425 ohci_alloc_std(ohci_softc_t *sc) 426 { 427 ohci_soft_td_t *std; 428 usbd_status err; 429 int i, offs; 430 usb_dma_t dma; 431 432 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 433 434 if (sc->sc_freetds == NULL) { 435 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 436 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 437 OHCI_TD_ALIGN, &dma); 438 if (err) 439 return (NULL); 440 for(i = 0; i < OHCI_STD_CHUNK; i++) { 441 offs = i * OHCI_STD_SIZE; 442 std = KERNADDR(&dma, offs); 443 std->physaddr = DMAADDR(&dma, offs); 444 std->dma = dma; 445 std->offs = offs; 446 std->nexttd = sc->sc_freetds; 447 sc->sc_freetds = std; 448 } 449 } 450 451 std = sc->sc_freetds; 452 sc->sc_freetds = std->nexttd; 453 memset(&std->td, 0, sizeof(ohci_td_t)); 454 std->nexttd = NULL; 455 std->xfer = NULL; 456 ohci_hash_add_td(sc, std); 457 458 return (std); 459 } 460 461 void 462 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 463 { 464 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 465 466 ohci_hash_rem_td(sc, std); 467 std->nexttd = sc->sc_freetds; 468 sc->sc_freetds = std; 469 } 470 471 usbd_status 472 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 473 int alen, int rd, usbd_xfer_handle xfer, 474 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 475 { 476 ohci_soft_td_t *next, *cur; 477 ohci_physaddr_t dataphys, dataphysend; 478 u_int32_t tdflags; 479 int len, curlen; 480 usb_dma_t *dma = &xfer->dmabuf; 481 u_int16_t flags = xfer->flags; 482 483 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 484 485 KASSERT(mutex_owned(&sc->sc_lock)); 486 487 len = alen; 488 cur = sp; 489 dataphys = DMAADDR(dma, 0); 490 dataphysend = OHCI_PAGE(dataphys + len - 1); 491 usb_syncmem(dma, 0, len, 492 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 493 tdflags = HTOO32( 494 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 495 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 496 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 497 498 for (;;) { 499 next = ohci_alloc_std(sc); 500 if (next == NULL) 501 goto nomem; 502 503 /* The OHCI hardware can handle at most one page crossing. */ 504 if (OHCI_PAGE(dataphys) == dataphysend || 505 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 506 /* we can handle it in this TD */ 507 curlen = len; 508 } else { 509 /* must use multiple TDs, fill as much as possible. */ 510 curlen = 2 * OHCI_PAGE_SIZE - 511 (dataphys & (OHCI_PAGE_SIZE-1)); 512 /* the length must be a multiple of the max size */ 513 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 514 #ifdef DIAGNOSTIC 515 if (curlen == 0) 516 panic("ohci_alloc_std: curlen == 0"); 517 #endif 518 } 519 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 520 "dataphysend=0x%08x len=%d curlen=%d\n", 521 dataphys, dataphysend, 522 len, curlen)); 523 len -= curlen; 524 525 cur->td.td_flags = tdflags; 526 cur->td.td_cbp = HTOO32(dataphys); 527 cur->nexttd = next; 528 cur->td.td_nexttd = HTOO32(next->physaddr); 529 cur->td.td_be = HTOO32(dataphys + curlen - 1); 530 cur->len = curlen; 531 cur->flags = OHCI_ADD_LEN; 532 cur->xfer = xfer; 533 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 535 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 536 dataphys, dataphys + curlen - 1)); 537 if (len == 0) 538 break; 539 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 540 dataphys += curlen; 541 cur = next; 542 } 543 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 544 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 545 /* Force a 0 length transfer at the end. */ 546 547 cur = next; 548 next = ohci_alloc_std(sc); 549 if (next == NULL) 550 goto nomem; 551 552 cur->td.td_flags = tdflags; 553 cur->td.td_cbp = 0; /* indicate 0 length packet */ 554 cur->nexttd = next; 555 cur->td.td_nexttd = HTOO32(next->physaddr); 556 cur->td.td_be = ~0; 557 cur->len = 0; 558 cur->flags = 0; 559 cur->xfer = xfer; 560 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 562 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 563 } 564 *ep = cur; 565 566 return (USBD_NORMAL_COMPLETION); 567 568 nomem: 569 570 /* Don't free sp - let the caller do that */ 571 ohci_free_std_chain(sc, sp->nexttd, NULL); 572 573 return (USBD_NOMEM); 574 } 575 576 Static void 577 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 578 ohci_soft_td_t *stdend) 579 { 580 ohci_soft_td_t *p; 581 582 for (; std != stdend; std = p) { 583 p = std->nexttd; 584 ohci_free_std(sc, std); 585 } 586 } 587 588 ohci_soft_itd_t * 589 ohci_alloc_sitd(ohci_softc_t *sc) 590 { 591 ohci_soft_itd_t *sitd; 592 usbd_status err; 593 int i, offs; 594 usb_dma_t dma; 595 596 if (sc->sc_freeitds == NULL) { 597 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 598 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 599 OHCI_ITD_ALIGN, &dma); 600 if (err) 601 return (NULL); 602 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 603 offs = i * OHCI_SITD_SIZE; 604 sitd = KERNADDR(&dma, offs); 605 sitd->physaddr = DMAADDR(&dma, offs); 606 sitd->dma = dma; 607 sitd->offs = offs; 608 sitd->nextitd = sc->sc_freeitds; 609 sc->sc_freeitds = sitd; 610 } 611 } 612 613 sitd = sc->sc_freeitds; 614 sc->sc_freeitds = sitd->nextitd; 615 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 616 sitd->nextitd = NULL; 617 sitd->xfer = NULL; 618 ohci_hash_add_itd(sc, sitd); 619 620 #ifdef DIAGNOSTIC 621 sitd->isdone = 0; 622 #endif 623 624 return (sitd); 625 } 626 627 void 628 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 629 { 630 631 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 632 633 #ifdef DIAGNOSTIC 634 if (!sitd->isdone) { 635 panic("ohci_free_sitd: sitd=%p not done", sitd); 636 return; 637 } 638 /* Warn double free */ 639 sitd->isdone = 0; 640 #endif 641 642 ohci_hash_rem_itd(sc, sitd); 643 sitd->nextitd = sc->sc_freeitds; 644 sc->sc_freeitds = sitd; 645 } 646 647 usbd_status 648 ohci_init(ohci_softc_t *sc) 649 { 650 ohci_soft_ed_t *sed, *psed; 651 usbd_status err; 652 int i; 653 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 654 655 DPRINTF(("ohci_init: start\n")); 656 aprint_normal_dev(sc->sc_dev, ""); 657 658 sc->sc_hcca = NULL; 659 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 660 661 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 662 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 663 cv_init(&sc->sc_softwake_cv, "ohciab"); 664 665 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 666 ohci_rhsc_softint, sc); 667 668 for (i = 0; i < OHCI_HASH_SIZE; i++) 669 LIST_INIT(&sc->sc_hash_tds[i]); 670 for (i = 0; i < OHCI_HASH_SIZE; i++) 671 LIST_INIT(&sc->sc_hash_itds[i]); 672 673 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 674 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 675 676 rev = OREAD4(sc, OHCI_REVISION); 677 aprint_normal("OHCI version %d.%d%s\n", 678 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 679 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 680 681 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 682 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 683 sc->sc_bus.usbrev = USBREV_UNKNOWN; 684 return (USBD_INVAL); 685 } 686 sc->sc_bus.usbrev = USBREV_1_0; 687 688 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 689 USB_MEM_RESERVE); 690 691 /* XXX determine alignment by R/W */ 692 /* Allocate the HCCA area. */ 693 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 694 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 695 if (err) { 696 sc->sc_hcca = NULL; 697 return err; 698 } 699 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 700 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 701 702 sc->sc_eintrs = OHCI_NORMAL_INTRS; 703 704 /* Allocate dummy ED that starts the control list. */ 705 sc->sc_ctrl_head = ohci_alloc_sed(sc); 706 if (sc->sc_ctrl_head == NULL) { 707 err = USBD_NOMEM; 708 goto bad1; 709 } 710 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 711 712 /* Allocate dummy ED that starts the bulk list. */ 713 sc->sc_bulk_head = ohci_alloc_sed(sc); 714 if (sc->sc_bulk_head == NULL) { 715 err = USBD_NOMEM; 716 goto bad2; 717 } 718 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 719 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 720 sizeof(sc->sc_bulk_head->ed), 721 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 722 723 /* Allocate dummy ED that starts the isochronous list. */ 724 sc->sc_isoc_head = ohci_alloc_sed(sc); 725 if (sc->sc_isoc_head == NULL) { 726 err = USBD_NOMEM; 727 goto bad3; 728 } 729 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 730 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 731 sizeof(sc->sc_isoc_head->ed), 732 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 733 734 /* Allocate all the dummy EDs that make up the interrupt tree. */ 735 for (i = 0; i < OHCI_NO_EDS; i++) { 736 sed = ohci_alloc_sed(sc); 737 if (sed == NULL) { 738 while (--i >= 0) 739 ohci_free_sed(sc, sc->sc_eds[i]); 740 err = USBD_NOMEM; 741 goto bad4; 742 } 743 /* All ED fields are set to 0. */ 744 sc->sc_eds[i] = sed; 745 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 746 if (i != 0) 747 psed = sc->sc_eds[(i-1) / 2]; 748 else 749 psed= sc->sc_isoc_head; 750 sed->next = psed; 751 sed->ed.ed_nexted = HTOO32(psed->physaddr); 752 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 753 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 754 } 755 /* 756 * Fill HCCA interrupt table. The bit reversal is to get 757 * the tree set up properly to spread the interrupts. 758 */ 759 for (i = 0; i < OHCI_NO_INTRS; i++) 760 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 761 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 762 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 763 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 764 765 #ifdef OHCI_DEBUG 766 if (ohcidebug > 15) { 767 for (i = 0; i < OHCI_NO_EDS; i++) { 768 printf("ed#%d ", i); 769 ohci_dump_ed(sc, sc->sc_eds[i]); 770 } 771 printf("iso "); 772 ohci_dump_ed(sc, sc->sc_isoc_head); 773 } 774 #endif 775 776 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 777 ctl = OREAD4(sc, OHCI_CONTROL); 778 rwc = ctl & OHCI_RWC; 779 fm = OREAD4(sc, OHCI_FM_INTERVAL); 780 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 781 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 782 783 /* Determine in what context we are running. */ 784 if (ctl & OHCI_IR) { 785 /* SMM active, request change */ 786 DPRINTF(("ohci_init: SMM active, request owner change\n")); 787 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 788 (OHCI_OC | OHCI_MIE)) 789 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 790 s = OREAD4(sc, OHCI_COMMAND_STATUS); 791 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 792 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 793 usb_delay_ms(&sc->sc_bus, 1); 794 ctl = OREAD4(sc, OHCI_CONTROL); 795 } 796 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 797 if ((ctl & OHCI_IR) == 0) { 798 aprint_error_dev(sc->sc_dev, 799 "SMM does not respond, resetting\n"); 800 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 801 goto reset; 802 } 803 #if 0 804 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 805 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 806 /* BIOS started controller. */ 807 DPRINTF(("ohci_init: BIOS active\n")); 808 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 809 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 810 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 811 } 812 #endif 813 } else { 814 DPRINTF(("ohci_init: cold started\n")); 815 reset: 816 /* Controller was cold started. */ 817 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 818 } 819 820 /* 821 * This reset should not be necessary according to the OHCI spec, but 822 * without it some controllers do not start. 823 */ 824 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 825 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 826 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 827 828 /* We now own the host controller and the bus has been reset. */ 829 830 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 831 /* Nominal time for a reset is 10 us. */ 832 for (i = 0; i < 10; i++) { 833 delay(10); 834 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 835 if (!hcr) 836 break; 837 } 838 if (hcr) { 839 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 840 err = USBD_IOERROR; 841 goto bad5; 842 } 843 #ifdef OHCI_DEBUG 844 if (ohcidebug > 15) 845 ohci_dumpregs(sc); 846 #endif 847 848 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 849 850 /* Set up HC registers. */ 851 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 852 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 853 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 854 /* disable all interrupts and then switch on all desired interrupts */ 855 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 856 /* switch on desired functional features */ 857 ctl = OREAD4(sc, OHCI_CONTROL); 858 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 859 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 860 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 861 /* And finally start it! */ 862 OWRITE4(sc, OHCI_CONTROL, ctl); 863 864 /* 865 * The controller is now OPERATIONAL. Set a some final 866 * registers that should be set earlier, but that the 867 * controller ignores when in the SUSPEND state. 868 */ 869 ival = OHCI_GET_IVAL(fm); 870 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 871 fm |= OHCI_FSMPS(ival) | ival; 872 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 873 per = OHCI_PERIODIC(ival); /* 90% periodic */ 874 OWRITE4(sc, OHCI_PERIODIC_START, per); 875 876 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 877 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 878 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 879 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 880 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 881 882 /* 883 * The AMD756 requires a delay before re-reading the register, 884 * otherwise it will occasionally report 0 ports. 885 */ 886 sc->sc_noport = 0; 887 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 888 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 889 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 890 } 891 892 #ifdef OHCI_DEBUG 893 if (ohcidebug > 5) 894 ohci_dumpregs(sc); 895 #endif 896 897 /* Set up the bus struct. */ 898 sc->sc_bus.methods = &ohci_bus_methods; 899 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 900 901 sc->sc_control = sc->sc_intre = 0; 902 903 /* Finally, turn on interrupts. */ 904 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 905 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 906 907 return (USBD_NORMAL_COMPLETION); 908 909 bad5: 910 for (i = 0; i < OHCI_NO_EDS; i++) 911 ohci_free_sed(sc, sc->sc_eds[i]); 912 bad4: 913 ohci_free_sed(sc, sc->sc_isoc_head); 914 bad3: 915 ohci_free_sed(sc, sc->sc_bulk_head); 916 bad2: 917 ohci_free_sed(sc, sc->sc_ctrl_head); 918 bad1: 919 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 920 sc->sc_hcca = NULL; 921 return (err); 922 } 923 924 usbd_status 925 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 926 { 927 struct ohci_softc *sc = bus->hci_private; 928 usbd_status status; 929 930 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 931 if (status == USBD_NOMEM) 932 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 933 return status; 934 } 935 936 void 937 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 938 { 939 struct ohci_softc *sc = bus->hci_private; 940 if (dma->block->flags & USB_DMA_RESERVE) { 941 usb_reserve_freem(&sc->sc_dma_reserve, dma); 942 return; 943 } 944 usb_freemem(&sc->sc_bus, dma); 945 } 946 947 usbd_xfer_handle 948 ohci_allocx(struct usbd_bus *bus) 949 { 950 struct ohci_softc *sc = bus->hci_private; 951 usbd_xfer_handle xfer; 952 953 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 954 if (xfer != NULL) { 955 memset(xfer, 0, sizeof(struct ohci_xfer)); 956 #ifdef DIAGNOSTIC 957 xfer->busy_free = XFER_BUSY; 958 #endif 959 } 960 return (xfer); 961 } 962 963 void 964 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 965 { 966 struct ohci_softc *sc = bus->hci_private; 967 968 #ifdef DIAGNOSTIC 969 if (xfer->busy_free != XFER_BUSY) { 970 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 971 xfer->busy_free); 972 } 973 xfer->busy_free = XFER_FREE; 974 #endif 975 pool_cache_put(sc->sc_xferpool, xfer); 976 } 977 978 Static void 979 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 980 { 981 struct ohci_softc *sc = bus->hci_private; 982 983 *lock = &sc->sc_lock; 984 } 985 986 /* 987 * Shut down the controller when the system is going down. 988 */ 989 bool 990 ohci_shutdown(device_t self, int flags) 991 { 992 ohci_softc_t *sc = device_private(self); 993 994 DPRINTF(("ohci_shutdown: stopping the HC\n")); 995 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 996 return true; 997 } 998 999 bool 1000 ohci_resume(device_t dv, const pmf_qual_t *qual) 1001 { 1002 ohci_softc_t *sc = device_private(dv); 1003 uint32_t ctl; 1004 1005 mutex_spin_enter(&sc->sc_intr_lock); 1006 sc->sc_bus.use_polling++; 1007 mutex_spin_exit(&sc->sc_intr_lock); 1008 1009 /* Some broken BIOSes do not recover these values */ 1010 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1011 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1012 sc->sc_ctrl_head->physaddr); 1013 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1014 sc->sc_bulk_head->physaddr); 1015 if (sc->sc_intre) 1016 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1017 (OHCI_ALL_INTRS | OHCI_MIE)); 1018 if (sc->sc_control) 1019 ctl = sc->sc_control; 1020 else 1021 ctl = OREAD4(sc, OHCI_CONTROL); 1022 ctl |= OHCI_HCFS_RESUME; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1025 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1026 OWRITE4(sc, OHCI_CONTROL, ctl); 1027 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1028 sc->sc_control = sc->sc_intre = 0; 1029 1030 mutex_spin_enter(&sc->sc_intr_lock); 1031 sc->sc_bus.use_polling--; 1032 mutex_spin_exit(&sc->sc_intr_lock); 1033 1034 return true; 1035 } 1036 1037 bool 1038 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1039 { 1040 ohci_softc_t *sc = device_private(dv); 1041 uint32_t ctl; 1042 1043 mutex_spin_enter(&sc->sc_intr_lock); 1044 sc->sc_bus.use_polling++; 1045 mutex_spin_exit(&sc->sc_intr_lock); 1046 1047 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1048 if (sc->sc_control == 0) { 1049 /* 1050 * Preserve register values, in case that BIOS 1051 * does not recover them. 1052 */ 1053 sc->sc_control = ctl; 1054 sc->sc_intre = OREAD4(sc, 1055 OHCI_INTERRUPT_ENABLE); 1056 } 1057 ctl |= OHCI_HCFS_SUSPEND; 1058 OWRITE4(sc, OHCI_CONTROL, ctl); 1059 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1060 1061 mutex_spin_enter(&sc->sc_intr_lock); 1062 sc->sc_bus.use_polling--; 1063 mutex_spin_exit(&sc->sc_intr_lock); 1064 1065 return true; 1066 } 1067 1068 #ifdef OHCI_DEBUG 1069 void 1070 ohci_dumpregs(ohci_softc_t *sc) 1071 { 1072 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1073 OREAD4(sc, OHCI_REVISION), 1074 OREAD4(sc, OHCI_CONTROL), 1075 OREAD4(sc, OHCI_COMMAND_STATUS))); 1076 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1077 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1078 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1079 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1080 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1081 OREAD4(sc, OHCI_HCCA), 1082 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1083 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1084 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1085 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1086 OREAD4(sc, OHCI_BULK_HEAD_ED), 1087 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1088 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1089 OREAD4(sc, OHCI_DONE_HEAD), 1090 OREAD4(sc, OHCI_FM_INTERVAL), 1091 OREAD4(sc, OHCI_FM_REMAINING))); 1092 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1093 OREAD4(sc, OHCI_FM_NUMBER), 1094 OREAD4(sc, OHCI_PERIODIC_START), 1095 OREAD4(sc, OHCI_LS_THRESHOLD))); 1096 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1097 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1098 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1099 OREAD4(sc, OHCI_RH_STATUS))); 1100 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1101 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1102 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1103 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1104 O32TOH(sc->sc_hcca->hcca_frame_number), 1105 O32TOH(sc->sc_hcca->hcca_done_head))); 1106 } 1107 #endif 1108 1109 Static int ohci_intr1(ohci_softc_t *); 1110 1111 int 1112 ohci_intr(void *p) 1113 { 1114 ohci_softc_t *sc = p; 1115 int ret = 0; 1116 1117 if (sc == NULL) 1118 return (0); 1119 1120 mutex_spin_enter(&sc->sc_intr_lock); 1121 1122 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1123 goto done; 1124 1125 /* If we get an interrupt while polling, then just ignore it. */ 1126 if (sc->sc_bus.use_polling) { 1127 #ifdef DIAGNOSTIC 1128 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1129 #endif 1130 /* for level triggered intrs, should do something to ack */ 1131 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1132 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1133 1134 goto done; 1135 } 1136 1137 ret = ohci_intr1(sc); 1138 1139 done: 1140 mutex_spin_exit(&sc->sc_intr_lock); 1141 return ret; 1142 } 1143 1144 Static int 1145 ohci_intr1(ohci_softc_t *sc) 1146 { 1147 u_int32_t intrs, eintrs; 1148 1149 DPRINTFN(14,("ohci_intr1: enter\n")); 1150 1151 /* In case the interrupt occurs before initialization has completed. */ 1152 if (sc == NULL || sc->sc_hcca == NULL) { 1153 #ifdef DIAGNOSTIC 1154 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1155 #endif 1156 return (0); 1157 } 1158 1159 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1160 1161 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1162 if (!intrs) 1163 return (0); 1164 1165 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1166 eintrs = intrs & sc->sc_eintrs; 1167 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1168 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1169 (u_int)eintrs, sc->sc_eintrs)); 1170 1171 if (!eintrs) { 1172 return (0); 1173 } 1174 1175 sc->sc_bus.no_intrs++; 1176 if (eintrs & OHCI_SO) { 1177 sc->sc_overrun_cnt++; 1178 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1179 printf("%s: %u scheduling overruns\n", 1180 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1181 sc->sc_overrun_cnt = 0; 1182 } 1183 /* XXX do what */ 1184 eintrs &= ~OHCI_SO; 1185 } 1186 if (eintrs & OHCI_WDH) { 1187 /* 1188 * We block the interrupt below, and reenable it later from 1189 * ohci_softintr(). 1190 */ 1191 usb_schedsoftintr(&sc->sc_bus); 1192 } 1193 if (eintrs & OHCI_RD) { 1194 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1195 /* XXX process resume detect */ 1196 } 1197 if (eintrs & OHCI_UE) { 1198 printf("%s: unrecoverable error, controller halted\n", 1199 device_xname(sc->sc_dev)); 1200 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1201 /* XXX what else */ 1202 } 1203 if (eintrs & OHCI_RHSC) { 1204 /* 1205 * We block the interrupt below, and reenable it later from 1206 * a timeout. 1207 */ 1208 softint_schedule(sc->sc_rhsc_si); 1209 } 1210 1211 if (eintrs != 0) { 1212 /* Block unprocessed interrupts. */ 1213 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1214 sc->sc_eintrs &= ~eintrs; 1215 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1216 device_xname(sc->sc_dev), eintrs)); 1217 } 1218 1219 return (1); 1220 } 1221 1222 void 1223 ohci_rhsc_enable(void *v_sc) 1224 { 1225 ohci_softc_t *sc = v_sc; 1226 1227 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1228 mutex_spin_enter(&sc->sc_intr_lock); 1229 sc->sc_eintrs |= OHCI_RHSC; 1230 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1231 mutex_spin_exit(&sc->sc_intr_lock); 1232 } 1233 1234 #ifdef OHCI_DEBUG 1235 const char *ohci_cc_strs[] = { 1236 "NO_ERROR", 1237 "CRC", 1238 "BIT_STUFFING", 1239 "DATA_TOGGLE_MISMATCH", 1240 "STALL", 1241 "DEVICE_NOT_RESPONDING", 1242 "PID_CHECK_FAILURE", 1243 "UNEXPECTED_PID", 1244 "DATA_OVERRUN", 1245 "DATA_UNDERRUN", 1246 "BUFFER_OVERRUN", 1247 "BUFFER_UNDERRUN", 1248 "reserved", 1249 "reserved", 1250 "NOT_ACCESSED", 1251 "NOT_ACCESSED", 1252 }; 1253 #endif 1254 1255 void 1256 ohci_softintr(void *v) 1257 { 1258 struct usbd_bus *bus = v; 1259 ohci_softc_t *sc = bus->hci_private; 1260 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1261 ohci_soft_td_t *std, *sdone, *stdnext; 1262 usbd_xfer_handle xfer; 1263 struct ohci_pipe *opipe; 1264 int len, cc; 1265 int i, j, actlen, iframes, uedir; 1266 ohci_physaddr_t done; 1267 1268 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1269 1270 DPRINTFN(10,("ohci_softintr: enter\n")); 1271 1272 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1273 sizeof(sc->sc_hcca->hcca_done_head), 1274 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1275 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1276 sc->sc_hcca->hcca_done_head = 0; 1277 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1278 sizeof(sc->sc_hcca->hcca_done_head), 1279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1280 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1281 sc->sc_eintrs |= OHCI_WDH; 1282 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1283 1284 /* Reverse the done list. */ 1285 for (sdone = NULL, sidone = NULL; done != 0; ) { 1286 std = ohci_hash_find_td(sc, done); 1287 if (std != NULL) { 1288 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1289 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1290 std->dnext = sdone; 1291 done = O32TOH(std->td.td_nexttd); 1292 sdone = std; 1293 DPRINTFN(10,("add TD %p\n", std)); 1294 continue; 1295 } 1296 sitd = ohci_hash_find_itd(sc, done); 1297 if (sitd != NULL) { 1298 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1299 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1300 sitd->dnext = sidone; 1301 done = O32TOH(sitd->itd.itd_nextitd); 1302 sidone = sitd; 1303 DPRINTFN(5,("add ITD %p\n", sitd)); 1304 continue; 1305 } 1306 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1307 (u_long)done); 1308 break; 1309 } 1310 1311 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1312 1313 #ifdef OHCI_DEBUG 1314 if (ohcidebug > 10) { 1315 DPRINTF(("ohci_process_done: TD done:\n")); 1316 for (std = sdone; std; std = std->dnext) 1317 ohci_dump_td(sc, std); 1318 } 1319 #endif 1320 1321 for (std = sdone; std; std = stdnext) { 1322 xfer = std->xfer; 1323 stdnext = std->dnext; 1324 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1325 std, xfer, xfer ? xfer->hcpriv : 0)); 1326 if (xfer == NULL) { 1327 /* 1328 * xfer == NULL: There seems to be no xfer associated 1329 * with this TD. It is tailp that happened to end up on 1330 * the done queue. 1331 * Shouldn't happen, but some chips are broken(?). 1332 */ 1333 continue; 1334 } 1335 if (xfer->status == USBD_CANCELLED || 1336 xfer->status == USBD_TIMEOUT) { 1337 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1338 xfer)); 1339 /* Handled by abort routine. */ 1340 continue; 1341 } 1342 callout_stop(&xfer->timeout_handle); 1343 1344 len = std->len; 1345 if (std->td.td_cbp != 0) 1346 len -= O32TOH(std->td.td_be) - 1347 O32TOH(std->td.td_cbp) + 1; 1348 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1349 std->flags)); 1350 if (std->flags & OHCI_ADD_LEN) 1351 xfer->actlen += len; 1352 1353 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1354 if (cc == OHCI_CC_NO_ERROR) { 1355 if (std->flags & OHCI_CALL_DONE) { 1356 xfer->status = USBD_NORMAL_COMPLETION; 1357 usb_transfer_complete(xfer); 1358 } 1359 ohci_free_std(sc, std); 1360 } else { 1361 /* 1362 * Endpoint is halted. First unlink all the TDs 1363 * belonging to the failed transfer, and then restart 1364 * the endpoint. 1365 */ 1366 ohci_soft_td_t *p, *n; 1367 opipe = (struct ohci_pipe *)xfer->pipe; 1368 1369 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1370 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1371 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1372 1373 /* remove TDs */ 1374 for (p = std; p->xfer == xfer; p = n) { 1375 n = p->nexttd; 1376 ohci_free_std(sc, p); 1377 } 1378 1379 /* clear halt */ 1380 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1381 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1382 1383 if (cc == OHCI_CC_STALL) 1384 xfer->status = USBD_STALLED; 1385 else 1386 xfer->status = USBD_IOERROR; 1387 usb_transfer_complete(xfer); 1388 } 1389 } 1390 1391 #ifdef OHCI_DEBUG 1392 if (ohcidebug > 10) { 1393 DPRINTF(("ohci_softintr: ITD done:\n")); 1394 for (sitd = sidone; sitd; sitd = sitd->dnext) 1395 ohci_dump_itd(sc, sitd); 1396 } 1397 #endif 1398 1399 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1400 xfer = sitd->xfer; 1401 sitdnext = sitd->dnext; 1402 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1403 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1404 if (xfer == NULL) 1405 continue; 1406 if (xfer->status == USBD_CANCELLED || 1407 xfer->status == USBD_TIMEOUT) { 1408 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1409 xfer)); 1410 /* Handled by abort routine. */ 1411 continue; 1412 } 1413 #ifdef DIAGNOSTIC 1414 if (sitd->isdone) 1415 printf("ohci_softintr: sitd=%p is done\n", sitd); 1416 sitd->isdone = 1; 1417 #endif 1418 if (sitd->flags & OHCI_CALL_DONE) { 1419 ohci_soft_itd_t *next; 1420 1421 opipe = (struct ohci_pipe *)xfer->pipe; 1422 opipe->u.iso.inuse -= xfer->nframes; 1423 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1424 bEndpointAddress); 1425 xfer->status = USBD_NORMAL_COMPLETION; 1426 actlen = 0; 1427 for (i = 0, sitd = xfer->hcpriv;; 1428 sitd = next) { 1429 next = sitd->nextitd; 1430 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1431 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1432 xfer->status = USBD_IOERROR; 1433 /* For input, update frlengths with actual */ 1434 /* XXX anything necessary for output? */ 1435 if (uedir == UE_DIR_IN && 1436 xfer->status == USBD_NORMAL_COMPLETION) { 1437 iframes = OHCI_ITD_GET_FC(O32TOH( 1438 sitd->itd.itd_flags)); 1439 for (j = 0; j < iframes; i++, j++) { 1440 len = O16TOH(sitd-> 1441 itd.itd_offset[j]); 1442 if ((OHCI_ITD_PSW_GET_CC(len) & 1443 OHCI_CC_NOT_ACCESSED_MASK) 1444 == OHCI_CC_NOT_ACCESSED) 1445 len = 0; 1446 else 1447 len = OHCI_ITD_PSW_LENGTH(len); 1448 xfer->frlengths[i] = len; 1449 actlen += len; 1450 } 1451 } 1452 if (sitd->flags & OHCI_CALL_DONE) 1453 break; 1454 ohci_free_sitd(sc, sitd); 1455 } 1456 ohci_free_sitd(sc, sitd); 1457 if (uedir == UE_DIR_IN && 1458 xfer->status == USBD_NORMAL_COMPLETION) 1459 xfer->actlen = actlen; 1460 xfer->hcpriv = NULL; 1461 1462 usb_transfer_complete(xfer); 1463 } 1464 } 1465 1466 if (sc->sc_softwake) { 1467 sc->sc_softwake = 0; 1468 cv_broadcast(&sc->sc_softwake_cv); 1469 } 1470 1471 DPRINTFN(10,("ohci_softintr: done:\n")); 1472 } 1473 1474 void 1475 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1476 { 1477 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1478 #ifdef DIAGNOSTIC 1479 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1480 #endif 1481 int len = UGETW(xfer->request.wLength); 1482 int isread = (xfer->request.bmRequestType & UT_READ); 1483 1484 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1485 1486 KASSERT(mutex_owned(&sc->sc_lock)); 1487 1488 #ifdef DIAGNOSTIC 1489 if (!(xfer->rqflags & URQ_REQUEST)) { 1490 panic("ohci_device_ctrl_done: not a request"); 1491 } 1492 #endif 1493 if (len) 1494 usb_syncmem(&xfer->dmabuf, 0, len, 1495 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1496 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1497 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1498 } 1499 1500 void 1501 ohci_device_intr_done(usbd_xfer_handle xfer) 1502 { 1503 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1504 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1505 ohci_soft_ed_t *sed = opipe->sed; 1506 ohci_soft_td_t *data, *tail; 1507 int isread = 1508 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1509 1510 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1511 xfer, xfer->actlen)); 1512 1513 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1514 1515 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1516 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1517 if (xfer->pipe->repeat) { 1518 data = opipe->tail.td; 1519 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1520 if (tail == NULL) { 1521 xfer->status = USBD_NOMEM; 1522 return; 1523 } 1524 tail->xfer = NULL; 1525 1526 data->td.td_flags = HTOO32( 1527 OHCI_TD_IN | OHCI_TD_NOCC | 1528 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1529 if (xfer->flags & USBD_SHORT_XFER_OK) 1530 data->td.td_flags |= HTOO32(OHCI_TD_R); 1531 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1532 data->nexttd = tail; 1533 data->td.td_nexttd = HTOO32(tail->physaddr); 1534 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1535 xfer->length - 1); 1536 data->len = xfer->length; 1537 data->xfer = xfer; 1538 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1539 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1541 xfer->hcpriv = data; 1542 xfer->actlen = 0; 1543 1544 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1545 usb_syncmem(&sed->dma, 1546 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1547 sizeof(sed->ed.ed_tailp), 1548 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1549 opipe->tail.td = tail; 1550 } 1551 } 1552 1553 void 1554 ohci_device_bulk_done(usbd_xfer_handle xfer) 1555 { 1556 #ifdef DIAGNOSTIC 1557 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1558 #endif 1559 int isread = 1560 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1561 1562 KASSERT(mutex_owned(&sc->sc_lock)); 1563 1564 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1565 xfer, xfer->actlen)); 1566 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1567 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1568 } 1569 1570 Static void 1571 ohci_rhsc_softint(void *arg) 1572 { 1573 ohci_softc_t *sc = arg; 1574 1575 mutex_enter(&sc->sc_lock); 1576 1577 ohci_rhsc(sc, sc->sc_intrxfer); 1578 1579 /* Do not allow RHSC interrupts > 1 per second */ 1580 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1581 1582 mutex_exit(&sc->sc_lock); 1583 } 1584 1585 void 1586 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1587 { 1588 usbd_pipe_handle pipe; 1589 u_char *p; 1590 int i, m; 1591 int hstatus; 1592 1593 KASSERT(mutex_owned(&sc->sc_lock)); 1594 1595 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1596 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1597 sc, xfer, hstatus)); 1598 1599 if (xfer == NULL) { 1600 /* Just ignore the change. */ 1601 return; 1602 } 1603 1604 pipe = xfer->pipe; 1605 1606 p = KERNADDR(&xfer->dmabuf, 0); 1607 m = min(sc->sc_noport, xfer->length * 8 - 1); 1608 memset(p, 0, xfer->length); 1609 for (i = 1; i <= m; i++) { 1610 /* Pick out CHANGE bits from the status reg. */ 1611 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1612 p[i/8] |= 1 << (i%8); 1613 } 1614 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1615 xfer->actlen = xfer->length; 1616 xfer->status = USBD_NORMAL_COMPLETION; 1617 1618 usb_transfer_complete(xfer); 1619 } 1620 1621 void 1622 ohci_root_intr_done(usbd_xfer_handle xfer) 1623 { 1624 } 1625 1626 void 1627 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1628 { 1629 } 1630 1631 /* 1632 * Wait here until controller claims to have an interrupt. 1633 * Then call ohci_intr and return. Use timeout to avoid waiting 1634 * too long. 1635 */ 1636 void 1637 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1638 { 1639 int timo; 1640 u_int32_t intrs; 1641 1642 mutex_enter(&sc->sc_lock); 1643 1644 xfer->status = USBD_IN_PROGRESS; 1645 for (timo = xfer->timeout; timo >= 0; timo--) { 1646 usb_delay_ms(&sc->sc_bus, 1); 1647 if (sc->sc_dying) 1648 break; 1649 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1650 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1651 #ifdef OHCI_DEBUG 1652 if (ohcidebug > 15) 1653 ohci_dumpregs(sc); 1654 #endif 1655 if (intrs) { 1656 mutex_spin_enter(&sc->sc_intr_lock); 1657 ohci_intr1(sc); 1658 mutex_spin_exit(&sc->sc_intr_lock); 1659 if (xfer->status != USBD_IN_PROGRESS) 1660 goto done; 1661 } 1662 } 1663 1664 /* Timeout */ 1665 DPRINTF(("ohci_waitintr: timeout\n")); 1666 xfer->status = USBD_TIMEOUT; 1667 usb_transfer_complete(xfer); 1668 1669 /* XXX should free TD */ 1670 1671 done: 1672 mutex_exit(&sc->sc_lock); 1673 } 1674 1675 void 1676 ohci_poll(struct usbd_bus *bus) 1677 { 1678 ohci_softc_t *sc = bus->hci_private; 1679 #ifdef OHCI_DEBUG 1680 static int last; 1681 int new; 1682 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1683 if (new != last) { 1684 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1685 last = new; 1686 } 1687 #endif 1688 sc->sc_eintrs |= OHCI_WDH; 1689 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1690 mutex_spin_enter(&sc->sc_intr_lock); 1691 ohci_intr1(sc); 1692 mutex_spin_exit(&sc->sc_intr_lock); 1693 } 1694 } 1695 1696 usbd_status 1697 ohci_device_request(usbd_xfer_handle xfer) 1698 { 1699 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1700 usb_device_request_t *req = &xfer->request; 1701 usbd_device_handle dev = opipe->pipe.device; 1702 ohci_softc_t *sc = dev->bus->hci_private; 1703 int addr = dev->address; 1704 ohci_soft_td_t *setup, *stat, *next, *tail; 1705 ohci_soft_ed_t *sed; 1706 int isread; 1707 int len; 1708 usbd_status err; 1709 1710 KASSERT(mutex_owned(&sc->sc_lock)); 1711 1712 isread = req->bmRequestType & UT_READ; 1713 len = UGETW(req->wLength); 1714 1715 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1716 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1717 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1718 UGETW(req->wIndex), len, addr, 1719 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1720 1721 setup = opipe->tail.td; 1722 stat = ohci_alloc_std(sc); 1723 if (stat == NULL) { 1724 err = USBD_NOMEM; 1725 goto bad1; 1726 } 1727 tail = ohci_alloc_std(sc); 1728 if (tail == NULL) { 1729 err = USBD_NOMEM; 1730 goto bad2; 1731 } 1732 tail->xfer = NULL; 1733 1734 sed = opipe->sed; 1735 opipe->u.ctl.length = len; 1736 1737 /* Update device address and length since they may have changed 1738 during the setup of the control pipe in usbd_new_device(). */ 1739 /* XXX This only needs to be done once, but it's too early in open. */ 1740 /* XXXX Should not touch ED here! */ 1741 1742 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1743 sizeof(sed->ed.ed_flags), 1744 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1745 sed->ed.ed_flags = HTOO32( 1746 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1747 OHCI_ED_SET_FA(addr) | 1748 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1749 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1750 sizeof(sed->ed.ed_flags), 1751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1752 1753 next = stat; 1754 1755 /* Set up data transaction */ 1756 if (len != 0) { 1757 ohci_soft_td_t *std = stat; 1758 1759 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1760 std, &stat); 1761 if (err) { 1762 /* stat is unchanged if error */ 1763 goto bad3; 1764 } 1765 stat = stat->nexttd; /* point at free TD */ 1766 1767 /* Start toggle at 1 and then use the carried toggle. */ 1768 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1769 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1770 usb_syncmem(&std->dma, 1771 std->offs + offsetof(ohci_td_t, td_flags), 1772 sizeof(std->td.td_flags), 1773 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1774 } 1775 1776 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1777 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1778 1779 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1780 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1781 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1782 setup->nexttd = next; 1783 setup->td.td_nexttd = HTOO32(next->physaddr); 1784 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1785 setup->len = 0; 1786 setup->xfer = xfer; 1787 setup->flags = 0; 1788 xfer->hcpriv = setup; 1789 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1790 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1791 1792 stat->td.td_flags = HTOO32( 1793 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1794 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1795 stat->td.td_cbp = 0; 1796 stat->nexttd = tail; 1797 stat->td.td_nexttd = HTOO32(tail->physaddr); 1798 stat->td.td_be = 0; 1799 stat->flags = OHCI_CALL_DONE; 1800 stat->len = 0; 1801 stat->xfer = xfer; 1802 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1803 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1804 1805 #ifdef OHCI_DEBUG 1806 if (ohcidebug > 5) { 1807 DPRINTF(("ohci_device_request:\n")); 1808 ohci_dump_ed(sc, sed); 1809 ohci_dump_tds(sc, setup); 1810 } 1811 #endif 1812 1813 /* Insert ED in schedule */ 1814 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1815 usb_syncmem(&sed->dma, 1816 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1817 sizeof(sed->ed.ed_tailp), 1818 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1819 opipe->tail.td = tail; 1820 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1821 if (xfer->timeout && !sc->sc_bus.use_polling) { 1822 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1823 ohci_timeout, xfer); 1824 } 1825 1826 #ifdef OHCI_DEBUG 1827 if (ohcidebug > 20) { 1828 delay(10000); 1829 DPRINTF(("ohci_device_request: status=%x\n", 1830 OREAD4(sc, OHCI_COMMAND_STATUS))); 1831 ohci_dumpregs(sc); 1832 printf("ctrl head:\n"); 1833 ohci_dump_ed(sc, sc->sc_ctrl_head); 1834 printf("sed:\n"); 1835 ohci_dump_ed(sc, sed); 1836 ohci_dump_tds(sc, setup); 1837 } 1838 #endif 1839 1840 return (USBD_NORMAL_COMPLETION); 1841 1842 bad3: 1843 ohci_free_std(sc, tail); 1844 bad2: 1845 ohci_free_std(sc, stat); 1846 bad1: 1847 return (err); 1848 } 1849 1850 /* 1851 * Add an ED to the schedule. Called with USB lock held. 1852 */ 1853 Static void 1854 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1855 { 1856 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1857 1858 KASSERT(mutex_owned(&sc->sc_lock)); 1859 1860 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1861 sizeof(head->ed.ed_nexted), 1862 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1863 sed->next = head->next; 1864 sed->ed.ed_nexted = head->ed.ed_nexted; 1865 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1866 sizeof(sed->ed.ed_nexted), 1867 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1868 head->next = sed; 1869 head->ed.ed_nexted = HTOO32(sed->physaddr); 1870 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1871 sizeof(head->ed.ed_nexted), 1872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1873 } 1874 1875 /* 1876 * Remove an ED from the schedule. Called with USB lock held. 1877 */ 1878 Static void 1879 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1880 { 1881 ohci_soft_ed_t *p; 1882 1883 KASSERT(mutex_owned(&sc->sc_lock)); 1884 1885 /* XXX */ 1886 for (p = head; p != NULL && p->next != sed; p = p->next) 1887 ; 1888 if (p == NULL) 1889 panic("ohci_rem_ed: ED not found"); 1890 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1891 sizeof(sed->ed.ed_nexted), 1892 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1893 p->next = sed->next; 1894 p->ed.ed_nexted = sed->ed.ed_nexted; 1895 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1896 sizeof(p->ed.ed_nexted), 1897 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1898 } 1899 1900 /* 1901 * When a transfer is completed the TD is added to the done queue by 1902 * the host controller. This queue is the processed by software. 1903 * Unfortunately the queue contains the physical address of the TD 1904 * and we have no simple way to translate this back to a kernel address. 1905 * To make the translation possible (and fast) we use a hash table of 1906 * TDs currently in the schedule. The physical address is used as the 1907 * hash value. 1908 */ 1909 1910 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1911 /* Called with USB lock held. */ 1912 void 1913 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1914 { 1915 int h = HASH(std->physaddr); 1916 1917 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1918 1919 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1920 } 1921 1922 /* Called with USB lock held. */ 1923 void 1924 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1925 { 1926 1927 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1928 1929 LIST_REMOVE(std, hnext); 1930 } 1931 1932 ohci_soft_td_t * 1933 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1934 { 1935 int h = HASH(a); 1936 ohci_soft_td_t *std; 1937 1938 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1939 std != NULL; 1940 std = LIST_NEXT(std, hnext)) 1941 if (std->physaddr == a) 1942 return (std); 1943 return (NULL); 1944 } 1945 1946 /* Called with USB lock held. */ 1947 void 1948 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1949 { 1950 int h = HASH(sitd->physaddr); 1951 1952 KASSERT(mutex_owned(&sc->sc_lock)); 1953 1954 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1955 sitd, (u_long)sitd->physaddr)); 1956 1957 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1958 } 1959 1960 /* Called with USB lock held. */ 1961 void 1962 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1963 { 1964 1965 KASSERT(mutex_owned(&sc->sc_lock)); 1966 1967 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1968 sitd, (u_long)sitd->physaddr)); 1969 1970 LIST_REMOVE(sitd, hnext); 1971 } 1972 1973 ohci_soft_itd_t * 1974 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1975 { 1976 int h = HASH(a); 1977 ohci_soft_itd_t *sitd; 1978 1979 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1980 sitd != NULL; 1981 sitd = LIST_NEXT(sitd, hnext)) 1982 if (sitd->physaddr == a) 1983 return (sitd); 1984 return (NULL); 1985 } 1986 1987 void 1988 ohci_timeout(void *addr) 1989 { 1990 struct ohci_xfer *oxfer = addr; 1991 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1992 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1993 1994 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1995 1996 if (sc->sc_dying) { 1997 mutex_enter(&sc->sc_lock); 1998 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1999 mutex_exit(&sc->sc_lock); 2000 return; 2001 } 2002 2003 /* Execute the abort in a process context. */ 2004 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2005 USB_TASKQ_MPSAFE); 2006 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2007 USB_TASKQ_HC); 2008 } 2009 2010 void 2011 ohci_timeout_task(void *addr) 2012 { 2013 usbd_xfer_handle xfer = addr; 2014 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2015 2016 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2017 2018 mutex_enter(&sc->sc_lock); 2019 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2020 mutex_exit(&sc->sc_lock); 2021 } 2022 2023 #ifdef OHCI_DEBUG 2024 void 2025 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2026 { 2027 for (; std; std = std->nexttd) 2028 ohci_dump_td(sc, std); 2029 } 2030 2031 void 2032 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2033 { 2034 char sbuf[128]; 2035 2036 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2038 snprintb(sbuf, sizeof(sbuf), 2039 "\177\20" 2040 "b\22R\0" 2041 "f\23\02DP\0" 2042 "=\x0" "setup\0" 2043 "=\x1" "out\0" 2044 "=\x2" "in\0" 2045 "=\x3" "reserved\0" 2046 "f\25\03DI\0" 2047 "=\x07" "none\0" 2048 "f\30\02T\0" 2049 "=\x0" "carry\0" 2050 "=\x1" "carry\0" 2051 "=\x2" "0\0" 2052 "=\x3" "1\0" 2053 "f\32\02EC\0" 2054 "f\34\04CC\0", 2055 (u_int32_t)O32TOH(std->td.td_flags)); 2056 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2057 std, (u_long)std->physaddr, sbuf, 2058 (u_long)O32TOH(std->td.td_cbp), 2059 (u_long)O32TOH(std->td.td_nexttd), 2060 (u_long)O32TOH(std->td.td_be)); 2061 } 2062 2063 void 2064 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2065 { 2066 int i; 2067 2068 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2069 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2070 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2071 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2072 sitd, (u_long)sitd->physaddr, 2073 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2074 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2075 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2076 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2077 (u_long)O32TOH(sitd->itd.itd_bp0), 2078 (u_long)O32TOH(sitd->itd.itd_nextitd), 2079 (u_long)O32TOH(sitd->itd.itd_be)); 2080 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2081 printf("offs[%d]=0x%04x ", i, 2082 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2083 printf("\n"); 2084 } 2085 2086 void 2087 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2088 { 2089 for (; sitd; sitd = sitd->nextitd) 2090 ohci_dump_itd(sc, sitd); 2091 } 2092 2093 void 2094 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2095 { 2096 char sbuf[128], sbuf2[128]; 2097 2098 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2099 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2100 snprintb(sbuf, sizeof(sbuf), 2101 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2102 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2103 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2104 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2105 2106 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2107 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2108 sed, (u_long)sed->physaddr, 2109 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2110 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2111 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2112 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2113 (u_long)O32TOH(sed->ed.ed_headp), 2114 (u_long)O32TOH(sed->ed.ed_nexted)); 2115 } 2116 #endif 2117 2118 usbd_status 2119 ohci_open(usbd_pipe_handle pipe) 2120 { 2121 usbd_device_handle dev = pipe->device; 2122 ohci_softc_t *sc = dev->bus->hci_private; 2123 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2124 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2125 u_int8_t addr = dev->address; 2126 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2127 ohci_soft_ed_t *sed; 2128 ohci_soft_td_t *std; 2129 ohci_soft_itd_t *sitd; 2130 ohci_physaddr_t tdphys; 2131 u_int32_t fmt; 2132 usbd_status err = USBD_NOMEM; 2133 int ival; 2134 2135 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2136 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2137 2138 if (sc->sc_dying) { 2139 return USBD_IOERROR; 2140 } 2141 2142 std = NULL; 2143 sed = NULL; 2144 2145 if (addr == sc->sc_addr) { 2146 switch (ed->bEndpointAddress) { 2147 case USB_CONTROL_ENDPOINT: 2148 pipe->methods = &ohci_root_ctrl_methods; 2149 break; 2150 case UE_DIR_IN | OHCI_INTR_ENDPT: 2151 pipe->methods = &ohci_root_intr_methods; 2152 break; 2153 default: 2154 err = USBD_INVAL; 2155 goto bad; 2156 } 2157 } else { 2158 sed = ohci_alloc_sed(sc); 2159 if (sed == NULL) 2160 goto bad; 2161 opipe->sed = sed; 2162 if (xfertype == UE_ISOCHRONOUS) { 2163 mutex_enter(&sc->sc_lock); 2164 sitd = ohci_alloc_sitd(sc); 2165 mutex_exit(&sc->sc_lock); 2166 if (sitd == NULL) 2167 goto bad; 2168 2169 opipe->tail.itd = sitd; 2170 tdphys = sitd->physaddr; 2171 fmt = OHCI_ED_FORMAT_ISO; 2172 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2173 fmt |= OHCI_ED_DIR_IN; 2174 else 2175 fmt |= OHCI_ED_DIR_OUT; 2176 } else { 2177 mutex_enter(&sc->sc_lock); 2178 std = ohci_alloc_std(sc); 2179 mutex_exit(&sc->sc_lock); 2180 if (std == NULL) 2181 goto bad; 2182 2183 opipe->tail.td = std; 2184 tdphys = std->physaddr; 2185 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2186 } 2187 sed->ed.ed_flags = HTOO32( 2188 OHCI_ED_SET_FA(addr) | 2189 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2190 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2191 fmt | 2192 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2193 sed->ed.ed_headp = HTOO32(tdphys | 2194 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2195 sed->ed.ed_tailp = HTOO32(tdphys); 2196 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2198 2199 switch (xfertype) { 2200 case UE_CONTROL: 2201 pipe->methods = &ohci_device_ctrl_methods; 2202 err = usb_allocmem(&sc->sc_bus, 2203 sizeof(usb_device_request_t), 2204 0, &opipe->u.ctl.reqdma); 2205 if (err) 2206 goto bad; 2207 mutex_enter(&sc->sc_lock); 2208 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2209 mutex_exit(&sc->sc_lock); 2210 break; 2211 case UE_INTERRUPT: 2212 pipe->methods = &ohci_device_intr_methods; 2213 ival = pipe->interval; 2214 if (ival == USBD_DEFAULT_INTERVAL) 2215 ival = ed->bInterval; 2216 err = ohci_device_setintr(sc, opipe, ival); 2217 if (err) 2218 goto bad; 2219 break; 2220 case UE_ISOCHRONOUS: 2221 pipe->methods = &ohci_device_isoc_methods; 2222 return (ohci_setup_isoc(pipe)); 2223 case UE_BULK: 2224 pipe->methods = &ohci_device_bulk_methods; 2225 mutex_enter(&sc->sc_lock); 2226 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2227 mutex_exit(&sc->sc_lock); 2228 break; 2229 } 2230 } 2231 2232 return USBD_NORMAL_COMPLETION; 2233 2234 bad: 2235 if (std != NULL) { 2236 mutex_enter(&sc->sc_lock); 2237 ohci_free_std(sc, std); 2238 mutex_exit(&sc->sc_lock); 2239 } 2240 if (sed != NULL) 2241 ohci_free_sed(sc, sed); 2242 return err; 2243 2244 } 2245 2246 /* 2247 * Close a reqular pipe. 2248 * Assumes that there are no pending transactions. 2249 */ 2250 void 2251 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2252 { 2253 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2254 ohci_softc_t *sc = pipe->device->bus->hci_private; 2255 ohci_soft_ed_t *sed = opipe->sed; 2256 2257 KASSERT(mutex_owned(&sc->sc_lock)); 2258 2259 #ifdef DIAGNOSTIC 2260 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2261 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2262 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2263 ohci_soft_td_t *std; 2264 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2265 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2266 "tl=0x%x pipe=%p, std=%p\n", sed, 2267 (int)O32TOH(sed->ed.ed_headp), 2268 (int)O32TOH(sed->ed.ed_tailp), 2269 pipe, std); 2270 #ifdef OHCI_DEBUG 2271 usbd_dump_pipe(&opipe->pipe); 2272 ohci_dump_ed(sc, sed); 2273 if (std) 2274 ohci_dump_td(sc, std); 2275 #endif 2276 usb_delay_ms(&sc->sc_bus, 2); 2277 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2278 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2279 printf("ohci_close_pipe: pipe still not empty\n"); 2280 } 2281 #endif 2282 ohci_rem_ed(sc, sed, head); 2283 /* Make sure the host controller is not touching this ED */ 2284 usb_delay_ms(&sc->sc_bus, 1); 2285 pipe->endpoint->datatoggle = 2286 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2287 ohci_free_sed(sc, opipe->sed); 2288 } 2289 2290 /* 2291 * Abort a device request. 2292 * If this routine is called at splusb() it guarantees that the request 2293 * will be removed from the hardware scheduling and that the callback 2294 * for it will be called with USBD_CANCELLED status. 2295 * It's impossible to guarantee that the requested transfer will not 2296 * have happened since the hardware runs concurrently. 2297 * If the transaction has already happened we rely on the ordinary 2298 * interrupt processing to process it. 2299 * XXX This is most probably wrong. 2300 * XXXMRG this doesn't make sense anymore. 2301 */ 2302 void 2303 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2304 { 2305 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2306 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2307 ohci_soft_ed_t *sed = opipe->sed; 2308 ohci_soft_td_t *p, *n; 2309 ohci_physaddr_t headp; 2310 int hit; 2311 int wake; 2312 2313 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2314 2315 KASSERT(mutex_owned(&sc->sc_lock)); 2316 2317 if (sc->sc_dying) { 2318 /* If we're dying, just do the software part. */ 2319 xfer->status = status; /* make software ignore it */ 2320 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2321 usb_transfer_complete(xfer); 2322 return; 2323 } 2324 2325 if (cpu_intr_p() || cpu_softintr_p()) 2326 panic("ohci_abort_xfer: not in process context"); 2327 2328 /* 2329 * If an abort is already in progress then just wait for it to 2330 * complete and return. 2331 */ 2332 if (xfer->hcflags & UXFER_ABORTING) { 2333 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2334 #ifdef DIAGNOSTIC 2335 if (status == USBD_TIMEOUT) 2336 printf("%s: TIMEOUT while aborting\n", __func__); 2337 #endif 2338 /* Override the status which might be USBD_TIMEOUT. */ 2339 xfer->status = status; 2340 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2341 xfer->hcflags |= UXFER_ABORTWAIT; 2342 while (xfer->hcflags & UXFER_ABORTING) 2343 cv_wait(&xfer->hccv, &sc->sc_lock); 2344 goto done; 2345 } 2346 xfer->hcflags |= UXFER_ABORTING; 2347 2348 /* 2349 * Step 1: Make interrupt routine and hardware ignore xfer. 2350 */ 2351 xfer->status = status; /* make software ignore it */ 2352 callout_stop(&xfer->timeout_handle); 2353 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2357 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2358 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2359 sizeof(sed->ed.ed_flags), 2360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2361 2362 /* 2363 * Step 2: Wait until we know hardware has finished any possible 2364 * use of the xfer. Also make sure the soft interrupt routine 2365 * has run. 2366 */ 2367 /* Hardware finishes in 1ms */ 2368 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2369 sc->sc_softwake = 1; 2370 usb_schedsoftintr(&sc->sc_bus); 2371 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2372 2373 /* 2374 * Step 3: Remove any vestiges of the xfer from the hardware. 2375 * The complication here is that the hardware may have executed 2376 * beyond the xfer we're trying to abort. So as we're scanning 2377 * the TDs of this xfer we check if the hardware points to 2378 * any of them. 2379 */ 2380 p = xfer->hcpriv; 2381 #ifdef DIAGNOSTIC 2382 if (p == NULL) { 2383 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2384 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2385 goto done; 2386 } 2387 #endif 2388 #ifdef OHCI_DEBUG 2389 if (ohcidebug > 1) { 2390 DPRINTF(("ohci_abort_xfer: sed=\n")); 2391 ohci_dump_ed(sc, sed); 2392 ohci_dump_tds(sc, p); 2393 } 2394 #endif 2395 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2396 hit = 0; 2397 for (; p->xfer == xfer; p = n) { 2398 hit |= headp == p->physaddr; 2399 n = p->nexttd; 2400 ohci_free_std(sc, p); 2401 } 2402 /* Zap headp register if hardware pointed inside the xfer. */ 2403 if (hit) { 2404 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2405 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2406 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2407 usb_syncmem(&sed->dma, 2408 sed->offs + offsetof(ohci_ed_t, ed_headp), 2409 sizeof(sed->ed.ed_headp), 2410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2411 } else { 2412 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2413 } 2414 2415 /* 2416 * Step 4: Turn on hardware again. 2417 */ 2418 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2419 sizeof(sed->ed.ed_flags), 2420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2421 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2422 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2423 sizeof(sed->ed.ed_flags), 2424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2425 2426 /* 2427 * Step 5: Execute callback. 2428 */ 2429 wake = xfer->hcflags & UXFER_ABORTWAIT; 2430 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2431 usb_transfer_complete(xfer); 2432 if (wake) 2433 cv_broadcast(&xfer->hccv); 2434 2435 done: 2436 KASSERT(mutex_owned(&sc->sc_lock)); 2437 } 2438 2439 /* 2440 * Data structures and routines to emulate the root hub. 2441 */ 2442 Static usb_device_descriptor_t ohci_devd = { 2443 USB_DEVICE_DESCRIPTOR_SIZE, 2444 UDESC_DEVICE, /* type */ 2445 {0x00, 0x01}, /* USB version */ 2446 UDCLASS_HUB, /* class */ 2447 UDSUBCLASS_HUB, /* subclass */ 2448 UDPROTO_FSHUB, /* protocol */ 2449 64, /* max packet */ 2450 {0},{0},{0x00,0x01}, /* device id */ 2451 1,2,0, /* string indicies */ 2452 1 /* # of configurations */ 2453 }; 2454 2455 Static const usb_config_descriptor_t ohci_confd = { 2456 USB_CONFIG_DESCRIPTOR_SIZE, 2457 UDESC_CONFIG, 2458 {USB_CONFIG_DESCRIPTOR_SIZE + 2459 USB_INTERFACE_DESCRIPTOR_SIZE + 2460 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2461 1, 2462 1, 2463 0, 2464 UC_ATTR_MBO | UC_SELF_POWERED, 2465 0 /* max power */ 2466 }; 2467 2468 Static const usb_interface_descriptor_t ohci_ifcd = { 2469 USB_INTERFACE_DESCRIPTOR_SIZE, 2470 UDESC_INTERFACE, 2471 0, 2472 0, 2473 1, 2474 UICLASS_HUB, 2475 UISUBCLASS_HUB, 2476 UIPROTO_FSHUB, 2477 0 2478 }; 2479 2480 Static const usb_endpoint_descriptor_t ohci_endpd = { 2481 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2482 .bDescriptorType = UDESC_ENDPOINT, 2483 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2484 .bmAttributes = UE_INTERRUPT, 2485 .wMaxPacketSize = {8, 0}, /* max packet */ 2486 .bInterval = 255, 2487 }; 2488 2489 Static const usb_hub_descriptor_t ohci_hubd = { 2490 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2491 .bDescriptorType = UDESC_HUB, 2492 }; 2493 2494 /* 2495 * Simulate a hardware hub by handling all the necessary requests. 2496 */ 2497 Static usbd_status 2498 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2499 { 2500 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2501 usbd_status err; 2502 2503 /* Insert last in queue. */ 2504 mutex_enter(&sc->sc_lock); 2505 err = usb_insert_transfer(xfer); 2506 mutex_exit(&sc->sc_lock); 2507 if (err) 2508 return (err); 2509 2510 /* Pipe isn't running, start first */ 2511 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2512 } 2513 2514 Static usbd_status 2515 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2516 { 2517 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2518 usb_device_request_t *req; 2519 void *buf = NULL; 2520 int port, i; 2521 int len, value, index, l, totlen = 0; 2522 usb_port_status_t ps; 2523 usb_hub_descriptor_t hubd; 2524 usbd_status err; 2525 u_int32_t v; 2526 2527 if (sc->sc_dying) 2528 return (USBD_IOERROR); 2529 2530 #ifdef DIAGNOSTIC 2531 if (!(xfer->rqflags & URQ_REQUEST)) 2532 /* XXX panic */ 2533 return (USBD_INVAL); 2534 #endif 2535 req = &xfer->request; 2536 2537 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2538 req->bmRequestType, req->bRequest)); 2539 2540 len = UGETW(req->wLength); 2541 value = UGETW(req->wValue); 2542 index = UGETW(req->wIndex); 2543 2544 if (len != 0) 2545 buf = KERNADDR(&xfer->dmabuf, 0); 2546 2547 #define C(x,y) ((x) | ((y) << 8)) 2548 switch(C(req->bRequest, req->bmRequestType)) { 2549 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2550 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2551 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2552 /* 2553 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2554 * for the integrated root hub. 2555 */ 2556 break; 2557 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2558 if (len > 0) { 2559 *(u_int8_t *)buf = sc->sc_conf; 2560 totlen = 1; 2561 } 2562 break; 2563 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2564 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2565 if (len == 0) 2566 break; 2567 switch(value >> 8) { 2568 case UDESC_DEVICE: 2569 if ((value & 0xff) != 0) { 2570 err = USBD_IOERROR; 2571 goto ret; 2572 } 2573 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2574 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2575 memcpy(buf, &ohci_devd, l); 2576 break; 2577 case UDESC_CONFIG: 2578 if ((value & 0xff) != 0) { 2579 err = USBD_IOERROR; 2580 goto ret; 2581 } 2582 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2583 memcpy(buf, &ohci_confd, l); 2584 buf = (char *)buf + l; 2585 len -= l; 2586 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2587 totlen += l; 2588 memcpy(buf, &ohci_ifcd, l); 2589 buf = (char *)buf + l; 2590 len -= l; 2591 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2592 totlen += l; 2593 memcpy(buf, &ohci_endpd, l); 2594 break; 2595 case UDESC_STRING: 2596 #define sd ((usb_string_descriptor_t *)buf) 2597 switch (value & 0xff) { 2598 case 0: /* Language table */ 2599 totlen = usb_makelangtbl(sd, len); 2600 break; 2601 case 1: /* Vendor */ 2602 totlen = usb_makestrdesc(sd, len, 2603 sc->sc_vendor); 2604 break; 2605 case 2: /* Product */ 2606 totlen = usb_makestrdesc(sd, len, 2607 "OHCI root hub"); 2608 break; 2609 } 2610 #undef sd 2611 break; 2612 default: 2613 err = USBD_IOERROR; 2614 goto ret; 2615 } 2616 break; 2617 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2618 if (len > 0) { 2619 *(u_int8_t *)buf = 0; 2620 totlen = 1; 2621 } 2622 break; 2623 case C(UR_GET_STATUS, UT_READ_DEVICE): 2624 if (len > 1) { 2625 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2626 totlen = 2; 2627 } 2628 break; 2629 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2630 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2631 if (len > 1) { 2632 USETW(((usb_status_t *)buf)->wStatus, 0); 2633 totlen = 2; 2634 } 2635 break; 2636 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2637 if (value >= USB_MAX_DEVICES) { 2638 err = USBD_IOERROR; 2639 goto ret; 2640 } 2641 sc->sc_addr = value; 2642 break; 2643 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2644 if (value != 0 && value != 1) { 2645 err = USBD_IOERROR; 2646 goto ret; 2647 } 2648 sc->sc_conf = value; 2649 break; 2650 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2651 break; 2652 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2653 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2654 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2655 err = USBD_IOERROR; 2656 goto ret; 2657 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2658 break; 2659 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2660 break; 2661 /* Hub requests */ 2662 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2663 break; 2664 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2665 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2666 "port=%d feature=%d\n", 2667 index, value)); 2668 if (index < 1 || index > sc->sc_noport) { 2669 err = USBD_IOERROR; 2670 goto ret; 2671 } 2672 port = OHCI_RH_PORT_STATUS(index); 2673 switch(value) { 2674 case UHF_PORT_ENABLE: 2675 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2676 break; 2677 case UHF_PORT_SUSPEND: 2678 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2679 break; 2680 case UHF_PORT_POWER: 2681 /* Yes, writing to the LOW_SPEED bit clears power. */ 2682 OWRITE4(sc, port, UPS_LOW_SPEED); 2683 break; 2684 case UHF_C_PORT_CONNECTION: 2685 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2686 break; 2687 case UHF_C_PORT_ENABLE: 2688 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2689 break; 2690 case UHF_C_PORT_SUSPEND: 2691 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2692 break; 2693 case UHF_C_PORT_OVER_CURRENT: 2694 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2695 break; 2696 case UHF_C_PORT_RESET: 2697 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2698 break; 2699 default: 2700 err = USBD_IOERROR; 2701 goto ret; 2702 } 2703 switch(value) { 2704 case UHF_C_PORT_CONNECTION: 2705 case UHF_C_PORT_ENABLE: 2706 case UHF_C_PORT_SUSPEND: 2707 case UHF_C_PORT_OVER_CURRENT: 2708 case UHF_C_PORT_RESET: 2709 /* Enable RHSC interrupt if condition is cleared. */ 2710 if ((OREAD4(sc, port) >> 16) == 0) 2711 ohci_rhsc_enable(sc); 2712 break; 2713 default: 2714 break; 2715 } 2716 break; 2717 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2718 if (len == 0) 2719 break; 2720 if ((value & 0xff) != 0) { 2721 err = USBD_IOERROR; 2722 goto ret; 2723 } 2724 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2725 hubd = ohci_hubd; 2726 hubd.bNbrPorts = sc->sc_noport; 2727 USETW(hubd.wHubCharacteristics, 2728 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2729 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2730 /* XXX overcurrent */ 2731 ); 2732 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2733 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2734 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2735 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2736 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2737 l = min(len, hubd.bDescLength); 2738 totlen = l; 2739 memcpy(buf, &hubd, l); 2740 break; 2741 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2742 if (len != 4) { 2743 err = USBD_IOERROR; 2744 goto ret; 2745 } 2746 memset(buf, 0, len); /* ? XXX */ 2747 totlen = len; 2748 break; 2749 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2750 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2751 index)); 2752 if (index < 1 || index > sc->sc_noport) { 2753 err = USBD_IOERROR; 2754 goto ret; 2755 } 2756 if (len != 4) { 2757 err = USBD_IOERROR; 2758 goto ret; 2759 } 2760 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2761 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2762 v)); 2763 USETW(ps.wPortStatus, v); 2764 USETW(ps.wPortChange, v >> 16); 2765 l = min(len, sizeof ps); 2766 memcpy(buf, &ps, l); 2767 totlen = l; 2768 break; 2769 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2770 err = USBD_IOERROR; 2771 goto ret; 2772 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2773 break; 2774 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2775 if (index < 1 || index > sc->sc_noport) { 2776 err = USBD_IOERROR; 2777 goto ret; 2778 } 2779 port = OHCI_RH_PORT_STATUS(index); 2780 switch(value) { 2781 case UHF_PORT_ENABLE: 2782 OWRITE4(sc, port, UPS_PORT_ENABLED); 2783 break; 2784 case UHF_PORT_SUSPEND: 2785 OWRITE4(sc, port, UPS_SUSPEND); 2786 break; 2787 case UHF_PORT_RESET: 2788 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2789 index)); 2790 OWRITE4(sc, port, UPS_RESET); 2791 for (i = 0; i < 5; i++) { 2792 usb_delay_ms(&sc->sc_bus, 2793 USB_PORT_ROOT_RESET_DELAY); 2794 if (sc->sc_dying) { 2795 err = USBD_IOERROR; 2796 goto ret; 2797 } 2798 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2799 break; 2800 } 2801 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2802 index, OREAD4(sc, port))); 2803 break; 2804 case UHF_PORT_POWER: 2805 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2806 "%d\n", index)); 2807 OWRITE4(sc, port, UPS_PORT_POWER); 2808 break; 2809 default: 2810 err = USBD_IOERROR; 2811 goto ret; 2812 } 2813 break; 2814 default: 2815 err = USBD_IOERROR; 2816 goto ret; 2817 } 2818 xfer->actlen = totlen; 2819 err = USBD_NORMAL_COMPLETION; 2820 ret: 2821 xfer->status = err; 2822 mutex_enter(&sc->sc_lock); 2823 usb_transfer_complete(xfer); 2824 mutex_exit(&sc->sc_lock); 2825 return (USBD_IN_PROGRESS); 2826 } 2827 2828 /* Abort a root control request. */ 2829 Static void 2830 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2831 { 2832 /* Nothing to do, all transfers are synchronous. */ 2833 } 2834 2835 /* Close the root pipe. */ 2836 Static void 2837 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2838 { 2839 DPRINTF(("ohci_root_ctrl_close\n")); 2840 /* Nothing to do. */ 2841 } 2842 2843 Static usbd_status 2844 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2845 { 2846 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2847 usbd_status err; 2848 2849 /* Insert last in queue. */ 2850 mutex_enter(&sc->sc_lock); 2851 err = usb_insert_transfer(xfer); 2852 mutex_exit(&sc->sc_lock); 2853 if (err) 2854 return (err); 2855 2856 /* Pipe isn't running, start first */ 2857 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2858 } 2859 2860 Static usbd_status 2861 ohci_root_intr_start(usbd_xfer_handle xfer) 2862 { 2863 usbd_pipe_handle pipe = xfer->pipe; 2864 ohci_softc_t *sc = pipe->device->bus->hci_private; 2865 2866 if (sc->sc_dying) 2867 return (USBD_IOERROR); 2868 2869 mutex_enter(&sc->sc_lock); 2870 KASSERT(sc->sc_intrxfer == NULL); 2871 sc->sc_intrxfer = xfer; 2872 mutex_exit(&sc->sc_lock); 2873 2874 return (USBD_IN_PROGRESS); 2875 } 2876 2877 /* Abort a root interrupt request. */ 2878 Static void 2879 ohci_root_intr_abort(usbd_xfer_handle xfer) 2880 { 2881 #ifdef DIAGNOSTIC 2882 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2883 #endif 2884 2885 KASSERT(mutex_owned(&sc->sc_lock)); 2886 2887 if (xfer->pipe->intrxfer == xfer) { 2888 DPRINTF(("ohci_root_intr_abort: remove\n")); 2889 xfer->pipe->intrxfer = NULL; 2890 } 2891 xfer->status = USBD_CANCELLED; 2892 usb_transfer_complete(xfer); 2893 } 2894 2895 /* Close the root pipe. */ 2896 Static void 2897 ohci_root_intr_close(usbd_pipe_handle pipe) 2898 { 2899 ohci_softc_t *sc = pipe->device->bus->hci_private; 2900 2901 KASSERT(mutex_owned(&sc->sc_lock)); 2902 2903 DPRINTF(("ohci_root_intr_close\n")); 2904 2905 sc->sc_intrxfer = NULL; 2906 } 2907 2908 /************************/ 2909 2910 Static usbd_status 2911 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2912 { 2913 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2914 usbd_status err; 2915 2916 /* Insert last in queue. */ 2917 mutex_enter(&sc->sc_lock); 2918 err = usb_insert_transfer(xfer); 2919 mutex_exit(&sc->sc_lock); 2920 if (err) 2921 return (err); 2922 2923 /* Pipe isn't running, start first */ 2924 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2925 } 2926 2927 Static usbd_status 2928 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2929 { 2930 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2931 usbd_status err; 2932 2933 if (sc->sc_dying) 2934 return (USBD_IOERROR); 2935 2936 #ifdef DIAGNOSTIC 2937 if (!(xfer->rqflags & URQ_REQUEST)) { 2938 /* XXX panic */ 2939 printf("ohci_device_ctrl_transfer: not a request\n"); 2940 return (USBD_INVAL); 2941 } 2942 #endif 2943 2944 mutex_enter(&sc->sc_lock); 2945 err = ohci_device_request(xfer); 2946 mutex_exit(&sc->sc_lock); 2947 if (err) 2948 return (err); 2949 2950 if (sc->sc_bus.use_polling) 2951 ohci_waitintr(sc, xfer); 2952 return (USBD_IN_PROGRESS); 2953 } 2954 2955 /* Abort a device control request. */ 2956 Static void 2957 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2958 { 2959 #ifdef DIAGNOSTIC 2960 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2961 #endif 2962 2963 KASSERT(mutex_owned(&sc->sc_lock)); 2964 2965 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2966 ohci_abort_xfer(xfer, USBD_CANCELLED); 2967 } 2968 2969 /* Close a device control pipe. */ 2970 Static void 2971 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2972 { 2973 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2974 ohci_softc_t *sc = pipe->device->bus->hci_private; 2975 2976 KASSERT(mutex_owned(&sc->sc_lock)); 2977 2978 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2979 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2980 ohci_free_std(sc, opipe->tail.td); 2981 } 2982 2983 /************************/ 2984 2985 Static void 2986 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2987 { 2988 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2989 ohci_softc_t *sc = pipe->device->bus->hci_private; 2990 2991 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2992 } 2993 2994 Static void 2995 ohci_noop(usbd_pipe_handle pipe) 2996 { 2997 } 2998 2999 Static usbd_status 3000 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 3001 { 3002 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3003 usbd_status err; 3004 3005 /* Insert last in queue. */ 3006 mutex_enter(&sc->sc_lock); 3007 err = usb_insert_transfer(xfer); 3008 mutex_exit(&sc->sc_lock); 3009 if (err) 3010 return (err); 3011 3012 /* Pipe isn't running, start first */ 3013 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3014 } 3015 3016 Static usbd_status 3017 ohci_device_bulk_start(usbd_xfer_handle xfer) 3018 { 3019 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3020 usbd_device_handle dev = opipe->pipe.device; 3021 ohci_softc_t *sc = dev->bus->hci_private; 3022 int addr = dev->address; 3023 ohci_soft_td_t *data, *tail, *tdp; 3024 ohci_soft_ed_t *sed; 3025 int len, isread, endpt; 3026 usbd_status err; 3027 3028 if (sc->sc_dying) 3029 return (USBD_IOERROR); 3030 3031 #ifdef DIAGNOSTIC 3032 if (xfer->rqflags & URQ_REQUEST) { 3033 /* XXX panic */ 3034 printf("ohci_device_bulk_start: a request\n"); 3035 return (USBD_INVAL); 3036 } 3037 #endif 3038 3039 mutex_enter(&sc->sc_lock); 3040 3041 len = xfer->length; 3042 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3043 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3044 sed = opipe->sed; 3045 3046 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3047 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3048 endpt)); 3049 3050 opipe->u.bulk.isread = isread; 3051 opipe->u.bulk.length = len; 3052 3053 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3055 /* Update device address */ 3056 sed->ed.ed_flags = HTOO32( 3057 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3058 OHCI_ED_SET_FA(addr)); 3059 3060 /* Allocate a chain of new TDs (including a new tail). */ 3061 data = opipe->tail.td; 3062 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3063 data, &tail); 3064 if (err) 3065 return err; 3066 3067 /* We want interrupt at the end of the transfer. */ 3068 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3069 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3070 tail->flags |= OHCI_CALL_DONE; 3071 tail = tail->nexttd; /* point at sentinel */ 3072 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3073 sizeof(tail->td.td_flags), 3074 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3075 if (err) { 3076 mutex_exit(&sc->sc_lock); 3077 return (err); 3078 } 3079 3080 tail->xfer = NULL; 3081 xfer->hcpriv = data; 3082 3083 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3084 "td_cbp=0x%08x td_be=0x%08x\n", 3085 (int)O32TOH(sed->ed.ed_flags), 3086 (int)O32TOH(data->td.td_flags), 3087 (int)O32TOH(data->td.td_cbp), 3088 (int)O32TOH(data->td.td_be))); 3089 3090 #ifdef OHCI_DEBUG 3091 if (ohcidebug > 5) { 3092 ohci_dump_ed(sc, sed); 3093 ohci_dump_tds(sc, data); 3094 } 3095 #endif 3096 3097 /* Insert ED in schedule */ 3098 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3099 tdp->xfer = xfer; 3100 } 3101 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3102 opipe->tail.td = tail; 3103 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3104 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3105 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3106 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3107 if (xfer->timeout && !sc->sc_bus.use_polling) { 3108 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3109 ohci_timeout, xfer); 3110 } 3111 mutex_exit(&sc->sc_lock); 3112 3113 #if 0 3114 /* This goes wrong if we are too slow. */ 3115 if (ohcidebug > 10) { 3116 delay(10000); 3117 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3118 OREAD4(sc, OHCI_COMMAND_STATUS))); 3119 ohci_dump_ed(sc, sed); 3120 ohci_dump_tds(sc, data); 3121 } 3122 #endif 3123 3124 return (USBD_IN_PROGRESS); 3125 } 3126 3127 Static void 3128 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3129 { 3130 #ifdef DIAGNOSTIC 3131 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3132 #endif 3133 3134 KASSERT(mutex_owned(&sc->sc_lock)); 3135 3136 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3137 ohci_abort_xfer(xfer, USBD_CANCELLED); 3138 } 3139 3140 /* 3141 * Close a device bulk pipe. 3142 */ 3143 Static void 3144 ohci_device_bulk_close(usbd_pipe_handle pipe) 3145 { 3146 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3147 ohci_softc_t *sc = pipe->device->bus->hci_private; 3148 3149 KASSERT(mutex_owned(&sc->sc_lock)); 3150 3151 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3152 ohci_close_pipe(pipe, sc->sc_bulk_head); 3153 ohci_free_std(sc, opipe->tail.td); 3154 } 3155 3156 /************************/ 3157 3158 Static usbd_status 3159 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3160 { 3161 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3162 usbd_status err; 3163 3164 /* Insert last in queue. */ 3165 mutex_enter(&sc->sc_lock); 3166 err = usb_insert_transfer(xfer); 3167 mutex_exit(&sc->sc_lock); 3168 if (err) 3169 return (err); 3170 3171 /* Pipe isn't running, start first */ 3172 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3173 } 3174 3175 Static usbd_status 3176 ohci_device_intr_start(usbd_xfer_handle xfer) 3177 { 3178 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3179 usbd_device_handle dev = opipe->pipe.device; 3180 ohci_softc_t *sc = dev->bus->hci_private; 3181 ohci_soft_ed_t *sed = opipe->sed; 3182 ohci_soft_td_t *data, *tail; 3183 int len, isread, endpt; 3184 3185 if (sc->sc_dying) 3186 return (USBD_IOERROR); 3187 3188 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3189 "flags=%d priv=%p\n", 3190 xfer, xfer->length, xfer->flags, xfer->priv)); 3191 3192 #ifdef DIAGNOSTIC 3193 if (xfer->rqflags & URQ_REQUEST) 3194 panic("ohci_device_intr_transfer: a request"); 3195 #endif 3196 3197 len = xfer->length; 3198 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3199 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3200 3201 data = opipe->tail.td; 3202 mutex_enter(&sc->sc_lock); 3203 tail = ohci_alloc_std(sc); 3204 mutex_exit(&sc->sc_lock); 3205 if (tail == NULL) 3206 return (USBD_NOMEM); 3207 tail->xfer = NULL; 3208 3209 data->td.td_flags = HTOO32( 3210 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3211 OHCI_TD_NOCC | 3212 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3213 if (xfer->flags & USBD_SHORT_XFER_OK) 3214 data->td.td_flags |= HTOO32(OHCI_TD_R); 3215 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3216 data->nexttd = tail; 3217 data->td.td_nexttd = HTOO32(tail->physaddr); 3218 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3219 data->len = len; 3220 data->xfer = xfer; 3221 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3222 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3223 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3224 xfer->hcpriv = data; 3225 3226 #ifdef OHCI_DEBUG 3227 if (ohcidebug > 5) { 3228 DPRINTF(("ohci_device_intr_transfer:\n")); 3229 ohci_dump_ed(sc, sed); 3230 ohci_dump_tds(sc, data); 3231 } 3232 #endif 3233 3234 /* Insert ED in schedule */ 3235 mutex_enter(&sc->sc_lock); 3236 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3237 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3238 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3239 opipe->tail.td = tail; 3240 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3241 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3242 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3243 3244 #if 0 3245 /* 3246 * This goes horribly wrong, printing thousands of descriptors, 3247 * because false references are followed due to the fact that the 3248 * TD is gone. 3249 */ 3250 if (ohcidebug > 5) { 3251 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3252 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3253 OREAD4(sc, OHCI_COMMAND_STATUS))); 3254 ohci_dump_ed(sc, sed); 3255 ohci_dump_tds(sc, data); 3256 } 3257 #endif 3258 mutex_exit(&sc->sc_lock); 3259 3260 return (USBD_IN_PROGRESS); 3261 } 3262 3263 /* Abort a device interrupt request. */ 3264 Static void 3265 ohci_device_intr_abort(usbd_xfer_handle xfer) 3266 { 3267 #ifdef DIAGNOSTIC 3268 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3269 #endif 3270 3271 KASSERT(mutex_owned(&sc->sc_lock)); 3272 3273 if (xfer->pipe->intrxfer == xfer) { 3274 DPRINTF(("ohci_device_intr_abort: remove\n")); 3275 xfer->pipe->intrxfer = NULL; 3276 } 3277 ohci_abort_xfer(xfer, USBD_CANCELLED); 3278 } 3279 3280 /* Close a device interrupt pipe. */ 3281 Static void 3282 ohci_device_intr_close(usbd_pipe_handle pipe) 3283 { 3284 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3285 ohci_softc_t *sc = pipe->device->bus->hci_private; 3286 int nslots = opipe->u.intr.nslots; 3287 int pos = opipe->u.intr.pos; 3288 int j; 3289 ohci_soft_ed_t *p, *sed = opipe->sed; 3290 3291 KASSERT(mutex_owned(&sc->sc_lock)); 3292 3293 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3294 pipe, nslots, pos)); 3295 usb_syncmem(&sed->dma, sed->offs, 3296 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3297 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3298 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3299 sizeof(sed->ed.ed_flags), 3300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3301 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3302 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3303 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3304 3305 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3306 continue; 3307 #ifdef DIAGNOSTIC 3308 if (p == NULL) 3309 panic("ohci_device_intr_close: ED not found"); 3310 #endif 3311 p->next = sed->next; 3312 p->ed.ed_nexted = sed->ed.ed_nexted; 3313 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3314 sizeof(p->ed.ed_nexted), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 3317 for (j = 0; j < nslots; j++) 3318 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3319 3320 ohci_free_std(sc, opipe->tail.td); 3321 ohci_free_sed(sc, opipe->sed); 3322 } 3323 3324 Static usbd_status 3325 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3326 { 3327 int i, j, best; 3328 u_int npoll, slow, shigh, nslots; 3329 u_int bestbw, bw; 3330 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3331 3332 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3333 if (ival == 0) { 3334 printf("ohci_setintr: 0 interval\n"); 3335 return (USBD_INVAL); 3336 } 3337 3338 npoll = OHCI_NO_INTRS; 3339 while (npoll > ival) 3340 npoll /= 2; 3341 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3342 3343 /* 3344 * We now know which level in the tree the ED must go into. 3345 * Figure out which slot has most bandwidth left over. 3346 * Slots to examine: 3347 * npoll 3348 * 1 0 3349 * 2 1 2 3350 * 4 3 4 5 6 3351 * 8 7 8 9 10 11 12 13 14 3352 * N (N-1) .. (N-1+N-1) 3353 */ 3354 slow = npoll-1; 3355 shigh = slow + npoll; 3356 nslots = OHCI_NO_INTRS / npoll; 3357 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3358 bw = 0; 3359 for (j = 0; j < nslots; j++) 3360 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3361 if (bw < bestbw) { 3362 best = i; 3363 bestbw = bw; 3364 } 3365 } 3366 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3367 best, slow, shigh, bestbw)); 3368 3369 mutex_enter(&sc->sc_lock); 3370 hsed = sc->sc_eds[best]; 3371 sed->next = hsed->next; 3372 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3373 sizeof(hsed->ed.ed_flags), 3374 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3375 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3376 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3377 sizeof(sed->ed.ed_flags), 3378 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3379 hsed->next = sed; 3380 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3381 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3382 sizeof(hsed->ed.ed_flags), 3383 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3384 mutex_exit(&sc->sc_lock); 3385 3386 for (j = 0; j < nslots; j++) 3387 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3388 opipe->u.intr.nslots = nslots; 3389 opipe->u.intr.pos = best; 3390 3391 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3392 return (USBD_NORMAL_COMPLETION); 3393 } 3394 3395 /***********************/ 3396 3397 usbd_status 3398 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3399 { 3400 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3401 usbd_status err; 3402 3403 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3404 3405 /* Put it on our queue, */ 3406 mutex_enter(&sc->sc_lock); 3407 err = usb_insert_transfer(xfer); 3408 mutex_exit(&sc->sc_lock); 3409 3410 /* bail out on error, */ 3411 if (err && err != USBD_IN_PROGRESS) 3412 return (err); 3413 3414 /* XXX should check inuse here */ 3415 3416 /* insert into schedule, */ 3417 ohci_device_isoc_enter(xfer); 3418 3419 /* and start if the pipe wasn't running */ 3420 if (!err) 3421 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3422 3423 return (err); 3424 } 3425 3426 void 3427 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3428 { 3429 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3430 usbd_device_handle dev = opipe->pipe.device; 3431 ohci_softc_t *sc = dev->bus->hci_private; 3432 ohci_soft_ed_t *sed = opipe->sed; 3433 struct iso *iso = &opipe->u.iso; 3434 ohci_soft_itd_t *sitd, *nsitd; 3435 ohci_physaddr_t buf, offs, noffs, bp0; 3436 int i, ncur, nframes; 3437 3438 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3439 "nframes=%d\n", 3440 iso->inuse, iso->next, xfer, xfer->nframes)); 3441 3442 if (sc->sc_dying) 3443 return; 3444 3445 if (iso->next == -1) { 3446 /* Not in use yet, schedule it a few frames ahead. */ 3447 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3448 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3449 iso->next)); 3450 } 3451 3452 sitd = opipe->tail.itd; 3453 buf = DMAADDR(&xfer->dmabuf, 0); 3454 bp0 = OHCI_PAGE(buf); 3455 offs = OHCI_PAGE_OFFSET(buf); 3456 nframes = xfer->nframes; 3457 xfer->hcpriv = sitd; 3458 for (i = ncur = 0; i < nframes; i++, ncur++) { 3459 noffs = offs + xfer->frlengths[i]; 3460 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3461 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3462 3463 /* Allocate next ITD */ 3464 mutex_enter(&sc->sc_lock); 3465 nsitd = ohci_alloc_sitd(sc); 3466 mutex_exit(&sc->sc_lock); 3467 if (nsitd == NULL) { 3468 /* XXX what now? */ 3469 printf("%s: isoc TD alloc failed\n", 3470 device_xname(sc->sc_dev)); 3471 return; 3472 } 3473 3474 /* Fill current ITD */ 3475 sitd->itd.itd_flags = HTOO32( 3476 OHCI_ITD_NOCC | 3477 OHCI_ITD_SET_SF(iso->next) | 3478 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3479 OHCI_ITD_SET_FC(ncur)); 3480 sitd->itd.itd_bp0 = HTOO32(bp0); 3481 sitd->nextitd = nsitd; 3482 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3483 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3484 sitd->xfer = xfer; 3485 sitd->flags = 0; 3486 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3487 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3488 3489 sitd = nsitd; 3490 iso->next = iso->next + ncur; 3491 bp0 = OHCI_PAGE(buf + offs); 3492 ncur = 0; 3493 } 3494 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3495 offs = noffs; 3496 } 3497 mutex_enter(&sc->sc_lock); 3498 nsitd = ohci_alloc_sitd(sc); 3499 mutex_exit(&sc->sc_lock); 3500 if (nsitd == NULL) { 3501 /* XXX what now? */ 3502 printf("%s: isoc TD alloc failed\n", 3503 device_xname(sc->sc_dev)); 3504 return; 3505 } 3506 /* Fixup last used ITD */ 3507 sitd->itd.itd_flags = HTOO32( 3508 OHCI_ITD_NOCC | 3509 OHCI_ITD_SET_SF(iso->next) | 3510 OHCI_ITD_SET_DI(0) | 3511 OHCI_ITD_SET_FC(ncur)); 3512 sitd->itd.itd_bp0 = HTOO32(bp0); 3513 sitd->nextitd = nsitd; 3514 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3515 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3516 sitd->xfer = xfer; 3517 sitd->flags = OHCI_CALL_DONE; 3518 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3520 3521 iso->next = iso->next + ncur; 3522 iso->inuse += nframes; 3523 3524 xfer->actlen = offs; /* XXX pretend we did it all */ 3525 3526 xfer->status = USBD_IN_PROGRESS; 3527 3528 #ifdef OHCI_DEBUG 3529 if (ohcidebug > 5) { 3530 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3531 O32TOH(sc->sc_hcca->hcca_frame_number))); 3532 ohci_dump_itds(sc, xfer->hcpriv); 3533 ohci_dump_ed(sc, sed); 3534 } 3535 #endif 3536 3537 mutex_enter(&sc->sc_lock); 3538 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3539 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3540 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3541 opipe->tail.itd = nsitd; 3542 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3543 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3544 sizeof(sed->ed.ed_flags), 3545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3546 mutex_exit(&sc->sc_lock); 3547 3548 #ifdef OHCI_DEBUG 3549 if (ohcidebug > 5) { 3550 delay(150000); 3551 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3552 O32TOH(sc->sc_hcca->hcca_frame_number))); 3553 ohci_dump_itds(sc, xfer->hcpriv); 3554 ohci_dump_ed(sc, sed); 3555 } 3556 #endif 3557 } 3558 3559 usbd_status 3560 ohci_device_isoc_start(usbd_xfer_handle xfer) 3561 { 3562 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3563 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3564 3565 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3566 3567 mutex_enter(&sc->sc_lock); 3568 3569 if (sc->sc_dying) { 3570 mutex_exit(&sc->sc_lock); 3571 return (USBD_IOERROR); 3572 } 3573 3574 #ifdef DIAGNOSTIC 3575 if (xfer->status != USBD_IN_PROGRESS) 3576 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3577 #endif 3578 3579 /* XXX anything to do? */ 3580 3581 mutex_exit(&sc->sc_lock); 3582 3583 return (USBD_IN_PROGRESS); 3584 } 3585 3586 void 3587 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3588 { 3589 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3590 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3591 ohci_soft_ed_t *sed; 3592 ohci_soft_itd_t *sitd; 3593 3594 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3595 3596 KASSERT(mutex_owned(&sc->sc_lock)); 3597 3598 /* Transfer is already done. */ 3599 if (xfer->status != USBD_NOT_STARTED && 3600 xfer->status != USBD_IN_PROGRESS) { 3601 printf("ohci_device_isoc_abort: early return\n"); 3602 goto done; 3603 } 3604 3605 /* Give xfer the requested abort code. */ 3606 xfer->status = USBD_CANCELLED; 3607 3608 sed = opipe->sed; 3609 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3610 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3611 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3612 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3613 sizeof(sed->ed.ed_flags), 3614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3615 3616 sitd = xfer->hcpriv; 3617 #ifdef DIAGNOSTIC 3618 if (sitd == NULL) { 3619 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3620 goto done; 3621 } 3622 #endif 3623 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3624 #ifdef DIAGNOSTIC 3625 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3626 sitd->isdone = 1; 3627 #endif 3628 } 3629 3630 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3631 3632 /* Run callback. */ 3633 usb_transfer_complete(xfer); 3634 3635 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3636 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3637 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3638 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3639 3640 done: 3641 KASSERT(mutex_owned(&sc->sc_lock)); 3642 } 3643 3644 void 3645 ohci_device_isoc_done(usbd_xfer_handle xfer) 3646 { 3647 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3648 } 3649 3650 usbd_status 3651 ohci_setup_isoc(usbd_pipe_handle pipe) 3652 { 3653 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3654 ohci_softc_t *sc = pipe->device->bus->hci_private; 3655 struct iso *iso = &opipe->u.iso; 3656 3657 iso->next = -1; 3658 iso->inuse = 0; 3659 3660 mutex_enter(&sc->sc_lock); 3661 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3662 mutex_exit(&sc->sc_lock); 3663 3664 return (USBD_NORMAL_COMPLETION); 3665 } 3666 3667 void 3668 ohci_device_isoc_close(usbd_pipe_handle pipe) 3669 { 3670 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3671 ohci_softc_t *sc = pipe->device->bus->hci_private; 3672 3673 KASSERT(mutex_owned(&sc->sc_lock)); 3674 3675 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3676 ohci_close_pipe(pipe, sc->sc_isoc_head); 3677 #ifdef DIAGNOSTIC 3678 opipe->tail.itd->isdone = 1; 3679 #endif 3680 ohci_free_sitd(sc, opipe->tail.itd); 3681 } 3682
Indexes created Fri Oct 03 02:09:57 GMT 2025