ohci.c revision 1.224.2.4
1 /* $NetBSD: ohci.c,v 1.224.2.4 2017/12/03 11:37:34 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.224.2.4 2017/12/03 11:37:34 jdolecek Exp $"); 45 46 #ifdef _KERNEL_OPT 47 #include "opt_usb.h" 48 #endif 49 50 #include <sys/param.h> 51 52 #include <sys/cpu.h> 53 #include <sys/device.h> 54 #include <sys/kernel.h> 55 #include <sys/kmem.h> 56 #include <sys/proc.h> 57 #include <sys/queue.h> 58 #include <sys/select.h> 59 #include <sys/sysctl.h> 60 #include <sys/systm.h> 61 62 #include <machine/endian.h> 63 64 #include <dev/usb/usb.h> 65 #include <dev/usb/usbdi.h> 66 #include <dev/usb/usbdivar.h> 67 #include <dev/usb/usb_mem.h> 68 #include <dev/usb/usb_quirks.h> 69 70 #include <dev/usb/ohcireg.h> 71 #include <dev/usb/ohcivar.h> 72 #include <dev/usb/usbroothub.h> 73 #include <dev/usb/usbhist.h> 74 75 #ifdef USB_DEBUG 76 #ifndef OHCI_DEBUG 77 #define ohcidebug 0 78 #else 79 static int ohcidebug = 10; 80 81 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 82 { 83 int err; 84 const struct sysctlnode *rnode; 85 const struct sysctlnode *cnode; 86 87 err = sysctl_createv(clog, 0, NULL, &rnode, 88 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 89 SYSCTL_DESCR("ohci global controls"), 90 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 91 92 if (err) 93 goto fail; 94 95 /* control debugging printfs */ 96 err = sysctl_createv(clog, 0, &rnode, &cnode, 97 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 98 "debug", SYSCTL_DESCR("Enable debugging output"), 99 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 100 if (err) 101 goto fail; 102 103 return; 104 fail: 105 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 106 } 107 108 #endif /* OHCI_DEBUG */ 109 #endif /* USB_DEBUG */ 110 111 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 112 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 113 #define OHCIHIST_FUNC() USBHIST_FUNC() 114 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 115 116 #if BYTE_ORDER == BIG_ENDIAN 117 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 118 #else 119 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 120 #endif 121 122 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 123 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 124 #define HTOO16(val) O16TOH(val) 125 #define HTOO32(val) O32TOH(val) 126 127 struct ohci_pipe; 128 129 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 130 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 131 132 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 133 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 134 Static void ohci_free_std_locked(ohci_softc_t *, ohci_soft_td_t *); 135 136 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 137 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 138 Static void ohci_free_sitd_locked(ohci_softc_t *, 139 ohci_soft_itd_t *); 140 141 Static int ohci_alloc_std_chain(ohci_softc_t *, struct usbd_xfer *, 142 int, int); 143 Static void ohci_free_stds(ohci_softc_t *, struct ohci_xfer *); 144 145 Static void ohci_reset_std_chain(ohci_softc_t *, struct usbd_xfer *, 146 int, int, ohci_soft_td_t *, ohci_soft_td_t **); 147 148 Static usbd_status ohci_open(struct usbd_pipe *); 149 Static void ohci_poll(struct usbd_bus *); 150 Static void ohci_softintr(void *); 151 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 152 Static void ohci_rhsc_softint(void *); 153 154 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 155 ohci_soft_ed_t *); 156 157 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 158 ohci_soft_ed_t *); 159 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 160 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 161 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 162 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 163 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 164 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 165 166 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 167 Static void ohci_device_isoc_enter(struct usbd_xfer *); 168 169 Static struct usbd_xfer * 170 ohci_allocx(struct usbd_bus *, unsigned int); 171 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 172 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 173 Static int ohci_roothub_ctrl(struct usbd_bus *, 174 usb_device_request_t *, void *, int); 175 176 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 177 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 178 Static void ohci_root_intr_abort(struct usbd_xfer *); 179 Static void ohci_root_intr_close(struct usbd_pipe *); 180 Static void ohci_root_intr_done(struct usbd_xfer *); 181 182 Static int ohci_device_ctrl_init(struct usbd_xfer *); 183 Static void ohci_device_ctrl_fini(struct usbd_xfer *); 184 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 186 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 187 Static void ohci_device_ctrl_close(struct usbd_pipe *); 188 Static void ohci_device_ctrl_done(struct usbd_xfer *); 189 190 Static int ohci_device_bulk_init(struct usbd_xfer *); 191 Static void ohci_device_bulk_fini(struct usbd_xfer *); 192 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 194 Static void ohci_device_bulk_abort(struct usbd_xfer *); 195 Static void ohci_device_bulk_close(struct usbd_pipe *); 196 Static void ohci_device_bulk_done(struct usbd_xfer *); 197 198 Static int ohci_device_intr_init(struct usbd_xfer *); 199 Static void ohci_device_intr_fini(struct usbd_xfer *); 200 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 201 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 202 Static void ohci_device_intr_abort(struct usbd_xfer *); 203 Static void ohci_device_intr_close(struct usbd_pipe *); 204 Static void ohci_device_intr_done(struct usbd_xfer *); 205 206 Static int ohci_device_isoc_init(struct usbd_xfer *); 207 Static void ohci_device_isoc_fini(struct usbd_xfer *); 208 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 209 Static void ohci_device_isoc_abort(struct usbd_xfer *); 210 Static void ohci_device_isoc_close(struct usbd_pipe *); 211 Static void ohci_device_isoc_done(struct usbd_xfer *); 212 213 Static usbd_status ohci_device_setintr(ohci_softc_t *, 214 struct ohci_pipe *, int); 215 216 Static void ohci_timeout(void *); 217 Static void ohci_timeout_task(void *); 218 Static void ohci_rhsc_enable(void *); 219 220 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 221 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 222 223 Static void ohci_device_clear_toggle(struct usbd_pipe *); 224 Static void ohci_noop(struct usbd_pipe *); 225 226 #ifdef OHCI_DEBUG 227 Static void ohci_dumpregs(ohci_softc_t *); 228 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 229 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 230 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 231 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 232 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 233 #endif 234 235 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 236 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 237 #define OWRITE1(sc, r, x) \ 238 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 239 #define OWRITE2(sc, r, x) \ 240 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 241 #define OWRITE4(sc, r, x) \ 242 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 243 244 static __inline uint32_t 245 OREAD4(ohci_softc_t *sc, bus_size_t r) 246 { 247 248 OBARR(sc); 249 return bus_space_read_4(sc->iot, sc->ioh, r); 250 } 251 252 /* Reverse the bits in a value 0 .. 31 */ 253 Static uint8_t revbits[OHCI_NO_INTRS] = 254 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 255 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 256 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 257 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 258 259 struct ohci_pipe { 260 struct usbd_pipe pipe; 261 ohci_soft_ed_t *sed; 262 union { 263 ohci_soft_td_t *td; 264 ohci_soft_itd_t *itd; 265 } tail; 266 /* Info needed for different pipe kinds. */ 267 union { 268 /* Control pipe */ 269 struct { 270 usb_dma_t reqdma; 271 } ctrl; 272 /* Interrupt pipe */ 273 struct { 274 int nslots; 275 int pos; 276 } intr; 277 /* Isochronous pipe */ 278 struct isoc { 279 int next, inuse; 280 } isoc; 281 }; 282 }; 283 284 Static const struct usbd_bus_methods ohci_bus_methods = { 285 .ubm_open = ohci_open, 286 .ubm_softint = ohci_softintr, 287 .ubm_dopoll = ohci_poll, 288 .ubm_allocx = ohci_allocx, 289 .ubm_freex = ohci_freex, 290 .ubm_getlock = ohci_get_lock, 291 .ubm_rhctrl = ohci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 295 .upm_transfer = ohci_root_intr_transfer, 296 .upm_start = ohci_root_intr_start, 297 .upm_abort = ohci_root_intr_abort, 298 .upm_close = ohci_root_intr_close, 299 .upm_cleartoggle = ohci_noop, 300 .upm_done = ohci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 304 .upm_init = ohci_device_ctrl_init, 305 .upm_fini = ohci_device_ctrl_fini, 306 .upm_transfer = ohci_device_ctrl_transfer, 307 .upm_start = ohci_device_ctrl_start, 308 .upm_abort = ohci_device_ctrl_abort, 309 .upm_close = ohci_device_ctrl_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_ctrl_done, 312 }; 313 314 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 315 .upm_init = ohci_device_intr_init, 316 .upm_fini = ohci_device_intr_fini, 317 .upm_transfer = ohci_device_intr_transfer, 318 .upm_start = ohci_device_intr_start, 319 .upm_abort = ohci_device_intr_abort, 320 .upm_close = ohci_device_intr_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_intr_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 326 .upm_init = ohci_device_bulk_init, 327 .upm_fini = ohci_device_bulk_fini, 328 .upm_transfer = ohci_device_bulk_transfer, 329 .upm_start = ohci_device_bulk_start, 330 .upm_abort = ohci_device_bulk_abort, 331 .upm_close = ohci_device_bulk_close, 332 .upm_cleartoggle = ohci_device_clear_toggle, 333 .upm_done = ohci_device_bulk_done, 334 }; 335 336 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 337 .upm_init = ohci_device_isoc_init, 338 .upm_fini = ohci_device_isoc_fini, 339 .upm_transfer = ohci_device_isoc_transfer, 340 .upm_abort = ohci_device_isoc_abort, 341 .upm_close = ohci_device_isoc_close, 342 .upm_cleartoggle = ohci_noop, 343 .upm_done = ohci_device_isoc_done, 344 }; 345 346 int 347 ohci_activate(device_t self, enum devact act) 348 { 349 struct ohci_softc *sc = device_private(self); 350 351 switch (act) { 352 case DVACT_DEACTIVATE: 353 sc->sc_dying = 1; 354 return 0; 355 default: 356 return EOPNOTSUPP; 357 } 358 } 359 360 void 361 ohci_childdet(device_t self, device_t child) 362 { 363 struct ohci_softc *sc = device_private(self); 364 365 KASSERT(sc->sc_child == child); 366 sc->sc_child = NULL; 367 } 368 369 int 370 ohci_detach(struct ohci_softc *sc, int flags) 371 { 372 int rv = 0; 373 374 if (sc->sc_child != NULL) 375 rv = config_detach(sc->sc_child, flags); 376 377 if (rv != 0) 378 return rv; 379 380 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 381 382 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 383 callout_destroy(&sc->sc_tmo_rhsc); 384 385 softint_disestablish(sc->sc_rhsc_si); 386 387 cv_destroy(&sc->sc_softwake_cv); 388 389 mutex_destroy(&sc->sc_lock); 390 mutex_destroy(&sc->sc_intr_lock); 391 392 if (sc->sc_hcca != NULL) 393 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 394 pool_cache_destroy(sc->sc_xferpool); 395 396 return rv; 397 } 398 399 ohci_soft_ed_t * 400 ohci_alloc_sed(ohci_softc_t *sc) 401 { 402 ohci_soft_ed_t *sed; 403 usbd_status err; 404 int i, offs; 405 usb_dma_t dma; 406 407 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 408 409 mutex_enter(&sc->sc_lock); 410 if (sc->sc_freeeds == NULL) { 411 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 412 mutex_exit(&sc->sc_lock); 413 414 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 415 OHCI_ED_ALIGN, &dma); 416 if (err) 417 return 0; 418 419 mutex_enter(&sc->sc_lock); 420 for (i = 0; i < OHCI_SED_CHUNK; i++) { 421 offs = i * OHCI_SED_SIZE; 422 sed = KERNADDR(&dma, offs); 423 sed->physaddr = DMAADDR(&dma, offs); 424 sed->dma = dma; 425 sed->offs = offs; 426 sed->next = sc->sc_freeeds; 427 sc->sc_freeeds = sed; 428 } 429 } 430 sed = sc->sc_freeeds; 431 sc->sc_freeeds = sed->next; 432 mutex_exit(&sc->sc_lock); 433 434 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 435 sed->next = 0; 436 return sed; 437 } 438 439 static inline void 440 ohci_free_sed_locked(ohci_softc_t *sc, ohci_soft_ed_t *sed) 441 { 442 443 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 444 445 sed->next = sc->sc_freeeds; 446 sc->sc_freeeds = sed; 447 } 448 449 void 450 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 451 { 452 453 mutex_enter(&sc->sc_lock); 454 ohci_free_sed_locked(sc, sed); 455 mutex_exit(&sc->sc_lock); 456 } 457 458 ohci_soft_td_t * 459 ohci_alloc_std(ohci_softc_t *sc) 460 { 461 ohci_soft_td_t *std; 462 usbd_status err; 463 int i, offs; 464 usb_dma_t dma; 465 466 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 467 468 mutex_enter(&sc->sc_lock); 469 if (sc->sc_freetds == NULL) { 470 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 471 mutex_exit(&sc->sc_lock); 472 473 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 474 OHCI_TD_ALIGN, &dma); 475 if (err) 476 return NULL; 477 478 mutex_enter(&sc->sc_lock); 479 for (i = 0; i < OHCI_STD_CHUNK; i++) { 480 offs = i * OHCI_STD_SIZE; 481 std = KERNADDR(&dma, offs); 482 std->physaddr = DMAADDR(&dma, offs); 483 std->dma = dma; 484 std->offs = offs; 485 std->nexttd = sc->sc_freetds; 486 sc->sc_freetds = std; 487 } 488 } 489 490 std = sc->sc_freetds; 491 sc->sc_freetds = std->nexttd; 492 mutex_exit(&sc->sc_lock); 493 494 memset(&std->td, 0, sizeof(ohci_td_t)); 495 std->nexttd = NULL; 496 std->xfer = NULL; 497 498 return std; 499 } 500 501 void 502 ohci_free_std_locked(ohci_softc_t *sc, ohci_soft_td_t *std) 503 { 504 505 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 506 507 std->nexttd = sc->sc_freetds; 508 sc->sc_freetds = std; 509 } 510 511 void 512 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 513 { 514 515 mutex_enter(&sc->sc_lock); 516 ohci_free_std_locked(sc, std); 517 mutex_exit(&sc->sc_lock); 518 } 519 520 Static int 521 ohci_alloc_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, int length, int rd) 522 { 523 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 524 uint16_t flags = xfer->ux_flags; 525 526 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 527 528 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 529 xfer->ux_pipe->up_dev->ud_addr, 530 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 531 length, xfer->ux_pipe->up_dev->ud_speed); 532 533 ASSERT_SLEEPABLE(); 534 KASSERT(length != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 535 536 size_t nstd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 537 nstd += ((length + OHCI_PAGE_SIZE - 1) / OHCI_PAGE_SIZE); 538 ox->ox_stds = kmem_zalloc(sizeof(ohci_soft_td_t *) * nstd, 539 KM_SLEEP); 540 ox->ox_nstd = nstd; 541 542 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, nstd, 0, 0); 543 544 for (size_t j = 0; j < ox->ox_nstd;) { 545 ohci_soft_td_t *cur = ohci_alloc_std(sc); 546 if (cur == NULL) 547 goto nomem; 548 549 ox->ox_stds[j++] = cur; 550 cur->xfer = xfer; 551 cur->flags = 0; 552 } 553 554 return 0; 555 556 nomem: 557 ohci_free_stds(sc, ox); 558 kmem_free(ox->ox_stds, sizeof(ohci_soft_td_t *) * nstd); 559 560 return ENOMEM; 561 } 562 563 Static void 564 ohci_free_stds(ohci_softc_t *sc, struct ohci_xfer *ox) 565 { 566 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 567 DPRINTF("ox=%#jx", (uintptr_t)ox, 0, 0, 0); 568 569 mutex_enter(&sc->sc_lock); 570 for (size_t i = 0; i < ox->ox_nstd; i++) { 571 ohci_soft_td_t *std = ox->ox_stds[i]; 572 if (std == NULL) 573 break; 574 ohci_free_std_locked(sc, std); 575 } 576 mutex_exit(&sc->sc_lock); 577 } 578 579 void 580 ohci_reset_std_chain(ohci_softc_t *sc, struct usbd_xfer *xfer, 581 int alen, int rd, ohci_soft_td_t *sp, ohci_soft_td_t **ep) 582 { 583 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 584 ohci_soft_td_t *next, *cur; 585 int len, curlen; 586 usb_dma_t *dma = &xfer->ux_dmabuf; 587 uint16_t flags = xfer->ux_flags; 588 589 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 590 DPRINTF("start len=%jd", alen, 0, 0, 0); 591 592 KASSERT(mutex_owned(&sc->sc_lock)); 593 594 DPRINTFN(8, "addr=%jd endpt=%jd len=%jd speed=%jd", 595 xfer->ux_pipe->up_dev->ud_addr, 596 UE_GET_ADDR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress), 597 alen, xfer->ux_pipe->up_dev->ud_speed); 598 599 KASSERT(sp); 600 601 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 602 603 /* 604 * Assign next for the len == 0 case where we don't go through the 605 * main loop. 606 */ 607 len = alen; 608 cur = next = sp; 609 610 usb_syncmem(dma, 0, len, 611 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 612 const uint32_t tdflags = HTOO32( 613 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 614 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 615 616 size_t curoffs = 0; 617 for (size_t j = 1; len != 0;) { 618 if (j == ox->ox_nstd) 619 next = NULL; 620 else 621 next = ox->ox_stds[j++]; 622 KASSERT(next != cur); 623 624 curlen = 0; 625 const ohci_physaddr_t sdataphys = DMAADDR(dma, curoffs); 626 ohci_physaddr_t edataphys = DMAADDR(dma, curoffs + len - 1); 627 628 const ohci_physaddr_t sphyspg = OHCI_PAGE(sdataphys); 629 ohci_physaddr_t ephyspg = OHCI_PAGE(edataphys); 630 /* 631 * The OHCI hardware can handle at most one page 632 * crossing per TD 633 */ 634 curlen = len; 635 if (sphyspg != ephyspg && 636 sphyspg + OHCI_PAGE_SIZE != ephyspg) { 637 /* must use multiple TDs, fill as much as possible. */ 638 curlen = 2 * OHCI_PAGE_SIZE - 639 OHCI_PAGE_OFFSET(sdataphys); 640 /* the length must be a multiple of the max size */ 641 curlen -= curlen % mps; 642 edataphys = DMAADDR(dma, curoffs + curlen - 1); 643 } 644 KASSERT(curlen != 0); 645 DPRINTFN(4, "sdataphys=0x%08jx edataphys=0x%08jx " 646 "len=%jd curlen=%jd", sdataphys, edataphys, len, curlen); 647 648 cur->td.td_flags = tdflags; 649 cur->td.td_cbp = HTOO32(sdataphys); 650 cur->td.td_be = HTOO32(edataphys); 651 cur->td.td_nexttd = (next != NULL) ? HTOO32(next->physaddr) : 0; 652 cur->nexttd = next; 653 cur->len = curlen; 654 cur->flags = OHCI_ADD_LEN; 655 cur->xfer = xfer; 656 ohci_hash_add_td(sc, cur); 657 658 curoffs += curlen; 659 len -= curlen; 660 661 if (len != 0) { 662 KASSERT(next != NULL); 663 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 664 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 665 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 666 667 cur = next; 668 } 669 } 670 cur->td.td_flags |= 671 HTOO32(xfer->ux_flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0); 672 673 if (!rd && 674 (flags & USBD_FORCE_SHORT_XFER) && 675 alen % mps == 0) { 676 /* We're adding a ZLP so sync the previous TD */ 677 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 678 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 679 680 /* Force a 0 length transfer at the end. */ 681 682 KASSERT(next != NULL); 683 cur = next; 684 685 cur->td.td_flags = tdflags; 686 cur->td.td_cbp = 0; /* indicate 0 length packet */ 687 cur->td.td_nexttd = 0; 688 cur->td.td_be = ~0; 689 cur->nexttd = NULL; 690 cur->len = 0; 691 cur->flags = 0; 692 cur->xfer = xfer; 693 ohci_hash_add_td(sc, cur); 694 695 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 696 } 697 698 /* Last TD gets usb_syncmem'ed by caller */ 699 *ep = cur; 700 } 701 702 ohci_soft_itd_t * 703 ohci_alloc_sitd(ohci_softc_t *sc) 704 { 705 ohci_soft_itd_t *sitd; 706 usbd_status err; 707 int i, offs; 708 usb_dma_t dma; 709 710 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 711 712 mutex_enter(&sc->sc_lock); 713 if (sc->sc_freeitds == NULL) { 714 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 715 mutex_exit(&sc->sc_lock); 716 717 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 718 OHCI_ITD_ALIGN, &dma); 719 if (err) 720 return NULL; 721 mutex_enter(&sc->sc_lock); 722 for (i = 0; i < OHCI_SITD_CHUNK; i++) { 723 offs = i * OHCI_SITD_SIZE; 724 sitd = KERNADDR(&dma, offs); 725 sitd->physaddr = DMAADDR(&dma, offs); 726 sitd->dma = dma; 727 sitd->offs = offs; 728 sitd->nextitd = sc->sc_freeitds; 729 sc->sc_freeitds = sitd; 730 } 731 } 732 733 sitd = sc->sc_freeitds; 734 sc->sc_freeitds = sitd->nextitd; 735 mutex_exit(&sc->sc_lock); 736 737 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 738 sitd->nextitd = NULL; 739 sitd->xfer = NULL; 740 741 #ifdef DIAGNOSTIC 742 sitd->isdone = true; 743 #endif 744 745 return sitd; 746 } 747 748 Static void 749 ohci_free_sitd_locked(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 750 { 751 752 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 753 DPRINTFN(10, "sitd=%#jx", (uintptr_t)sitd, 0, 0, 0); 754 755 KASSERT(sitd->isdone); 756 #ifdef DIAGNOSTIC 757 /* Warn double free */ 758 sitd->isdone = false; 759 #endif 760 761 sitd->nextitd = sc->sc_freeitds; 762 sc->sc_freeitds = sitd; 763 } 764 765 void 766 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 767 { 768 769 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 ohci_free_sitd_locked(sc, sitd); 773 mutex_exit(&sc->sc_lock); 774 } 775 776 int 777 ohci_init(ohci_softc_t *sc) 778 { 779 ohci_soft_ed_t *sed, *psed; 780 usbd_status err; 781 int i; 782 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 783 784 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 785 786 aprint_normal_dev(sc->sc_dev, ""); 787 788 sc->sc_hcca = NULL; 789 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 790 791 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 792 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 793 cv_init(&sc->sc_softwake_cv, "ohciab"); 794 795 sc->sc_rhsc_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 796 ohci_rhsc_softint, sc); 797 798 for (i = 0; i < OHCI_HASH_SIZE; i++) 799 LIST_INIT(&sc->sc_hash_tds[i]); 800 for (i = 0; i < OHCI_HASH_SIZE; i++) 801 LIST_INIT(&sc->sc_hash_itds[i]); 802 803 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 804 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 805 806 rev = OREAD4(sc, OHCI_REVISION); 807 aprint_normal("OHCI version %d.%d%s\n", 808 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 809 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 810 811 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 812 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 813 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 814 return -1; 815 } 816 sc->sc_bus.ub_revision = USBREV_1_0; 817 sc->sc_bus.ub_usedma = true; 818 819 /* XXX determine alignment by R/W */ 820 /* Allocate the HCCA area. */ 821 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 822 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 823 if (err) { 824 sc->sc_hcca = NULL; 825 return err; 826 } 827 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 828 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 829 830 sc->sc_eintrs = OHCI_NORMAL_INTRS; 831 832 /* Allocate dummy ED that starts the control list. */ 833 sc->sc_ctrl_head = ohci_alloc_sed(sc); 834 if (sc->sc_ctrl_head == NULL) { 835 err = ENOMEM; 836 goto bad1; 837 } 838 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 839 840 /* Allocate dummy ED that starts the bulk list. */ 841 sc->sc_bulk_head = ohci_alloc_sed(sc); 842 if (sc->sc_bulk_head == NULL) { 843 err = ENOMEM; 844 goto bad2; 845 } 846 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 847 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 848 sizeof(sc->sc_bulk_head->ed), 849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 850 851 /* Allocate dummy ED that starts the isochronous list. */ 852 sc->sc_isoc_head = ohci_alloc_sed(sc); 853 if (sc->sc_isoc_head == NULL) { 854 err = ENOMEM; 855 goto bad3; 856 } 857 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 858 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 859 sizeof(sc->sc_isoc_head->ed), 860 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 861 862 /* Allocate all the dummy EDs that make up the interrupt tree. */ 863 for (i = 0; i < OHCI_NO_EDS; i++) { 864 sed = ohci_alloc_sed(sc); 865 if (sed == NULL) { 866 while (--i >= 0) 867 ohci_free_sed(sc, sc->sc_eds[i]); 868 err = ENOMEM; 869 goto bad4; 870 } 871 /* All ED fields are set to 0. */ 872 sc->sc_eds[i] = sed; 873 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 874 if (i != 0) 875 psed = sc->sc_eds[(i-1) / 2]; 876 else 877 psed= sc->sc_isoc_head; 878 sed->next = psed; 879 sed->ed.ed_nexted = HTOO32(psed->physaddr); 880 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 882 } 883 /* 884 * Fill HCCA interrupt table. The bit reversal is to get 885 * the tree set up properly to spread the interrupts. 886 */ 887 for (i = 0; i < OHCI_NO_INTRS; i++) 888 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 889 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 890 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 892 893 #ifdef OHCI_DEBUG 894 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 895 if (ohcidebug >= 15) { 896 for (i = 0; i < OHCI_NO_EDS; i++) { 897 DPRINTFN(15, "ed#%jd ", i, 0, 0, 0); 898 ohci_dump_ed(sc, sc->sc_eds[i]); 899 } 900 DPRINTFN(15, "iso", 0, 0, 0 ,0); 901 ohci_dump_ed(sc, sc->sc_isoc_head); 902 } 903 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 904 #endif 905 906 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 907 ctl = OREAD4(sc, OHCI_CONTROL); 908 rwc = ctl & OHCI_RWC; 909 fm = OREAD4(sc, OHCI_FM_INTERVAL); 910 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 911 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 912 913 /* Determine in what context we are running. */ 914 if (ctl & OHCI_IR) { 915 /* SMM active, request change */ 916 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 917 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 918 (OHCI_OC | OHCI_MIE)) 919 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 920 s = OREAD4(sc, OHCI_COMMAND_STATUS); 921 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 922 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 923 usb_delay_ms(&sc->sc_bus, 1); 924 ctl = OREAD4(sc, OHCI_CONTROL); 925 } 926 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 927 if ((ctl & OHCI_IR) == 0) { 928 aprint_error_dev(sc->sc_dev, 929 "SMM does not respond, resetting\n"); 930 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 931 goto reset; 932 } 933 #if 0 934 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 935 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 936 /* BIOS started controller. */ 937 DPRINTF("BIOS active", 0, 0, 0, 0); 938 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 939 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 940 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 941 } 942 #endif 943 } else { 944 DPRINTF("cold started", 0 ,0 ,0 ,0); 945 reset: 946 /* Controller was cold started. */ 947 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 948 } 949 950 /* 951 * This reset should not be necessary according to the OHCI spec, but 952 * without it some controllers do not start. 953 */ 954 DPRINTF("sc %#jx: resetting", (uintptr_t)sc, 0, 0, 0); 955 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 956 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 957 958 /* We now own the host controller and the bus has been reset. */ 959 960 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 961 /* Nominal time for a reset is 10 us. */ 962 for (i = 0; i < 10; i++) { 963 delay(10); 964 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 965 if (!hcr) 966 break; 967 } 968 if (hcr) { 969 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 970 err = EIO; 971 goto bad5; 972 } 973 #ifdef OHCI_DEBUG 974 if (ohcidebug >= 15) 975 ohci_dumpregs(sc); 976 #endif 977 978 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 979 980 /* Set up HC registers. */ 981 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 982 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 983 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 984 /* disable all interrupts and then switch on all desired interrupts */ 985 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 986 /* switch on desired functional features */ 987 ctl = OREAD4(sc, OHCI_CONTROL); 988 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 989 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 990 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 991 /* And finally start it! */ 992 OWRITE4(sc, OHCI_CONTROL, ctl); 993 994 /* 995 * The controller is now OPERATIONAL. Set a some final 996 * registers that should be set earlier, but that the 997 * controller ignores when in the SUSPEND state. 998 */ 999 ival = OHCI_GET_IVAL(fm); 1000 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 1001 fm |= OHCI_FSMPS(ival) | ival; 1002 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 1003 per = OHCI_PERIODIC(ival); /* 90% periodic */ 1004 OWRITE4(sc, OHCI_PERIODIC_START, per); 1005 1006 if (sc->sc_flags & OHCIF_SUPERIO) { 1007 /* no overcurrent protection */ 1008 desca |= OHCI_NOCP; 1009 /* 1010 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 1011 * that 1012 * - ports are always power switched 1013 * - don't wait for powered root hub port 1014 */ 1015 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 1016 } 1017 1018 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 1019 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 1020 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 1021 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 1022 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 1023 1024 /* 1025 * The AMD756 requires a delay before re-reading the register, 1026 * otherwise it will occasionally report 0 ports. 1027 */ 1028 sc->sc_noport = 0; 1029 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 1030 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 1031 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 1032 } 1033 1034 #ifdef OHCI_DEBUG 1035 if (ohcidebug >= 5) 1036 ohci_dumpregs(sc); 1037 #endif 1038 1039 /* Set up the bus struct. */ 1040 sc->sc_bus.ub_methods = &ohci_bus_methods; 1041 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 1042 1043 sc->sc_control = sc->sc_intre = 0; 1044 1045 /* Finally, turn on interrupts. */ 1046 DPRINTF("enabling %#jx", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 1047 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 1048 1049 return 0; 1050 1051 bad5: 1052 for (i = 0; i < OHCI_NO_EDS; i++) 1053 ohci_free_sed(sc, sc->sc_eds[i]); 1054 bad4: 1055 ohci_free_sed(sc, sc->sc_isoc_head); 1056 bad3: 1057 ohci_free_sed(sc, sc->sc_bulk_head); 1058 bad2: 1059 ohci_free_sed(sc, sc->sc_ctrl_head); 1060 bad1: 1061 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 1062 sc->sc_hcca = NULL; 1063 return err; 1064 } 1065 1066 struct usbd_xfer * 1067 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 1068 { 1069 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1070 struct usbd_xfer *xfer; 1071 1072 xfer = pool_cache_get(sc->sc_xferpool, PR_WAITOK); 1073 if (xfer != NULL) { 1074 memset(xfer, 0, sizeof(struct ohci_xfer)); 1075 #ifdef DIAGNOSTIC 1076 xfer->ux_state = XFER_BUSY; 1077 #endif 1078 } 1079 return xfer; 1080 } 1081 1082 void 1083 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1084 { 1085 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1086 1087 KASSERTMSG(xfer->ux_state == XFER_BUSY, 1088 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 1089 #ifdef DIAGNOSTIC 1090 xfer->ux_state = XFER_FREE; 1091 #endif 1092 pool_cache_put(sc->sc_xferpool, xfer); 1093 } 1094 1095 Static void 1096 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1097 { 1098 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1099 1100 *lock = &sc->sc_lock; 1101 } 1102 1103 /* 1104 * Shut down the controller when the system is going down. 1105 */ 1106 bool 1107 ohci_shutdown(device_t self, int flags) 1108 { 1109 ohci_softc_t *sc = device_private(self); 1110 1111 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1112 1113 DPRINTF("stopping the HC", 0, 0, 0, 0); 1114 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1115 return true; 1116 } 1117 1118 bool 1119 ohci_resume(device_t dv, const pmf_qual_t *qual) 1120 { 1121 ohci_softc_t *sc = device_private(dv); 1122 uint32_t ctl; 1123 1124 mutex_spin_enter(&sc->sc_intr_lock); 1125 sc->sc_bus.ub_usepolling++; 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 1128 /* Some broken BIOSes do not recover these values */ 1129 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1130 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1131 sc->sc_ctrl_head->physaddr); 1132 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1133 sc->sc_bulk_head->physaddr); 1134 if (sc->sc_intre) 1135 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1136 (OHCI_ALL_INTRS | OHCI_MIE)); 1137 if (sc->sc_control) 1138 ctl = sc->sc_control; 1139 else 1140 ctl = OREAD4(sc, OHCI_CONTROL); 1141 ctl |= OHCI_HCFS_RESUME; 1142 OWRITE4(sc, OHCI_CONTROL, ctl); 1143 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1144 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1145 OWRITE4(sc, OHCI_CONTROL, ctl); 1146 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1147 sc->sc_control = sc->sc_intre = 0; 1148 1149 mutex_spin_enter(&sc->sc_intr_lock); 1150 sc->sc_bus.ub_usepolling--; 1151 mutex_spin_exit(&sc->sc_intr_lock); 1152 1153 return true; 1154 } 1155 1156 bool 1157 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1158 { 1159 ohci_softc_t *sc = device_private(dv); 1160 uint32_t ctl; 1161 1162 mutex_spin_enter(&sc->sc_intr_lock); 1163 sc->sc_bus.ub_usepolling++; 1164 mutex_spin_exit(&sc->sc_intr_lock); 1165 1166 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1167 if (sc->sc_control == 0) { 1168 /* 1169 * Preserve register values, in case that BIOS 1170 * does not recover them. 1171 */ 1172 sc->sc_control = ctl; 1173 sc->sc_intre = OREAD4(sc, 1174 OHCI_INTERRUPT_ENABLE); 1175 } 1176 ctl |= OHCI_HCFS_SUSPEND; 1177 OWRITE4(sc, OHCI_CONTROL, ctl); 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 mutex_spin_enter(&sc->sc_intr_lock); 1181 sc->sc_bus.ub_usepolling--; 1182 mutex_spin_exit(&sc->sc_intr_lock); 1183 1184 return true; 1185 } 1186 1187 #ifdef OHCI_DEBUG 1188 void 1189 ohci_dumpregs(ohci_softc_t *sc) 1190 { 1191 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1192 1193 DPRINTF("rev=0x%08jx control=0x%08jx command=0x%08jx", 1194 OREAD4(sc, OHCI_REVISION), 1195 OREAD4(sc, OHCI_CONTROL), 1196 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1197 DPRINTF(" intrstat=0x%08jx intre=0x%08jx intrd=0x%08jx", 1198 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1199 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1200 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1201 DPRINTF(" hcca=0x%08jx percur=0x%08jx ctrlhd=0x%08jx", 1202 OREAD4(sc, OHCI_HCCA), 1203 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1204 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1205 DPRINTF(" ctrlcur=0x%08jx bulkhd=0x%08jx bulkcur=0x%08jx", 1206 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1207 OREAD4(sc, OHCI_BULK_HEAD_ED), 1208 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1209 DPRINTF(" done=0x%08jx fmival=0x%08jx fmrem=0x%08jx", 1210 OREAD4(sc, OHCI_DONE_HEAD), 1211 OREAD4(sc, OHCI_FM_INTERVAL), 1212 OREAD4(sc, OHCI_FM_REMAINING), 0); 1213 DPRINTF(" fmnum=0x%08jx perst=0x%08jx lsthrs=0x%08jx", 1214 OREAD4(sc, OHCI_FM_NUMBER), 1215 OREAD4(sc, OHCI_PERIODIC_START), 1216 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1217 DPRINTF(" desca=0x%08jx descb=0x%08jx stat=0x%08jx", 1218 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1219 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1220 OREAD4(sc, OHCI_RH_STATUS), 0); 1221 DPRINTF(" port1=0x%08jx port2=0x%08jx", 1222 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1223 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1224 DPRINTF(" HCCA: frame_number=0x%04jx done_head=0x%08jx", 1225 O32TOH(sc->sc_hcca->hcca_frame_number), 1226 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1227 } 1228 #endif 1229 1230 Static int ohci_intr1(ohci_softc_t *); 1231 1232 int 1233 ohci_intr(void *p) 1234 { 1235 ohci_softc_t *sc = p; 1236 int ret = 0; 1237 1238 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1239 1240 if (sc == NULL) 1241 return 0; 1242 1243 mutex_spin_enter(&sc->sc_intr_lock); 1244 1245 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1246 goto done; 1247 1248 /* If we get an interrupt while polling, then just ignore it. */ 1249 if (sc->sc_bus.ub_usepolling) { 1250 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1251 /* for level triggered intrs, should do something to ack */ 1252 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1253 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1254 1255 goto done; 1256 } 1257 1258 ret = ohci_intr1(sc); 1259 1260 done: 1261 mutex_spin_exit(&sc->sc_intr_lock); 1262 return ret; 1263 } 1264 1265 Static int 1266 ohci_intr1(ohci_softc_t *sc) 1267 { 1268 uint32_t intrs, eintrs; 1269 1270 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1271 1272 /* In case the interrupt occurs before initialization has completed. */ 1273 if (sc == NULL || sc->sc_hcca == NULL) { 1274 #ifdef DIAGNOSTIC 1275 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1276 #endif 1277 return 0; 1278 } 1279 1280 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1281 1282 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1283 if (!intrs) 1284 return 0; 1285 1286 /* Acknowledge */ 1287 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); 1288 eintrs = intrs & sc->sc_eintrs; 1289 DPRINTFN(7, "sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1290 DPRINTFN(7, "intrs=%#jx(%#jx) eintrs=%#jx(%#jx)", 1291 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1292 sc->sc_eintrs); 1293 1294 if (!eintrs) { 1295 return 0; 1296 } 1297 1298 if (eintrs & OHCI_SO) { 1299 sc->sc_overrun_cnt++; 1300 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1301 printf("%s: %u scheduling overruns\n", 1302 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1303 sc->sc_overrun_cnt = 0; 1304 } 1305 /* XXX do what */ 1306 eintrs &= ~OHCI_SO; 1307 } 1308 if (eintrs & OHCI_WDH) { 1309 /* 1310 * We block the interrupt below, and reenable it later from 1311 * ohci_softintr(). 1312 */ 1313 usb_schedsoftintr(&sc->sc_bus); 1314 } 1315 if (eintrs & OHCI_RD) { 1316 DPRINTFN(5, "resume detect sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1317 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1318 /* XXX process resume detect */ 1319 } 1320 if (eintrs & OHCI_UE) { 1321 DPRINTFN(5, "unrecoverable error sc=%#jx", (uintptr_t)sc, 0, 0, 0); 1322 printf("%s: unrecoverable error, controller halted\n", 1323 device_xname(sc->sc_dev)); 1324 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1325 /* XXX what else */ 1326 } 1327 if (eintrs & OHCI_RHSC) { 1328 /* 1329 * We block the interrupt below, and reenable it later from 1330 * a timeout. 1331 */ 1332 softint_schedule(sc->sc_rhsc_si); 1333 } 1334 1335 if (eintrs != 0) { 1336 /* Block unprocessed interrupts. */ 1337 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1338 sc->sc_eintrs &= ~eintrs; 1339 DPRINTF("sc %#jx blocking intrs 0x%jx", (uintptr_t)sc, 1340 eintrs, 0, 0); 1341 } 1342 1343 return 1; 1344 } 1345 1346 void 1347 ohci_rhsc_enable(void *v_sc) 1348 { 1349 ohci_softc_t *sc = v_sc; 1350 1351 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1352 DPRINTF("sc %#jx", (uintptr_t)sc, 0, 0, 0); 1353 mutex_spin_enter(&sc->sc_intr_lock); 1354 sc->sc_eintrs |= OHCI_RHSC; 1355 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1356 mutex_spin_exit(&sc->sc_intr_lock); 1357 } 1358 1359 #ifdef OHCI_DEBUG 1360 const char *ohci_cc_strs[] = { 1361 "NO_ERROR", 1362 "CRC", 1363 "BIT_STUFFING", 1364 "DATA_TOGGLE_MISMATCH", 1365 "STALL", 1366 "DEVICE_NOT_RESPONDING", 1367 "PID_CHECK_FAILURE", 1368 "UNEXPECTED_PID", 1369 "DATA_OVERRUN", 1370 "DATA_UNDERRUN", 1371 "BUFFER_OVERRUN", 1372 "BUFFER_UNDERRUN", 1373 "reserved", 1374 "reserved", 1375 "NOT_ACCESSED", 1376 "NOT_ACCESSED", 1377 }; 1378 #endif 1379 1380 void 1381 ohci_softintr(void *v) 1382 { 1383 struct usbd_bus *bus = v; 1384 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1385 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1386 ohci_soft_td_t *std, *sdone, *stdnext; 1387 struct usbd_xfer *xfer; 1388 struct ohci_pipe *opipe; 1389 int len, cc; 1390 int i, j, actlen, iframes, uedir; 1391 ohci_physaddr_t done; 1392 1393 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1394 1395 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1396 1397 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1398 sizeof(sc->sc_hcca->hcca_done_head), 1399 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1400 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1401 sc->sc_hcca->hcca_done_head = 0; 1402 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1403 sizeof(sc->sc_hcca->hcca_done_head), 1404 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1405 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1406 sc->sc_eintrs |= OHCI_WDH; 1407 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1408 1409 /* Reverse the done list. */ 1410 for (sdone = NULL, sidone = NULL; done != 0; ) { 1411 std = ohci_hash_find_td(sc, done); 1412 if (std != NULL) { 1413 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1415 std->dnext = sdone; 1416 done = O32TOH(std->td.td_nexttd); 1417 sdone = std; 1418 DPRINTFN(10, "add TD %#jx", (uintptr_t)std, 0, 0, 0); 1419 continue; 1420 } 1421 sitd = ohci_hash_find_itd(sc, done); 1422 if (sitd != NULL) { 1423 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1424 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1425 sitd->dnext = sidone; 1426 done = O32TOH(sitd->itd.itd_nextitd); 1427 sidone = sitd; 1428 DPRINTFN(5, "add ITD %#jx", (uintptr_t)sitd, 0, 0, 0); 1429 continue; 1430 } 1431 DPRINTFN(10, "addr %#jx not found", (uintptr_t)done, 0, 0, 0); 1432 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1433 (u_long)done); 1434 break; 1435 } 1436 1437 DPRINTFN(10, "sdone=%#jx sidone=%#jx", (uintptr_t)sdone, 1438 (uintptr_t)sidone, 0, 0); 1439 DPRINTFN(10, "--- TD dump start ---", 0, 0, 0, 0); 1440 #ifdef OHCI_DEBUG 1441 if (ohcidebug >= 10) { 1442 for (std = sdone; std; std = std->dnext) 1443 ohci_dump_td(sc, std); 1444 } 1445 #endif 1446 DPRINTFN(10, "--- TD dump end ---", 0, 0, 0, 0); 1447 1448 for (std = sdone; std; std = stdnext) { 1449 xfer = std->xfer; 1450 stdnext = std->dnext; 1451 DPRINTFN(10, "std=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)std, 1452 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1453 0); 1454 if (xfer == NULL) { 1455 /* 1456 * xfer == NULL: There seems to be no xfer associated 1457 * with this TD. It is tailp that happened to end up on 1458 * the done queue. 1459 * Shouldn't happen, but some chips are broken(?). 1460 */ 1461 continue; 1462 } 1463 if (xfer->ux_status == USBD_CANCELLED || 1464 xfer->ux_status == USBD_TIMEOUT) { 1465 DPRINTF("cancel/timeout %#jx", (uintptr_t)xfer, 0, 0, 1466 0); 1467 /* Handled by abort routine. */ 1468 continue; 1469 } 1470 callout_stop(&xfer->ux_callout); 1471 1472 len = std->len; 1473 if (std->td.td_cbp != 0) 1474 len -= O32TOH(std->td.td_be) - 1475 O32TOH(std->td.td_cbp) + 1; 1476 DPRINTFN(10, "len=%jd, flags=0x%jx", len, std->flags, 0, 0); 1477 if (std->flags & OHCI_ADD_LEN) 1478 xfer->ux_actlen += len; 1479 1480 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1481 if (cc == OHCI_CC_NO_ERROR) { 1482 ohci_hash_rem_td(sc, std); 1483 if (std->flags & OHCI_CALL_DONE) { 1484 xfer->ux_status = USBD_NORMAL_COMPLETION; 1485 usb_transfer_complete(xfer); 1486 } 1487 } else { 1488 /* 1489 * Endpoint is halted. First unlink all the TDs 1490 * belonging to the failed transfer, and then restart 1491 * the endpoint. 1492 */ 1493 ohci_soft_td_t *p, *n; 1494 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1495 1496 DPRINTFN(10, "error cc=%jd", cc, 0, 0, 0); 1497 1498 /* remove xfer's TDs from the hash */ 1499 for (p = std; p->xfer == xfer; p = n) { 1500 n = p->nexttd; 1501 ohci_hash_rem_td(sc, p); 1502 } 1503 1504 ohci_soft_ed_t *sed = opipe->sed; 1505 1506 /* clear halt and TD chain */ 1507 sed->ed.ed_headp = HTOO32(p->physaddr); 1508 usb_syncmem(&sed->dma, 1509 sed->offs + offsetof(ohci_ed_t, ed_headp), 1510 sizeof(sed->ed.ed_headp), 1511 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1512 1513 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1514 1515 if (cc == OHCI_CC_DATA_UNDERRUN) 1516 xfer->ux_status = USBD_NORMAL_COMPLETION; 1517 else if (cc == OHCI_CC_STALL) 1518 xfer->ux_status = USBD_STALLED; 1519 else 1520 xfer->ux_status = USBD_IOERROR; 1521 usb_transfer_complete(xfer); 1522 } 1523 } 1524 DPRINTFN(10, "--- ITD dump start ---", 0, 0, 0, 0); 1525 #ifdef OHCI_DEBUG 1526 if (ohcidebug >= 10) { 1527 for (sitd = sidone; sitd; sitd = sitd->dnext) 1528 ohci_dump_itd(sc, sitd); 1529 } 1530 #endif 1531 DPRINTFN(10, "--- ITD dump end ---", 0, 0, 0, 0); 1532 1533 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1534 xfer = sitd->xfer; 1535 sitdnext = sitd->dnext; 1536 DPRINTFN(1, "sitd=%#jx xfer=%#jx hcpriv=%#jx", (uintptr_t)sitd, 1537 (uintptr_t)xfer, (uintptr_t)(xfer ? xfer->ux_hcpriv : 0), 1538 0); 1539 if (xfer == NULL) 1540 continue; 1541 if (xfer->ux_status == USBD_CANCELLED || 1542 xfer->ux_status == USBD_TIMEOUT) { 1543 DPRINTF("cancel/timeout %#jx", 1544 (uintptr_t)xfer, 0, 0, 0); 1545 /* Handled by abort routine. */ 1546 continue; 1547 } 1548 KASSERT(!sitd->isdone); 1549 #ifdef DIAGNOSTIC 1550 sitd->isdone = true; 1551 #endif 1552 if (sitd->flags & OHCI_CALL_DONE) { 1553 ohci_soft_itd_t *next; 1554 1555 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1556 opipe->isoc.inuse -= xfer->ux_nframes; 1557 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1558 bEndpointAddress); 1559 xfer->ux_status = USBD_NORMAL_COMPLETION; 1560 actlen = 0; 1561 for (i = 0, sitd = xfer->ux_hcpriv;; 1562 sitd = next) { 1563 next = sitd->nextitd; 1564 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1565 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1566 xfer->ux_status = USBD_IOERROR; 1567 /* For input, update frlengths with actual */ 1568 /* XXX anything necessary for output? */ 1569 if (uedir == UE_DIR_IN && 1570 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1571 iframes = OHCI_ITD_GET_FC(O32TOH( 1572 sitd->itd.itd_flags)); 1573 for (j = 0; j < iframes; i++, j++) { 1574 len = O16TOH(sitd-> 1575 itd.itd_offset[j]); 1576 if ((OHCI_ITD_PSW_GET_CC(len) & 1577 OHCI_CC_NOT_ACCESSED_MASK) 1578 == OHCI_CC_NOT_ACCESSED) 1579 len = 0; 1580 else 1581 len = OHCI_ITD_PSW_LENGTH(len); 1582 xfer->ux_frlengths[i] = len; 1583 actlen += len; 1584 } 1585 } 1586 if (sitd->flags & OHCI_CALL_DONE) 1587 break; 1588 ohci_hash_rem_itd(sc, sitd); 1589 1590 } 1591 ohci_hash_rem_itd(sc, sitd); 1592 if (uedir == UE_DIR_IN && 1593 xfer->ux_status == USBD_NORMAL_COMPLETION) 1594 xfer->ux_actlen = actlen; 1595 xfer->ux_hcpriv = NULL; 1596 1597 usb_transfer_complete(xfer); 1598 } 1599 } 1600 1601 if (sc->sc_softwake) { 1602 sc->sc_softwake = 0; 1603 cv_broadcast(&sc->sc_softwake_cv); 1604 } 1605 1606 DPRINTFN(10, "done", 0, 0, 0, 0); 1607 } 1608 1609 void 1610 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1611 { 1612 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1613 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1614 int len = UGETW(xfer->ux_request.wLength); 1615 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1616 1617 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1618 DPRINTFN(10, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1619 1620 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1621 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1622 1623 if (len) 1624 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1625 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1626 usb_syncmem(&opipe->ctrl.reqdma, 0, 1627 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1628 } 1629 1630 void 1631 ohci_device_intr_done(struct usbd_xfer *xfer) 1632 { 1633 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1634 int isread = 1635 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1636 1637 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1638 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, 1639 xfer->ux_actlen, 0, 0); 1640 1641 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1642 1643 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1644 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1645 } 1646 1647 void 1648 ohci_device_bulk_done(struct usbd_xfer *xfer) 1649 { 1650 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1651 1652 int isread = 1653 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1654 1655 KASSERT(mutex_owned(&sc->sc_lock)); 1656 1657 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1658 DPRINTFN(10, "xfer=%#jx, actlen=%jd", (uintptr_t)xfer, xfer->ux_actlen, 1659 0, 0); 1660 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1661 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1662 } 1663 1664 Static void 1665 ohci_rhsc_softint(void *arg) 1666 { 1667 ohci_softc_t *sc = arg; 1668 1669 mutex_enter(&sc->sc_lock); 1670 1671 ohci_rhsc(sc, sc->sc_intrxfer); 1672 1673 /* Do not allow RHSC interrupts > 1 per second */ 1674 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1675 1676 mutex_exit(&sc->sc_lock); 1677 } 1678 1679 void 1680 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1681 { 1682 u_char *p; 1683 int i, m; 1684 int hstatus __unused; 1685 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1686 1687 KASSERT(mutex_owned(&sc->sc_lock)); 1688 1689 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1690 DPRINTF("sc=%#jx xfer=%#jx hstatus=0x%08jx", (uintptr_t)sc, 1691 (uintptr_t)xfer, hstatus, 0); 1692 1693 if (xfer == NULL) { 1694 /* Just ignore the change. */ 1695 return; 1696 } 1697 1698 p = xfer->ux_buf; 1699 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1700 memset(p, 0, xfer->ux_length); 1701 for (i = 1; i <= m; i++) { 1702 /* Pick out CHANGE bits from the status reg. */ 1703 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1704 p[i/8] |= 1 << (i%8); 1705 } 1706 DPRINTF("change=0x%02jx", *p, 0, 0, 0); 1707 xfer->ux_actlen = xfer->ux_length; 1708 xfer->ux_status = USBD_NORMAL_COMPLETION; 1709 1710 usb_transfer_complete(xfer); 1711 } 1712 1713 void 1714 ohci_root_intr_done(struct usbd_xfer *xfer) 1715 { 1716 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1717 1718 KASSERT(mutex_owned(&sc->sc_lock)); 1719 1720 KASSERT(sc->sc_intrxfer == xfer); 1721 sc->sc_intrxfer = NULL; 1722 } 1723 1724 void 1725 ohci_poll(struct usbd_bus *bus) 1726 { 1727 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1728 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1729 1730 #ifdef OHCI_DEBUG 1731 static int last; 1732 int new; 1733 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1734 if (new != last) { 1735 DPRINTFN(10, "intrs=0x%04jx", new, 0, 0, 0); 1736 last = new; 1737 } 1738 #endif 1739 sc->sc_eintrs |= OHCI_WDH; 1740 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1741 mutex_spin_enter(&sc->sc_intr_lock); 1742 ohci_intr1(sc); 1743 mutex_spin_exit(&sc->sc_intr_lock); 1744 } 1745 } 1746 1747 /* 1748 * Add an ED to the schedule. Called with USB lock held. 1749 */ 1750 Static void 1751 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1752 { 1753 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1754 DPRINTFN(8, "sed=%#jx head=%#jx", (uintptr_t)sed, (uintptr_t)head, 0, 1755 0); 1756 1757 KASSERT(mutex_owned(&sc->sc_lock)); 1758 1759 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1760 sizeof(head->ed.ed_nexted), 1761 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1762 sed->next = head->next; 1763 sed->ed.ed_nexted = head->ed.ed_nexted; 1764 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1765 sizeof(sed->ed.ed_nexted), 1766 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1767 head->next = sed; 1768 head->ed.ed_nexted = HTOO32(sed->physaddr); 1769 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1770 sizeof(head->ed.ed_nexted), 1771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1772 } 1773 1774 /* 1775 * Remove an ED from the schedule. Called with USB lock held. 1776 */ 1777 Static void 1778 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1779 { 1780 ohci_soft_ed_t *p; 1781 1782 KASSERT(mutex_owned(&sc->sc_lock)); 1783 1784 /* XXX */ 1785 for (p = head; p != NULL && p->next != sed; p = p->next) 1786 ; 1787 KASSERT(p != NULL); 1788 1789 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1790 sizeof(sed->ed.ed_nexted), 1791 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1792 p->next = sed->next; 1793 p->ed.ed_nexted = sed->ed.ed_nexted; 1794 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1795 sizeof(p->ed.ed_nexted), 1796 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1797 } 1798 1799 /* 1800 * When a transfer is completed the TD is added to the done queue by 1801 * the host controller. This queue is the processed by software. 1802 * Unfortunately the queue contains the physical address of the TD 1803 * and we have no simple way to translate this back to a kernel address. 1804 * To make the translation possible (and fast) we use a hash table of 1805 * TDs currently in the schedule. The physical address is used as the 1806 * hash value. 1807 */ 1808 1809 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1810 /* Called with USB lock held. */ 1811 void 1812 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1813 { 1814 int h = HASH(std->physaddr); 1815 1816 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1817 1818 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1819 } 1820 1821 /* Called with USB lock held. */ 1822 void 1823 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1824 { 1825 1826 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1827 1828 LIST_REMOVE(std, hnext); 1829 } 1830 1831 ohci_soft_td_t * 1832 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1833 { 1834 int h = HASH(a); 1835 ohci_soft_td_t *std; 1836 1837 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1838 std != NULL; 1839 std = LIST_NEXT(std, hnext)) 1840 if (std->physaddr == a) 1841 return std; 1842 return NULL; 1843 } 1844 1845 /* Called with USB lock held. */ 1846 void 1847 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1848 { 1849 int h = HASH(sitd->physaddr); 1850 1851 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1852 1853 KASSERT(mutex_owned(&sc->sc_lock)); 1854 1855 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", 1856 (uintptr_t)sitd, (u_long)sitd->physaddr, 0, 0); 1857 1858 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1859 } 1860 1861 /* Called with USB lock held. */ 1862 void 1863 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1864 { 1865 1866 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1867 1868 KASSERT(mutex_owned(&sc->sc_lock)); 1869 1870 DPRINTFN(10, "sitd=%#jx physaddr=0x%08jx", (uintptr_t)sitd, 1871 sitd->physaddr, 0, 0); 1872 1873 LIST_REMOVE(sitd, hnext); 1874 } 1875 1876 ohci_soft_itd_t * 1877 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1878 { 1879 int h = HASH(a); 1880 ohci_soft_itd_t *sitd; 1881 1882 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1883 sitd != NULL; 1884 sitd = LIST_NEXT(sitd, hnext)) 1885 if (sitd->physaddr == a) 1886 return sitd; 1887 return NULL; 1888 } 1889 1890 void 1891 ohci_timeout(void *addr) 1892 { 1893 struct usbd_xfer *xfer = addr; 1894 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1895 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1896 1897 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1898 DPRINTF("oxfer=%#jx", (uintptr_t)oxfer, 0, 0, 0); 1899 1900 if (sc->sc_dying) { 1901 mutex_enter(&sc->sc_lock); 1902 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1903 mutex_exit(&sc->sc_lock); 1904 return; 1905 } 1906 1907 /* Execute the abort in a process context. */ 1908 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1909 USB_TASKQ_MPSAFE); 1910 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1911 USB_TASKQ_HC); 1912 } 1913 1914 void 1915 ohci_timeout_task(void *addr) 1916 { 1917 struct usbd_xfer *xfer = addr; 1918 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1919 1920 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1921 1922 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 1923 1924 mutex_enter(&sc->sc_lock); 1925 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1926 mutex_exit(&sc->sc_lock); 1927 } 1928 1929 #ifdef OHCI_DEBUG 1930 void 1931 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1932 { 1933 for (; std; std = std->nexttd) { 1934 ohci_dump_td(sc, std); 1935 KASSERTMSG(std->nexttd == NULL || std != std->nexttd, 1936 "std %p next %p", std, std->nexttd); 1937 } 1938 } 1939 1940 void 1941 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1942 { 1943 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1944 1945 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1946 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1947 1948 uint32_t flags = O32TOH(std->td.td_flags); 1949 DPRINTF("TD(%#jx) at 0x%08jx:", (uintptr_t)std, std->physaddr, 0, 0); 1950 DPRINTF(" round=%jd DP=%jx DI=%jx T=%jx", 1951 !!(flags & OHCI_TD_R), 1952 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1953 OHCI_TD_GET_DI(flags), 1954 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1955 DPRINTF(" EC=%jd CC=%jd", OHCI_TD_GET_EC(flags), 1956 OHCI_TD_GET_CC(flags), 0, 0); 1957 DPRINTF(" td_cbp=0x%08jx td_nexttd=0x%08jx td_be=0x%08jx", 1958 (u_long)O32TOH(std->td.td_cbp), 1959 (u_long)O32TOH(std->td.td_nexttd), 1960 (u_long)O32TOH(std->td.td_be), 0); 1961 } 1962 1963 void 1964 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1965 { 1966 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1967 1968 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1969 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1970 1971 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1972 DPRINTF("ITD(%#jx) at 0x%08jx", (uintptr_t)sitd, sitd->physaddr, 0, 0); 1973 DPRINTF(" sf=%jd di=%jd fc=%jd cc=%jd", 1974 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1975 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1976 DPRINTF(" bp0=0x%08jx next=0x%08jx be=0x%08jx", 1977 O32TOH(sitd->itd.itd_bp0), 1978 O32TOH(sitd->itd.itd_nextitd), 1979 O32TOH(sitd->itd.itd_be), 0); 1980 CTASSERT(OHCI_ITD_NOFFSET == 8); 1981 DPRINTF(" offs[0] = 0x%04jx offs[1] = 0x%04jx " 1982 "offs[2] = 0x%04jx offs[3] = 0x%04jx", 1983 O16TOH(sitd->itd.itd_offset[0]), 1984 O16TOH(sitd->itd.itd_offset[1]), 1985 O16TOH(sitd->itd.itd_offset[2]), 1986 O16TOH(sitd->itd.itd_offset[3])); 1987 DPRINTF(" offs[4] = 0x%04jx offs[5] = 0x%04jx " 1988 "offs[6] = 0x%04jx offs[7] = 0x%04jx", 1989 O16TOH(sitd->itd.itd_offset[4]), 1990 O16TOH(sitd->itd.itd_offset[5]), 1991 O16TOH(sitd->itd.itd_offset[6]), 1992 O16TOH(sitd->itd.itd_offset[7])); 1993 } 1994 1995 void 1996 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1997 { 1998 for (; sitd; sitd = sitd->nextitd) 1999 ohci_dump_itd(sc, sitd); 2000 } 2001 2002 void 2003 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2004 { 2005 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2006 2007 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2008 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2009 2010 uint32_t flags = O32TOH(sed->ed.ed_flags); 2011 DPRINTF("ED(%#jx) at 0x%08jx:", (uintptr_t)sed, sed->physaddr, 0, 0); 2012 DPRINTF(" addr=%jd endpt=%jd maxp=%jd", 2013 OHCI_ED_GET_FA(flags), 2014 OHCI_ED_GET_EN(flags), 2015 OHCI_ED_GET_MAXP(flags), 2016 0); 2017 DPRINTF(" dir=%jd speed=%jd skip=%jd iso=%jd", 2018 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2019 !!(flags & OHCI_ED_SPEED), 2020 !!(flags & OHCI_ED_SKIP), 2021 !!(flags & OHCI_ED_FORMAT_ISO)); 2022 DPRINTF(" tailp=0x%08jx", (u_long)O32TOH(sed->ed.ed_tailp), 2023 0, 0, 0); 2024 DPRINTF(" headp=0x%08jx nexted=0x%08jx halted=%jd carry=%jd", 2025 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2026 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2027 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2028 } 2029 #endif 2030 2031 usbd_status 2032 ohci_open(struct usbd_pipe *pipe) 2033 { 2034 struct usbd_device *dev = pipe->up_dev; 2035 struct usbd_bus *bus = dev->ud_bus; 2036 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2037 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2038 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2039 uint8_t addr = dev->ud_addr; 2040 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2041 ohci_soft_ed_t *sed; 2042 ohci_soft_td_t *std; 2043 ohci_soft_itd_t *sitd; 2044 ohci_physaddr_t tdphys; 2045 uint32_t fmt; 2046 usbd_status err = USBD_NOMEM; 2047 int ival; 2048 2049 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2050 DPRINTFN(1, "pipe=%#jx, addr=%jd, endpt=%jd (%jd)", (uintptr_t)pipe, 2051 addr, ed->bEndpointAddress, bus->ub_rhaddr); 2052 2053 if (sc->sc_dying) { 2054 return USBD_IOERROR; 2055 } 2056 2057 std = NULL; 2058 sed = NULL; 2059 2060 if (addr == bus->ub_rhaddr) { 2061 switch (ed->bEndpointAddress) { 2062 case USB_CONTROL_ENDPOINT: 2063 pipe->up_methods = &roothub_ctrl_methods; 2064 break; 2065 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2066 pipe->up_methods = &ohci_root_intr_methods; 2067 break; 2068 default: 2069 err = USBD_INVAL; 2070 goto bad; 2071 } 2072 } else { 2073 sed = ohci_alloc_sed(sc); 2074 if (sed == NULL) 2075 goto bad; 2076 opipe->sed = sed; 2077 if (xfertype == UE_ISOCHRONOUS) { 2078 sitd = ohci_alloc_sitd(sc); 2079 if (sitd == NULL) 2080 goto bad; 2081 2082 opipe->tail.itd = sitd; 2083 tdphys = sitd->physaddr; 2084 fmt = OHCI_ED_FORMAT_ISO; 2085 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2086 fmt |= OHCI_ED_DIR_IN; 2087 else 2088 fmt |= OHCI_ED_DIR_OUT; 2089 } else { 2090 std = ohci_alloc_std(sc); 2091 if (std == NULL) 2092 goto bad; 2093 2094 opipe->tail.td = std; 2095 tdphys = std->physaddr; 2096 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2097 } 2098 sed->ed.ed_flags = HTOO32( 2099 OHCI_ED_SET_FA(addr) | 2100 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2101 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2102 fmt | 2103 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2104 sed->ed.ed_headp = HTOO32(tdphys | 2105 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2106 sed->ed.ed_tailp = HTOO32(tdphys); 2107 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2109 2110 switch (xfertype) { 2111 case UE_CONTROL: 2112 pipe->up_methods = &ohci_device_ctrl_methods; 2113 err = usb_allocmem(&sc->sc_bus, 2114 sizeof(usb_device_request_t), 2115 0, &opipe->ctrl.reqdma); 2116 if (err) 2117 goto bad; 2118 mutex_enter(&sc->sc_lock); 2119 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2120 mutex_exit(&sc->sc_lock); 2121 break; 2122 case UE_INTERRUPT: 2123 pipe->up_methods = &ohci_device_intr_methods; 2124 ival = pipe->up_interval; 2125 if (ival == USBD_DEFAULT_INTERVAL) 2126 ival = ed->bInterval; 2127 err = ohci_device_setintr(sc, opipe, ival); 2128 if (err) 2129 goto bad; 2130 break; 2131 case UE_ISOCHRONOUS: 2132 pipe->up_serialise = false; 2133 pipe->up_methods = &ohci_device_isoc_methods; 2134 return ohci_setup_isoc(pipe); 2135 case UE_BULK: 2136 pipe->up_methods = &ohci_device_bulk_methods; 2137 mutex_enter(&sc->sc_lock); 2138 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2139 mutex_exit(&sc->sc_lock); 2140 break; 2141 } 2142 } 2143 2144 return USBD_NORMAL_COMPLETION; 2145 2146 bad: 2147 if (std != NULL) { 2148 ohci_free_std(sc, std); 2149 } 2150 if (sed != NULL) 2151 ohci_free_sed(sc, sed); 2152 return err; 2153 2154 } 2155 2156 /* 2157 * Close a reqular pipe. 2158 * Assumes that there are no pending transactions. 2159 */ 2160 void 2161 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2162 { 2163 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2164 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2165 ohci_soft_ed_t *sed = opipe->sed; 2166 2167 KASSERT(mutex_owned(&sc->sc_lock)); 2168 2169 #ifdef DIAGNOSTIC 2170 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2171 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2172 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2173 ohci_soft_td_t *std; 2174 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2175 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2176 "tl=0x%x pipe=%p, std=%p\n", sed, 2177 (int)O32TOH(sed->ed.ed_headp), 2178 (int)O32TOH(sed->ed.ed_tailp), 2179 pipe, std); 2180 #ifdef OHCI_DEBUG 2181 usbd_dump_pipe(&opipe->pipe); 2182 ohci_dump_ed(sc, sed); 2183 if (std) 2184 ohci_dump_td(sc, std); 2185 #endif 2186 usb_delay_ms(&sc->sc_bus, 2); 2187 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2188 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2189 printf("ohci_close_pipe: pipe still not empty\n"); 2190 } 2191 #endif 2192 ohci_rem_ed(sc, sed, head); 2193 /* Make sure the host controller is not touching this ED */ 2194 usb_delay_ms(&sc->sc_bus, 1); 2195 pipe->up_endpoint->ue_toggle = 2196 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2197 ohci_free_sed_locked(sc, opipe->sed); 2198 } 2199 2200 /* 2201 * Abort a device request. 2202 * If this routine is called at splusb() it guarantees that the request 2203 * will be removed from the hardware scheduling and that the callback 2204 * for it will be called with USBD_CANCELLED status. 2205 * It's impossible to guarantee that the requested transfer will not 2206 * have happened since the hardware runs concurrently. 2207 * If the transaction has already happened we rely on the ordinary 2208 * interrupt processing to process it. 2209 * XXX This is most probably wrong. 2210 * XXXMRG this doesn't make sense anymore. 2211 */ 2212 void 2213 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2214 { 2215 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2216 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2217 ohci_soft_ed_t *sed = opipe->sed; 2218 ohci_soft_td_t *p, *n; 2219 ohci_physaddr_t headp; 2220 int hit; 2221 int wake; 2222 2223 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2224 DPRINTF("xfer=%#jx pipe=%#jx sed=%#jx", (uintptr_t)xfer, 2225 (uintptr_t)opipe, (uintptr_t)sed, 0); 2226 2227 KASSERT(mutex_owned(&sc->sc_lock)); 2228 ASSERT_SLEEPABLE(); 2229 2230 if (sc->sc_dying) { 2231 /* If we're dying, just do the software part. */ 2232 xfer->ux_status = status; /* make software ignore it */ 2233 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2234 usb_transfer_complete(xfer); 2235 return; 2236 } 2237 2238 /* 2239 * If an abort is already in progress then just wait for it to 2240 * complete and return. 2241 */ 2242 if (xfer->ux_hcflags & UXFER_ABORTING) { 2243 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2244 #ifdef DIAGNOSTIC 2245 if (status == USBD_TIMEOUT) 2246 printf("%s: TIMEOUT while aborting\n", __func__); 2247 #endif 2248 /* Override the status which might be USBD_TIMEOUT. */ 2249 xfer->ux_status = status; 2250 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2251 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2252 while (xfer->ux_hcflags & UXFER_ABORTING) 2253 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2254 goto done; 2255 } 2256 xfer->ux_hcflags |= UXFER_ABORTING; 2257 2258 /* 2259 * Step 1: Make interrupt routine and hardware ignore xfer. 2260 */ 2261 xfer->ux_status = status; /* make software ignore it */ 2262 callout_stop(&xfer->ux_callout); 2263 DPRINTFN(1, "stop ed=%#jx", (uintptr_t)sed, 0, 0, 0); 2264 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2265 sizeof(sed->ed.ed_flags), 2266 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2267 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2268 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2269 sizeof(sed->ed.ed_flags), 2270 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2271 2272 /* 2273 * Step 2: Wait until we know hardware has finished any possible 2274 * use of the xfer. Also make sure the soft interrupt routine 2275 * has run. 2276 */ 2277 /* Hardware finishes in 1ms */ 2278 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2279 sc->sc_softwake = 1; 2280 usb_schedsoftintr(&sc->sc_bus); 2281 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2282 2283 /* 2284 * Step 3: Remove any vestiges of the xfer from the hardware. 2285 * The complication here is that the hardware may have executed 2286 * beyond the xfer we're trying to abort. So as we're scanning 2287 * the TDs of this xfer we check if the hardware points to 2288 * any of them. 2289 */ 2290 p = xfer->ux_hcpriv; 2291 KASSERT(p); 2292 2293 #ifdef OHCI_DEBUG 2294 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2295 2296 if (ohcidebug >= 2) { 2297 DPRINTF("sed:", 0, 0, 0, 0); 2298 ohci_dump_ed(sc, sed); 2299 ohci_dump_tds(sc, p); 2300 } 2301 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2302 #endif 2303 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2304 hit = 0; 2305 for (; p->xfer == xfer; p = n) { 2306 hit |= headp == p->physaddr; 2307 n = p->nexttd; 2308 ohci_hash_rem_td(sc, p); 2309 } 2310 /* Zap headp register if hardware pointed inside the xfer. */ 2311 if (hit) { 2312 DPRINTFN(1, "set hd=0x%08jx, tl=0x%08jx", (int)p->physaddr, 2313 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2314 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2315 usb_syncmem(&sed->dma, 2316 sed->offs + offsetof(ohci_ed_t, ed_headp), 2317 sizeof(sed->ed.ed_headp), 2318 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2319 } else { 2320 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2321 } 2322 2323 /* 2324 * Step 4: Turn on hardware again. 2325 */ 2326 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2327 sizeof(sed->ed.ed_flags), 2328 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2329 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2330 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2331 sizeof(sed->ed.ed_flags), 2332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2333 2334 /* 2335 * Step 5: Execute callback. 2336 */ 2337 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2338 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2339 usb_transfer_complete(xfer); 2340 if (wake) 2341 cv_broadcast(&xfer->ux_hccv); 2342 2343 done: 2344 KASSERT(mutex_owned(&sc->sc_lock)); 2345 } 2346 2347 /* 2348 * Data structures and routines to emulate the root hub. 2349 */ 2350 Static int 2351 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2352 void *buf, int buflen) 2353 { 2354 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2355 usb_port_status_t ps; 2356 uint16_t len, value, index; 2357 int l, totlen = 0; 2358 int port, i; 2359 uint32_t v; 2360 2361 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2362 2363 if (sc->sc_dying) 2364 return -1; 2365 2366 DPRINTFN(4, "type=0x%02jx request=%02jx", req->bmRequestType, 2367 req->bRequest, 0, 0); 2368 2369 len = UGETW(req->wLength); 2370 value = UGETW(req->wValue); 2371 index = UGETW(req->wIndex); 2372 2373 #define C(x,y) ((x) | ((y) << 8)) 2374 switch (C(req->bRequest, req->bmRequestType)) { 2375 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2376 DPRINTFN(8, "wValue=0x%04jx", value, 0, 0, 0); 2377 if (len == 0) 2378 break; 2379 switch (value) { 2380 case C(0, UDESC_DEVICE): { 2381 usb_device_descriptor_t devd; 2382 2383 totlen = min(buflen, sizeof(devd)); 2384 memcpy(&devd, buf, totlen); 2385 USETW(devd.idVendor, sc->sc_id_vendor); 2386 memcpy(buf, &devd, totlen); 2387 break; 2388 } 2389 case C(1, UDESC_STRING): 2390 #define sd ((usb_string_descriptor_t *)buf) 2391 /* Vendor */ 2392 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2393 break; 2394 case C(2, UDESC_STRING): 2395 /* Product */ 2396 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2397 break; 2398 #undef sd 2399 default: 2400 /* default from usbroothub */ 2401 return buflen; 2402 } 2403 break; 2404 2405 /* Hub requests */ 2406 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2407 break; 2408 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2409 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%jd feature=%jd", 2410 index, value, 0, 0); 2411 if (index < 1 || index > sc->sc_noport) { 2412 return -1; 2413 } 2414 port = OHCI_RH_PORT_STATUS(index); 2415 switch(value) { 2416 case UHF_PORT_ENABLE: 2417 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2418 break; 2419 case UHF_PORT_SUSPEND: 2420 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2421 break; 2422 case UHF_PORT_POWER: 2423 /* Yes, writing to the LOW_SPEED bit clears power. */ 2424 OWRITE4(sc, port, UPS_LOW_SPEED); 2425 break; 2426 case UHF_C_PORT_CONNECTION: 2427 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2428 break; 2429 case UHF_C_PORT_ENABLE: 2430 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2431 break; 2432 case UHF_C_PORT_SUSPEND: 2433 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2434 break; 2435 case UHF_C_PORT_OVER_CURRENT: 2436 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2437 break; 2438 case UHF_C_PORT_RESET: 2439 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2440 break; 2441 default: 2442 return -1; 2443 } 2444 switch(value) { 2445 case UHF_C_PORT_CONNECTION: 2446 case UHF_C_PORT_ENABLE: 2447 case UHF_C_PORT_SUSPEND: 2448 case UHF_C_PORT_OVER_CURRENT: 2449 case UHF_C_PORT_RESET: 2450 /* Enable RHSC interrupt if condition is cleared. */ 2451 if ((OREAD4(sc, port) >> 16) == 0) 2452 ohci_rhsc_enable(sc); 2453 break; 2454 default: 2455 break; 2456 } 2457 break; 2458 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2459 if (len == 0) 2460 break; 2461 if ((value & 0xff) != 0) { 2462 return -1; 2463 } 2464 usb_hub_descriptor_t hubd; 2465 2466 totlen = min(buflen, sizeof(hubd)); 2467 memcpy(&hubd, buf, totlen); 2468 2469 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2470 hubd.bNbrPorts = sc->sc_noport; 2471 USETW(hubd.wHubCharacteristics, 2472 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2473 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2474 /* XXX overcurrent */ 2475 ); 2476 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2477 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2478 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2479 hubd.DeviceRemovable[i++] = (uint8_t)v; 2480 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2481 totlen = min(totlen, hubd.bDescLength); 2482 memcpy(buf, &hubd, totlen); 2483 break; 2484 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2485 if (len != 4) { 2486 return -1; 2487 } 2488 memset(buf, 0, len); /* ? XXX */ 2489 totlen = len; 2490 break; 2491 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2492 DPRINTFN(8, "get port status i=%jd", index, 0, 0, 0); 2493 if (index < 1 || index > sc->sc_noport) { 2494 return -1; 2495 } 2496 if (len != 4) { 2497 return -1; 2498 } 2499 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2500 DPRINTFN(8, "port status=0x%04jx", v, 0, 0, 0); 2501 USETW(ps.wPortStatus, v); 2502 USETW(ps.wPortChange, v >> 16); 2503 totlen = min(len, sizeof(ps)); 2504 memcpy(buf, &ps, totlen); 2505 break; 2506 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2507 return -1; 2508 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2509 break; 2510 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2511 if (index < 1 || index > sc->sc_noport) { 2512 return -1; 2513 } 2514 port = OHCI_RH_PORT_STATUS(index); 2515 switch(value) { 2516 case UHF_PORT_ENABLE: 2517 OWRITE4(sc, port, UPS_PORT_ENABLED); 2518 break; 2519 case UHF_PORT_SUSPEND: 2520 OWRITE4(sc, port, UPS_SUSPEND); 2521 break; 2522 case UHF_PORT_RESET: 2523 DPRINTFN(5, "reset port %jd", index, 0, 0, 0); 2524 OWRITE4(sc, port, UPS_RESET); 2525 for (i = 0; i < 5; i++) { 2526 usb_delay_ms(&sc->sc_bus, 2527 USB_PORT_ROOT_RESET_DELAY); 2528 if (sc->sc_dying) { 2529 return -1; 2530 } 2531 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2532 break; 2533 } 2534 DPRINTFN(8, "port %jd reset, status = 0x%04jx", index, 2535 OREAD4(sc, port), 0, 0); 2536 break; 2537 case UHF_PORT_POWER: 2538 DPRINTFN(2, "set port power %jd", index, 0, 0, 0); 2539 OWRITE4(sc, port, UPS_PORT_POWER); 2540 break; 2541 default: 2542 return -1; 2543 } 2544 break; 2545 default: 2546 /* default from usbroothub */ 2547 return buflen; 2548 } 2549 2550 return totlen; 2551 } 2552 2553 Static usbd_status 2554 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2555 { 2556 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2557 usbd_status err; 2558 2559 /* Insert last in queue. */ 2560 mutex_enter(&sc->sc_lock); 2561 err = usb_insert_transfer(xfer); 2562 mutex_exit(&sc->sc_lock); 2563 if (err) 2564 return err; 2565 2566 /* Pipe isn't running, start first */ 2567 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2568 } 2569 2570 Static usbd_status 2571 ohci_root_intr_start(struct usbd_xfer *xfer) 2572 { 2573 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2574 2575 if (sc->sc_dying) 2576 return USBD_IOERROR; 2577 2578 mutex_enter(&sc->sc_lock); 2579 KASSERT(sc->sc_intrxfer == NULL); 2580 sc->sc_intrxfer = xfer; 2581 mutex_exit(&sc->sc_lock); 2582 2583 return USBD_IN_PROGRESS; 2584 } 2585 2586 /* Abort a root interrupt request. */ 2587 Static void 2588 ohci_root_intr_abort(struct usbd_xfer *xfer) 2589 { 2590 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2591 2592 KASSERT(mutex_owned(&sc->sc_lock)); 2593 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2594 2595 sc->sc_intrxfer = NULL; 2596 2597 xfer->ux_status = USBD_CANCELLED; 2598 usb_transfer_complete(xfer); 2599 } 2600 2601 /* Close the root pipe. */ 2602 Static void 2603 ohci_root_intr_close(struct usbd_pipe *pipe) 2604 { 2605 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2606 2607 KASSERT(mutex_owned(&sc->sc_lock)); 2608 2609 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2610 2611 sc->sc_intrxfer = NULL; 2612 } 2613 2614 /************************/ 2615 2616 int 2617 ohci_device_ctrl_init(struct usbd_xfer *xfer) 2618 { 2619 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2620 usb_device_request_t *req = &xfer->ux_request; 2621 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2622 ohci_soft_td_t *stat, *setup; 2623 int isread = req->bmRequestType & UT_READ; 2624 int len = xfer->ux_bufsize; 2625 int err = ENOMEM; 2626 2627 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2628 2629 setup = ohci_alloc_std(sc); 2630 if (setup == NULL) { 2631 goto bad1; 2632 } 2633 stat = ohci_alloc_std(sc); 2634 if (stat == NULL) { 2635 goto bad2; 2636 } 2637 2638 ox->ox_setup = setup; 2639 ox->ox_stat = stat; 2640 ox->ox_nstd = 0; 2641 2642 /* Set up data transaction */ 2643 if (len != 0) { 2644 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2645 if (err) { 2646 goto bad3; 2647 } 2648 } 2649 return 0; 2650 2651 bad3: 2652 ohci_free_std(sc, stat); 2653 bad2: 2654 ohci_free_std(sc, setup); 2655 bad1: 2656 return err; 2657 } 2658 2659 void 2660 ohci_device_ctrl_fini(struct usbd_xfer *xfer) 2661 { 2662 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2663 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2664 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2665 2666 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2667 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2668 2669 mutex_enter(&sc->sc_lock); 2670 if (ox->ox_setup != opipe->tail.td) { 2671 ohci_free_std_locked(sc, ox->ox_setup); 2672 } 2673 for (size_t i = 0; i < ox->ox_nstd; i++) { 2674 ohci_soft_td_t *std = ox->ox_stds[i]; 2675 if (std == NULL) 2676 break; 2677 ohci_free_std_locked(sc, std); 2678 } 2679 ohci_free_std_locked(sc, ox->ox_stat); 2680 mutex_exit(&sc->sc_lock); 2681 2682 if (ox->ox_nstd) { 2683 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2684 kmem_free(ox->ox_stds, sz); 2685 } 2686 } 2687 2688 Static usbd_status 2689 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2690 { 2691 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2692 usbd_status err; 2693 2694 /* Insert last in queue. */ 2695 mutex_enter(&sc->sc_lock); 2696 err = usb_insert_transfer(xfer); 2697 mutex_exit(&sc->sc_lock); 2698 if (err) 2699 return err; 2700 2701 /* Pipe isn't running, start first */ 2702 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2703 } 2704 2705 Static usbd_status 2706 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2707 { 2708 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2709 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2710 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2711 usb_device_request_t *req = &xfer->ux_request; 2712 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2713 ohci_soft_td_t *setup, *stat, *next, *tail; 2714 ohci_soft_ed_t *sed; 2715 int isread; 2716 int len; 2717 2718 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2719 2720 if (sc->sc_dying) 2721 return USBD_IOERROR; 2722 2723 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2724 2725 isread = req->bmRequestType & UT_READ; 2726 len = UGETW(req->wLength); 2727 2728 DPRINTF("xfer=%#jx len=%jd, addr=%jd, endpt=%jd", (uintptr_t)xfer, len, 2729 dev->ud_addr, opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress); 2730 DPRINTF("type=0x%02jx, request=0x%02jx, wValue=0x%04jx, wIndex=0x%04jx", 2731 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2732 UGETW(req->wIndex)); 2733 2734 /* Need to take lock here for pipe->tail.td */ 2735 mutex_enter(&sc->sc_lock); 2736 2737 /* 2738 * Use the pipe "tail" TD as our first and loan our first TD to the 2739 * next transfer 2740 */ 2741 setup = opipe->tail.td; 2742 opipe->tail.td = ox->ox_setup; 2743 ox->ox_setup = setup; 2744 2745 stat = ox->ox_stat; 2746 2747 /* point at sentinel */ 2748 tail = opipe->tail.td; 2749 sed = opipe->sed; 2750 2751 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2752 "address ED %d pipe %d\n", 2753 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2754 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2755 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2756 "MPL ED %d pipe %d\n", 2757 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2758 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2759 2760 /* next will point to data if len != 0 */ 2761 next = stat; 2762 2763 /* Set up data transaction */ 2764 if (len != 0) { 2765 ohci_soft_td_t *std; 2766 ohci_soft_td_t *end; 2767 2768 next = ox->ox_stds[0]; 2769 ohci_reset_std_chain(sc, xfer, len, isread, next, &end); 2770 2771 end->td.td_nexttd = HTOO32(stat->physaddr); 2772 end->nexttd = stat; 2773 2774 usb_syncmem(&end->dma, end->offs, sizeof(end->td), 2775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2776 2777 usb_syncmem(&xfer->ux_dmabuf, 0, len, 2778 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2779 std = ox->ox_stds[0]; 2780 /* Start toggle at 1 and then use the carried toggle. */ 2781 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2782 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2783 usb_syncmem(&std->dma, 2784 std->offs + offsetof(ohci_td_t, td_flags), 2785 sizeof(std->td.td_flags), 2786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2787 } 2788 2789 DPRINTFN(8, "setup %#jx data %#jx stat %#jx tail %#jx", 2790 (uintptr_t)setup, 2791 (uintptr_t)(len != 0 ? ox->ox_stds[0] : NULL), (uintptr_t)stat, 2792 (uintptr_t)tail); 2793 KASSERT(opipe->tail.td == tail); 2794 2795 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2796 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2797 2798 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2799 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2800 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2801 setup->td.td_nexttd = HTOO32(next->physaddr); 2802 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2803 setup->nexttd = next; 2804 setup->len = 0; 2805 setup->xfer = xfer; 2806 setup->flags = 0; 2807 ohci_hash_add_td(sc, setup); 2808 2809 xfer->ux_hcpriv = setup; 2810 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2811 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2812 2813 stat->td.td_flags = HTOO32( 2814 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2815 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2816 stat->td.td_cbp = 0; 2817 stat->td.td_nexttd = HTOO32(tail->physaddr); 2818 stat->td.td_be = 0; 2819 stat->nexttd = tail; 2820 stat->flags = OHCI_CALL_DONE; 2821 stat->len = 0; 2822 stat->xfer = xfer; 2823 ohci_hash_add_td(sc, stat); 2824 2825 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2826 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2827 2828 memset(&tail->td, 0, sizeof(tail->td)); 2829 tail->nexttd = NULL; 2830 tail->xfer = NULL; 2831 2832 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 2833 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2834 2835 #ifdef OHCI_DEBUG 2836 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2837 if (ohcidebug >= 5) { 2838 ohci_dump_ed(sc, sed); 2839 ohci_dump_tds(sc, setup); 2840 } 2841 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2842 #endif 2843 2844 /* Insert ED in schedule */ 2845 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2846 usb_syncmem(&sed->dma, 2847 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2848 sizeof(sed->ed.ed_tailp), 2849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2850 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2851 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2852 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2853 ohci_timeout, xfer); 2854 } 2855 2856 DPRINTF("done", 0, 0, 0, 0); 2857 2858 mutex_exit(&sc->sc_lock); 2859 2860 return USBD_IN_PROGRESS; 2861 } 2862 2863 /* Abort a device control request. */ 2864 Static void 2865 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2866 { 2867 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2868 2869 KASSERT(mutex_owned(&sc->sc_lock)); 2870 2871 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2872 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 2873 ohci_abort_xfer(xfer, USBD_CANCELLED); 2874 } 2875 2876 /* Close a device control pipe. */ 2877 Static void 2878 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2879 { 2880 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2881 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2882 2883 KASSERT(mutex_owned(&sc->sc_lock)); 2884 2885 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2886 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 2887 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2888 ohci_free_std_locked(sc, opipe->tail.td); 2889 } 2890 2891 /************************/ 2892 2893 Static void 2894 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2895 { 2896 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2897 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2898 2899 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2900 } 2901 2902 Static void 2903 ohci_noop(struct usbd_pipe *pipe) 2904 { 2905 } 2906 2907 Static int 2908 ohci_device_bulk_init(struct usbd_xfer *xfer) 2909 { 2910 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2911 int len = xfer->ux_bufsize; 2912 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 2913 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2914 int err; 2915 2916 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2917 2918 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2919 2920 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2921 len, isread, xfer->ux_flags); 2922 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 2923 2924 /* Allocate a chain of new TDs (including a new tail). */ 2925 err = ohci_alloc_std_chain(sc, xfer, len, isread); 2926 if (err) 2927 return err; 2928 2929 return 0; 2930 } 2931 2932 Static void 2933 ohci_device_bulk_fini(struct usbd_xfer *xfer) 2934 { 2935 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2936 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2937 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2938 2939 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2940 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 2941 2942 mutex_enter(&sc->sc_lock); 2943 for (size_t i = 0; i < ox->ox_nstd; i++) { 2944 ohci_soft_td_t *std = ox->ox_stds[i]; 2945 if (std == NULL) 2946 break; 2947 if (std != opipe->tail.td) 2948 ohci_free_std_locked(sc, std); 2949 } 2950 mutex_exit(&sc->sc_lock); 2951 2952 if (ox->ox_nstd) { 2953 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 2954 kmem_free(ox->ox_stds, sz); 2955 } 2956 } 2957 2958 Static usbd_status 2959 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2960 { 2961 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2962 usbd_status err; 2963 2964 /* Insert last in queue. */ 2965 mutex_enter(&sc->sc_lock); 2966 err = usb_insert_transfer(xfer); 2967 mutex_exit(&sc->sc_lock); 2968 if (err) 2969 return err; 2970 2971 /* Pipe isn't running, start first */ 2972 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2973 } 2974 2975 Static usbd_status 2976 ohci_device_bulk_start(struct usbd_xfer *xfer) 2977 { 2978 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 2979 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2980 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2981 ohci_soft_td_t *last; 2982 ohci_soft_td_t *data, *tail, *tdp; 2983 ohci_soft_ed_t *sed; 2984 int len, isread, endpt; 2985 2986 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2987 2988 if (sc->sc_dying) 2989 return USBD_IOERROR; 2990 2991 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2992 2993 len = xfer->ux_length; 2994 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2995 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2996 sed = opipe->sed; 2997 2998 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 2999 len, isread, xfer->ux_flags); 3000 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3001 3002 mutex_enter(&sc->sc_lock); 3003 3004 /* 3005 * Use the pipe "tail" TD as our first and loan our first TD to the 3006 * next transfer 3007 */ 3008 data = opipe->tail.td; 3009 opipe->tail.td = ox->ox_stds[0]; 3010 ox->ox_stds[0] = data; 3011 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3012 3013 /* point at sentinel */ 3014 tail = opipe->tail.td; 3015 memset(&tail->td, 0, sizeof(tail->td)); 3016 tail->nexttd = NULL; 3017 tail->xfer = NULL; 3018 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3020 xfer->ux_hcpriv = data; 3021 3022 DPRINTFN(8, "xfer %#jx data %#jx tail %#jx", (uintptr_t)xfer, 3023 (uintptr_t)ox->ox_stds[0], (uintptr_t)tail, 0); 3024 KASSERT(opipe->tail.td == tail); 3025 3026 /* We want interrupt at the end of the transfer. */ 3027 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3028 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3029 last->td.td_nexttd = HTOO32(tail->physaddr); 3030 last->nexttd = tail; 3031 last->flags |= OHCI_CALL_DONE; 3032 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3033 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3034 3035 DPRINTFN(4, "ed_flags=0x%08jx td_flags=0x%08jx " 3036 "td_cbp=0x%08jx td_be=0x%08jx", 3037 (int)O32TOH(sed->ed.ed_flags), 3038 (int)O32TOH(data->td.td_flags), 3039 (int)O32TOH(data->td.td_cbp), 3040 (int)O32TOH(data->td.td_be)); 3041 3042 #ifdef OHCI_DEBUG 3043 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3044 if (ohcidebug >= 5) { 3045 ohci_dump_ed(sc, sed); 3046 ohci_dump_tds(sc, data); 3047 } 3048 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3049 #endif 3050 3051 /* Insert ED in schedule */ 3052 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3053 KASSERT(tdp->xfer == xfer); 3054 } 3055 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3057 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3058 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3059 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3060 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3061 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3062 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3063 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3064 ohci_timeout, xfer); 3065 } 3066 mutex_exit(&sc->sc_lock); 3067 3068 return USBD_IN_PROGRESS; 3069 } 3070 3071 Static void 3072 ohci_device_bulk_abort(struct usbd_xfer *xfer) 3073 { 3074 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3075 3076 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3077 3078 KASSERT(mutex_owned(&sc->sc_lock)); 3079 3080 DPRINTF("xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3081 ohci_abort_xfer(xfer, USBD_CANCELLED); 3082 } 3083 3084 /* 3085 * Close a device bulk pipe. 3086 */ 3087 Static void 3088 ohci_device_bulk_close(struct usbd_pipe *pipe) 3089 { 3090 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3091 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3092 3093 KASSERT(mutex_owned(&sc->sc_lock)); 3094 3095 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3096 3097 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3098 ohci_close_pipe(pipe, sc->sc_bulk_head); 3099 ohci_free_std_locked(sc, opipe->tail.td); 3100 } 3101 3102 /************************/ 3103 3104 Static int 3105 ohci_device_intr_init(struct usbd_xfer *xfer) 3106 { 3107 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3108 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3109 int len = xfer->ux_bufsize; 3110 int endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress;; 3111 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3112 int err; 3113 3114 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3115 3116 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3117 KASSERT(len != 0); 3118 3119 DPRINTFN(4, "xfer=%#jx len=%jd isread=%jd flags=%jd", (uintptr_t)xfer, 3120 len, isread, xfer->ux_flags); 3121 DPRINTFN(4, "endpt=%jd", endpt, 0, 0, 0); 3122 3123 ox->ox_nstd = 0; 3124 3125 err = ohci_alloc_std_chain(sc, xfer, len, isread); 3126 if (err) { 3127 return err; 3128 } 3129 3130 return 0; 3131 } 3132 3133 Static void 3134 ohci_device_intr_fini(struct usbd_xfer *xfer) 3135 { 3136 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3137 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3138 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3139 3140 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3141 DPRINTFN(8, "xfer %#jx nstd %jd", (uintptr_t)xfer, ox->ox_nstd, 0, 0); 3142 3143 mutex_enter(&sc->sc_lock); 3144 for (size_t i = 0; i < ox->ox_nstd; i++) { 3145 ohci_soft_td_t *std = ox->ox_stds[i]; 3146 if (std != NULL) 3147 break; 3148 if (std != opipe->tail.td) 3149 ohci_free_std_locked(sc, std); 3150 } 3151 mutex_exit(&sc->sc_lock); 3152 3153 if (ox->ox_nstd) { 3154 const size_t sz = sizeof(ohci_soft_td_t *) * ox->ox_nstd; 3155 kmem_free(ox->ox_stds, sz); 3156 } 3157 } 3158 3159 Static usbd_status 3160 ohci_device_intr_transfer(struct usbd_xfer *xfer) 3161 { 3162 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3163 usbd_status err; 3164 3165 /* Insert last in queue. */ 3166 mutex_enter(&sc->sc_lock); 3167 err = usb_insert_transfer(xfer); 3168 mutex_exit(&sc->sc_lock); 3169 if (err) 3170 return err; 3171 3172 /* Pipe isn't running, start first */ 3173 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3174 } 3175 3176 Static usbd_status 3177 ohci_device_intr_start(struct usbd_xfer *xfer) 3178 { 3179 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3180 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3181 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3182 ohci_soft_ed_t *sed = opipe->sed; 3183 ohci_soft_td_t *data, *last, *tail; 3184 int len, isread, endpt; 3185 3186 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3187 3188 if (sc->sc_dying) 3189 return USBD_IOERROR; 3190 3191 DPRINTFN(3, "xfer=%#jx len=%jd flags=%jd priv=%#jx", (uintptr_t)xfer, 3192 xfer->ux_length, xfer->ux_flags, (uintptr_t)xfer->ux_priv); 3193 3194 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3195 3196 len = xfer->ux_length; 3197 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3198 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3199 3200 mutex_enter(&sc->sc_lock); 3201 3202 /* 3203 * Use the pipe "tail" TD as our first and loan our first TD to the 3204 * next transfer. 3205 */ 3206 data = opipe->tail.td; 3207 opipe->tail.td = ox->ox_stds[0]; 3208 ox->ox_stds[0] = data; 3209 ohci_reset_std_chain(sc, xfer, len, isread, data, &last); 3210 3211 /* point at sentinel */ 3212 tail = opipe->tail.td; 3213 memset(&tail->td, 0, sizeof(tail->td)); 3214 tail->nexttd = NULL; 3215 tail->xfer = NULL; 3216 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->td), 3217 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3218 xfer->ux_hcpriv = data; 3219 3220 DPRINTFN(8, "data %#jx tail %#jx", (uintptr_t)ox->ox_stds[0], 3221 (uintptr_t)tail, 0, 0); 3222 KASSERT(opipe->tail.td == tail); 3223 3224 /* We want interrupt at the end of the transfer. */ 3225 last->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3226 last->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3227 3228 last->td.td_nexttd = HTOO32(tail->physaddr); 3229 last->nexttd = tail; 3230 last->flags |= OHCI_CALL_DONE; 3231 usb_syncmem(&last->dma, last->offs, sizeof(last->td), 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 3234 #ifdef OHCI_DEBUG 3235 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3236 if (ohcidebug >= 5) { 3237 ohci_dump_ed(sc, sed); 3238 ohci_dump_tds(sc, data); 3239 } 3240 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3241 #endif 3242 3243 /* Insert ED in schedule */ 3244 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3245 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3246 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3247 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3248 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3249 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3250 3251 mutex_exit(&sc->sc_lock); 3252 3253 return USBD_IN_PROGRESS; 3254 } 3255 3256 /* Abort a device interrupt request. */ 3257 Static void 3258 ohci_device_intr_abort(struct usbd_xfer *xfer) 3259 { 3260 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3261 3262 KASSERT(mutex_owned(&sc->sc_lock)); 3263 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3264 3265 ohci_abort_xfer(xfer, USBD_CANCELLED); 3266 } 3267 3268 /* Close a device interrupt pipe. */ 3269 Static void 3270 ohci_device_intr_close(struct usbd_pipe *pipe) 3271 { 3272 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3273 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3274 int nslots = opipe->intr.nslots; 3275 int pos = opipe->intr.pos; 3276 int j; 3277 ohci_soft_ed_t *p, *sed = opipe->sed; 3278 3279 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3280 3281 KASSERT(mutex_owned(&sc->sc_lock)); 3282 3283 DPRINTFN(1, "pipe=%#jx nslots=%jd pos=%jd", (uintptr_t)pipe, nslots, 3284 pos, 0); 3285 usb_syncmem(&sed->dma, sed->offs, 3286 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3287 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3288 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3289 sizeof(sed->ed.ed_flags), 3290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3291 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3292 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3293 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3294 3295 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3296 continue; 3297 KASSERT(p); 3298 p->next = sed->next; 3299 p->ed.ed_nexted = sed->ed.ed_nexted; 3300 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3301 sizeof(p->ed.ed_nexted), 3302 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3303 3304 for (j = 0; j < nslots; j++) 3305 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3306 3307 ohci_free_std_locked(sc, opipe->tail.td); 3308 ohci_free_sed_locked(sc, opipe->sed); 3309 } 3310 3311 Static usbd_status 3312 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3313 { 3314 int i, j, best; 3315 u_int npoll, slow, shigh, nslots; 3316 u_int bestbw, bw; 3317 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3318 3319 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3320 3321 DPRINTFN(2, "pipe=%#jx", (uintptr_t)opipe, 0, 0, 0); 3322 if (ival == 0) { 3323 printf("ohci_setintr: 0 interval\n"); 3324 return USBD_INVAL; 3325 } 3326 3327 npoll = OHCI_NO_INTRS; 3328 while (npoll > ival) 3329 npoll /= 2; 3330 DPRINTFN(2, "ival=%jd npoll=%jd", ival, npoll, 0, 0); 3331 3332 /* 3333 * We now know which level in the tree the ED must go into. 3334 * Figure out which slot has most bandwidth left over. 3335 * Slots to examine: 3336 * npoll 3337 * 1 0 3338 * 2 1 2 3339 * 4 3 4 5 6 3340 * 8 7 8 9 10 11 12 13 14 3341 * N (N-1) .. (N-1+N-1) 3342 */ 3343 slow = npoll-1; 3344 shigh = slow + npoll; 3345 nslots = OHCI_NO_INTRS / npoll; 3346 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3347 bw = 0; 3348 for (j = 0; j < nslots; j++) 3349 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3350 if (bw < bestbw) { 3351 best = i; 3352 bestbw = bw; 3353 } 3354 } 3355 DPRINTFN(2, "best=%jd(%jd..%jd) bestbw=%jd", best, slow, shigh, bestbw); 3356 3357 mutex_enter(&sc->sc_lock); 3358 hsed = sc->sc_eds[best]; 3359 sed->next = hsed->next; 3360 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3361 sizeof(hsed->ed.ed_flags), 3362 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3363 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3364 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3365 sizeof(sed->ed.ed_flags), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 hsed->next = sed; 3368 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3369 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3370 sizeof(hsed->ed.ed_flags), 3371 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3372 mutex_exit(&sc->sc_lock); 3373 3374 for (j = 0; j < nslots; j++) 3375 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3376 opipe->intr.nslots = nslots; 3377 opipe->intr.pos = best; 3378 3379 DPRINTFN(5, "returns %#jx", (uintptr_t)opipe, 0, 0, 0); 3380 return USBD_NORMAL_COMPLETION; 3381 } 3382 3383 /***********************/ 3384 3385 Static int 3386 ohci_device_isoc_init(struct usbd_xfer *xfer) 3387 { 3388 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3389 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3390 ohci_soft_itd_t *sitd; 3391 size_t i; 3392 int err; 3393 3394 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3395 3396 DPRINTFN(1, "xfer %#jx len %jd flags %jd", (uintptr_t)xfer, 3397 xfer->ux_length, xfer->ux_flags, 0); 3398 3399 const size_t nfsitd = 3400 (xfer->ux_nframes + OHCI_ITD_NOFFSET - 1) / OHCI_ITD_NOFFSET; 3401 const size_t nbsitd = xfer->ux_bufsize / OHCI_PAGE_SIZE; 3402 const size_t nsitd = MAX(nfsitd, nbsitd) + 1; 3403 3404 ox->ox_sitds = kmem_zalloc(sizeof(ohci_soft_itd_t *) * nsitd, 3405 KM_SLEEP); 3406 ox->ox_nsitd = nsitd; 3407 3408 for (i = 0; i < nsitd; i++) { 3409 /* Allocate next ITD */ 3410 sitd = ohci_alloc_sitd(sc); 3411 if (sitd == NULL) { 3412 err = ENOMEM; 3413 goto fail; 3414 } 3415 ox->ox_sitds[i] = sitd; 3416 sitd->xfer = xfer; 3417 sitd->flags = 0; 3418 } 3419 3420 return 0; 3421 fail: 3422 for (; i > 0;) { 3423 ohci_free_sitd(sc, ox->ox_sitds[--i]); 3424 } 3425 return err; 3426 } 3427 3428 Static void 3429 ohci_device_isoc_fini(struct usbd_xfer *xfer) 3430 { 3431 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3432 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3433 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3434 3435 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3436 3437 mutex_enter(&sc->sc_lock); 3438 for (size_t i = 0; i < ox->ox_nsitd; i++) { 3439 if (ox->ox_sitds[i] != opipe->tail.itd) { 3440 ohci_free_sitd_locked(sc, ox->ox_sitds[i]); 3441 } 3442 } 3443 mutex_exit(&sc->sc_lock); 3444 3445 if (ox->ox_nsitd) { 3446 const size_t sz = sizeof(ohci_soft_itd_t *) * ox->ox_nsitd; 3447 kmem_free(ox->ox_sitds, sz); 3448 } 3449 } 3450 3451 3452 usbd_status 3453 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3454 { 3455 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3456 usbd_status __diagused err; 3457 3458 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3459 3460 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3461 3462 /* Put it on our queue, */ 3463 mutex_enter(&sc->sc_lock); 3464 err = usb_insert_transfer(xfer); 3465 mutex_exit(&sc->sc_lock); 3466 3467 KASSERT(err == USBD_NORMAL_COMPLETION); 3468 3469 /* insert into schedule, */ 3470 ohci_device_isoc_enter(xfer); 3471 3472 /* and start if the pipe wasn't running */ 3473 return USBD_IN_PROGRESS; 3474 } 3475 3476 void 3477 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3478 { 3479 struct ohci_xfer *ox = OHCI_XFER2OXFER(xfer); 3480 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3481 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3482 ohci_soft_ed_t *sed = opipe->sed; 3483 ohci_soft_itd_t *sitd, *nsitd, *tail; 3484 ohci_physaddr_t buf, offs, noffs, bp0; 3485 int i, ncur, nframes; 3486 3487 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3488 DPRINTFN(5, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3489 3490 mutex_enter(&sc->sc_lock); 3491 3492 if (sc->sc_dying) { 3493 mutex_exit(&sc->sc_lock); 3494 return; 3495 } 3496 3497 struct isoc *isoc = &opipe->isoc; 3498 3499 DPRINTFN(1, "used=%jd next=%jd xfer=%#jx nframes=%jd", 3500 isoc->inuse, isoc->next, (uintptr_t)xfer, xfer->ux_nframes); 3501 3502 if (isoc->next == -1) { 3503 /* Not in use yet, schedule it a few frames ahead. */ 3504 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3505 DPRINTFN(2,"start next=%jd", isoc->next, 0, 0, 0); 3506 } 3507 3508 sitd = opipe->tail.itd; 3509 opipe->tail.itd = ox->ox_sitds[0]; 3510 ox->ox_sitds[0] = sitd; 3511 3512 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3513 bp0 = OHCI_PAGE(buf); 3514 offs = OHCI_PAGE_OFFSET(buf); 3515 nframes = xfer->ux_nframes; 3516 xfer->ux_hcpriv = sitd; 3517 size_t j = 1; 3518 for (i = ncur = 0; i < nframes; i++, ncur++) { 3519 noffs = offs + xfer->ux_frlengths[i]; 3520 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3521 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3522 3523 /* Allocate next ITD */ 3524 nsitd = ox->ox_sitds[j++]; 3525 KASSERT(nsitd != NULL); 3526 KASSERT(j < ox->ox_nsitd); 3527 3528 /* Fill current ITD */ 3529 sitd->itd.itd_flags = HTOO32( 3530 OHCI_ITD_NOCC | 3531 OHCI_ITD_SET_SF(isoc->next) | 3532 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3533 OHCI_ITD_SET_FC(ncur)); 3534 sitd->itd.itd_bp0 = HTOO32(bp0); 3535 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3536 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3537 sitd->nextitd = nsitd; 3538 sitd->xfer = xfer; 3539 sitd->flags = 0; 3540 #ifdef DIAGNOSTIC 3541 sitd->isdone = false; 3542 #endif 3543 ohci_hash_add_itd(sc, sitd); 3544 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3546 3547 sitd = nsitd; 3548 isoc->next = isoc->next + ncur; 3549 bp0 = OHCI_PAGE(buf + offs); 3550 ncur = 0; 3551 } 3552 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3553 /* XXX Sync */ 3554 offs = noffs; 3555 } 3556 KASSERT(j <= ox->ox_nsitd); 3557 3558 /* point at sentinel */ 3559 tail = opipe->tail.itd; 3560 memset(&tail->itd, 0, sizeof(tail->itd)); 3561 tail->nextitd = NULL; 3562 tail->xfer = NULL; 3563 usb_syncmem(&tail->dma, tail->offs, sizeof(tail->itd), 3564 BUS_DMASYNC_PREWRITE); 3565 3566 /* Fixup last used ITD */ 3567 sitd->itd.itd_flags = HTOO32( 3568 OHCI_ITD_NOCC | 3569 OHCI_ITD_SET_SF(isoc->next) | 3570 OHCI_ITD_SET_DI(0) | 3571 OHCI_ITD_SET_FC(ncur)); 3572 sitd->itd.itd_bp0 = HTOO32(bp0); 3573 sitd->itd.itd_nextitd = HTOO32(tail->physaddr); 3574 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3575 sitd->nextitd = tail; 3576 sitd->xfer = xfer; 3577 sitd->flags = OHCI_CALL_DONE; 3578 #ifdef DIAGNOSTIC 3579 sitd->isdone = false; 3580 #endif 3581 ohci_hash_add_itd(sc, sitd); 3582 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3584 3585 isoc->next = isoc->next + ncur; 3586 isoc->inuse += nframes; 3587 3588 /* XXX pretend we did it all */ 3589 xfer->ux_actlen = offs; 3590 xfer->ux_status = USBD_IN_PROGRESS; 3591 3592 #ifdef OHCI_DEBUG 3593 if (ohcidebug >= 5) { 3594 DPRINTF("frame=%jd", O32TOH(sc->sc_hcca->hcca_frame_number), 3595 0, 0, 0); 3596 ohci_dump_itds(sc, xfer->ux_hcpriv); 3597 ohci_dump_ed(sc, sed); 3598 } 3599 #endif 3600 3601 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3602 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3603 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3604 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3605 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3606 sizeof(sed->ed.ed_flags), 3607 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3608 mutex_exit(&sc->sc_lock); 3609 } 3610 3611 void 3612 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3613 { 3614 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3615 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3616 ohci_soft_ed_t *sed; 3617 ohci_soft_itd_t *sitd; 3618 3619 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3620 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3621 3622 KASSERT(mutex_owned(&sc->sc_lock)); 3623 3624 /* Transfer is already done. */ 3625 if (xfer->ux_status != USBD_NOT_STARTED && 3626 xfer->ux_status != USBD_IN_PROGRESS) { 3627 printf("ohci_device_isoc_abort: early return\n"); 3628 goto done; 3629 } 3630 3631 /* Give xfer the requested abort code. */ 3632 xfer->ux_status = USBD_CANCELLED; 3633 3634 sed = opipe->sed; 3635 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3636 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3637 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3638 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3639 sizeof(sed->ed.ed_flags), 3640 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3641 3642 sitd = xfer->ux_hcpriv; 3643 KASSERT(sitd); 3644 3645 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3646 3647 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3648 ohci_hash_rem_itd(sc, sitd); 3649 #ifdef DIAGNOSTIC 3650 DPRINTFN(1, "abort sets done sitd=%#jx", (uintptr_t)sitd, 3651 0, 0, 0); 3652 sitd->isdone = true; 3653 #endif 3654 } 3655 3656 /* Run callback. */ 3657 usb_transfer_complete(xfer); 3658 3659 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3660 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3661 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3663 3664 done: 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 } 3667 3668 void 3669 ohci_device_isoc_done(struct usbd_xfer *xfer) 3670 { 3671 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3672 DPRINTFN(1, "xfer=%#jx", (uintptr_t)xfer, 0, 0, 0); 3673 } 3674 3675 usbd_status 3676 ohci_setup_isoc(struct usbd_pipe *pipe) 3677 { 3678 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3679 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3680 struct isoc *isoc = &opipe->isoc; 3681 3682 isoc->next = -1; 3683 isoc->inuse = 0; 3684 3685 mutex_enter(&sc->sc_lock); 3686 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3687 mutex_exit(&sc->sc_lock); 3688 3689 return USBD_NORMAL_COMPLETION; 3690 } 3691 3692 void 3693 ohci_device_isoc_close(struct usbd_pipe *pipe) 3694 { 3695 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3696 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3697 3698 KASSERT(mutex_owned(&sc->sc_lock)); 3699 3700 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3701 DPRINTF("pipe=%#jx", (uintptr_t)pipe, 0, 0, 0); 3702 ohci_close_pipe(pipe, sc->sc_isoc_head); 3703 #ifdef DIAGNOSTIC 3704 opipe->tail.itd->isdone = true; 3705 #endif 3706 ohci_free_sitd_locked(sc, opipe->tail.itd); 3707 } 3708
Indexes created Fri Oct 03 02:09:57 GMT 2025