ohci.c revision 1.225
1 /* $NetBSD: ohci.c,v 1.225 2012/11/20 21:16:01 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.225 2012/11/20 21:16:01 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kmem.h> 51 #include <sys/kernel.h> 52 #include <sys/device.h> 53 #include <sys/select.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/cpu.h> 57 58 #include <machine/endian.h> 59 60 #include <dev/usb/usb.h> 61 #include <dev/usb/usbdi.h> 62 #include <dev/usb/usbdivar.h> 63 #include <dev/usb/usb_mem.h> 64 #include <dev/usb/usb_quirks.h> 65 66 #include <dev/usb/ohcireg.h> 67 #include <dev/usb/ohcivar.h> 68 #include <dev/usb/usbroothub_subr.h> 69 70 71 72 #ifdef OHCI_DEBUG 73 #define DPRINTF(x) if (ohcidebug) printf x 74 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 75 int ohcidebug = 0; 76 #else 77 #define DPRINTF(x) 78 #define DPRINTFN(n,x) 79 #endif 80 81 #if BYTE_ORDER == BIG_ENDIAN 82 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 83 #else 84 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 85 #endif 86 87 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 88 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 89 #define HTOO16(val) O16TOH(val) 90 #define HTOO32(val) O32TOH(val) 91 92 struct ohci_pipe; 93 94 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 95 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 96 97 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 98 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 99 100 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 101 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 102 103 #if 0 104 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 105 ohci_soft_td_t *); 106 #endif 107 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 108 ohci_softc_t *, int, int, usbd_xfer_handle, 109 ohci_soft_td_t *, ohci_soft_td_t **); 110 111 Static usbd_status ohci_open(usbd_pipe_handle); 112 Static void ohci_poll(struct usbd_bus *); 113 Static void ohci_softintr(void *); 114 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 115 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 116 Static void ohci_rhsc_softint(void *arg); 117 118 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 119 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 120 ohci_soft_ed_t *); 121 122 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 123 ohci_soft_ed_t *); 124 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 125 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 126 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 127 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 128 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 129 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 130 131 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 132 Static void ohci_device_isoc_enter(usbd_xfer_handle); 133 134 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 135 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 136 137 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 138 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 139 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 140 141 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 142 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 143 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 144 Static void ohci_root_ctrl_close(usbd_pipe_handle); 145 Static void ohci_root_ctrl_done(usbd_xfer_handle); 146 147 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 148 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 149 Static void ohci_root_intr_abort(usbd_xfer_handle); 150 Static void ohci_root_intr_close(usbd_pipe_handle); 151 Static void ohci_root_intr_done(usbd_xfer_handle); 152 153 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 154 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 155 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 156 Static void ohci_device_ctrl_close(usbd_pipe_handle); 157 Static void ohci_device_ctrl_done(usbd_xfer_handle); 158 159 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 160 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 161 Static void ohci_device_bulk_abort(usbd_xfer_handle); 162 Static void ohci_device_bulk_close(usbd_pipe_handle); 163 Static void ohci_device_bulk_done(usbd_xfer_handle); 164 165 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 167 Static void ohci_device_intr_abort(usbd_xfer_handle); 168 Static void ohci_device_intr_close(usbd_pipe_handle); 169 Static void ohci_device_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 172 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 173 Static void ohci_device_isoc_abort(usbd_xfer_handle); 174 Static void ohci_device_isoc_close(usbd_pipe_handle); 175 Static void ohci_device_isoc_done(usbd_xfer_handle); 176 177 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 178 struct ohci_pipe *pipe, int ival); 179 180 Static void ohci_timeout(void *); 181 Static void ohci_timeout_task(void *); 182 Static void ohci_rhsc_enable(void *); 183 184 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 185 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 186 187 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 188 Static void ohci_noop(usbd_pipe_handle pipe); 189 190 #ifdef OHCI_DEBUG 191 Static void ohci_dumpregs(ohci_softc_t *); 192 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 193 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 194 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 195 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 196 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 197 #endif 198 199 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 200 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 201 #define OWRITE1(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 #define OWRITE2(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 #define OWRITE4(sc, r, x) \ 206 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 207 static __inline uint8_t 208 OREAD1(ohci_softc_t *sc, bus_size_t r) 209 { 210 211 OBARR(sc); 212 return bus_space_read_1(sc->iot, sc->ioh, r); 213 } 214 215 static __inline uint16_t 216 OREAD2(ohci_softc_t *sc, bus_size_t r) 217 { 218 219 OBARR(sc); 220 return bus_space_read_2(sc->iot, sc->ioh, r); 221 } 222 223 static __inline uint32_t 224 OREAD4(ohci_softc_t *sc, bus_size_t r) 225 { 226 227 OBARR(sc); 228 return bus_space_read_4(sc->iot, sc->ioh, r); 229 } 230 231 /* Reverse the bits in a value 0 .. 31 */ 232 Static u_int8_t revbits[OHCI_NO_INTRS] = 233 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 234 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 235 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 236 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 237 238 struct ohci_pipe { 239 struct usbd_pipe pipe; 240 ohci_soft_ed_t *sed; 241 union { 242 ohci_soft_td_t *td; 243 ohci_soft_itd_t *itd; 244 } tail; 245 /* Info needed for different pipe kinds. */ 246 union { 247 /* Control pipe */ 248 struct { 249 usb_dma_t reqdma; 250 u_int length; 251 ohci_soft_td_t *setup, *data, *stat; 252 } ctl; 253 /* Interrupt pipe */ 254 struct { 255 int nslots; 256 int pos; 257 } intr; 258 /* Bulk pipe */ 259 struct { 260 u_int length; 261 int isread; 262 } bulk; 263 /* Iso pipe */ 264 struct iso { 265 int next, inuse; 266 } iso; 267 } u; 268 }; 269 270 #define OHCI_INTR_ENDPT 1 271 272 Static const struct usbd_bus_methods ohci_bus_methods = { 273 .open_pipe = ohci_open, 274 .soft_intr = ohci_softintr, 275 .do_poll = ohci_poll, 276 .allocm = ohci_allocm, 277 .freem = ohci_freem, 278 .allocx = ohci_allocx, 279 .freex = ohci_freex, 280 .get_lock = ohci_get_lock, 281 }; 282 283 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 284 .transfer = ohci_root_ctrl_transfer, 285 .start = ohci_root_ctrl_start, 286 .abort = ohci_root_ctrl_abort, 287 .close = ohci_root_ctrl_close, 288 .cleartoggle = ohci_noop, 289 .done = ohci_root_ctrl_done, 290 }; 291 292 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 293 .transfer = ohci_root_intr_transfer, 294 .start = ohci_root_intr_start, 295 .abort = ohci_root_intr_abort, 296 .close = ohci_root_intr_close, 297 .cleartoggle = ohci_noop, 298 .done = ohci_root_intr_done, 299 }; 300 301 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 302 .transfer = ohci_device_ctrl_transfer, 303 .start = ohci_device_ctrl_start, 304 .abort = ohci_device_ctrl_abort, 305 .close = ohci_device_ctrl_close, 306 .cleartoggle = ohci_noop, 307 .done = ohci_device_ctrl_done, 308 }; 309 310 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 311 .transfer = ohci_device_intr_transfer, 312 .start = ohci_device_intr_start, 313 .abort = ohci_device_intr_abort, 314 .close = ohci_device_intr_close, 315 .cleartoggle = ohci_device_clear_toggle, 316 .done = ohci_device_intr_done, 317 }; 318 319 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 320 .transfer = ohci_device_bulk_transfer, 321 .start = ohci_device_bulk_start, 322 .abort = ohci_device_bulk_abort, 323 .close = ohci_device_bulk_close, 324 .cleartoggle = ohci_device_clear_toggle, 325 .done = ohci_device_bulk_done, 326 }; 327 328 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 329 .transfer = ohci_device_isoc_transfer, 330 .start = ohci_device_isoc_start, 331 .abort = ohci_device_isoc_abort, 332 .close = ohci_device_isoc_close, 333 .cleartoggle = ohci_noop, 334 .done = ohci_device_isoc_done, 335 }; 336 337 int 338 ohci_activate(device_t self, enum devact act) 339 { 340 struct ohci_softc *sc = device_private(self); 341 342 switch (act) { 343 case DVACT_DEACTIVATE: 344 sc->sc_dying = 1; 345 return 0; 346 default: 347 return EOPNOTSUPP; 348 } 349 } 350 351 void 352 ohci_childdet(device_t self, device_t child) 353 { 354 struct ohci_softc *sc = device_private(self); 355 356 KASSERT(sc->sc_child == child); 357 sc->sc_child = NULL; 358 } 359 360 int 361 ohci_detach(struct ohci_softc *sc, int flags) 362 { 363 int rv = 0; 364 usbd_xfer_handle xfer; 365 366 if (sc->sc_child != NULL) 367 rv = config_detach(sc->sc_child, flags); 368 369 if (rv != 0) 370 return (rv); 371 372 callout_stop(&sc->sc_tmo_rhsc); 373 374 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 375 callout_destroy(&sc->sc_tmo_rhsc); 376 377 softint_disestablish(sc->sc_rhsc_si); 378 379 cv_destroy(&sc->sc_softwake_cv); 380 381 mutex_destroy(&sc->sc_lock); 382 mutex_destroy(&sc->sc_intr_lock); 383 384 if (sc->sc_hcca != NULL) 385 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 386 while((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 387 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 388 kmem_free(xfer, sizeof(struct ohci_xfer)); 389 } 390 391 return (rv); 392 } 393 394 ohci_soft_ed_t * 395 ohci_alloc_sed(ohci_softc_t *sc) 396 { 397 ohci_soft_ed_t *sed; 398 usbd_status err; 399 int i, offs; 400 usb_dma_t dma; 401 402 if (sc->sc_freeeds == NULL) { 403 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 404 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 405 OHCI_ED_ALIGN, &dma); 406 if (err) 407 return (0); 408 for (i = 0; i < OHCI_SED_CHUNK; i++) { 409 offs = i * OHCI_SED_SIZE; 410 sed = KERNADDR(&dma, offs); 411 sed->physaddr = DMAADDR(&dma, offs); 412 sed->dma = dma; 413 sed->offs = offs; 414 sed->next = sc->sc_freeeds; 415 sc->sc_freeeds = sed; 416 } 417 } 418 sed = sc->sc_freeeds; 419 sc->sc_freeeds = sed->next; 420 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 421 sed->next = 0; 422 return (sed); 423 } 424 425 void 426 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 427 { 428 sed->next = sc->sc_freeeds; 429 sc->sc_freeeds = sed; 430 } 431 432 ohci_soft_td_t * 433 ohci_alloc_std(ohci_softc_t *sc) 434 { 435 ohci_soft_td_t *std; 436 usbd_status err; 437 int i, offs; 438 usb_dma_t dma; 439 440 if (sc->sc_freetds == NULL) { 441 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 442 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 443 OHCI_TD_ALIGN, &dma); 444 if (err) 445 return (NULL); 446 for(i = 0; i < OHCI_STD_CHUNK; i++) { 447 offs = i * OHCI_STD_SIZE; 448 std = KERNADDR(&dma, offs); 449 std->physaddr = DMAADDR(&dma, offs); 450 std->dma = dma; 451 std->offs = offs; 452 std->nexttd = sc->sc_freetds; 453 sc->sc_freetds = std; 454 } 455 } 456 457 std = sc->sc_freetds; 458 sc->sc_freetds = std->nexttd; 459 memset(&std->td, 0, sizeof(ohci_td_t)); 460 std->nexttd = NULL; 461 std->xfer = NULL; 462 ohci_hash_add_td(sc, std); 463 464 return (std); 465 } 466 467 void 468 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 469 { 470 471 ohci_hash_rem_td(sc, std); 472 std->nexttd = sc->sc_freetds; 473 sc->sc_freetds = std; 474 } 475 476 usbd_status 477 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 478 int alen, int rd, usbd_xfer_handle xfer, 479 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 480 { 481 ohci_soft_td_t *next, *cur; 482 ohci_physaddr_t dataphys, dataphysend; 483 u_int32_t tdflags; 484 int len, curlen; 485 usb_dma_t *dma = &xfer->dmabuf; 486 u_int16_t flags = xfer->flags; 487 488 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 489 490 KASSERT(mutex_owned(&sc->sc_lock)); 491 492 len = alen; 493 cur = sp; 494 dataphys = DMAADDR(dma, 0); 495 dataphysend = OHCI_PAGE(dataphys + len - 1); 496 usb_syncmem(dma, 0, len, 497 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 498 tdflags = HTOO32( 499 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 500 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 501 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 502 503 for (;;) { 504 next = ohci_alloc_std(sc); 505 if (next == NULL) 506 goto nomem; 507 508 /* The OHCI hardware can handle at most one page crossing. */ 509 if (OHCI_PAGE(dataphys) == dataphysend || 510 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 511 /* we can handle it in this TD */ 512 curlen = len; 513 } else { 514 /* must use multiple TDs, fill as much as possible. */ 515 curlen = 2 * OHCI_PAGE_SIZE - 516 (dataphys & (OHCI_PAGE_SIZE-1)); 517 /* the length must be a multiple of the max size */ 518 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 519 #ifdef DIAGNOSTIC 520 if (curlen == 0) 521 panic("ohci_alloc_std: curlen == 0"); 522 #endif 523 } 524 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 525 "dataphysend=0x%08x len=%d curlen=%d\n", 526 dataphys, dataphysend, 527 len, curlen)); 528 len -= curlen; 529 530 cur->td.td_flags = tdflags; 531 cur->td.td_cbp = HTOO32(dataphys); 532 cur->nexttd = next; 533 cur->td.td_nexttd = HTOO32(next->physaddr); 534 cur->td.td_be = HTOO32(dataphys + curlen - 1); 535 cur->len = curlen; 536 cur->flags = OHCI_ADD_LEN; 537 cur->xfer = xfer; 538 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 540 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 541 dataphys, dataphys + curlen - 1)); 542 if (len == 0) 543 break; 544 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 545 dataphys += curlen; 546 cur = next; 547 } 548 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 549 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 550 /* Force a 0 length transfer at the end. */ 551 552 cur = next; 553 next = ohci_alloc_std(sc); 554 if (next == NULL) 555 goto nomem; 556 557 cur->td.td_flags = tdflags; 558 cur->td.td_cbp = 0; /* indicate 0 length packet */ 559 cur->nexttd = next; 560 cur->td.td_nexttd = HTOO32(next->physaddr); 561 cur->td.td_be = ~0; 562 cur->len = 0; 563 cur->flags = 0; 564 cur->xfer = xfer; 565 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 566 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 567 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 568 } 569 *ep = cur; 570 571 return (USBD_NORMAL_COMPLETION); 572 573 nomem: 574 /* XXX free chain */ 575 return (USBD_NOMEM); 576 } 577 578 #if 0 579 Static void 580 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 581 ohci_soft_td_t *stdend) 582 { 583 ohci_soft_td_t *p; 584 585 for (; std != stdend; std = p) { 586 p = std->nexttd; 587 ohci_free_std(sc, std); 588 } 589 } 590 #endif 591 592 ohci_soft_itd_t * 593 ohci_alloc_sitd(ohci_softc_t *sc) 594 { 595 ohci_soft_itd_t *sitd; 596 usbd_status err; 597 int i, offs; 598 usb_dma_t dma; 599 600 if (sc->sc_freeitds == NULL) { 601 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 602 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 603 OHCI_ITD_ALIGN, &dma); 604 if (err) 605 return (NULL); 606 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 607 offs = i * OHCI_SITD_SIZE; 608 sitd = KERNADDR(&dma, offs); 609 sitd->physaddr = DMAADDR(&dma, offs); 610 sitd->dma = dma; 611 sitd->offs = offs; 612 sitd->nextitd = sc->sc_freeitds; 613 sc->sc_freeitds = sitd; 614 } 615 } 616 617 sitd = sc->sc_freeitds; 618 sc->sc_freeitds = sitd->nextitd; 619 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 620 sitd->nextitd = NULL; 621 sitd->xfer = NULL; 622 ohci_hash_add_itd(sc, sitd); 623 624 #ifdef DIAGNOSTIC 625 sitd->isdone = 0; 626 #endif 627 628 return (sitd); 629 } 630 631 void 632 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 633 { 634 635 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 636 637 #ifdef DIAGNOSTIC 638 if (!sitd->isdone) { 639 panic("ohci_free_sitd: sitd=%p not done", sitd); 640 return; 641 } 642 /* Warn double free */ 643 sitd->isdone = 0; 644 #endif 645 646 ohci_hash_rem_itd(sc, sitd); 647 sitd->nextitd = sc->sc_freeitds; 648 sc->sc_freeitds = sitd; 649 } 650 651 usbd_status 652 ohci_init(ohci_softc_t *sc) 653 { 654 ohci_soft_ed_t *sed, *psed; 655 usbd_status err; 656 int i; 657 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 658 659 DPRINTF(("ohci_init: start\n")); 660 aprint_normal_dev(sc->sc_dev, ""); 661 662 sc->sc_hcca = NULL; 663 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 664 665 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 666 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 667 cv_init(&sc->sc_softwake_cv, "ohciab"); 668 669 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 670 ohci_rhsc_softint, sc); 671 672 for (i = 0; i < OHCI_HASH_SIZE; i++) 673 LIST_INIT(&sc->sc_hash_tds[i]); 674 for (i = 0; i < OHCI_HASH_SIZE; i++) 675 LIST_INIT(&sc->sc_hash_itds[i]); 676 677 SIMPLEQ_INIT(&sc->sc_free_xfers); 678 679 rev = OREAD4(sc, OHCI_REVISION); 680 aprint_normal("OHCI version %d.%d%s\n", 681 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 682 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 683 684 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 685 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 686 sc->sc_bus.usbrev = USBREV_UNKNOWN; 687 return (USBD_INVAL); 688 } 689 sc->sc_bus.usbrev = USBREV_1_0; 690 691 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 692 USB_MEM_RESERVE); 693 694 /* XXX determine alignment by R/W */ 695 /* Allocate the HCCA area. */ 696 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 697 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 698 if (err) { 699 sc->sc_hcca = NULL; 700 return err; 701 } 702 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 703 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 704 705 sc->sc_eintrs = OHCI_NORMAL_INTRS; 706 707 /* Allocate dummy ED that starts the control list. */ 708 sc->sc_ctrl_head = ohci_alloc_sed(sc); 709 if (sc->sc_ctrl_head == NULL) { 710 err = USBD_NOMEM; 711 goto bad1; 712 } 713 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 714 715 /* Allocate dummy ED that starts the bulk list. */ 716 sc->sc_bulk_head = ohci_alloc_sed(sc); 717 if (sc->sc_bulk_head == NULL) { 718 err = USBD_NOMEM; 719 goto bad2; 720 } 721 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 722 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 723 sizeof(sc->sc_bulk_head->ed), 724 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 725 726 /* Allocate dummy ED that starts the isochronous list. */ 727 sc->sc_isoc_head = ohci_alloc_sed(sc); 728 if (sc->sc_isoc_head == NULL) { 729 err = USBD_NOMEM; 730 goto bad3; 731 } 732 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 733 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 734 sizeof(sc->sc_isoc_head->ed), 735 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 736 737 /* Allocate all the dummy EDs that make up the interrupt tree. */ 738 for (i = 0; i < OHCI_NO_EDS; i++) { 739 sed = ohci_alloc_sed(sc); 740 if (sed == NULL) { 741 while (--i >= 0) 742 ohci_free_sed(sc, sc->sc_eds[i]); 743 err = USBD_NOMEM; 744 goto bad4; 745 } 746 /* All ED fields are set to 0. */ 747 sc->sc_eds[i] = sed; 748 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 749 if (i != 0) 750 psed = sc->sc_eds[(i-1) / 2]; 751 else 752 psed= sc->sc_isoc_head; 753 sed->next = psed; 754 sed->ed.ed_nexted = HTOO32(psed->physaddr); 755 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 756 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 757 } 758 /* 759 * Fill HCCA interrupt table. The bit reversal is to get 760 * the tree set up properly to spread the interrupts. 761 */ 762 for (i = 0; i < OHCI_NO_INTRS; i++) 763 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 764 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 765 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 766 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 767 768 #ifdef OHCI_DEBUG 769 if (ohcidebug > 15) { 770 for (i = 0; i < OHCI_NO_EDS; i++) { 771 printf("ed#%d ", i); 772 ohci_dump_ed(sc, sc->sc_eds[i]); 773 } 774 printf("iso "); 775 ohci_dump_ed(sc, sc->sc_isoc_head); 776 } 777 #endif 778 779 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 780 ctl = OREAD4(sc, OHCI_CONTROL); 781 rwc = ctl & OHCI_RWC; 782 fm = OREAD4(sc, OHCI_FM_INTERVAL); 783 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 784 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 785 786 /* Determine in what context we are running. */ 787 if (ctl & OHCI_IR) { 788 /* SMM active, request change */ 789 DPRINTF(("ohci_init: SMM active, request owner change\n")); 790 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 791 (OHCI_OC | OHCI_MIE)) 792 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 793 s = OREAD4(sc, OHCI_COMMAND_STATUS); 794 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 795 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 796 usb_delay_ms(&sc->sc_bus, 1); 797 ctl = OREAD4(sc, OHCI_CONTROL); 798 } 799 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 800 if ((ctl & OHCI_IR) == 0) { 801 aprint_error_dev(sc->sc_dev, 802 "SMM does not respond, resetting\n"); 803 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 804 goto reset; 805 } 806 #if 0 807 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 808 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 809 /* BIOS started controller. */ 810 DPRINTF(("ohci_init: BIOS active\n")); 811 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 812 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 813 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 814 } 815 #endif 816 } else { 817 DPRINTF(("ohci_init: cold started\n")); 818 reset: 819 /* Controller was cold started. */ 820 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 821 } 822 823 /* 824 * This reset should not be necessary according to the OHCI spec, but 825 * without it some controllers do not start. 826 */ 827 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 828 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 829 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 830 831 /* We now own the host controller and the bus has been reset. */ 832 833 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 834 /* Nominal time for a reset is 10 us. */ 835 for (i = 0; i < 10; i++) { 836 delay(10); 837 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 838 if (!hcr) 839 break; 840 } 841 if (hcr) { 842 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 843 err = USBD_IOERROR; 844 goto bad5; 845 } 846 #ifdef OHCI_DEBUG 847 if (ohcidebug > 15) 848 ohci_dumpregs(sc); 849 #endif 850 851 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 852 853 /* Set up HC registers. */ 854 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 855 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 856 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 857 /* disable all interrupts and then switch on all desired interrupts */ 858 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 859 /* switch on desired functional features */ 860 ctl = OREAD4(sc, OHCI_CONTROL); 861 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 862 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 863 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 864 /* And finally start it! */ 865 OWRITE4(sc, OHCI_CONTROL, ctl); 866 867 /* 868 * The controller is now OPERATIONAL. Set a some final 869 * registers that should be set earlier, but that the 870 * controller ignores when in the SUSPEND state. 871 */ 872 ival = OHCI_GET_IVAL(fm); 873 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 874 fm |= OHCI_FSMPS(ival) | ival; 875 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 876 per = OHCI_PERIODIC(ival); /* 90% periodic */ 877 OWRITE4(sc, OHCI_PERIODIC_START, per); 878 879 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 880 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 881 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 882 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 883 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 884 885 /* 886 * The AMD756 requires a delay before re-reading the register, 887 * otherwise it will occasionally report 0 ports. 888 */ 889 sc->sc_noport = 0; 890 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 891 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 892 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 893 } 894 895 #ifdef OHCI_DEBUG 896 if (ohcidebug > 5) 897 ohci_dumpregs(sc); 898 #endif 899 900 /* Set up the bus struct. */ 901 sc->sc_bus.methods = &ohci_bus_methods; 902 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 903 904 sc->sc_control = sc->sc_intre = 0; 905 906 /* Finally, turn on interrupts. */ 907 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 908 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 909 910 return (USBD_NORMAL_COMPLETION); 911 912 bad5: 913 for (i = 0; i < OHCI_NO_EDS; i++) 914 ohci_free_sed(sc, sc->sc_eds[i]); 915 bad4: 916 ohci_free_sed(sc, sc->sc_isoc_head); 917 bad3: 918 ohci_free_sed(sc, sc->sc_bulk_head); 919 bad2: 920 ohci_free_sed(sc, sc->sc_ctrl_head); 921 bad1: 922 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 923 sc->sc_hcca = NULL; 924 return (err); 925 } 926 927 usbd_status 928 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 929 { 930 struct ohci_softc *sc = bus->hci_private; 931 usbd_status status; 932 933 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 934 if (status == USBD_NOMEM) 935 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 936 return status; 937 } 938 939 void 940 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 941 { 942 struct ohci_softc *sc = bus->hci_private; 943 if (dma->block->flags & USB_DMA_RESERVE) { 944 usb_reserve_freem(&sc->sc_dma_reserve, dma); 945 return; 946 } 947 usb_freemem(&sc->sc_bus, dma); 948 } 949 950 usbd_xfer_handle 951 ohci_allocx(struct usbd_bus *bus) 952 { 953 struct ohci_softc *sc = bus->hci_private; 954 usbd_xfer_handle xfer; 955 956 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 957 if (xfer != NULL) { 958 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 959 #ifdef DIAGNOSTIC 960 if (xfer->busy_free != XFER_FREE) { 961 printf("ohci_allocx: xfer=%p not free, 0x%08x\n", xfer, 962 xfer->busy_free); 963 } 964 #endif 965 } else { 966 xfer = kmem_alloc(sizeof(struct ohci_xfer), KM_SLEEP); 967 } 968 if (xfer != NULL) { 969 memset(xfer, 0, sizeof (struct ohci_xfer)); 970 #ifdef DIAGNOSTIC 971 xfer->busy_free = XFER_BUSY; 972 #endif 973 } 974 return (xfer); 975 } 976 977 void 978 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 979 { 980 struct ohci_softc *sc = bus->hci_private; 981 982 #ifdef DIAGNOSTIC 983 if (xfer->busy_free != XFER_BUSY) { 984 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 985 xfer->busy_free); 986 } 987 xfer->busy_free = XFER_FREE; 988 #endif 989 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 990 } 991 992 Static void 993 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 994 { 995 struct ohci_softc *sc = bus->hci_private; 996 997 *lock = &sc->sc_lock; 998 } 999 1000 /* 1001 * Shut down the controller when the system is going down. 1002 */ 1003 bool 1004 ohci_shutdown(device_t self, int flags) 1005 { 1006 ohci_softc_t *sc = device_private(self); 1007 1008 DPRINTF(("ohci_shutdown: stopping the HC\n")); 1009 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1010 return true; 1011 } 1012 1013 bool 1014 ohci_resume(device_t dv, const pmf_qual_t *qual) 1015 { 1016 ohci_softc_t *sc = device_private(dv); 1017 uint32_t ctl; 1018 1019 mutex_spin_enter(&sc->sc_intr_lock); 1020 sc->sc_bus.use_polling++; 1021 mutex_spin_exit(&sc->sc_intr_lock); 1022 1023 /* Some broken BIOSes do not recover these values */ 1024 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1025 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1026 sc->sc_ctrl_head->physaddr); 1027 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1028 sc->sc_bulk_head->physaddr); 1029 if (sc->sc_intre) 1030 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1031 (OHCI_ALL_INTRS | OHCI_MIE)); 1032 if (sc->sc_control) 1033 ctl = sc->sc_control; 1034 else 1035 ctl = OREAD4(sc, OHCI_CONTROL); 1036 ctl |= OHCI_HCFS_RESUME; 1037 OWRITE4(sc, OHCI_CONTROL, ctl); 1038 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1039 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1040 OWRITE4(sc, OHCI_CONTROL, ctl); 1041 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1042 sc->sc_control = sc->sc_intre = 0; 1043 1044 mutex_spin_enter(&sc->sc_intr_lock); 1045 sc->sc_bus.use_polling--; 1046 mutex_spin_exit(&sc->sc_intr_lock); 1047 1048 return true; 1049 } 1050 1051 bool 1052 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1053 { 1054 ohci_softc_t *sc = device_private(dv); 1055 uint32_t ctl; 1056 1057 mutex_spin_enter(&sc->sc_intr_lock); 1058 sc->sc_bus.use_polling++; 1059 mutex_spin_exit(&sc->sc_intr_lock); 1060 1061 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1062 if (sc->sc_control == 0) { 1063 /* 1064 * Preserve register values, in case that BIOS 1065 * does not recover them. 1066 */ 1067 sc->sc_control = ctl; 1068 sc->sc_intre = OREAD4(sc, 1069 OHCI_INTERRUPT_ENABLE); 1070 } 1071 ctl |= OHCI_HCFS_SUSPEND; 1072 OWRITE4(sc, OHCI_CONTROL, ctl); 1073 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1074 1075 mutex_spin_enter(&sc->sc_intr_lock); 1076 sc->sc_bus.use_polling--; 1077 mutex_spin_exit(&sc->sc_intr_lock); 1078 1079 return true; 1080 } 1081 1082 #ifdef OHCI_DEBUG 1083 void 1084 ohci_dumpregs(ohci_softc_t *sc) 1085 { 1086 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1087 OREAD4(sc, OHCI_REVISION), 1088 OREAD4(sc, OHCI_CONTROL), 1089 OREAD4(sc, OHCI_COMMAND_STATUS))); 1090 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1091 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1092 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1093 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1094 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1095 OREAD4(sc, OHCI_HCCA), 1096 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1097 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1098 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1099 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1100 OREAD4(sc, OHCI_BULK_HEAD_ED), 1101 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1102 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1103 OREAD4(sc, OHCI_DONE_HEAD), 1104 OREAD4(sc, OHCI_FM_INTERVAL), 1105 OREAD4(sc, OHCI_FM_REMAINING))); 1106 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1107 OREAD4(sc, OHCI_FM_NUMBER), 1108 OREAD4(sc, OHCI_PERIODIC_START), 1109 OREAD4(sc, OHCI_LS_THRESHOLD))); 1110 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1111 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1112 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1113 OREAD4(sc, OHCI_RH_STATUS))); 1114 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1115 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1116 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1117 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1118 O32TOH(sc->sc_hcca->hcca_frame_number), 1119 O32TOH(sc->sc_hcca->hcca_done_head))); 1120 } 1121 #endif 1122 1123 Static int ohci_intr1(ohci_softc_t *); 1124 1125 int 1126 ohci_intr(void *p) 1127 { 1128 ohci_softc_t *sc = p; 1129 int ret = 0; 1130 1131 if (sc == NULL) 1132 return (0); 1133 1134 mutex_spin_enter(&sc->sc_intr_lock); 1135 1136 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1137 goto done; 1138 1139 /* If we get an interrupt while polling, then just ignore it. */ 1140 if (sc->sc_bus.use_polling) { 1141 #ifdef DIAGNOSTIC 1142 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1143 #endif 1144 /* for level triggered intrs, should do something to ack */ 1145 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1146 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1147 1148 goto done; 1149 } 1150 1151 ret = ohci_intr1(sc); 1152 1153 done: 1154 mutex_spin_exit(&sc->sc_intr_lock); 1155 return ret; 1156 } 1157 1158 Static int 1159 ohci_intr1(ohci_softc_t *sc) 1160 { 1161 u_int32_t intrs, eintrs; 1162 1163 DPRINTFN(14,("ohci_intr1: enter\n")); 1164 1165 /* In case the interrupt occurs before initialization has completed. */ 1166 if (sc == NULL || sc->sc_hcca == NULL) { 1167 #ifdef DIAGNOSTIC 1168 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1169 #endif 1170 return (0); 1171 } 1172 1173 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1174 1175 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1176 if (!intrs) 1177 return (0); 1178 1179 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1180 eintrs = intrs & sc->sc_eintrs; 1181 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1182 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1183 (u_int)eintrs, sc->sc_eintrs)); 1184 1185 if (!eintrs) { 1186 return (0); 1187 } 1188 1189 sc->sc_bus.no_intrs++; 1190 if (eintrs & OHCI_SO) { 1191 sc->sc_overrun_cnt++; 1192 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1193 printf("%s: %u scheduling overruns\n", 1194 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1195 sc->sc_overrun_cnt = 0; 1196 } 1197 /* XXX do what */ 1198 eintrs &= ~OHCI_SO; 1199 } 1200 if (eintrs & OHCI_WDH) { 1201 /* 1202 * We block the interrupt below, and reenable it later from 1203 * ohci_softintr(). 1204 */ 1205 usb_schedsoftintr(&sc->sc_bus); 1206 } 1207 if (eintrs & OHCI_RD) { 1208 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1209 /* XXX process resume detect */ 1210 } 1211 if (eintrs & OHCI_UE) { 1212 printf("%s: unrecoverable error, controller halted\n", 1213 device_xname(sc->sc_dev)); 1214 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1215 /* XXX what else */ 1216 } 1217 if (eintrs & OHCI_RHSC) { 1218 /* 1219 * We block the interrupt below, and reenable it later from 1220 * a timeout. 1221 */ 1222 softint_schedule(sc->sc_rhsc_si); 1223 } 1224 1225 if (eintrs != 0) { 1226 /* Block unprocessed interrupts. */ 1227 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1228 sc->sc_eintrs &= ~eintrs; 1229 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1230 device_xname(sc->sc_dev), eintrs)); 1231 } 1232 1233 return (1); 1234 } 1235 1236 void 1237 ohci_rhsc_enable(void *v_sc) 1238 { 1239 ohci_softc_t *sc = v_sc; 1240 1241 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1242 mutex_spin_enter(&sc->sc_intr_lock); 1243 sc->sc_eintrs |= OHCI_RHSC; 1244 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1245 mutex_spin_exit(&sc->sc_intr_lock); 1246 } 1247 1248 #ifdef OHCI_DEBUG 1249 const char *ohci_cc_strs[] = { 1250 "NO_ERROR", 1251 "CRC", 1252 "BIT_STUFFING", 1253 "DATA_TOGGLE_MISMATCH", 1254 "STALL", 1255 "DEVICE_NOT_RESPONDING", 1256 "PID_CHECK_FAILURE", 1257 "UNEXPECTED_PID", 1258 "DATA_OVERRUN", 1259 "DATA_UNDERRUN", 1260 "BUFFER_OVERRUN", 1261 "BUFFER_UNDERRUN", 1262 "reserved", 1263 "reserved", 1264 "NOT_ACCESSED", 1265 "NOT_ACCESSED", 1266 }; 1267 #endif 1268 1269 void 1270 ohci_softintr(void *v) 1271 { 1272 struct usbd_bus *bus = v; 1273 ohci_softc_t *sc = bus->hci_private; 1274 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1275 ohci_soft_td_t *std, *sdone, *stdnext; 1276 usbd_xfer_handle xfer; 1277 struct ohci_pipe *opipe; 1278 int len, cc; 1279 int i, j, actlen, iframes, uedir; 1280 ohci_physaddr_t done; 1281 1282 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1283 1284 DPRINTFN(10,("ohci_softintr: enter\n")); 1285 1286 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1287 sizeof(sc->sc_hcca->hcca_done_head), 1288 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1289 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1290 sc->sc_hcca->hcca_done_head = 0; 1291 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1292 sizeof(sc->sc_hcca->hcca_done_head), 1293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1294 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1295 sc->sc_eintrs |= OHCI_WDH; 1296 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1297 1298 /* Reverse the done list. */ 1299 for (sdone = NULL, sidone = NULL; done != 0; ) { 1300 std = ohci_hash_find_td(sc, done); 1301 if (std != NULL) { 1302 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1303 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1304 std->dnext = sdone; 1305 done = O32TOH(std->td.td_nexttd); 1306 sdone = std; 1307 DPRINTFN(10,("add TD %p\n", std)); 1308 continue; 1309 } 1310 sitd = ohci_hash_find_itd(sc, done); 1311 if (sitd != NULL) { 1312 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1313 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1314 sitd->dnext = sidone; 1315 done = O32TOH(sitd->itd.itd_nextitd); 1316 sidone = sitd; 1317 DPRINTFN(5,("add ITD %p\n", sitd)); 1318 continue; 1319 } 1320 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1321 (u_long)done); 1322 break; 1323 } 1324 1325 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1326 1327 #ifdef OHCI_DEBUG 1328 if (ohcidebug > 10) { 1329 DPRINTF(("ohci_process_done: TD done:\n")); 1330 ohci_dump_tds(sc, sdone); 1331 } 1332 #endif 1333 1334 for (std = sdone; std; std = stdnext) { 1335 xfer = std->xfer; 1336 stdnext = std->dnext; 1337 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1338 std, xfer, xfer ? xfer->hcpriv : 0)); 1339 if (xfer == NULL) { 1340 /* 1341 * xfer == NULL: There seems to be no xfer associated 1342 * with this TD. It is tailp that happened to end up on 1343 * the done queue. 1344 * Shouldn't happen, but some chips are broken(?). 1345 */ 1346 continue; 1347 } 1348 if (xfer->status == USBD_CANCELLED || 1349 xfer->status == USBD_TIMEOUT) { 1350 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1351 xfer)); 1352 /* Handled by abort routine. */ 1353 continue; 1354 } 1355 callout_stop(&xfer->timeout_handle); 1356 1357 len = std->len; 1358 if (std->td.td_cbp != 0) 1359 len -= O32TOH(std->td.td_be) - 1360 O32TOH(std->td.td_cbp) + 1; 1361 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1362 std->flags)); 1363 if (std->flags & OHCI_ADD_LEN) 1364 xfer->actlen += len; 1365 1366 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1367 if (cc == OHCI_CC_NO_ERROR) { 1368 if (std->flags & OHCI_CALL_DONE) { 1369 xfer->status = USBD_NORMAL_COMPLETION; 1370 usb_transfer_complete(xfer); 1371 } 1372 ohci_free_std(sc, std); 1373 } else { 1374 /* 1375 * Endpoint is halted. First unlink all the TDs 1376 * belonging to the failed transfer, and then restart 1377 * the endpoint. 1378 */ 1379 ohci_soft_td_t *p, *n; 1380 opipe = (struct ohci_pipe *)xfer->pipe; 1381 1382 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1383 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1384 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1385 1386 /* remove TDs */ 1387 for (p = std; p->xfer == xfer; p = n) { 1388 n = p->nexttd; 1389 ohci_free_std(sc, p); 1390 } 1391 1392 /* clear halt */ 1393 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1394 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1395 1396 if (cc == OHCI_CC_STALL) 1397 xfer->status = USBD_STALLED; 1398 else 1399 xfer->status = USBD_IOERROR; 1400 usb_transfer_complete(xfer); 1401 } 1402 } 1403 1404 #ifdef OHCI_DEBUG 1405 if (ohcidebug > 10) { 1406 DPRINTF(("ohci_softintr: ITD done:\n")); 1407 ohci_dump_itds(sc, sidone); 1408 } 1409 #endif 1410 1411 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1412 xfer = sitd->xfer; 1413 sitdnext = sitd->dnext; 1414 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1415 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1416 if (xfer == NULL) 1417 continue; 1418 if (xfer->status == USBD_CANCELLED || 1419 xfer->status == USBD_TIMEOUT) { 1420 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1421 xfer)); 1422 /* Handled by abort routine. */ 1423 continue; 1424 } 1425 #ifdef DIAGNOSTIC 1426 if (sitd->isdone) 1427 printf("ohci_softintr: sitd=%p is done\n", sitd); 1428 sitd->isdone = 1; 1429 #endif 1430 if (sitd->flags & OHCI_CALL_DONE) { 1431 ohci_soft_itd_t *next; 1432 1433 opipe = (struct ohci_pipe *)xfer->pipe; 1434 opipe->u.iso.inuse -= xfer->nframes; 1435 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1436 bEndpointAddress); 1437 xfer->status = USBD_NORMAL_COMPLETION; 1438 actlen = 0; 1439 for (i = 0, sitd = xfer->hcpriv;; 1440 sitd = next) { 1441 next = sitd->nextitd; 1442 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1443 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1444 xfer->status = USBD_IOERROR; 1445 /* For input, update frlengths with actual */ 1446 /* XXX anything necessary for output? */ 1447 if (uedir == UE_DIR_IN && 1448 xfer->status == USBD_NORMAL_COMPLETION) { 1449 iframes = OHCI_ITD_GET_FC(O32TOH( 1450 sitd->itd.itd_flags)); 1451 for (j = 0; j < iframes; i++, j++) { 1452 len = O16TOH(sitd-> 1453 itd.itd_offset[j]); 1454 if ((OHCI_ITD_PSW_GET_CC(len) & 1455 OHCI_CC_NOT_ACCESSED_MASK) 1456 == OHCI_CC_NOT_ACCESSED) 1457 len = 0; 1458 else 1459 len = OHCI_ITD_PSW_LENGTH(len); 1460 xfer->frlengths[i] = len; 1461 actlen += len; 1462 } 1463 } 1464 if (sitd->flags & OHCI_CALL_DONE) 1465 break; 1466 ohci_free_sitd(sc, sitd); 1467 } 1468 ohci_free_sitd(sc, sitd); 1469 if (uedir == UE_DIR_IN && 1470 xfer->status == USBD_NORMAL_COMPLETION) 1471 xfer->actlen = actlen; 1472 xfer->hcpriv = NULL; 1473 1474 usb_transfer_complete(xfer); 1475 } 1476 } 1477 1478 if (sc->sc_softwake) { 1479 sc->sc_softwake = 0; 1480 cv_broadcast(&sc->sc_softwake_cv); 1481 } 1482 1483 DPRINTFN(10,("ohci_softintr: done:\n")); 1484 } 1485 1486 void 1487 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1488 { 1489 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1490 #ifdef DIAGNOSTIC 1491 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1492 #endif 1493 int len = UGETW(xfer->request.wLength); 1494 int isread = (xfer->request.bmRequestType & UT_READ); 1495 1496 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1497 1498 KASSERT(mutex_owned(&sc->sc_lock)); 1499 1500 #ifdef DIAGNOSTIC 1501 if (!(xfer->rqflags & URQ_REQUEST)) { 1502 panic("ohci_device_ctrl_done: not a request"); 1503 } 1504 #endif 1505 if (len) 1506 usb_syncmem(&xfer->dmabuf, 0, len, 1507 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1508 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1509 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1510 } 1511 1512 void 1513 ohci_device_intr_done(usbd_xfer_handle xfer) 1514 { 1515 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1516 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1517 ohci_soft_ed_t *sed = opipe->sed; 1518 ohci_soft_td_t *data, *tail; 1519 int isread = 1520 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1521 1522 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1523 xfer, xfer->actlen)); 1524 1525 KASSERT(mutex_owned(&sc->sc_lock)); 1526 1527 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1528 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1529 if (xfer->pipe->repeat) { 1530 data = opipe->tail.td; 1531 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1532 if (tail == NULL) { 1533 xfer->status = USBD_NOMEM; 1534 return; 1535 } 1536 tail->xfer = NULL; 1537 1538 data->td.td_flags = HTOO32( 1539 OHCI_TD_IN | OHCI_TD_NOCC | 1540 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1541 if (xfer->flags & USBD_SHORT_XFER_OK) 1542 data->td.td_flags |= HTOO32(OHCI_TD_R); 1543 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1544 data->nexttd = tail; 1545 data->td.td_nexttd = HTOO32(tail->physaddr); 1546 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1547 xfer->length - 1); 1548 data->len = xfer->length; 1549 data->xfer = xfer; 1550 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1551 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1552 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1553 xfer->hcpriv = data; 1554 xfer->actlen = 0; 1555 1556 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1557 usb_syncmem(&sed->dma, 1558 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1559 sizeof(sed->ed.ed_tailp), 1560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1561 opipe->tail.td = tail; 1562 } 1563 } 1564 1565 void 1566 ohci_device_bulk_done(usbd_xfer_handle xfer) 1567 { 1568 #ifdef DIAGNOSTIC 1569 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1570 #endif 1571 int isread = 1572 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1573 1574 KASSERT(mutex_owned(&sc->sc_lock)); 1575 1576 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1577 xfer, xfer->actlen)); 1578 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1579 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1580 } 1581 1582 Static void 1583 ohci_rhsc_softint(void *arg) 1584 { 1585 ohci_softc_t *sc = arg; 1586 1587 mutex_enter(&sc->sc_lock); 1588 1589 ohci_rhsc(sc, sc->sc_intrxfer); 1590 1591 /* Do not allow RHSC interrupts > 1 per second */ 1592 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1593 1594 mutex_exit(&sc->sc_lock); 1595 } 1596 1597 void 1598 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1599 { 1600 usbd_pipe_handle pipe; 1601 u_char *p; 1602 int i, m; 1603 int hstatus; 1604 1605 KASSERT(mutex_owned(&sc->sc_lock)); 1606 1607 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1608 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1609 sc, xfer, hstatus)); 1610 1611 if (xfer == NULL) { 1612 /* Just ignore the change. */ 1613 return; 1614 } 1615 1616 pipe = xfer->pipe; 1617 1618 p = KERNADDR(&xfer->dmabuf, 0); 1619 m = min(sc->sc_noport, xfer->length * 8 - 1); 1620 memset(p, 0, xfer->length); 1621 for (i = 1; i <= m; i++) { 1622 /* Pick out CHANGE bits from the status reg. */ 1623 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1624 p[i/8] |= 1 << (i%8); 1625 } 1626 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1627 xfer->actlen = xfer->length; 1628 xfer->status = USBD_NORMAL_COMPLETION; 1629 1630 usb_transfer_complete(xfer); 1631 } 1632 1633 void 1634 ohci_root_intr_done(usbd_xfer_handle xfer) 1635 { 1636 } 1637 1638 void 1639 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1640 { 1641 } 1642 1643 /* 1644 * Wait here until controller claims to have an interrupt. 1645 * Then call ohci_intr and return. Use timeout to avoid waiting 1646 * too long. 1647 */ 1648 void 1649 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1650 { 1651 int timo; 1652 u_int32_t intrs; 1653 1654 mutex_enter(&sc->sc_lock); 1655 1656 xfer->status = USBD_IN_PROGRESS; 1657 for (timo = xfer->timeout; timo >= 0; timo--) { 1658 usb_delay_ms(&sc->sc_bus, 1); 1659 if (sc->sc_dying) 1660 break; 1661 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1662 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1663 #ifdef OHCI_DEBUG 1664 if (ohcidebug > 15) 1665 ohci_dumpregs(sc); 1666 #endif 1667 if (intrs) { 1668 mutex_spin_enter(&sc->sc_intr_lock); 1669 ohci_intr1(sc); 1670 mutex_spin_exit(&sc->sc_intr_lock); 1671 if (xfer->status != USBD_IN_PROGRESS) 1672 return; 1673 } 1674 } 1675 1676 /* Timeout */ 1677 DPRINTF(("ohci_waitintr: timeout\n")); 1678 xfer->status = USBD_TIMEOUT; 1679 usb_transfer_complete(xfer); 1680 1681 /* XXX should free TD */ 1682 1683 mutex_exit(&sc->sc_lock); 1684 } 1685 1686 void 1687 ohci_poll(struct usbd_bus *bus) 1688 { 1689 ohci_softc_t *sc = bus->hci_private; 1690 #ifdef OHCI_DEBUG 1691 static int last; 1692 int new; 1693 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1694 if (new != last) { 1695 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1696 last = new; 1697 } 1698 #endif 1699 1700 sc->sc_eintrs |= OHCI_WDH; 1701 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1702 mutex_spin_enter(&sc->sc_intr_lock); 1703 ohci_intr1(sc); 1704 mutex_spin_exit(&sc->sc_intr_lock); 1705 } 1706 } 1707 1708 usbd_status 1709 ohci_device_request(usbd_xfer_handle xfer) 1710 { 1711 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1712 usb_device_request_t *req = &xfer->request; 1713 usbd_device_handle dev = opipe->pipe.device; 1714 ohci_softc_t *sc = dev->bus->hci_private; 1715 int addr = dev->address; 1716 ohci_soft_td_t *setup, *stat, *next, *tail; 1717 ohci_soft_ed_t *sed; 1718 int isread; 1719 int len; 1720 usbd_status err; 1721 1722 KASSERT(mutex_owned(&sc->sc_lock)); 1723 1724 isread = req->bmRequestType & UT_READ; 1725 len = UGETW(req->wLength); 1726 1727 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1728 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1729 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1730 UGETW(req->wIndex), len, addr, 1731 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1732 1733 setup = opipe->tail.td; 1734 stat = ohci_alloc_std(sc); 1735 if (stat == NULL) { 1736 err = USBD_NOMEM; 1737 goto bad1; 1738 } 1739 tail = ohci_alloc_std(sc); 1740 if (tail == NULL) { 1741 err = USBD_NOMEM; 1742 goto bad2; 1743 } 1744 tail->xfer = NULL; 1745 1746 sed = opipe->sed; 1747 opipe->u.ctl.length = len; 1748 1749 /* Update device address and length since they may have changed 1750 during the setup of the control pipe in usbd_new_device(). */ 1751 /* XXX This only needs to be done once, but it's too early in open. */ 1752 /* XXXX Should not touch ED here! */ 1753 1754 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1755 sizeof(sed->ed.ed_flags), 1756 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1757 sed->ed.ed_flags = HTOO32( 1758 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1759 OHCI_ED_SET_FA(addr) | 1760 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1761 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1762 sizeof(sed->ed.ed_flags), 1763 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1764 1765 next = stat; 1766 1767 /* Set up data transaction */ 1768 if (len != 0) { 1769 ohci_soft_td_t *std = stat; 1770 1771 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1772 std, &stat); 1773 stat = stat->nexttd; /* point at free TD */ 1774 if (err) 1775 goto bad3; 1776 /* Start toggle at 1 and then use the carried toggle. */ 1777 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1778 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1779 usb_syncmem(&std->dma, 1780 std->offs + offsetof(ohci_td_t, td_flags), 1781 sizeof(std->td.td_flags), 1782 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1783 } 1784 1785 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1786 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1787 1788 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1789 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1790 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1791 setup->nexttd = next; 1792 setup->td.td_nexttd = HTOO32(next->physaddr); 1793 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1794 setup->len = 0; 1795 setup->xfer = xfer; 1796 setup->flags = 0; 1797 xfer->hcpriv = setup; 1798 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 1801 stat->td.td_flags = HTOO32( 1802 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1803 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1804 stat->td.td_cbp = 0; 1805 stat->nexttd = tail; 1806 stat->td.td_nexttd = HTOO32(tail->physaddr); 1807 stat->td.td_be = 0; 1808 stat->flags = OHCI_CALL_DONE; 1809 stat->len = 0; 1810 stat->xfer = xfer; 1811 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1812 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1813 1814 #ifdef OHCI_DEBUG 1815 if (ohcidebug > 5) { 1816 DPRINTF(("ohci_device_request:\n")); 1817 ohci_dump_ed(sc, sed); 1818 ohci_dump_tds(sc, setup); 1819 } 1820 #endif 1821 1822 /* Insert ED in schedule */ 1823 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1824 usb_syncmem(&sed->dma, 1825 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1826 sizeof(sed->ed.ed_tailp), 1827 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1828 opipe->tail.td = tail; 1829 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1830 if (xfer->timeout && !sc->sc_bus.use_polling) { 1831 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1832 ohci_timeout, xfer); 1833 } 1834 1835 #ifdef OHCI_DEBUG 1836 if (ohcidebug > 20) { 1837 delay(10000); 1838 DPRINTF(("ohci_device_request: status=%x\n", 1839 OREAD4(sc, OHCI_COMMAND_STATUS))); 1840 ohci_dumpregs(sc); 1841 printf("ctrl head:\n"); 1842 ohci_dump_ed(sc, sc->sc_ctrl_head); 1843 printf("sed:\n"); 1844 ohci_dump_ed(sc, sed); 1845 ohci_dump_tds(sc, setup); 1846 } 1847 #endif 1848 1849 return (USBD_NORMAL_COMPLETION); 1850 1851 bad3: 1852 ohci_free_std(sc, tail); 1853 bad2: 1854 ohci_free_std(sc, stat); 1855 bad1: 1856 return (err); 1857 } 1858 1859 /* 1860 * Add an ED to the schedule. Called with USB lock held. 1861 */ 1862 Static void 1863 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1864 { 1865 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1866 1867 KASSERT(mutex_owned(&sc->sc_lock)); 1868 1869 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1870 sizeof(head->ed.ed_nexted), 1871 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1872 sed->next = head->next; 1873 sed->ed.ed_nexted = head->ed.ed_nexted; 1874 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1875 sizeof(sed->ed.ed_nexted), 1876 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1877 head->next = sed; 1878 head->ed.ed_nexted = HTOO32(sed->physaddr); 1879 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1880 sizeof(head->ed.ed_nexted), 1881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1882 } 1883 1884 /* 1885 * Remove an ED from the schedule. Called with USB lock held. 1886 */ 1887 Static void 1888 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1889 { 1890 ohci_soft_ed_t *p; 1891 1892 KASSERT(mutex_owned(&sc->sc_lock)); 1893 1894 /* XXX */ 1895 for (p = head; p != NULL && p->next != sed; p = p->next) 1896 ; 1897 if (p == NULL) 1898 panic("ohci_rem_ed: ED not found"); 1899 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1900 sizeof(sed->ed.ed_nexted), 1901 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1902 p->next = sed->next; 1903 p->ed.ed_nexted = sed->ed.ed_nexted; 1904 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1905 sizeof(p->ed.ed_nexted), 1906 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1907 } 1908 1909 /* 1910 * When a transfer is completed the TD is added to the done queue by 1911 * the host controller. This queue is the processed by software. 1912 * Unfortunately the queue contains the physical address of the TD 1913 * and we have no simple way to translate this back to a kernel address. 1914 * To make the translation possible (and fast) we use a hash table of 1915 * TDs currently in the schedule. The physical address is used as the 1916 * hash value. 1917 */ 1918 1919 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1920 /* Called with USB lock held. */ 1921 void 1922 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1923 { 1924 int h = HASH(std->physaddr); 1925 1926 KASSERT(mutex_owned(&sc->sc_lock)); 1927 1928 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1929 } 1930 1931 /* Called with USB lock held. */ 1932 void 1933 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1934 { 1935 1936 KASSERT(mutex_owned(&sc->sc_lock)); 1937 1938 LIST_REMOVE(std, hnext); 1939 } 1940 1941 ohci_soft_td_t * 1942 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1943 { 1944 int h = HASH(a); 1945 ohci_soft_td_t *std; 1946 1947 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1948 std != NULL; 1949 std = LIST_NEXT(std, hnext)) 1950 if (std->physaddr == a) 1951 return (std); 1952 return (NULL); 1953 } 1954 1955 /* Called with USB lock held. */ 1956 void 1957 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1958 { 1959 int h = HASH(sitd->physaddr); 1960 1961 KASSERT(mutex_owned(&sc->sc_lock)); 1962 1963 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1964 sitd, (u_long)sitd->physaddr)); 1965 1966 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1967 } 1968 1969 /* Called with USB lock held. */ 1970 void 1971 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1972 { 1973 1974 KASSERT(mutex_owned(&sc->sc_lock)); 1975 1976 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1977 sitd, (u_long)sitd->physaddr)); 1978 1979 LIST_REMOVE(sitd, hnext); 1980 } 1981 1982 ohci_soft_itd_t * 1983 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1984 { 1985 int h = HASH(a); 1986 ohci_soft_itd_t *sitd; 1987 1988 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1989 sitd != NULL; 1990 sitd = LIST_NEXT(sitd, hnext)) 1991 if (sitd->physaddr == a) 1992 return (sitd); 1993 return (NULL); 1994 } 1995 1996 void 1997 ohci_timeout(void *addr) 1998 { 1999 struct ohci_xfer *oxfer = addr; 2000 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 2001 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2002 2003 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 2004 2005 if (sc->sc_dying) { 2006 mutex_enter(&sc->sc_lock); 2007 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 2008 mutex_exit(&sc->sc_lock); 2009 return; 2010 } 2011 2012 /* Execute the abort in a process context. */ 2013 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr); 2014 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2015 USB_TASKQ_HC); 2016 } 2017 2018 void 2019 ohci_timeout_task(void *addr) 2020 { 2021 usbd_xfer_handle xfer = addr; 2022 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2023 2024 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2025 2026 mutex_enter(&sc->sc_lock); 2027 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2028 mutex_exit(&sc->sc_lock); 2029 } 2030 2031 #ifdef OHCI_DEBUG 2032 void 2033 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2034 { 2035 for (; std; std = std->nexttd) 2036 ohci_dump_td(sc, std); 2037 } 2038 2039 void 2040 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2041 { 2042 char sbuf[128]; 2043 2044 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2046 snprintb(sbuf, sizeof(sbuf), 2047 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2048 (u_int32_t)O32TOH(std->td.td_flags)); 2049 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2050 "nexttd=0x%08lx be=0x%08lx\n", 2051 std, (u_long)std->physaddr, sbuf, 2052 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2053 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2054 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2055 (u_long)O32TOH(std->td.td_cbp), 2056 (u_long)O32TOH(std->td.td_nexttd), 2057 (u_long)O32TOH(std->td.td_be)); 2058 } 2059 2060 void 2061 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2062 { 2063 int i; 2064 2065 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2066 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2067 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2068 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2069 sitd, (u_long)sitd->physaddr, 2070 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2071 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2072 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2073 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2074 (u_long)O32TOH(sitd->itd.itd_bp0), 2075 (u_long)O32TOH(sitd->itd.itd_nextitd), 2076 (u_long)O32TOH(sitd->itd.itd_be)); 2077 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2078 printf("offs[%d]=0x%04x ", i, 2079 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2080 printf("\n"); 2081 } 2082 2083 void 2084 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2085 { 2086 for (; sitd; sitd = sitd->nextitd) 2087 ohci_dump_itd(sc, sitd); 2088 } 2089 2090 void 2091 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2092 { 2093 char sbuf[128], sbuf2[128]; 2094 2095 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2096 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2097 snprintb(sbuf, sizeof(sbuf), 2098 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2099 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2100 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2101 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2102 2103 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2104 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2105 sed, (u_long)sed->physaddr, 2106 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2107 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2108 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2109 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2110 (u_long)O32TOH(sed->ed.ed_headp), 2111 (u_long)O32TOH(sed->ed.ed_nexted)); 2112 } 2113 #endif 2114 2115 usbd_status 2116 ohci_open(usbd_pipe_handle pipe) 2117 { 2118 usbd_device_handle dev = pipe->device; 2119 ohci_softc_t *sc = dev->bus->hci_private; 2120 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2121 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2122 u_int8_t addr = dev->address; 2123 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2124 ohci_soft_ed_t *sed; 2125 ohci_soft_td_t *std; 2126 ohci_soft_itd_t *sitd; 2127 ohci_physaddr_t tdphys; 2128 u_int32_t fmt; 2129 usbd_status err = USBD_NOMEM; 2130 int ival; 2131 2132 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2133 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2134 2135 if (sc->sc_dying) { 2136 err = USBD_IOERROR; 2137 goto bad0; 2138 } 2139 2140 std = NULL; 2141 sed = NULL; 2142 2143 if (addr == sc->sc_addr) { 2144 switch (ed->bEndpointAddress) { 2145 case USB_CONTROL_ENDPOINT: 2146 pipe->methods = &ohci_root_ctrl_methods; 2147 break; 2148 case UE_DIR_IN | OHCI_INTR_ENDPT: 2149 pipe->methods = &ohci_root_intr_methods; 2150 break; 2151 default: 2152 err = USBD_INVAL; 2153 goto bad0; 2154 } 2155 } else { 2156 sed = ohci_alloc_sed(sc); 2157 if (sed == NULL) 2158 goto bad0; 2159 opipe->sed = sed; 2160 if (xfertype == UE_ISOCHRONOUS) { 2161 mutex_enter(&sc->sc_lock); 2162 sitd = ohci_alloc_sitd(sc); 2163 mutex_exit(&sc->sc_lock); 2164 if (sitd == NULL) 2165 goto bad1; 2166 opipe->tail.itd = sitd; 2167 tdphys = sitd->physaddr; 2168 fmt = OHCI_ED_FORMAT_ISO; 2169 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2170 fmt |= OHCI_ED_DIR_IN; 2171 else 2172 fmt |= OHCI_ED_DIR_OUT; 2173 } else { 2174 mutex_enter(&sc->sc_lock); 2175 std = ohci_alloc_std(sc); 2176 mutex_exit(&sc->sc_lock); 2177 if (std == NULL) 2178 goto bad1; 2179 opipe->tail.td = std; 2180 tdphys = std->physaddr; 2181 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2182 } 2183 sed->ed.ed_flags = HTOO32( 2184 OHCI_ED_SET_FA(addr) | 2185 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2186 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2187 fmt | 2188 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2189 sed->ed.ed_headp = HTOO32(tdphys | 2190 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2191 sed->ed.ed_tailp = HTOO32(tdphys); 2192 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2194 2195 switch (xfertype) { 2196 case UE_CONTROL: 2197 pipe->methods = &ohci_device_ctrl_methods; 2198 err = usb_allocmem(&sc->sc_bus, 2199 sizeof(usb_device_request_t), 2200 0, &opipe->u.ctl.reqdma); 2201 if (err) 2202 goto bad; 2203 mutex_enter(&sc->sc_lock); 2204 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2205 mutex_exit(&sc->sc_lock); 2206 break; 2207 case UE_INTERRUPT: 2208 pipe->methods = &ohci_device_intr_methods; 2209 ival = pipe->interval; 2210 if (ival == USBD_DEFAULT_INTERVAL) 2211 ival = ed->bInterval; 2212 return (ohci_device_setintr(sc, opipe, ival)); 2213 case UE_ISOCHRONOUS: 2214 pipe->methods = &ohci_device_isoc_methods; 2215 return (ohci_setup_isoc(pipe)); 2216 case UE_BULK: 2217 pipe->methods = &ohci_device_bulk_methods; 2218 mutex_enter(&sc->sc_lock); 2219 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2220 mutex_exit(&sc->sc_lock); 2221 break; 2222 } 2223 } 2224 2225 return USBD_NORMAL_COMPLETION; 2226 2227 bad: 2228 if (std != NULL) 2229 ohci_free_std(sc, std); 2230 bad1: 2231 if (sed != NULL) 2232 ohci_free_sed(sc, sed); 2233 bad0: 2234 return err; 2235 2236 } 2237 2238 /* 2239 * Close a reqular pipe. 2240 * Assumes that there are no pending transactions. 2241 */ 2242 void 2243 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2244 { 2245 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2246 ohci_softc_t *sc = pipe->device->bus->hci_private; 2247 ohci_soft_ed_t *sed = opipe->sed; 2248 2249 KASSERT(mutex_owned(&sc->sc_lock)); 2250 2251 #ifdef DIAGNOSTIC 2252 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2253 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2254 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2255 ohci_soft_td_t *std; 2256 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2257 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2258 "tl=0x%x pipe=%p, std=%p\n", sed, 2259 (int)O32TOH(sed->ed.ed_headp), 2260 (int)O32TOH(sed->ed.ed_tailp), 2261 pipe, std); 2262 #ifdef USB_DEBUG 2263 usbd_dump_pipe(&opipe->pipe); 2264 #endif 2265 #ifdef OHCI_DEBUG 2266 ohci_dump_ed(sc, sed); 2267 if (std) 2268 ohci_dump_td(sc, std); 2269 #endif 2270 usb_delay_ms(&sc->sc_bus, 2); 2271 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2272 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2273 printf("ohci_close_pipe: pipe still not empty\n"); 2274 } 2275 #endif 2276 ohci_rem_ed(sc, sed, head); 2277 /* Make sure the host controller is not touching this ED */ 2278 usb_delay_ms(&sc->sc_bus, 1); 2279 pipe->endpoint->datatoggle = 2280 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2281 ohci_free_sed(sc, opipe->sed); 2282 } 2283 2284 /* 2285 * Abort a device request. 2286 * If this routine is called at splusb() it guarantees that the request 2287 * will be removed from the hardware scheduling and that the callback 2288 * for it will be called with USBD_CANCELLED status. 2289 * It's impossible to guarantee that the requested transfer will not 2290 * have happened since the hardware runs concurrently. 2291 * If the transaction has already happened we rely on the ordinary 2292 * interrupt processing to process it. 2293 * XXX This is most probably wrong. 2294 * XXXMRG this doesn't make sense anymore. 2295 */ 2296 void 2297 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2298 { 2299 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2300 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2301 ohci_soft_ed_t *sed = opipe->sed; 2302 ohci_soft_td_t *p, *n; 2303 ohci_physaddr_t headp; 2304 int hit; 2305 int wake; 2306 2307 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2308 2309 KASSERT(mutex_owned(&sc->sc_lock)); 2310 2311 if (sc->sc_dying) { 2312 /* If we're dying, just do the software part. */ 2313 xfer->status = status; /* make software ignore it */ 2314 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2315 usb_transfer_complete(xfer); 2316 return; 2317 } 2318 2319 if (cpu_intr_p() || cpu_softintr_p()) 2320 panic("ohci_abort_xfer: not in process context"); 2321 2322 /* 2323 * If an abort is already in progress then just wait for it to 2324 * complete and return. 2325 */ 2326 if (xfer->hcflags & UXFER_ABORTING) { 2327 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2328 #ifdef DIAGNOSTIC 2329 if (status == USBD_TIMEOUT) 2330 printf("0hci_abort_xfer: TIMEOUT while aborting\n"); 2331 #endif 2332 /* Override the status which might be USBD_TIMEOUT. */ 2333 xfer->status = status; 2334 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2335 xfer->hcflags |= UXFER_ABORTWAIT; 2336 while (xfer->hcflags & UXFER_ABORTING) 2337 cv_wait(&xfer->hccv, &sc->sc_lock); 2338 goto done; 2339 return; 2340 } 2341 xfer->hcflags |= UXFER_ABORTING; 2342 2343 /* 2344 * Step 1: Make interrupt routine and hardware ignore xfer. 2345 */ 2346 xfer->status = status; /* make software ignore it */ 2347 callout_stop(&xfer->timeout_handle); 2348 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2349 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2350 sizeof(sed->ed.ed_flags), 2351 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2352 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2353 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2354 sizeof(sed->ed.ed_flags), 2355 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2356 2357 /* 2358 * Step 2: Wait until we know hardware has finished any possible 2359 * use of the xfer. Also make sure the soft interrupt routine 2360 * has run. 2361 */ 2362 /* Hardware finishes in 1ms */ 2363 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2364 sc->sc_softwake = 1; 2365 usb_schedsoftintr(&sc->sc_bus); 2366 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2367 2368 /* 2369 * Step 3: Remove any vestiges of the xfer from the hardware. 2370 * The complication here is that the hardware may have executed 2371 * beyond the xfer we're trying to abort. So as we're scanning 2372 * the TDs of this xfer we check if the hardware points to 2373 * any of them. 2374 */ 2375 p = xfer->hcpriv; 2376 #ifdef DIAGNOSTIC 2377 if (p == NULL) { 2378 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2379 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2380 goto done; 2381 } 2382 #endif 2383 #ifdef OHCI_DEBUG 2384 if (ohcidebug > 1) { 2385 DPRINTF(("ohci_abort_xfer: sed=\n")); 2386 ohci_dump_ed(sc, sed); 2387 ohci_dump_tds(sc, p); 2388 } 2389 #endif 2390 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2391 hit = 0; 2392 for (; p->xfer == xfer; p = n) { 2393 hit |= headp == p->physaddr; 2394 n = p->nexttd; 2395 ohci_free_std(sc, p); 2396 } 2397 /* Zap headp register if hardware pointed inside the xfer. */ 2398 if (hit) { 2399 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2400 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2401 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2402 usb_syncmem(&sed->dma, 2403 sed->offs + offsetof(ohci_ed_t, ed_headp), 2404 sizeof(sed->ed.ed_headp), 2405 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2406 } else { 2407 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2408 } 2409 2410 /* 2411 * Step 4: Turn on hardware again. 2412 */ 2413 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2414 sizeof(sed->ed.ed_flags), 2415 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2416 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2417 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2418 sizeof(sed->ed.ed_flags), 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 2421 /* 2422 * Step 5: Execute callback. 2423 */ 2424 wake = xfer->hcflags & UXFER_ABORTWAIT; 2425 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2426 usb_transfer_complete(xfer); 2427 if (wake) 2428 cv_broadcast(&xfer->hccv); 2429 2430 done: 2431 KASSERT(mutex_owned(&sc->sc_lock)); 2432 } 2433 2434 /* 2435 * Data structures and routines to emulate the root hub. 2436 */ 2437 Static usb_device_descriptor_t ohci_devd = { 2438 USB_DEVICE_DESCRIPTOR_SIZE, 2439 UDESC_DEVICE, /* type */ 2440 {0x00, 0x01}, /* USB version */ 2441 UDCLASS_HUB, /* class */ 2442 UDSUBCLASS_HUB, /* subclass */ 2443 UDPROTO_FSHUB, /* protocol */ 2444 64, /* max packet */ 2445 {0},{0},{0x00,0x01}, /* device id */ 2446 1,2,0, /* string indicies */ 2447 1 /* # of configurations */ 2448 }; 2449 2450 Static const usb_config_descriptor_t ohci_confd = { 2451 USB_CONFIG_DESCRIPTOR_SIZE, 2452 UDESC_CONFIG, 2453 {USB_CONFIG_DESCRIPTOR_SIZE + 2454 USB_INTERFACE_DESCRIPTOR_SIZE + 2455 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2456 1, 2457 1, 2458 0, 2459 UC_ATTR_MBO | UC_SELF_POWERED, 2460 0 /* max power */ 2461 }; 2462 2463 Static const usb_interface_descriptor_t ohci_ifcd = { 2464 USB_INTERFACE_DESCRIPTOR_SIZE, 2465 UDESC_INTERFACE, 2466 0, 2467 0, 2468 1, 2469 UICLASS_HUB, 2470 UISUBCLASS_HUB, 2471 UIPROTO_FSHUB, 2472 0 2473 }; 2474 2475 Static const usb_endpoint_descriptor_t ohci_endpd = { 2476 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2477 .bDescriptorType = UDESC_ENDPOINT, 2478 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2479 .bmAttributes = UE_INTERRUPT, 2480 .wMaxPacketSize = {8, 0}, /* max packet */ 2481 .bInterval = 255, 2482 }; 2483 2484 Static const usb_hub_descriptor_t ohci_hubd = { 2485 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2486 .bDescriptorType = UDESC_HUB, 2487 }; 2488 2489 /* 2490 * Simulate a hardware hub by handling all the necessary requests. 2491 */ 2492 Static usbd_status 2493 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2494 { 2495 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2496 usbd_status err; 2497 2498 /* Insert last in queue. */ 2499 mutex_enter(&sc->sc_lock); 2500 err = usb_insert_transfer(xfer); 2501 mutex_exit(&sc->sc_lock); 2502 if (err) 2503 return (err); 2504 2505 /* Pipe isn't running, start first */ 2506 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2507 } 2508 2509 Static usbd_status 2510 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2511 { 2512 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2513 usb_device_request_t *req; 2514 void *buf = NULL; 2515 int port, i; 2516 int len, value, index, l, totlen = 0; 2517 usb_port_status_t ps; 2518 usb_hub_descriptor_t hubd; 2519 usbd_status err; 2520 u_int32_t v; 2521 2522 if (sc->sc_dying) 2523 return (USBD_IOERROR); 2524 2525 #ifdef DIAGNOSTIC 2526 if (!(xfer->rqflags & URQ_REQUEST)) 2527 /* XXX panic */ 2528 return (USBD_INVAL); 2529 #endif 2530 req = &xfer->request; 2531 2532 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2533 req->bmRequestType, req->bRequest)); 2534 2535 len = UGETW(req->wLength); 2536 value = UGETW(req->wValue); 2537 index = UGETW(req->wIndex); 2538 2539 if (len != 0) 2540 buf = KERNADDR(&xfer->dmabuf, 0); 2541 2542 #define C(x,y) ((x) | ((y) << 8)) 2543 switch(C(req->bRequest, req->bmRequestType)) { 2544 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2545 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2546 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2547 /* 2548 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2549 * for the integrated root hub. 2550 */ 2551 break; 2552 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2553 if (len > 0) { 2554 *(u_int8_t *)buf = sc->sc_conf; 2555 totlen = 1; 2556 } 2557 break; 2558 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2559 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2560 if (len == 0) 2561 break; 2562 switch(value >> 8) { 2563 case UDESC_DEVICE: 2564 if ((value & 0xff) != 0) { 2565 err = USBD_IOERROR; 2566 goto ret; 2567 } 2568 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2569 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2570 memcpy(buf, &ohci_devd, l); 2571 break; 2572 case UDESC_CONFIG: 2573 if ((value & 0xff) != 0) { 2574 err = USBD_IOERROR; 2575 goto ret; 2576 } 2577 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2578 memcpy(buf, &ohci_confd, l); 2579 buf = (char *)buf + l; 2580 len -= l; 2581 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2582 totlen += l; 2583 memcpy(buf, &ohci_ifcd, l); 2584 buf = (char *)buf + l; 2585 len -= l; 2586 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2587 totlen += l; 2588 memcpy(buf, &ohci_endpd, l); 2589 break; 2590 case UDESC_STRING: 2591 #define sd ((usb_string_descriptor_t *)buf) 2592 switch (value & 0xff) { 2593 case 0: /* Language table */ 2594 totlen = usb_makelangtbl(sd, len); 2595 break; 2596 case 1: /* Vendor */ 2597 totlen = usb_makestrdesc(sd, len, 2598 sc->sc_vendor); 2599 break; 2600 case 2: /* Product */ 2601 totlen = usb_makestrdesc(sd, len, 2602 "OHCI root hub"); 2603 break; 2604 } 2605 #undef sd 2606 break; 2607 default: 2608 err = USBD_IOERROR; 2609 goto ret; 2610 } 2611 break; 2612 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2613 if (len > 0) { 2614 *(u_int8_t *)buf = 0; 2615 totlen = 1; 2616 } 2617 break; 2618 case C(UR_GET_STATUS, UT_READ_DEVICE): 2619 if (len > 1) { 2620 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2621 totlen = 2; 2622 } 2623 break; 2624 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2625 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2626 if (len > 1) { 2627 USETW(((usb_status_t *)buf)->wStatus, 0); 2628 totlen = 2; 2629 } 2630 break; 2631 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2632 if (value >= USB_MAX_DEVICES) { 2633 err = USBD_IOERROR; 2634 goto ret; 2635 } 2636 sc->sc_addr = value; 2637 break; 2638 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2639 if (value != 0 && value != 1) { 2640 err = USBD_IOERROR; 2641 goto ret; 2642 } 2643 sc->sc_conf = value; 2644 break; 2645 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2646 break; 2647 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2648 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2649 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2650 err = USBD_IOERROR; 2651 goto ret; 2652 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2653 break; 2654 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2655 break; 2656 /* Hub requests */ 2657 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2658 break; 2659 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2660 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2661 "port=%d feature=%d\n", 2662 index, value)); 2663 if (index < 1 || index > sc->sc_noport) { 2664 err = USBD_IOERROR; 2665 goto ret; 2666 } 2667 port = OHCI_RH_PORT_STATUS(index); 2668 switch(value) { 2669 case UHF_PORT_ENABLE: 2670 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2671 break; 2672 case UHF_PORT_SUSPEND: 2673 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2674 break; 2675 case UHF_PORT_POWER: 2676 /* Yes, writing to the LOW_SPEED bit clears power. */ 2677 OWRITE4(sc, port, UPS_LOW_SPEED); 2678 break; 2679 case UHF_C_PORT_CONNECTION: 2680 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2681 break; 2682 case UHF_C_PORT_ENABLE: 2683 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2684 break; 2685 case UHF_C_PORT_SUSPEND: 2686 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2687 break; 2688 case UHF_C_PORT_OVER_CURRENT: 2689 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2690 break; 2691 case UHF_C_PORT_RESET: 2692 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2693 break; 2694 default: 2695 err = USBD_IOERROR; 2696 goto ret; 2697 } 2698 switch(value) { 2699 case UHF_C_PORT_CONNECTION: 2700 case UHF_C_PORT_ENABLE: 2701 case UHF_C_PORT_SUSPEND: 2702 case UHF_C_PORT_OVER_CURRENT: 2703 case UHF_C_PORT_RESET: 2704 /* Enable RHSC interrupt if condition is cleared. */ 2705 if ((OREAD4(sc, port) >> 16) == 0) 2706 ohci_rhsc_enable(sc); 2707 break; 2708 default: 2709 break; 2710 } 2711 break; 2712 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2713 if (len == 0) 2714 break; 2715 if ((value & 0xff) != 0) { 2716 err = USBD_IOERROR; 2717 goto ret; 2718 } 2719 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2720 hubd = ohci_hubd; 2721 hubd.bNbrPorts = sc->sc_noport; 2722 USETW(hubd.wHubCharacteristics, 2723 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2724 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2725 /* XXX overcurrent */ 2726 ); 2727 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2728 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2729 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2730 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2731 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2732 l = min(len, hubd.bDescLength); 2733 totlen = l; 2734 memcpy(buf, &hubd, l); 2735 break; 2736 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2737 if (len != 4) { 2738 err = USBD_IOERROR; 2739 goto ret; 2740 } 2741 memset(buf, 0, len); /* ? XXX */ 2742 totlen = len; 2743 break; 2744 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2745 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2746 index)); 2747 if (index < 1 || index > sc->sc_noport) { 2748 err = USBD_IOERROR; 2749 goto ret; 2750 } 2751 if (len != 4) { 2752 err = USBD_IOERROR; 2753 goto ret; 2754 } 2755 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2756 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2757 v)); 2758 USETW(ps.wPortStatus, v); 2759 USETW(ps.wPortChange, v >> 16); 2760 l = min(len, sizeof ps); 2761 memcpy(buf, &ps, l); 2762 totlen = l; 2763 break; 2764 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2765 err = USBD_IOERROR; 2766 goto ret; 2767 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2768 break; 2769 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2770 if (index < 1 || index > sc->sc_noport) { 2771 err = USBD_IOERROR; 2772 goto ret; 2773 } 2774 port = OHCI_RH_PORT_STATUS(index); 2775 switch(value) { 2776 case UHF_PORT_ENABLE: 2777 OWRITE4(sc, port, UPS_PORT_ENABLED); 2778 break; 2779 case UHF_PORT_SUSPEND: 2780 OWRITE4(sc, port, UPS_SUSPEND); 2781 break; 2782 case UHF_PORT_RESET: 2783 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2784 index)); 2785 OWRITE4(sc, port, UPS_RESET); 2786 for (i = 0; i < 5; i++) { 2787 usb_delay_ms(&sc->sc_bus, 2788 USB_PORT_ROOT_RESET_DELAY); 2789 if (sc->sc_dying) { 2790 err = USBD_IOERROR; 2791 goto ret; 2792 } 2793 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2794 break; 2795 } 2796 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2797 index, OREAD4(sc, port))); 2798 break; 2799 case UHF_PORT_POWER: 2800 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2801 "%d\n", index)); 2802 OWRITE4(sc, port, UPS_PORT_POWER); 2803 break; 2804 default: 2805 err = USBD_IOERROR; 2806 goto ret; 2807 } 2808 break; 2809 default: 2810 err = USBD_IOERROR; 2811 goto ret; 2812 } 2813 xfer->actlen = totlen; 2814 err = USBD_NORMAL_COMPLETION; 2815 ret: 2816 xfer->status = err; 2817 mutex_enter(&sc->sc_lock); 2818 usb_transfer_complete(xfer); 2819 mutex_exit(&sc->sc_lock); 2820 return (USBD_IN_PROGRESS); 2821 } 2822 2823 /* Abort a root control request. */ 2824 Static void 2825 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2826 { 2827 /* Nothing to do, all transfers are synchronous. */ 2828 } 2829 2830 /* Close the root pipe. */ 2831 Static void 2832 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2833 { 2834 DPRINTF(("ohci_root_ctrl_close\n")); 2835 /* Nothing to do. */ 2836 } 2837 2838 Static usbd_status 2839 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2840 { 2841 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2842 usbd_status err; 2843 2844 /* Insert last in queue. */ 2845 mutex_enter(&sc->sc_lock); 2846 err = usb_insert_transfer(xfer); 2847 mutex_exit(&sc->sc_lock); 2848 if (err) 2849 return (err); 2850 2851 /* Pipe isn't running, start first */ 2852 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2853 } 2854 2855 Static usbd_status 2856 ohci_root_intr_start(usbd_xfer_handle xfer) 2857 { 2858 usbd_pipe_handle pipe = xfer->pipe; 2859 ohci_softc_t *sc = pipe->device->bus->hci_private; 2860 2861 if (sc->sc_dying) 2862 return (USBD_IOERROR); 2863 2864 mutex_enter(&sc->sc_lock); 2865 KASSERT(sc->sc_intrxfer == NULL); 2866 sc->sc_intrxfer = xfer; 2867 mutex_exit(&sc->sc_lock); 2868 2869 return (USBD_IN_PROGRESS); 2870 } 2871 2872 /* Abort a root interrupt request. */ 2873 Static void 2874 ohci_root_intr_abort(usbd_xfer_handle xfer) 2875 { 2876 #ifdef DIAGNOSTIC 2877 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2878 #endif 2879 2880 KASSERT(mutex_owned(&sc->sc_lock)); 2881 2882 if (xfer->pipe->intrxfer == xfer) { 2883 DPRINTF(("ohci_root_intr_abort: remove\n")); 2884 xfer->pipe->intrxfer = NULL; 2885 } 2886 xfer->status = USBD_CANCELLED; 2887 usb_transfer_complete(xfer); 2888 } 2889 2890 /* Close the root pipe. */ 2891 Static void 2892 ohci_root_intr_close(usbd_pipe_handle pipe) 2893 { 2894 ohci_softc_t *sc = pipe->device->bus->hci_private; 2895 2896 KASSERT(mutex_owned(&sc->sc_lock)); 2897 2898 DPRINTF(("ohci_root_intr_close\n")); 2899 2900 sc->sc_intrxfer = NULL; 2901 } 2902 2903 /************************/ 2904 2905 Static usbd_status 2906 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2907 { 2908 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2909 usbd_status err; 2910 2911 /* Insert last in queue. */ 2912 mutex_enter(&sc->sc_lock); 2913 err = usb_insert_transfer(xfer); 2914 mutex_exit(&sc->sc_lock); 2915 if (err) 2916 return (err); 2917 2918 /* Pipe isn't running, start first */ 2919 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2920 } 2921 2922 Static usbd_status 2923 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2924 { 2925 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2926 usbd_status err; 2927 2928 if (sc->sc_dying) 2929 return (USBD_IOERROR); 2930 2931 #ifdef DIAGNOSTIC 2932 if (!(xfer->rqflags & URQ_REQUEST)) { 2933 /* XXX panic */ 2934 printf("ohci_device_ctrl_transfer: not a request\n"); 2935 return (USBD_INVAL); 2936 } 2937 #endif 2938 2939 mutex_enter(&sc->sc_lock); 2940 err = ohci_device_request(xfer); 2941 mutex_exit(&sc->sc_lock); 2942 if (err) 2943 return (err); 2944 2945 if (sc->sc_bus.use_polling) 2946 ohci_waitintr(sc, xfer); 2947 return (USBD_IN_PROGRESS); 2948 } 2949 2950 /* Abort a device control request. */ 2951 Static void 2952 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2953 { 2954 #ifdef DIAGNOSTIC 2955 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2956 #endif 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2961 ohci_abort_xfer(xfer, USBD_CANCELLED); 2962 } 2963 2964 /* Close a device control pipe. */ 2965 Static void 2966 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2967 { 2968 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2969 ohci_softc_t *sc = pipe->device->bus->hci_private; 2970 2971 KASSERT(mutex_owned(&sc->sc_lock)); 2972 2973 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2974 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2975 ohci_free_std(sc, opipe->tail.td); 2976 } 2977 2978 /************************/ 2979 2980 Static void 2981 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2982 { 2983 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2984 ohci_softc_t *sc = pipe->device->bus->hci_private; 2985 2986 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2987 } 2988 2989 Static void 2990 ohci_noop(usbd_pipe_handle pipe) 2991 { 2992 } 2993 2994 Static usbd_status 2995 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2996 { 2997 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2998 usbd_status err; 2999 3000 /* Insert last in queue. */ 3001 mutex_enter(&sc->sc_lock); 3002 err = usb_insert_transfer(xfer); 3003 mutex_exit(&sc->sc_lock); 3004 if (err) 3005 return (err); 3006 3007 /* Pipe isn't running, start first */ 3008 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3009 } 3010 3011 Static usbd_status 3012 ohci_device_bulk_start(usbd_xfer_handle xfer) 3013 { 3014 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3015 usbd_device_handle dev = opipe->pipe.device; 3016 ohci_softc_t *sc = dev->bus->hci_private; 3017 int addr = dev->address; 3018 ohci_soft_td_t *data, *tail, *tdp; 3019 ohci_soft_ed_t *sed; 3020 int len, isread, endpt; 3021 usbd_status err; 3022 3023 if (sc->sc_dying) 3024 return (USBD_IOERROR); 3025 3026 #ifdef DIAGNOSTIC 3027 if (xfer->rqflags & URQ_REQUEST) { 3028 /* XXX panic */ 3029 printf("ohci_device_bulk_start: a request\n"); 3030 return (USBD_INVAL); 3031 } 3032 #endif 3033 3034 mutex_enter(&sc->sc_lock); 3035 3036 len = xfer->length; 3037 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3038 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3039 sed = opipe->sed; 3040 3041 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3042 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3043 endpt)); 3044 3045 opipe->u.bulk.isread = isread; 3046 opipe->u.bulk.length = len; 3047 3048 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3049 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3050 /* Update device address */ 3051 sed->ed.ed_flags = HTOO32( 3052 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3053 OHCI_ED_SET_FA(addr)); 3054 3055 /* Allocate a chain of new TDs (including a new tail). */ 3056 data = opipe->tail.td; 3057 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3058 data, &tail); 3059 /* We want interrupt at the end of the transfer. */ 3060 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3061 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3062 tail->flags |= OHCI_CALL_DONE; 3063 tail = tail->nexttd; /* point at sentinel */ 3064 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3065 sizeof(tail->td.td_flags), 3066 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3067 if (err) { 3068 mutex_exit(&sc->sc_lock); 3069 return (err); 3070 } 3071 3072 tail->xfer = NULL; 3073 xfer->hcpriv = data; 3074 3075 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3076 "td_cbp=0x%08x td_be=0x%08x\n", 3077 (int)O32TOH(sed->ed.ed_flags), 3078 (int)O32TOH(data->td.td_flags), 3079 (int)O32TOH(data->td.td_cbp), 3080 (int)O32TOH(data->td.td_be))); 3081 3082 #ifdef OHCI_DEBUG 3083 if (ohcidebug > 5) { 3084 ohci_dump_ed(sc, sed); 3085 ohci_dump_tds(sc, data); 3086 } 3087 #endif 3088 3089 /* Insert ED in schedule */ 3090 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3091 tdp->xfer = xfer; 3092 } 3093 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3094 opipe->tail.td = tail; 3095 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3096 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3097 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3098 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3099 if (xfer->timeout && !sc->sc_bus.use_polling) { 3100 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3101 ohci_timeout, xfer); 3102 } 3103 mutex_exit(&sc->sc_lock); 3104 3105 #if 0 3106 /* This goes wrong if we are too slow. */ 3107 if (ohcidebug > 10) { 3108 delay(10000); 3109 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3110 OREAD4(sc, OHCI_COMMAND_STATUS))); 3111 ohci_dump_ed(sc, sed); 3112 ohci_dump_tds(sc, data); 3113 } 3114 #endif 3115 3116 return (USBD_IN_PROGRESS); 3117 } 3118 3119 Static void 3120 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3121 { 3122 #ifdef DIAGNOSTIC 3123 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3124 #endif 3125 3126 KASSERT(mutex_owned(&sc->sc_lock)); 3127 3128 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3129 ohci_abort_xfer(xfer, USBD_CANCELLED); 3130 } 3131 3132 /* 3133 * Close a device bulk pipe. 3134 */ 3135 Static void 3136 ohci_device_bulk_close(usbd_pipe_handle pipe) 3137 { 3138 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3139 ohci_softc_t *sc = pipe->device->bus->hci_private; 3140 3141 KASSERT(mutex_owned(&sc->sc_lock)); 3142 3143 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3144 ohci_close_pipe(pipe, sc->sc_bulk_head); 3145 ohci_free_std(sc, opipe->tail.td); 3146 } 3147 3148 /************************/ 3149 3150 Static usbd_status 3151 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3152 { 3153 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3154 usbd_status err; 3155 3156 /* Insert last in queue. */ 3157 mutex_enter(&sc->sc_lock); 3158 err = usb_insert_transfer(xfer); 3159 mutex_exit(&sc->sc_lock); 3160 if (err) 3161 return (err); 3162 3163 /* Pipe isn't running, start first */ 3164 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3165 } 3166 3167 Static usbd_status 3168 ohci_device_intr_start(usbd_xfer_handle xfer) 3169 { 3170 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3171 usbd_device_handle dev = opipe->pipe.device; 3172 ohci_softc_t *sc = dev->bus->hci_private; 3173 ohci_soft_ed_t *sed = opipe->sed; 3174 ohci_soft_td_t *data, *tail; 3175 int len, isread, endpt; 3176 3177 if (sc->sc_dying) 3178 return (USBD_IOERROR); 3179 3180 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3181 "flags=%d priv=%p\n", 3182 xfer, xfer->length, xfer->flags, xfer->priv)); 3183 3184 #ifdef DIAGNOSTIC 3185 if (xfer->rqflags & URQ_REQUEST) 3186 panic("ohci_device_intr_transfer: a request"); 3187 #endif 3188 3189 len = xfer->length; 3190 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3191 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3192 3193 data = opipe->tail.td; 3194 mutex_enter(&sc->sc_lock); 3195 tail = ohci_alloc_std(sc); 3196 mutex_exit(&sc->sc_lock); 3197 if (tail == NULL) 3198 return (USBD_NOMEM); 3199 tail->xfer = NULL; 3200 3201 data->td.td_flags = HTOO32( 3202 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3203 OHCI_TD_NOCC | 3204 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3205 if (xfer->flags & USBD_SHORT_XFER_OK) 3206 data->td.td_flags |= HTOO32(OHCI_TD_R); 3207 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3208 data->nexttd = tail; 3209 data->td.td_nexttd = HTOO32(tail->physaddr); 3210 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3211 data->len = len; 3212 data->xfer = xfer; 3213 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3214 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3215 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3216 xfer->hcpriv = data; 3217 3218 #ifdef OHCI_DEBUG 3219 if (ohcidebug > 5) { 3220 DPRINTF(("ohci_device_intr_transfer:\n")); 3221 ohci_dump_ed(sc, sed); 3222 ohci_dump_tds(sc, data); 3223 } 3224 #endif 3225 3226 /* Insert ED in schedule */ 3227 mutex_enter(&sc->sc_lock); 3228 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3229 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3230 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3231 opipe->tail.td = tail; 3232 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3233 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3234 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3235 3236 #if 0 3237 /* 3238 * This goes horribly wrong, printing thousands of descriptors, 3239 * because false references are followed due to the fact that the 3240 * TD is gone. 3241 */ 3242 if (ohcidebug > 5) { 3243 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3244 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3245 OREAD4(sc, OHCI_COMMAND_STATUS))); 3246 ohci_dump_ed(sc, sed); 3247 ohci_dump_tds(sc, data); 3248 } 3249 #endif 3250 mutex_exit(&sc->sc_lock); 3251 3252 return (USBD_IN_PROGRESS); 3253 } 3254 3255 /* Abort a device control request. */ 3256 Static void 3257 ohci_device_intr_abort(usbd_xfer_handle xfer) 3258 { 3259 #ifdef DIAGNOSTIC 3260 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3261 #endif 3262 3263 KASSERT(mutex_owned(&sc->sc_lock)); 3264 3265 if (xfer->pipe->intrxfer == xfer) { 3266 DPRINTF(("ohci_device_intr_abort: remove\n")); 3267 xfer->pipe->intrxfer = NULL; 3268 } 3269 ohci_abort_xfer(xfer, USBD_CANCELLED); 3270 } 3271 3272 /* Close a device interrupt pipe. */ 3273 Static void 3274 ohci_device_intr_close(usbd_pipe_handle pipe) 3275 { 3276 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3277 ohci_softc_t *sc = pipe->device->bus->hci_private; 3278 int nslots = opipe->u.intr.nslots; 3279 int pos = opipe->u.intr.pos; 3280 int j; 3281 ohci_soft_ed_t *p, *sed = opipe->sed; 3282 3283 KASSERT(mutex_owned(&sc->sc_lock)); 3284 3285 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3286 pipe, nslots, pos)); 3287 usb_syncmem(&sed->dma, sed->offs, 3288 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3289 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3290 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3291 sizeof(sed->ed.ed_flags), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3294 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3295 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3296 3297 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3298 continue; 3299 #ifdef DIAGNOSTIC 3300 if (p == NULL) 3301 panic("ohci_device_intr_close: ED not found"); 3302 #endif 3303 p->next = sed->next; 3304 p->ed.ed_nexted = sed->ed.ed_nexted; 3305 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3306 sizeof(p->ed.ed_nexted), 3307 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3308 3309 for (j = 0; j < nslots; j++) 3310 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3311 3312 ohci_free_std(sc, opipe->tail.td); 3313 ohci_free_sed(sc, opipe->sed); 3314 } 3315 3316 Static usbd_status 3317 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3318 { 3319 int i, j, best; 3320 u_int npoll, slow, shigh, nslots; 3321 u_int bestbw, bw; 3322 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3323 3324 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3325 if (ival == 0) { 3326 printf("ohci_setintr: 0 interval\n"); 3327 return (USBD_INVAL); 3328 } 3329 3330 npoll = OHCI_NO_INTRS; 3331 while (npoll > ival) 3332 npoll /= 2; 3333 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3334 3335 /* 3336 * We now know which level in the tree the ED must go into. 3337 * Figure out which slot has most bandwidth left over. 3338 * Slots to examine: 3339 * npoll 3340 * 1 0 3341 * 2 1 2 3342 * 4 3 4 5 6 3343 * 8 7 8 9 10 11 12 13 14 3344 * N (N-1) .. (N-1+N-1) 3345 */ 3346 slow = npoll-1; 3347 shigh = slow + npoll; 3348 nslots = OHCI_NO_INTRS / npoll; 3349 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3350 bw = 0; 3351 for (j = 0; j < nslots; j++) 3352 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3353 if (bw < bestbw) { 3354 best = i; 3355 bestbw = bw; 3356 } 3357 } 3358 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3359 best, slow, shigh, bestbw)); 3360 3361 mutex_enter(&sc->sc_lock); 3362 hsed = sc->sc_eds[best]; 3363 sed->next = hsed->next; 3364 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3365 sizeof(hsed->ed.ed_flags), 3366 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3367 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3368 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3369 sizeof(sed->ed.ed_flags), 3370 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3371 hsed->next = sed; 3372 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3373 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3374 sizeof(hsed->ed.ed_flags), 3375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3376 mutex_exit(&sc->sc_lock); 3377 3378 for (j = 0; j < nslots; j++) 3379 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3380 opipe->u.intr.nslots = nslots; 3381 opipe->u.intr.pos = best; 3382 3383 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3384 return (USBD_NORMAL_COMPLETION); 3385 } 3386 3387 /***********************/ 3388 3389 usbd_status 3390 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3391 { 3392 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3393 usbd_status err; 3394 3395 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3396 3397 /* Put it on our queue, */ 3398 mutex_enter(&sc->sc_lock); 3399 err = usb_insert_transfer(xfer); 3400 mutex_exit(&sc->sc_lock); 3401 3402 /* bail out on error, */ 3403 if (err && err != USBD_IN_PROGRESS) 3404 return (err); 3405 3406 /* XXX should check inuse here */ 3407 3408 /* insert into schedule, */ 3409 ohci_device_isoc_enter(xfer); 3410 3411 /* and start if the pipe wasn't running */ 3412 if (!err) 3413 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3414 3415 return (err); 3416 } 3417 3418 void 3419 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3420 { 3421 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3422 usbd_device_handle dev = opipe->pipe.device; 3423 ohci_softc_t *sc = dev->bus->hci_private; 3424 ohci_soft_ed_t *sed = opipe->sed; 3425 struct iso *iso = &opipe->u.iso; 3426 ohci_soft_itd_t *sitd, *nsitd; 3427 ohci_physaddr_t buf, offs, noffs, bp0; 3428 int i, ncur, nframes; 3429 3430 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3431 "nframes=%d\n", 3432 iso->inuse, iso->next, xfer, xfer->nframes)); 3433 3434 if (sc->sc_dying) 3435 return; 3436 3437 if (iso->next == -1) { 3438 /* Not in use yet, schedule it a few frames ahead. */ 3439 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3440 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3441 iso->next)); 3442 } 3443 3444 sitd = opipe->tail.itd; 3445 buf = DMAADDR(&xfer->dmabuf, 0); 3446 bp0 = OHCI_PAGE(buf); 3447 offs = OHCI_PAGE_OFFSET(buf); 3448 nframes = xfer->nframes; 3449 xfer->hcpriv = sitd; 3450 for (i = ncur = 0; i < nframes; i++, ncur++) { 3451 noffs = offs + xfer->frlengths[i]; 3452 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3453 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3454 3455 /* Allocate next ITD */ 3456 mutex_enter(&sc->sc_lock); 3457 nsitd = ohci_alloc_sitd(sc); 3458 mutex_exit(&sc->sc_lock); 3459 if (nsitd == NULL) { 3460 /* XXX what now? */ 3461 printf("%s: isoc TD alloc failed\n", 3462 device_xname(sc->sc_dev)); 3463 return; 3464 } 3465 3466 /* Fill current ITD */ 3467 sitd->itd.itd_flags = HTOO32( 3468 OHCI_ITD_NOCC | 3469 OHCI_ITD_SET_SF(iso->next) | 3470 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3471 OHCI_ITD_SET_FC(ncur)); 3472 sitd->itd.itd_bp0 = HTOO32(bp0); 3473 sitd->nextitd = nsitd; 3474 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3475 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3476 sitd->xfer = xfer; 3477 sitd->flags = 0; 3478 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3480 3481 sitd = nsitd; 3482 iso->next = iso->next + ncur; 3483 bp0 = OHCI_PAGE(buf + offs); 3484 ncur = 0; 3485 } 3486 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3487 offs = noffs; 3488 } 3489 mutex_enter(&sc->sc_lock); 3490 nsitd = ohci_alloc_sitd(sc); 3491 mutex_exit(&sc->sc_lock); 3492 if (nsitd == NULL) { 3493 /* XXX what now? */ 3494 printf("%s: isoc TD alloc failed\n", 3495 device_xname(sc->sc_dev)); 3496 return; 3497 } 3498 /* Fixup last used ITD */ 3499 sitd->itd.itd_flags = HTOO32( 3500 OHCI_ITD_NOCC | 3501 OHCI_ITD_SET_SF(iso->next) | 3502 OHCI_ITD_SET_DI(0) | 3503 OHCI_ITD_SET_FC(ncur)); 3504 sitd->itd.itd_bp0 = HTOO32(bp0); 3505 sitd->nextitd = nsitd; 3506 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3507 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3508 sitd->xfer = xfer; 3509 sitd->flags = OHCI_CALL_DONE; 3510 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3511 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3512 3513 iso->next = iso->next + ncur; 3514 iso->inuse += nframes; 3515 3516 xfer->actlen = offs; /* XXX pretend we did it all */ 3517 3518 xfer->status = USBD_IN_PROGRESS; 3519 3520 #ifdef OHCI_DEBUG 3521 if (ohcidebug > 5) { 3522 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3523 O32TOH(sc->sc_hcca->hcca_frame_number))); 3524 ohci_dump_itds(sc, xfer->hcpriv); 3525 ohci_dump_ed(sc, sed); 3526 } 3527 #endif 3528 3529 mutex_enter(&sc->sc_lock); 3530 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3531 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3532 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3533 opipe->tail.itd = nsitd; 3534 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3535 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3536 sizeof(sed->ed.ed_flags), 3537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3538 mutex_exit(&sc->sc_lock); 3539 3540 #ifdef OHCI_DEBUG 3541 if (ohcidebug > 5) { 3542 delay(150000); 3543 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3544 O32TOH(sc->sc_hcca->hcca_frame_number))); 3545 ohci_dump_itds(sc, xfer->hcpriv); 3546 ohci_dump_ed(sc, sed); 3547 } 3548 #endif 3549 } 3550 3551 usbd_status 3552 ohci_device_isoc_start(usbd_xfer_handle xfer) 3553 { 3554 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3555 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3556 3557 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3558 3559 mutex_enter(&sc->sc_lock); 3560 3561 if (sc->sc_dying) { 3562 mutex_exit(&sc->sc_lock); 3563 return (USBD_IOERROR); 3564 } 3565 3566 #ifdef DIAGNOSTIC 3567 if (xfer->status != USBD_IN_PROGRESS) 3568 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3569 #endif 3570 3571 /* XXX anything to do? */ 3572 3573 mutex_exit(&sc->sc_lock); 3574 3575 return (USBD_IN_PROGRESS); 3576 } 3577 3578 void 3579 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3580 { 3581 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3582 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3583 ohci_soft_ed_t *sed; 3584 ohci_soft_itd_t *sitd; 3585 3586 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3587 3588 KASSERT(mutex_owned(&sc->sc_lock)); 3589 3590 /* Transfer is already done. */ 3591 if (xfer->status != USBD_NOT_STARTED && 3592 xfer->status != USBD_IN_PROGRESS) { 3593 printf("ohci_device_isoc_abort: early return\n"); 3594 goto done; 3595 } 3596 3597 /* Give xfer the requested abort code. */ 3598 xfer->status = USBD_CANCELLED; 3599 3600 sed = opipe->sed; 3601 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3602 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3603 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3604 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3605 sizeof(sed->ed.ed_flags), 3606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3607 3608 sitd = xfer->hcpriv; 3609 #ifdef DIAGNOSTIC 3610 if (sitd == NULL) { 3611 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3612 goto done; 3613 } 3614 #endif 3615 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3616 #ifdef DIAGNOSTIC 3617 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3618 sitd->isdone = 1; 3619 #endif 3620 } 3621 3622 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3623 3624 /* Run callback. */ 3625 usb_transfer_complete(xfer); 3626 3627 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3628 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3629 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3631 3632 done: 3633 KASSERT(mutex_owned(&sc->sc_lock)); 3634 } 3635 3636 void 3637 ohci_device_isoc_done(usbd_xfer_handle xfer) 3638 { 3639 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3640 } 3641 3642 usbd_status 3643 ohci_setup_isoc(usbd_pipe_handle pipe) 3644 { 3645 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3646 ohci_softc_t *sc = pipe->device->bus->hci_private; 3647 struct iso *iso = &opipe->u.iso; 3648 3649 iso->next = -1; 3650 iso->inuse = 0; 3651 3652 mutex_enter(&sc->sc_lock); 3653 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3654 mutex_exit(&sc->sc_lock); 3655 3656 return (USBD_NORMAL_COMPLETION); 3657 } 3658 3659 void 3660 ohci_device_isoc_close(usbd_pipe_handle pipe) 3661 { 3662 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3663 ohci_softc_t *sc = pipe->device->bus->hci_private; 3664 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 3667 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3668 ohci_close_pipe(pipe, sc->sc_isoc_head); 3669 #ifdef DIAGNOSTIC 3670 opipe->tail.itd->isdone = 1; 3671 #endif 3672 ohci_free_sitd(sc, opipe->tail.itd); 3673 } 3674
Indexes created Wed Sep 24 15:09:51 GMT 2025