ohci.c revision 1.235
1 /* $NetBSD: ohci.c,v 1.235 2013/03/22 13:28:11 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.235 2013/03/22 13:28:11 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 #if 0 102 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 103 ohci_soft_td_t *); 104 #endif 105 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 106 ohci_softc_t *, int, int, usbd_xfer_handle, 107 ohci_soft_td_t *, ohci_soft_td_t **); 108 109 Static usbd_status ohci_open(usbd_pipe_handle); 110 Static void ohci_poll(struct usbd_bus *); 111 Static void ohci_softintr(void *); 112 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 113 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 114 Static void ohci_rhsc_softint(void *arg); 115 116 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 117 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 118 ohci_soft_ed_t *); 119 120 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 121 ohci_soft_ed_t *); 122 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 123 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 124 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 125 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 126 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 127 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 128 129 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 130 Static void ohci_device_isoc_enter(usbd_xfer_handle); 131 132 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 133 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 134 135 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 136 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 137 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 138 139 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 140 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 141 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 142 Static void ohci_root_ctrl_close(usbd_pipe_handle); 143 Static void ohci_root_ctrl_done(usbd_xfer_handle); 144 145 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 146 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 147 Static void ohci_root_intr_abort(usbd_xfer_handle); 148 Static void ohci_root_intr_close(usbd_pipe_handle); 149 Static void ohci_root_intr_done(usbd_xfer_handle); 150 151 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 152 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 153 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 154 Static void ohci_device_ctrl_close(usbd_pipe_handle); 155 Static void ohci_device_ctrl_done(usbd_xfer_handle); 156 157 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 158 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 159 Static void ohci_device_bulk_abort(usbd_xfer_handle); 160 Static void ohci_device_bulk_close(usbd_pipe_handle); 161 Static void ohci_device_bulk_done(usbd_xfer_handle); 162 163 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 164 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 165 Static void ohci_device_intr_abort(usbd_xfer_handle); 166 Static void ohci_device_intr_close(usbd_pipe_handle); 167 Static void ohci_device_intr_done(usbd_xfer_handle); 168 169 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 170 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 171 Static void ohci_device_isoc_abort(usbd_xfer_handle); 172 Static void ohci_device_isoc_close(usbd_pipe_handle); 173 Static void ohci_device_isoc_done(usbd_xfer_handle); 174 175 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 176 struct ohci_pipe *pipe, int ival); 177 178 Static void ohci_timeout(void *); 179 Static void ohci_timeout_task(void *); 180 Static void ohci_rhsc_enable(void *); 181 182 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 183 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 184 185 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 186 Static void ohci_noop(usbd_pipe_handle pipe); 187 188 #ifdef OHCI_DEBUG 189 Static void ohci_dumpregs(ohci_softc_t *); 190 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 191 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 192 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 193 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 194 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 195 #endif 196 197 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 198 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 199 #define OWRITE1(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE2(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 #define OWRITE4(sc, r, x) \ 204 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 205 static __inline uint8_t 206 OREAD1(ohci_softc_t *sc, bus_size_t r) 207 { 208 209 OBARR(sc); 210 return bus_space_read_1(sc->iot, sc->ioh, r); 211 } 212 213 static __inline uint16_t 214 OREAD2(ohci_softc_t *sc, bus_size_t r) 215 { 216 217 OBARR(sc); 218 return bus_space_read_2(sc->iot, sc->ioh, r); 219 } 220 221 static __inline uint32_t 222 OREAD4(ohci_softc_t *sc, bus_size_t r) 223 { 224 225 OBARR(sc); 226 return bus_space_read_4(sc->iot, sc->ioh, r); 227 } 228 229 /* Reverse the bits in a value 0 .. 31 */ 230 Static u_int8_t revbits[OHCI_NO_INTRS] = 231 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 232 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 233 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 234 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 235 236 struct ohci_pipe { 237 struct usbd_pipe pipe; 238 ohci_soft_ed_t *sed; 239 union { 240 ohci_soft_td_t *td; 241 ohci_soft_itd_t *itd; 242 } tail; 243 /* Info needed for different pipe kinds. */ 244 union { 245 /* Control pipe */ 246 struct { 247 usb_dma_t reqdma; 248 u_int length; 249 ohci_soft_td_t *setup, *data, *stat; 250 } ctl; 251 /* Interrupt pipe */ 252 struct { 253 int nslots; 254 int pos; 255 } intr; 256 /* Bulk pipe */ 257 struct { 258 u_int length; 259 int isread; 260 } bulk; 261 /* Iso pipe */ 262 struct iso { 263 int next, inuse; 264 } iso; 265 } u; 266 }; 267 268 #define OHCI_INTR_ENDPT 1 269 270 Static const struct usbd_bus_methods ohci_bus_methods = { 271 .open_pipe = ohci_open, 272 .soft_intr = ohci_softintr, 273 .do_poll = ohci_poll, 274 .allocm = ohci_allocm, 275 .freem = ohci_freem, 276 .allocx = ohci_allocx, 277 .freex = ohci_freex, 278 .get_lock = ohci_get_lock, 279 }; 280 281 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 282 .transfer = ohci_root_ctrl_transfer, 283 .start = ohci_root_ctrl_start, 284 .abort = ohci_root_ctrl_abort, 285 .close = ohci_root_ctrl_close, 286 .cleartoggle = ohci_noop, 287 .done = ohci_root_ctrl_done, 288 }; 289 290 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 291 .transfer = ohci_root_intr_transfer, 292 .start = ohci_root_intr_start, 293 .abort = ohci_root_intr_abort, 294 .close = ohci_root_intr_close, 295 .cleartoggle = ohci_noop, 296 .done = ohci_root_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 300 .transfer = ohci_device_ctrl_transfer, 301 .start = ohci_device_ctrl_start, 302 .abort = ohci_device_ctrl_abort, 303 .close = ohci_device_ctrl_close, 304 .cleartoggle = ohci_noop, 305 .done = ohci_device_ctrl_done, 306 }; 307 308 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 309 .transfer = ohci_device_intr_transfer, 310 .start = ohci_device_intr_start, 311 .abort = ohci_device_intr_abort, 312 .close = ohci_device_intr_close, 313 .cleartoggle = ohci_device_clear_toggle, 314 .done = ohci_device_intr_done, 315 }; 316 317 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 318 .transfer = ohci_device_bulk_transfer, 319 .start = ohci_device_bulk_start, 320 .abort = ohci_device_bulk_abort, 321 .close = ohci_device_bulk_close, 322 .cleartoggle = ohci_device_clear_toggle, 323 .done = ohci_device_bulk_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 327 .transfer = ohci_device_isoc_transfer, 328 .start = ohci_device_isoc_start, 329 .abort = ohci_device_isoc_abort, 330 .close = ohci_device_isoc_close, 331 .cleartoggle = ohci_noop, 332 .done = ohci_device_isoc_done, 333 }; 334 335 int 336 ohci_activate(device_t self, enum devact act) 337 { 338 struct ohci_softc *sc = device_private(self); 339 340 switch (act) { 341 case DVACT_DEACTIVATE: 342 sc->sc_dying = 1; 343 return 0; 344 default: 345 return EOPNOTSUPP; 346 } 347 } 348 349 void 350 ohci_childdet(device_t self, device_t child) 351 { 352 struct ohci_softc *sc = device_private(self); 353 354 KASSERT(sc->sc_child == child); 355 sc->sc_child = NULL; 356 } 357 358 int 359 ohci_detach(struct ohci_softc *sc, int flags) 360 { 361 int rv = 0; 362 363 if (sc->sc_child != NULL) 364 rv = config_detach(sc->sc_child, flags); 365 366 if (rv != 0) 367 return (rv); 368 369 callout_stop(&sc->sc_tmo_rhsc); 370 371 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 372 callout_destroy(&sc->sc_tmo_rhsc); 373 374 softint_disestablish(sc->sc_rhsc_si); 375 376 cv_destroy(&sc->sc_softwake_cv); 377 378 mutex_destroy(&sc->sc_lock); 379 mutex_destroy(&sc->sc_intr_lock); 380 381 if (sc->sc_hcca != NULL) 382 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 383 pool_cache_destroy(sc->sc_xferpool); 384 385 return (rv); 386 } 387 388 ohci_soft_ed_t * 389 ohci_alloc_sed(ohci_softc_t *sc) 390 { 391 ohci_soft_ed_t *sed; 392 usbd_status err; 393 int i, offs; 394 usb_dma_t dma; 395 396 if (sc->sc_freeeds == NULL) { 397 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 398 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 399 OHCI_ED_ALIGN, &dma); 400 if (err) 401 return (0); 402 for (i = 0; i < OHCI_SED_CHUNK; i++) { 403 offs = i * OHCI_SED_SIZE; 404 sed = KERNADDR(&dma, offs); 405 sed->physaddr = DMAADDR(&dma, offs); 406 sed->dma = dma; 407 sed->offs = offs; 408 sed->next = sc->sc_freeeds; 409 sc->sc_freeeds = sed; 410 } 411 } 412 sed = sc->sc_freeeds; 413 sc->sc_freeeds = sed->next; 414 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 415 sed->next = 0; 416 return (sed); 417 } 418 419 void 420 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 421 { 422 sed->next = sc->sc_freeeds; 423 sc->sc_freeeds = sed; 424 } 425 426 ohci_soft_td_t * 427 ohci_alloc_std(ohci_softc_t *sc) 428 { 429 ohci_soft_td_t *std; 430 usbd_status err; 431 int i, offs; 432 usb_dma_t dma; 433 434 if (sc->sc_freetds == NULL) { 435 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 436 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 437 OHCI_TD_ALIGN, &dma); 438 if (err) 439 return (NULL); 440 for(i = 0; i < OHCI_STD_CHUNK; i++) { 441 offs = i * OHCI_STD_SIZE; 442 std = KERNADDR(&dma, offs); 443 std->physaddr = DMAADDR(&dma, offs); 444 std->dma = dma; 445 std->offs = offs; 446 std->nexttd = sc->sc_freetds; 447 sc->sc_freetds = std; 448 } 449 } 450 451 std = sc->sc_freetds; 452 sc->sc_freetds = std->nexttd; 453 memset(&std->td, 0, sizeof(ohci_td_t)); 454 std->nexttd = NULL; 455 std->xfer = NULL; 456 ohci_hash_add_td(sc, std); 457 458 return (std); 459 } 460 461 void 462 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 463 { 464 465 ohci_hash_rem_td(sc, std); 466 std->nexttd = sc->sc_freetds; 467 sc->sc_freetds = std; 468 } 469 470 usbd_status 471 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 472 int alen, int rd, usbd_xfer_handle xfer, 473 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 474 { 475 ohci_soft_td_t *next, *cur; 476 ohci_physaddr_t dataphys, dataphysend; 477 u_int32_t tdflags; 478 int len, curlen; 479 usb_dma_t *dma = &xfer->dmabuf; 480 u_int16_t flags = xfer->flags; 481 482 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 483 484 KASSERT(mutex_owned(&sc->sc_lock)); 485 486 len = alen; 487 cur = sp; 488 dataphys = DMAADDR(dma, 0); 489 dataphysend = OHCI_PAGE(dataphys + len - 1); 490 usb_syncmem(dma, 0, len, 491 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 492 tdflags = HTOO32( 493 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 494 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 495 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 496 497 for (;;) { 498 next = ohci_alloc_std(sc); 499 if (next == NULL) 500 goto nomem; 501 502 /* The OHCI hardware can handle at most one page crossing. */ 503 if (OHCI_PAGE(dataphys) == dataphysend || 504 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 505 /* we can handle it in this TD */ 506 curlen = len; 507 } else { 508 /* must use multiple TDs, fill as much as possible. */ 509 curlen = 2 * OHCI_PAGE_SIZE - 510 (dataphys & (OHCI_PAGE_SIZE-1)); 511 /* the length must be a multiple of the max size */ 512 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 513 #ifdef DIAGNOSTIC 514 if (curlen == 0) 515 panic("ohci_alloc_std: curlen == 0"); 516 #endif 517 } 518 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 519 "dataphysend=0x%08x len=%d curlen=%d\n", 520 dataphys, dataphysend, 521 len, curlen)); 522 len -= curlen; 523 524 cur->td.td_flags = tdflags; 525 cur->td.td_cbp = HTOO32(dataphys); 526 cur->nexttd = next; 527 cur->td.td_nexttd = HTOO32(next->physaddr); 528 cur->td.td_be = HTOO32(dataphys + curlen - 1); 529 cur->len = curlen; 530 cur->flags = OHCI_ADD_LEN; 531 cur->xfer = xfer; 532 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 534 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 535 dataphys, dataphys + curlen - 1)); 536 if (len == 0) 537 break; 538 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 539 dataphys += curlen; 540 cur = next; 541 } 542 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 543 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 544 /* Force a 0 length transfer at the end. */ 545 546 cur = next; 547 next = ohci_alloc_std(sc); 548 if (next == NULL) 549 goto nomem; 550 551 cur->td.td_flags = tdflags; 552 cur->td.td_cbp = 0; /* indicate 0 length packet */ 553 cur->nexttd = next; 554 cur->td.td_nexttd = HTOO32(next->physaddr); 555 cur->td.td_be = ~0; 556 cur->len = 0; 557 cur->flags = 0; 558 cur->xfer = xfer; 559 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 561 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 562 } 563 *ep = cur; 564 565 return (USBD_NORMAL_COMPLETION); 566 567 nomem: 568 /* XXX free chain */ 569 return (USBD_NOMEM); 570 } 571 572 #if 0 573 Static void 574 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 575 ohci_soft_td_t *stdend) 576 { 577 ohci_soft_td_t *p; 578 579 for (; std != stdend; std = p) { 580 p = std->nexttd; 581 ohci_free_std(sc, std); 582 } 583 } 584 #endif 585 586 ohci_soft_itd_t * 587 ohci_alloc_sitd(ohci_softc_t *sc) 588 { 589 ohci_soft_itd_t *sitd; 590 usbd_status err; 591 int i, offs; 592 usb_dma_t dma; 593 594 if (sc->sc_freeitds == NULL) { 595 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 596 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 597 OHCI_ITD_ALIGN, &dma); 598 if (err) 599 return (NULL); 600 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 601 offs = i * OHCI_SITD_SIZE; 602 sitd = KERNADDR(&dma, offs); 603 sitd->physaddr = DMAADDR(&dma, offs); 604 sitd->dma = dma; 605 sitd->offs = offs; 606 sitd->nextitd = sc->sc_freeitds; 607 sc->sc_freeitds = sitd; 608 } 609 } 610 611 sitd = sc->sc_freeitds; 612 sc->sc_freeitds = sitd->nextitd; 613 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 614 sitd->nextitd = NULL; 615 sitd->xfer = NULL; 616 ohci_hash_add_itd(sc, sitd); 617 618 #ifdef DIAGNOSTIC 619 sitd->isdone = 0; 620 #endif 621 622 return (sitd); 623 } 624 625 void 626 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 627 { 628 629 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 630 631 #ifdef DIAGNOSTIC 632 if (!sitd->isdone) { 633 panic("ohci_free_sitd: sitd=%p not done", sitd); 634 return; 635 } 636 /* Warn double free */ 637 sitd->isdone = 0; 638 #endif 639 640 ohci_hash_rem_itd(sc, sitd); 641 sitd->nextitd = sc->sc_freeitds; 642 sc->sc_freeitds = sitd; 643 } 644 645 usbd_status 646 ohci_init(ohci_softc_t *sc) 647 { 648 ohci_soft_ed_t *sed, *psed; 649 usbd_status err; 650 int i; 651 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 652 653 DPRINTF(("ohci_init: start\n")); 654 aprint_normal_dev(sc->sc_dev, ""); 655 656 sc->sc_hcca = NULL; 657 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 658 659 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 660 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 661 cv_init(&sc->sc_softwake_cv, "ohciab"); 662 663 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 664 ohci_rhsc_softint, sc); 665 666 for (i = 0; i < OHCI_HASH_SIZE; i++) 667 LIST_INIT(&sc->sc_hash_tds[i]); 668 for (i = 0; i < OHCI_HASH_SIZE; i++) 669 LIST_INIT(&sc->sc_hash_itds[i]); 670 671 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 672 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 673 674 rev = OREAD4(sc, OHCI_REVISION); 675 aprint_normal("OHCI version %d.%d%s\n", 676 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 677 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 678 679 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 680 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 681 sc->sc_bus.usbrev = USBREV_UNKNOWN; 682 return (USBD_INVAL); 683 } 684 sc->sc_bus.usbrev = USBREV_1_0; 685 686 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 687 USB_MEM_RESERVE); 688 689 /* XXX determine alignment by R/W */ 690 /* Allocate the HCCA area. */ 691 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 692 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 693 if (err) { 694 sc->sc_hcca = NULL; 695 return err; 696 } 697 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 698 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 699 700 sc->sc_eintrs = OHCI_NORMAL_INTRS; 701 702 /* Allocate dummy ED that starts the control list. */ 703 sc->sc_ctrl_head = ohci_alloc_sed(sc); 704 if (sc->sc_ctrl_head == NULL) { 705 err = USBD_NOMEM; 706 goto bad1; 707 } 708 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 709 710 /* Allocate dummy ED that starts the bulk list. */ 711 sc->sc_bulk_head = ohci_alloc_sed(sc); 712 if (sc->sc_bulk_head == NULL) { 713 err = USBD_NOMEM; 714 goto bad2; 715 } 716 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 717 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 718 sizeof(sc->sc_bulk_head->ed), 719 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 720 721 /* Allocate dummy ED that starts the isochronous list. */ 722 sc->sc_isoc_head = ohci_alloc_sed(sc); 723 if (sc->sc_isoc_head == NULL) { 724 err = USBD_NOMEM; 725 goto bad3; 726 } 727 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 728 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 729 sizeof(sc->sc_isoc_head->ed), 730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 731 732 /* Allocate all the dummy EDs that make up the interrupt tree. */ 733 for (i = 0; i < OHCI_NO_EDS; i++) { 734 sed = ohci_alloc_sed(sc); 735 if (sed == NULL) { 736 while (--i >= 0) 737 ohci_free_sed(sc, sc->sc_eds[i]); 738 err = USBD_NOMEM; 739 goto bad4; 740 } 741 /* All ED fields are set to 0. */ 742 sc->sc_eds[i] = sed; 743 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 744 if (i != 0) 745 psed = sc->sc_eds[(i-1) / 2]; 746 else 747 psed= sc->sc_isoc_head; 748 sed->next = psed; 749 sed->ed.ed_nexted = HTOO32(psed->physaddr); 750 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 751 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 752 } 753 /* 754 * Fill HCCA interrupt table. The bit reversal is to get 755 * the tree set up properly to spread the interrupts. 756 */ 757 for (i = 0; i < OHCI_NO_INTRS; i++) 758 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 759 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 760 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 761 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 762 763 #ifdef OHCI_DEBUG 764 if (ohcidebug > 15) { 765 for (i = 0; i < OHCI_NO_EDS; i++) { 766 printf("ed#%d ", i); 767 ohci_dump_ed(sc, sc->sc_eds[i]); 768 } 769 printf("iso "); 770 ohci_dump_ed(sc, sc->sc_isoc_head); 771 } 772 #endif 773 774 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 775 ctl = OREAD4(sc, OHCI_CONTROL); 776 rwc = ctl & OHCI_RWC; 777 fm = OREAD4(sc, OHCI_FM_INTERVAL); 778 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 779 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 780 781 /* Determine in what context we are running. */ 782 if (ctl & OHCI_IR) { 783 /* SMM active, request change */ 784 DPRINTF(("ohci_init: SMM active, request owner change\n")); 785 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 786 (OHCI_OC | OHCI_MIE)) 787 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 788 s = OREAD4(sc, OHCI_COMMAND_STATUS); 789 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 790 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 791 usb_delay_ms(&sc->sc_bus, 1); 792 ctl = OREAD4(sc, OHCI_CONTROL); 793 } 794 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 795 if ((ctl & OHCI_IR) == 0) { 796 aprint_error_dev(sc->sc_dev, 797 "SMM does not respond, resetting\n"); 798 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 799 goto reset; 800 } 801 #if 0 802 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 803 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 804 /* BIOS started controller. */ 805 DPRINTF(("ohci_init: BIOS active\n")); 806 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 807 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 808 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 809 } 810 #endif 811 } else { 812 DPRINTF(("ohci_init: cold started\n")); 813 reset: 814 /* Controller was cold started. */ 815 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 816 } 817 818 /* 819 * This reset should not be necessary according to the OHCI spec, but 820 * without it some controllers do not start. 821 */ 822 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 823 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 824 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 825 826 /* We now own the host controller and the bus has been reset. */ 827 828 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 829 /* Nominal time for a reset is 10 us. */ 830 for (i = 0; i < 10; i++) { 831 delay(10); 832 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 833 if (!hcr) 834 break; 835 } 836 if (hcr) { 837 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 838 err = USBD_IOERROR; 839 goto bad5; 840 } 841 #ifdef OHCI_DEBUG 842 if (ohcidebug > 15) 843 ohci_dumpregs(sc); 844 #endif 845 846 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 847 848 /* Set up HC registers. */ 849 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 850 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 851 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 852 /* disable all interrupts and then switch on all desired interrupts */ 853 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 854 /* switch on desired functional features */ 855 ctl = OREAD4(sc, OHCI_CONTROL); 856 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 857 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 858 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 859 /* And finally start it! */ 860 OWRITE4(sc, OHCI_CONTROL, ctl); 861 862 /* 863 * The controller is now OPERATIONAL. Set a some final 864 * registers that should be set earlier, but that the 865 * controller ignores when in the SUSPEND state. 866 */ 867 ival = OHCI_GET_IVAL(fm); 868 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 869 fm |= OHCI_FSMPS(ival) | ival; 870 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 871 per = OHCI_PERIODIC(ival); /* 90% periodic */ 872 OWRITE4(sc, OHCI_PERIODIC_START, per); 873 874 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 875 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 876 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 877 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 878 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 879 880 /* 881 * The AMD756 requires a delay before re-reading the register, 882 * otherwise it will occasionally report 0 ports. 883 */ 884 sc->sc_noport = 0; 885 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 886 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 887 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 888 } 889 890 #ifdef OHCI_DEBUG 891 if (ohcidebug > 5) 892 ohci_dumpregs(sc); 893 #endif 894 895 /* Set up the bus struct. */ 896 sc->sc_bus.methods = &ohci_bus_methods; 897 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 898 899 sc->sc_control = sc->sc_intre = 0; 900 901 /* Finally, turn on interrupts. */ 902 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 903 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 904 905 return (USBD_NORMAL_COMPLETION); 906 907 bad5: 908 for (i = 0; i < OHCI_NO_EDS; i++) 909 ohci_free_sed(sc, sc->sc_eds[i]); 910 bad4: 911 ohci_free_sed(sc, sc->sc_isoc_head); 912 bad3: 913 ohci_free_sed(sc, sc->sc_bulk_head); 914 bad2: 915 ohci_free_sed(sc, sc->sc_ctrl_head); 916 bad1: 917 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 918 sc->sc_hcca = NULL; 919 return (err); 920 } 921 922 usbd_status 923 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 924 { 925 struct ohci_softc *sc = bus->hci_private; 926 usbd_status status; 927 928 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 929 if (status == USBD_NOMEM) 930 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 931 return status; 932 } 933 934 void 935 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 936 { 937 struct ohci_softc *sc = bus->hci_private; 938 if (dma->block->flags & USB_DMA_RESERVE) { 939 usb_reserve_freem(&sc->sc_dma_reserve, dma); 940 return; 941 } 942 usb_freemem(&sc->sc_bus, dma); 943 } 944 945 usbd_xfer_handle 946 ohci_allocx(struct usbd_bus *bus) 947 { 948 struct ohci_softc *sc = bus->hci_private; 949 usbd_xfer_handle xfer; 950 951 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 952 if (xfer != NULL) { 953 memset(xfer, 0, sizeof(struct ohci_xfer)); 954 #ifdef DIAGNOSTIC 955 xfer->busy_free = XFER_BUSY; 956 #endif 957 } 958 return (xfer); 959 } 960 961 void 962 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 963 { 964 struct ohci_softc *sc = bus->hci_private; 965 966 #ifdef DIAGNOSTIC 967 if (xfer->busy_free != XFER_BUSY) { 968 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 969 xfer->busy_free); 970 } 971 xfer->busy_free = XFER_FREE; 972 #endif 973 pool_cache_put(sc->sc_xferpool, xfer); 974 } 975 976 Static void 977 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 978 { 979 struct ohci_softc *sc = bus->hci_private; 980 981 *lock = &sc->sc_lock; 982 } 983 984 /* 985 * Shut down the controller when the system is going down. 986 */ 987 bool 988 ohci_shutdown(device_t self, int flags) 989 { 990 ohci_softc_t *sc = device_private(self); 991 992 DPRINTF(("ohci_shutdown: stopping the HC\n")); 993 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 994 return true; 995 } 996 997 bool 998 ohci_resume(device_t dv, const pmf_qual_t *qual) 999 { 1000 ohci_softc_t *sc = device_private(dv); 1001 uint32_t ctl; 1002 1003 mutex_spin_enter(&sc->sc_intr_lock); 1004 sc->sc_bus.use_polling++; 1005 mutex_spin_exit(&sc->sc_intr_lock); 1006 1007 /* Some broken BIOSes do not recover these values */ 1008 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1009 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1010 sc->sc_ctrl_head->physaddr); 1011 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1012 sc->sc_bulk_head->physaddr); 1013 if (sc->sc_intre) 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1015 (OHCI_ALL_INTRS | OHCI_MIE)); 1016 if (sc->sc_control) 1017 ctl = sc->sc_control; 1018 else 1019 ctl = OREAD4(sc, OHCI_CONTROL); 1020 ctl |= OHCI_HCFS_RESUME; 1021 OWRITE4(sc, OHCI_CONTROL, ctl); 1022 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1023 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1024 OWRITE4(sc, OHCI_CONTROL, ctl); 1025 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1026 sc->sc_control = sc->sc_intre = 0; 1027 1028 mutex_spin_enter(&sc->sc_intr_lock); 1029 sc->sc_bus.use_polling--; 1030 mutex_spin_exit(&sc->sc_intr_lock); 1031 1032 return true; 1033 } 1034 1035 bool 1036 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1037 { 1038 ohci_softc_t *sc = device_private(dv); 1039 uint32_t ctl; 1040 1041 mutex_spin_enter(&sc->sc_intr_lock); 1042 sc->sc_bus.use_polling++; 1043 mutex_spin_exit(&sc->sc_intr_lock); 1044 1045 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1046 if (sc->sc_control == 0) { 1047 /* 1048 * Preserve register values, in case that BIOS 1049 * does not recover them. 1050 */ 1051 sc->sc_control = ctl; 1052 sc->sc_intre = OREAD4(sc, 1053 OHCI_INTERRUPT_ENABLE); 1054 } 1055 ctl |= OHCI_HCFS_SUSPEND; 1056 OWRITE4(sc, OHCI_CONTROL, ctl); 1057 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1058 1059 mutex_spin_enter(&sc->sc_intr_lock); 1060 sc->sc_bus.use_polling--; 1061 mutex_spin_exit(&sc->sc_intr_lock); 1062 1063 return true; 1064 } 1065 1066 #ifdef OHCI_DEBUG 1067 void 1068 ohci_dumpregs(ohci_softc_t *sc) 1069 { 1070 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1071 OREAD4(sc, OHCI_REVISION), 1072 OREAD4(sc, OHCI_CONTROL), 1073 OREAD4(sc, OHCI_COMMAND_STATUS))); 1074 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1075 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1076 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1077 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1078 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1079 OREAD4(sc, OHCI_HCCA), 1080 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1081 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1082 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1083 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1084 OREAD4(sc, OHCI_BULK_HEAD_ED), 1085 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1086 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1087 OREAD4(sc, OHCI_DONE_HEAD), 1088 OREAD4(sc, OHCI_FM_INTERVAL), 1089 OREAD4(sc, OHCI_FM_REMAINING))); 1090 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1091 OREAD4(sc, OHCI_FM_NUMBER), 1092 OREAD4(sc, OHCI_PERIODIC_START), 1093 OREAD4(sc, OHCI_LS_THRESHOLD))); 1094 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1095 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1096 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1097 OREAD4(sc, OHCI_RH_STATUS))); 1098 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1099 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1100 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1101 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1102 O32TOH(sc->sc_hcca->hcca_frame_number), 1103 O32TOH(sc->sc_hcca->hcca_done_head))); 1104 } 1105 #endif 1106 1107 Static int ohci_intr1(ohci_softc_t *); 1108 1109 int 1110 ohci_intr(void *p) 1111 { 1112 ohci_softc_t *sc = p; 1113 int ret = 0; 1114 1115 if (sc == NULL) 1116 return (0); 1117 1118 mutex_spin_enter(&sc->sc_intr_lock); 1119 1120 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1121 goto done; 1122 1123 /* If we get an interrupt while polling, then just ignore it. */ 1124 if (sc->sc_bus.use_polling) { 1125 #ifdef DIAGNOSTIC 1126 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1127 #endif 1128 /* for level triggered intrs, should do something to ack */ 1129 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1130 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1131 1132 goto done; 1133 } 1134 1135 ret = ohci_intr1(sc); 1136 1137 done: 1138 mutex_spin_exit(&sc->sc_intr_lock); 1139 return ret; 1140 } 1141 1142 Static int 1143 ohci_intr1(ohci_softc_t *sc) 1144 { 1145 u_int32_t intrs, eintrs; 1146 1147 DPRINTFN(14,("ohci_intr1: enter\n")); 1148 1149 /* In case the interrupt occurs before initialization has completed. */ 1150 if (sc == NULL || sc->sc_hcca == NULL) { 1151 #ifdef DIAGNOSTIC 1152 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1153 #endif 1154 return (0); 1155 } 1156 1157 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1158 1159 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1160 if (!intrs) 1161 return (0); 1162 1163 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1164 eintrs = intrs & sc->sc_eintrs; 1165 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1166 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1167 (u_int)eintrs, sc->sc_eintrs)); 1168 1169 if (!eintrs) { 1170 return (0); 1171 } 1172 1173 sc->sc_bus.no_intrs++; 1174 if (eintrs & OHCI_SO) { 1175 sc->sc_overrun_cnt++; 1176 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1177 printf("%s: %u scheduling overruns\n", 1178 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1179 sc->sc_overrun_cnt = 0; 1180 } 1181 /* XXX do what */ 1182 eintrs &= ~OHCI_SO; 1183 } 1184 if (eintrs & OHCI_WDH) { 1185 /* 1186 * We block the interrupt below, and reenable it later from 1187 * ohci_softintr(). 1188 */ 1189 usb_schedsoftintr(&sc->sc_bus); 1190 } 1191 if (eintrs & OHCI_RD) { 1192 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1193 /* XXX process resume detect */ 1194 } 1195 if (eintrs & OHCI_UE) { 1196 printf("%s: unrecoverable error, controller halted\n", 1197 device_xname(sc->sc_dev)); 1198 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1199 /* XXX what else */ 1200 } 1201 if (eintrs & OHCI_RHSC) { 1202 /* 1203 * We block the interrupt below, and reenable it later from 1204 * a timeout. 1205 */ 1206 softint_schedule(sc->sc_rhsc_si); 1207 } 1208 1209 if (eintrs != 0) { 1210 /* Block unprocessed interrupts. */ 1211 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1212 sc->sc_eintrs &= ~eintrs; 1213 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1214 device_xname(sc->sc_dev), eintrs)); 1215 } 1216 1217 return (1); 1218 } 1219 1220 void 1221 ohci_rhsc_enable(void *v_sc) 1222 { 1223 ohci_softc_t *sc = v_sc; 1224 1225 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1226 mutex_spin_enter(&sc->sc_intr_lock); 1227 sc->sc_eintrs |= OHCI_RHSC; 1228 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1229 mutex_spin_exit(&sc->sc_intr_lock); 1230 } 1231 1232 #ifdef OHCI_DEBUG 1233 const char *ohci_cc_strs[] = { 1234 "NO_ERROR", 1235 "CRC", 1236 "BIT_STUFFING", 1237 "DATA_TOGGLE_MISMATCH", 1238 "STALL", 1239 "DEVICE_NOT_RESPONDING", 1240 "PID_CHECK_FAILURE", 1241 "UNEXPECTED_PID", 1242 "DATA_OVERRUN", 1243 "DATA_UNDERRUN", 1244 "BUFFER_OVERRUN", 1245 "BUFFER_UNDERRUN", 1246 "reserved", 1247 "reserved", 1248 "NOT_ACCESSED", 1249 "NOT_ACCESSED", 1250 }; 1251 #endif 1252 1253 void 1254 ohci_softintr(void *v) 1255 { 1256 struct usbd_bus *bus = v; 1257 ohci_softc_t *sc = bus->hci_private; 1258 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1259 ohci_soft_td_t *std, *sdone, *stdnext; 1260 usbd_xfer_handle xfer; 1261 struct ohci_pipe *opipe; 1262 int len, cc; 1263 int i, j, actlen, iframes, uedir; 1264 ohci_physaddr_t done; 1265 1266 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1267 1268 DPRINTFN(10,("ohci_softintr: enter\n")); 1269 1270 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1271 sizeof(sc->sc_hcca->hcca_done_head), 1272 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1273 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1274 sc->sc_hcca->hcca_done_head = 0; 1275 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1276 sizeof(sc->sc_hcca->hcca_done_head), 1277 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1278 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1279 sc->sc_eintrs |= OHCI_WDH; 1280 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1281 1282 /* Reverse the done list. */ 1283 for (sdone = NULL, sidone = NULL; done != 0; ) { 1284 std = ohci_hash_find_td(sc, done); 1285 if (std != NULL) { 1286 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1287 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1288 std->dnext = sdone; 1289 done = O32TOH(std->td.td_nexttd); 1290 sdone = std; 1291 DPRINTFN(10,("add TD %p\n", std)); 1292 continue; 1293 } 1294 sitd = ohci_hash_find_itd(sc, done); 1295 if (sitd != NULL) { 1296 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1297 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1298 sitd->dnext = sidone; 1299 done = O32TOH(sitd->itd.itd_nextitd); 1300 sidone = sitd; 1301 DPRINTFN(5,("add ITD %p\n", sitd)); 1302 continue; 1303 } 1304 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1305 (u_long)done); 1306 break; 1307 } 1308 1309 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1310 1311 #ifdef OHCI_DEBUG 1312 if (ohcidebug > 10) { 1313 DPRINTF(("ohci_process_done: TD done:\n")); 1314 for (std = sdone; std; std = std->dnext) 1315 ohci_dump_td(sc, std); 1316 } 1317 #endif 1318 1319 for (std = sdone; std; std = stdnext) { 1320 xfer = std->xfer; 1321 stdnext = std->dnext; 1322 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1323 std, xfer, xfer ? xfer->hcpriv : 0)); 1324 if (xfer == NULL) { 1325 /* 1326 * xfer == NULL: There seems to be no xfer associated 1327 * with this TD. It is tailp that happened to end up on 1328 * the done queue. 1329 * Shouldn't happen, but some chips are broken(?). 1330 */ 1331 continue; 1332 } 1333 if (xfer->status == USBD_CANCELLED || 1334 xfer->status == USBD_TIMEOUT) { 1335 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1336 xfer)); 1337 /* Handled by abort routine. */ 1338 continue; 1339 } 1340 callout_stop(&xfer->timeout_handle); 1341 1342 len = std->len; 1343 if (std->td.td_cbp != 0) 1344 len -= O32TOH(std->td.td_be) - 1345 O32TOH(std->td.td_cbp) + 1; 1346 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1347 std->flags)); 1348 if (std->flags & OHCI_ADD_LEN) 1349 xfer->actlen += len; 1350 1351 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1352 if (cc == OHCI_CC_NO_ERROR) { 1353 if (std->flags & OHCI_CALL_DONE) { 1354 xfer->status = USBD_NORMAL_COMPLETION; 1355 usb_transfer_complete(xfer); 1356 } 1357 ohci_free_std(sc, std); 1358 } else { 1359 /* 1360 * Endpoint is halted. First unlink all the TDs 1361 * belonging to the failed transfer, and then restart 1362 * the endpoint. 1363 */ 1364 ohci_soft_td_t *p, *n; 1365 opipe = (struct ohci_pipe *)xfer->pipe; 1366 1367 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1368 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1369 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1370 1371 /* remove TDs */ 1372 for (p = std; p->xfer == xfer; p = n) { 1373 n = p->nexttd; 1374 ohci_free_std(sc, p); 1375 } 1376 1377 /* clear halt */ 1378 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1379 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1380 1381 if (cc == OHCI_CC_STALL) 1382 xfer->status = USBD_STALLED; 1383 else 1384 xfer->status = USBD_IOERROR; 1385 usb_transfer_complete(xfer); 1386 } 1387 } 1388 1389 #ifdef OHCI_DEBUG 1390 if (ohcidebug > 10) { 1391 DPRINTF(("ohci_softintr: ITD done:\n")); 1392 for (sitd = sidone; sitd; sitd = sitd->dnext) 1393 ohci_dump_itd(sc, sitd); 1394 } 1395 #endif 1396 1397 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1398 xfer = sitd->xfer; 1399 sitdnext = sitd->dnext; 1400 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1401 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1402 if (xfer == NULL) 1403 continue; 1404 if (xfer->status == USBD_CANCELLED || 1405 xfer->status == USBD_TIMEOUT) { 1406 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1407 xfer)); 1408 /* Handled by abort routine. */ 1409 continue; 1410 } 1411 #ifdef DIAGNOSTIC 1412 if (sitd->isdone) 1413 printf("ohci_softintr: sitd=%p is done\n", sitd); 1414 sitd->isdone = 1; 1415 #endif 1416 if (sitd->flags & OHCI_CALL_DONE) { 1417 ohci_soft_itd_t *next; 1418 1419 opipe = (struct ohci_pipe *)xfer->pipe; 1420 opipe->u.iso.inuse -= xfer->nframes; 1421 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1422 bEndpointAddress); 1423 xfer->status = USBD_NORMAL_COMPLETION; 1424 actlen = 0; 1425 for (i = 0, sitd = xfer->hcpriv;; 1426 sitd = next) { 1427 next = sitd->nextitd; 1428 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1429 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1430 xfer->status = USBD_IOERROR; 1431 /* For input, update frlengths with actual */ 1432 /* XXX anything necessary for output? */ 1433 if (uedir == UE_DIR_IN && 1434 xfer->status == USBD_NORMAL_COMPLETION) { 1435 iframes = OHCI_ITD_GET_FC(O32TOH( 1436 sitd->itd.itd_flags)); 1437 for (j = 0; j < iframes; i++, j++) { 1438 len = O16TOH(sitd-> 1439 itd.itd_offset[j]); 1440 if ((OHCI_ITD_PSW_GET_CC(len) & 1441 OHCI_CC_NOT_ACCESSED_MASK) 1442 == OHCI_CC_NOT_ACCESSED) 1443 len = 0; 1444 else 1445 len = OHCI_ITD_PSW_LENGTH(len); 1446 xfer->frlengths[i] = len; 1447 actlen += len; 1448 } 1449 } 1450 if (sitd->flags & OHCI_CALL_DONE) 1451 break; 1452 ohci_free_sitd(sc, sitd); 1453 } 1454 ohci_free_sitd(sc, sitd); 1455 if (uedir == UE_DIR_IN && 1456 xfer->status == USBD_NORMAL_COMPLETION) 1457 xfer->actlen = actlen; 1458 xfer->hcpriv = NULL; 1459 1460 usb_transfer_complete(xfer); 1461 } 1462 } 1463 1464 if (sc->sc_softwake) { 1465 sc->sc_softwake = 0; 1466 cv_broadcast(&sc->sc_softwake_cv); 1467 } 1468 1469 DPRINTFN(10,("ohci_softintr: done:\n")); 1470 } 1471 1472 void 1473 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1474 { 1475 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1476 #ifdef DIAGNOSTIC 1477 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1478 #endif 1479 int len = UGETW(xfer->request.wLength); 1480 int isread = (xfer->request.bmRequestType & UT_READ); 1481 1482 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1483 1484 KASSERT(mutex_owned(&sc->sc_lock)); 1485 1486 #ifdef DIAGNOSTIC 1487 if (!(xfer->rqflags & URQ_REQUEST)) { 1488 panic("ohci_device_ctrl_done: not a request"); 1489 } 1490 #endif 1491 if (len) 1492 usb_syncmem(&xfer->dmabuf, 0, len, 1493 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1494 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1495 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1496 } 1497 1498 void 1499 ohci_device_intr_done(usbd_xfer_handle xfer) 1500 { 1501 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1502 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1503 ohci_soft_ed_t *sed = opipe->sed; 1504 ohci_soft_td_t *data, *tail; 1505 int isread = 1506 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1507 1508 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1509 xfer, xfer->actlen)); 1510 1511 KASSERT(mutex_owned(&sc->sc_lock)); 1512 1513 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1514 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1515 if (xfer->pipe->repeat) { 1516 data = opipe->tail.td; 1517 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1518 if (tail == NULL) { 1519 xfer->status = USBD_NOMEM; 1520 return; 1521 } 1522 tail->xfer = NULL; 1523 1524 data->td.td_flags = HTOO32( 1525 OHCI_TD_IN | OHCI_TD_NOCC | 1526 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1527 if (xfer->flags & USBD_SHORT_XFER_OK) 1528 data->td.td_flags |= HTOO32(OHCI_TD_R); 1529 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1530 data->nexttd = tail; 1531 data->td.td_nexttd = HTOO32(tail->physaddr); 1532 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1533 xfer->length - 1); 1534 data->len = xfer->length; 1535 data->xfer = xfer; 1536 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1537 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1539 xfer->hcpriv = data; 1540 xfer->actlen = 0; 1541 1542 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1543 usb_syncmem(&sed->dma, 1544 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1545 sizeof(sed->ed.ed_tailp), 1546 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1547 opipe->tail.td = tail; 1548 } 1549 } 1550 1551 void 1552 ohci_device_bulk_done(usbd_xfer_handle xfer) 1553 { 1554 #ifdef DIAGNOSTIC 1555 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1556 #endif 1557 int isread = 1558 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1559 1560 KASSERT(mutex_owned(&sc->sc_lock)); 1561 1562 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1563 xfer, xfer->actlen)); 1564 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1565 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1566 } 1567 1568 Static void 1569 ohci_rhsc_softint(void *arg) 1570 { 1571 ohci_softc_t *sc = arg; 1572 1573 mutex_enter(&sc->sc_lock); 1574 1575 ohci_rhsc(sc, sc->sc_intrxfer); 1576 1577 /* Do not allow RHSC interrupts > 1 per second */ 1578 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1579 1580 mutex_exit(&sc->sc_lock); 1581 } 1582 1583 void 1584 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1585 { 1586 usbd_pipe_handle pipe; 1587 u_char *p; 1588 int i, m; 1589 int hstatus; 1590 1591 KASSERT(mutex_owned(&sc->sc_lock)); 1592 1593 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1594 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1595 sc, xfer, hstatus)); 1596 1597 if (xfer == NULL) { 1598 /* Just ignore the change. */ 1599 return; 1600 } 1601 1602 pipe = xfer->pipe; 1603 1604 p = KERNADDR(&xfer->dmabuf, 0); 1605 m = min(sc->sc_noport, xfer->length * 8 - 1); 1606 memset(p, 0, xfer->length); 1607 for (i = 1; i <= m; i++) { 1608 /* Pick out CHANGE bits from the status reg. */ 1609 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1610 p[i/8] |= 1 << (i%8); 1611 } 1612 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1613 xfer->actlen = xfer->length; 1614 xfer->status = USBD_NORMAL_COMPLETION; 1615 1616 usb_transfer_complete(xfer); 1617 } 1618 1619 void 1620 ohci_root_intr_done(usbd_xfer_handle xfer) 1621 { 1622 } 1623 1624 void 1625 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1626 { 1627 } 1628 1629 /* 1630 * Wait here until controller claims to have an interrupt. 1631 * Then call ohci_intr and return. Use timeout to avoid waiting 1632 * too long. 1633 */ 1634 void 1635 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1636 { 1637 int timo; 1638 u_int32_t intrs; 1639 1640 mutex_enter(&sc->sc_lock); 1641 1642 xfer->status = USBD_IN_PROGRESS; 1643 for (timo = xfer->timeout; timo >= 0; timo--) { 1644 usb_delay_ms(&sc->sc_bus, 1); 1645 if (sc->sc_dying) 1646 break; 1647 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1648 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1649 #ifdef OHCI_DEBUG 1650 if (ohcidebug > 15) 1651 ohci_dumpregs(sc); 1652 #endif 1653 if (intrs) { 1654 mutex_spin_enter(&sc->sc_intr_lock); 1655 ohci_intr1(sc); 1656 mutex_spin_exit(&sc->sc_intr_lock); 1657 if (xfer->status != USBD_IN_PROGRESS) 1658 goto done; 1659 } 1660 } 1661 1662 /* Timeout */ 1663 DPRINTF(("ohci_waitintr: timeout\n")); 1664 xfer->status = USBD_TIMEOUT; 1665 usb_transfer_complete(xfer); 1666 1667 /* XXX should free TD */ 1668 1669 done: 1670 mutex_exit(&sc->sc_lock); 1671 } 1672 1673 void 1674 ohci_poll(struct usbd_bus *bus) 1675 { 1676 ohci_softc_t *sc = bus->hci_private; 1677 #ifdef OHCI_DEBUG 1678 static int last; 1679 int new; 1680 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1681 if (new != last) { 1682 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1683 last = new; 1684 } 1685 #endif 1686 1687 sc->sc_eintrs |= OHCI_WDH; 1688 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1689 mutex_spin_enter(&sc->sc_intr_lock); 1690 ohci_intr1(sc); 1691 mutex_spin_exit(&sc->sc_intr_lock); 1692 } 1693 } 1694 1695 usbd_status 1696 ohci_device_request(usbd_xfer_handle xfer) 1697 { 1698 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1699 usb_device_request_t *req = &xfer->request; 1700 usbd_device_handle dev = opipe->pipe.device; 1701 ohci_softc_t *sc = dev->bus->hci_private; 1702 int addr = dev->address; 1703 ohci_soft_td_t *setup, *stat, *next, *tail; 1704 ohci_soft_ed_t *sed; 1705 int isread; 1706 int len; 1707 usbd_status err; 1708 1709 KASSERT(mutex_owned(&sc->sc_lock)); 1710 1711 isread = req->bmRequestType & UT_READ; 1712 len = UGETW(req->wLength); 1713 1714 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1715 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1716 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1717 UGETW(req->wIndex), len, addr, 1718 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1719 1720 setup = opipe->tail.td; 1721 stat = ohci_alloc_std(sc); 1722 if (stat == NULL) { 1723 err = USBD_NOMEM; 1724 goto bad1; 1725 } 1726 tail = ohci_alloc_std(sc); 1727 if (tail == NULL) { 1728 err = USBD_NOMEM; 1729 goto bad2; 1730 } 1731 tail->xfer = NULL; 1732 1733 sed = opipe->sed; 1734 opipe->u.ctl.length = len; 1735 1736 /* Update device address and length since they may have changed 1737 during the setup of the control pipe in usbd_new_device(). */ 1738 /* XXX This only needs to be done once, but it's too early in open. */ 1739 /* XXXX Should not touch ED here! */ 1740 1741 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1742 sizeof(sed->ed.ed_flags), 1743 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1744 sed->ed.ed_flags = HTOO32( 1745 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1746 OHCI_ED_SET_FA(addr) | 1747 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1748 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1749 sizeof(sed->ed.ed_flags), 1750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1751 1752 next = stat; 1753 1754 /* Set up data transaction */ 1755 if (len != 0) { 1756 ohci_soft_td_t *std = stat; 1757 1758 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1759 std, &stat); 1760 stat = stat->nexttd; /* point at free TD */ 1761 if (err) 1762 goto bad3; 1763 /* Start toggle at 1 and then use the carried toggle. */ 1764 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1765 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1766 usb_syncmem(&std->dma, 1767 std->offs + offsetof(ohci_td_t, td_flags), 1768 sizeof(std->td.td_flags), 1769 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1770 } 1771 1772 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1773 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1774 1775 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1776 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1777 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1778 setup->nexttd = next; 1779 setup->td.td_nexttd = HTOO32(next->physaddr); 1780 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1781 setup->len = 0; 1782 setup->xfer = xfer; 1783 setup->flags = 0; 1784 xfer->hcpriv = setup; 1785 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1787 1788 stat->td.td_flags = HTOO32( 1789 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1790 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1791 stat->td.td_cbp = 0; 1792 stat->nexttd = tail; 1793 stat->td.td_nexttd = HTOO32(tail->physaddr); 1794 stat->td.td_be = 0; 1795 stat->flags = OHCI_CALL_DONE; 1796 stat->len = 0; 1797 stat->xfer = xfer; 1798 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 1801 #ifdef OHCI_DEBUG 1802 if (ohcidebug > 5) { 1803 DPRINTF(("ohci_device_request:\n")); 1804 ohci_dump_ed(sc, sed); 1805 ohci_dump_tds(sc, setup); 1806 } 1807 #endif 1808 1809 /* Insert ED in schedule */ 1810 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1811 usb_syncmem(&sed->dma, 1812 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1813 sizeof(sed->ed.ed_tailp), 1814 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1815 opipe->tail.td = tail; 1816 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1817 if (xfer->timeout && !sc->sc_bus.use_polling) { 1818 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1819 ohci_timeout, xfer); 1820 } 1821 1822 #ifdef OHCI_DEBUG 1823 if (ohcidebug > 20) { 1824 delay(10000); 1825 DPRINTF(("ohci_device_request: status=%x\n", 1826 OREAD4(sc, OHCI_COMMAND_STATUS))); 1827 ohci_dumpregs(sc); 1828 printf("ctrl head:\n"); 1829 ohci_dump_ed(sc, sc->sc_ctrl_head); 1830 printf("sed:\n"); 1831 ohci_dump_ed(sc, sed); 1832 ohci_dump_tds(sc, setup); 1833 } 1834 #endif 1835 1836 return (USBD_NORMAL_COMPLETION); 1837 1838 bad3: 1839 ohci_free_std(sc, tail); 1840 bad2: 1841 ohci_free_std(sc, stat); 1842 bad1: 1843 return (err); 1844 } 1845 1846 /* 1847 * Add an ED to the schedule. Called with USB lock held. 1848 */ 1849 Static void 1850 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1851 { 1852 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1853 1854 KASSERT(mutex_owned(&sc->sc_lock)); 1855 1856 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1857 sizeof(head->ed.ed_nexted), 1858 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1859 sed->next = head->next; 1860 sed->ed.ed_nexted = head->ed.ed_nexted; 1861 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1862 sizeof(sed->ed.ed_nexted), 1863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1864 head->next = sed; 1865 head->ed.ed_nexted = HTOO32(sed->physaddr); 1866 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1867 sizeof(head->ed.ed_nexted), 1868 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1869 } 1870 1871 /* 1872 * Remove an ED from the schedule. Called with USB lock held. 1873 */ 1874 Static void 1875 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1876 { 1877 ohci_soft_ed_t *p; 1878 1879 KASSERT(mutex_owned(&sc->sc_lock)); 1880 1881 /* XXX */ 1882 for (p = head; p != NULL && p->next != sed; p = p->next) 1883 ; 1884 if (p == NULL) 1885 panic("ohci_rem_ed: ED not found"); 1886 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1887 sizeof(sed->ed.ed_nexted), 1888 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1889 p->next = sed->next; 1890 p->ed.ed_nexted = sed->ed.ed_nexted; 1891 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1892 sizeof(p->ed.ed_nexted), 1893 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1894 } 1895 1896 /* 1897 * When a transfer is completed the TD is added to the done queue by 1898 * the host controller. This queue is the processed by software. 1899 * Unfortunately the queue contains the physical address of the TD 1900 * and we have no simple way to translate this back to a kernel address. 1901 * To make the translation possible (and fast) we use a hash table of 1902 * TDs currently in the schedule. The physical address is used as the 1903 * hash value. 1904 */ 1905 1906 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1907 /* Called with USB lock held. */ 1908 void 1909 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1910 { 1911 int h = HASH(std->physaddr); 1912 1913 KASSERT(mutex_owned(&sc->sc_lock)); 1914 1915 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1916 } 1917 1918 /* Called with USB lock held. */ 1919 void 1920 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1921 { 1922 1923 KASSERT(mutex_owned(&sc->sc_lock)); 1924 1925 LIST_REMOVE(std, hnext); 1926 } 1927 1928 ohci_soft_td_t * 1929 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1930 { 1931 int h = HASH(a); 1932 ohci_soft_td_t *std; 1933 1934 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1935 std != NULL; 1936 std = LIST_NEXT(std, hnext)) 1937 if (std->physaddr == a) 1938 return (std); 1939 return (NULL); 1940 } 1941 1942 /* Called with USB lock held. */ 1943 void 1944 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1945 { 1946 int h = HASH(sitd->physaddr); 1947 1948 KASSERT(mutex_owned(&sc->sc_lock)); 1949 1950 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1951 sitd, (u_long)sitd->physaddr)); 1952 1953 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1954 } 1955 1956 /* Called with USB lock held. */ 1957 void 1958 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1959 { 1960 1961 KASSERT(mutex_owned(&sc->sc_lock)); 1962 1963 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1964 sitd, (u_long)sitd->physaddr)); 1965 1966 LIST_REMOVE(sitd, hnext); 1967 } 1968 1969 ohci_soft_itd_t * 1970 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1971 { 1972 int h = HASH(a); 1973 ohci_soft_itd_t *sitd; 1974 1975 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1976 sitd != NULL; 1977 sitd = LIST_NEXT(sitd, hnext)) 1978 if (sitd->physaddr == a) 1979 return (sitd); 1980 return (NULL); 1981 } 1982 1983 void 1984 ohci_timeout(void *addr) 1985 { 1986 struct ohci_xfer *oxfer = addr; 1987 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1988 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1989 1990 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1991 1992 if (sc->sc_dying) { 1993 mutex_enter(&sc->sc_lock); 1994 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1995 mutex_exit(&sc->sc_lock); 1996 return; 1997 } 1998 1999 /* Execute the abort in a process context. */ 2000 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2001 USB_TASKQ_MPSAFE); 2002 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2003 USB_TASKQ_HC); 2004 } 2005 2006 void 2007 ohci_timeout_task(void *addr) 2008 { 2009 usbd_xfer_handle xfer = addr; 2010 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2011 2012 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2013 2014 mutex_enter(&sc->sc_lock); 2015 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2016 mutex_exit(&sc->sc_lock); 2017 } 2018 2019 #ifdef OHCI_DEBUG 2020 void 2021 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2022 { 2023 for (; std; std = std->nexttd) 2024 ohci_dump_td(sc, std); 2025 } 2026 2027 void 2028 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2029 { 2030 char sbuf[128]; 2031 2032 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2033 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2034 snprintb(sbuf, sizeof(sbuf), 2035 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2036 (u_int32_t)O32TOH(std->td.td_flags)); 2037 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2038 "nexttd=0x%08lx be=0x%08lx\n", 2039 std, (u_long)std->physaddr, sbuf, 2040 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2041 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2042 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2043 (u_long)O32TOH(std->td.td_cbp), 2044 (u_long)O32TOH(std->td.td_nexttd), 2045 (u_long)O32TOH(std->td.td_be)); 2046 } 2047 2048 void 2049 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2050 { 2051 int i; 2052 2053 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2055 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2056 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2057 sitd, (u_long)sitd->physaddr, 2058 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2059 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2060 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2061 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2062 (u_long)O32TOH(sitd->itd.itd_bp0), 2063 (u_long)O32TOH(sitd->itd.itd_nextitd), 2064 (u_long)O32TOH(sitd->itd.itd_be)); 2065 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2066 printf("offs[%d]=0x%04x ", i, 2067 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2068 printf("\n"); 2069 } 2070 2071 void 2072 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2073 { 2074 for (; sitd; sitd = sitd->nextitd) 2075 ohci_dump_itd(sc, sitd); 2076 } 2077 2078 void 2079 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2080 { 2081 char sbuf[128], sbuf2[128]; 2082 2083 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2084 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2085 snprintb(sbuf, sizeof(sbuf), 2086 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2087 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2088 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2089 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2090 2091 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2092 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2093 sed, (u_long)sed->physaddr, 2094 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2095 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2096 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2097 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2098 (u_long)O32TOH(sed->ed.ed_headp), 2099 (u_long)O32TOH(sed->ed.ed_nexted)); 2100 } 2101 #endif 2102 2103 usbd_status 2104 ohci_open(usbd_pipe_handle pipe) 2105 { 2106 usbd_device_handle dev = pipe->device; 2107 ohci_softc_t *sc = dev->bus->hci_private; 2108 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2109 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2110 u_int8_t addr = dev->address; 2111 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2112 ohci_soft_ed_t *sed; 2113 ohci_soft_td_t *std; 2114 ohci_soft_itd_t *sitd; 2115 ohci_physaddr_t tdphys; 2116 u_int32_t fmt; 2117 usbd_status err = USBD_NOMEM; 2118 int ival; 2119 2120 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2121 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2122 2123 if (sc->sc_dying) { 2124 err = USBD_IOERROR; 2125 goto bad0; 2126 } 2127 2128 std = NULL; 2129 sed = NULL; 2130 2131 if (addr == sc->sc_addr) { 2132 switch (ed->bEndpointAddress) { 2133 case USB_CONTROL_ENDPOINT: 2134 pipe->methods = &ohci_root_ctrl_methods; 2135 break; 2136 case UE_DIR_IN | OHCI_INTR_ENDPT: 2137 pipe->methods = &ohci_root_intr_methods; 2138 break; 2139 default: 2140 err = USBD_INVAL; 2141 goto bad0; 2142 } 2143 } else { 2144 sed = ohci_alloc_sed(sc); 2145 if (sed == NULL) 2146 goto bad0; 2147 opipe->sed = sed; 2148 if (xfertype == UE_ISOCHRONOUS) { 2149 mutex_enter(&sc->sc_lock); 2150 sitd = ohci_alloc_sitd(sc); 2151 mutex_exit(&sc->sc_lock); 2152 if (sitd == NULL) 2153 goto bad1; 2154 opipe->tail.itd = sitd; 2155 tdphys = sitd->physaddr; 2156 fmt = OHCI_ED_FORMAT_ISO; 2157 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2158 fmt |= OHCI_ED_DIR_IN; 2159 else 2160 fmt |= OHCI_ED_DIR_OUT; 2161 } else { 2162 mutex_enter(&sc->sc_lock); 2163 std = ohci_alloc_std(sc); 2164 mutex_exit(&sc->sc_lock); 2165 if (std == NULL) 2166 goto bad1; 2167 opipe->tail.td = std; 2168 tdphys = std->physaddr; 2169 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2170 } 2171 sed->ed.ed_flags = HTOO32( 2172 OHCI_ED_SET_FA(addr) | 2173 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2174 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2175 fmt | 2176 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2177 sed->ed.ed_headp = HTOO32(tdphys | 2178 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2179 sed->ed.ed_tailp = HTOO32(tdphys); 2180 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2182 2183 switch (xfertype) { 2184 case UE_CONTROL: 2185 pipe->methods = &ohci_device_ctrl_methods; 2186 err = usb_allocmem(&sc->sc_bus, 2187 sizeof(usb_device_request_t), 2188 0, &opipe->u.ctl.reqdma); 2189 if (err) 2190 goto bad; 2191 mutex_enter(&sc->sc_lock); 2192 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2193 mutex_exit(&sc->sc_lock); 2194 break; 2195 case UE_INTERRUPT: 2196 pipe->methods = &ohci_device_intr_methods; 2197 ival = pipe->interval; 2198 if (ival == USBD_DEFAULT_INTERVAL) 2199 ival = ed->bInterval; 2200 err = ohci_device_setintr(sc, opipe, ival); 2201 if (err) 2202 goto bad; 2203 break; 2204 case UE_ISOCHRONOUS: 2205 pipe->methods = &ohci_device_isoc_methods; 2206 return (ohci_setup_isoc(pipe)); 2207 case UE_BULK: 2208 pipe->methods = &ohci_device_bulk_methods; 2209 mutex_enter(&sc->sc_lock); 2210 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2211 mutex_exit(&sc->sc_lock); 2212 break; 2213 } 2214 } 2215 2216 return USBD_NORMAL_COMPLETION; 2217 2218 bad: 2219 if (std != NULL) 2220 ohci_free_std(sc, std); 2221 bad1: 2222 if (sed != NULL) 2223 ohci_free_sed(sc, sed); 2224 bad0: 2225 return err; 2226 2227 } 2228 2229 /* 2230 * Close a reqular pipe. 2231 * Assumes that there are no pending transactions. 2232 */ 2233 void 2234 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2235 { 2236 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2237 ohci_softc_t *sc = pipe->device->bus->hci_private; 2238 ohci_soft_ed_t *sed = opipe->sed; 2239 2240 KASSERT(mutex_owned(&sc->sc_lock)); 2241 2242 #ifdef DIAGNOSTIC 2243 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2244 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2245 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2246 ohci_soft_td_t *std; 2247 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2248 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2249 "tl=0x%x pipe=%p, std=%p\n", sed, 2250 (int)O32TOH(sed->ed.ed_headp), 2251 (int)O32TOH(sed->ed.ed_tailp), 2252 pipe, std); 2253 #ifdef OHCI_DEBUG 2254 usbd_dump_pipe(&opipe->pipe); 2255 ohci_dump_ed(sc, sed); 2256 if (std) 2257 ohci_dump_td(sc, std); 2258 #endif 2259 usb_delay_ms(&sc->sc_bus, 2); 2260 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2261 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2262 printf("ohci_close_pipe: pipe still not empty\n"); 2263 } 2264 #endif 2265 ohci_rem_ed(sc, sed, head); 2266 /* Make sure the host controller is not touching this ED */ 2267 usb_delay_ms(&sc->sc_bus, 1); 2268 pipe->endpoint->datatoggle = 2269 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2270 ohci_free_sed(sc, opipe->sed); 2271 } 2272 2273 /* 2274 * Abort a device request. 2275 * If this routine is called at splusb() it guarantees that the request 2276 * will be removed from the hardware scheduling and that the callback 2277 * for it will be called with USBD_CANCELLED status. 2278 * It's impossible to guarantee that the requested transfer will not 2279 * have happened since the hardware runs concurrently. 2280 * If the transaction has already happened we rely on the ordinary 2281 * interrupt processing to process it. 2282 * XXX This is most probably wrong. 2283 * XXXMRG this doesn't make sense anymore. 2284 */ 2285 void 2286 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2287 { 2288 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2289 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2290 ohci_soft_ed_t *sed = opipe->sed; 2291 ohci_soft_td_t *p, *n; 2292 ohci_physaddr_t headp; 2293 int hit; 2294 int wake; 2295 2296 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2297 2298 KASSERT(mutex_owned(&sc->sc_lock)); 2299 2300 if (sc->sc_dying) { 2301 /* If we're dying, just do the software part. */ 2302 xfer->status = status; /* make software ignore it */ 2303 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2304 usb_transfer_complete(xfer); 2305 return; 2306 } 2307 2308 if (cpu_intr_p() || cpu_softintr_p()) 2309 panic("ohci_abort_xfer: not in process context"); 2310 2311 /* 2312 * If an abort is already in progress then just wait for it to 2313 * complete and return. 2314 */ 2315 if (xfer->hcflags & UXFER_ABORTING) { 2316 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2317 #ifdef DIAGNOSTIC 2318 if (status == USBD_TIMEOUT) 2319 printf("%s: TIMEOUT while aborting\n", __func__); 2320 #endif 2321 /* Override the status which might be USBD_TIMEOUT. */ 2322 xfer->status = status; 2323 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2324 xfer->hcflags |= UXFER_ABORTWAIT; 2325 while (xfer->hcflags & UXFER_ABORTING) 2326 cv_wait(&xfer->hccv, &sc->sc_lock); 2327 goto done; 2328 } 2329 xfer->hcflags |= UXFER_ABORTING; 2330 2331 /* 2332 * Step 1: Make interrupt routine and hardware ignore xfer. 2333 */ 2334 xfer->status = status; /* make software ignore it */ 2335 callout_stop(&xfer->timeout_handle); 2336 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2337 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2338 sizeof(sed->ed.ed_flags), 2339 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2340 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2341 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2342 sizeof(sed->ed.ed_flags), 2343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2344 2345 /* 2346 * Step 2: Wait until we know hardware has finished any possible 2347 * use of the xfer. Also make sure the soft interrupt routine 2348 * has run. 2349 */ 2350 /* Hardware finishes in 1ms */ 2351 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2352 sc->sc_softwake = 1; 2353 usb_schedsoftintr(&sc->sc_bus); 2354 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2355 2356 /* 2357 * Step 3: Remove any vestiges of the xfer from the hardware. 2358 * The complication here is that the hardware may have executed 2359 * beyond the xfer we're trying to abort. So as we're scanning 2360 * the TDs of this xfer we check if the hardware points to 2361 * any of them. 2362 */ 2363 p = xfer->hcpriv; 2364 #ifdef DIAGNOSTIC 2365 if (p == NULL) { 2366 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2367 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2368 goto done; 2369 } 2370 #endif 2371 #ifdef OHCI_DEBUG 2372 if (ohcidebug > 1) { 2373 DPRINTF(("ohci_abort_xfer: sed=\n")); 2374 ohci_dump_ed(sc, sed); 2375 ohci_dump_tds(sc, p); 2376 } 2377 #endif 2378 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2379 hit = 0; 2380 for (; p->xfer == xfer; p = n) { 2381 hit |= headp == p->physaddr; 2382 n = p->nexttd; 2383 ohci_free_std(sc, p); 2384 } 2385 /* Zap headp register if hardware pointed inside the xfer. */ 2386 if (hit) { 2387 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2388 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2389 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2390 usb_syncmem(&sed->dma, 2391 sed->offs + offsetof(ohci_ed_t, ed_headp), 2392 sizeof(sed->ed.ed_headp), 2393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2394 } else { 2395 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2396 } 2397 2398 /* 2399 * Step 4: Turn on hardware again. 2400 */ 2401 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2402 sizeof(sed->ed.ed_flags), 2403 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2404 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2405 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2406 sizeof(sed->ed.ed_flags), 2407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2408 2409 /* 2410 * Step 5: Execute callback. 2411 */ 2412 wake = xfer->hcflags & UXFER_ABORTWAIT; 2413 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2414 usb_transfer_complete(xfer); 2415 if (wake) 2416 cv_broadcast(&xfer->hccv); 2417 2418 done: 2419 KASSERT(mutex_owned(&sc->sc_lock)); 2420 } 2421 2422 /* 2423 * Data structures and routines to emulate the root hub. 2424 */ 2425 Static usb_device_descriptor_t ohci_devd = { 2426 USB_DEVICE_DESCRIPTOR_SIZE, 2427 UDESC_DEVICE, /* type */ 2428 {0x00, 0x01}, /* USB version */ 2429 UDCLASS_HUB, /* class */ 2430 UDSUBCLASS_HUB, /* subclass */ 2431 UDPROTO_FSHUB, /* protocol */ 2432 64, /* max packet */ 2433 {0},{0},{0x00,0x01}, /* device id */ 2434 1,2,0, /* string indicies */ 2435 1 /* # of configurations */ 2436 }; 2437 2438 Static const usb_config_descriptor_t ohci_confd = { 2439 USB_CONFIG_DESCRIPTOR_SIZE, 2440 UDESC_CONFIG, 2441 {USB_CONFIG_DESCRIPTOR_SIZE + 2442 USB_INTERFACE_DESCRIPTOR_SIZE + 2443 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2444 1, 2445 1, 2446 0, 2447 UC_ATTR_MBO | UC_SELF_POWERED, 2448 0 /* max power */ 2449 }; 2450 2451 Static const usb_interface_descriptor_t ohci_ifcd = { 2452 USB_INTERFACE_DESCRIPTOR_SIZE, 2453 UDESC_INTERFACE, 2454 0, 2455 0, 2456 1, 2457 UICLASS_HUB, 2458 UISUBCLASS_HUB, 2459 UIPROTO_FSHUB, 2460 0 2461 }; 2462 2463 Static const usb_endpoint_descriptor_t ohci_endpd = { 2464 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2465 .bDescriptorType = UDESC_ENDPOINT, 2466 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2467 .bmAttributes = UE_INTERRUPT, 2468 .wMaxPacketSize = {8, 0}, /* max packet */ 2469 .bInterval = 255, 2470 }; 2471 2472 Static const usb_hub_descriptor_t ohci_hubd = { 2473 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2474 .bDescriptorType = UDESC_HUB, 2475 }; 2476 2477 /* 2478 * Simulate a hardware hub by handling all the necessary requests. 2479 */ 2480 Static usbd_status 2481 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2482 { 2483 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2484 usbd_status err; 2485 2486 /* Insert last in queue. */ 2487 mutex_enter(&sc->sc_lock); 2488 err = usb_insert_transfer(xfer); 2489 mutex_exit(&sc->sc_lock); 2490 if (err) 2491 return (err); 2492 2493 /* Pipe isn't running, start first */ 2494 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2495 } 2496 2497 Static usbd_status 2498 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2499 { 2500 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2501 usb_device_request_t *req; 2502 void *buf = NULL; 2503 int port, i; 2504 int len, value, index, l, totlen = 0; 2505 usb_port_status_t ps; 2506 usb_hub_descriptor_t hubd; 2507 usbd_status err; 2508 u_int32_t v; 2509 2510 if (sc->sc_dying) 2511 return (USBD_IOERROR); 2512 2513 #ifdef DIAGNOSTIC 2514 if (!(xfer->rqflags & URQ_REQUEST)) 2515 /* XXX panic */ 2516 return (USBD_INVAL); 2517 #endif 2518 req = &xfer->request; 2519 2520 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2521 req->bmRequestType, req->bRequest)); 2522 2523 len = UGETW(req->wLength); 2524 value = UGETW(req->wValue); 2525 index = UGETW(req->wIndex); 2526 2527 if (len != 0) 2528 buf = KERNADDR(&xfer->dmabuf, 0); 2529 2530 #define C(x,y) ((x) | ((y) << 8)) 2531 switch(C(req->bRequest, req->bmRequestType)) { 2532 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2533 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2534 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2535 /* 2536 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2537 * for the integrated root hub. 2538 */ 2539 break; 2540 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2541 if (len > 0) { 2542 *(u_int8_t *)buf = sc->sc_conf; 2543 totlen = 1; 2544 } 2545 break; 2546 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2547 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2548 if (len == 0) 2549 break; 2550 switch(value >> 8) { 2551 case UDESC_DEVICE: 2552 if ((value & 0xff) != 0) { 2553 err = USBD_IOERROR; 2554 goto ret; 2555 } 2556 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2557 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2558 memcpy(buf, &ohci_devd, l); 2559 break; 2560 case UDESC_CONFIG: 2561 if ((value & 0xff) != 0) { 2562 err = USBD_IOERROR; 2563 goto ret; 2564 } 2565 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2566 memcpy(buf, &ohci_confd, l); 2567 buf = (char *)buf + l; 2568 len -= l; 2569 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2570 totlen += l; 2571 memcpy(buf, &ohci_ifcd, l); 2572 buf = (char *)buf + l; 2573 len -= l; 2574 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2575 totlen += l; 2576 memcpy(buf, &ohci_endpd, l); 2577 break; 2578 case UDESC_STRING: 2579 #define sd ((usb_string_descriptor_t *)buf) 2580 switch (value & 0xff) { 2581 case 0: /* Language table */ 2582 totlen = usb_makelangtbl(sd, len); 2583 break; 2584 case 1: /* Vendor */ 2585 totlen = usb_makestrdesc(sd, len, 2586 sc->sc_vendor); 2587 break; 2588 case 2: /* Product */ 2589 totlen = usb_makestrdesc(sd, len, 2590 "OHCI root hub"); 2591 break; 2592 } 2593 #undef sd 2594 break; 2595 default: 2596 err = USBD_IOERROR; 2597 goto ret; 2598 } 2599 break; 2600 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2601 if (len > 0) { 2602 *(u_int8_t *)buf = 0; 2603 totlen = 1; 2604 } 2605 break; 2606 case C(UR_GET_STATUS, UT_READ_DEVICE): 2607 if (len > 1) { 2608 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2609 totlen = 2; 2610 } 2611 break; 2612 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2613 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2614 if (len > 1) { 2615 USETW(((usb_status_t *)buf)->wStatus, 0); 2616 totlen = 2; 2617 } 2618 break; 2619 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2620 if (value >= USB_MAX_DEVICES) { 2621 err = USBD_IOERROR; 2622 goto ret; 2623 } 2624 sc->sc_addr = value; 2625 break; 2626 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2627 if (value != 0 && value != 1) { 2628 err = USBD_IOERROR; 2629 goto ret; 2630 } 2631 sc->sc_conf = value; 2632 break; 2633 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2634 break; 2635 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2636 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2637 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2638 err = USBD_IOERROR; 2639 goto ret; 2640 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2641 break; 2642 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2643 break; 2644 /* Hub requests */ 2645 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2646 break; 2647 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2648 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2649 "port=%d feature=%d\n", 2650 index, value)); 2651 if (index < 1 || index > sc->sc_noport) { 2652 err = USBD_IOERROR; 2653 goto ret; 2654 } 2655 port = OHCI_RH_PORT_STATUS(index); 2656 switch(value) { 2657 case UHF_PORT_ENABLE: 2658 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2659 break; 2660 case UHF_PORT_SUSPEND: 2661 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2662 break; 2663 case UHF_PORT_POWER: 2664 /* Yes, writing to the LOW_SPEED bit clears power. */ 2665 OWRITE4(sc, port, UPS_LOW_SPEED); 2666 break; 2667 case UHF_C_PORT_CONNECTION: 2668 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2669 break; 2670 case UHF_C_PORT_ENABLE: 2671 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2672 break; 2673 case UHF_C_PORT_SUSPEND: 2674 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2675 break; 2676 case UHF_C_PORT_OVER_CURRENT: 2677 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2678 break; 2679 case UHF_C_PORT_RESET: 2680 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2681 break; 2682 default: 2683 err = USBD_IOERROR; 2684 goto ret; 2685 } 2686 switch(value) { 2687 case UHF_C_PORT_CONNECTION: 2688 case UHF_C_PORT_ENABLE: 2689 case UHF_C_PORT_SUSPEND: 2690 case UHF_C_PORT_OVER_CURRENT: 2691 case UHF_C_PORT_RESET: 2692 /* Enable RHSC interrupt if condition is cleared. */ 2693 if ((OREAD4(sc, port) >> 16) == 0) 2694 ohci_rhsc_enable(sc); 2695 break; 2696 default: 2697 break; 2698 } 2699 break; 2700 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2701 if (len == 0) 2702 break; 2703 if ((value & 0xff) != 0) { 2704 err = USBD_IOERROR; 2705 goto ret; 2706 } 2707 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2708 hubd = ohci_hubd; 2709 hubd.bNbrPorts = sc->sc_noport; 2710 USETW(hubd.wHubCharacteristics, 2711 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2712 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2713 /* XXX overcurrent */ 2714 ); 2715 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2716 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2717 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2718 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2719 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2720 l = min(len, hubd.bDescLength); 2721 totlen = l; 2722 memcpy(buf, &hubd, l); 2723 break; 2724 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2725 if (len != 4) { 2726 err = USBD_IOERROR; 2727 goto ret; 2728 } 2729 memset(buf, 0, len); /* ? XXX */ 2730 totlen = len; 2731 break; 2732 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2733 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2734 index)); 2735 if (index < 1 || index > sc->sc_noport) { 2736 err = USBD_IOERROR; 2737 goto ret; 2738 } 2739 if (len != 4) { 2740 err = USBD_IOERROR; 2741 goto ret; 2742 } 2743 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2744 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2745 v)); 2746 USETW(ps.wPortStatus, v); 2747 USETW(ps.wPortChange, v >> 16); 2748 l = min(len, sizeof ps); 2749 memcpy(buf, &ps, l); 2750 totlen = l; 2751 break; 2752 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2753 err = USBD_IOERROR; 2754 goto ret; 2755 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2756 break; 2757 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2758 if (index < 1 || index > sc->sc_noport) { 2759 err = USBD_IOERROR; 2760 goto ret; 2761 } 2762 port = OHCI_RH_PORT_STATUS(index); 2763 switch(value) { 2764 case UHF_PORT_ENABLE: 2765 OWRITE4(sc, port, UPS_PORT_ENABLED); 2766 break; 2767 case UHF_PORT_SUSPEND: 2768 OWRITE4(sc, port, UPS_SUSPEND); 2769 break; 2770 case UHF_PORT_RESET: 2771 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2772 index)); 2773 OWRITE4(sc, port, UPS_RESET); 2774 for (i = 0; i < 5; i++) { 2775 usb_delay_ms(&sc->sc_bus, 2776 USB_PORT_ROOT_RESET_DELAY); 2777 if (sc->sc_dying) { 2778 err = USBD_IOERROR; 2779 goto ret; 2780 } 2781 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2782 break; 2783 } 2784 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2785 index, OREAD4(sc, port))); 2786 break; 2787 case UHF_PORT_POWER: 2788 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2789 "%d\n", index)); 2790 OWRITE4(sc, port, UPS_PORT_POWER); 2791 break; 2792 default: 2793 err = USBD_IOERROR; 2794 goto ret; 2795 } 2796 break; 2797 default: 2798 err = USBD_IOERROR; 2799 goto ret; 2800 } 2801 xfer->actlen = totlen; 2802 err = USBD_NORMAL_COMPLETION; 2803 ret: 2804 xfer->status = err; 2805 mutex_enter(&sc->sc_lock); 2806 usb_transfer_complete(xfer); 2807 mutex_exit(&sc->sc_lock); 2808 return (USBD_IN_PROGRESS); 2809 } 2810 2811 /* Abort a root control request. */ 2812 Static void 2813 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2814 { 2815 /* Nothing to do, all transfers are synchronous. */ 2816 } 2817 2818 /* Close the root pipe. */ 2819 Static void 2820 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2821 { 2822 DPRINTF(("ohci_root_ctrl_close\n")); 2823 /* Nothing to do. */ 2824 } 2825 2826 Static usbd_status 2827 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2828 { 2829 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2830 usbd_status err; 2831 2832 /* Insert last in queue. */ 2833 mutex_enter(&sc->sc_lock); 2834 err = usb_insert_transfer(xfer); 2835 mutex_exit(&sc->sc_lock); 2836 if (err) 2837 return (err); 2838 2839 /* Pipe isn't running, start first */ 2840 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2841 } 2842 2843 Static usbd_status 2844 ohci_root_intr_start(usbd_xfer_handle xfer) 2845 { 2846 usbd_pipe_handle pipe = xfer->pipe; 2847 ohci_softc_t *sc = pipe->device->bus->hci_private; 2848 2849 if (sc->sc_dying) 2850 return (USBD_IOERROR); 2851 2852 mutex_enter(&sc->sc_lock); 2853 KASSERT(sc->sc_intrxfer == NULL); 2854 sc->sc_intrxfer = xfer; 2855 mutex_exit(&sc->sc_lock); 2856 2857 return (USBD_IN_PROGRESS); 2858 } 2859 2860 /* Abort a root interrupt request. */ 2861 Static void 2862 ohci_root_intr_abort(usbd_xfer_handle xfer) 2863 { 2864 #ifdef DIAGNOSTIC 2865 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2866 #endif 2867 2868 KASSERT(mutex_owned(&sc->sc_lock)); 2869 2870 if (xfer->pipe->intrxfer == xfer) { 2871 DPRINTF(("ohci_root_intr_abort: remove\n")); 2872 xfer->pipe->intrxfer = NULL; 2873 } 2874 xfer->status = USBD_CANCELLED; 2875 usb_transfer_complete(xfer); 2876 } 2877 2878 /* Close the root pipe. */ 2879 Static void 2880 ohci_root_intr_close(usbd_pipe_handle pipe) 2881 { 2882 ohci_softc_t *sc = pipe->device->bus->hci_private; 2883 2884 KASSERT(mutex_owned(&sc->sc_lock)); 2885 2886 DPRINTF(("ohci_root_intr_close\n")); 2887 2888 sc->sc_intrxfer = NULL; 2889 } 2890 2891 /************************/ 2892 2893 Static usbd_status 2894 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2895 { 2896 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2897 usbd_status err; 2898 2899 /* Insert last in queue. */ 2900 mutex_enter(&sc->sc_lock); 2901 err = usb_insert_transfer(xfer); 2902 mutex_exit(&sc->sc_lock); 2903 if (err) 2904 return (err); 2905 2906 /* Pipe isn't running, start first */ 2907 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2908 } 2909 2910 Static usbd_status 2911 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2912 { 2913 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2914 usbd_status err; 2915 2916 if (sc->sc_dying) 2917 return (USBD_IOERROR); 2918 2919 #ifdef DIAGNOSTIC 2920 if (!(xfer->rqflags & URQ_REQUEST)) { 2921 /* XXX panic */ 2922 printf("ohci_device_ctrl_transfer: not a request\n"); 2923 return (USBD_INVAL); 2924 } 2925 #endif 2926 2927 mutex_enter(&sc->sc_lock); 2928 err = ohci_device_request(xfer); 2929 mutex_exit(&sc->sc_lock); 2930 if (err) 2931 return (err); 2932 2933 if (sc->sc_bus.use_polling) 2934 ohci_waitintr(sc, xfer); 2935 return (USBD_IN_PROGRESS); 2936 } 2937 2938 /* Abort a device control request. */ 2939 Static void 2940 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2941 { 2942 #ifdef DIAGNOSTIC 2943 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2944 #endif 2945 2946 KASSERT(mutex_owned(&sc->sc_lock)); 2947 2948 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2949 ohci_abort_xfer(xfer, USBD_CANCELLED); 2950 } 2951 2952 /* Close a device control pipe. */ 2953 Static void 2954 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2955 { 2956 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2957 ohci_softc_t *sc = pipe->device->bus->hci_private; 2958 2959 KASSERT(mutex_owned(&sc->sc_lock)); 2960 2961 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2962 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2963 ohci_free_std(sc, opipe->tail.td); 2964 } 2965 2966 /************************/ 2967 2968 Static void 2969 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2970 { 2971 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2972 ohci_softc_t *sc = pipe->device->bus->hci_private; 2973 2974 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2975 } 2976 2977 Static void 2978 ohci_noop(usbd_pipe_handle pipe) 2979 { 2980 } 2981 2982 Static usbd_status 2983 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2984 { 2985 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2986 usbd_status err; 2987 2988 /* Insert last in queue. */ 2989 mutex_enter(&sc->sc_lock); 2990 err = usb_insert_transfer(xfer); 2991 mutex_exit(&sc->sc_lock); 2992 if (err) 2993 return (err); 2994 2995 /* Pipe isn't running, start first */ 2996 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2997 } 2998 2999 Static usbd_status 3000 ohci_device_bulk_start(usbd_xfer_handle xfer) 3001 { 3002 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3003 usbd_device_handle dev = opipe->pipe.device; 3004 ohci_softc_t *sc = dev->bus->hci_private; 3005 int addr = dev->address; 3006 ohci_soft_td_t *data, *tail, *tdp; 3007 ohci_soft_ed_t *sed; 3008 int len, isread, endpt; 3009 usbd_status err; 3010 3011 if (sc->sc_dying) 3012 return (USBD_IOERROR); 3013 3014 #ifdef DIAGNOSTIC 3015 if (xfer->rqflags & URQ_REQUEST) { 3016 /* XXX panic */ 3017 printf("ohci_device_bulk_start: a request\n"); 3018 return (USBD_INVAL); 3019 } 3020 #endif 3021 3022 mutex_enter(&sc->sc_lock); 3023 3024 len = xfer->length; 3025 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3026 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3027 sed = opipe->sed; 3028 3029 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3030 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3031 endpt)); 3032 3033 opipe->u.bulk.isread = isread; 3034 opipe->u.bulk.length = len; 3035 3036 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3038 /* Update device address */ 3039 sed->ed.ed_flags = HTOO32( 3040 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3041 OHCI_ED_SET_FA(addr)); 3042 3043 /* Allocate a chain of new TDs (including a new tail). */ 3044 data = opipe->tail.td; 3045 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3046 data, &tail); 3047 /* We want interrupt at the end of the transfer. */ 3048 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3049 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3050 tail->flags |= OHCI_CALL_DONE; 3051 tail = tail->nexttd; /* point at sentinel */ 3052 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3053 sizeof(tail->td.td_flags), 3054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3055 if (err) { 3056 mutex_exit(&sc->sc_lock); 3057 return (err); 3058 } 3059 3060 tail->xfer = NULL; 3061 xfer->hcpriv = data; 3062 3063 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3064 "td_cbp=0x%08x td_be=0x%08x\n", 3065 (int)O32TOH(sed->ed.ed_flags), 3066 (int)O32TOH(data->td.td_flags), 3067 (int)O32TOH(data->td.td_cbp), 3068 (int)O32TOH(data->td.td_be))); 3069 3070 #ifdef OHCI_DEBUG 3071 if (ohcidebug > 5) { 3072 ohci_dump_ed(sc, sed); 3073 ohci_dump_tds(sc, data); 3074 } 3075 #endif 3076 3077 /* Insert ED in schedule */ 3078 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3079 tdp->xfer = xfer; 3080 } 3081 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3082 opipe->tail.td = tail; 3083 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3084 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3085 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3086 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3087 if (xfer->timeout && !sc->sc_bus.use_polling) { 3088 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3089 ohci_timeout, xfer); 3090 } 3091 mutex_exit(&sc->sc_lock); 3092 3093 #if 0 3094 /* This goes wrong if we are too slow. */ 3095 if (ohcidebug > 10) { 3096 delay(10000); 3097 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3098 OREAD4(sc, OHCI_COMMAND_STATUS))); 3099 ohci_dump_ed(sc, sed); 3100 ohci_dump_tds(sc, data); 3101 } 3102 #endif 3103 3104 return (USBD_IN_PROGRESS); 3105 } 3106 3107 Static void 3108 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3109 { 3110 #ifdef DIAGNOSTIC 3111 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3112 #endif 3113 3114 KASSERT(mutex_owned(&sc->sc_lock)); 3115 3116 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3117 ohci_abort_xfer(xfer, USBD_CANCELLED); 3118 } 3119 3120 /* 3121 * Close a device bulk pipe. 3122 */ 3123 Static void 3124 ohci_device_bulk_close(usbd_pipe_handle pipe) 3125 { 3126 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3127 ohci_softc_t *sc = pipe->device->bus->hci_private; 3128 3129 KASSERT(mutex_owned(&sc->sc_lock)); 3130 3131 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3132 ohci_close_pipe(pipe, sc->sc_bulk_head); 3133 ohci_free_std(sc, opipe->tail.td); 3134 } 3135 3136 /************************/ 3137 3138 Static usbd_status 3139 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3140 { 3141 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3142 usbd_status err; 3143 3144 /* Insert last in queue. */ 3145 mutex_enter(&sc->sc_lock); 3146 err = usb_insert_transfer(xfer); 3147 mutex_exit(&sc->sc_lock); 3148 if (err) 3149 return (err); 3150 3151 /* Pipe isn't running, start first */ 3152 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3153 } 3154 3155 Static usbd_status 3156 ohci_device_intr_start(usbd_xfer_handle xfer) 3157 { 3158 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3159 usbd_device_handle dev = opipe->pipe.device; 3160 ohci_softc_t *sc = dev->bus->hci_private; 3161 ohci_soft_ed_t *sed = opipe->sed; 3162 ohci_soft_td_t *data, *tail; 3163 int len, isread, endpt; 3164 3165 if (sc->sc_dying) 3166 return (USBD_IOERROR); 3167 3168 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3169 "flags=%d priv=%p\n", 3170 xfer, xfer->length, xfer->flags, xfer->priv)); 3171 3172 #ifdef DIAGNOSTIC 3173 if (xfer->rqflags & URQ_REQUEST) 3174 panic("ohci_device_intr_transfer: a request"); 3175 #endif 3176 3177 len = xfer->length; 3178 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3179 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3180 3181 data = opipe->tail.td; 3182 mutex_enter(&sc->sc_lock); 3183 tail = ohci_alloc_std(sc); 3184 mutex_exit(&sc->sc_lock); 3185 if (tail == NULL) 3186 return (USBD_NOMEM); 3187 tail->xfer = NULL; 3188 3189 data->td.td_flags = HTOO32( 3190 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3191 OHCI_TD_NOCC | 3192 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3193 if (xfer->flags & USBD_SHORT_XFER_OK) 3194 data->td.td_flags |= HTOO32(OHCI_TD_R); 3195 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3196 data->nexttd = tail; 3197 data->td.td_nexttd = HTOO32(tail->physaddr); 3198 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3199 data->len = len; 3200 data->xfer = xfer; 3201 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3202 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3203 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3204 xfer->hcpriv = data; 3205 3206 #ifdef OHCI_DEBUG 3207 if (ohcidebug > 5) { 3208 DPRINTF(("ohci_device_intr_transfer:\n")); 3209 ohci_dump_ed(sc, sed); 3210 ohci_dump_tds(sc, data); 3211 } 3212 #endif 3213 3214 /* Insert ED in schedule */ 3215 mutex_enter(&sc->sc_lock); 3216 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3217 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3218 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3219 opipe->tail.td = tail; 3220 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3221 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3223 3224 #if 0 3225 /* 3226 * This goes horribly wrong, printing thousands of descriptors, 3227 * because false references are followed due to the fact that the 3228 * TD is gone. 3229 */ 3230 if (ohcidebug > 5) { 3231 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3232 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3233 OREAD4(sc, OHCI_COMMAND_STATUS))); 3234 ohci_dump_ed(sc, sed); 3235 ohci_dump_tds(sc, data); 3236 } 3237 #endif 3238 mutex_exit(&sc->sc_lock); 3239 3240 return (USBD_IN_PROGRESS); 3241 } 3242 3243 /* Abort a device interrupt request. */ 3244 Static void 3245 ohci_device_intr_abort(usbd_xfer_handle xfer) 3246 { 3247 #ifdef DIAGNOSTIC 3248 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3249 #endif 3250 3251 KASSERT(mutex_owned(&sc->sc_lock)); 3252 3253 if (xfer->pipe->intrxfer == xfer) { 3254 DPRINTF(("ohci_device_intr_abort: remove\n")); 3255 xfer->pipe->intrxfer = NULL; 3256 } 3257 ohci_abort_xfer(xfer, USBD_CANCELLED); 3258 } 3259 3260 /* Close a device interrupt pipe. */ 3261 Static void 3262 ohci_device_intr_close(usbd_pipe_handle pipe) 3263 { 3264 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3265 ohci_softc_t *sc = pipe->device->bus->hci_private; 3266 int nslots = opipe->u.intr.nslots; 3267 int pos = opipe->u.intr.pos; 3268 int j; 3269 ohci_soft_ed_t *p, *sed = opipe->sed; 3270 3271 KASSERT(mutex_owned(&sc->sc_lock)); 3272 3273 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3274 pipe, nslots, pos)); 3275 usb_syncmem(&sed->dma, sed->offs, 3276 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3277 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3278 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3279 sizeof(sed->ed.ed_flags), 3280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3281 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3282 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3283 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3284 3285 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3286 continue; 3287 #ifdef DIAGNOSTIC 3288 if (p == NULL) 3289 panic("ohci_device_intr_close: ED not found"); 3290 #endif 3291 p->next = sed->next; 3292 p->ed.ed_nexted = sed->ed.ed_nexted; 3293 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3294 sizeof(p->ed.ed_nexted), 3295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3296 3297 for (j = 0; j < nslots; j++) 3298 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3299 3300 ohci_free_std(sc, opipe->tail.td); 3301 ohci_free_sed(sc, opipe->sed); 3302 } 3303 3304 Static usbd_status 3305 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3306 { 3307 int i, j, best; 3308 u_int npoll, slow, shigh, nslots; 3309 u_int bestbw, bw; 3310 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3311 3312 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3313 if (ival == 0) { 3314 printf("ohci_setintr: 0 interval\n"); 3315 return (USBD_INVAL); 3316 } 3317 3318 npoll = OHCI_NO_INTRS; 3319 while (npoll > ival) 3320 npoll /= 2; 3321 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3322 3323 /* 3324 * We now know which level in the tree the ED must go into. 3325 * Figure out which slot has most bandwidth left over. 3326 * Slots to examine: 3327 * npoll 3328 * 1 0 3329 * 2 1 2 3330 * 4 3 4 5 6 3331 * 8 7 8 9 10 11 12 13 14 3332 * N (N-1) .. (N-1+N-1) 3333 */ 3334 slow = npoll-1; 3335 shigh = slow + npoll; 3336 nslots = OHCI_NO_INTRS / npoll; 3337 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3338 bw = 0; 3339 for (j = 0; j < nslots; j++) 3340 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3341 if (bw < bestbw) { 3342 best = i; 3343 bestbw = bw; 3344 } 3345 } 3346 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3347 best, slow, shigh, bestbw)); 3348 3349 mutex_enter(&sc->sc_lock); 3350 hsed = sc->sc_eds[best]; 3351 sed->next = hsed->next; 3352 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3353 sizeof(hsed->ed.ed_flags), 3354 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3355 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3356 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3357 sizeof(sed->ed.ed_flags), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 hsed->next = sed; 3360 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3361 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3362 sizeof(hsed->ed.ed_flags), 3363 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3364 mutex_exit(&sc->sc_lock); 3365 3366 for (j = 0; j < nslots; j++) 3367 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3368 opipe->u.intr.nslots = nslots; 3369 opipe->u.intr.pos = best; 3370 3371 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3372 return (USBD_NORMAL_COMPLETION); 3373 } 3374 3375 /***********************/ 3376 3377 usbd_status 3378 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3379 { 3380 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3381 usbd_status err; 3382 3383 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3384 3385 /* Put it on our queue, */ 3386 mutex_enter(&sc->sc_lock); 3387 err = usb_insert_transfer(xfer); 3388 mutex_exit(&sc->sc_lock); 3389 3390 /* bail out on error, */ 3391 if (err && err != USBD_IN_PROGRESS) 3392 return (err); 3393 3394 /* XXX should check inuse here */ 3395 3396 /* insert into schedule, */ 3397 ohci_device_isoc_enter(xfer); 3398 3399 /* and start if the pipe wasn't running */ 3400 if (!err) 3401 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3402 3403 return (err); 3404 } 3405 3406 void 3407 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3408 { 3409 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3410 usbd_device_handle dev = opipe->pipe.device; 3411 ohci_softc_t *sc = dev->bus->hci_private; 3412 ohci_soft_ed_t *sed = opipe->sed; 3413 struct iso *iso = &opipe->u.iso; 3414 ohci_soft_itd_t *sitd, *nsitd; 3415 ohci_physaddr_t buf, offs, noffs, bp0; 3416 int i, ncur, nframes; 3417 3418 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3419 "nframes=%d\n", 3420 iso->inuse, iso->next, xfer, xfer->nframes)); 3421 3422 if (sc->sc_dying) 3423 return; 3424 3425 if (iso->next == -1) { 3426 /* Not in use yet, schedule it a few frames ahead. */ 3427 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3428 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3429 iso->next)); 3430 } 3431 3432 sitd = opipe->tail.itd; 3433 buf = DMAADDR(&xfer->dmabuf, 0); 3434 bp0 = OHCI_PAGE(buf); 3435 offs = OHCI_PAGE_OFFSET(buf); 3436 nframes = xfer->nframes; 3437 xfer->hcpriv = sitd; 3438 for (i = ncur = 0; i < nframes; i++, ncur++) { 3439 noffs = offs + xfer->frlengths[i]; 3440 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3441 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3442 3443 /* Allocate next ITD */ 3444 mutex_enter(&sc->sc_lock); 3445 nsitd = ohci_alloc_sitd(sc); 3446 mutex_exit(&sc->sc_lock); 3447 if (nsitd == NULL) { 3448 /* XXX what now? */ 3449 printf("%s: isoc TD alloc failed\n", 3450 device_xname(sc->sc_dev)); 3451 return; 3452 } 3453 3454 /* Fill current ITD */ 3455 sitd->itd.itd_flags = HTOO32( 3456 OHCI_ITD_NOCC | 3457 OHCI_ITD_SET_SF(iso->next) | 3458 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3459 OHCI_ITD_SET_FC(ncur)); 3460 sitd->itd.itd_bp0 = HTOO32(bp0); 3461 sitd->nextitd = nsitd; 3462 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3463 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3464 sitd->xfer = xfer; 3465 sitd->flags = 0; 3466 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3468 3469 sitd = nsitd; 3470 iso->next = iso->next + ncur; 3471 bp0 = OHCI_PAGE(buf + offs); 3472 ncur = 0; 3473 } 3474 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3475 offs = noffs; 3476 } 3477 mutex_enter(&sc->sc_lock); 3478 nsitd = ohci_alloc_sitd(sc); 3479 mutex_exit(&sc->sc_lock); 3480 if (nsitd == NULL) { 3481 /* XXX what now? */ 3482 printf("%s: isoc TD alloc failed\n", 3483 device_xname(sc->sc_dev)); 3484 return; 3485 } 3486 /* Fixup last used ITD */ 3487 sitd->itd.itd_flags = HTOO32( 3488 OHCI_ITD_NOCC | 3489 OHCI_ITD_SET_SF(iso->next) | 3490 OHCI_ITD_SET_DI(0) | 3491 OHCI_ITD_SET_FC(ncur)); 3492 sitd->itd.itd_bp0 = HTOO32(bp0); 3493 sitd->nextitd = nsitd; 3494 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3495 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3496 sitd->xfer = xfer; 3497 sitd->flags = OHCI_CALL_DONE; 3498 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3500 3501 iso->next = iso->next + ncur; 3502 iso->inuse += nframes; 3503 3504 xfer->actlen = offs; /* XXX pretend we did it all */ 3505 3506 xfer->status = USBD_IN_PROGRESS; 3507 3508 #ifdef OHCI_DEBUG 3509 if (ohcidebug > 5) { 3510 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3511 O32TOH(sc->sc_hcca->hcca_frame_number))); 3512 ohci_dump_itds(sc, xfer->hcpriv); 3513 ohci_dump_ed(sc, sed); 3514 } 3515 #endif 3516 3517 mutex_enter(&sc->sc_lock); 3518 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3519 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3520 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3521 opipe->tail.itd = nsitd; 3522 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3523 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3524 sizeof(sed->ed.ed_flags), 3525 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3526 mutex_exit(&sc->sc_lock); 3527 3528 #ifdef OHCI_DEBUG 3529 if (ohcidebug > 5) { 3530 delay(150000); 3531 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3532 O32TOH(sc->sc_hcca->hcca_frame_number))); 3533 ohci_dump_itds(sc, xfer->hcpriv); 3534 ohci_dump_ed(sc, sed); 3535 } 3536 #endif 3537 } 3538 3539 usbd_status 3540 ohci_device_isoc_start(usbd_xfer_handle xfer) 3541 { 3542 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3543 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3544 3545 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3546 3547 mutex_enter(&sc->sc_lock); 3548 3549 if (sc->sc_dying) { 3550 mutex_exit(&sc->sc_lock); 3551 return (USBD_IOERROR); 3552 } 3553 3554 #ifdef DIAGNOSTIC 3555 if (xfer->status != USBD_IN_PROGRESS) 3556 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3557 #endif 3558 3559 /* XXX anything to do? */ 3560 3561 mutex_exit(&sc->sc_lock); 3562 3563 return (USBD_IN_PROGRESS); 3564 } 3565 3566 void 3567 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3568 { 3569 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3570 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3571 ohci_soft_ed_t *sed; 3572 ohci_soft_itd_t *sitd; 3573 3574 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3575 3576 KASSERT(mutex_owned(&sc->sc_lock)); 3577 3578 /* Transfer is already done. */ 3579 if (xfer->status != USBD_NOT_STARTED && 3580 xfer->status != USBD_IN_PROGRESS) { 3581 printf("ohci_device_isoc_abort: early return\n"); 3582 goto done; 3583 } 3584 3585 /* Give xfer the requested abort code. */ 3586 xfer->status = USBD_CANCELLED; 3587 3588 sed = opipe->sed; 3589 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3590 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3591 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3592 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3593 sizeof(sed->ed.ed_flags), 3594 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3595 3596 sitd = xfer->hcpriv; 3597 #ifdef DIAGNOSTIC 3598 if (sitd == NULL) { 3599 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3600 goto done; 3601 } 3602 #endif 3603 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3604 #ifdef DIAGNOSTIC 3605 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3606 sitd->isdone = 1; 3607 #endif 3608 } 3609 3610 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3611 3612 /* Run callback. */ 3613 usb_transfer_complete(xfer); 3614 3615 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3616 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3617 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3618 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3619 3620 done: 3621 KASSERT(mutex_owned(&sc->sc_lock)); 3622 } 3623 3624 void 3625 ohci_device_isoc_done(usbd_xfer_handle xfer) 3626 { 3627 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3628 } 3629 3630 usbd_status 3631 ohci_setup_isoc(usbd_pipe_handle pipe) 3632 { 3633 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3634 ohci_softc_t *sc = pipe->device->bus->hci_private; 3635 struct iso *iso = &opipe->u.iso; 3636 3637 iso->next = -1; 3638 iso->inuse = 0; 3639 3640 mutex_enter(&sc->sc_lock); 3641 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3642 mutex_exit(&sc->sc_lock); 3643 3644 return (USBD_NORMAL_COMPLETION); 3645 } 3646 3647 void 3648 ohci_device_isoc_close(usbd_pipe_handle pipe) 3649 { 3650 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3651 ohci_softc_t *sc = pipe->device->bus->hci_private; 3652 3653 KASSERT(mutex_owned(&sc->sc_lock)); 3654 3655 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3656 ohci_close_pipe(pipe, sc->sc_isoc_head); 3657 #ifdef DIAGNOSTIC 3658 opipe->tail.itd->isdone = 1; 3659 #endif 3660 ohci_free_sitd(sc, opipe->tail.itd); 3661 } 3662
Indexes created Tue Sep 23 07:09:52 GMT 2025