ohci.c revision 1.236
1 /* $NetBSD: ohci.c,v 1.236 2013/04/03 19:02:12 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.236 2013/04/03 19:02:12 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 136 137 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 138 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 139 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 140 Static void ohci_root_ctrl_close(usbd_pipe_handle); 141 Static void ohci_root_ctrl_done(usbd_xfer_handle); 142 143 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 145 Static void ohci_root_intr_abort(usbd_xfer_handle); 146 Static void ohci_root_intr_close(usbd_pipe_handle); 147 Static void ohci_root_intr_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 151 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 152 Static void ohci_device_ctrl_close(usbd_pipe_handle); 153 Static void ohci_device_ctrl_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 157 Static void ohci_device_bulk_abort(usbd_xfer_handle); 158 Static void ohci_device_bulk_close(usbd_pipe_handle); 159 Static void ohci_device_bulk_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 163 Static void ohci_device_intr_abort(usbd_xfer_handle); 164 Static void ohci_device_intr_close(usbd_pipe_handle); 165 Static void ohci_device_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 169 Static void ohci_device_isoc_abort(usbd_xfer_handle); 170 Static void ohci_device_isoc_close(usbd_pipe_handle); 171 Static void ohci_device_isoc_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 174 struct ohci_pipe *pipe, int ival); 175 176 Static void ohci_timeout(void *); 177 Static void ohci_timeout_task(void *); 178 Static void ohci_rhsc_enable(void *); 179 180 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 181 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 182 183 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ohci_noop(usbd_pipe_handle pipe); 185 186 #ifdef OHCI_DEBUG 187 Static void ohci_dumpregs(ohci_softc_t *); 188 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 191 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 192 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 193 #endif 194 195 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 196 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 197 #define OWRITE1(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OWRITE2(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE4(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 static __inline uint8_t 204 OREAD1(ohci_softc_t *sc, bus_size_t r) 205 { 206 207 OBARR(sc); 208 return bus_space_read_1(sc->iot, sc->ioh, r); 209 } 210 211 static __inline uint16_t 212 OREAD2(ohci_softc_t *sc, bus_size_t r) 213 { 214 215 OBARR(sc); 216 return bus_space_read_2(sc->iot, sc->ioh, r); 217 } 218 219 static __inline uint32_t 220 OREAD4(ohci_softc_t *sc, bus_size_t r) 221 { 222 223 OBARR(sc); 224 return bus_space_read_4(sc->iot, sc->ioh, r); 225 } 226 227 /* Reverse the bits in a value 0 .. 31 */ 228 Static u_int8_t revbits[OHCI_NO_INTRS] = 229 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 230 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 231 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 232 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 233 234 struct ohci_pipe { 235 struct usbd_pipe pipe; 236 ohci_soft_ed_t *sed; 237 union { 238 ohci_soft_td_t *td; 239 ohci_soft_itd_t *itd; 240 } tail; 241 /* Info needed for different pipe kinds. */ 242 union { 243 /* Control pipe */ 244 struct { 245 usb_dma_t reqdma; 246 u_int length; 247 ohci_soft_td_t *setup, *data, *stat; 248 } ctl; 249 /* Interrupt pipe */ 250 struct { 251 int nslots; 252 int pos; 253 } intr; 254 /* Bulk pipe */ 255 struct { 256 u_int length; 257 int isread; 258 } bulk; 259 /* Iso pipe */ 260 struct iso { 261 int next, inuse; 262 } iso; 263 } u; 264 }; 265 266 #define OHCI_INTR_ENDPT 1 267 268 Static const struct usbd_bus_methods ohci_bus_methods = { 269 .open_pipe = ohci_open, 270 .soft_intr = ohci_softintr, 271 .do_poll = ohci_poll, 272 .allocm = ohci_allocm, 273 .freem = ohci_freem, 274 .allocx = ohci_allocx, 275 .freex = ohci_freex, 276 .get_lock = ohci_get_lock, 277 }; 278 279 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 280 .transfer = ohci_root_ctrl_transfer, 281 .start = ohci_root_ctrl_start, 282 .abort = ohci_root_ctrl_abort, 283 .close = ohci_root_ctrl_close, 284 .cleartoggle = ohci_noop, 285 .done = ohci_root_ctrl_done, 286 }; 287 288 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 289 .transfer = ohci_root_intr_transfer, 290 .start = ohci_root_intr_start, 291 .abort = ohci_root_intr_abort, 292 .close = ohci_root_intr_close, 293 .cleartoggle = ohci_noop, 294 .done = ohci_root_intr_done, 295 }; 296 297 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 298 .transfer = ohci_device_ctrl_transfer, 299 .start = ohci_device_ctrl_start, 300 .abort = ohci_device_ctrl_abort, 301 .close = ohci_device_ctrl_close, 302 .cleartoggle = ohci_noop, 303 .done = ohci_device_ctrl_done, 304 }; 305 306 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 307 .transfer = ohci_device_intr_transfer, 308 .start = ohci_device_intr_start, 309 .abort = ohci_device_intr_abort, 310 .close = ohci_device_intr_close, 311 .cleartoggle = ohci_device_clear_toggle, 312 .done = ohci_device_intr_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 316 .transfer = ohci_device_bulk_transfer, 317 .start = ohci_device_bulk_start, 318 .abort = ohci_device_bulk_abort, 319 .close = ohci_device_bulk_close, 320 .cleartoggle = ohci_device_clear_toggle, 321 .done = ohci_device_bulk_done, 322 }; 323 324 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 325 .transfer = ohci_device_isoc_transfer, 326 .start = ohci_device_isoc_start, 327 .abort = ohci_device_isoc_abort, 328 .close = ohci_device_isoc_close, 329 .cleartoggle = ohci_noop, 330 .done = ohci_device_isoc_done, 331 }; 332 333 int 334 ohci_activate(device_t self, enum devact act) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 switch (act) { 339 case DVACT_DEACTIVATE: 340 sc->sc_dying = 1; 341 return 0; 342 default: 343 return EOPNOTSUPP; 344 } 345 } 346 347 void 348 ohci_childdet(device_t self, device_t child) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 KASSERT(sc->sc_child == child); 353 sc->sc_child = NULL; 354 } 355 356 int 357 ohci_detach(struct ohci_softc *sc, int flags) 358 { 359 int rv = 0; 360 361 if (sc->sc_child != NULL) 362 rv = config_detach(sc->sc_child, flags); 363 364 if (rv != 0) 365 return (rv); 366 367 callout_stop(&sc->sc_tmo_rhsc); 368 369 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 370 callout_destroy(&sc->sc_tmo_rhsc); 371 372 softint_disestablish(sc->sc_rhsc_si); 373 374 cv_destroy(&sc->sc_softwake_cv); 375 376 mutex_destroy(&sc->sc_lock); 377 mutex_destroy(&sc->sc_intr_lock); 378 379 if (sc->sc_hcca != NULL) 380 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 381 pool_cache_destroy(sc->sc_xferpool); 382 383 return (rv); 384 } 385 386 ohci_soft_ed_t * 387 ohci_alloc_sed(ohci_softc_t *sc) 388 { 389 ohci_soft_ed_t *sed; 390 usbd_status err; 391 int i, offs; 392 usb_dma_t dma; 393 394 if (sc->sc_freeeds == NULL) { 395 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 396 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 397 OHCI_ED_ALIGN, &dma); 398 if (err) 399 return (0); 400 for (i = 0; i < OHCI_SED_CHUNK; i++) { 401 offs = i * OHCI_SED_SIZE; 402 sed = KERNADDR(&dma, offs); 403 sed->physaddr = DMAADDR(&dma, offs); 404 sed->dma = dma; 405 sed->offs = offs; 406 sed->next = sc->sc_freeeds; 407 sc->sc_freeeds = sed; 408 } 409 } 410 sed = sc->sc_freeeds; 411 sc->sc_freeeds = sed->next; 412 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 413 sed->next = 0; 414 return (sed); 415 } 416 417 void 418 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 419 { 420 sed->next = sc->sc_freeeds; 421 sc->sc_freeeds = sed; 422 } 423 424 ohci_soft_td_t * 425 ohci_alloc_std(ohci_softc_t *sc) 426 { 427 ohci_soft_td_t *std; 428 usbd_status err; 429 int i, offs; 430 usb_dma_t dma; 431 432 if (sc->sc_freetds == NULL) { 433 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 434 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 435 OHCI_TD_ALIGN, &dma); 436 if (err) 437 return (NULL); 438 for(i = 0; i < OHCI_STD_CHUNK; i++) { 439 offs = i * OHCI_STD_SIZE; 440 std = KERNADDR(&dma, offs); 441 std->physaddr = DMAADDR(&dma, offs); 442 std->dma = dma; 443 std->offs = offs; 444 std->nexttd = sc->sc_freetds; 445 sc->sc_freetds = std; 446 } 447 } 448 449 std = sc->sc_freetds; 450 sc->sc_freetds = std->nexttd; 451 memset(&std->td, 0, sizeof(ohci_td_t)); 452 std->nexttd = NULL; 453 std->xfer = NULL; 454 ohci_hash_add_td(sc, std); 455 456 return (std); 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 463 ohci_hash_rem_td(sc, std); 464 std->nexttd = sc->sc_freetds; 465 sc->sc_freetds = std; 466 } 467 468 usbd_status 469 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 470 int alen, int rd, usbd_xfer_handle xfer, 471 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 472 { 473 ohci_soft_td_t *next, *cur; 474 ohci_physaddr_t dataphys, dataphysend; 475 u_int32_t tdflags; 476 int len, curlen; 477 usb_dma_t *dma = &xfer->dmabuf; 478 u_int16_t flags = xfer->flags; 479 480 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 481 482 KASSERT(mutex_owned(&sc->sc_lock)); 483 484 len = alen; 485 cur = sp; 486 dataphys = DMAADDR(dma, 0); 487 dataphysend = OHCI_PAGE(dataphys + len - 1); 488 usb_syncmem(dma, 0, len, 489 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 490 tdflags = HTOO32( 491 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 492 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 493 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 494 495 for (;;) { 496 next = ohci_alloc_std(sc); 497 if (next == NULL) 498 goto nomem; 499 500 /* The OHCI hardware can handle at most one page crossing. */ 501 if (OHCI_PAGE(dataphys) == dataphysend || 502 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 503 /* we can handle it in this TD */ 504 curlen = len; 505 } else { 506 /* must use multiple TDs, fill as much as possible. */ 507 curlen = 2 * OHCI_PAGE_SIZE - 508 (dataphys & (OHCI_PAGE_SIZE-1)); 509 /* the length must be a multiple of the max size */ 510 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 511 #ifdef DIAGNOSTIC 512 if (curlen == 0) 513 panic("ohci_alloc_std: curlen == 0"); 514 #endif 515 } 516 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 517 "dataphysend=0x%08x len=%d curlen=%d\n", 518 dataphys, dataphysend, 519 len, curlen)); 520 len -= curlen; 521 522 cur->td.td_flags = tdflags; 523 cur->td.td_cbp = HTOO32(dataphys); 524 cur->nexttd = next; 525 cur->td.td_nexttd = HTOO32(next->physaddr); 526 cur->td.td_be = HTOO32(dataphys + curlen - 1); 527 cur->len = curlen; 528 cur->flags = OHCI_ADD_LEN; 529 cur->xfer = xfer; 530 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 533 dataphys, dataphys + curlen - 1)); 534 if (len == 0) 535 break; 536 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 537 dataphys += curlen; 538 cur = next; 539 } 540 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 541 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 542 /* Force a 0 length transfer at the end. */ 543 544 cur = next; 545 next = ohci_alloc_std(sc); 546 if (next == NULL) 547 goto nomem; 548 549 cur->td.td_flags = tdflags; 550 cur->td.td_cbp = 0; /* indicate 0 length packet */ 551 cur->nexttd = next; 552 cur->td.td_nexttd = HTOO32(next->physaddr); 553 cur->td.td_be = ~0; 554 cur->len = 0; 555 cur->flags = 0; 556 cur->xfer = xfer; 557 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 560 } 561 *ep = cur; 562 563 return (USBD_NORMAL_COMPLETION); 564 565 nomem: 566 567 /* Don't free sp - let the caller do that */ 568 ohci_free_std_chain(sc, sp->nexttd, NULL); 569 570 return (USBD_NOMEM); 571 } 572 573 Static void 574 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 575 ohci_soft_td_t *stdend) 576 { 577 ohci_soft_td_t *p; 578 579 for (; std != stdend; std = p) { 580 p = std->nexttd; 581 ohci_free_std(sc, std); 582 } 583 } 584 585 ohci_soft_itd_t * 586 ohci_alloc_sitd(ohci_softc_t *sc) 587 { 588 ohci_soft_itd_t *sitd; 589 usbd_status err; 590 int i, offs; 591 usb_dma_t dma; 592 593 if (sc->sc_freeitds == NULL) { 594 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 595 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 596 OHCI_ITD_ALIGN, &dma); 597 if (err) 598 return (NULL); 599 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 600 offs = i * OHCI_SITD_SIZE; 601 sitd = KERNADDR(&dma, offs); 602 sitd->physaddr = DMAADDR(&dma, offs); 603 sitd->dma = dma; 604 sitd->offs = offs; 605 sitd->nextitd = sc->sc_freeitds; 606 sc->sc_freeitds = sitd; 607 } 608 } 609 610 sitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd->nextitd; 612 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 613 sitd->nextitd = NULL; 614 sitd->xfer = NULL; 615 ohci_hash_add_itd(sc, sitd); 616 617 #ifdef DIAGNOSTIC 618 sitd->isdone = 0; 619 #endif 620 621 return (sitd); 622 } 623 624 void 625 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 626 { 627 628 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 629 630 #ifdef DIAGNOSTIC 631 if (!sitd->isdone) { 632 panic("ohci_free_sitd: sitd=%p not done", sitd); 633 return; 634 } 635 /* Warn double free */ 636 sitd->isdone = 0; 637 #endif 638 639 ohci_hash_rem_itd(sc, sitd); 640 sitd->nextitd = sc->sc_freeitds; 641 sc->sc_freeitds = sitd; 642 } 643 644 usbd_status 645 ohci_init(ohci_softc_t *sc) 646 { 647 ohci_soft_ed_t *sed, *psed; 648 usbd_status err; 649 int i; 650 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 651 652 DPRINTF(("ohci_init: start\n")); 653 aprint_normal_dev(sc->sc_dev, ""); 654 655 sc->sc_hcca = NULL; 656 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 657 658 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 659 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 660 cv_init(&sc->sc_softwake_cv, "ohciab"); 661 662 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 663 ohci_rhsc_softint, sc); 664 665 for (i = 0; i < OHCI_HASH_SIZE; i++) 666 LIST_INIT(&sc->sc_hash_tds[i]); 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_itds[i]); 669 670 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 671 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 672 673 rev = OREAD4(sc, OHCI_REVISION); 674 aprint_normal("OHCI version %d.%d%s\n", 675 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 676 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 677 678 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 679 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 680 sc->sc_bus.usbrev = USBREV_UNKNOWN; 681 return (USBD_INVAL); 682 } 683 sc->sc_bus.usbrev = USBREV_1_0; 684 685 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 686 USB_MEM_RESERVE); 687 688 /* XXX determine alignment by R/W */ 689 /* Allocate the HCCA area. */ 690 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 691 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 692 if (err) { 693 sc->sc_hcca = NULL; 694 return err; 695 } 696 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 697 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 698 699 sc->sc_eintrs = OHCI_NORMAL_INTRS; 700 701 /* Allocate dummy ED that starts the control list. */ 702 sc->sc_ctrl_head = ohci_alloc_sed(sc); 703 if (sc->sc_ctrl_head == NULL) { 704 err = USBD_NOMEM; 705 goto bad1; 706 } 707 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 708 709 /* Allocate dummy ED that starts the bulk list. */ 710 sc->sc_bulk_head = ohci_alloc_sed(sc); 711 if (sc->sc_bulk_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad2; 714 } 715 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 717 sizeof(sc->sc_bulk_head->ed), 718 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 719 720 /* Allocate dummy ED that starts the isochronous list. */ 721 sc->sc_isoc_head = ohci_alloc_sed(sc); 722 if (sc->sc_isoc_head == NULL) { 723 err = USBD_NOMEM; 724 goto bad3; 725 } 726 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 727 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 728 sizeof(sc->sc_isoc_head->ed), 729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 730 731 /* Allocate all the dummy EDs that make up the interrupt tree. */ 732 for (i = 0; i < OHCI_NO_EDS; i++) { 733 sed = ohci_alloc_sed(sc); 734 if (sed == NULL) { 735 while (--i >= 0) 736 ohci_free_sed(sc, sc->sc_eds[i]); 737 err = USBD_NOMEM; 738 goto bad4; 739 } 740 /* All ED fields are set to 0. */ 741 sc->sc_eds[i] = sed; 742 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 743 if (i != 0) 744 psed = sc->sc_eds[(i-1) / 2]; 745 else 746 psed= sc->sc_isoc_head; 747 sed->next = psed; 748 sed->ed.ed_nexted = HTOO32(psed->physaddr); 749 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 751 } 752 /* 753 * Fill HCCA interrupt table. The bit reversal is to get 754 * the tree set up properly to spread the interrupts. 755 */ 756 for (i = 0; i < OHCI_NO_INTRS; i++) 757 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 758 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 759 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 761 762 #ifdef OHCI_DEBUG 763 if (ohcidebug > 15) { 764 for (i = 0; i < OHCI_NO_EDS; i++) { 765 printf("ed#%d ", i); 766 ohci_dump_ed(sc, sc->sc_eds[i]); 767 } 768 printf("iso "); 769 ohci_dump_ed(sc, sc->sc_isoc_head); 770 } 771 #endif 772 773 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 774 ctl = OREAD4(sc, OHCI_CONTROL); 775 rwc = ctl & OHCI_RWC; 776 fm = OREAD4(sc, OHCI_FM_INTERVAL); 777 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 778 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 779 780 /* Determine in what context we are running. */ 781 if (ctl & OHCI_IR) { 782 /* SMM active, request change */ 783 DPRINTF(("ohci_init: SMM active, request owner change\n")); 784 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 785 (OHCI_OC | OHCI_MIE)) 786 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 787 s = OREAD4(sc, OHCI_COMMAND_STATUS); 788 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 789 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 790 usb_delay_ms(&sc->sc_bus, 1); 791 ctl = OREAD4(sc, OHCI_CONTROL); 792 } 793 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 794 if ((ctl & OHCI_IR) == 0) { 795 aprint_error_dev(sc->sc_dev, 796 "SMM does not respond, resetting\n"); 797 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 798 goto reset; 799 } 800 #if 0 801 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 802 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 803 /* BIOS started controller. */ 804 DPRINTF(("ohci_init: BIOS active\n")); 805 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 806 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 807 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 808 } 809 #endif 810 } else { 811 DPRINTF(("ohci_init: cold started\n")); 812 reset: 813 /* Controller was cold started. */ 814 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 815 } 816 817 /* 818 * This reset should not be necessary according to the OHCI spec, but 819 * without it some controllers do not start. 820 */ 821 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 822 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 823 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 824 825 /* We now own the host controller and the bus has been reset. */ 826 827 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 828 /* Nominal time for a reset is 10 us. */ 829 for (i = 0; i < 10; i++) { 830 delay(10); 831 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 832 if (!hcr) 833 break; 834 } 835 if (hcr) { 836 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 837 err = USBD_IOERROR; 838 goto bad5; 839 } 840 #ifdef OHCI_DEBUG 841 if (ohcidebug > 15) 842 ohci_dumpregs(sc); 843 #endif 844 845 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 846 847 /* Set up HC registers. */ 848 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 849 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 850 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 851 /* disable all interrupts and then switch on all desired interrupts */ 852 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 853 /* switch on desired functional features */ 854 ctl = OREAD4(sc, OHCI_CONTROL); 855 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 856 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 857 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 858 /* And finally start it! */ 859 OWRITE4(sc, OHCI_CONTROL, ctl); 860 861 /* 862 * The controller is now OPERATIONAL. Set a some final 863 * registers that should be set earlier, but that the 864 * controller ignores when in the SUSPEND state. 865 */ 866 ival = OHCI_GET_IVAL(fm); 867 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 868 fm |= OHCI_FSMPS(ival) | ival; 869 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 870 per = OHCI_PERIODIC(ival); /* 90% periodic */ 871 OWRITE4(sc, OHCI_PERIODIC_START, per); 872 873 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 874 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 875 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 876 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 877 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 878 879 /* 880 * The AMD756 requires a delay before re-reading the register, 881 * otherwise it will occasionally report 0 ports. 882 */ 883 sc->sc_noport = 0; 884 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 885 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 886 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 887 } 888 889 #ifdef OHCI_DEBUG 890 if (ohcidebug > 5) 891 ohci_dumpregs(sc); 892 #endif 893 894 /* Set up the bus struct. */ 895 sc->sc_bus.methods = &ohci_bus_methods; 896 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 897 898 sc->sc_control = sc->sc_intre = 0; 899 900 /* Finally, turn on interrupts. */ 901 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 902 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 903 904 return (USBD_NORMAL_COMPLETION); 905 906 bad5: 907 for (i = 0; i < OHCI_NO_EDS; i++) 908 ohci_free_sed(sc, sc->sc_eds[i]); 909 bad4: 910 ohci_free_sed(sc, sc->sc_isoc_head); 911 bad3: 912 ohci_free_sed(sc, sc->sc_bulk_head); 913 bad2: 914 ohci_free_sed(sc, sc->sc_ctrl_head); 915 bad1: 916 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 917 sc->sc_hcca = NULL; 918 return (err); 919 } 920 921 usbd_status 922 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 923 { 924 struct ohci_softc *sc = bus->hci_private; 925 usbd_status status; 926 927 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 928 if (status == USBD_NOMEM) 929 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 930 return status; 931 } 932 933 void 934 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 935 { 936 struct ohci_softc *sc = bus->hci_private; 937 if (dma->block->flags & USB_DMA_RESERVE) { 938 usb_reserve_freem(&sc->sc_dma_reserve, dma); 939 return; 940 } 941 usb_freemem(&sc->sc_bus, dma); 942 } 943 944 usbd_xfer_handle 945 ohci_allocx(struct usbd_bus *bus) 946 { 947 struct ohci_softc *sc = bus->hci_private; 948 usbd_xfer_handle xfer; 949 950 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 951 if (xfer != NULL) { 952 memset(xfer, 0, sizeof(struct ohci_xfer)); 953 #ifdef DIAGNOSTIC 954 xfer->busy_free = XFER_BUSY; 955 #endif 956 } 957 return (xfer); 958 } 959 960 void 961 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 962 { 963 struct ohci_softc *sc = bus->hci_private; 964 965 #ifdef DIAGNOSTIC 966 if (xfer->busy_free != XFER_BUSY) { 967 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 968 xfer->busy_free); 969 } 970 xfer->busy_free = XFER_FREE; 971 #endif 972 pool_cache_put(sc->sc_xferpool, xfer); 973 } 974 975 Static void 976 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 977 { 978 struct ohci_softc *sc = bus->hci_private; 979 980 *lock = &sc->sc_lock; 981 } 982 983 /* 984 * Shut down the controller when the system is going down. 985 */ 986 bool 987 ohci_shutdown(device_t self, int flags) 988 { 989 ohci_softc_t *sc = device_private(self); 990 991 DPRINTF(("ohci_shutdown: stopping the HC\n")); 992 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 993 return true; 994 } 995 996 bool 997 ohci_resume(device_t dv, const pmf_qual_t *qual) 998 { 999 ohci_softc_t *sc = device_private(dv); 1000 uint32_t ctl; 1001 1002 mutex_spin_enter(&sc->sc_intr_lock); 1003 sc->sc_bus.use_polling++; 1004 mutex_spin_exit(&sc->sc_intr_lock); 1005 1006 /* Some broken BIOSes do not recover these values */ 1007 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1008 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1009 sc->sc_ctrl_head->physaddr); 1010 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1011 sc->sc_bulk_head->physaddr); 1012 if (sc->sc_intre) 1013 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1014 (OHCI_ALL_INTRS | OHCI_MIE)); 1015 if (sc->sc_control) 1016 ctl = sc->sc_control; 1017 else 1018 ctl = OREAD4(sc, OHCI_CONTROL); 1019 ctl |= OHCI_HCFS_RESUME; 1020 OWRITE4(sc, OHCI_CONTROL, ctl); 1021 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1022 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1025 sc->sc_control = sc->sc_intre = 0; 1026 1027 mutex_spin_enter(&sc->sc_intr_lock); 1028 sc->sc_bus.use_polling--; 1029 mutex_spin_exit(&sc->sc_intr_lock); 1030 1031 return true; 1032 } 1033 1034 bool 1035 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1036 { 1037 ohci_softc_t *sc = device_private(dv); 1038 uint32_t ctl; 1039 1040 mutex_spin_enter(&sc->sc_intr_lock); 1041 sc->sc_bus.use_polling++; 1042 mutex_spin_exit(&sc->sc_intr_lock); 1043 1044 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1045 if (sc->sc_control == 0) { 1046 /* 1047 * Preserve register values, in case that BIOS 1048 * does not recover them. 1049 */ 1050 sc->sc_control = ctl; 1051 sc->sc_intre = OREAD4(sc, 1052 OHCI_INTERRUPT_ENABLE); 1053 } 1054 ctl |= OHCI_HCFS_SUSPEND; 1055 OWRITE4(sc, OHCI_CONTROL, ctl); 1056 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1057 1058 mutex_spin_enter(&sc->sc_intr_lock); 1059 sc->sc_bus.use_polling--; 1060 mutex_spin_exit(&sc->sc_intr_lock); 1061 1062 return true; 1063 } 1064 1065 #ifdef OHCI_DEBUG 1066 void 1067 ohci_dumpregs(ohci_softc_t *sc) 1068 { 1069 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1070 OREAD4(sc, OHCI_REVISION), 1071 OREAD4(sc, OHCI_CONTROL), 1072 OREAD4(sc, OHCI_COMMAND_STATUS))); 1073 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1074 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1075 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1076 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1077 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1078 OREAD4(sc, OHCI_HCCA), 1079 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1080 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1081 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1082 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1083 OREAD4(sc, OHCI_BULK_HEAD_ED), 1084 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1085 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1086 OREAD4(sc, OHCI_DONE_HEAD), 1087 OREAD4(sc, OHCI_FM_INTERVAL), 1088 OREAD4(sc, OHCI_FM_REMAINING))); 1089 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1090 OREAD4(sc, OHCI_FM_NUMBER), 1091 OREAD4(sc, OHCI_PERIODIC_START), 1092 OREAD4(sc, OHCI_LS_THRESHOLD))); 1093 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1094 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1095 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1096 OREAD4(sc, OHCI_RH_STATUS))); 1097 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1098 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1099 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1100 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1101 O32TOH(sc->sc_hcca->hcca_frame_number), 1102 O32TOH(sc->sc_hcca->hcca_done_head))); 1103 } 1104 #endif 1105 1106 Static int ohci_intr1(ohci_softc_t *); 1107 1108 int 1109 ohci_intr(void *p) 1110 { 1111 ohci_softc_t *sc = p; 1112 int ret = 0; 1113 1114 if (sc == NULL) 1115 return (0); 1116 1117 mutex_spin_enter(&sc->sc_intr_lock); 1118 1119 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1120 goto done; 1121 1122 /* If we get an interrupt while polling, then just ignore it. */ 1123 if (sc->sc_bus.use_polling) { 1124 #ifdef DIAGNOSTIC 1125 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1126 #endif 1127 /* for level triggered intrs, should do something to ack */ 1128 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1129 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1130 1131 goto done; 1132 } 1133 1134 ret = ohci_intr1(sc); 1135 1136 done: 1137 mutex_spin_exit(&sc->sc_intr_lock); 1138 return ret; 1139 } 1140 1141 Static int 1142 ohci_intr1(ohci_softc_t *sc) 1143 { 1144 u_int32_t intrs, eintrs; 1145 1146 DPRINTFN(14,("ohci_intr1: enter\n")); 1147 1148 /* In case the interrupt occurs before initialization has completed. */ 1149 if (sc == NULL || sc->sc_hcca == NULL) { 1150 #ifdef DIAGNOSTIC 1151 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1152 #endif 1153 return (0); 1154 } 1155 1156 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1157 1158 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1159 if (!intrs) 1160 return (0); 1161 1162 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1163 eintrs = intrs & sc->sc_eintrs; 1164 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1165 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1166 (u_int)eintrs, sc->sc_eintrs)); 1167 1168 if (!eintrs) { 1169 return (0); 1170 } 1171 1172 sc->sc_bus.no_intrs++; 1173 if (eintrs & OHCI_SO) { 1174 sc->sc_overrun_cnt++; 1175 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1176 printf("%s: %u scheduling overruns\n", 1177 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1178 sc->sc_overrun_cnt = 0; 1179 } 1180 /* XXX do what */ 1181 eintrs &= ~OHCI_SO; 1182 } 1183 if (eintrs & OHCI_WDH) { 1184 /* 1185 * We block the interrupt below, and reenable it later from 1186 * ohci_softintr(). 1187 */ 1188 usb_schedsoftintr(&sc->sc_bus); 1189 } 1190 if (eintrs & OHCI_RD) { 1191 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1192 /* XXX process resume detect */ 1193 } 1194 if (eintrs & OHCI_UE) { 1195 printf("%s: unrecoverable error, controller halted\n", 1196 device_xname(sc->sc_dev)); 1197 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1198 /* XXX what else */ 1199 } 1200 if (eintrs & OHCI_RHSC) { 1201 /* 1202 * We block the interrupt below, and reenable it later from 1203 * a timeout. 1204 */ 1205 softint_schedule(sc->sc_rhsc_si); 1206 } 1207 1208 if (eintrs != 0) { 1209 /* Block unprocessed interrupts. */ 1210 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1211 sc->sc_eintrs &= ~eintrs; 1212 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1213 device_xname(sc->sc_dev), eintrs)); 1214 } 1215 1216 return (1); 1217 } 1218 1219 void 1220 ohci_rhsc_enable(void *v_sc) 1221 { 1222 ohci_softc_t *sc = v_sc; 1223 1224 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 sc->sc_eintrs |= OHCI_RHSC; 1227 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1228 mutex_spin_exit(&sc->sc_intr_lock); 1229 } 1230 1231 #ifdef OHCI_DEBUG 1232 const char *ohci_cc_strs[] = { 1233 "NO_ERROR", 1234 "CRC", 1235 "BIT_STUFFING", 1236 "DATA_TOGGLE_MISMATCH", 1237 "STALL", 1238 "DEVICE_NOT_RESPONDING", 1239 "PID_CHECK_FAILURE", 1240 "UNEXPECTED_PID", 1241 "DATA_OVERRUN", 1242 "DATA_UNDERRUN", 1243 "BUFFER_OVERRUN", 1244 "BUFFER_UNDERRUN", 1245 "reserved", 1246 "reserved", 1247 "NOT_ACCESSED", 1248 "NOT_ACCESSED", 1249 }; 1250 #endif 1251 1252 void 1253 ohci_softintr(void *v) 1254 { 1255 struct usbd_bus *bus = v; 1256 ohci_softc_t *sc = bus->hci_private; 1257 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1258 ohci_soft_td_t *std, *sdone, *stdnext; 1259 usbd_xfer_handle xfer; 1260 struct ohci_pipe *opipe; 1261 int len, cc; 1262 int i, j, actlen, iframes, uedir; 1263 ohci_physaddr_t done; 1264 1265 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1266 1267 DPRINTFN(10,("ohci_softintr: enter\n")); 1268 1269 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1270 sizeof(sc->sc_hcca->hcca_done_head), 1271 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1272 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1273 sc->sc_hcca->hcca_done_head = 0; 1274 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1275 sizeof(sc->sc_hcca->hcca_done_head), 1276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1277 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1278 sc->sc_eintrs |= OHCI_WDH; 1279 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1280 1281 /* Reverse the done list. */ 1282 for (sdone = NULL, sidone = NULL; done != 0; ) { 1283 std = ohci_hash_find_td(sc, done); 1284 if (std != NULL) { 1285 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1286 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1287 std->dnext = sdone; 1288 done = O32TOH(std->td.td_nexttd); 1289 sdone = std; 1290 DPRINTFN(10,("add TD %p\n", std)); 1291 continue; 1292 } 1293 sitd = ohci_hash_find_itd(sc, done); 1294 if (sitd != NULL) { 1295 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1296 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1297 sitd->dnext = sidone; 1298 done = O32TOH(sitd->itd.itd_nextitd); 1299 sidone = sitd; 1300 DPRINTFN(5,("add ITD %p\n", sitd)); 1301 continue; 1302 } 1303 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1304 (u_long)done); 1305 break; 1306 } 1307 1308 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1309 1310 #ifdef OHCI_DEBUG 1311 if (ohcidebug > 10) { 1312 DPRINTF(("ohci_process_done: TD done:\n")); 1313 for (std = sdone; std; std = std->dnext) 1314 ohci_dump_td(sc, std); 1315 } 1316 #endif 1317 1318 for (std = sdone; std; std = stdnext) { 1319 xfer = std->xfer; 1320 stdnext = std->dnext; 1321 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1322 std, xfer, xfer ? xfer->hcpriv : 0)); 1323 if (xfer == NULL) { 1324 /* 1325 * xfer == NULL: There seems to be no xfer associated 1326 * with this TD. It is tailp that happened to end up on 1327 * the done queue. 1328 * Shouldn't happen, but some chips are broken(?). 1329 */ 1330 continue; 1331 } 1332 if (xfer->status == USBD_CANCELLED || 1333 xfer->status == USBD_TIMEOUT) { 1334 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1335 xfer)); 1336 /* Handled by abort routine. */ 1337 continue; 1338 } 1339 callout_stop(&xfer->timeout_handle); 1340 1341 len = std->len; 1342 if (std->td.td_cbp != 0) 1343 len -= O32TOH(std->td.td_be) - 1344 O32TOH(std->td.td_cbp) + 1; 1345 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1346 std->flags)); 1347 if (std->flags & OHCI_ADD_LEN) 1348 xfer->actlen += len; 1349 1350 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1351 if (cc == OHCI_CC_NO_ERROR) { 1352 if (std->flags & OHCI_CALL_DONE) { 1353 xfer->status = USBD_NORMAL_COMPLETION; 1354 usb_transfer_complete(xfer); 1355 } 1356 ohci_free_std(sc, std); 1357 } else { 1358 /* 1359 * Endpoint is halted. First unlink all the TDs 1360 * belonging to the failed transfer, and then restart 1361 * the endpoint. 1362 */ 1363 ohci_soft_td_t *p, *n; 1364 opipe = (struct ohci_pipe *)xfer->pipe; 1365 1366 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1367 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1368 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1369 1370 /* remove TDs */ 1371 for (p = std; p->xfer == xfer; p = n) { 1372 n = p->nexttd; 1373 ohci_free_std(sc, p); 1374 } 1375 1376 /* clear halt */ 1377 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1378 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1379 1380 if (cc == OHCI_CC_STALL) 1381 xfer->status = USBD_STALLED; 1382 else 1383 xfer->status = USBD_IOERROR; 1384 usb_transfer_complete(xfer); 1385 } 1386 } 1387 1388 #ifdef OHCI_DEBUG 1389 if (ohcidebug > 10) { 1390 DPRINTF(("ohci_softintr: ITD done:\n")); 1391 for (sitd = sidone; sitd; sitd = sitd->dnext) 1392 ohci_dump_itd(sc, sitd); 1393 } 1394 #endif 1395 1396 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1397 xfer = sitd->xfer; 1398 sitdnext = sitd->dnext; 1399 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1400 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1401 if (xfer == NULL) 1402 continue; 1403 if (xfer->status == USBD_CANCELLED || 1404 xfer->status == USBD_TIMEOUT) { 1405 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1406 xfer)); 1407 /* Handled by abort routine. */ 1408 continue; 1409 } 1410 #ifdef DIAGNOSTIC 1411 if (sitd->isdone) 1412 printf("ohci_softintr: sitd=%p is done\n", sitd); 1413 sitd->isdone = 1; 1414 #endif 1415 if (sitd->flags & OHCI_CALL_DONE) { 1416 ohci_soft_itd_t *next; 1417 1418 opipe = (struct ohci_pipe *)xfer->pipe; 1419 opipe->u.iso.inuse -= xfer->nframes; 1420 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1421 bEndpointAddress); 1422 xfer->status = USBD_NORMAL_COMPLETION; 1423 actlen = 0; 1424 for (i = 0, sitd = xfer->hcpriv;; 1425 sitd = next) { 1426 next = sitd->nextitd; 1427 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1428 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1429 xfer->status = USBD_IOERROR; 1430 /* For input, update frlengths with actual */ 1431 /* XXX anything necessary for output? */ 1432 if (uedir == UE_DIR_IN && 1433 xfer->status == USBD_NORMAL_COMPLETION) { 1434 iframes = OHCI_ITD_GET_FC(O32TOH( 1435 sitd->itd.itd_flags)); 1436 for (j = 0; j < iframes; i++, j++) { 1437 len = O16TOH(sitd-> 1438 itd.itd_offset[j]); 1439 if ((OHCI_ITD_PSW_GET_CC(len) & 1440 OHCI_CC_NOT_ACCESSED_MASK) 1441 == OHCI_CC_NOT_ACCESSED) 1442 len = 0; 1443 else 1444 len = OHCI_ITD_PSW_LENGTH(len); 1445 xfer->frlengths[i] = len; 1446 actlen += len; 1447 } 1448 } 1449 if (sitd->flags & OHCI_CALL_DONE) 1450 break; 1451 ohci_free_sitd(sc, sitd); 1452 } 1453 ohci_free_sitd(sc, sitd); 1454 if (uedir == UE_DIR_IN && 1455 xfer->status == USBD_NORMAL_COMPLETION) 1456 xfer->actlen = actlen; 1457 xfer->hcpriv = NULL; 1458 1459 usb_transfer_complete(xfer); 1460 } 1461 } 1462 1463 if (sc->sc_softwake) { 1464 sc->sc_softwake = 0; 1465 cv_broadcast(&sc->sc_softwake_cv); 1466 } 1467 1468 DPRINTFN(10,("ohci_softintr: done:\n")); 1469 } 1470 1471 void 1472 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1473 { 1474 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1475 #ifdef DIAGNOSTIC 1476 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1477 #endif 1478 int len = UGETW(xfer->request.wLength); 1479 int isread = (xfer->request.bmRequestType & UT_READ); 1480 1481 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1482 1483 KASSERT(mutex_owned(&sc->sc_lock)); 1484 1485 #ifdef DIAGNOSTIC 1486 if (!(xfer->rqflags & URQ_REQUEST)) { 1487 panic("ohci_device_ctrl_done: not a request"); 1488 } 1489 #endif 1490 if (len) 1491 usb_syncmem(&xfer->dmabuf, 0, len, 1492 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1493 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1494 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1495 } 1496 1497 void 1498 ohci_device_intr_done(usbd_xfer_handle xfer) 1499 { 1500 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1501 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1502 ohci_soft_ed_t *sed = opipe->sed; 1503 ohci_soft_td_t *data, *tail; 1504 int isread = 1505 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1506 1507 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1508 xfer, xfer->actlen)); 1509 1510 KASSERT(mutex_owned(&sc->sc_lock)); 1511 1512 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1513 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1514 if (xfer->pipe->repeat) { 1515 data = opipe->tail.td; 1516 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1517 if (tail == NULL) { 1518 xfer->status = USBD_NOMEM; 1519 return; 1520 } 1521 tail->xfer = NULL; 1522 1523 data->td.td_flags = HTOO32( 1524 OHCI_TD_IN | OHCI_TD_NOCC | 1525 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1526 if (xfer->flags & USBD_SHORT_XFER_OK) 1527 data->td.td_flags |= HTOO32(OHCI_TD_R); 1528 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1529 data->nexttd = tail; 1530 data->td.td_nexttd = HTOO32(tail->physaddr); 1531 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1532 xfer->length - 1); 1533 data->len = xfer->length; 1534 data->xfer = xfer; 1535 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1536 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1538 xfer->hcpriv = data; 1539 xfer->actlen = 0; 1540 1541 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1542 usb_syncmem(&sed->dma, 1543 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1544 sizeof(sed->ed.ed_tailp), 1545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1546 opipe->tail.td = tail; 1547 } 1548 } 1549 1550 void 1551 ohci_device_bulk_done(usbd_xfer_handle xfer) 1552 { 1553 #ifdef DIAGNOSTIC 1554 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1555 #endif 1556 int isread = 1557 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1558 1559 KASSERT(mutex_owned(&sc->sc_lock)); 1560 1561 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1562 xfer, xfer->actlen)); 1563 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1564 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1565 } 1566 1567 Static void 1568 ohci_rhsc_softint(void *arg) 1569 { 1570 ohci_softc_t *sc = arg; 1571 1572 mutex_enter(&sc->sc_lock); 1573 1574 ohci_rhsc(sc, sc->sc_intrxfer); 1575 1576 /* Do not allow RHSC interrupts > 1 per second */ 1577 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1578 1579 mutex_exit(&sc->sc_lock); 1580 } 1581 1582 void 1583 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1584 { 1585 usbd_pipe_handle pipe; 1586 u_char *p; 1587 int i, m; 1588 int hstatus; 1589 1590 KASSERT(mutex_owned(&sc->sc_lock)); 1591 1592 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1593 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1594 sc, xfer, hstatus)); 1595 1596 if (xfer == NULL) { 1597 /* Just ignore the change. */ 1598 return; 1599 } 1600 1601 pipe = xfer->pipe; 1602 1603 p = KERNADDR(&xfer->dmabuf, 0); 1604 m = min(sc->sc_noport, xfer->length * 8 - 1); 1605 memset(p, 0, xfer->length); 1606 for (i = 1; i <= m; i++) { 1607 /* Pick out CHANGE bits from the status reg. */ 1608 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1609 p[i/8] |= 1 << (i%8); 1610 } 1611 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1612 xfer->actlen = xfer->length; 1613 xfer->status = USBD_NORMAL_COMPLETION; 1614 1615 usb_transfer_complete(xfer); 1616 } 1617 1618 void 1619 ohci_root_intr_done(usbd_xfer_handle xfer) 1620 { 1621 } 1622 1623 void 1624 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1625 { 1626 } 1627 1628 /* 1629 * Wait here until controller claims to have an interrupt. 1630 * Then call ohci_intr and return. Use timeout to avoid waiting 1631 * too long. 1632 */ 1633 void 1634 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1635 { 1636 int timo; 1637 u_int32_t intrs; 1638 1639 mutex_enter(&sc->sc_lock); 1640 1641 xfer->status = USBD_IN_PROGRESS; 1642 for (timo = xfer->timeout; timo >= 0; timo--) { 1643 usb_delay_ms(&sc->sc_bus, 1); 1644 if (sc->sc_dying) 1645 break; 1646 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1647 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1648 #ifdef OHCI_DEBUG 1649 if (ohcidebug > 15) 1650 ohci_dumpregs(sc); 1651 #endif 1652 if (intrs) { 1653 mutex_spin_enter(&sc->sc_intr_lock); 1654 ohci_intr1(sc); 1655 mutex_spin_exit(&sc->sc_intr_lock); 1656 if (xfer->status != USBD_IN_PROGRESS) 1657 goto done; 1658 } 1659 } 1660 1661 /* Timeout */ 1662 DPRINTF(("ohci_waitintr: timeout\n")); 1663 xfer->status = USBD_TIMEOUT; 1664 usb_transfer_complete(xfer); 1665 1666 /* XXX should free TD */ 1667 1668 done: 1669 mutex_exit(&sc->sc_lock); 1670 } 1671 1672 void 1673 ohci_poll(struct usbd_bus *bus) 1674 { 1675 ohci_softc_t *sc = bus->hci_private; 1676 #ifdef OHCI_DEBUG 1677 static int last; 1678 int new; 1679 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1680 if (new != last) { 1681 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1682 last = new; 1683 } 1684 #endif 1685 1686 sc->sc_eintrs |= OHCI_WDH; 1687 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1688 mutex_spin_enter(&sc->sc_intr_lock); 1689 ohci_intr1(sc); 1690 mutex_spin_exit(&sc->sc_intr_lock); 1691 } 1692 } 1693 1694 usbd_status 1695 ohci_device_request(usbd_xfer_handle xfer) 1696 { 1697 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1698 usb_device_request_t *req = &xfer->request; 1699 usbd_device_handle dev = opipe->pipe.device; 1700 ohci_softc_t *sc = dev->bus->hci_private; 1701 int addr = dev->address; 1702 ohci_soft_td_t *setup, *stat, *next, *tail; 1703 ohci_soft_ed_t *sed; 1704 int isread; 1705 int len; 1706 usbd_status err; 1707 1708 KASSERT(mutex_owned(&sc->sc_lock)); 1709 1710 isread = req->bmRequestType & UT_READ; 1711 len = UGETW(req->wLength); 1712 1713 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1714 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1715 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1716 UGETW(req->wIndex), len, addr, 1717 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1718 1719 setup = opipe->tail.td; 1720 stat = ohci_alloc_std(sc); 1721 if (stat == NULL) { 1722 err = USBD_NOMEM; 1723 goto bad1; 1724 } 1725 tail = ohci_alloc_std(sc); 1726 if (tail == NULL) { 1727 err = USBD_NOMEM; 1728 goto bad2; 1729 } 1730 tail->xfer = NULL; 1731 1732 sed = opipe->sed; 1733 opipe->u.ctl.length = len; 1734 1735 /* Update device address and length since they may have changed 1736 during the setup of the control pipe in usbd_new_device(). */ 1737 /* XXX This only needs to be done once, but it's too early in open. */ 1738 /* XXXX Should not touch ED here! */ 1739 1740 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1741 sizeof(sed->ed.ed_flags), 1742 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1743 sed->ed.ed_flags = HTOO32( 1744 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1745 OHCI_ED_SET_FA(addr) | 1746 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1747 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1748 sizeof(sed->ed.ed_flags), 1749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1750 1751 next = stat; 1752 1753 /* Set up data transaction */ 1754 if (len != 0) { 1755 ohci_soft_td_t *std = stat; 1756 1757 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1758 std, &stat); 1759 if (err) { 1760 /* stat is unchanged if error */ 1761 goto bad3; 1762 } 1763 stat = stat->nexttd; /* point at free TD */ 1764 1765 /* Start toggle at 1 and then use the carried toggle. */ 1766 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1767 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1768 usb_syncmem(&std->dma, 1769 std->offs + offsetof(ohci_td_t, td_flags), 1770 sizeof(std->td.td_flags), 1771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1772 } 1773 1774 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1775 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1776 1777 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1778 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1779 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1780 setup->nexttd = next; 1781 setup->td.td_nexttd = HTOO32(next->physaddr); 1782 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1783 setup->len = 0; 1784 setup->xfer = xfer; 1785 setup->flags = 0; 1786 xfer->hcpriv = setup; 1787 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1788 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1789 1790 stat->td.td_flags = HTOO32( 1791 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1792 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1793 stat->td.td_cbp = 0; 1794 stat->nexttd = tail; 1795 stat->td.td_nexttd = HTOO32(tail->physaddr); 1796 stat->td.td_be = 0; 1797 stat->flags = OHCI_CALL_DONE; 1798 stat->len = 0; 1799 stat->xfer = xfer; 1800 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1801 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1802 1803 #ifdef OHCI_DEBUG 1804 if (ohcidebug > 5) { 1805 DPRINTF(("ohci_device_request:\n")); 1806 ohci_dump_ed(sc, sed); 1807 ohci_dump_tds(sc, setup); 1808 } 1809 #endif 1810 1811 /* Insert ED in schedule */ 1812 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1813 usb_syncmem(&sed->dma, 1814 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1815 sizeof(sed->ed.ed_tailp), 1816 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1817 opipe->tail.td = tail; 1818 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1819 if (xfer->timeout && !sc->sc_bus.use_polling) { 1820 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1821 ohci_timeout, xfer); 1822 } 1823 1824 #ifdef OHCI_DEBUG 1825 if (ohcidebug > 20) { 1826 delay(10000); 1827 DPRINTF(("ohci_device_request: status=%x\n", 1828 OREAD4(sc, OHCI_COMMAND_STATUS))); 1829 ohci_dumpregs(sc); 1830 printf("ctrl head:\n"); 1831 ohci_dump_ed(sc, sc->sc_ctrl_head); 1832 printf("sed:\n"); 1833 ohci_dump_ed(sc, sed); 1834 ohci_dump_tds(sc, setup); 1835 } 1836 #endif 1837 1838 return (USBD_NORMAL_COMPLETION); 1839 1840 bad3: 1841 ohci_free_std(sc, tail); 1842 bad2: 1843 ohci_free_std(sc, stat); 1844 bad1: 1845 return (err); 1846 } 1847 1848 /* 1849 * Add an ED to the schedule. Called with USB lock held. 1850 */ 1851 Static void 1852 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1853 { 1854 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1855 1856 KASSERT(mutex_owned(&sc->sc_lock)); 1857 1858 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1859 sizeof(head->ed.ed_nexted), 1860 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1861 sed->next = head->next; 1862 sed->ed.ed_nexted = head->ed.ed_nexted; 1863 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1864 sizeof(sed->ed.ed_nexted), 1865 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1866 head->next = sed; 1867 head->ed.ed_nexted = HTOO32(sed->physaddr); 1868 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1869 sizeof(head->ed.ed_nexted), 1870 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1871 } 1872 1873 /* 1874 * Remove an ED from the schedule. Called with USB lock held. 1875 */ 1876 Static void 1877 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1878 { 1879 ohci_soft_ed_t *p; 1880 1881 KASSERT(mutex_owned(&sc->sc_lock)); 1882 1883 /* XXX */ 1884 for (p = head; p != NULL && p->next != sed; p = p->next) 1885 ; 1886 if (p == NULL) 1887 panic("ohci_rem_ed: ED not found"); 1888 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1889 sizeof(sed->ed.ed_nexted), 1890 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1891 p->next = sed->next; 1892 p->ed.ed_nexted = sed->ed.ed_nexted; 1893 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1894 sizeof(p->ed.ed_nexted), 1895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1896 } 1897 1898 /* 1899 * When a transfer is completed the TD is added to the done queue by 1900 * the host controller. This queue is the processed by software. 1901 * Unfortunately the queue contains the physical address of the TD 1902 * and we have no simple way to translate this back to a kernel address. 1903 * To make the translation possible (and fast) we use a hash table of 1904 * TDs currently in the schedule. The physical address is used as the 1905 * hash value. 1906 */ 1907 1908 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1909 /* Called with USB lock held. */ 1910 void 1911 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1912 { 1913 int h = HASH(std->physaddr); 1914 1915 KASSERT(mutex_owned(&sc->sc_lock)); 1916 1917 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1918 } 1919 1920 /* Called with USB lock held. */ 1921 void 1922 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1923 { 1924 1925 KASSERT(mutex_owned(&sc->sc_lock)); 1926 1927 LIST_REMOVE(std, hnext); 1928 } 1929 1930 ohci_soft_td_t * 1931 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1932 { 1933 int h = HASH(a); 1934 ohci_soft_td_t *std; 1935 1936 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1937 std != NULL; 1938 std = LIST_NEXT(std, hnext)) 1939 if (std->physaddr == a) 1940 return (std); 1941 return (NULL); 1942 } 1943 1944 /* Called with USB lock held. */ 1945 void 1946 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1947 { 1948 int h = HASH(sitd->physaddr); 1949 1950 KASSERT(mutex_owned(&sc->sc_lock)); 1951 1952 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1953 sitd, (u_long)sitd->physaddr)); 1954 1955 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1956 } 1957 1958 /* Called with USB lock held. */ 1959 void 1960 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1961 { 1962 1963 KASSERT(mutex_owned(&sc->sc_lock)); 1964 1965 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1966 sitd, (u_long)sitd->physaddr)); 1967 1968 LIST_REMOVE(sitd, hnext); 1969 } 1970 1971 ohci_soft_itd_t * 1972 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1973 { 1974 int h = HASH(a); 1975 ohci_soft_itd_t *sitd; 1976 1977 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1978 sitd != NULL; 1979 sitd = LIST_NEXT(sitd, hnext)) 1980 if (sitd->physaddr == a) 1981 return (sitd); 1982 return (NULL); 1983 } 1984 1985 void 1986 ohci_timeout(void *addr) 1987 { 1988 struct ohci_xfer *oxfer = addr; 1989 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1990 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1991 1992 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1993 1994 if (sc->sc_dying) { 1995 mutex_enter(&sc->sc_lock); 1996 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1997 mutex_exit(&sc->sc_lock); 1998 return; 1999 } 2000 2001 /* Execute the abort in a process context. */ 2002 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2003 USB_TASKQ_MPSAFE); 2004 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2005 USB_TASKQ_HC); 2006 } 2007 2008 void 2009 ohci_timeout_task(void *addr) 2010 { 2011 usbd_xfer_handle xfer = addr; 2012 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2013 2014 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2015 2016 mutex_enter(&sc->sc_lock); 2017 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2018 mutex_exit(&sc->sc_lock); 2019 } 2020 2021 #ifdef OHCI_DEBUG 2022 void 2023 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2024 { 2025 for (; std; std = std->nexttd) 2026 ohci_dump_td(sc, std); 2027 } 2028 2029 void 2030 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2031 { 2032 char sbuf[128]; 2033 2034 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2035 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2036 snprintb(sbuf, sizeof(sbuf), 2037 "\20\23R\24OUT\25IN\31TOG1\32SETTOGGLE", 2038 (u_int32_t)O32TOH(std->td.td_flags)); 2039 printf("TD(%p) at %08lx: %s delay=%d ec=%d cc=%d\ncbp=0x%08lx " 2040 "nexttd=0x%08lx be=0x%08lx\n", 2041 std, (u_long)std->physaddr, sbuf, 2042 OHCI_TD_GET_DI(O32TOH(std->td.td_flags)), 2043 OHCI_TD_GET_EC(O32TOH(std->td.td_flags)), 2044 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 2045 (u_long)O32TOH(std->td.td_cbp), 2046 (u_long)O32TOH(std->td.td_nexttd), 2047 (u_long)O32TOH(std->td.td_be)); 2048 } 2049 2050 void 2051 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2052 { 2053 int i; 2054 2055 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2057 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2058 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2059 sitd, (u_long)sitd->physaddr, 2060 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2061 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2062 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2063 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2064 (u_long)O32TOH(sitd->itd.itd_bp0), 2065 (u_long)O32TOH(sitd->itd.itd_nextitd), 2066 (u_long)O32TOH(sitd->itd.itd_be)); 2067 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2068 printf("offs[%d]=0x%04x ", i, 2069 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2070 printf("\n"); 2071 } 2072 2073 void 2074 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2075 { 2076 for (; sitd; sitd = sitd->nextitd) 2077 ohci_dump_itd(sc, sitd); 2078 } 2079 2080 void 2081 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2082 { 2083 char sbuf[128], sbuf2[128]; 2084 2085 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2086 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2087 snprintb(sbuf, sizeof(sbuf), 2088 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2089 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2090 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2091 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2092 2093 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2094 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2095 sed, (u_long)sed->physaddr, 2096 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2097 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2098 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2099 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2100 (u_long)O32TOH(sed->ed.ed_headp), 2101 (u_long)O32TOH(sed->ed.ed_nexted)); 2102 } 2103 #endif 2104 2105 usbd_status 2106 ohci_open(usbd_pipe_handle pipe) 2107 { 2108 usbd_device_handle dev = pipe->device; 2109 ohci_softc_t *sc = dev->bus->hci_private; 2110 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2111 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2112 u_int8_t addr = dev->address; 2113 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2114 ohci_soft_ed_t *sed; 2115 ohci_soft_td_t *std; 2116 ohci_soft_itd_t *sitd; 2117 ohci_physaddr_t tdphys; 2118 u_int32_t fmt; 2119 usbd_status err = USBD_NOMEM; 2120 int ival; 2121 2122 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2123 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2124 2125 if (sc->sc_dying) { 2126 err = USBD_IOERROR; 2127 goto bad0; 2128 } 2129 2130 std = NULL; 2131 sed = NULL; 2132 2133 if (addr == sc->sc_addr) { 2134 switch (ed->bEndpointAddress) { 2135 case USB_CONTROL_ENDPOINT: 2136 pipe->methods = &ohci_root_ctrl_methods; 2137 break; 2138 case UE_DIR_IN | OHCI_INTR_ENDPT: 2139 pipe->methods = &ohci_root_intr_methods; 2140 break; 2141 default: 2142 err = USBD_INVAL; 2143 goto bad0; 2144 } 2145 } else { 2146 sed = ohci_alloc_sed(sc); 2147 if (sed == NULL) 2148 goto bad0; 2149 opipe->sed = sed; 2150 if (xfertype == UE_ISOCHRONOUS) { 2151 mutex_enter(&sc->sc_lock); 2152 sitd = ohci_alloc_sitd(sc); 2153 mutex_exit(&sc->sc_lock); 2154 if (sitd == NULL) 2155 goto bad1; 2156 opipe->tail.itd = sitd; 2157 tdphys = sitd->physaddr; 2158 fmt = OHCI_ED_FORMAT_ISO; 2159 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2160 fmt |= OHCI_ED_DIR_IN; 2161 else 2162 fmt |= OHCI_ED_DIR_OUT; 2163 } else { 2164 mutex_enter(&sc->sc_lock); 2165 std = ohci_alloc_std(sc); 2166 mutex_exit(&sc->sc_lock); 2167 if (std == NULL) 2168 goto bad1; 2169 opipe->tail.td = std; 2170 tdphys = std->physaddr; 2171 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2172 } 2173 sed->ed.ed_flags = HTOO32( 2174 OHCI_ED_SET_FA(addr) | 2175 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2176 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2177 fmt | 2178 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2179 sed->ed.ed_headp = HTOO32(tdphys | 2180 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2181 sed->ed.ed_tailp = HTOO32(tdphys); 2182 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2184 2185 switch (xfertype) { 2186 case UE_CONTROL: 2187 pipe->methods = &ohci_device_ctrl_methods; 2188 err = usb_allocmem(&sc->sc_bus, 2189 sizeof(usb_device_request_t), 2190 0, &opipe->u.ctl.reqdma); 2191 if (err) 2192 goto bad; 2193 mutex_enter(&sc->sc_lock); 2194 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2195 mutex_exit(&sc->sc_lock); 2196 break; 2197 case UE_INTERRUPT: 2198 pipe->methods = &ohci_device_intr_methods; 2199 ival = pipe->interval; 2200 if (ival == USBD_DEFAULT_INTERVAL) 2201 ival = ed->bInterval; 2202 err = ohci_device_setintr(sc, opipe, ival); 2203 if (err) 2204 goto bad; 2205 break; 2206 case UE_ISOCHRONOUS: 2207 pipe->methods = &ohci_device_isoc_methods; 2208 return (ohci_setup_isoc(pipe)); 2209 case UE_BULK: 2210 pipe->methods = &ohci_device_bulk_methods; 2211 mutex_enter(&sc->sc_lock); 2212 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2213 mutex_exit(&sc->sc_lock); 2214 break; 2215 } 2216 } 2217 2218 return USBD_NORMAL_COMPLETION; 2219 2220 bad: 2221 if (std != NULL) 2222 ohci_free_std(sc, std); 2223 bad1: 2224 if (sed != NULL) 2225 ohci_free_sed(sc, sed); 2226 bad0: 2227 return err; 2228 2229 } 2230 2231 /* 2232 * Close a reqular pipe. 2233 * Assumes that there are no pending transactions. 2234 */ 2235 void 2236 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2237 { 2238 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2239 ohci_softc_t *sc = pipe->device->bus->hci_private; 2240 ohci_soft_ed_t *sed = opipe->sed; 2241 2242 KASSERT(mutex_owned(&sc->sc_lock)); 2243 2244 #ifdef DIAGNOSTIC 2245 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2246 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2247 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2248 ohci_soft_td_t *std; 2249 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2250 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2251 "tl=0x%x pipe=%p, std=%p\n", sed, 2252 (int)O32TOH(sed->ed.ed_headp), 2253 (int)O32TOH(sed->ed.ed_tailp), 2254 pipe, std); 2255 #ifdef OHCI_DEBUG 2256 usbd_dump_pipe(&opipe->pipe); 2257 ohci_dump_ed(sc, sed); 2258 if (std) 2259 ohci_dump_td(sc, std); 2260 #endif 2261 usb_delay_ms(&sc->sc_bus, 2); 2262 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2263 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2264 printf("ohci_close_pipe: pipe still not empty\n"); 2265 } 2266 #endif 2267 ohci_rem_ed(sc, sed, head); 2268 /* Make sure the host controller is not touching this ED */ 2269 usb_delay_ms(&sc->sc_bus, 1); 2270 pipe->endpoint->datatoggle = 2271 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2272 ohci_free_sed(sc, opipe->sed); 2273 } 2274 2275 /* 2276 * Abort a device request. 2277 * If this routine is called at splusb() it guarantees that the request 2278 * will be removed from the hardware scheduling and that the callback 2279 * for it will be called with USBD_CANCELLED status. 2280 * It's impossible to guarantee that the requested transfer will not 2281 * have happened since the hardware runs concurrently. 2282 * If the transaction has already happened we rely on the ordinary 2283 * interrupt processing to process it. 2284 * XXX This is most probably wrong. 2285 * XXXMRG this doesn't make sense anymore. 2286 */ 2287 void 2288 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2289 { 2290 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2291 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2292 ohci_soft_ed_t *sed = opipe->sed; 2293 ohci_soft_td_t *p, *n; 2294 ohci_physaddr_t headp; 2295 int hit; 2296 int wake; 2297 2298 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2299 2300 KASSERT(mutex_owned(&sc->sc_lock)); 2301 2302 if (sc->sc_dying) { 2303 /* If we're dying, just do the software part. */ 2304 xfer->status = status; /* make software ignore it */ 2305 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2306 usb_transfer_complete(xfer); 2307 return; 2308 } 2309 2310 if (cpu_intr_p() || cpu_softintr_p()) 2311 panic("ohci_abort_xfer: not in process context"); 2312 2313 /* 2314 * If an abort is already in progress then just wait for it to 2315 * complete and return. 2316 */ 2317 if (xfer->hcflags & UXFER_ABORTING) { 2318 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2319 #ifdef DIAGNOSTIC 2320 if (status == USBD_TIMEOUT) 2321 printf("%s: TIMEOUT while aborting\n", __func__); 2322 #endif 2323 /* Override the status which might be USBD_TIMEOUT. */ 2324 xfer->status = status; 2325 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2326 xfer->hcflags |= UXFER_ABORTWAIT; 2327 while (xfer->hcflags & UXFER_ABORTING) 2328 cv_wait(&xfer->hccv, &sc->sc_lock); 2329 goto done; 2330 } 2331 xfer->hcflags |= UXFER_ABORTING; 2332 2333 /* 2334 * Step 1: Make interrupt routine and hardware ignore xfer. 2335 */ 2336 xfer->status = status; /* make software ignore it */ 2337 callout_stop(&xfer->timeout_handle); 2338 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2339 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2340 sizeof(sed->ed.ed_flags), 2341 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2342 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2343 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2344 sizeof(sed->ed.ed_flags), 2345 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2346 2347 /* 2348 * Step 2: Wait until we know hardware has finished any possible 2349 * use of the xfer. Also make sure the soft interrupt routine 2350 * has run. 2351 */ 2352 /* Hardware finishes in 1ms */ 2353 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2354 sc->sc_softwake = 1; 2355 usb_schedsoftintr(&sc->sc_bus); 2356 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2357 2358 /* 2359 * Step 3: Remove any vestiges of the xfer from the hardware. 2360 * The complication here is that the hardware may have executed 2361 * beyond the xfer we're trying to abort. So as we're scanning 2362 * the TDs of this xfer we check if the hardware points to 2363 * any of them. 2364 */ 2365 p = xfer->hcpriv; 2366 #ifdef DIAGNOSTIC 2367 if (p == NULL) { 2368 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2369 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2370 goto done; 2371 } 2372 #endif 2373 #ifdef OHCI_DEBUG 2374 if (ohcidebug > 1) { 2375 DPRINTF(("ohci_abort_xfer: sed=\n")); 2376 ohci_dump_ed(sc, sed); 2377 ohci_dump_tds(sc, p); 2378 } 2379 #endif 2380 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2381 hit = 0; 2382 for (; p->xfer == xfer; p = n) { 2383 hit |= headp == p->physaddr; 2384 n = p->nexttd; 2385 ohci_free_std(sc, p); 2386 } 2387 /* Zap headp register if hardware pointed inside the xfer. */ 2388 if (hit) { 2389 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2390 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2391 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2392 usb_syncmem(&sed->dma, 2393 sed->offs + offsetof(ohci_ed_t, ed_headp), 2394 sizeof(sed->ed.ed_headp), 2395 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2396 } else { 2397 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2398 } 2399 2400 /* 2401 * Step 4: Turn on hardware again. 2402 */ 2403 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2404 sizeof(sed->ed.ed_flags), 2405 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2406 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2407 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2408 sizeof(sed->ed.ed_flags), 2409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2410 2411 /* 2412 * Step 5: Execute callback. 2413 */ 2414 wake = xfer->hcflags & UXFER_ABORTWAIT; 2415 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2416 usb_transfer_complete(xfer); 2417 if (wake) 2418 cv_broadcast(&xfer->hccv); 2419 2420 done: 2421 KASSERT(mutex_owned(&sc->sc_lock)); 2422 } 2423 2424 /* 2425 * Data structures and routines to emulate the root hub. 2426 */ 2427 Static usb_device_descriptor_t ohci_devd = { 2428 USB_DEVICE_DESCRIPTOR_SIZE, 2429 UDESC_DEVICE, /* type */ 2430 {0x00, 0x01}, /* USB version */ 2431 UDCLASS_HUB, /* class */ 2432 UDSUBCLASS_HUB, /* subclass */ 2433 UDPROTO_FSHUB, /* protocol */ 2434 64, /* max packet */ 2435 {0},{0},{0x00,0x01}, /* device id */ 2436 1,2,0, /* string indicies */ 2437 1 /* # of configurations */ 2438 }; 2439 2440 Static const usb_config_descriptor_t ohci_confd = { 2441 USB_CONFIG_DESCRIPTOR_SIZE, 2442 UDESC_CONFIG, 2443 {USB_CONFIG_DESCRIPTOR_SIZE + 2444 USB_INTERFACE_DESCRIPTOR_SIZE + 2445 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2446 1, 2447 1, 2448 0, 2449 UC_ATTR_MBO | UC_SELF_POWERED, 2450 0 /* max power */ 2451 }; 2452 2453 Static const usb_interface_descriptor_t ohci_ifcd = { 2454 USB_INTERFACE_DESCRIPTOR_SIZE, 2455 UDESC_INTERFACE, 2456 0, 2457 0, 2458 1, 2459 UICLASS_HUB, 2460 UISUBCLASS_HUB, 2461 UIPROTO_FSHUB, 2462 0 2463 }; 2464 2465 Static const usb_endpoint_descriptor_t ohci_endpd = { 2466 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2467 .bDescriptorType = UDESC_ENDPOINT, 2468 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2469 .bmAttributes = UE_INTERRUPT, 2470 .wMaxPacketSize = {8, 0}, /* max packet */ 2471 .bInterval = 255, 2472 }; 2473 2474 Static const usb_hub_descriptor_t ohci_hubd = { 2475 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2476 .bDescriptorType = UDESC_HUB, 2477 }; 2478 2479 /* 2480 * Simulate a hardware hub by handling all the necessary requests. 2481 */ 2482 Static usbd_status 2483 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2484 { 2485 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2486 usbd_status err; 2487 2488 /* Insert last in queue. */ 2489 mutex_enter(&sc->sc_lock); 2490 err = usb_insert_transfer(xfer); 2491 mutex_exit(&sc->sc_lock); 2492 if (err) 2493 return (err); 2494 2495 /* Pipe isn't running, start first */ 2496 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2497 } 2498 2499 Static usbd_status 2500 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2501 { 2502 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2503 usb_device_request_t *req; 2504 void *buf = NULL; 2505 int port, i; 2506 int len, value, index, l, totlen = 0; 2507 usb_port_status_t ps; 2508 usb_hub_descriptor_t hubd; 2509 usbd_status err; 2510 u_int32_t v; 2511 2512 if (sc->sc_dying) 2513 return (USBD_IOERROR); 2514 2515 #ifdef DIAGNOSTIC 2516 if (!(xfer->rqflags & URQ_REQUEST)) 2517 /* XXX panic */ 2518 return (USBD_INVAL); 2519 #endif 2520 req = &xfer->request; 2521 2522 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2523 req->bmRequestType, req->bRequest)); 2524 2525 len = UGETW(req->wLength); 2526 value = UGETW(req->wValue); 2527 index = UGETW(req->wIndex); 2528 2529 if (len != 0) 2530 buf = KERNADDR(&xfer->dmabuf, 0); 2531 2532 #define C(x,y) ((x) | ((y) << 8)) 2533 switch(C(req->bRequest, req->bmRequestType)) { 2534 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2535 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2536 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2537 /* 2538 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2539 * for the integrated root hub. 2540 */ 2541 break; 2542 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2543 if (len > 0) { 2544 *(u_int8_t *)buf = sc->sc_conf; 2545 totlen = 1; 2546 } 2547 break; 2548 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2549 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2550 if (len == 0) 2551 break; 2552 switch(value >> 8) { 2553 case UDESC_DEVICE: 2554 if ((value & 0xff) != 0) { 2555 err = USBD_IOERROR; 2556 goto ret; 2557 } 2558 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2559 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2560 memcpy(buf, &ohci_devd, l); 2561 break; 2562 case UDESC_CONFIG: 2563 if ((value & 0xff) != 0) { 2564 err = USBD_IOERROR; 2565 goto ret; 2566 } 2567 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2568 memcpy(buf, &ohci_confd, l); 2569 buf = (char *)buf + l; 2570 len -= l; 2571 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2572 totlen += l; 2573 memcpy(buf, &ohci_ifcd, l); 2574 buf = (char *)buf + l; 2575 len -= l; 2576 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2577 totlen += l; 2578 memcpy(buf, &ohci_endpd, l); 2579 break; 2580 case UDESC_STRING: 2581 #define sd ((usb_string_descriptor_t *)buf) 2582 switch (value & 0xff) { 2583 case 0: /* Language table */ 2584 totlen = usb_makelangtbl(sd, len); 2585 break; 2586 case 1: /* Vendor */ 2587 totlen = usb_makestrdesc(sd, len, 2588 sc->sc_vendor); 2589 break; 2590 case 2: /* Product */ 2591 totlen = usb_makestrdesc(sd, len, 2592 "OHCI root hub"); 2593 break; 2594 } 2595 #undef sd 2596 break; 2597 default: 2598 err = USBD_IOERROR; 2599 goto ret; 2600 } 2601 break; 2602 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2603 if (len > 0) { 2604 *(u_int8_t *)buf = 0; 2605 totlen = 1; 2606 } 2607 break; 2608 case C(UR_GET_STATUS, UT_READ_DEVICE): 2609 if (len > 1) { 2610 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2611 totlen = 2; 2612 } 2613 break; 2614 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2615 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2616 if (len > 1) { 2617 USETW(((usb_status_t *)buf)->wStatus, 0); 2618 totlen = 2; 2619 } 2620 break; 2621 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2622 if (value >= USB_MAX_DEVICES) { 2623 err = USBD_IOERROR; 2624 goto ret; 2625 } 2626 sc->sc_addr = value; 2627 break; 2628 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2629 if (value != 0 && value != 1) { 2630 err = USBD_IOERROR; 2631 goto ret; 2632 } 2633 sc->sc_conf = value; 2634 break; 2635 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2636 break; 2637 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2638 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2639 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2640 err = USBD_IOERROR; 2641 goto ret; 2642 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2643 break; 2644 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2645 break; 2646 /* Hub requests */ 2647 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2648 break; 2649 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2650 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2651 "port=%d feature=%d\n", 2652 index, value)); 2653 if (index < 1 || index > sc->sc_noport) { 2654 err = USBD_IOERROR; 2655 goto ret; 2656 } 2657 port = OHCI_RH_PORT_STATUS(index); 2658 switch(value) { 2659 case UHF_PORT_ENABLE: 2660 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2661 break; 2662 case UHF_PORT_SUSPEND: 2663 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2664 break; 2665 case UHF_PORT_POWER: 2666 /* Yes, writing to the LOW_SPEED bit clears power. */ 2667 OWRITE4(sc, port, UPS_LOW_SPEED); 2668 break; 2669 case UHF_C_PORT_CONNECTION: 2670 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2671 break; 2672 case UHF_C_PORT_ENABLE: 2673 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2674 break; 2675 case UHF_C_PORT_SUSPEND: 2676 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2677 break; 2678 case UHF_C_PORT_OVER_CURRENT: 2679 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2680 break; 2681 case UHF_C_PORT_RESET: 2682 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2683 break; 2684 default: 2685 err = USBD_IOERROR; 2686 goto ret; 2687 } 2688 switch(value) { 2689 case UHF_C_PORT_CONNECTION: 2690 case UHF_C_PORT_ENABLE: 2691 case UHF_C_PORT_SUSPEND: 2692 case UHF_C_PORT_OVER_CURRENT: 2693 case UHF_C_PORT_RESET: 2694 /* Enable RHSC interrupt if condition is cleared. */ 2695 if ((OREAD4(sc, port) >> 16) == 0) 2696 ohci_rhsc_enable(sc); 2697 break; 2698 default: 2699 break; 2700 } 2701 break; 2702 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2703 if (len == 0) 2704 break; 2705 if ((value & 0xff) != 0) { 2706 err = USBD_IOERROR; 2707 goto ret; 2708 } 2709 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2710 hubd = ohci_hubd; 2711 hubd.bNbrPorts = sc->sc_noport; 2712 USETW(hubd.wHubCharacteristics, 2713 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2714 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2715 /* XXX overcurrent */ 2716 ); 2717 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2718 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2719 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2720 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2721 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2722 l = min(len, hubd.bDescLength); 2723 totlen = l; 2724 memcpy(buf, &hubd, l); 2725 break; 2726 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2727 if (len != 4) { 2728 err = USBD_IOERROR; 2729 goto ret; 2730 } 2731 memset(buf, 0, len); /* ? XXX */ 2732 totlen = len; 2733 break; 2734 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2735 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2736 index)); 2737 if (index < 1 || index > sc->sc_noport) { 2738 err = USBD_IOERROR; 2739 goto ret; 2740 } 2741 if (len != 4) { 2742 err = USBD_IOERROR; 2743 goto ret; 2744 } 2745 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2746 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2747 v)); 2748 USETW(ps.wPortStatus, v); 2749 USETW(ps.wPortChange, v >> 16); 2750 l = min(len, sizeof ps); 2751 memcpy(buf, &ps, l); 2752 totlen = l; 2753 break; 2754 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2755 err = USBD_IOERROR; 2756 goto ret; 2757 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2758 break; 2759 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2760 if (index < 1 || index > sc->sc_noport) { 2761 err = USBD_IOERROR; 2762 goto ret; 2763 } 2764 port = OHCI_RH_PORT_STATUS(index); 2765 switch(value) { 2766 case UHF_PORT_ENABLE: 2767 OWRITE4(sc, port, UPS_PORT_ENABLED); 2768 break; 2769 case UHF_PORT_SUSPEND: 2770 OWRITE4(sc, port, UPS_SUSPEND); 2771 break; 2772 case UHF_PORT_RESET: 2773 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2774 index)); 2775 OWRITE4(sc, port, UPS_RESET); 2776 for (i = 0; i < 5; i++) { 2777 usb_delay_ms(&sc->sc_bus, 2778 USB_PORT_ROOT_RESET_DELAY); 2779 if (sc->sc_dying) { 2780 err = USBD_IOERROR; 2781 goto ret; 2782 } 2783 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2784 break; 2785 } 2786 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2787 index, OREAD4(sc, port))); 2788 break; 2789 case UHF_PORT_POWER: 2790 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2791 "%d\n", index)); 2792 OWRITE4(sc, port, UPS_PORT_POWER); 2793 break; 2794 default: 2795 err = USBD_IOERROR; 2796 goto ret; 2797 } 2798 break; 2799 default: 2800 err = USBD_IOERROR; 2801 goto ret; 2802 } 2803 xfer->actlen = totlen; 2804 err = USBD_NORMAL_COMPLETION; 2805 ret: 2806 xfer->status = err; 2807 mutex_enter(&sc->sc_lock); 2808 usb_transfer_complete(xfer); 2809 mutex_exit(&sc->sc_lock); 2810 return (USBD_IN_PROGRESS); 2811 } 2812 2813 /* Abort a root control request. */ 2814 Static void 2815 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2816 { 2817 /* Nothing to do, all transfers are synchronous. */ 2818 } 2819 2820 /* Close the root pipe. */ 2821 Static void 2822 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2823 { 2824 DPRINTF(("ohci_root_ctrl_close\n")); 2825 /* Nothing to do. */ 2826 } 2827 2828 Static usbd_status 2829 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2830 { 2831 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2832 usbd_status err; 2833 2834 /* Insert last in queue. */ 2835 mutex_enter(&sc->sc_lock); 2836 err = usb_insert_transfer(xfer); 2837 mutex_exit(&sc->sc_lock); 2838 if (err) 2839 return (err); 2840 2841 /* Pipe isn't running, start first */ 2842 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2843 } 2844 2845 Static usbd_status 2846 ohci_root_intr_start(usbd_xfer_handle xfer) 2847 { 2848 usbd_pipe_handle pipe = xfer->pipe; 2849 ohci_softc_t *sc = pipe->device->bus->hci_private; 2850 2851 if (sc->sc_dying) 2852 return (USBD_IOERROR); 2853 2854 mutex_enter(&sc->sc_lock); 2855 KASSERT(sc->sc_intrxfer == NULL); 2856 sc->sc_intrxfer = xfer; 2857 mutex_exit(&sc->sc_lock); 2858 2859 return (USBD_IN_PROGRESS); 2860 } 2861 2862 /* Abort a root interrupt request. */ 2863 Static void 2864 ohci_root_intr_abort(usbd_xfer_handle xfer) 2865 { 2866 #ifdef DIAGNOSTIC 2867 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2868 #endif 2869 2870 KASSERT(mutex_owned(&sc->sc_lock)); 2871 2872 if (xfer->pipe->intrxfer == xfer) { 2873 DPRINTF(("ohci_root_intr_abort: remove\n")); 2874 xfer->pipe->intrxfer = NULL; 2875 } 2876 xfer->status = USBD_CANCELLED; 2877 usb_transfer_complete(xfer); 2878 } 2879 2880 /* Close the root pipe. */ 2881 Static void 2882 ohci_root_intr_close(usbd_pipe_handle pipe) 2883 { 2884 ohci_softc_t *sc = pipe->device->bus->hci_private; 2885 2886 KASSERT(mutex_owned(&sc->sc_lock)); 2887 2888 DPRINTF(("ohci_root_intr_close\n")); 2889 2890 sc->sc_intrxfer = NULL; 2891 } 2892 2893 /************************/ 2894 2895 Static usbd_status 2896 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2897 { 2898 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2899 usbd_status err; 2900 2901 /* Insert last in queue. */ 2902 mutex_enter(&sc->sc_lock); 2903 err = usb_insert_transfer(xfer); 2904 mutex_exit(&sc->sc_lock); 2905 if (err) 2906 return (err); 2907 2908 /* Pipe isn't running, start first */ 2909 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2910 } 2911 2912 Static usbd_status 2913 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2914 { 2915 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2916 usbd_status err; 2917 2918 if (sc->sc_dying) 2919 return (USBD_IOERROR); 2920 2921 #ifdef DIAGNOSTIC 2922 if (!(xfer->rqflags & URQ_REQUEST)) { 2923 /* XXX panic */ 2924 printf("ohci_device_ctrl_transfer: not a request\n"); 2925 return (USBD_INVAL); 2926 } 2927 #endif 2928 2929 mutex_enter(&sc->sc_lock); 2930 err = ohci_device_request(xfer); 2931 mutex_exit(&sc->sc_lock); 2932 if (err) 2933 return (err); 2934 2935 if (sc->sc_bus.use_polling) 2936 ohci_waitintr(sc, xfer); 2937 return (USBD_IN_PROGRESS); 2938 } 2939 2940 /* Abort a device control request. */ 2941 Static void 2942 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2943 { 2944 #ifdef DIAGNOSTIC 2945 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2946 #endif 2947 2948 KASSERT(mutex_owned(&sc->sc_lock)); 2949 2950 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2951 ohci_abort_xfer(xfer, USBD_CANCELLED); 2952 } 2953 2954 /* Close a device control pipe. */ 2955 Static void 2956 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2957 { 2958 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2959 ohci_softc_t *sc = pipe->device->bus->hci_private; 2960 2961 KASSERT(mutex_owned(&sc->sc_lock)); 2962 2963 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2964 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2965 ohci_free_std(sc, opipe->tail.td); 2966 } 2967 2968 /************************/ 2969 2970 Static void 2971 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2972 { 2973 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2974 ohci_softc_t *sc = pipe->device->bus->hci_private; 2975 2976 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2977 } 2978 2979 Static void 2980 ohci_noop(usbd_pipe_handle pipe) 2981 { 2982 } 2983 2984 Static usbd_status 2985 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2986 { 2987 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2988 usbd_status err; 2989 2990 /* Insert last in queue. */ 2991 mutex_enter(&sc->sc_lock); 2992 err = usb_insert_transfer(xfer); 2993 mutex_exit(&sc->sc_lock); 2994 if (err) 2995 return (err); 2996 2997 /* Pipe isn't running, start first */ 2998 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2999 } 3000 3001 Static usbd_status 3002 ohci_device_bulk_start(usbd_xfer_handle xfer) 3003 { 3004 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3005 usbd_device_handle dev = opipe->pipe.device; 3006 ohci_softc_t *sc = dev->bus->hci_private; 3007 int addr = dev->address; 3008 ohci_soft_td_t *data, *tail, *tdp; 3009 ohci_soft_ed_t *sed; 3010 int len, isread, endpt; 3011 usbd_status err; 3012 3013 if (sc->sc_dying) 3014 return (USBD_IOERROR); 3015 3016 #ifdef DIAGNOSTIC 3017 if (xfer->rqflags & URQ_REQUEST) { 3018 /* XXX panic */ 3019 printf("ohci_device_bulk_start: a request\n"); 3020 return (USBD_INVAL); 3021 } 3022 #endif 3023 3024 mutex_enter(&sc->sc_lock); 3025 3026 len = xfer->length; 3027 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3028 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3029 sed = opipe->sed; 3030 3031 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3032 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3033 endpt)); 3034 3035 opipe->u.bulk.isread = isread; 3036 opipe->u.bulk.length = len; 3037 3038 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3039 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3040 /* Update device address */ 3041 sed->ed.ed_flags = HTOO32( 3042 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3043 OHCI_ED_SET_FA(addr)); 3044 3045 /* Allocate a chain of new TDs (including a new tail). */ 3046 data = opipe->tail.td; 3047 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3048 data, &tail); 3049 if (err) 3050 return err; 3051 3052 /* We want interrupt at the end of the transfer. */ 3053 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3054 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3055 tail->flags |= OHCI_CALL_DONE; 3056 tail = tail->nexttd; /* point at sentinel */ 3057 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3058 sizeof(tail->td.td_flags), 3059 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3060 if (err) { 3061 mutex_exit(&sc->sc_lock); 3062 return (err); 3063 } 3064 3065 tail->xfer = NULL; 3066 xfer->hcpriv = data; 3067 3068 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3069 "td_cbp=0x%08x td_be=0x%08x\n", 3070 (int)O32TOH(sed->ed.ed_flags), 3071 (int)O32TOH(data->td.td_flags), 3072 (int)O32TOH(data->td.td_cbp), 3073 (int)O32TOH(data->td.td_be))); 3074 3075 #ifdef OHCI_DEBUG 3076 if (ohcidebug > 5) { 3077 ohci_dump_ed(sc, sed); 3078 ohci_dump_tds(sc, data); 3079 } 3080 #endif 3081 3082 /* Insert ED in schedule */ 3083 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3084 tdp->xfer = xfer; 3085 } 3086 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3087 opipe->tail.td = tail; 3088 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3089 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3090 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3091 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3092 if (xfer->timeout && !sc->sc_bus.use_polling) { 3093 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3094 ohci_timeout, xfer); 3095 } 3096 mutex_exit(&sc->sc_lock); 3097 3098 #if 0 3099 /* This goes wrong if we are too slow. */ 3100 if (ohcidebug > 10) { 3101 delay(10000); 3102 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3103 OREAD4(sc, OHCI_COMMAND_STATUS))); 3104 ohci_dump_ed(sc, sed); 3105 ohci_dump_tds(sc, data); 3106 } 3107 #endif 3108 3109 return (USBD_IN_PROGRESS); 3110 } 3111 3112 Static void 3113 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3114 { 3115 #ifdef DIAGNOSTIC 3116 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3117 #endif 3118 3119 KASSERT(mutex_owned(&sc->sc_lock)); 3120 3121 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3122 ohci_abort_xfer(xfer, USBD_CANCELLED); 3123 } 3124 3125 /* 3126 * Close a device bulk pipe. 3127 */ 3128 Static void 3129 ohci_device_bulk_close(usbd_pipe_handle pipe) 3130 { 3131 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3132 ohci_softc_t *sc = pipe->device->bus->hci_private; 3133 3134 KASSERT(mutex_owned(&sc->sc_lock)); 3135 3136 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3137 ohci_close_pipe(pipe, sc->sc_bulk_head); 3138 ohci_free_std(sc, opipe->tail.td); 3139 } 3140 3141 /************************/ 3142 3143 Static usbd_status 3144 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3145 { 3146 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3147 usbd_status err; 3148 3149 /* Insert last in queue. */ 3150 mutex_enter(&sc->sc_lock); 3151 err = usb_insert_transfer(xfer); 3152 mutex_exit(&sc->sc_lock); 3153 if (err) 3154 return (err); 3155 3156 /* Pipe isn't running, start first */ 3157 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3158 } 3159 3160 Static usbd_status 3161 ohci_device_intr_start(usbd_xfer_handle xfer) 3162 { 3163 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3164 usbd_device_handle dev = opipe->pipe.device; 3165 ohci_softc_t *sc = dev->bus->hci_private; 3166 ohci_soft_ed_t *sed = opipe->sed; 3167 ohci_soft_td_t *data, *tail; 3168 int len, isread, endpt; 3169 3170 if (sc->sc_dying) 3171 return (USBD_IOERROR); 3172 3173 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3174 "flags=%d priv=%p\n", 3175 xfer, xfer->length, xfer->flags, xfer->priv)); 3176 3177 #ifdef DIAGNOSTIC 3178 if (xfer->rqflags & URQ_REQUEST) 3179 panic("ohci_device_intr_transfer: a request"); 3180 #endif 3181 3182 len = xfer->length; 3183 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3184 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3185 3186 data = opipe->tail.td; 3187 mutex_enter(&sc->sc_lock); 3188 tail = ohci_alloc_std(sc); 3189 mutex_exit(&sc->sc_lock); 3190 if (tail == NULL) 3191 return (USBD_NOMEM); 3192 tail->xfer = NULL; 3193 3194 data->td.td_flags = HTOO32( 3195 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3196 OHCI_TD_NOCC | 3197 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3198 if (xfer->flags & USBD_SHORT_XFER_OK) 3199 data->td.td_flags |= HTOO32(OHCI_TD_R); 3200 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3201 data->nexttd = tail; 3202 data->td.td_nexttd = HTOO32(tail->physaddr); 3203 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3204 data->len = len; 3205 data->xfer = xfer; 3206 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3207 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3209 xfer->hcpriv = data; 3210 3211 #ifdef OHCI_DEBUG 3212 if (ohcidebug > 5) { 3213 DPRINTF(("ohci_device_intr_transfer:\n")); 3214 ohci_dump_ed(sc, sed); 3215 ohci_dump_tds(sc, data); 3216 } 3217 #endif 3218 3219 /* Insert ED in schedule */ 3220 mutex_enter(&sc->sc_lock); 3221 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3222 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3223 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3224 opipe->tail.td = tail; 3225 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3226 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3228 3229 #if 0 3230 /* 3231 * This goes horribly wrong, printing thousands of descriptors, 3232 * because false references are followed due to the fact that the 3233 * TD is gone. 3234 */ 3235 if (ohcidebug > 5) { 3236 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3237 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3238 OREAD4(sc, OHCI_COMMAND_STATUS))); 3239 ohci_dump_ed(sc, sed); 3240 ohci_dump_tds(sc, data); 3241 } 3242 #endif 3243 mutex_exit(&sc->sc_lock); 3244 3245 return (USBD_IN_PROGRESS); 3246 } 3247 3248 /* Abort a device interrupt request. */ 3249 Static void 3250 ohci_device_intr_abort(usbd_xfer_handle xfer) 3251 { 3252 #ifdef DIAGNOSTIC 3253 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3254 #endif 3255 3256 KASSERT(mutex_owned(&sc->sc_lock)); 3257 3258 if (xfer->pipe->intrxfer == xfer) { 3259 DPRINTF(("ohci_device_intr_abort: remove\n")); 3260 xfer->pipe->intrxfer = NULL; 3261 } 3262 ohci_abort_xfer(xfer, USBD_CANCELLED); 3263 } 3264 3265 /* Close a device interrupt pipe. */ 3266 Static void 3267 ohci_device_intr_close(usbd_pipe_handle pipe) 3268 { 3269 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3270 ohci_softc_t *sc = pipe->device->bus->hci_private; 3271 int nslots = opipe->u.intr.nslots; 3272 int pos = opipe->u.intr.pos; 3273 int j; 3274 ohci_soft_ed_t *p, *sed = opipe->sed; 3275 3276 KASSERT(mutex_owned(&sc->sc_lock)); 3277 3278 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3279 pipe, nslots, pos)); 3280 usb_syncmem(&sed->dma, sed->offs, 3281 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3282 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3283 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3284 sizeof(sed->ed.ed_flags), 3285 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3286 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3287 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3288 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3289 3290 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3291 continue; 3292 #ifdef DIAGNOSTIC 3293 if (p == NULL) 3294 panic("ohci_device_intr_close: ED not found"); 3295 #endif 3296 p->next = sed->next; 3297 p->ed.ed_nexted = sed->ed.ed_nexted; 3298 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3299 sizeof(p->ed.ed_nexted), 3300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3301 3302 for (j = 0; j < nslots; j++) 3303 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3304 3305 ohci_free_std(sc, opipe->tail.td); 3306 ohci_free_sed(sc, opipe->sed); 3307 } 3308 3309 Static usbd_status 3310 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3311 { 3312 int i, j, best; 3313 u_int npoll, slow, shigh, nslots; 3314 u_int bestbw, bw; 3315 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3316 3317 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3318 if (ival == 0) { 3319 printf("ohci_setintr: 0 interval\n"); 3320 return (USBD_INVAL); 3321 } 3322 3323 npoll = OHCI_NO_INTRS; 3324 while (npoll > ival) 3325 npoll /= 2; 3326 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3327 3328 /* 3329 * We now know which level in the tree the ED must go into. 3330 * Figure out which slot has most bandwidth left over. 3331 * Slots to examine: 3332 * npoll 3333 * 1 0 3334 * 2 1 2 3335 * 4 3 4 5 6 3336 * 8 7 8 9 10 11 12 13 14 3337 * N (N-1) .. (N-1+N-1) 3338 */ 3339 slow = npoll-1; 3340 shigh = slow + npoll; 3341 nslots = OHCI_NO_INTRS / npoll; 3342 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3343 bw = 0; 3344 for (j = 0; j < nslots; j++) 3345 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3346 if (bw < bestbw) { 3347 best = i; 3348 bestbw = bw; 3349 } 3350 } 3351 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3352 best, slow, shigh, bestbw)); 3353 3354 mutex_enter(&sc->sc_lock); 3355 hsed = sc->sc_eds[best]; 3356 sed->next = hsed->next; 3357 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3358 sizeof(hsed->ed.ed_flags), 3359 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3360 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3361 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3362 sizeof(sed->ed.ed_flags), 3363 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3364 hsed->next = sed; 3365 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3366 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3367 sizeof(hsed->ed.ed_flags), 3368 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3369 mutex_exit(&sc->sc_lock); 3370 3371 for (j = 0; j < nslots; j++) 3372 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3373 opipe->u.intr.nslots = nslots; 3374 opipe->u.intr.pos = best; 3375 3376 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3377 return (USBD_NORMAL_COMPLETION); 3378 } 3379 3380 /***********************/ 3381 3382 usbd_status 3383 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3384 { 3385 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3386 usbd_status err; 3387 3388 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3389 3390 /* Put it on our queue, */ 3391 mutex_enter(&sc->sc_lock); 3392 err = usb_insert_transfer(xfer); 3393 mutex_exit(&sc->sc_lock); 3394 3395 /* bail out on error, */ 3396 if (err && err != USBD_IN_PROGRESS) 3397 return (err); 3398 3399 /* XXX should check inuse here */ 3400 3401 /* insert into schedule, */ 3402 ohci_device_isoc_enter(xfer); 3403 3404 /* and start if the pipe wasn't running */ 3405 if (!err) 3406 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3407 3408 return (err); 3409 } 3410 3411 void 3412 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3413 { 3414 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3415 usbd_device_handle dev = opipe->pipe.device; 3416 ohci_softc_t *sc = dev->bus->hci_private; 3417 ohci_soft_ed_t *sed = opipe->sed; 3418 struct iso *iso = &opipe->u.iso; 3419 ohci_soft_itd_t *sitd, *nsitd; 3420 ohci_physaddr_t buf, offs, noffs, bp0; 3421 int i, ncur, nframes; 3422 3423 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3424 "nframes=%d\n", 3425 iso->inuse, iso->next, xfer, xfer->nframes)); 3426 3427 if (sc->sc_dying) 3428 return; 3429 3430 if (iso->next == -1) { 3431 /* Not in use yet, schedule it a few frames ahead. */ 3432 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3433 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3434 iso->next)); 3435 } 3436 3437 sitd = opipe->tail.itd; 3438 buf = DMAADDR(&xfer->dmabuf, 0); 3439 bp0 = OHCI_PAGE(buf); 3440 offs = OHCI_PAGE_OFFSET(buf); 3441 nframes = xfer->nframes; 3442 xfer->hcpriv = sitd; 3443 for (i = ncur = 0; i < nframes; i++, ncur++) { 3444 noffs = offs + xfer->frlengths[i]; 3445 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3446 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3447 3448 /* Allocate next ITD */ 3449 mutex_enter(&sc->sc_lock); 3450 nsitd = ohci_alloc_sitd(sc); 3451 mutex_exit(&sc->sc_lock); 3452 if (nsitd == NULL) { 3453 /* XXX what now? */ 3454 printf("%s: isoc TD alloc failed\n", 3455 device_xname(sc->sc_dev)); 3456 return; 3457 } 3458 3459 /* Fill current ITD */ 3460 sitd->itd.itd_flags = HTOO32( 3461 OHCI_ITD_NOCC | 3462 OHCI_ITD_SET_SF(iso->next) | 3463 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3464 OHCI_ITD_SET_FC(ncur)); 3465 sitd->itd.itd_bp0 = HTOO32(bp0); 3466 sitd->nextitd = nsitd; 3467 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3468 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3469 sitd->xfer = xfer; 3470 sitd->flags = 0; 3471 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3472 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3473 3474 sitd = nsitd; 3475 iso->next = iso->next + ncur; 3476 bp0 = OHCI_PAGE(buf + offs); 3477 ncur = 0; 3478 } 3479 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3480 offs = noffs; 3481 } 3482 mutex_enter(&sc->sc_lock); 3483 nsitd = ohci_alloc_sitd(sc); 3484 mutex_exit(&sc->sc_lock); 3485 if (nsitd == NULL) { 3486 /* XXX what now? */ 3487 printf("%s: isoc TD alloc failed\n", 3488 device_xname(sc->sc_dev)); 3489 return; 3490 } 3491 /* Fixup last used ITD */ 3492 sitd->itd.itd_flags = HTOO32( 3493 OHCI_ITD_NOCC | 3494 OHCI_ITD_SET_SF(iso->next) | 3495 OHCI_ITD_SET_DI(0) | 3496 OHCI_ITD_SET_FC(ncur)); 3497 sitd->itd.itd_bp0 = HTOO32(bp0); 3498 sitd->nextitd = nsitd; 3499 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3500 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3501 sitd->xfer = xfer; 3502 sitd->flags = OHCI_CALL_DONE; 3503 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3504 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3505 3506 iso->next = iso->next + ncur; 3507 iso->inuse += nframes; 3508 3509 xfer->actlen = offs; /* XXX pretend we did it all */ 3510 3511 xfer->status = USBD_IN_PROGRESS; 3512 3513 #ifdef OHCI_DEBUG 3514 if (ohcidebug > 5) { 3515 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3516 O32TOH(sc->sc_hcca->hcca_frame_number))); 3517 ohci_dump_itds(sc, xfer->hcpriv); 3518 ohci_dump_ed(sc, sed); 3519 } 3520 #endif 3521 3522 mutex_enter(&sc->sc_lock); 3523 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3524 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3525 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3526 opipe->tail.itd = nsitd; 3527 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3528 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3529 sizeof(sed->ed.ed_flags), 3530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3531 mutex_exit(&sc->sc_lock); 3532 3533 #ifdef OHCI_DEBUG 3534 if (ohcidebug > 5) { 3535 delay(150000); 3536 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3537 O32TOH(sc->sc_hcca->hcca_frame_number))); 3538 ohci_dump_itds(sc, xfer->hcpriv); 3539 ohci_dump_ed(sc, sed); 3540 } 3541 #endif 3542 } 3543 3544 usbd_status 3545 ohci_device_isoc_start(usbd_xfer_handle xfer) 3546 { 3547 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3548 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3549 3550 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3551 3552 mutex_enter(&sc->sc_lock); 3553 3554 if (sc->sc_dying) { 3555 mutex_exit(&sc->sc_lock); 3556 return (USBD_IOERROR); 3557 } 3558 3559 #ifdef DIAGNOSTIC 3560 if (xfer->status != USBD_IN_PROGRESS) 3561 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3562 #endif 3563 3564 /* XXX anything to do? */ 3565 3566 mutex_exit(&sc->sc_lock); 3567 3568 return (USBD_IN_PROGRESS); 3569 } 3570 3571 void 3572 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3573 { 3574 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3575 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3576 ohci_soft_ed_t *sed; 3577 ohci_soft_itd_t *sitd; 3578 3579 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3580 3581 KASSERT(mutex_owned(&sc->sc_lock)); 3582 3583 /* Transfer is already done. */ 3584 if (xfer->status != USBD_NOT_STARTED && 3585 xfer->status != USBD_IN_PROGRESS) { 3586 printf("ohci_device_isoc_abort: early return\n"); 3587 goto done; 3588 } 3589 3590 /* Give xfer the requested abort code. */ 3591 xfer->status = USBD_CANCELLED; 3592 3593 sed = opipe->sed; 3594 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3595 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3596 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3597 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3598 sizeof(sed->ed.ed_flags), 3599 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3600 3601 sitd = xfer->hcpriv; 3602 #ifdef DIAGNOSTIC 3603 if (sitd == NULL) { 3604 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3605 goto done; 3606 } 3607 #endif 3608 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3609 #ifdef DIAGNOSTIC 3610 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3611 sitd->isdone = 1; 3612 #endif 3613 } 3614 3615 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3616 3617 /* Run callback. */ 3618 usb_transfer_complete(xfer); 3619 3620 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3621 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3622 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3624 3625 done: 3626 KASSERT(mutex_owned(&sc->sc_lock)); 3627 } 3628 3629 void 3630 ohci_device_isoc_done(usbd_xfer_handle xfer) 3631 { 3632 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3633 } 3634 3635 usbd_status 3636 ohci_setup_isoc(usbd_pipe_handle pipe) 3637 { 3638 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3639 ohci_softc_t *sc = pipe->device->bus->hci_private; 3640 struct iso *iso = &opipe->u.iso; 3641 3642 iso->next = -1; 3643 iso->inuse = 0; 3644 3645 mutex_enter(&sc->sc_lock); 3646 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3647 mutex_exit(&sc->sc_lock); 3648 3649 return (USBD_NORMAL_COMPLETION); 3650 } 3651 3652 void 3653 ohci_device_isoc_close(usbd_pipe_handle pipe) 3654 { 3655 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3656 ohci_softc_t *sc = pipe->device->bus->hci_private; 3657 3658 KASSERT(mutex_owned(&sc->sc_lock)); 3659 3660 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3661 ohci_close_pipe(pipe, sc->sc_isoc_head); 3662 #ifdef DIAGNOSTIC 3663 opipe->tail.itd->isdone = 1; 3664 #endif 3665 ohci_free_sitd(sc, opipe->tail.itd); 3666 } 3667
Indexes created Wed Sep 24 15:09:51 GMT 2025