ohci.c revision 1.239
1 /* $NetBSD: ohci.c,v 1.239 2013/04/04 12:21:12 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.239 2013/04/04 12:21:12 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 136 137 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 138 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 139 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 140 Static void ohci_root_ctrl_close(usbd_pipe_handle); 141 Static void ohci_root_ctrl_done(usbd_xfer_handle); 142 143 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 145 Static void ohci_root_intr_abort(usbd_xfer_handle); 146 Static void ohci_root_intr_close(usbd_pipe_handle); 147 Static void ohci_root_intr_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 151 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 152 Static void ohci_device_ctrl_close(usbd_pipe_handle); 153 Static void ohci_device_ctrl_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 157 Static void ohci_device_bulk_abort(usbd_xfer_handle); 158 Static void ohci_device_bulk_close(usbd_pipe_handle); 159 Static void ohci_device_bulk_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 163 Static void ohci_device_intr_abort(usbd_xfer_handle); 164 Static void ohci_device_intr_close(usbd_pipe_handle); 165 Static void ohci_device_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 169 Static void ohci_device_isoc_abort(usbd_xfer_handle); 170 Static void ohci_device_isoc_close(usbd_pipe_handle); 171 Static void ohci_device_isoc_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 174 struct ohci_pipe *pipe, int ival); 175 176 Static void ohci_timeout(void *); 177 Static void ohci_timeout_task(void *); 178 Static void ohci_rhsc_enable(void *); 179 180 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 181 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 182 183 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ohci_noop(usbd_pipe_handle pipe); 185 186 #ifdef OHCI_DEBUG 187 Static void ohci_dumpregs(ohci_softc_t *); 188 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 191 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 192 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 193 #endif 194 195 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 196 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 197 #define OWRITE1(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OWRITE2(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE4(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 static __inline uint8_t 204 OREAD1(ohci_softc_t *sc, bus_size_t r) 205 { 206 207 OBARR(sc); 208 return bus_space_read_1(sc->iot, sc->ioh, r); 209 } 210 211 static __inline uint16_t 212 OREAD2(ohci_softc_t *sc, bus_size_t r) 213 { 214 215 OBARR(sc); 216 return bus_space_read_2(sc->iot, sc->ioh, r); 217 } 218 219 static __inline uint32_t 220 OREAD4(ohci_softc_t *sc, bus_size_t r) 221 { 222 223 OBARR(sc); 224 return bus_space_read_4(sc->iot, sc->ioh, r); 225 } 226 227 /* Reverse the bits in a value 0 .. 31 */ 228 Static u_int8_t revbits[OHCI_NO_INTRS] = 229 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 230 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 231 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 232 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 233 234 struct ohci_pipe { 235 struct usbd_pipe pipe; 236 ohci_soft_ed_t *sed; 237 union { 238 ohci_soft_td_t *td; 239 ohci_soft_itd_t *itd; 240 } tail; 241 /* Info needed for different pipe kinds. */ 242 union { 243 /* Control pipe */ 244 struct { 245 usb_dma_t reqdma; 246 u_int length; 247 ohci_soft_td_t *setup, *data, *stat; 248 } ctl; 249 /* Interrupt pipe */ 250 struct { 251 int nslots; 252 int pos; 253 } intr; 254 /* Bulk pipe */ 255 struct { 256 u_int length; 257 int isread; 258 } bulk; 259 /* Iso pipe */ 260 struct iso { 261 int next, inuse; 262 } iso; 263 } u; 264 }; 265 266 #define OHCI_INTR_ENDPT 1 267 268 Static const struct usbd_bus_methods ohci_bus_methods = { 269 .open_pipe = ohci_open, 270 .soft_intr = ohci_softintr, 271 .do_poll = ohci_poll, 272 .allocm = ohci_allocm, 273 .freem = ohci_freem, 274 .allocx = ohci_allocx, 275 .freex = ohci_freex, 276 .get_lock = ohci_get_lock, 277 }; 278 279 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 280 .transfer = ohci_root_ctrl_transfer, 281 .start = ohci_root_ctrl_start, 282 .abort = ohci_root_ctrl_abort, 283 .close = ohci_root_ctrl_close, 284 .cleartoggle = ohci_noop, 285 .done = ohci_root_ctrl_done, 286 }; 287 288 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 289 .transfer = ohci_root_intr_transfer, 290 .start = ohci_root_intr_start, 291 .abort = ohci_root_intr_abort, 292 .close = ohci_root_intr_close, 293 .cleartoggle = ohci_noop, 294 .done = ohci_root_intr_done, 295 }; 296 297 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 298 .transfer = ohci_device_ctrl_transfer, 299 .start = ohci_device_ctrl_start, 300 .abort = ohci_device_ctrl_abort, 301 .close = ohci_device_ctrl_close, 302 .cleartoggle = ohci_noop, 303 .done = ohci_device_ctrl_done, 304 }; 305 306 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 307 .transfer = ohci_device_intr_transfer, 308 .start = ohci_device_intr_start, 309 .abort = ohci_device_intr_abort, 310 .close = ohci_device_intr_close, 311 .cleartoggle = ohci_device_clear_toggle, 312 .done = ohci_device_intr_done, 313 }; 314 315 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 316 .transfer = ohci_device_bulk_transfer, 317 .start = ohci_device_bulk_start, 318 .abort = ohci_device_bulk_abort, 319 .close = ohci_device_bulk_close, 320 .cleartoggle = ohci_device_clear_toggle, 321 .done = ohci_device_bulk_done, 322 }; 323 324 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 325 .transfer = ohci_device_isoc_transfer, 326 .start = ohci_device_isoc_start, 327 .abort = ohci_device_isoc_abort, 328 .close = ohci_device_isoc_close, 329 .cleartoggle = ohci_noop, 330 .done = ohci_device_isoc_done, 331 }; 332 333 int 334 ohci_activate(device_t self, enum devact act) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 switch (act) { 339 case DVACT_DEACTIVATE: 340 sc->sc_dying = 1; 341 return 0; 342 default: 343 return EOPNOTSUPP; 344 } 345 } 346 347 void 348 ohci_childdet(device_t self, device_t child) 349 { 350 struct ohci_softc *sc = device_private(self); 351 352 KASSERT(sc->sc_child == child); 353 sc->sc_child = NULL; 354 } 355 356 int 357 ohci_detach(struct ohci_softc *sc, int flags) 358 { 359 int rv = 0; 360 361 if (sc->sc_child != NULL) 362 rv = config_detach(sc->sc_child, flags); 363 364 if (rv != 0) 365 return (rv); 366 367 callout_stop(&sc->sc_tmo_rhsc); 368 369 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 370 callout_destroy(&sc->sc_tmo_rhsc); 371 372 softint_disestablish(sc->sc_rhsc_si); 373 374 cv_destroy(&sc->sc_softwake_cv); 375 376 mutex_destroy(&sc->sc_lock); 377 mutex_destroy(&sc->sc_intr_lock); 378 379 if (sc->sc_hcca != NULL) 380 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 381 pool_cache_destroy(sc->sc_xferpool); 382 383 return (rv); 384 } 385 386 ohci_soft_ed_t * 387 ohci_alloc_sed(ohci_softc_t *sc) 388 { 389 ohci_soft_ed_t *sed; 390 usbd_status err; 391 int i, offs; 392 usb_dma_t dma; 393 394 if (sc->sc_freeeds == NULL) { 395 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 396 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 397 OHCI_ED_ALIGN, &dma); 398 if (err) 399 return (0); 400 for (i = 0; i < OHCI_SED_CHUNK; i++) { 401 offs = i * OHCI_SED_SIZE; 402 sed = KERNADDR(&dma, offs); 403 sed->physaddr = DMAADDR(&dma, offs); 404 sed->dma = dma; 405 sed->offs = offs; 406 sed->next = sc->sc_freeeds; 407 sc->sc_freeeds = sed; 408 } 409 } 410 sed = sc->sc_freeeds; 411 sc->sc_freeeds = sed->next; 412 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 413 sed->next = 0; 414 return (sed); 415 } 416 417 void 418 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 419 { 420 sed->next = sc->sc_freeeds; 421 sc->sc_freeeds = sed; 422 } 423 424 ohci_soft_td_t * 425 ohci_alloc_std(ohci_softc_t *sc) 426 { 427 ohci_soft_td_t *std; 428 usbd_status err; 429 int i, offs; 430 usb_dma_t dma; 431 432 if (sc->sc_freetds == NULL) { 433 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 434 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 435 OHCI_TD_ALIGN, &dma); 436 if (err) 437 return (NULL); 438 for(i = 0; i < OHCI_STD_CHUNK; i++) { 439 offs = i * OHCI_STD_SIZE; 440 std = KERNADDR(&dma, offs); 441 std->physaddr = DMAADDR(&dma, offs); 442 std->dma = dma; 443 std->offs = offs; 444 std->nexttd = sc->sc_freetds; 445 sc->sc_freetds = std; 446 } 447 } 448 449 std = sc->sc_freetds; 450 sc->sc_freetds = std->nexttd; 451 memset(&std->td, 0, sizeof(ohci_td_t)); 452 std->nexttd = NULL; 453 std->xfer = NULL; 454 ohci_hash_add_td(sc, std); 455 456 return (std); 457 } 458 459 void 460 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 461 { 462 463 ohci_hash_rem_td(sc, std); 464 std->nexttd = sc->sc_freetds; 465 sc->sc_freetds = std; 466 } 467 468 usbd_status 469 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 470 int alen, int rd, usbd_xfer_handle xfer, 471 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 472 { 473 ohci_soft_td_t *next, *cur; 474 ohci_physaddr_t dataphys, dataphysend; 475 u_int32_t tdflags; 476 int len, curlen; 477 usb_dma_t *dma = &xfer->dmabuf; 478 u_int16_t flags = xfer->flags; 479 480 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 481 482 KASSERT(mutex_owned(&sc->sc_lock)); 483 484 len = alen; 485 cur = sp; 486 dataphys = DMAADDR(dma, 0); 487 dataphysend = OHCI_PAGE(dataphys + len - 1); 488 usb_syncmem(dma, 0, len, 489 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 490 tdflags = HTOO32( 491 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 492 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 493 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 494 495 for (;;) { 496 next = ohci_alloc_std(sc); 497 if (next == NULL) 498 goto nomem; 499 500 /* The OHCI hardware can handle at most one page crossing. */ 501 if (OHCI_PAGE(dataphys) == dataphysend || 502 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 503 /* we can handle it in this TD */ 504 curlen = len; 505 } else { 506 /* must use multiple TDs, fill as much as possible. */ 507 curlen = 2 * OHCI_PAGE_SIZE - 508 (dataphys & (OHCI_PAGE_SIZE-1)); 509 /* the length must be a multiple of the max size */ 510 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 511 #ifdef DIAGNOSTIC 512 if (curlen == 0) 513 panic("ohci_alloc_std: curlen == 0"); 514 #endif 515 } 516 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 517 "dataphysend=0x%08x len=%d curlen=%d\n", 518 dataphys, dataphysend, 519 len, curlen)); 520 len -= curlen; 521 522 cur->td.td_flags = tdflags; 523 cur->td.td_cbp = HTOO32(dataphys); 524 cur->nexttd = next; 525 cur->td.td_nexttd = HTOO32(next->physaddr); 526 cur->td.td_be = HTOO32(dataphys + curlen - 1); 527 cur->len = curlen; 528 cur->flags = OHCI_ADD_LEN; 529 cur->xfer = xfer; 530 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 533 dataphys, dataphys + curlen - 1)); 534 if (len == 0) 535 break; 536 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 537 dataphys += curlen; 538 cur = next; 539 } 540 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 541 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 542 /* Force a 0 length transfer at the end. */ 543 544 cur = next; 545 next = ohci_alloc_std(sc); 546 if (next == NULL) 547 goto nomem; 548 549 cur->td.td_flags = tdflags; 550 cur->td.td_cbp = 0; /* indicate 0 length packet */ 551 cur->nexttd = next; 552 cur->td.td_nexttd = HTOO32(next->physaddr); 553 cur->td.td_be = ~0; 554 cur->len = 0; 555 cur->flags = 0; 556 cur->xfer = xfer; 557 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 558 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 559 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 560 } 561 *ep = cur; 562 563 return (USBD_NORMAL_COMPLETION); 564 565 nomem: 566 567 /* Don't free sp - let the caller do that */ 568 ohci_free_std_chain(sc, sp->nexttd, NULL); 569 570 return (USBD_NOMEM); 571 } 572 573 Static void 574 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 575 ohci_soft_td_t *stdend) 576 { 577 ohci_soft_td_t *p; 578 579 for (; std != stdend; std = p) { 580 p = std->nexttd; 581 ohci_free_std(sc, std); 582 } 583 } 584 585 ohci_soft_itd_t * 586 ohci_alloc_sitd(ohci_softc_t *sc) 587 { 588 ohci_soft_itd_t *sitd; 589 usbd_status err; 590 int i, offs; 591 usb_dma_t dma; 592 593 if (sc->sc_freeitds == NULL) { 594 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 595 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 596 OHCI_ITD_ALIGN, &dma); 597 if (err) 598 return (NULL); 599 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 600 offs = i * OHCI_SITD_SIZE; 601 sitd = KERNADDR(&dma, offs); 602 sitd->physaddr = DMAADDR(&dma, offs); 603 sitd->dma = dma; 604 sitd->offs = offs; 605 sitd->nextitd = sc->sc_freeitds; 606 sc->sc_freeitds = sitd; 607 } 608 } 609 610 sitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd->nextitd; 612 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 613 sitd->nextitd = NULL; 614 sitd->xfer = NULL; 615 ohci_hash_add_itd(sc, sitd); 616 617 #ifdef DIAGNOSTIC 618 sitd->isdone = 0; 619 #endif 620 621 return (sitd); 622 } 623 624 void 625 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 626 { 627 628 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 629 630 #ifdef DIAGNOSTIC 631 if (!sitd->isdone) { 632 panic("ohci_free_sitd: sitd=%p not done", sitd); 633 return; 634 } 635 /* Warn double free */ 636 sitd->isdone = 0; 637 #endif 638 639 ohci_hash_rem_itd(sc, sitd); 640 sitd->nextitd = sc->sc_freeitds; 641 sc->sc_freeitds = sitd; 642 } 643 644 usbd_status 645 ohci_init(ohci_softc_t *sc) 646 { 647 ohci_soft_ed_t *sed, *psed; 648 usbd_status err; 649 int i; 650 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca, descb; 651 652 DPRINTF(("ohci_init: start\n")); 653 aprint_normal_dev(sc->sc_dev, ""); 654 655 sc->sc_hcca = NULL; 656 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 657 658 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 659 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 660 cv_init(&sc->sc_softwake_cv, "ohciab"); 661 662 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 663 ohci_rhsc_softint, sc); 664 665 for (i = 0; i < OHCI_HASH_SIZE; i++) 666 LIST_INIT(&sc->sc_hash_tds[i]); 667 for (i = 0; i < OHCI_HASH_SIZE; i++) 668 LIST_INIT(&sc->sc_hash_itds[i]); 669 670 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 671 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 672 673 rev = OREAD4(sc, OHCI_REVISION); 674 aprint_normal("OHCI version %d.%d%s\n", 675 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 676 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 677 678 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 679 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 680 sc->sc_bus.usbrev = USBREV_UNKNOWN; 681 return (USBD_INVAL); 682 } 683 sc->sc_bus.usbrev = USBREV_1_0; 684 685 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 686 USB_MEM_RESERVE); 687 688 /* XXX determine alignment by R/W */ 689 /* Allocate the HCCA area. */ 690 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 691 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 692 if (err) { 693 sc->sc_hcca = NULL; 694 return err; 695 } 696 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 697 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 698 699 sc->sc_eintrs = OHCI_NORMAL_INTRS; 700 701 /* Allocate dummy ED that starts the control list. */ 702 sc->sc_ctrl_head = ohci_alloc_sed(sc); 703 if (sc->sc_ctrl_head == NULL) { 704 err = USBD_NOMEM; 705 goto bad1; 706 } 707 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 708 709 /* Allocate dummy ED that starts the bulk list. */ 710 sc->sc_bulk_head = ohci_alloc_sed(sc); 711 if (sc->sc_bulk_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad2; 714 } 715 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 717 sizeof(sc->sc_bulk_head->ed), 718 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 719 720 /* Allocate dummy ED that starts the isochronous list. */ 721 sc->sc_isoc_head = ohci_alloc_sed(sc); 722 if (sc->sc_isoc_head == NULL) { 723 err = USBD_NOMEM; 724 goto bad3; 725 } 726 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 727 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 728 sizeof(sc->sc_isoc_head->ed), 729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 730 731 /* Allocate all the dummy EDs that make up the interrupt tree. */ 732 for (i = 0; i < OHCI_NO_EDS; i++) { 733 sed = ohci_alloc_sed(sc); 734 if (sed == NULL) { 735 while (--i >= 0) 736 ohci_free_sed(sc, sc->sc_eds[i]); 737 err = USBD_NOMEM; 738 goto bad4; 739 } 740 /* All ED fields are set to 0. */ 741 sc->sc_eds[i] = sed; 742 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 743 if (i != 0) 744 psed = sc->sc_eds[(i-1) / 2]; 745 else 746 psed= sc->sc_isoc_head; 747 sed->next = psed; 748 sed->ed.ed_nexted = HTOO32(psed->physaddr); 749 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 751 } 752 /* 753 * Fill HCCA interrupt table. The bit reversal is to get 754 * the tree set up properly to spread the interrupts. 755 */ 756 for (i = 0; i < OHCI_NO_INTRS; i++) 757 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 758 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 759 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 761 762 #ifdef OHCI_DEBUG 763 if (ohcidebug > 15) { 764 for (i = 0; i < OHCI_NO_EDS; i++) { 765 printf("ed#%d ", i); 766 ohci_dump_ed(sc, sc->sc_eds[i]); 767 } 768 printf("iso "); 769 ohci_dump_ed(sc, sc->sc_isoc_head); 770 } 771 #endif 772 773 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 774 ctl = OREAD4(sc, OHCI_CONTROL); 775 rwc = ctl & OHCI_RWC; 776 fm = OREAD4(sc, OHCI_FM_INTERVAL); 777 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 778 descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 779 780 /* Determine in what context we are running. */ 781 if (ctl & OHCI_IR) { 782 /* SMM active, request change */ 783 DPRINTF(("ohci_init: SMM active, request owner change\n")); 784 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 785 (OHCI_OC | OHCI_MIE)) 786 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 787 s = OREAD4(sc, OHCI_COMMAND_STATUS); 788 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 789 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 790 usb_delay_ms(&sc->sc_bus, 1); 791 ctl = OREAD4(sc, OHCI_CONTROL); 792 } 793 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 794 if ((ctl & OHCI_IR) == 0) { 795 aprint_error_dev(sc->sc_dev, 796 "SMM does not respond, resetting\n"); 797 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 798 goto reset; 799 } 800 #if 0 801 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 802 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 803 /* BIOS started controller. */ 804 DPRINTF(("ohci_init: BIOS active\n")); 805 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 806 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 807 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 808 } 809 #endif 810 } else { 811 DPRINTF(("ohci_init: cold started\n")); 812 reset: 813 /* Controller was cold started. */ 814 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 815 } 816 817 /* 818 * This reset should not be necessary according to the OHCI spec, but 819 * without it some controllers do not start. 820 */ 821 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 822 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 823 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 824 825 /* We now own the host controller and the bus has been reset. */ 826 827 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 828 /* Nominal time for a reset is 10 us. */ 829 for (i = 0; i < 10; i++) { 830 delay(10); 831 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 832 if (!hcr) 833 break; 834 } 835 if (hcr) { 836 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 837 err = USBD_IOERROR; 838 goto bad5; 839 } 840 #ifdef OHCI_DEBUG 841 if (ohcidebug > 15) 842 ohci_dumpregs(sc); 843 #endif 844 845 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 846 847 /* Set up HC registers. */ 848 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 849 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 850 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 851 /* disable all interrupts and then switch on all desired interrupts */ 852 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 853 /* switch on desired functional features */ 854 ctl = OREAD4(sc, OHCI_CONTROL); 855 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 856 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 857 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 858 /* And finally start it! */ 859 OWRITE4(sc, OHCI_CONTROL, ctl); 860 861 /* 862 * The controller is now OPERATIONAL. Set a some final 863 * registers that should be set earlier, but that the 864 * controller ignores when in the SUSPEND state. 865 */ 866 ival = OHCI_GET_IVAL(fm); 867 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 868 fm |= OHCI_FSMPS(ival) | ival; 869 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 870 per = OHCI_PERIODIC(ival); /* 90% periodic */ 871 OWRITE4(sc, OHCI_PERIODIC_START, per); 872 873 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 874 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 875 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 876 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 877 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 878 879 /* 880 * The AMD756 requires a delay before re-reading the register, 881 * otherwise it will occasionally report 0 ports. 882 */ 883 sc->sc_noport = 0; 884 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 885 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 886 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 887 } 888 889 #ifdef OHCI_DEBUG 890 if (ohcidebug > 5) 891 ohci_dumpregs(sc); 892 #endif 893 894 /* Set up the bus struct. */ 895 sc->sc_bus.methods = &ohci_bus_methods; 896 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 897 898 sc->sc_control = sc->sc_intre = 0; 899 900 /* Finally, turn on interrupts. */ 901 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 902 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 903 904 return (USBD_NORMAL_COMPLETION); 905 906 bad5: 907 for (i = 0; i < OHCI_NO_EDS; i++) 908 ohci_free_sed(sc, sc->sc_eds[i]); 909 bad4: 910 ohci_free_sed(sc, sc->sc_isoc_head); 911 bad3: 912 ohci_free_sed(sc, sc->sc_bulk_head); 913 bad2: 914 ohci_free_sed(sc, sc->sc_ctrl_head); 915 bad1: 916 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 917 sc->sc_hcca = NULL; 918 return (err); 919 } 920 921 usbd_status 922 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 923 { 924 struct ohci_softc *sc = bus->hci_private; 925 usbd_status status; 926 927 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 928 if (status == USBD_NOMEM) 929 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 930 return status; 931 } 932 933 void 934 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 935 { 936 struct ohci_softc *sc = bus->hci_private; 937 if (dma->block->flags & USB_DMA_RESERVE) { 938 usb_reserve_freem(&sc->sc_dma_reserve, dma); 939 return; 940 } 941 usb_freemem(&sc->sc_bus, dma); 942 } 943 944 usbd_xfer_handle 945 ohci_allocx(struct usbd_bus *bus) 946 { 947 struct ohci_softc *sc = bus->hci_private; 948 usbd_xfer_handle xfer; 949 950 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 951 if (xfer != NULL) { 952 memset(xfer, 0, sizeof(struct ohci_xfer)); 953 #ifdef DIAGNOSTIC 954 xfer->busy_free = XFER_BUSY; 955 #endif 956 } 957 return (xfer); 958 } 959 960 void 961 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 962 { 963 struct ohci_softc *sc = bus->hci_private; 964 965 #ifdef DIAGNOSTIC 966 if (xfer->busy_free != XFER_BUSY) { 967 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 968 xfer->busy_free); 969 } 970 xfer->busy_free = XFER_FREE; 971 #endif 972 pool_cache_put(sc->sc_xferpool, xfer); 973 } 974 975 Static void 976 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 977 { 978 struct ohci_softc *sc = bus->hci_private; 979 980 *lock = &sc->sc_lock; 981 } 982 983 /* 984 * Shut down the controller when the system is going down. 985 */ 986 bool 987 ohci_shutdown(device_t self, int flags) 988 { 989 ohci_softc_t *sc = device_private(self); 990 991 DPRINTF(("ohci_shutdown: stopping the HC\n")); 992 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 993 return true; 994 } 995 996 bool 997 ohci_resume(device_t dv, const pmf_qual_t *qual) 998 { 999 ohci_softc_t *sc = device_private(dv); 1000 uint32_t ctl; 1001 1002 mutex_spin_enter(&sc->sc_intr_lock); 1003 sc->sc_bus.use_polling++; 1004 mutex_spin_exit(&sc->sc_intr_lock); 1005 1006 /* Some broken BIOSes do not recover these values */ 1007 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1008 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1009 sc->sc_ctrl_head->physaddr); 1010 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1011 sc->sc_bulk_head->physaddr); 1012 if (sc->sc_intre) 1013 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1014 (OHCI_ALL_INTRS | OHCI_MIE)); 1015 if (sc->sc_control) 1016 ctl = sc->sc_control; 1017 else 1018 ctl = OREAD4(sc, OHCI_CONTROL); 1019 ctl |= OHCI_HCFS_RESUME; 1020 OWRITE4(sc, OHCI_CONTROL, ctl); 1021 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1022 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1025 sc->sc_control = sc->sc_intre = 0; 1026 1027 mutex_spin_enter(&sc->sc_intr_lock); 1028 sc->sc_bus.use_polling--; 1029 mutex_spin_exit(&sc->sc_intr_lock); 1030 1031 return true; 1032 } 1033 1034 bool 1035 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1036 { 1037 ohci_softc_t *sc = device_private(dv); 1038 uint32_t ctl; 1039 1040 mutex_spin_enter(&sc->sc_intr_lock); 1041 sc->sc_bus.use_polling++; 1042 mutex_spin_exit(&sc->sc_intr_lock); 1043 1044 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1045 if (sc->sc_control == 0) { 1046 /* 1047 * Preserve register values, in case that BIOS 1048 * does not recover them. 1049 */ 1050 sc->sc_control = ctl; 1051 sc->sc_intre = OREAD4(sc, 1052 OHCI_INTERRUPT_ENABLE); 1053 } 1054 ctl |= OHCI_HCFS_SUSPEND; 1055 OWRITE4(sc, OHCI_CONTROL, ctl); 1056 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1057 1058 mutex_spin_enter(&sc->sc_intr_lock); 1059 sc->sc_bus.use_polling--; 1060 mutex_spin_exit(&sc->sc_intr_lock); 1061 1062 return true; 1063 } 1064 1065 #ifdef OHCI_DEBUG 1066 void 1067 ohci_dumpregs(ohci_softc_t *sc) 1068 { 1069 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1070 OREAD4(sc, OHCI_REVISION), 1071 OREAD4(sc, OHCI_CONTROL), 1072 OREAD4(sc, OHCI_COMMAND_STATUS))); 1073 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1074 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1075 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1076 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1077 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1078 OREAD4(sc, OHCI_HCCA), 1079 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1080 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1081 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1082 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1083 OREAD4(sc, OHCI_BULK_HEAD_ED), 1084 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1085 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1086 OREAD4(sc, OHCI_DONE_HEAD), 1087 OREAD4(sc, OHCI_FM_INTERVAL), 1088 OREAD4(sc, OHCI_FM_REMAINING))); 1089 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1090 OREAD4(sc, OHCI_FM_NUMBER), 1091 OREAD4(sc, OHCI_PERIODIC_START), 1092 OREAD4(sc, OHCI_LS_THRESHOLD))); 1093 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1094 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1095 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1096 OREAD4(sc, OHCI_RH_STATUS))); 1097 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1098 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1099 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1100 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1101 O32TOH(sc->sc_hcca->hcca_frame_number), 1102 O32TOH(sc->sc_hcca->hcca_done_head))); 1103 } 1104 #endif 1105 1106 Static int ohci_intr1(ohci_softc_t *); 1107 1108 int 1109 ohci_intr(void *p) 1110 { 1111 ohci_softc_t *sc = p; 1112 int ret = 0; 1113 1114 if (sc == NULL) 1115 return (0); 1116 1117 mutex_spin_enter(&sc->sc_intr_lock); 1118 1119 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1120 goto done; 1121 1122 /* If we get an interrupt while polling, then just ignore it. */ 1123 if (sc->sc_bus.use_polling) { 1124 #ifdef DIAGNOSTIC 1125 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1126 #endif 1127 /* for level triggered intrs, should do something to ack */ 1128 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1129 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1130 1131 goto done; 1132 } 1133 1134 ret = ohci_intr1(sc); 1135 1136 done: 1137 mutex_spin_exit(&sc->sc_intr_lock); 1138 return ret; 1139 } 1140 1141 Static int 1142 ohci_intr1(ohci_softc_t *sc) 1143 { 1144 u_int32_t intrs, eintrs; 1145 1146 DPRINTFN(14,("ohci_intr1: enter\n")); 1147 1148 /* In case the interrupt occurs before initialization has completed. */ 1149 if (sc == NULL || sc->sc_hcca == NULL) { 1150 #ifdef DIAGNOSTIC 1151 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1152 #endif 1153 return (0); 1154 } 1155 1156 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1157 1158 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1159 if (!intrs) 1160 return (0); 1161 1162 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1163 eintrs = intrs & sc->sc_eintrs; 1164 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1165 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1166 (u_int)eintrs, sc->sc_eintrs)); 1167 1168 if (!eintrs) { 1169 return (0); 1170 } 1171 1172 sc->sc_bus.no_intrs++; 1173 if (eintrs & OHCI_SO) { 1174 sc->sc_overrun_cnt++; 1175 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1176 printf("%s: %u scheduling overruns\n", 1177 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1178 sc->sc_overrun_cnt = 0; 1179 } 1180 /* XXX do what */ 1181 eintrs &= ~OHCI_SO; 1182 } 1183 if (eintrs & OHCI_WDH) { 1184 /* 1185 * We block the interrupt below, and reenable it later from 1186 * ohci_softintr(). 1187 */ 1188 usb_schedsoftintr(&sc->sc_bus); 1189 } 1190 if (eintrs & OHCI_RD) { 1191 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1192 /* XXX process resume detect */ 1193 } 1194 if (eintrs & OHCI_UE) { 1195 printf("%s: unrecoverable error, controller halted\n", 1196 device_xname(sc->sc_dev)); 1197 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1198 /* XXX what else */ 1199 } 1200 if (eintrs & OHCI_RHSC) { 1201 /* 1202 * We block the interrupt below, and reenable it later from 1203 * a timeout. 1204 */ 1205 softint_schedule(sc->sc_rhsc_si); 1206 } 1207 1208 if (eintrs != 0) { 1209 /* Block unprocessed interrupts. */ 1210 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1211 sc->sc_eintrs &= ~eintrs; 1212 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1213 device_xname(sc->sc_dev), eintrs)); 1214 } 1215 1216 return (1); 1217 } 1218 1219 void 1220 ohci_rhsc_enable(void *v_sc) 1221 { 1222 ohci_softc_t *sc = v_sc; 1223 1224 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1225 mutex_spin_enter(&sc->sc_intr_lock); 1226 sc->sc_eintrs |= OHCI_RHSC; 1227 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1228 mutex_spin_exit(&sc->sc_intr_lock); 1229 } 1230 1231 #ifdef OHCI_DEBUG 1232 const char *ohci_cc_strs[] = { 1233 "NO_ERROR", 1234 "CRC", 1235 "BIT_STUFFING", 1236 "DATA_TOGGLE_MISMATCH", 1237 "STALL", 1238 "DEVICE_NOT_RESPONDING", 1239 "PID_CHECK_FAILURE", 1240 "UNEXPECTED_PID", 1241 "DATA_OVERRUN", 1242 "DATA_UNDERRUN", 1243 "BUFFER_OVERRUN", 1244 "BUFFER_UNDERRUN", 1245 "reserved", 1246 "reserved", 1247 "NOT_ACCESSED", 1248 "NOT_ACCESSED", 1249 }; 1250 #endif 1251 1252 void 1253 ohci_softintr(void *v) 1254 { 1255 struct usbd_bus *bus = v; 1256 ohci_softc_t *sc = bus->hci_private; 1257 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1258 ohci_soft_td_t *std, *sdone, *stdnext; 1259 usbd_xfer_handle xfer; 1260 struct ohci_pipe *opipe; 1261 int len, cc; 1262 int i, j, actlen, iframes, uedir; 1263 ohci_physaddr_t done; 1264 1265 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1266 1267 DPRINTFN(10,("ohci_softintr: enter\n")); 1268 1269 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1270 sizeof(sc->sc_hcca->hcca_done_head), 1271 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1272 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1273 sc->sc_hcca->hcca_done_head = 0; 1274 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1275 sizeof(sc->sc_hcca->hcca_done_head), 1276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1277 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1278 sc->sc_eintrs |= OHCI_WDH; 1279 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1280 1281 /* Reverse the done list. */ 1282 for (sdone = NULL, sidone = NULL; done != 0; ) { 1283 std = ohci_hash_find_td(sc, done); 1284 if (std != NULL) { 1285 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1286 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1287 std->dnext = sdone; 1288 done = O32TOH(std->td.td_nexttd); 1289 sdone = std; 1290 DPRINTFN(10,("add TD %p\n", std)); 1291 continue; 1292 } 1293 sitd = ohci_hash_find_itd(sc, done); 1294 if (sitd != NULL) { 1295 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1296 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1297 sitd->dnext = sidone; 1298 done = O32TOH(sitd->itd.itd_nextitd); 1299 sidone = sitd; 1300 DPRINTFN(5,("add ITD %p\n", sitd)); 1301 continue; 1302 } 1303 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1304 (u_long)done); 1305 break; 1306 } 1307 1308 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1309 1310 #ifdef OHCI_DEBUG 1311 if (ohcidebug > 10) { 1312 DPRINTF(("ohci_process_done: TD done:\n")); 1313 for (std = sdone; std; std = std->dnext) 1314 ohci_dump_td(sc, std); 1315 } 1316 #endif 1317 1318 for (std = sdone; std; std = stdnext) { 1319 xfer = std->xfer; 1320 stdnext = std->dnext; 1321 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1322 std, xfer, xfer ? xfer->hcpriv : 0)); 1323 if (xfer == NULL) { 1324 /* 1325 * xfer == NULL: There seems to be no xfer associated 1326 * with this TD. It is tailp that happened to end up on 1327 * the done queue. 1328 * Shouldn't happen, but some chips are broken(?). 1329 */ 1330 continue; 1331 } 1332 if (xfer->status == USBD_CANCELLED || 1333 xfer->status == USBD_TIMEOUT) { 1334 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1335 xfer)); 1336 /* Handled by abort routine. */ 1337 continue; 1338 } 1339 callout_stop(&xfer->timeout_handle); 1340 1341 len = std->len; 1342 if (std->td.td_cbp != 0) 1343 len -= O32TOH(std->td.td_be) - 1344 O32TOH(std->td.td_cbp) + 1; 1345 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1346 std->flags)); 1347 if (std->flags & OHCI_ADD_LEN) 1348 xfer->actlen += len; 1349 1350 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1351 if (cc == OHCI_CC_NO_ERROR) { 1352 if (std->flags & OHCI_CALL_DONE) { 1353 xfer->status = USBD_NORMAL_COMPLETION; 1354 usb_transfer_complete(xfer); 1355 } 1356 ohci_free_std(sc, std); 1357 } else { 1358 /* 1359 * Endpoint is halted. First unlink all the TDs 1360 * belonging to the failed transfer, and then restart 1361 * the endpoint. 1362 */ 1363 ohci_soft_td_t *p, *n; 1364 opipe = (struct ohci_pipe *)xfer->pipe; 1365 1366 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1367 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1368 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1369 1370 /* remove TDs */ 1371 for (p = std; p->xfer == xfer; p = n) { 1372 n = p->nexttd; 1373 ohci_free_std(sc, p); 1374 } 1375 1376 /* clear halt */ 1377 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1378 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1379 1380 if (cc == OHCI_CC_STALL) 1381 xfer->status = USBD_STALLED; 1382 else 1383 xfer->status = USBD_IOERROR; 1384 usb_transfer_complete(xfer); 1385 } 1386 } 1387 1388 #ifdef OHCI_DEBUG 1389 if (ohcidebug > 10) { 1390 DPRINTF(("ohci_softintr: ITD done:\n")); 1391 for (sitd = sidone; sitd; sitd = sitd->dnext) 1392 ohci_dump_itd(sc, sitd); 1393 } 1394 #endif 1395 1396 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1397 xfer = sitd->xfer; 1398 sitdnext = sitd->dnext; 1399 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1400 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1401 if (xfer == NULL) 1402 continue; 1403 if (xfer->status == USBD_CANCELLED || 1404 xfer->status == USBD_TIMEOUT) { 1405 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1406 xfer)); 1407 /* Handled by abort routine. */ 1408 continue; 1409 } 1410 #ifdef DIAGNOSTIC 1411 if (sitd->isdone) 1412 printf("ohci_softintr: sitd=%p is done\n", sitd); 1413 sitd->isdone = 1; 1414 #endif 1415 if (sitd->flags & OHCI_CALL_DONE) { 1416 ohci_soft_itd_t *next; 1417 1418 opipe = (struct ohci_pipe *)xfer->pipe; 1419 opipe->u.iso.inuse -= xfer->nframes; 1420 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1421 bEndpointAddress); 1422 xfer->status = USBD_NORMAL_COMPLETION; 1423 actlen = 0; 1424 for (i = 0, sitd = xfer->hcpriv;; 1425 sitd = next) { 1426 next = sitd->nextitd; 1427 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1428 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1429 xfer->status = USBD_IOERROR; 1430 /* For input, update frlengths with actual */ 1431 /* XXX anything necessary for output? */ 1432 if (uedir == UE_DIR_IN && 1433 xfer->status == USBD_NORMAL_COMPLETION) { 1434 iframes = OHCI_ITD_GET_FC(O32TOH( 1435 sitd->itd.itd_flags)); 1436 for (j = 0; j < iframes; i++, j++) { 1437 len = O16TOH(sitd-> 1438 itd.itd_offset[j]); 1439 if ((OHCI_ITD_PSW_GET_CC(len) & 1440 OHCI_CC_NOT_ACCESSED_MASK) 1441 == OHCI_CC_NOT_ACCESSED) 1442 len = 0; 1443 else 1444 len = OHCI_ITD_PSW_LENGTH(len); 1445 xfer->frlengths[i] = len; 1446 actlen += len; 1447 } 1448 } 1449 if (sitd->flags & OHCI_CALL_DONE) 1450 break; 1451 ohci_free_sitd(sc, sitd); 1452 } 1453 ohci_free_sitd(sc, sitd); 1454 if (uedir == UE_DIR_IN && 1455 xfer->status == USBD_NORMAL_COMPLETION) 1456 xfer->actlen = actlen; 1457 xfer->hcpriv = NULL; 1458 1459 usb_transfer_complete(xfer); 1460 } 1461 } 1462 1463 if (sc->sc_softwake) { 1464 sc->sc_softwake = 0; 1465 cv_broadcast(&sc->sc_softwake_cv); 1466 } 1467 1468 DPRINTFN(10,("ohci_softintr: done:\n")); 1469 } 1470 1471 void 1472 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1473 { 1474 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1475 #ifdef DIAGNOSTIC 1476 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1477 #endif 1478 int len = UGETW(xfer->request.wLength); 1479 int isread = (xfer->request.bmRequestType & UT_READ); 1480 1481 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1482 1483 KASSERT(mutex_owned(&sc->sc_lock)); 1484 1485 #ifdef DIAGNOSTIC 1486 if (!(xfer->rqflags & URQ_REQUEST)) { 1487 panic("ohci_device_ctrl_done: not a request"); 1488 } 1489 #endif 1490 if (len) 1491 usb_syncmem(&xfer->dmabuf, 0, len, 1492 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1493 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1494 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1495 } 1496 1497 void 1498 ohci_device_intr_done(usbd_xfer_handle xfer) 1499 { 1500 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1501 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1502 ohci_soft_ed_t *sed = opipe->sed; 1503 ohci_soft_td_t *data, *tail; 1504 int isread = 1505 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1506 1507 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1508 xfer, xfer->actlen)); 1509 1510 KASSERT(mutex_owned(&sc->sc_lock)); 1511 1512 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1513 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1514 if (xfer->pipe->repeat) { 1515 data = opipe->tail.td; 1516 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1517 if (tail == NULL) { 1518 xfer->status = USBD_NOMEM; 1519 return; 1520 } 1521 tail->xfer = NULL; 1522 1523 data->td.td_flags = HTOO32( 1524 OHCI_TD_IN | OHCI_TD_NOCC | 1525 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1526 if (xfer->flags & USBD_SHORT_XFER_OK) 1527 data->td.td_flags |= HTOO32(OHCI_TD_R); 1528 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1529 data->nexttd = tail; 1530 data->td.td_nexttd = HTOO32(tail->physaddr); 1531 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1532 xfer->length - 1); 1533 data->len = xfer->length; 1534 data->xfer = xfer; 1535 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1536 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1538 xfer->hcpriv = data; 1539 xfer->actlen = 0; 1540 1541 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1542 usb_syncmem(&sed->dma, 1543 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1544 sizeof(sed->ed.ed_tailp), 1545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1546 opipe->tail.td = tail; 1547 } 1548 } 1549 1550 void 1551 ohci_device_bulk_done(usbd_xfer_handle xfer) 1552 { 1553 #ifdef DIAGNOSTIC 1554 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1555 #endif 1556 int isread = 1557 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1558 1559 KASSERT(mutex_owned(&sc->sc_lock)); 1560 1561 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1562 xfer, xfer->actlen)); 1563 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1564 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1565 } 1566 1567 Static void 1568 ohci_rhsc_softint(void *arg) 1569 { 1570 ohci_softc_t *sc = arg; 1571 1572 mutex_enter(&sc->sc_lock); 1573 1574 ohci_rhsc(sc, sc->sc_intrxfer); 1575 1576 /* Do not allow RHSC interrupts > 1 per second */ 1577 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1578 1579 mutex_exit(&sc->sc_lock); 1580 } 1581 1582 void 1583 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1584 { 1585 usbd_pipe_handle pipe; 1586 u_char *p; 1587 int i, m; 1588 int hstatus; 1589 1590 KASSERT(mutex_owned(&sc->sc_lock)); 1591 1592 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1593 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1594 sc, xfer, hstatus)); 1595 1596 if (xfer == NULL) { 1597 /* Just ignore the change. */ 1598 return; 1599 } 1600 1601 pipe = xfer->pipe; 1602 1603 p = KERNADDR(&xfer->dmabuf, 0); 1604 m = min(sc->sc_noport, xfer->length * 8 - 1); 1605 memset(p, 0, xfer->length); 1606 for (i = 1; i <= m; i++) { 1607 /* Pick out CHANGE bits from the status reg. */ 1608 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1609 p[i/8] |= 1 << (i%8); 1610 } 1611 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1612 xfer->actlen = xfer->length; 1613 xfer->status = USBD_NORMAL_COMPLETION; 1614 1615 usb_transfer_complete(xfer); 1616 } 1617 1618 void 1619 ohci_root_intr_done(usbd_xfer_handle xfer) 1620 { 1621 } 1622 1623 void 1624 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1625 { 1626 } 1627 1628 /* 1629 * Wait here until controller claims to have an interrupt. 1630 * Then call ohci_intr and return. Use timeout to avoid waiting 1631 * too long. 1632 */ 1633 void 1634 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1635 { 1636 int timo; 1637 u_int32_t intrs; 1638 1639 mutex_enter(&sc->sc_lock); 1640 1641 xfer->status = USBD_IN_PROGRESS; 1642 for (timo = xfer->timeout; timo >= 0; timo--) { 1643 usb_delay_ms(&sc->sc_bus, 1); 1644 if (sc->sc_dying) 1645 break; 1646 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1647 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1648 #ifdef OHCI_DEBUG 1649 if (ohcidebug > 15) 1650 ohci_dumpregs(sc); 1651 #endif 1652 if (intrs) { 1653 mutex_spin_enter(&sc->sc_intr_lock); 1654 ohci_intr1(sc); 1655 mutex_spin_exit(&sc->sc_intr_lock); 1656 if (xfer->status != USBD_IN_PROGRESS) 1657 goto done; 1658 } 1659 } 1660 1661 /* Timeout */ 1662 DPRINTF(("ohci_waitintr: timeout\n")); 1663 xfer->status = USBD_TIMEOUT; 1664 usb_transfer_complete(xfer); 1665 1666 /* XXX should free TD */ 1667 1668 done: 1669 mutex_exit(&sc->sc_lock); 1670 } 1671 1672 void 1673 ohci_poll(struct usbd_bus *bus) 1674 { 1675 ohci_softc_t *sc = bus->hci_private; 1676 #ifdef OHCI_DEBUG 1677 static int last; 1678 int new; 1679 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1680 if (new != last) { 1681 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1682 last = new; 1683 } 1684 #endif 1685 mutex_enter(&sc->sc_lock); 1686 sc->sc_eintrs |= OHCI_WDH; 1687 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1688 mutex_spin_enter(&sc->sc_intr_lock); 1689 ohci_intr1(sc); 1690 mutex_spin_exit(&sc->sc_intr_lock); 1691 } 1692 mutex_exit(&sc->sc_lock); 1693 } 1694 1695 usbd_status 1696 ohci_device_request(usbd_xfer_handle xfer) 1697 { 1698 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1699 usb_device_request_t *req = &xfer->request; 1700 usbd_device_handle dev = opipe->pipe.device; 1701 ohci_softc_t *sc = dev->bus->hci_private; 1702 int addr = dev->address; 1703 ohci_soft_td_t *setup, *stat, *next, *tail; 1704 ohci_soft_ed_t *sed; 1705 int isread; 1706 int len; 1707 usbd_status err; 1708 1709 KASSERT(mutex_owned(&sc->sc_lock)); 1710 1711 isread = req->bmRequestType & UT_READ; 1712 len = UGETW(req->wLength); 1713 1714 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1715 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1716 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1717 UGETW(req->wIndex), len, addr, 1718 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1719 1720 setup = opipe->tail.td; 1721 stat = ohci_alloc_std(sc); 1722 if (stat == NULL) { 1723 err = USBD_NOMEM; 1724 goto bad1; 1725 } 1726 tail = ohci_alloc_std(sc); 1727 if (tail == NULL) { 1728 err = USBD_NOMEM; 1729 goto bad2; 1730 } 1731 tail->xfer = NULL; 1732 1733 sed = opipe->sed; 1734 opipe->u.ctl.length = len; 1735 1736 /* Update device address and length since they may have changed 1737 during the setup of the control pipe in usbd_new_device(). */ 1738 /* XXX This only needs to be done once, but it's too early in open. */ 1739 /* XXXX Should not touch ED here! */ 1740 1741 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1742 sizeof(sed->ed.ed_flags), 1743 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1744 sed->ed.ed_flags = HTOO32( 1745 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1746 OHCI_ED_SET_FA(addr) | 1747 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1748 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1749 sizeof(sed->ed.ed_flags), 1750 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1751 1752 next = stat; 1753 1754 /* Set up data transaction */ 1755 if (len != 0) { 1756 ohci_soft_td_t *std = stat; 1757 1758 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1759 std, &stat); 1760 if (err) { 1761 /* stat is unchanged if error */ 1762 goto bad3; 1763 } 1764 stat = stat->nexttd; /* point at free TD */ 1765 1766 /* Start toggle at 1 and then use the carried toggle. */ 1767 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1768 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1769 usb_syncmem(&std->dma, 1770 std->offs + offsetof(ohci_td_t, td_flags), 1771 sizeof(std->td.td_flags), 1772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1773 } 1774 1775 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1776 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1777 1778 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1779 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1780 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1781 setup->nexttd = next; 1782 setup->td.td_nexttd = HTOO32(next->physaddr); 1783 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1784 setup->len = 0; 1785 setup->xfer = xfer; 1786 setup->flags = 0; 1787 xfer->hcpriv = setup; 1788 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1789 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1790 1791 stat->td.td_flags = HTOO32( 1792 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1793 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1794 stat->td.td_cbp = 0; 1795 stat->nexttd = tail; 1796 stat->td.td_nexttd = HTOO32(tail->physaddr); 1797 stat->td.td_be = 0; 1798 stat->flags = OHCI_CALL_DONE; 1799 stat->len = 0; 1800 stat->xfer = xfer; 1801 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1802 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1803 1804 #ifdef OHCI_DEBUG 1805 if (ohcidebug > 5) { 1806 DPRINTF(("ohci_device_request:\n")); 1807 ohci_dump_ed(sc, sed); 1808 ohci_dump_tds(sc, setup); 1809 } 1810 #endif 1811 1812 /* Insert ED in schedule */ 1813 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1814 usb_syncmem(&sed->dma, 1815 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1816 sizeof(sed->ed.ed_tailp), 1817 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1818 opipe->tail.td = tail; 1819 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1820 if (xfer->timeout && !sc->sc_bus.use_polling) { 1821 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1822 ohci_timeout, xfer); 1823 } 1824 1825 #ifdef OHCI_DEBUG 1826 if (ohcidebug > 20) { 1827 delay(10000); 1828 DPRINTF(("ohci_device_request: status=%x\n", 1829 OREAD4(sc, OHCI_COMMAND_STATUS))); 1830 ohci_dumpregs(sc); 1831 printf("ctrl head:\n"); 1832 ohci_dump_ed(sc, sc->sc_ctrl_head); 1833 printf("sed:\n"); 1834 ohci_dump_ed(sc, sed); 1835 ohci_dump_tds(sc, setup); 1836 } 1837 #endif 1838 1839 return (USBD_NORMAL_COMPLETION); 1840 1841 bad3: 1842 ohci_free_std(sc, tail); 1843 bad2: 1844 ohci_free_std(sc, stat); 1845 bad1: 1846 return (err); 1847 } 1848 1849 /* 1850 * Add an ED to the schedule. Called with USB lock held. 1851 */ 1852 Static void 1853 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1854 { 1855 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1856 1857 KASSERT(mutex_owned(&sc->sc_lock)); 1858 1859 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1860 sizeof(head->ed.ed_nexted), 1861 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1862 sed->next = head->next; 1863 sed->ed.ed_nexted = head->ed.ed_nexted; 1864 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1865 sizeof(sed->ed.ed_nexted), 1866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1867 head->next = sed; 1868 head->ed.ed_nexted = HTOO32(sed->physaddr); 1869 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1870 sizeof(head->ed.ed_nexted), 1871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1872 } 1873 1874 /* 1875 * Remove an ED from the schedule. Called with USB lock held. 1876 */ 1877 Static void 1878 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1879 { 1880 ohci_soft_ed_t *p; 1881 1882 KASSERT(mutex_owned(&sc->sc_lock)); 1883 1884 /* XXX */ 1885 for (p = head; p != NULL && p->next != sed; p = p->next) 1886 ; 1887 if (p == NULL) 1888 panic("ohci_rem_ed: ED not found"); 1889 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1890 sizeof(sed->ed.ed_nexted), 1891 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1892 p->next = sed->next; 1893 p->ed.ed_nexted = sed->ed.ed_nexted; 1894 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1895 sizeof(p->ed.ed_nexted), 1896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1897 } 1898 1899 /* 1900 * When a transfer is completed the TD is added to the done queue by 1901 * the host controller. This queue is the processed by software. 1902 * Unfortunately the queue contains the physical address of the TD 1903 * and we have no simple way to translate this back to a kernel address. 1904 * To make the translation possible (and fast) we use a hash table of 1905 * TDs currently in the schedule. The physical address is used as the 1906 * hash value. 1907 */ 1908 1909 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1910 /* Called with USB lock held. */ 1911 void 1912 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1913 { 1914 int h = HASH(std->physaddr); 1915 1916 KASSERT(mutex_owned(&sc->sc_lock)); 1917 1918 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1919 } 1920 1921 /* Called with USB lock held. */ 1922 void 1923 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1924 { 1925 1926 KASSERT(mutex_owned(&sc->sc_lock)); 1927 1928 LIST_REMOVE(std, hnext); 1929 } 1930 1931 ohci_soft_td_t * 1932 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1933 { 1934 int h = HASH(a); 1935 ohci_soft_td_t *std; 1936 1937 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1938 std != NULL; 1939 std = LIST_NEXT(std, hnext)) 1940 if (std->physaddr == a) 1941 return (std); 1942 return (NULL); 1943 } 1944 1945 /* Called with USB lock held. */ 1946 void 1947 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1948 { 1949 int h = HASH(sitd->physaddr); 1950 1951 KASSERT(mutex_owned(&sc->sc_lock)); 1952 1953 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1954 sitd, (u_long)sitd->physaddr)); 1955 1956 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1957 } 1958 1959 /* Called with USB lock held. */ 1960 void 1961 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1962 { 1963 1964 KASSERT(mutex_owned(&sc->sc_lock)); 1965 1966 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1967 sitd, (u_long)sitd->physaddr)); 1968 1969 LIST_REMOVE(sitd, hnext); 1970 } 1971 1972 ohci_soft_itd_t * 1973 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1974 { 1975 int h = HASH(a); 1976 ohci_soft_itd_t *sitd; 1977 1978 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1979 sitd != NULL; 1980 sitd = LIST_NEXT(sitd, hnext)) 1981 if (sitd->physaddr == a) 1982 return (sitd); 1983 return (NULL); 1984 } 1985 1986 void 1987 ohci_timeout(void *addr) 1988 { 1989 struct ohci_xfer *oxfer = addr; 1990 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1991 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1992 1993 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1994 1995 if (sc->sc_dying) { 1996 mutex_enter(&sc->sc_lock); 1997 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1998 mutex_exit(&sc->sc_lock); 1999 return; 2000 } 2001 2002 /* Execute the abort in a process context. */ 2003 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 2004 USB_TASKQ_MPSAFE); 2005 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 2006 USB_TASKQ_HC); 2007 } 2008 2009 void 2010 ohci_timeout_task(void *addr) 2011 { 2012 usbd_xfer_handle xfer = addr; 2013 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2014 2015 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2016 2017 mutex_enter(&sc->sc_lock); 2018 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2019 mutex_exit(&sc->sc_lock); 2020 } 2021 2022 #ifdef OHCI_DEBUG 2023 void 2024 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2025 { 2026 for (; std; std = std->nexttd) 2027 ohci_dump_td(sc, std); 2028 } 2029 2030 void 2031 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2032 { 2033 char sbuf[128]; 2034 2035 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2037 snprintb(sbuf, sizeof(sbuf), 2038 "\177\20" 2039 "b\22R\0" 2040 "f\23\02DP\0" 2041 "=\x0" "setup\0" 2042 "=\x1" "out\0" 2043 "=\x2" "in\0" 2044 "=\x3" "reserved\0" 2045 "f\25\03DI\0" 2046 "=\x07" "none\0" 2047 "f\30\02T\0" 2048 "=\x0" "carry\0" 2049 "=\x1" "carry\0" 2050 "=\x2" "0\0" 2051 "=\x3" "1\0" 2052 "f\32\02EC\0" 2053 "f\34\04CC\0", 2054 (u_int32_t)O32TOH(std->td.td_flags)); 2055 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2056 std, (u_long)std->physaddr, sbuf, 2057 (u_long)O32TOH(std->td.td_cbp), 2058 (u_long)O32TOH(std->td.td_nexttd), 2059 (u_long)O32TOH(std->td.td_be)); 2060 } 2061 2062 void 2063 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2064 { 2065 int i; 2066 2067 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2068 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2069 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2070 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2071 sitd, (u_long)sitd->physaddr, 2072 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2073 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2074 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2075 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2076 (u_long)O32TOH(sitd->itd.itd_bp0), 2077 (u_long)O32TOH(sitd->itd.itd_nextitd), 2078 (u_long)O32TOH(sitd->itd.itd_be)); 2079 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2080 printf("offs[%d]=0x%04x ", i, 2081 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2082 printf("\n"); 2083 } 2084 2085 void 2086 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2087 { 2088 for (; sitd; sitd = sitd->nextitd) 2089 ohci_dump_itd(sc, sitd); 2090 } 2091 2092 void 2093 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2094 { 2095 char sbuf[128], sbuf2[128]; 2096 2097 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2098 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2099 snprintb(sbuf, sizeof(sbuf), 2100 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2101 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2102 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2103 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2104 2105 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2106 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2107 sed, (u_long)sed->physaddr, 2108 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2109 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2110 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2111 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2112 (u_long)O32TOH(sed->ed.ed_headp), 2113 (u_long)O32TOH(sed->ed.ed_nexted)); 2114 } 2115 #endif 2116 2117 usbd_status 2118 ohci_open(usbd_pipe_handle pipe) 2119 { 2120 usbd_device_handle dev = pipe->device; 2121 ohci_softc_t *sc = dev->bus->hci_private; 2122 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2123 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2124 u_int8_t addr = dev->address; 2125 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2126 ohci_soft_ed_t *sed; 2127 ohci_soft_td_t *std; 2128 ohci_soft_itd_t *sitd; 2129 ohci_physaddr_t tdphys; 2130 u_int32_t fmt; 2131 usbd_status err = USBD_NOMEM; 2132 int ival; 2133 2134 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2135 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2136 2137 if (sc->sc_dying) { 2138 err = USBD_IOERROR; 2139 goto bad0; 2140 } 2141 2142 std = NULL; 2143 sed = NULL; 2144 2145 if (addr == sc->sc_addr) { 2146 switch (ed->bEndpointAddress) { 2147 case USB_CONTROL_ENDPOINT: 2148 pipe->methods = &ohci_root_ctrl_methods; 2149 break; 2150 case UE_DIR_IN | OHCI_INTR_ENDPT: 2151 pipe->methods = &ohci_root_intr_methods; 2152 break; 2153 default: 2154 err = USBD_INVAL; 2155 goto bad0; 2156 } 2157 } else { 2158 sed = ohci_alloc_sed(sc); 2159 if (sed == NULL) 2160 goto bad0; 2161 opipe->sed = sed; 2162 if (xfertype == UE_ISOCHRONOUS) { 2163 mutex_enter(&sc->sc_lock); 2164 sitd = ohci_alloc_sitd(sc); 2165 mutex_exit(&sc->sc_lock); 2166 if (sitd == NULL) 2167 goto bad1; 2168 opipe->tail.itd = sitd; 2169 tdphys = sitd->physaddr; 2170 fmt = OHCI_ED_FORMAT_ISO; 2171 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2172 fmt |= OHCI_ED_DIR_IN; 2173 else 2174 fmt |= OHCI_ED_DIR_OUT; 2175 } else { 2176 mutex_enter(&sc->sc_lock); 2177 std = ohci_alloc_std(sc); 2178 mutex_exit(&sc->sc_lock); 2179 if (std == NULL) 2180 goto bad1; 2181 opipe->tail.td = std; 2182 tdphys = std->physaddr; 2183 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2184 } 2185 sed->ed.ed_flags = HTOO32( 2186 OHCI_ED_SET_FA(addr) | 2187 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2188 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2189 fmt | 2190 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2191 sed->ed.ed_headp = HTOO32(tdphys | 2192 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2193 sed->ed.ed_tailp = HTOO32(tdphys); 2194 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2196 2197 switch (xfertype) { 2198 case UE_CONTROL: 2199 pipe->methods = &ohci_device_ctrl_methods; 2200 err = usb_allocmem(&sc->sc_bus, 2201 sizeof(usb_device_request_t), 2202 0, &opipe->u.ctl.reqdma); 2203 if (err) 2204 goto bad; 2205 mutex_enter(&sc->sc_lock); 2206 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2207 mutex_exit(&sc->sc_lock); 2208 break; 2209 case UE_INTERRUPT: 2210 pipe->methods = &ohci_device_intr_methods; 2211 ival = pipe->interval; 2212 if (ival == USBD_DEFAULT_INTERVAL) 2213 ival = ed->bInterval; 2214 err = ohci_device_setintr(sc, opipe, ival); 2215 if (err) 2216 goto bad; 2217 break; 2218 case UE_ISOCHRONOUS: 2219 pipe->methods = &ohci_device_isoc_methods; 2220 return (ohci_setup_isoc(pipe)); 2221 case UE_BULK: 2222 pipe->methods = &ohci_device_bulk_methods; 2223 mutex_enter(&sc->sc_lock); 2224 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2225 mutex_exit(&sc->sc_lock); 2226 break; 2227 } 2228 } 2229 2230 return USBD_NORMAL_COMPLETION; 2231 2232 bad: 2233 if (std != NULL) 2234 ohci_free_std(sc, std); 2235 bad1: 2236 if (sed != NULL) 2237 ohci_free_sed(sc, sed); 2238 bad0: 2239 return err; 2240 2241 } 2242 2243 /* 2244 * Close a reqular pipe. 2245 * Assumes that there are no pending transactions. 2246 */ 2247 void 2248 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2249 { 2250 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2251 ohci_softc_t *sc = pipe->device->bus->hci_private; 2252 ohci_soft_ed_t *sed = opipe->sed; 2253 2254 KASSERT(mutex_owned(&sc->sc_lock)); 2255 2256 #ifdef DIAGNOSTIC 2257 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2258 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2259 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2260 ohci_soft_td_t *std; 2261 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2262 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2263 "tl=0x%x pipe=%p, std=%p\n", sed, 2264 (int)O32TOH(sed->ed.ed_headp), 2265 (int)O32TOH(sed->ed.ed_tailp), 2266 pipe, std); 2267 #ifdef OHCI_DEBUG 2268 usbd_dump_pipe(&opipe->pipe); 2269 ohci_dump_ed(sc, sed); 2270 if (std) 2271 ohci_dump_td(sc, std); 2272 #endif 2273 usb_delay_ms(&sc->sc_bus, 2); 2274 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2275 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2276 printf("ohci_close_pipe: pipe still not empty\n"); 2277 } 2278 #endif 2279 ohci_rem_ed(sc, sed, head); 2280 /* Make sure the host controller is not touching this ED */ 2281 usb_delay_ms(&sc->sc_bus, 1); 2282 pipe->endpoint->datatoggle = 2283 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2284 ohci_free_sed(sc, opipe->sed); 2285 } 2286 2287 /* 2288 * Abort a device request. 2289 * If this routine is called at splusb() it guarantees that the request 2290 * will be removed from the hardware scheduling and that the callback 2291 * for it will be called with USBD_CANCELLED status. 2292 * It's impossible to guarantee that the requested transfer will not 2293 * have happened since the hardware runs concurrently. 2294 * If the transaction has already happened we rely on the ordinary 2295 * interrupt processing to process it. 2296 * XXX This is most probably wrong. 2297 * XXXMRG this doesn't make sense anymore. 2298 */ 2299 void 2300 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2301 { 2302 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2303 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2304 ohci_soft_ed_t *sed = opipe->sed; 2305 ohci_soft_td_t *p, *n; 2306 ohci_physaddr_t headp; 2307 int hit; 2308 int wake; 2309 2310 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2311 2312 KASSERT(mutex_owned(&sc->sc_lock)); 2313 2314 if (sc->sc_dying) { 2315 /* If we're dying, just do the software part. */ 2316 xfer->status = status; /* make software ignore it */ 2317 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2318 usb_transfer_complete(xfer); 2319 return; 2320 } 2321 2322 if (cpu_intr_p() || cpu_softintr_p()) 2323 panic("ohci_abort_xfer: not in process context"); 2324 2325 /* 2326 * If an abort is already in progress then just wait for it to 2327 * complete and return. 2328 */ 2329 if (xfer->hcflags & UXFER_ABORTING) { 2330 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2331 #ifdef DIAGNOSTIC 2332 if (status == USBD_TIMEOUT) 2333 printf("%s: TIMEOUT while aborting\n", __func__); 2334 #endif 2335 /* Override the status which might be USBD_TIMEOUT. */ 2336 xfer->status = status; 2337 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2338 xfer->hcflags |= UXFER_ABORTWAIT; 2339 while (xfer->hcflags & UXFER_ABORTING) 2340 cv_wait(&xfer->hccv, &sc->sc_lock); 2341 goto done; 2342 } 2343 xfer->hcflags |= UXFER_ABORTING; 2344 2345 /* 2346 * Step 1: Make interrupt routine and hardware ignore xfer. 2347 */ 2348 xfer->status = status; /* make software ignore it */ 2349 callout_stop(&xfer->timeout_handle); 2350 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2351 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2352 sizeof(sed->ed.ed_flags), 2353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2354 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2355 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2356 sizeof(sed->ed.ed_flags), 2357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2358 2359 /* 2360 * Step 2: Wait until we know hardware has finished any possible 2361 * use of the xfer. Also make sure the soft interrupt routine 2362 * has run. 2363 */ 2364 /* Hardware finishes in 1ms */ 2365 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2366 sc->sc_softwake = 1; 2367 usb_schedsoftintr(&sc->sc_bus); 2368 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2369 2370 /* 2371 * Step 3: Remove any vestiges of the xfer from the hardware. 2372 * The complication here is that the hardware may have executed 2373 * beyond the xfer we're trying to abort. So as we're scanning 2374 * the TDs of this xfer we check if the hardware points to 2375 * any of them. 2376 */ 2377 p = xfer->hcpriv; 2378 #ifdef DIAGNOSTIC 2379 if (p == NULL) { 2380 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2381 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2382 goto done; 2383 } 2384 #endif 2385 #ifdef OHCI_DEBUG 2386 if (ohcidebug > 1) { 2387 DPRINTF(("ohci_abort_xfer: sed=\n")); 2388 ohci_dump_ed(sc, sed); 2389 ohci_dump_tds(sc, p); 2390 } 2391 #endif 2392 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2393 hit = 0; 2394 for (; p->xfer == xfer; p = n) { 2395 hit |= headp == p->physaddr; 2396 n = p->nexttd; 2397 ohci_free_std(sc, p); 2398 } 2399 /* Zap headp register if hardware pointed inside the xfer. */ 2400 if (hit) { 2401 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2402 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2403 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2404 usb_syncmem(&sed->dma, 2405 sed->offs + offsetof(ohci_ed_t, ed_headp), 2406 sizeof(sed->ed.ed_headp), 2407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2408 } else { 2409 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2410 } 2411 2412 /* 2413 * Step 4: Turn on hardware again. 2414 */ 2415 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2416 sizeof(sed->ed.ed_flags), 2417 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2418 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2419 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2420 sizeof(sed->ed.ed_flags), 2421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2422 2423 /* 2424 * Step 5: Execute callback. 2425 */ 2426 wake = xfer->hcflags & UXFER_ABORTWAIT; 2427 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2428 usb_transfer_complete(xfer); 2429 if (wake) 2430 cv_broadcast(&xfer->hccv); 2431 2432 done: 2433 KASSERT(mutex_owned(&sc->sc_lock)); 2434 } 2435 2436 /* 2437 * Data structures and routines to emulate the root hub. 2438 */ 2439 Static usb_device_descriptor_t ohci_devd = { 2440 USB_DEVICE_DESCRIPTOR_SIZE, 2441 UDESC_DEVICE, /* type */ 2442 {0x00, 0x01}, /* USB version */ 2443 UDCLASS_HUB, /* class */ 2444 UDSUBCLASS_HUB, /* subclass */ 2445 UDPROTO_FSHUB, /* protocol */ 2446 64, /* max packet */ 2447 {0},{0},{0x00,0x01}, /* device id */ 2448 1,2,0, /* string indicies */ 2449 1 /* # of configurations */ 2450 }; 2451 2452 Static const usb_config_descriptor_t ohci_confd = { 2453 USB_CONFIG_DESCRIPTOR_SIZE, 2454 UDESC_CONFIG, 2455 {USB_CONFIG_DESCRIPTOR_SIZE + 2456 USB_INTERFACE_DESCRIPTOR_SIZE + 2457 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2458 1, 2459 1, 2460 0, 2461 UC_ATTR_MBO | UC_SELF_POWERED, 2462 0 /* max power */ 2463 }; 2464 2465 Static const usb_interface_descriptor_t ohci_ifcd = { 2466 USB_INTERFACE_DESCRIPTOR_SIZE, 2467 UDESC_INTERFACE, 2468 0, 2469 0, 2470 1, 2471 UICLASS_HUB, 2472 UISUBCLASS_HUB, 2473 UIPROTO_FSHUB, 2474 0 2475 }; 2476 2477 Static const usb_endpoint_descriptor_t ohci_endpd = { 2478 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2479 .bDescriptorType = UDESC_ENDPOINT, 2480 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2481 .bmAttributes = UE_INTERRUPT, 2482 .wMaxPacketSize = {8, 0}, /* max packet */ 2483 .bInterval = 255, 2484 }; 2485 2486 Static const usb_hub_descriptor_t ohci_hubd = { 2487 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2488 .bDescriptorType = UDESC_HUB, 2489 }; 2490 2491 /* 2492 * Simulate a hardware hub by handling all the necessary requests. 2493 */ 2494 Static usbd_status 2495 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2496 { 2497 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2498 usbd_status err; 2499 2500 /* Insert last in queue. */ 2501 mutex_enter(&sc->sc_lock); 2502 err = usb_insert_transfer(xfer); 2503 mutex_exit(&sc->sc_lock); 2504 if (err) 2505 return (err); 2506 2507 /* Pipe isn't running, start first */ 2508 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2509 } 2510 2511 Static usbd_status 2512 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2513 { 2514 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2515 usb_device_request_t *req; 2516 void *buf = NULL; 2517 int port, i; 2518 int len, value, index, l, totlen = 0; 2519 usb_port_status_t ps; 2520 usb_hub_descriptor_t hubd; 2521 usbd_status err; 2522 u_int32_t v; 2523 2524 if (sc->sc_dying) 2525 return (USBD_IOERROR); 2526 2527 #ifdef DIAGNOSTIC 2528 if (!(xfer->rqflags & URQ_REQUEST)) 2529 /* XXX panic */ 2530 return (USBD_INVAL); 2531 #endif 2532 req = &xfer->request; 2533 2534 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2535 req->bmRequestType, req->bRequest)); 2536 2537 len = UGETW(req->wLength); 2538 value = UGETW(req->wValue); 2539 index = UGETW(req->wIndex); 2540 2541 if (len != 0) 2542 buf = KERNADDR(&xfer->dmabuf, 0); 2543 2544 #define C(x,y) ((x) | ((y) << 8)) 2545 switch(C(req->bRequest, req->bmRequestType)) { 2546 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2547 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2548 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2549 /* 2550 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2551 * for the integrated root hub. 2552 */ 2553 break; 2554 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2555 if (len > 0) { 2556 *(u_int8_t *)buf = sc->sc_conf; 2557 totlen = 1; 2558 } 2559 break; 2560 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2561 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2562 if (len == 0) 2563 break; 2564 switch(value >> 8) { 2565 case UDESC_DEVICE: 2566 if ((value & 0xff) != 0) { 2567 err = USBD_IOERROR; 2568 goto ret; 2569 } 2570 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2571 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2572 memcpy(buf, &ohci_devd, l); 2573 break; 2574 case UDESC_CONFIG: 2575 if ((value & 0xff) != 0) { 2576 err = USBD_IOERROR; 2577 goto ret; 2578 } 2579 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2580 memcpy(buf, &ohci_confd, l); 2581 buf = (char *)buf + l; 2582 len -= l; 2583 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2584 totlen += l; 2585 memcpy(buf, &ohci_ifcd, l); 2586 buf = (char *)buf + l; 2587 len -= l; 2588 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2589 totlen += l; 2590 memcpy(buf, &ohci_endpd, l); 2591 break; 2592 case UDESC_STRING: 2593 #define sd ((usb_string_descriptor_t *)buf) 2594 switch (value & 0xff) { 2595 case 0: /* Language table */ 2596 totlen = usb_makelangtbl(sd, len); 2597 break; 2598 case 1: /* Vendor */ 2599 totlen = usb_makestrdesc(sd, len, 2600 sc->sc_vendor); 2601 break; 2602 case 2: /* Product */ 2603 totlen = usb_makestrdesc(sd, len, 2604 "OHCI root hub"); 2605 break; 2606 } 2607 #undef sd 2608 break; 2609 default: 2610 err = USBD_IOERROR; 2611 goto ret; 2612 } 2613 break; 2614 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2615 if (len > 0) { 2616 *(u_int8_t *)buf = 0; 2617 totlen = 1; 2618 } 2619 break; 2620 case C(UR_GET_STATUS, UT_READ_DEVICE): 2621 if (len > 1) { 2622 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2623 totlen = 2; 2624 } 2625 break; 2626 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2627 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2628 if (len > 1) { 2629 USETW(((usb_status_t *)buf)->wStatus, 0); 2630 totlen = 2; 2631 } 2632 break; 2633 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2634 if (value >= USB_MAX_DEVICES) { 2635 err = USBD_IOERROR; 2636 goto ret; 2637 } 2638 sc->sc_addr = value; 2639 break; 2640 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2641 if (value != 0 && value != 1) { 2642 err = USBD_IOERROR; 2643 goto ret; 2644 } 2645 sc->sc_conf = value; 2646 break; 2647 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2648 break; 2649 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2650 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2651 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2652 err = USBD_IOERROR; 2653 goto ret; 2654 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2655 break; 2656 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2657 break; 2658 /* Hub requests */ 2659 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2660 break; 2661 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2662 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2663 "port=%d feature=%d\n", 2664 index, value)); 2665 if (index < 1 || index > sc->sc_noport) { 2666 err = USBD_IOERROR; 2667 goto ret; 2668 } 2669 port = OHCI_RH_PORT_STATUS(index); 2670 switch(value) { 2671 case UHF_PORT_ENABLE: 2672 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2673 break; 2674 case UHF_PORT_SUSPEND: 2675 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2676 break; 2677 case UHF_PORT_POWER: 2678 /* Yes, writing to the LOW_SPEED bit clears power. */ 2679 OWRITE4(sc, port, UPS_LOW_SPEED); 2680 break; 2681 case UHF_C_PORT_CONNECTION: 2682 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2683 break; 2684 case UHF_C_PORT_ENABLE: 2685 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2686 break; 2687 case UHF_C_PORT_SUSPEND: 2688 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2689 break; 2690 case UHF_C_PORT_OVER_CURRENT: 2691 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2692 break; 2693 case UHF_C_PORT_RESET: 2694 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2695 break; 2696 default: 2697 err = USBD_IOERROR; 2698 goto ret; 2699 } 2700 switch(value) { 2701 case UHF_C_PORT_CONNECTION: 2702 case UHF_C_PORT_ENABLE: 2703 case UHF_C_PORT_SUSPEND: 2704 case UHF_C_PORT_OVER_CURRENT: 2705 case UHF_C_PORT_RESET: 2706 /* Enable RHSC interrupt if condition is cleared. */ 2707 if ((OREAD4(sc, port) >> 16) == 0) 2708 ohci_rhsc_enable(sc); 2709 break; 2710 default: 2711 break; 2712 } 2713 break; 2714 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2715 if (len == 0) 2716 break; 2717 if ((value & 0xff) != 0) { 2718 err = USBD_IOERROR; 2719 goto ret; 2720 } 2721 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2722 hubd = ohci_hubd; 2723 hubd.bNbrPorts = sc->sc_noport; 2724 USETW(hubd.wHubCharacteristics, 2725 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2726 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2727 /* XXX overcurrent */ 2728 ); 2729 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2730 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2731 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2732 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2733 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2734 l = min(len, hubd.bDescLength); 2735 totlen = l; 2736 memcpy(buf, &hubd, l); 2737 break; 2738 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2739 if (len != 4) { 2740 err = USBD_IOERROR; 2741 goto ret; 2742 } 2743 memset(buf, 0, len); /* ? XXX */ 2744 totlen = len; 2745 break; 2746 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2747 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2748 index)); 2749 if (index < 1 || index > sc->sc_noport) { 2750 err = USBD_IOERROR; 2751 goto ret; 2752 } 2753 if (len != 4) { 2754 err = USBD_IOERROR; 2755 goto ret; 2756 } 2757 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2758 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2759 v)); 2760 USETW(ps.wPortStatus, v); 2761 USETW(ps.wPortChange, v >> 16); 2762 l = min(len, sizeof ps); 2763 memcpy(buf, &ps, l); 2764 totlen = l; 2765 break; 2766 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2767 err = USBD_IOERROR; 2768 goto ret; 2769 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2770 break; 2771 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2772 if (index < 1 || index > sc->sc_noport) { 2773 err = USBD_IOERROR; 2774 goto ret; 2775 } 2776 port = OHCI_RH_PORT_STATUS(index); 2777 switch(value) { 2778 case UHF_PORT_ENABLE: 2779 OWRITE4(sc, port, UPS_PORT_ENABLED); 2780 break; 2781 case UHF_PORT_SUSPEND: 2782 OWRITE4(sc, port, UPS_SUSPEND); 2783 break; 2784 case UHF_PORT_RESET: 2785 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2786 index)); 2787 OWRITE4(sc, port, UPS_RESET); 2788 for (i = 0; i < 5; i++) { 2789 usb_delay_ms(&sc->sc_bus, 2790 USB_PORT_ROOT_RESET_DELAY); 2791 if (sc->sc_dying) { 2792 err = USBD_IOERROR; 2793 goto ret; 2794 } 2795 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2796 break; 2797 } 2798 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2799 index, OREAD4(sc, port))); 2800 break; 2801 case UHF_PORT_POWER: 2802 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2803 "%d\n", index)); 2804 OWRITE4(sc, port, UPS_PORT_POWER); 2805 break; 2806 default: 2807 err = USBD_IOERROR; 2808 goto ret; 2809 } 2810 break; 2811 default: 2812 err = USBD_IOERROR; 2813 goto ret; 2814 } 2815 xfer->actlen = totlen; 2816 err = USBD_NORMAL_COMPLETION; 2817 ret: 2818 xfer->status = err; 2819 mutex_enter(&sc->sc_lock); 2820 usb_transfer_complete(xfer); 2821 mutex_exit(&sc->sc_lock); 2822 return (USBD_IN_PROGRESS); 2823 } 2824 2825 /* Abort a root control request. */ 2826 Static void 2827 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2828 { 2829 /* Nothing to do, all transfers are synchronous. */ 2830 } 2831 2832 /* Close the root pipe. */ 2833 Static void 2834 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2835 { 2836 DPRINTF(("ohci_root_ctrl_close\n")); 2837 /* Nothing to do. */ 2838 } 2839 2840 Static usbd_status 2841 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2842 { 2843 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2844 usbd_status err; 2845 2846 /* Insert last in queue. */ 2847 mutex_enter(&sc->sc_lock); 2848 err = usb_insert_transfer(xfer); 2849 mutex_exit(&sc->sc_lock); 2850 if (err) 2851 return (err); 2852 2853 /* Pipe isn't running, start first */ 2854 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2855 } 2856 2857 Static usbd_status 2858 ohci_root_intr_start(usbd_xfer_handle xfer) 2859 { 2860 usbd_pipe_handle pipe = xfer->pipe; 2861 ohci_softc_t *sc = pipe->device->bus->hci_private; 2862 2863 if (sc->sc_dying) 2864 return (USBD_IOERROR); 2865 2866 mutex_enter(&sc->sc_lock); 2867 KASSERT(sc->sc_intrxfer == NULL); 2868 sc->sc_intrxfer = xfer; 2869 mutex_exit(&sc->sc_lock); 2870 2871 return (USBD_IN_PROGRESS); 2872 } 2873 2874 /* Abort a root interrupt request. */ 2875 Static void 2876 ohci_root_intr_abort(usbd_xfer_handle xfer) 2877 { 2878 #ifdef DIAGNOSTIC 2879 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2880 #endif 2881 2882 KASSERT(mutex_owned(&sc->sc_lock)); 2883 2884 if (xfer->pipe->intrxfer == xfer) { 2885 DPRINTF(("ohci_root_intr_abort: remove\n")); 2886 xfer->pipe->intrxfer = NULL; 2887 } 2888 xfer->status = USBD_CANCELLED; 2889 usb_transfer_complete(xfer); 2890 } 2891 2892 /* Close the root pipe. */ 2893 Static void 2894 ohci_root_intr_close(usbd_pipe_handle pipe) 2895 { 2896 ohci_softc_t *sc = pipe->device->bus->hci_private; 2897 2898 KASSERT(mutex_owned(&sc->sc_lock)); 2899 2900 DPRINTF(("ohci_root_intr_close\n")); 2901 2902 sc->sc_intrxfer = NULL; 2903 } 2904 2905 /************************/ 2906 2907 Static usbd_status 2908 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2909 { 2910 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2911 usbd_status err; 2912 2913 /* Insert last in queue. */ 2914 mutex_enter(&sc->sc_lock); 2915 err = usb_insert_transfer(xfer); 2916 mutex_exit(&sc->sc_lock); 2917 if (err) 2918 return (err); 2919 2920 /* Pipe isn't running, start first */ 2921 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2922 } 2923 2924 Static usbd_status 2925 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2926 { 2927 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2928 usbd_status err; 2929 2930 if (sc->sc_dying) 2931 return (USBD_IOERROR); 2932 2933 #ifdef DIAGNOSTIC 2934 if (!(xfer->rqflags & URQ_REQUEST)) { 2935 /* XXX panic */ 2936 printf("ohci_device_ctrl_transfer: not a request\n"); 2937 return (USBD_INVAL); 2938 } 2939 #endif 2940 2941 mutex_enter(&sc->sc_lock); 2942 err = ohci_device_request(xfer); 2943 mutex_exit(&sc->sc_lock); 2944 if (err) 2945 return (err); 2946 2947 if (sc->sc_bus.use_polling) 2948 ohci_waitintr(sc, xfer); 2949 return (USBD_IN_PROGRESS); 2950 } 2951 2952 /* Abort a device control request. */ 2953 Static void 2954 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2955 { 2956 #ifdef DIAGNOSTIC 2957 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2958 #endif 2959 2960 KASSERT(mutex_owned(&sc->sc_lock)); 2961 2962 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2963 ohci_abort_xfer(xfer, USBD_CANCELLED); 2964 } 2965 2966 /* Close a device control pipe. */ 2967 Static void 2968 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2969 { 2970 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2971 ohci_softc_t *sc = pipe->device->bus->hci_private; 2972 2973 KASSERT(mutex_owned(&sc->sc_lock)); 2974 2975 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2976 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2977 ohci_free_std(sc, opipe->tail.td); 2978 } 2979 2980 /************************/ 2981 2982 Static void 2983 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2984 { 2985 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2986 ohci_softc_t *sc = pipe->device->bus->hci_private; 2987 2988 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2989 } 2990 2991 Static void 2992 ohci_noop(usbd_pipe_handle pipe) 2993 { 2994 } 2995 2996 Static usbd_status 2997 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2998 { 2999 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3000 usbd_status err; 3001 3002 /* Insert last in queue. */ 3003 mutex_enter(&sc->sc_lock); 3004 err = usb_insert_transfer(xfer); 3005 mutex_exit(&sc->sc_lock); 3006 if (err) 3007 return (err); 3008 3009 /* Pipe isn't running, start first */ 3010 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3011 } 3012 3013 Static usbd_status 3014 ohci_device_bulk_start(usbd_xfer_handle xfer) 3015 { 3016 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3017 usbd_device_handle dev = opipe->pipe.device; 3018 ohci_softc_t *sc = dev->bus->hci_private; 3019 int addr = dev->address; 3020 ohci_soft_td_t *data, *tail, *tdp; 3021 ohci_soft_ed_t *sed; 3022 int len, isread, endpt; 3023 usbd_status err; 3024 3025 if (sc->sc_dying) 3026 return (USBD_IOERROR); 3027 3028 #ifdef DIAGNOSTIC 3029 if (xfer->rqflags & URQ_REQUEST) { 3030 /* XXX panic */ 3031 printf("ohci_device_bulk_start: a request\n"); 3032 return (USBD_INVAL); 3033 } 3034 #endif 3035 3036 mutex_enter(&sc->sc_lock); 3037 3038 len = xfer->length; 3039 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3040 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3041 sed = opipe->sed; 3042 3043 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3044 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3045 endpt)); 3046 3047 opipe->u.bulk.isread = isread; 3048 opipe->u.bulk.length = len; 3049 3050 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3051 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3052 /* Update device address */ 3053 sed->ed.ed_flags = HTOO32( 3054 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3055 OHCI_ED_SET_FA(addr)); 3056 3057 /* Allocate a chain of new TDs (including a new tail). */ 3058 data = opipe->tail.td; 3059 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3060 data, &tail); 3061 if (err) 3062 return err; 3063 3064 /* We want interrupt at the end of the transfer. */ 3065 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3066 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3067 tail->flags |= OHCI_CALL_DONE; 3068 tail = tail->nexttd; /* point at sentinel */ 3069 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3070 sizeof(tail->td.td_flags), 3071 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3072 if (err) { 3073 mutex_exit(&sc->sc_lock); 3074 return (err); 3075 } 3076 3077 tail->xfer = NULL; 3078 xfer->hcpriv = data; 3079 3080 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3081 "td_cbp=0x%08x td_be=0x%08x\n", 3082 (int)O32TOH(sed->ed.ed_flags), 3083 (int)O32TOH(data->td.td_flags), 3084 (int)O32TOH(data->td.td_cbp), 3085 (int)O32TOH(data->td.td_be))); 3086 3087 #ifdef OHCI_DEBUG 3088 if (ohcidebug > 5) { 3089 ohci_dump_ed(sc, sed); 3090 ohci_dump_tds(sc, data); 3091 } 3092 #endif 3093 3094 /* Insert ED in schedule */ 3095 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3096 tdp->xfer = xfer; 3097 } 3098 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3099 opipe->tail.td = tail; 3100 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3101 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3102 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3103 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3104 if (xfer->timeout && !sc->sc_bus.use_polling) { 3105 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3106 ohci_timeout, xfer); 3107 } 3108 mutex_exit(&sc->sc_lock); 3109 3110 #if 0 3111 /* This goes wrong if we are too slow. */ 3112 if (ohcidebug > 10) { 3113 delay(10000); 3114 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3115 OREAD4(sc, OHCI_COMMAND_STATUS))); 3116 ohci_dump_ed(sc, sed); 3117 ohci_dump_tds(sc, data); 3118 } 3119 #endif 3120 3121 return (USBD_IN_PROGRESS); 3122 } 3123 3124 Static void 3125 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3126 { 3127 #ifdef DIAGNOSTIC 3128 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3129 #endif 3130 3131 KASSERT(mutex_owned(&sc->sc_lock)); 3132 3133 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3134 ohci_abort_xfer(xfer, USBD_CANCELLED); 3135 } 3136 3137 /* 3138 * Close a device bulk pipe. 3139 */ 3140 Static void 3141 ohci_device_bulk_close(usbd_pipe_handle pipe) 3142 { 3143 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3144 ohci_softc_t *sc = pipe->device->bus->hci_private; 3145 3146 KASSERT(mutex_owned(&sc->sc_lock)); 3147 3148 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3149 ohci_close_pipe(pipe, sc->sc_bulk_head); 3150 ohci_free_std(sc, opipe->tail.td); 3151 } 3152 3153 /************************/ 3154 3155 Static usbd_status 3156 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3157 { 3158 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3159 usbd_status err; 3160 3161 /* Insert last in queue. */ 3162 mutex_enter(&sc->sc_lock); 3163 err = usb_insert_transfer(xfer); 3164 mutex_exit(&sc->sc_lock); 3165 if (err) 3166 return (err); 3167 3168 /* Pipe isn't running, start first */ 3169 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3170 } 3171 3172 Static usbd_status 3173 ohci_device_intr_start(usbd_xfer_handle xfer) 3174 { 3175 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3176 usbd_device_handle dev = opipe->pipe.device; 3177 ohci_softc_t *sc = dev->bus->hci_private; 3178 ohci_soft_ed_t *sed = opipe->sed; 3179 ohci_soft_td_t *data, *tail; 3180 int len, isread, endpt; 3181 3182 if (sc->sc_dying) 3183 return (USBD_IOERROR); 3184 3185 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3186 "flags=%d priv=%p\n", 3187 xfer, xfer->length, xfer->flags, xfer->priv)); 3188 3189 #ifdef DIAGNOSTIC 3190 if (xfer->rqflags & URQ_REQUEST) 3191 panic("ohci_device_intr_transfer: a request"); 3192 #endif 3193 3194 len = xfer->length; 3195 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3196 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3197 3198 data = opipe->tail.td; 3199 mutex_enter(&sc->sc_lock); 3200 tail = ohci_alloc_std(sc); 3201 mutex_exit(&sc->sc_lock); 3202 if (tail == NULL) 3203 return (USBD_NOMEM); 3204 tail->xfer = NULL; 3205 3206 data->td.td_flags = HTOO32( 3207 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3208 OHCI_TD_NOCC | 3209 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3210 if (xfer->flags & USBD_SHORT_XFER_OK) 3211 data->td.td_flags |= HTOO32(OHCI_TD_R); 3212 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3213 data->nexttd = tail; 3214 data->td.td_nexttd = HTOO32(tail->physaddr); 3215 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3216 data->len = len; 3217 data->xfer = xfer; 3218 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3219 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 xfer->hcpriv = data; 3222 3223 #ifdef OHCI_DEBUG 3224 if (ohcidebug > 5) { 3225 DPRINTF(("ohci_device_intr_transfer:\n")); 3226 ohci_dump_ed(sc, sed); 3227 ohci_dump_tds(sc, data); 3228 } 3229 #endif 3230 3231 /* Insert ED in schedule */ 3232 mutex_enter(&sc->sc_lock); 3233 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3234 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3235 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3236 opipe->tail.td = tail; 3237 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3238 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3239 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3240 3241 #if 0 3242 /* 3243 * This goes horribly wrong, printing thousands of descriptors, 3244 * because false references are followed due to the fact that the 3245 * TD is gone. 3246 */ 3247 if (ohcidebug > 5) { 3248 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3249 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3250 OREAD4(sc, OHCI_COMMAND_STATUS))); 3251 ohci_dump_ed(sc, sed); 3252 ohci_dump_tds(sc, data); 3253 } 3254 #endif 3255 mutex_exit(&sc->sc_lock); 3256 3257 return (USBD_IN_PROGRESS); 3258 } 3259 3260 /* Abort a device interrupt request. */ 3261 Static void 3262 ohci_device_intr_abort(usbd_xfer_handle xfer) 3263 { 3264 #ifdef DIAGNOSTIC 3265 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3266 #endif 3267 3268 KASSERT(mutex_owned(&sc->sc_lock)); 3269 3270 if (xfer->pipe->intrxfer == xfer) { 3271 DPRINTF(("ohci_device_intr_abort: remove\n")); 3272 xfer->pipe->intrxfer = NULL; 3273 } 3274 ohci_abort_xfer(xfer, USBD_CANCELLED); 3275 } 3276 3277 /* Close a device interrupt pipe. */ 3278 Static void 3279 ohci_device_intr_close(usbd_pipe_handle pipe) 3280 { 3281 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3282 ohci_softc_t *sc = pipe->device->bus->hci_private; 3283 int nslots = opipe->u.intr.nslots; 3284 int pos = opipe->u.intr.pos; 3285 int j; 3286 ohci_soft_ed_t *p, *sed = opipe->sed; 3287 3288 KASSERT(mutex_owned(&sc->sc_lock)); 3289 3290 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3291 pipe, nslots, pos)); 3292 usb_syncmem(&sed->dma, sed->offs, 3293 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3294 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3295 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3296 sizeof(sed->ed.ed_flags), 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3299 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3300 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3301 3302 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3303 continue; 3304 #ifdef DIAGNOSTIC 3305 if (p == NULL) 3306 panic("ohci_device_intr_close: ED not found"); 3307 #endif 3308 p->next = sed->next; 3309 p->ed.ed_nexted = sed->ed.ed_nexted; 3310 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3311 sizeof(p->ed.ed_nexted), 3312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3313 3314 for (j = 0; j < nslots; j++) 3315 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3316 3317 ohci_free_std(sc, opipe->tail.td); 3318 ohci_free_sed(sc, opipe->sed); 3319 } 3320 3321 Static usbd_status 3322 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3323 { 3324 int i, j, best; 3325 u_int npoll, slow, shigh, nslots; 3326 u_int bestbw, bw; 3327 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3328 3329 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3330 if (ival == 0) { 3331 printf("ohci_setintr: 0 interval\n"); 3332 return (USBD_INVAL); 3333 } 3334 3335 npoll = OHCI_NO_INTRS; 3336 while (npoll > ival) 3337 npoll /= 2; 3338 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3339 3340 /* 3341 * We now know which level in the tree the ED must go into. 3342 * Figure out which slot has most bandwidth left over. 3343 * Slots to examine: 3344 * npoll 3345 * 1 0 3346 * 2 1 2 3347 * 4 3 4 5 6 3348 * 8 7 8 9 10 11 12 13 14 3349 * N (N-1) .. (N-1+N-1) 3350 */ 3351 slow = npoll-1; 3352 shigh = slow + npoll; 3353 nslots = OHCI_NO_INTRS / npoll; 3354 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3355 bw = 0; 3356 for (j = 0; j < nslots; j++) 3357 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3358 if (bw < bestbw) { 3359 best = i; 3360 bestbw = bw; 3361 } 3362 } 3363 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3364 best, slow, shigh, bestbw)); 3365 3366 mutex_enter(&sc->sc_lock); 3367 hsed = sc->sc_eds[best]; 3368 sed->next = hsed->next; 3369 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3370 sizeof(hsed->ed.ed_flags), 3371 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3372 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3373 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3374 sizeof(sed->ed.ed_flags), 3375 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3376 hsed->next = sed; 3377 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3378 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3379 sizeof(hsed->ed.ed_flags), 3380 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3381 mutex_exit(&sc->sc_lock); 3382 3383 for (j = 0; j < nslots; j++) 3384 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3385 opipe->u.intr.nslots = nslots; 3386 opipe->u.intr.pos = best; 3387 3388 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3389 return (USBD_NORMAL_COMPLETION); 3390 } 3391 3392 /***********************/ 3393 3394 usbd_status 3395 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3396 { 3397 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3398 usbd_status err; 3399 3400 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3401 3402 /* Put it on our queue, */ 3403 mutex_enter(&sc->sc_lock); 3404 err = usb_insert_transfer(xfer); 3405 mutex_exit(&sc->sc_lock); 3406 3407 /* bail out on error, */ 3408 if (err && err != USBD_IN_PROGRESS) 3409 return (err); 3410 3411 /* XXX should check inuse here */ 3412 3413 /* insert into schedule, */ 3414 ohci_device_isoc_enter(xfer); 3415 3416 /* and start if the pipe wasn't running */ 3417 if (!err) 3418 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3419 3420 return (err); 3421 } 3422 3423 void 3424 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3425 { 3426 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3427 usbd_device_handle dev = opipe->pipe.device; 3428 ohci_softc_t *sc = dev->bus->hci_private; 3429 ohci_soft_ed_t *sed = opipe->sed; 3430 struct iso *iso = &opipe->u.iso; 3431 ohci_soft_itd_t *sitd, *nsitd; 3432 ohci_physaddr_t buf, offs, noffs, bp0; 3433 int i, ncur, nframes; 3434 3435 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3436 "nframes=%d\n", 3437 iso->inuse, iso->next, xfer, xfer->nframes)); 3438 3439 if (sc->sc_dying) 3440 return; 3441 3442 if (iso->next == -1) { 3443 /* Not in use yet, schedule it a few frames ahead. */ 3444 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3445 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3446 iso->next)); 3447 } 3448 3449 sitd = opipe->tail.itd; 3450 buf = DMAADDR(&xfer->dmabuf, 0); 3451 bp0 = OHCI_PAGE(buf); 3452 offs = OHCI_PAGE_OFFSET(buf); 3453 nframes = xfer->nframes; 3454 xfer->hcpriv = sitd; 3455 for (i = ncur = 0; i < nframes; i++, ncur++) { 3456 noffs = offs + xfer->frlengths[i]; 3457 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3458 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3459 3460 /* Allocate next ITD */ 3461 mutex_enter(&sc->sc_lock); 3462 nsitd = ohci_alloc_sitd(sc); 3463 mutex_exit(&sc->sc_lock); 3464 if (nsitd == NULL) { 3465 /* XXX what now? */ 3466 printf("%s: isoc TD alloc failed\n", 3467 device_xname(sc->sc_dev)); 3468 return; 3469 } 3470 3471 /* Fill current ITD */ 3472 sitd->itd.itd_flags = HTOO32( 3473 OHCI_ITD_NOCC | 3474 OHCI_ITD_SET_SF(iso->next) | 3475 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3476 OHCI_ITD_SET_FC(ncur)); 3477 sitd->itd.itd_bp0 = HTOO32(bp0); 3478 sitd->nextitd = nsitd; 3479 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3480 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3481 sitd->xfer = xfer; 3482 sitd->flags = 0; 3483 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3484 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3485 3486 sitd = nsitd; 3487 iso->next = iso->next + ncur; 3488 bp0 = OHCI_PAGE(buf + offs); 3489 ncur = 0; 3490 } 3491 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3492 offs = noffs; 3493 } 3494 mutex_enter(&sc->sc_lock); 3495 nsitd = ohci_alloc_sitd(sc); 3496 mutex_exit(&sc->sc_lock); 3497 if (nsitd == NULL) { 3498 /* XXX what now? */ 3499 printf("%s: isoc TD alloc failed\n", 3500 device_xname(sc->sc_dev)); 3501 return; 3502 } 3503 /* Fixup last used ITD */ 3504 sitd->itd.itd_flags = HTOO32( 3505 OHCI_ITD_NOCC | 3506 OHCI_ITD_SET_SF(iso->next) | 3507 OHCI_ITD_SET_DI(0) | 3508 OHCI_ITD_SET_FC(ncur)); 3509 sitd->itd.itd_bp0 = HTOO32(bp0); 3510 sitd->nextitd = nsitd; 3511 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3512 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3513 sitd->xfer = xfer; 3514 sitd->flags = OHCI_CALL_DONE; 3515 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3517 3518 iso->next = iso->next + ncur; 3519 iso->inuse += nframes; 3520 3521 xfer->actlen = offs; /* XXX pretend we did it all */ 3522 3523 xfer->status = USBD_IN_PROGRESS; 3524 3525 #ifdef OHCI_DEBUG 3526 if (ohcidebug > 5) { 3527 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3528 O32TOH(sc->sc_hcca->hcca_frame_number))); 3529 ohci_dump_itds(sc, xfer->hcpriv); 3530 ohci_dump_ed(sc, sed); 3531 } 3532 #endif 3533 3534 mutex_enter(&sc->sc_lock); 3535 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3536 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3537 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3538 opipe->tail.itd = nsitd; 3539 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3540 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3541 sizeof(sed->ed.ed_flags), 3542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3543 mutex_exit(&sc->sc_lock); 3544 3545 #ifdef OHCI_DEBUG 3546 if (ohcidebug > 5) { 3547 delay(150000); 3548 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3549 O32TOH(sc->sc_hcca->hcca_frame_number))); 3550 ohci_dump_itds(sc, xfer->hcpriv); 3551 ohci_dump_ed(sc, sed); 3552 } 3553 #endif 3554 } 3555 3556 usbd_status 3557 ohci_device_isoc_start(usbd_xfer_handle xfer) 3558 { 3559 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3560 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3561 3562 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3563 3564 mutex_enter(&sc->sc_lock); 3565 3566 if (sc->sc_dying) { 3567 mutex_exit(&sc->sc_lock); 3568 return (USBD_IOERROR); 3569 } 3570 3571 #ifdef DIAGNOSTIC 3572 if (xfer->status != USBD_IN_PROGRESS) 3573 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3574 #endif 3575 3576 /* XXX anything to do? */ 3577 3578 mutex_exit(&sc->sc_lock); 3579 3580 return (USBD_IN_PROGRESS); 3581 } 3582 3583 void 3584 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3585 { 3586 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3587 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3588 ohci_soft_ed_t *sed; 3589 ohci_soft_itd_t *sitd; 3590 3591 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3592 3593 KASSERT(mutex_owned(&sc->sc_lock)); 3594 3595 /* Transfer is already done. */ 3596 if (xfer->status != USBD_NOT_STARTED && 3597 xfer->status != USBD_IN_PROGRESS) { 3598 printf("ohci_device_isoc_abort: early return\n"); 3599 goto done; 3600 } 3601 3602 /* Give xfer the requested abort code. */ 3603 xfer->status = USBD_CANCELLED; 3604 3605 sed = opipe->sed; 3606 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3607 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3608 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3609 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3610 sizeof(sed->ed.ed_flags), 3611 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3612 3613 sitd = xfer->hcpriv; 3614 #ifdef DIAGNOSTIC 3615 if (sitd == NULL) { 3616 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3617 goto done; 3618 } 3619 #endif 3620 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3621 #ifdef DIAGNOSTIC 3622 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3623 sitd->isdone = 1; 3624 #endif 3625 } 3626 3627 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3628 3629 /* Run callback. */ 3630 usb_transfer_complete(xfer); 3631 3632 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3633 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3634 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3635 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3636 3637 done: 3638 KASSERT(mutex_owned(&sc->sc_lock)); 3639 } 3640 3641 void 3642 ohci_device_isoc_done(usbd_xfer_handle xfer) 3643 { 3644 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3645 } 3646 3647 usbd_status 3648 ohci_setup_isoc(usbd_pipe_handle pipe) 3649 { 3650 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3651 ohci_softc_t *sc = pipe->device->bus->hci_private; 3652 struct iso *iso = &opipe->u.iso; 3653 3654 iso->next = -1; 3655 iso->inuse = 0; 3656 3657 mutex_enter(&sc->sc_lock); 3658 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3659 mutex_exit(&sc->sc_lock); 3660 3661 return (USBD_NORMAL_COMPLETION); 3662 } 3663 3664 void 3665 ohci_device_isoc_close(usbd_pipe_handle pipe) 3666 { 3667 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3668 ohci_softc_t *sc = pipe->device->bus->hci_private; 3669 3670 KASSERT(mutex_owned(&sc->sc_lock)); 3671 3672 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3673 ohci_close_pipe(pipe, sc->sc_isoc_head); 3674 #ifdef DIAGNOSTIC 3675 opipe->tail.itd->isdone = 1; 3676 #endif 3677 ohci_free_sitd(sc, opipe->tail.itd); 3678 } 3679
Indexes created Fri Oct 03 02:09:57 GMT 2025