ohci.c revision 1.243
1 /* $NetBSD: ohci.c,v 1.243 2013/09/15 09:16:21 martin Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.243 2013/09/15 09:16:21 martin Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 136 137 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 138 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 139 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 140 Static void ohci_root_ctrl_close(usbd_pipe_handle); 141 Static void ohci_root_ctrl_done(usbd_xfer_handle); 142 143 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 145 Static void ohci_root_intr_abort(usbd_xfer_handle); 146 Static void ohci_root_intr_close(usbd_pipe_handle); 147 Static void ohci_root_intr_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 151 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 152 Static void ohci_device_ctrl_close(usbd_pipe_handle); 153 Static void ohci_device_ctrl_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 157 Static void ohci_device_bulk_abort(usbd_xfer_handle); 158 Static void ohci_device_bulk_close(usbd_pipe_handle); 159 Static void ohci_device_bulk_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 163 Static void ohci_device_intr_abort(usbd_xfer_handle); 164 Static void ohci_device_intr_close(usbd_pipe_handle); 165 Static void ohci_device_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 169 Static void ohci_device_isoc_abort(usbd_xfer_handle); 170 Static void ohci_device_isoc_close(usbd_pipe_handle); 171 Static void ohci_device_isoc_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 174 struct ohci_pipe *pipe, int ival); 175 176 Static void ohci_timeout(void *); 177 Static void ohci_timeout_task(void *); 178 Static void ohci_rhsc_enable(void *); 179 180 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 181 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 182 183 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ohci_noop(usbd_pipe_handle pipe); 185 186 #ifdef OHCI_DEBUG 187 Static void ohci_dumpregs(ohci_softc_t *); 188 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 191 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 192 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 193 #endif 194 195 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 196 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 197 #define OWRITE1(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OWRITE2(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE4(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 204 static __inline uint32_t 205 OREAD4(ohci_softc_t *sc, bus_size_t r) 206 { 207 208 OBARR(sc); 209 return bus_space_read_4(sc->iot, sc->ioh, r); 210 } 211 212 /* Reverse the bits in a value 0 .. 31 */ 213 Static u_int8_t revbits[OHCI_NO_INTRS] = 214 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 215 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 216 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 217 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 218 219 struct ohci_pipe { 220 struct usbd_pipe pipe; 221 ohci_soft_ed_t *sed; 222 union { 223 ohci_soft_td_t *td; 224 ohci_soft_itd_t *itd; 225 } tail; 226 /* Info needed for different pipe kinds. */ 227 union { 228 /* Control pipe */ 229 struct { 230 usb_dma_t reqdma; 231 u_int length; 232 ohci_soft_td_t *setup, *data, *stat; 233 } ctl; 234 /* Interrupt pipe */ 235 struct { 236 int nslots; 237 int pos; 238 } intr; 239 /* Bulk pipe */ 240 struct { 241 u_int length; 242 int isread; 243 } bulk; 244 /* Iso pipe */ 245 struct iso { 246 int next, inuse; 247 } iso; 248 } u; 249 }; 250 251 #define OHCI_INTR_ENDPT 1 252 253 Static const struct usbd_bus_methods ohci_bus_methods = { 254 .open_pipe = ohci_open, 255 .soft_intr = ohci_softintr, 256 .do_poll = ohci_poll, 257 .allocm = ohci_allocm, 258 .freem = ohci_freem, 259 .allocx = ohci_allocx, 260 .freex = ohci_freex, 261 .get_lock = ohci_get_lock, 262 }; 263 264 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 265 .transfer = ohci_root_ctrl_transfer, 266 .start = ohci_root_ctrl_start, 267 .abort = ohci_root_ctrl_abort, 268 .close = ohci_root_ctrl_close, 269 .cleartoggle = ohci_noop, 270 .done = ohci_root_ctrl_done, 271 }; 272 273 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 274 .transfer = ohci_root_intr_transfer, 275 .start = ohci_root_intr_start, 276 .abort = ohci_root_intr_abort, 277 .close = ohci_root_intr_close, 278 .cleartoggle = ohci_noop, 279 .done = ohci_root_intr_done, 280 }; 281 282 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 283 .transfer = ohci_device_ctrl_transfer, 284 .start = ohci_device_ctrl_start, 285 .abort = ohci_device_ctrl_abort, 286 .close = ohci_device_ctrl_close, 287 .cleartoggle = ohci_noop, 288 .done = ohci_device_ctrl_done, 289 }; 290 291 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 292 .transfer = ohci_device_intr_transfer, 293 .start = ohci_device_intr_start, 294 .abort = ohci_device_intr_abort, 295 .close = ohci_device_intr_close, 296 .cleartoggle = ohci_device_clear_toggle, 297 .done = ohci_device_intr_done, 298 }; 299 300 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 301 .transfer = ohci_device_bulk_transfer, 302 .start = ohci_device_bulk_start, 303 .abort = ohci_device_bulk_abort, 304 .close = ohci_device_bulk_close, 305 .cleartoggle = ohci_device_clear_toggle, 306 .done = ohci_device_bulk_done, 307 }; 308 309 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 310 .transfer = ohci_device_isoc_transfer, 311 .start = ohci_device_isoc_start, 312 .abort = ohci_device_isoc_abort, 313 .close = ohci_device_isoc_close, 314 .cleartoggle = ohci_noop, 315 .done = ohci_device_isoc_done, 316 }; 317 318 int 319 ohci_activate(device_t self, enum devact act) 320 { 321 struct ohci_softc *sc = device_private(self); 322 323 switch (act) { 324 case DVACT_DEACTIVATE: 325 sc->sc_dying = 1; 326 return 0; 327 default: 328 return EOPNOTSUPP; 329 } 330 } 331 332 void 333 ohci_childdet(device_t self, device_t child) 334 { 335 struct ohci_softc *sc = device_private(self); 336 337 KASSERT(sc->sc_child == child); 338 sc->sc_child = NULL; 339 } 340 341 int 342 ohci_detach(struct ohci_softc *sc, int flags) 343 { 344 int rv = 0; 345 346 if (sc->sc_child != NULL) 347 rv = config_detach(sc->sc_child, flags); 348 349 if (rv != 0) 350 return (rv); 351 352 callout_stop(&sc->sc_tmo_rhsc); 353 354 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 355 callout_destroy(&sc->sc_tmo_rhsc); 356 357 softint_disestablish(sc->sc_rhsc_si); 358 359 cv_destroy(&sc->sc_softwake_cv); 360 361 mutex_destroy(&sc->sc_lock); 362 mutex_destroy(&sc->sc_intr_lock); 363 364 if (sc->sc_hcca != NULL) 365 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 366 pool_cache_destroy(sc->sc_xferpool); 367 368 return (rv); 369 } 370 371 ohci_soft_ed_t * 372 ohci_alloc_sed(ohci_softc_t *sc) 373 { 374 ohci_soft_ed_t *sed; 375 usbd_status err; 376 int i, offs; 377 usb_dma_t dma; 378 379 if (sc->sc_freeeds == NULL) { 380 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 381 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 382 OHCI_ED_ALIGN, &dma); 383 if (err) 384 return (0); 385 for (i = 0; i < OHCI_SED_CHUNK; i++) { 386 offs = i * OHCI_SED_SIZE; 387 sed = KERNADDR(&dma, offs); 388 sed->physaddr = DMAADDR(&dma, offs); 389 sed->dma = dma; 390 sed->offs = offs; 391 sed->next = sc->sc_freeeds; 392 sc->sc_freeeds = sed; 393 } 394 } 395 sed = sc->sc_freeeds; 396 sc->sc_freeeds = sed->next; 397 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 398 sed->next = 0; 399 return (sed); 400 } 401 402 void 403 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 404 { 405 sed->next = sc->sc_freeeds; 406 sc->sc_freeeds = sed; 407 } 408 409 ohci_soft_td_t * 410 ohci_alloc_std(ohci_softc_t *sc) 411 { 412 ohci_soft_td_t *std; 413 usbd_status err; 414 int i, offs; 415 usb_dma_t dma; 416 417 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 418 419 if (sc->sc_freetds == NULL) { 420 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 421 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 422 OHCI_TD_ALIGN, &dma); 423 if (err) 424 return (NULL); 425 for(i = 0; i < OHCI_STD_CHUNK; i++) { 426 offs = i * OHCI_STD_SIZE; 427 std = KERNADDR(&dma, offs); 428 std->physaddr = DMAADDR(&dma, offs); 429 std->dma = dma; 430 std->offs = offs; 431 std->nexttd = sc->sc_freetds; 432 sc->sc_freetds = std; 433 } 434 } 435 436 std = sc->sc_freetds; 437 sc->sc_freetds = std->nexttd; 438 memset(&std->td, 0, sizeof(ohci_td_t)); 439 std->nexttd = NULL; 440 std->xfer = NULL; 441 ohci_hash_add_td(sc, std); 442 443 return (std); 444 } 445 446 void 447 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 448 { 449 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 450 451 ohci_hash_rem_td(sc, std); 452 std->nexttd = sc->sc_freetds; 453 sc->sc_freetds = std; 454 } 455 456 usbd_status 457 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 458 int alen, int rd, usbd_xfer_handle xfer, 459 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 460 { 461 ohci_soft_td_t *next, *cur; 462 ohci_physaddr_t dataphys, dataphysend; 463 u_int32_t tdflags; 464 int len, curlen; 465 usb_dma_t *dma = &xfer->dmabuf; 466 u_int16_t flags = xfer->flags; 467 468 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 469 470 KASSERT(mutex_owned(&sc->sc_lock)); 471 472 len = alen; 473 cur = sp; 474 dataphys = DMAADDR(dma, 0); 475 dataphysend = OHCI_PAGE(dataphys + len - 1); 476 usb_syncmem(dma, 0, len, 477 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 478 tdflags = HTOO32( 479 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 480 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 481 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 482 483 for (;;) { 484 next = ohci_alloc_std(sc); 485 if (next == NULL) 486 goto nomem; 487 488 /* The OHCI hardware can handle at most one page crossing. */ 489 if (OHCI_PAGE(dataphys) == dataphysend || 490 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 491 /* we can handle it in this TD */ 492 curlen = len; 493 } else { 494 /* must use multiple TDs, fill as much as possible. */ 495 curlen = 2 * OHCI_PAGE_SIZE - 496 (dataphys & (OHCI_PAGE_SIZE-1)); 497 /* the length must be a multiple of the max size */ 498 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 499 #ifdef DIAGNOSTIC 500 if (curlen == 0) 501 panic("ohci_alloc_std: curlen == 0"); 502 #endif 503 } 504 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 505 "dataphysend=0x%08x len=%d curlen=%d\n", 506 dataphys, dataphysend, 507 len, curlen)); 508 len -= curlen; 509 510 cur->td.td_flags = tdflags; 511 cur->td.td_cbp = HTOO32(dataphys); 512 cur->nexttd = next; 513 cur->td.td_nexttd = HTOO32(next->physaddr); 514 cur->td.td_be = HTOO32(dataphys + curlen - 1); 515 cur->len = curlen; 516 cur->flags = OHCI_ADD_LEN; 517 cur->xfer = xfer; 518 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 519 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 520 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 521 dataphys, dataphys + curlen - 1)); 522 if (len == 0) 523 break; 524 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 525 dataphys += curlen; 526 cur = next; 527 } 528 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 529 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 530 /* Force a 0 length transfer at the end. */ 531 532 cur = next; 533 next = ohci_alloc_std(sc); 534 if (next == NULL) 535 goto nomem; 536 537 cur->td.td_flags = tdflags; 538 cur->td.td_cbp = 0; /* indicate 0 length packet */ 539 cur->nexttd = next; 540 cur->td.td_nexttd = HTOO32(next->physaddr); 541 cur->td.td_be = ~0; 542 cur->len = 0; 543 cur->flags = 0; 544 cur->xfer = xfer; 545 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 546 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 547 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 548 } 549 *ep = cur; 550 551 return (USBD_NORMAL_COMPLETION); 552 553 nomem: 554 555 /* Don't free sp - let the caller do that */ 556 ohci_free_std_chain(sc, sp->nexttd, NULL); 557 558 return (USBD_NOMEM); 559 } 560 561 Static void 562 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 563 ohci_soft_td_t *stdend) 564 { 565 ohci_soft_td_t *p; 566 567 for (; std != stdend; std = p) { 568 p = std->nexttd; 569 ohci_free_std(sc, std); 570 } 571 } 572 573 ohci_soft_itd_t * 574 ohci_alloc_sitd(ohci_softc_t *sc) 575 { 576 ohci_soft_itd_t *sitd; 577 usbd_status err; 578 int i, offs; 579 usb_dma_t dma; 580 581 if (sc->sc_freeitds == NULL) { 582 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 583 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 584 OHCI_ITD_ALIGN, &dma); 585 if (err) 586 return (NULL); 587 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 588 offs = i * OHCI_SITD_SIZE; 589 sitd = KERNADDR(&dma, offs); 590 sitd->physaddr = DMAADDR(&dma, offs); 591 sitd->dma = dma; 592 sitd->offs = offs; 593 sitd->nextitd = sc->sc_freeitds; 594 sc->sc_freeitds = sitd; 595 } 596 } 597 598 sitd = sc->sc_freeitds; 599 sc->sc_freeitds = sitd->nextitd; 600 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 601 sitd->nextitd = NULL; 602 sitd->xfer = NULL; 603 ohci_hash_add_itd(sc, sitd); 604 605 #ifdef DIAGNOSTIC 606 sitd->isdone = 0; 607 #endif 608 609 return (sitd); 610 } 611 612 void 613 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 614 { 615 616 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 617 618 #ifdef DIAGNOSTIC 619 if (!sitd->isdone) { 620 panic("ohci_free_sitd: sitd=%p not done", sitd); 621 return; 622 } 623 /* Warn double free */ 624 sitd->isdone = 0; 625 #endif 626 627 ohci_hash_rem_itd(sc, sitd); 628 sitd->nextitd = sc->sc_freeitds; 629 sc->sc_freeitds = sitd; 630 } 631 632 usbd_status 633 ohci_init(ohci_softc_t *sc) 634 { 635 ohci_soft_ed_t *sed, *psed; 636 usbd_status err; 637 int i; 638 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 639 640 DPRINTF(("ohci_init: start\n")); 641 aprint_normal_dev(sc->sc_dev, ""); 642 643 sc->sc_hcca = NULL; 644 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 645 646 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 647 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 648 cv_init(&sc->sc_softwake_cv, "ohciab"); 649 650 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 651 ohci_rhsc_softint, sc); 652 653 for (i = 0; i < OHCI_HASH_SIZE; i++) 654 LIST_INIT(&sc->sc_hash_tds[i]); 655 for (i = 0; i < OHCI_HASH_SIZE; i++) 656 LIST_INIT(&sc->sc_hash_itds[i]); 657 658 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 659 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 660 661 rev = OREAD4(sc, OHCI_REVISION); 662 aprint_normal("OHCI version %d.%d%s\n", 663 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 664 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 665 666 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 667 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 668 sc->sc_bus.usbrev = USBREV_UNKNOWN; 669 return (USBD_INVAL); 670 } 671 sc->sc_bus.usbrev = USBREV_1_0; 672 673 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 674 USB_MEM_RESERVE); 675 676 /* XXX determine alignment by R/W */ 677 /* Allocate the HCCA area. */ 678 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 679 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 680 if (err) { 681 sc->sc_hcca = NULL; 682 return err; 683 } 684 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 685 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 686 687 sc->sc_eintrs = OHCI_NORMAL_INTRS; 688 689 /* Allocate dummy ED that starts the control list. */ 690 sc->sc_ctrl_head = ohci_alloc_sed(sc); 691 if (sc->sc_ctrl_head == NULL) { 692 err = USBD_NOMEM; 693 goto bad1; 694 } 695 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 696 697 /* Allocate dummy ED that starts the bulk list. */ 698 sc->sc_bulk_head = ohci_alloc_sed(sc); 699 if (sc->sc_bulk_head == NULL) { 700 err = USBD_NOMEM; 701 goto bad2; 702 } 703 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 704 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 705 sizeof(sc->sc_bulk_head->ed), 706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 707 708 /* Allocate dummy ED that starts the isochronous list. */ 709 sc->sc_isoc_head = ohci_alloc_sed(sc); 710 if (sc->sc_isoc_head == NULL) { 711 err = USBD_NOMEM; 712 goto bad3; 713 } 714 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 715 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 716 sizeof(sc->sc_isoc_head->ed), 717 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 718 719 /* Allocate all the dummy EDs that make up the interrupt tree. */ 720 for (i = 0; i < OHCI_NO_EDS; i++) { 721 sed = ohci_alloc_sed(sc); 722 if (sed == NULL) { 723 while (--i >= 0) 724 ohci_free_sed(sc, sc->sc_eds[i]); 725 err = USBD_NOMEM; 726 goto bad4; 727 } 728 /* All ED fields are set to 0. */ 729 sc->sc_eds[i] = sed; 730 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 731 if (i != 0) 732 psed = sc->sc_eds[(i-1) / 2]; 733 else 734 psed= sc->sc_isoc_head; 735 sed->next = psed; 736 sed->ed.ed_nexted = HTOO32(psed->physaddr); 737 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 738 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 739 } 740 /* 741 * Fill HCCA interrupt table. The bit reversal is to get 742 * the tree set up properly to spread the interrupts. 743 */ 744 for (i = 0; i < OHCI_NO_INTRS; i++) 745 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 746 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 747 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 749 750 #ifdef OHCI_DEBUG 751 if (ohcidebug > 15) { 752 for (i = 0; i < OHCI_NO_EDS; i++) { 753 printf("ed#%d ", i); 754 ohci_dump_ed(sc, sc->sc_eds[i]); 755 } 756 printf("iso "); 757 ohci_dump_ed(sc, sc->sc_isoc_head); 758 } 759 #endif 760 761 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 762 ctl = OREAD4(sc, OHCI_CONTROL); 763 rwc = ctl & OHCI_RWC; 764 fm = OREAD4(sc, OHCI_FM_INTERVAL); 765 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 766 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 767 768 /* Determine in what context we are running. */ 769 if (ctl & OHCI_IR) { 770 /* SMM active, request change */ 771 DPRINTF(("ohci_init: SMM active, request owner change\n")); 772 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 773 (OHCI_OC | OHCI_MIE)) 774 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 775 s = OREAD4(sc, OHCI_COMMAND_STATUS); 776 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 777 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 778 usb_delay_ms(&sc->sc_bus, 1); 779 ctl = OREAD4(sc, OHCI_CONTROL); 780 } 781 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 782 if ((ctl & OHCI_IR) == 0) { 783 aprint_error_dev(sc->sc_dev, 784 "SMM does not respond, resetting\n"); 785 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 786 goto reset; 787 } 788 #if 0 789 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 790 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 791 /* BIOS started controller. */ 792 DPRINTF(("ohci_init: BIOS active\n")); 793 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 794 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 795 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 796 } 797 #endif 798 } else { 799 DPRINTF(("ohci_init: cold started\n")); 800 reset: 801 /* Controller was cold started. */ 802 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 803 } 804 805 /* 806 * This reset should not be necessary according to the OHCI spec, but 807 * without it some controllers do not start. 808 */ 809 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 810 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 811 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 812 813 /* We now own the host controller and the bus has been reset. */ 814 815 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 816 /* Nominal time for a reset is 10 us. */ 817 for (i = 0; i < 10; i++) { 818 delay(10); 819 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 820 if (!hcr) 821 break; 822 } 823 if (hcr) { 824 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 825 err = USBD_IOERROR; 826 goto bad5; 827 } 828 #ifdef OHCI_DEBUG 829 if (ohcidebug > 15) 830 ohci_dumpregs(sc); 831 #endif 832 833 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 834 835 /* Set up HC registers. */ 836 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 837 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 838 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 839 /* disable all interrupts and then switch on all desired interrupts */ 840 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 841 /* switch on desired functional features */ 842 ctl = OREAD4(sc, OHCI_CONTROL); 843 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 844 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 845 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 846 /* And finally start it! */ 847 OWRITE4(sc, OHCI_CONTROL, ctl); 848 849 /* 850 * The controller is now OPERATIONAL. Set a some final 851 * registers that should be set earlier, but that the 852 * controller ignores when in the SUSPEND state. 853 */ 854 ival = OHCI_GET_IVAL(fm); 855 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 856 fm |= OHCI_FSMPS(ival) | ival; 857 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 858 per = OHCI_PERIODIC(ival); /* 90% periodic */ 859 OWRITE4(sc, OHCI_PERIODIC_START, per); 860 861 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 862 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 863 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 864 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 865 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 866 867 /* 868 * The AMD756 requires a delay before re-reading the register, 869 * otherwise it will occasionally report 0 ports. 870 */ 871 sc->sc_noport = 0; 872 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 873 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 874 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 875 } 876 877 #ifdef OHCI_DEBUG 878 if (ohcidebug > 5) 879 ohci_dumpregs(sc); 880 #endif 881 882 /* Set up the bus struct. */ 883 sc->sc_bus.methods = &ohci_bus_methods; 884 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 885 886 sc->sc_control = sc->sc_intre = 0; 887 888 /* Finally, turn on interrupts. */ 889 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 890 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 891 892 return (USBD_NORMAL_COMPLETION); 893 894 bad5: 895 for (i = 0; i < OHCI_NO_EDS; i++) 896 ohci_free_sed(sc, sc->sc_eds[i]); 897 bad4: 898 ohci_free_sed(sc, sc->sc_isoc_head); 899 bad3: 900 ohci_free_sed(sc, sc->sc_bulk_head); 901 bad2: 902 ohci_free_sed(sc, sc->sc_ctrl_head); 903 bad1: 904 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 905 sc->sc_hcca = NULL; 906 return (err); 907 } 908 909 usbd_status 910 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 911 { 912 struct ohci_softc *sc = bus->hci_private; 913 usbd_status status; 914 915 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 916 if (status == USBD_NOMEM) 917 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 918 return status; 919 } 920 921 void 922 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 923 { 924 struct ohci_softc *sc = bus->hci_private; 925 if (dma->block->flags & USB_DMA_RESERVE) { 926 usb_reserve_freem(&sc->sc_dma_reserve, dma); 927 return; 928 } 929 usb_freemem(&sc->sc_bus, dma); 930 } 931 932 usbd_xfer_handle 933 ohci_allocx(struct usbd_bus *bus) 934 { 935 struct ohci_softc *sc = bus->hci_private; 936 usbd_xfer_handle xfer; 937 938 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 939 if (xfer != NULL) { 940 memset(xfer, 0, sizeof(struct ohci_xfer)); 941 #ifdef DIAGNOSTIC 942 xfer->busy_free = XFER_BUSY; 943 #endif 944 } 945 return (xfer); 946 } 947 948 void 949 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 950 { 951 struct ohci_softc *sc = bus->hci_private; 952 953 #ifdef DIAGNOSTIC 954 if (xfer->busy_free != XFER_BUSY) { 955 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 956 xfer->busy_free); 957 } 958 xfer->busy_free = XFER_FREE; 959 #endif 960 pool_cache_put(sc->sc_xferpool, xfer); 961 } 962 963 Static void 964 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 965 { 966 struct ohci_softc *sc = bus->hci_private; 967 968 *lock = &sc->sc_lock; 969 } 970 971 /* 972 * Shut down the controller when the system is going down. 973 */ 974 bool 975 ohci_shutdown(device_t self, int flags) 976 { 977 ohci_softc_t *sc = device_private(self); 978 979 DPRINTF(("ohci_shutdown: stopping the HC\n")); 980 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 981 return true; 982 } 983 984 bool 985 ohci_resume(device_t dv, const pmf_qual_t *qual) 986 { 987 ohci_softc_t *sc = device_private(dv); 988 uint32_t ctl; 989 990 mutex_spin_enter(&sc->sc_intr_lock); 991 sc->sc_bus.use_polling++; 992 mutex_spin_exit(&sc->sc_intr_lock); 993 994 /* Some broken BIOSes do not recover these values */ 995 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 996 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 997 sc->sc_ctrl_head->physaddr); 998 OWRITE4(sc, OHCI_BULK_HEAD_ED, 999 sc->sc_bulk_head->physaddr); 1000 if (sc->sc_intre) 1001 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1002 (OHCI_ALL_INTRS | OHCI_MIE)); 1003 if (sc->sc_control) 1004 ctl = sc->sc_control; 1005 else 1006 ctl = OREAD4(sc, OHCI_CONTROL); 1007 ctl |= OHCI_HCFS_RESUME; 1008 OWRITE4(sc, OHCI_CONTROL, ctl); 1009 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1010 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1011 OWRITE4(sc, OHCI_CONTROL, ctl); 1012 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1013 sc->sc_control = sc->sc_intre = 0; 1014 1015 mutex_spin_enter(&sc->sc_intr_lock); 1016 sc->sc_bus.use_polling--; 1017 mutex_spin_exit(&sc->sc_intr_lock); 1018 1019 return true; 1020 } 1021 1022 bool 1023 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1024 { 1025 ohci_softc_t *sc = device_private(dv); 1026 uint32_t ctl; 1027 1028 mutex_spin_enter(&sc->sc_intr_lock); 1029 sc->sc_bus.use_polling++; 1030 mutex_spin_exit(&sc->sc_intr_lock); 1031 1032 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1033 if (sc->sc_control == 0) { 1034 /* 1035 * Preserve register values, in case that BIOS 1036 * does not recover them. 1037 */ 1038 sc->sc_control = ctl; 1039 sc->sc_intre = OREAD4(sc, 1040 OHCI_INTERRUPT_ENABLE); 1041 } 1042 ctl |= OHCI_HCFS_SUSPEND; 1043 OWRITE4(sc, OHCI_CONTROL, ctl); 1044 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1045 1046 mutex_spin_enter(&sc->sc_intr_lock); 1047 sc->sc_bus.use_polling--; 1048 mutex_spin_exit(&sc->sc_intr_lock); 1049 1050 return true; 1051 } 1052 1053 #ifdef OHCI_DEBUG 1054 void 1055 ohci_dumpregs(ohci_softc_t *sc) 1056 { 1057 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1058 OREAD4(sc, OHCI_REVISION), 1059 OREAD4(sc, OHCI_CONTROL), 1060 OREAD4(sc, OHCI_COMMAND_STATUS))); 1061 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1062 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1063 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1064 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1065 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1066 OREAD4(sc, OHCI_HCCA), 1067 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1068 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1069 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1070 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1071 OREAD4(sc, OHCI_BULK_HEAD_ED), 1072 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1073 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1074 OREAD4(sc, OHCI_DONE_HEAD), 1075 OREAD4(sc, OHCI_FM_INTERVAL), 1076 OREAD4(sc, OHCI_FM_REMAINING))); 1077 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1078 OREAD4(sc, OHCI_FM_NUMBER), 1079 OREAD4(sc, OHCI_PERIODIC_START), 1080 OREAD4(sc, OHCI_LS_THRESHOLD))); 1081 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1082 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1083 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1084 OREAD4(sc, OHCI_RH_STATUS))); 1085 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1086 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1087 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1088 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1089 O32TOH(sc->sc_hcca->hcca_frame_number), 1090 O32TOH(sc->sc_hcca->hcca_done_head))); 1091 } 1092 #endif 1093 1094 Static int ohci_intr1(ohci_softc_t *); 1095 1096 int 1097 ohci_intr(void *p) 1098 { 1099 ohci_softc_t *sc = p; 1100 int ret = 0; 1101 1102 if (sc == NULL) 1103 return (0); 1104 1105 mutex_spin_enter(&sc->sc_intr_lock); 1106 1107 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1108 goto done; 1109 1110 /* If we get an interrupt while polling, then just ignore it. */ 1111 if (sc->sc_bus.use_polling) { 1112 #ifdef DIAGNOSTIC 1113 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1114 #endif 1115 /* for level triggered intrs, should do something to ack */ 1116 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1117 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1118 1119 goto done; 1120 } 1121 1122 ret = ohci_intr1(sc); 1123 1124 done: 1125 mutex_spin_exit(&sc->sc_intr_lock); 1126 return ret; 1127 } 1128 1129 Static int 1130 ohci_intr1(ohci_softc_t *sc) 1131 { 1132 u_int32_t intrs, eintrs; 1133 1134 DPRINTFN(14,("ohci_intr1: enter\n")); 1135 1136 /* In case the interrupt occurs before initialization has completed. */ 1137 if (sc == NULL || sc->sc_hcca == NULL) { 1138 #ifdef DIAGNOSTIC 1139 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1140 #endif 1141 return (0); 1142 } 1143 1144 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1145 1146 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1147 if (!intrs) 1148 return (0); 1149 1150 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1151 eintrs = intrs & sc->sc_eintrs; 1152 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1153 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1154 (u_int)eintrs, sc->sc_eintrs)); 1155 1156 if (!eintrs) { 1157 return (0); 1158 } 1159 1160 sc->sc_bus.no_intrs++; 1161 if (eintrs & OHCI_SO) { 1162 sc->sc_overrun_cnt++; 1163 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1164 printf("%s: %u scheduling overruns\n", 1165 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1166 sc->sc_overrun_cnt = 0; 1167 } 1168 /* XXX do what */ 1169 eintrs &= ~OHCI_SO; 1170 } 1171 if (eintrs & OHCI_WDH) { 1172 /* 1173 * We block the interrupt below, and reenable it later from 1174 * ohci_softintr(). 1175 */ 1176 usb_schedsoftintr(&sc->sc_bus); 1177 } 1178 if (eintrs & OHCI_RD) { 1179 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1180 /* XXX process resume detect */ 1181 } 1182 if (eintrs & OHCI_UE) { 1183 printf("%s: unrecoverable error, controller halted\n", 1184 device_xname(sc->sc_dev)); 1185 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1186 /* XXX what else */ 1187 } 1188 if (eintrs & OHCI_RHSC) { 1189 /* 1190 * We block the interrupt below, and reenable it later from 1191 * a timeout. 1192 */ 1193 softint_schedule(sc->sc_rhsc_si); 1194 } 1195 1196 if (eintrs != 0) { 1197 /* Block unprocessed interrupts. */ 1198 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1199 sc->sc_eintrs &= ~eintrs; 1200 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1201 device_xname(sc->sc_dev), eintrs)); 1202 } 1203 1204 return (1); 1205 } 1206 1207 void 1208 ohci_rhsc_enable(void *v_sc) 1209 { 1210 ohci_softc_t *sc = v_sc; 1211 1212 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1213 mutex_spin_enter(&sc->sc_intr_lock); 1214 sc->sc_eintrs |= OHCI_RHSC; 1215 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1216 mutex_spin_exit(&sc->sc_intr_lock); 1217 } 1218 1219 #ifdef OHCI_DEBUG 1220 const char *ohci_cc_strs[] = { 1221 "NO_ERROR", 1222 "CRC", 1223 "BIT_STUFFING", 1224 "DATA_TOGGLE_MISMATCH", 1225 "STALL", 1226 "DEVICE_NOT_RESPONDING", 1227 "PID_CHECK_FAILURE", 1228 "UNEXPECTED_PID", 1229 "DATA_OVERRUN", 1230 "DATA_UNDERRUN", 1231 "BUFFER_OVERRUN", 1232 "BUFFER_UNDERRUN", 1233 "reserved", 1234 "reserved", 1235 "NOT_ACCESSED", 1236 "NOT_ACCESSED", 1237 }; 1238 #endif 1239 1240 void 1241 ohci_softintr(void *v) 1242 { 1243 struct usbd_bus *bus = v; 1244 ohci_softc_t *sc = bus->hci_private; 1245 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1246 ohci_soft_td_t *std, *sdone, *stdnext; 1247 usbd_xfer_handle xfer; 1248 struct ohci_pipe *opipe; 1249 int len, cc; 1250 int i, j, actlen, iframes, uedir; 1251 ohci_physaddr_t done; 1252 1253 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1254 1255 DPRINTFN(10,("ohci_softintr: enter\n")); 1256 1257 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1258 sizeof(sc->sc_hcca->hcca_done_head), 1259 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1260 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1261 sc->sc_hcca->hcca_done_head = 0; 1262 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1263 sizeof(sc->sc_hcca->hcca_done_head), 1264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1265 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1266 sc->sc_eintrs |= OHCI_WDH; 1267 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1268 1269 /* Reverse the done list. */ 1270 for (sdone = NULL, sidone = NULL; done != 0; ) { 1271 std = ohci_hash_find_td(sc, done); 1272 if (std != NULL) { 1273 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1274 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1275 std->dnext = sdone; 1276 done = O32TOH(std->td.td_nexttd); 1277 sdone = std; 1278 DPRINTFN(10,("add TD %p\n", std)); 1279 continue; 1280 } 1281 sitd = ohci_hash_find_itd(sc, done); 1282 if (sitd != NULL) { 1283 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1284 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1285 sitd->dnext = sidone; 1286 done = O32TOH(sitd->itd.itd_nextitd); 1287 sidone = sitd; 1288 DPRINTFN(5,("add ITD %p\n", sitd)); 1289 continue; 1290 } 1291 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1292 (u_long)done); 1293 break; 1294 } 1295 1296 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1297 1298 #ifdef OHCI_DEBUG 1299 if (ohcidebug > 10) { 1300 DPRINTF(("ohci_process_done: TD done:\n")); 1301 for (std = sdone; std; std = std->dnext) 1302 ohci_dump_td(sc, std); 1303 } 1304 #endif 1305 1306 for (std = sdone; std; std = stdnext) { 1307 xfer = std->xfer; 1308 stdnext = std->dnext; 1309 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1310 std, xfer, xfer ? xfer->hcpriv : 0)); 1311 if (xfer == NULL) { 1312 /* 1313 * xfer == NULL: There seems to be no xfer associated 1314 * with this TD. It is tailp that happened to end up on 1315 * the done queue. 1316 * Shouldn't happen, but some chips are broken(?). 1317 */ 1318 continue; 1319 } 1320 if (xfer->status == USBD_CANCELLED || 1321 xfer->status == USBD_TIMEOUT) { 1322 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1323 xfer)); 1324 /* Handled by abort routine. */ 1325 continue; 1326 } 1327 callout_stop(&xfer->timeout_handle); 1328 1329 len = std->len; 1330 if (std->td.td_cbp != 0) 1331 len -= O32TOH(std->td.td_be) - 1332 O32TOH(std->td.td_cbp) + 1; 1333 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1334 std->flags)); 1335 if (std->flags & OHCI_ADD_LEN) 1336 xfer->actlen += len; 1337 1338 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1339 if (cc == OHCI_CC_NO_ERROR) { 1340 if (std->flags & OHCI_CALL_DONE) { 1341 xfer->status = USBD_NORMAL_COMPLETION; 1342 usb_transfer_complete(xfer); 1343 } 1344 ohci_free_std(sc, std); 1345 } else { 1346 /* 1347 * Endpoint is halted. First unlink all the TDs 1348 * belonging to the failed transfer, and then restart 1349 * the endpoint. 1350 */ 1351 ohci_soft_td_t *p, *n; 1352 opipe = (struct ohci_pipe *)xfer->pipe; 1353 1354 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1355 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1356 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1357 1358 /* remove TDs */ 1359 for (p = std; p->xfer == xfer; p = n) { 1360 n = p->nexttd; 1361 ohci_free_std(sc, p); 1362 } 1363 1364 /* clear halt */ 1365 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1366 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1367 1368 if (cc == OHCI_CC_STALL) 1369 xfer->status = USBD_STALLED; 1370 else 1371 xfer->status = USBD_IOERROR; 1372 usb_transfer_complete(xfer); 1373 } 1374 } 1375 1376 #ifdef OHCI_DEBUG 1377 if (ohcidebug > 10) { 1378 DPRINTF(("ohci_softintr: ITD done:\n")); 1379 for (sitd = sidone; sitd; sitd = sitd->dnext) 1380 ohci_dump_itd(sc, sitd); 1381 } 1382 #endif 1383 1384 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1385 xfer = sitd->xfer; 1386 sitdnext = sitd->dnext; 1387 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1388 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1389 if (xfer == NULL) 1390 continue; 1391 if (xfer->status == USBD_CANCELLED || 1392 xfer->status == USBD_TIMEOUT) { 1393 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1394 xfer)); 1395 /* Handled by abort routine. */ 1396 continue; 1397 } 1398 #ifdef DIAGNOSTIC 1399 if (sitd->isdone) 1400 printf("ohci_softintr: sitd=%p is done\n", sitd); 1401 sitd->isdone = 1; 1402 #endif 1403 if (sitd->flags & OHCI_CALL_DONE) { 1404 ohci_soft_itd_t *next; 1405 1406 opipe = (struct ohci_pipe *)xfer->pipe; 1407 opipe->u.iso.inuse -= xfer->nframes; 1408 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1409 bEndpointAddress); 1410 xfer->status = USBD_NORMAL_COMPLETION; 1411 actlen = 0; 1412 for (i = 0, sitd = xfer->hcpriv;; 1413 sitd = next) { 1414 next = sitd->nextitd; 1415 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1416 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1417 xfer->status = USBD_IOERROR; 1418 /* For input, update frlengths with actual */ 1419 /* XXX anything necessary for output? */ 1420 if (uedir == UE_DIR_IN && 1421 xfer->status == USBD_NORMAL_COMPLETION) { 1422 iframes = OHCI_ITD_GET_FC(O32TOH( 1423 sitd->itd.itd_flags)); 1424 for (j = 0; j < iframes; i++, j++) { 1425 len = O16TOH(sitd-> 1426 itd.itd_offset[j]); 1427 if ((OHCI_ITD_PSW_GET_CC(len) & 1428 OHCI_CC_NOT_ACCESSED_MASK) 1429 == OHCI_CC_NOT_ACCESSED) 1430 len = 0; 1431 else 1432 len = OHCI_ITD_PSW_LENGTH(len); 1433 xfer->frlengths[i] = len; 1434 actlen += len; 1435 } 1436 } 1437 if (sitd->flags & OHCI_CALL_DONE) 1438 break; 1439 ohci_free_sitd(sc, sitd); 1440 } 1441 ohci_free_sitd(sc, sitd); 1442 if (uedir == UE_DIR_IN && 1443 xfer->status == USBD_NORMAL_COMPLETION) 1444 xfer->actlen = actlen; 1445 xfer->hcpriv = NULL; 1446 1447 usb_transfer_complete(xfer); 1448 } 1449 } 1450 1451 if (sc->sc_softwake) { 1452 sc->sc_softwake = 0; 1453 cv_broadcast(&sc->sc_softwake_cv); 1454 } 1455 1456 DPRINTFN(10,("ohci_softintr: done:\n")); 1457 } 1458 1459 void 1460 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1461 { 1462 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1463 #ifdef DIAGNOSTIC 1464 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1465 #endif 1466 int len = UGETW(xfer->request.wLength); 1467 int isread = (xfer->request.bmRequestType & UT_READ); 1468 1469 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1470 1471 KASSERT(mutex_owned(&sc->sc_lock)); 1472 1473 #ifdef DIAGNOSTIC 1474 if (!(xfer->rqflags & URQ_REQUEST)) { 1475 panic("ohci_device_ctrl_done: not a request"); 1476 } 1477 #endif 1478 if (len) 1479 usb_syncmem(&xfer->dmabuf, 0, len, 1480 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1481 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1482 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1483 } 1484 1485 void 1486 ohci_device_intr_done(usbd_xfer_handle xfer) 1487 { 1488 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1489 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1490 ohci_soft_ed_t *sed = opipe->sed; 1491 ohci_soft_td_t *data, *tail; 1492 int isread = 1493 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1494 1495 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1496 xfer, xfer->actlen)); 1497 1498 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1499 1500 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1501 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1502 if (xfer->pipe->repeat) { 1503 data = opipe->tail.td; 1504 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1505 if (tail == NULL) { 1506 xfer->status = USBD_NOMEM; 1507 return; 1508 } 1509 tail->xfer = NULL; 1510 1511 data->td.td_flags = HTOO32( 1512 OHCI_TD_IN | OHCI_TD_NOCC | 1513 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1514 if (xfer->flags & USBD_SHORT_XFER_OK) 1515 data->td.td_flags |= HTOO32(OHCI_TD_R); 1516 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1517 data->nexttd = tail; 1518 data->td.td_nexttd = HTOO32(tail->physaddr); 1519 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1520 xfer->length - 1); 1521 data->len = xfer->length; 1522 data->xfer = xfer; 1523 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1524 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1525 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1526 xfer->hcpriv = data; 1527 xfer->actlen = 0; 1528 1529 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1530 usb_syncmem(&sed->dma, 1531 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1532 sizeof(sed->ed.ed_tailp), 1533 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1534 opipe->tail.td = tail; 1535 } 1536 } 1537 1538 void 1539 ohci_device_bulk_done(usbd_xfer_handle xfer) 1540 { 1541 #ifdef DIAGNOSTIC 1542 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1543 #endif 1544 int isread = 1545 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1546 1547 KASSERT(mutex_owned(&sc->sc_lock)); 1548 1549 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1550 xfer, xfer->actlen)); 1551 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1552 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1553 } 1554 1555 Static void 1556 ohci_rhsc_softint(void *arg) 1557 { 1558 ohci_softc_t *sc = arg; 1559 1560 mutex_enter(&sc->sc_lock); 1561 1562 ohci_rhsc(sc, sc->sc_intrxfer); 1563 1564 /* Do not allow RHSC interrupts > 1 per second */ 1565 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1566 1567 mutex_exit(&sc->sc_lock); 1568 } 1569 1570 void 1571 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1572 { 1573 u_char *p; 1574 int i, m; 1575 int hstatus __unused; 1576 1577 KASSERT(mutex_owned(&sc->sc_lock)); 1578 1579 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1580 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1581 sc, xfer, hstatus)); 1582 1583 if (xfer == NULL) { 1584 /* Just ignore the change. */ 1585 return; 1586 } 1587 1588 p = KERNADDR(&xfer->dmabuf, 0); 1589 m = min(sc->sc_noport, xfer->length * 8 - 1); 1590 memset(p, 0, xfer->length); 1591 for (i = 1; i <= m; i++) { 1592 /* Pick out CHANGE bits from the status reg. */ 1593 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1594 p[i/8] |= 1 << (i%8); 1595 } 1596 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1597 xfer->actlen = xfer->length; 1598 xfer->status = USBD_NORMAL_COMPLETION; 1599 1600 usb_transfer_complete(xfer); 1601 } 1602 1603 void 1604 ohci_root_intr_done(usbd_xfer_handle xfer) 1605 { 1606 } 1607 1608 void 1609 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1610 { 1611 } 1612 1613 /* 1614 * Wait here until controller claims to have an interrupt. 1615 * Then call ohci_intr and return. Use timeout to avoid waiting 1616 * too long. 1617 */ 1618 void 1619 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1620 { 1621 int timo; 1622 u_int32_t intrs; 1623 1624 mutex_enter(&sc->sc_lock); 1625 1626 xfer->status = USBD_IN_PROGRESS; 1627 for (timo = xfer->timeout; timo >= 0; timo--) { 1628 usb_delay_ms(&sc->sc_bus, 1); 1629 if (sc->sc_dying) 1630 break; 1631 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1632 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1633 #ifdef OHCI_DEBUG 1634 if (ohcidebug > 15) 1635 ohci_dumpregs(sc); 1636 #endif 1637 if (intrs) { 1638 mutex_spin_enter(&sc->sc_intr_lock); 1639 ohci_intr1(sc); 1640 mutex_spin_exit(&sc->sc_intr_lock); 1641 if (xfer->status != USBD_IN_PROGRESS) 1642 goto done; 1643 } 1644 } 1645 1646 /* Timeout */ 1647 DPRINTF(("ohci_waitintr: timeout\n")); 1648 xfer->status = USBD_TIMEOUT; 1649 usb_transfer_complete(xfer); 1650 1651 /* XXX should free TD */ 1652 1653 done: 1654 mutex_exit(&sc->sc_lock); 1655 } 1656 1657 void 1658 ohci_poll(struct usbd_bus *bus) 1659 { 1660 ohci_softc_t *sc = bus->hci_private; 1661 #ifdef OHCI_DEBUG 1662 static int last; 1663 int new; 1664 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1665 if (new != last) { 1666 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1667 last = new; 1668 } 1669 #endif 1670 sc->sc_eintrs |= OHCI_WDH; 1671 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1672 mutex_spin_enter(&sc->sc_intr_lock); 1673 ohci_intr1(sc); 1674 mutex_spin_exit(&sc->sc_intr_lock); 1675 } 1676 } 1677 1678 usbd_status 1679 ohci_device_request(usbd_xfer_handle xfer) 1680 { 1681 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1682 usb_device_request_t *req = &xfer->request; 1683 usbd_device_handle dev = opipe->pipe.device; 1684 ohci_softc_t *sc = dev->bus->hci_private; 1685 int addr = dev->address; 1686 ohci_soft_td_t *setup, *stat, *next, *tail; 1687 ohci_soft_ed_t *sed; 1688 int isread; 1689 int len; 1690 usbd_status err; 1691 1692 KASSERT(mutex_owned(&sc->sc_lock)); 1693 1694 isread = req->bmRequestType & UT_READ; 1695 len = UGETW(req->wLength); 1696 1697 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1698 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1699 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1700 UGETW(req->wIndex), len, addr, 1701 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1702 1703 setup = opipe->tail.td; 1704 stat = ohci_alloc_std(sc); 1705 if (stat == NULL) { 1706 err = USBD_NOMEM; 1707 goto bad1; 1708 } 1709 tail = ohci_alloc_std(sc); 1710 if (tail == NULL) { 1711 err = USBD_NOMEM; 1712 goto bad2; 1713 } 1714 tail->xfer = NULL; 1715 1716 sed = opipe->sed; 1717 opipe->u.ctl.length = len; 1718 1719 /* Update device address and length since they may have changed 1720 during the setup of the control pipe in usbd_new_device(). */ 1721 /* XXX This only needs to be done once, but it's too early in open. */ 1722 /* XXXX Should not touch ED here! */ 1723 1724 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1725 sizeof(sed->ed.ed_flags), 1726 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1727 sed->ed.ed_flags = HTOO32( 1728 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1729 OHCI_ED_SET_FA(addr) | 1730 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1731 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1732 sizeof(sed->ed.ed_flags), 1733 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1734 1735 next = stat; 1736 1737 /* Set up data transaction */ 1738 if (len != 0) { 1739 ohci_soft_td_t *std = stat; 1740 1741 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1742 std, &stat); 1743 if (err) { 1744 /* stat is unchanged if error */ 1745 goto bad3; 1746 } 1747 stat = stat->nexttd; /* point at free TD */ 1748 1749 /* Start toggle at 1 and then use the carried toggle. */ 1750 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1751 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1752 usb_syncmem(&std->dma, 1753 std->offs + offsetof(ohci_td_t, td_flags), 1754 sizeof(std->td.td_flags), 1755 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1756 } 1757 1758 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1759 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1760 1761 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1762 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1763 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1764 setup->nexttd = next; 1765 setup->td.td_nexttd = HTOO32(next->physaddr); 1766 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1767 setup->len = 0; 1768 setup->xfer = xfer; 1769 setup->flags = 0; 1770 xfer->hcpriv = setup; 1771 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1773 1774 stat->td.td_flags = HTOO32( 1775 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1776 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1777 stat->td.td_cbp = 0; 1778 stat->nexttd = tail; 1779 stat->td.td_nexttd = HTOO32(tail->physaddr); 1780 stat->td.td_be = 0; 1781 stat->flags = OHCI_CALL_DONE; 1782 stat->len = 0; 1783 stat->xfer = xfer; 1784 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1786 1787 #ifdef OHCI_DEBUG 1788 if (ohcidebug > 5) { 1789 DPRINTF(("ohci_device_request:\n")); 1790 ohci_dump_ed(sc, sed); 1791 ohci_dump_tds(sc, setup); 1792 } 1793 #endif 1794 1795 /* Insert ED in schedule */ 1796 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1797 usb_syncmem(&sed->dma, 1798 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1799 sizeof(sed->ed.ed_tailp), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 opipe->tail.td = tail; 1802 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1803 if (xfer->timeout && !sc->sc_bus.use_polling) { 1804 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1805 ohci_timeout, xfer); 1806 } 1807 1808 #ifdef OHCI_DEBUG 1809 if (ohcidebug > 20) { 1810 delay(10000); 1811 DPRINTF(("ohci_device_request: status=%x\n", 1812 OREAD4(sc, OHCI_COMMAND_STATUS))); 1813 ohci_dumpregs(sc); 1814 printf("ctrl head:\n"); 1815 ohci_dump_ed(sc, sc->sc_ctrl_head); 1816 printf("sed:\n"); 1817 ohci_dump_ed(sc, sed); 1818 ohci_dump_tds(sc, setup); 1819 } 1820 #endif 1821 1822 return (USBD_NORMAL_COMPLETION); 1823 1824 bad3: 1825 ohci_free_std(sc, tail); 1826 bad2: 1827 ohci_free_std(sc, stat); 1828 bad1: 1829 return (err); 1830 } 1831 1832 /* 1833 * Add an ED to the schedule. Called with USB lock held. 1834 */ 1835 Static void 1836 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1837 { 1838 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1839 1840 KASSERT(mutex_owned(&sc->sc_lock)); 1841 1842 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1843 sizeof(head->ed.ed_nexted), 1844 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1845 sed->next = head->next; 1846 sed->ed.ed_nexted = head->ed.ed_nexted; 1847 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1848 sizeof(sed->ed.ed_nexted), 1849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1850 head->next = sed; 1851 head->ed.ed_nexted = HTOO32(sed->physaddr); 1852 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1853 sizeof(head->ed.ed_nexted), 1854 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1855 } 1856 1857 /* 1858 * Remove an ED from the schedule. Called with USB lock held. 1859 */ 1860 Static void 1861 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1862 { 1863 ohci_soft_ed_t *p; 1864 1865 KASSERT(mutex_owned(&sc->sc_lock)); 1866 1867 /* XXX */ 1868 for (p = head; p != NULL && p->next != sed; p = p->next) 1869 ; 1870 if (p == NULL) 1871 panic("ohci_rem_ed: ED not found"); 1872 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1873 sizeof(sed->ed.ed_nexted), 1874 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1875 p->next = sed->next; 1876 p->ed.ed_nexted = sed->ed.ed_nexted; 1877 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1878 sizeof(p->ed.ed_nexted), 1879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1880 } 1881 1882 /* 1883 * When a transfer is completed the TD is added to the done queue by 1884 * the host controller. This queue is the processed by software. 1885 * Unfortunately the queue contains the physical address of the TD 1886 * and we have no simple way to translate this back to a kernel address. 1887 * To make the translation possible (and fast) we use a hash table of 1888 * TDs currently in the schedule. The physical address is used as the 1889 * hash value. 1890 */ 1891 1892 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1893 /* Called with USB lock held. */ 1894 void 1895 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1896 { 1897 int h = HASH(std->physaddr); 1898 1899 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1900 1901 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1902 } 1903 1904 /* Called with USB lock held. */ 1905 void 1906 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1907 { 1908 1909 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1910 1911 LIST_REMOVE(std, hnext); 1912 } 1913 1914 ohci_soft_td_t * 1915 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1916 { 1917 int h = HASH(a); 1918 ohci_soft_td_t *std; 1919 1920 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1921 std != NULL; 1922 std = LIST_NEXT(std, hnext)) 1923 if (std->physaddr == a) 1924 return (std); 1925 return (NULL); 1926 } 1927 1928 /* Called with USB lock held. */ 1929 void 1930 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1931 { 1932 int h = HASH(sitd->physaddr); 1933 1934 KASSERT(mutex_owned(&sc->sc_lock)); 1935 1936 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1937 sitd, (u_long)sitd->physaddr)); 1938 1939 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1940 } 1941 1942 /* Called with USB lock held. */ 1943 void 1944 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1945 { 1946 1947 KASSERT(mutex_owned(&sc->sc_lock)); 1948 1949 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1950 sitd, (u_long)sitd->physaddr)); 1951 1952 LIST_REMOVE(sitd, hnext); 1953 } 1954 1955 ohci_soft_itd_t * 1956 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1957 { 1958 int h = HASH(a); 1959 ohci_soft_itd_t *sitd; 1960 1961 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1962 sitd != NULL; 1963 sitd = LIST_NEXT(sitd, hnext)) 1964 if (sitd->physaddr == a) 1965 return (sitd); 1966 return (NULL); 1967 } 1968 1969 void 1970 ohci_timeout(void *addr) 1971 { 1972 struct ohci_xfer *oxfer = addr; 1973 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1974 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1975 1976 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1977 1978 if (sc->sc_dying) { 1979 mutex_enter(&sc->sc_lock); 1980 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1981 mutex_exit(&sc->sc_lock); 1982 return; 1983 } 1984 1985 /* Execute the abort in a process context. */ 1986 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1987 USB_TASKQ_MPSAFE); 1988 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1989 USB_TASKQ_HC); 1990 } 1991 1992 void 1993 ohci_timeout_task(void *addr) 1994 { 1995 usbd_xfer_handle xfer = addr; 1996 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1997 1998 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1999 2000 mutex_enter(&sc->sc_lock); 2001 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2002 mutex_exit(&sc->sc_lock); 2003 } 2004 2005 #ifdef OHCI_DEBUG 2006 void 2007 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2008 { 2009 for (; std; std = std->nexttd) 2010 ohci_dump_td(sc, std); 2011 } 2012 2013 void 2014 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2015 { 2016 char sbuf[128]; 2017 2018 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2019 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2020 snprintb(sbuf, sizeof(sbuf), 2021 "\177\20" 2022 "b\22R\0" 2023 "f\23\02DP\0" 2024 "=\x0" "setup\0" 2025 "=\x1" "out\0" 2026 "=\x2" "in\0" 2027 "=\x3" "reserved\0" 2028 "f\25\03DI\0" 2029 "=\x07" "none\0" 2030 "f\30\02T\0" 2031 "=\x0" "carry\0" 2032 "=\x1" "carry\0" 2033 "=\x2" "0\0" 2034 "=\x3" "1\0" 2035 "f\32\02EC\0" 2036 "f\34\04CC\0", 2037 (u_int32_t)O32TOH(std->td.td_flags)); 2038 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2039 std, (u_long)std->physaddr, sbuf, 2040 (u_long)O32TOH(std->td.td_cbp), 2041 (u_long)O32TOH(std->td.td_nexttd), 2042 (u_long)O32TOH(std->td.td_be)); 2043 } 2044 2045 void 2046 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2047 { 2048 int i; 2049 2050 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2051 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2052 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2053 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2054 sitd, (u_long)sitd->physaddr, 2055 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2056 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2057 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2058 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2059 (u_long)O32TOH(sitd->itd.itd_bp0), 2060 (u_long)O32TOH(sitd->itd.itd_nextitd), 2061 (u_long)O32TOH(sitd->itd.itd_be)); 2062 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2063 printf("offs[%d]=0x%04x ", i, 2064 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2065 printf("\n"); 2066 } 2067 2068 void 2069 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2070 { 2071 for (; sitd; sitd = sitd->nextitd) 2072 ohci_dump_itd(sc, sitd); 2073 } 2074 2075 void 2076 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2077 { 2078 char sbuf[128], sbuf2[128]; 2079 2080 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2081 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2082 snprintb(sbuf, sizeof(sbuf), 2083 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2084 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2085 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2086 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2087 2088 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2089 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2090 sed, (u_long)sed->physaddr, 2091 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2092 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2093 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2094 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2095 (u_long)O32TOH(sed->ed.ed_headp), 2096 (u_long)O32TOH(sed->ed.ed_nexted)); 2097 } 2098 #endif 2099 2100 usbd_status 2101 ohci_open(usbd_pipe_handle pipe) 2102 { 2103 usbd_device_handle dev = pipe->device; 2104 ohci_softc_t *sc = dev->bus->hci_private; 2105 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2106 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2107 u_int8_t addr = dev->address; 2108 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2109 ohci_soft_ed_t *sed; 2110 ohci_soft_td_t *std; 2111 ohci_soft_itd_t *sitd; 2112 ohci_physaddr_t tdphys; 2113 u_int32_t fmt; 2114 usbd_status err = USBD_NOMEM; 2115 int ival; 2116 2117 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2118 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2119 2120 if (sc->sc_dying) { 2121 return USBD_IOERROR; 2122 } 2123 2124 std = NULL; 2125 sed = NULL; 2126 2127 if (addr == sc->sc_addr) { 2128 switch (ed->bEndpointAddress) { 2129 case USB_CONTROL_ENDPOINT: 2130 pipe->methods = &ohci_root_ctrl_methods; 2131 break; 2132 case UE_DIR_IN | OHCI_INTR_ENDPT: 2133 pipe->methods = &ohci_root_intr_methods; 2134 break; 2135 default: 2136 err = USBD_INVAL; 2137 goto bad; 2138 } 2139 } else { 2140 sed = ohci_alloc_sed(sc); 2141 if (sed == NULL) 2142 goto bad; 2143 opipe->sed = sed; 2144 if (xfertype == UE_ISOCHRONOUS) { 2145 mutex_enter(&sc->sc_lock); 2146 sitd = ohci_alloc_sitd(sc); 2147 mutex_exit(&sc->sc_lock); 2148 if (sitd == NULL) 2149 goto bad; 2150 2151 opipe->tail.itd = sitd; 2152 tdphys = sitd->physaddr; 2153 fmt = OHCI_ED_FORMAT_ISO; 2154 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2155 fmt |= OHCI_ED_DIR_IN; 2156 else 2157 fmt |= OHCI_ED_DIR_OUT; 2158 } else { 2159 mutex_enter(&sc->sc_lock); 2160 std = ohci_alloc_std(sc); 2161 mutex_exit(&sc->sc_lock); 2162 if (std == NULL) 2163 goto bad; 2164 2165 opipe->tail.td = std; 2166 tdphys = std->physaddr; 2167 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2168 } 2169 sed->ed.ed_flags = HTOO32( 2170 OHCI_ED_SET_FA(addr) | 2171 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2172 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2173 fmt | 2174 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2175 sed->ed.ed_headp = HTOO32(tdphys | 2176 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2177 sed->ed.ed_tailp = HTOO32(tdphys); 2178 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2180 2181 switch (xfertype) { 2182 case UE_CONTROL: 2183 pipe->methods = &ohci_device_ctrl_methods; 2184 err = usb_allocmem(&sc->sc_bus, 2185 sizeof(usb_device_request_t), 2186 0, &opipe->u.ctl.reqdma); 2187 if (err) 2188 goto bad; 2189 mutex_enter(&sc->sc_lock); 2190 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2191 mutex_exit(&sc->sc_lock); 2192 break; 2193 case UE_INTERRUPT: 2194 pipe->methods = &ohci_device_intr_methods; 2195 ival = pipe->interval; 2196 if (ival == USBD_DEFAULT_INTERVAL) 2197 ival = ed->bInterval; 2198 err = ohci_device_setintr(sc, opipe, ival); 2199 if (err) 2200 goto bad; 2201 break; 2202 case UE_ISOCHRONOUS: 2203 pipe->methods = &ohci_device_isoc_methods; 2204 return (ohci_setup_isoc(pipe)); 2205 case UE_BULK: 2206 pipe->methods = &ohci_device_bulk_methods; 2207 mutex_enter(&sc->sc_lock); 2208 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2209 mutex_exit(&sc->sc_lock); 2210 break; 2211 } 2212 } 2213 2214 return USBD_NORMAL_COMPLETION; 2215 2216 bad: 2217 if (std != NULL) { 2218 mutex_enter(&sc->sc_lock); 2219 ohci_free_std(sc, std); 2220 mutex_exit(&sc->sc_lock); 2221 } 2222 if (sed != NULL) 2223 ohci_free_sed(sc, sed); 2224 return err; 2225 2226 } 2227 2228 /* 2229 * Close a reqular pipe. 2230 * Assumes that there are no pending transactions. 2231 */ 2232 void 2233 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2234 { 2235 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2236 ohci_softc_t *sc = pipe->device->bus->hci_private; 2237 ohci_soft_ed_t *sed = opipe->sed; 2238 2239 KASSERT(mutex_owned(&sc->sc_lock)); 2240 2241 #ifdef DIAGNOSTIC 2242 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2243 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2244 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2245 ohci_soft_td_t *std; 2246 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2247 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2248 "tl=0x%x pipe=%p, std=%p\n", sed, 2249 (int)O32TOH(sed->ed.ed_headp), 2250 (int)O32TOH(sed->ed.ed_tailp), 2251 pipe, std); 2252 #ifdef OHCI_DEBUG 2253 usbd_dump_pipe(&opipe->pipe); 2254 ohci_dump_ed(sc, sed); 2255 if (std) 2256 ohci_dump_td(sc, std); 2257 #endif 2258 usb_delay_ms(&sc->sc_bus, 2); 2259 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2260 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2261 printf("ohci_close_pipe: pipe still not empty\n"); 2262 } 2263 #endif 2264 ohci_rem_ed(sc, sed, head); 2265 /* Make sure the host controller is not touching this ED */ 2266 usb_delay_ms(&sc->sc_bus, 1); 2267 pipe->endpoint->datatoggle = 2268 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2269 ohci_free_sed(sc, opipe->sed); 2270 } 2271 2272 /* 2273 * Abort a device request. 2274 * If this routine is called at splusb() it guarantees that the request 2275 * will be removed from the hardware scheduling and that the callback 2276 * for it will be called with USBD_CANCELLED status. 2277 * It's impossible to guarantee that the requested transfer will not 2278 * have happened since the hardware runs concurrently. 2279 * If the transaction has already happened we rely on the ordinary 2280 * interrupt processing to process it. 2281 * XXX This is most probably wrong. 2282 * XXXMRG this doesn't make sense anymore. 2283 */ 2284 void 2285 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2286 { 2287 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2288 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2289 ohci_soft_ed_t *sed = opipe->sed; 2290 ohci_soft_td_t *p, *n; 2291 ohci_physaddr_t headp; 2292 int hit; 2293 int wake; 2294 2295 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2296 2297 KASSERT(mutex_owned(&sc->sc_lock)); 2298 2299 if (sc->sc_dying) { 2300 /* If we're dying, just do the software part. */ 2301 xfer->status = status; /* make software ignore it */ 2302 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2303 usb_transfer_complete(xfer); 2304 return; 2305 } 2306 2307 if (cpu_intr_p() || cpu_softintr_p()) 2308 panic("ohci_abort_xfer: not in process context"); 2309 2310 /* 2311 * If an abort is already in progress then just wait for it to 2312 * complete and return. 2313 */ 2314 if (xfer->hcflags & UXFER_ABORTING) { 2315 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2316 #ifdef DIAGNOSTIC 2317 if (status == USBD_TIMEOUT) 2318 printf("%s: TIMEOUT while aborting\n", __func__); 2319 #endif 2320 /* Override the status which might be USBD_TIMEOUT. */ 2321 xfer->status = status; 2322 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2323 xfer->hcflags |= UXFER_ABORTWAIT; 2324 while (xfer->hcflags & UXFER_ABORTING) 2325 cv_wait(&xfer->hccv, &sc->sc_lock); 2326 goto done; 2327 } 2328 xfer->hcflags |= UXFER_ABORTING; 2329 2330 /* 2331 * Step 1: Make interrupt routine and hardware ignore xfer. 2332 */ 2333 xfer->status = status; /* make software ignore it */ 2334 callout_stop(&xfer->timeout_handle); 2335 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2336 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2337 sizeof(sed->ed.ed_flags), 2338 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2339 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2340 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2341 sizeof(sed->ed.ed_flags), 2342 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2343 2344 /* 2345 * Step 2: Wait until we know hardware has finished any possible 2346 * use of the xfer. Also make sure the soft interrupt routine 2347 * has run. 2348 */ 2349 /* Hardware finishes in 1ms */ 2350 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2351 sc->sc_softwake = 1; 2352 usb_schedsoftintr(&sc->sc_bus); 2353 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2354 2355 /* 2356 * Step 3: Remove any vestiges of the xfer from the hardware. 2357 * The complication here is that the hardware may have executed 2358 * beyond the xfer we're trying to abort. So as we're scanning 2359 * the TDs of this xfer we check if the hardware points to 2360 * any of them. 2361 */ 2362 p = xfer->hcpriv; 2363 #ifdef DIAGNOSTIC 2364 if (p == NULL) { 2365 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2366 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2367 goto done; 2368 } 2369 #endif 2370 #ifdef OHCI_DEBUG 2371 if (ohcidebug > 1) { 2372 DPRINTF(("ohci_abort_xfer: sed=\n")); 2373 ohci_dump_ed(sc, sed); 2374 ohci_dump_tds(sc, p); 2375 } 2376 #endif 2377 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2378 hit = 0; 2379 for (; p->xfer == xfer; p = n) { 2380 hit |= headp == p->physaddr; 2381 n = p->nexttd; 2382 ohci_free_std(sc, p); 2383 } 2384 /* Zap headp register if hardware pointed inside the xfer. */ 2385 if (hit) { 2386 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2387 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2388 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2389 usb_syncmem(&sed->dma, 2390 sed->offs + offsetof(ohci_ed_t, ed_headp), 2391 sizeof(sed->ed.ed_headp), 2392 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2393 } else { 2394 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2395 } 2396 2397 /* 2398 * Step 4: Turn on hardware again. 2399 */ 2400 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2401 sizeof(sed->ed.ed_flags), 2402 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2403 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2404 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2405 sizeof(sed->ed.ed_flags), 2406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2407 2408 /* 2409 * Step 5: Execute callback. 2410 */ 2411 wake = xfer->hcflags & UXFER_ABORTWAIT; 2412 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2413 usb_transfer_complete(xfer); 2414 if (wake) 2415 cv_broadcast(&xfer->hccv); 2416 2417 done: 2418 KASSERT(mutex_owned(&sc->sc_lock)); 2419 } 2420 2421 /* 2422 * Data structures and routines to emulate the root hub. 2423 */ 2424 Static usb_device_descriptor_t ohci_devd = { 2425 USB_DEVICE_DESCRIPTOR_SIZE, 2426 UDESC_DEVICE, /* type */ 2427 {0x00, 0x01}, /* USB version */ 2428 UDCLASS_HUB, /* class */ 2429 UDSUBCLASS_HUB, /* subclass */ 2430 UDPROTO_FSHUB, /* protocol */ 2431 64, /* max packet */ 2432 {0},{0},{0x00,0x01}, /* device id */ 2433 1,2,0, /* string indicies */ 2434 1 /* # of configurations */ 2435 }; 2436 2437 Static const usb_config_descriptor_t ohci_confd = { 2438 USB_CONFIG_DESCRIPTOR_SIZE, 2439 UDESC_CONFIG, 2440 {USB_CONFIG_DESCRIPTOR_SIZE + 2441 USB_INTERFACE_DESCRIPTOR_SIZE + 2442 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2443 1, 2444 1, 2445 0, 2446 UC_ATTR_MBO | UC_SELF_POWERED, 2447 0 /* max power */ 2448 }; 2449 2450 Static const usb_interface_descriptor_t ohci_ifcd = { 2451 USB_INTERFACE_DESCRIPTOR_SIZE, 2452 UDESC_INTERFACE, 2453 0, 2454 0, 2455 1, 2456 UICLASS_HUB, 2457 UISUBCLASS_HUB, 2458 UIPROTO_FSHUB, 2459 0 2460 }; 2461 2462 Static const usb_endpoint_descriptor_t ohci_endpd = { 2463 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2464 .bDescriptorType = UDESC_ENDPOINT, 2465 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2466 .bmAttributes = UE_INTERRUPT, 2467 .wMaxPacketSize = {8, 0}, /* max packet */ 2468 .bInterval = 255, 2469 }; 2470 2471 Static const usb_hub_descriptor_t ohci_hubd = { 2472 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2473 .bDescriptorType = UDESC_HUB, 2474 }; 2475 2476 /* 2477 * Simulate a hardware hub by handling all the necessary requests. 2478 */ 2479 Static usbd_status 2480 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2481 { 2482 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2483 usbd_status err; 2484 2485 /* Insert last in queue. */ 2486 mutex_enter(&sc->sc_lock); 2487 err = usb_insert_transfer(xfer); 2488 mutex_exit(&sc->sc_lock); 2489 if (err) 2490 return (err); 2491 2492 /* Pipe isn't running, start first */ 2493 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2494 } 2495 2496 Static usbd_status 2497 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2498 { 2499 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2500 usb_device_request_t *req; 2501 void *buf = NULL; 2502 int port, i; 2503 int len, value, index, l, totlen = 0; 2504 usb_port_status_t ps; 2505 usb_hub_descriptor_t hubd; 2506 usbd_status err; 2507 u_int32_t v; 2508 2509 if (sc->sc_dying) 2510 return (USBD_IOERROR); 2511 2512 #ifdef DIAGNOSTIC 2513 if (!(xfer->rqflags & URQ_REQUEST)) 2514 /* XXX panic */ 2515 return (USBD_INVAL); 2516 #endif 2517 req = &xfer->request; 2518 2519 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2520 req->bmRequestType, req->bRequest)); 2521 2522 len = UGETW(req->wLength); 2523 value = UGETW(req->wValue); 2524 index = UGETW(req->wIndex); 2525 2526 if (len != 0) 2527 buf = KERNADDR(&xfer->dmabuf, 0); 2528 2529 #define C(x,y) ((x) | ((y) << 8)) 2530 switch(C(req->bRequest, req->bmRequestType)) { 2531 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2532 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2533 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2534 /* 2535 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2536 * for the integrated root hub. 2537 */ 2538 break; 2539 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2540 if (len > 0) { 2541 *(u_int8_t *)buf = sc->sc_conf; 2542 totlen = 1; 2543 } 2544 break; 2545 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2546 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2547 if (len == 0) 2548 break; 2549 switch(value >> 8) { 2550 case UDESC_DEVICE: 2551 if ((value & 0xff) != 0) { 2552 err = USBD_IOERROR; 2553 goto ret; 2554 } 2555 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2556 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2557 memcpy(buf, &ohci_devd, l); 2558 break; 2559 case UDESC_CONFIG: 2560 if ((value & 0xff) != 0) { 2561 err = USBD_IOERROR; 2562 goto ret; 2563 } 2564 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2565 memcpy(buf, &ohci_confd, l); 2566 buf = (char *)buf + l; 2567 len -= l; 2568 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2569 totlen += l; 2570 memcpy(buf, &ohci_ifcd, l); 2571 buf = (char *)buf + l; 2572 len -= l; 2573 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2574 totlen += l; 2575 memcpy(buf, &ohci_endpd, l); 2576 break; 2577 case UDESC_STRING: 2578 #define sd ((usb_string_descriptor_t *)buf) 2579 switch (value & 0xff) { 2580 case 0: /* Language table */ 2581 totlen = usb_makelangtbl(sd, len); 2582 break; 2583 case 1: /* Vendor */ 2584 totlen = usb_makestrdesc(sd, len, 2585 sc->sc_vendor); 2586 break; 2587 case 2: /* Product */ 2588 totlen = usb_makestrdesc(sd, len, 2589 "OHCI root hub"); 2590 break; 2591 } 2592 #undef sd 2593 break; 2594 default: 2595 err = USBD_IOERROR; 2596 goto ret; 2597 } 2598 break; 2599 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2600 if (len > 0) { 2601 *(u_int8_t *)buf = 0; 2602 totlen = 1; 2603 } 2604 break; 2605 case C(UR_GET_STATUS, UT_READ_DEVICE): 2606 if (len > 1) { 2607 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2608 totlen = 2; 2609 } 2610 break; 2611 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2612 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2613 if (len > 1) { 2614 USETW(((usb_status_t *)buf)->wStatus, 0); 2615 totlen = 2; 2616 } 2617 break; 2618 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2619 if (value >= USB_MAX_DEVICES) { 2620 err = USBD_IOERROR; 2621 goto ret; 2622 } 2623 sc->sc_addr = value; 2624 break; 2625 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2626 if (value != 0 && value != 1) { 2627 err = USBD_IOERROR; 2628 goto ret; 2629 } 2630 sc->sc_conf = value; 2631 break; 2632 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2633 break; 2634 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2635 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2636 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2637 err = USBD_IOERROR; 2638 goto ret; 2639 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2640 break; 2641 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2642 break; 2643 /* Hub requests */ 2644 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2645 break; 2646 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2647 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2648 "port=%d feature=%d\n", 2649 index, value)); 2650 if (index < 1 || index > sc->sc_noport) { 2651 err = USBD_IOERROR; 2652 goto ret; 2653 } 2654 port = OHCI_RH_PORT_STATUS(index); 2655 switch(value) { 2656 case UHF_PORT_ENABLE: 2657 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2658 break; 2659 case UHF_PORT_SUSPEND: 2660 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2661 break; 2662 case UHF_PORT_POWER: 2663 /* Yes, writing to the LOW_SPEED bit clears power. */ 2664 OWRITE4(sc, port, UPS_LOW_SPEED); 2665 break; 2666 case UHF_C_PORT_CONNECTION: 2667 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2668 break; 2669 case UHF_C_PORT_ENABLE: 2670 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2671 break; 2672 case UHF_C_PORT_SUSPEND: 2673 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2674 break; 2675 case UHF_C_PORT_OVER_CURRENT: 2676 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2677 break; 2678 case UHF_C_PORT_RESET: 2679 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2680 break; 2681 default: 2682 err = USBD_IOERROR; 2683 goto ret; 2684 } 2685 switch(value) { 2686 case UHF_C_PORT_CONNECTION: 2687 case UHF_C_PORT_ENABLE: 2688 case UHF_C_PORT_SUSPEND: 2689 case UHF_C_PORT_OVER_CURRENT: 2690 case UHF_C_PORT_RESET: 2691 /* Enable RHSC interrupt if condition is cleared. */ 2692 if ((OREAD4(sc, port) >> 16) == 0) 2693 ohci_rhsc_enable(sc); 2694 break; 2695 default: 2696 break; 2697 } 2698 break; 2699 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2700 if (len == 0) 2701 break; 2702 if ((value & 0xff) != 0) { 2703 err = USBD_IOERROR; 2704 goto ret; 2705 } 2706 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2707 hubd = ohci_hubd; 2708 hubd.bNbrPorts = sc->sc_noport; 2709 USETW(hubd.wHubCharacteristics, 2710 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2711 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2712 /* XXX overcurrent */ 2713 ); 2714 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2715 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2716 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2717 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2718 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2719 l = min(len, hubd.bDescLength); 2720 totlen = l; 2721 memcpy(buf, &hubd, l); 2722 break; 2723 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2724 if (len != 4) { 2725 err = USBD_IOERROR; 2726 goto ret; 2727 } 2728 memset(buf, 0, len); /* ? XXX */ 2729 totlen = len; 2730 break; 2731 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2732 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2733 index)); 2734 if (index < 1 || index > sc->sc_noport) { 2735 err = USBD_IOERROR; 2736 goto ret; 2737 } 2738 if (len != 4) { 2739 err = USBD_IOERROR; 2740 goto ret; 2741 } 2742 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2743 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2744 v)); 2745 USETW(ps.wPortStatus, v); 2746 USETW(ps.wPortChange, v >> 16); 2747 l = min(len, sizeof ps); 2748 memcpy(buf, &ps, l); 2749 totlen = l; 2750 break; 2751 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2752 err = USBD_IOERROR; 2753 goto ret; 2754 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2755 break; 2756 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2757 if (index < 1 || index > sc->sc_noport) { 2758 err = USBD_IOERROR; 2759 goto ret; 2760 } 2761 port = OHCI_RH_PORT_STATUS(index); 2762 switch(value) { 2763 case UHF_PORT_ENABLE: 2764 OWRITE4(sc, port, UPS_PORT_ENABLED); 2765 break; 2766 case UHF_PORT_SUSPEND: 2767 OWRITE4(sc, port, UPS_SUSPEND); 2768 break; 2769 case UHF_PORT_RESET: 2770 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2771 index)); 2772 OWRITE4(sc, port, UPS_RESET); 2773 for (i = 0; i < 5; i++) { 2774 usb_delay_ms(&sc->sc_bus, 2775 USB_PORT_ROOT_RESET_DELAY); 2776 if (sc->sc_dying) { 2777 err = USBD_IOERROR; 2778 goto ret; 2779 } 2780 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2781 break; 2782 } 2783 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2784 index, OREAD4(sc, port))); 2785 break; 2786 case UHF_PORT_POWER: 2787 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2788 "%d\n", index)); 2789 OWRITE4(sc, port, UPS_PORT_POWER); 2790 break; 2791 default: 2792 err = USBD_IOERROR; 2793 goto ret; 2794 } 2795 break; 2796 default: 2797 err = USBD_IOERROR; 2798 goto ret; 2799 } 2800 xfer->actlen = totlen; 2801 err = USBD_NORMAL_COMPLETION; 2802 ret: 2803 xfer->status = err; 2804 mutex_enter(&sc->sc_lock); 2805 usb_transfer_complete(xfer); 2806 mutex_exit(&sc->sc_lock); 2807 return (USBD_IN_PROGRESS); 2808 } 2809 2810 /* Abort a root control request. */ 2811 Static void 2812 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2813 { 2814 /* Nothing to do, all transfers are synchronous. */ 2815 } 2816 2817 /* Close the root pipe. */ 2818 Static void 2819 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2820 { 2821 DPRINTF(("ohci_root_ctrl_close\n")); 2822 /* Nothing to do. */ 2823 } 2824 2825 Static usbd_status 2826 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2827 { 2828 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2829 usbd_status err; 2830 2831 /* Insert last in queue. */ 2832 mutex_enter(&sc->sc_lock); 2833 err = usb_insert_transfer(xfer); 2834 mutex_exit(&sc->sc_lock); 2835 if (err) 2836 return (err); 2837 2838 /* Pipe isn't running, start first */ 2839 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2840 } 2841 2842 Static usbd_status 2843 ohci_root_intr_start(usbd_xfer_handle xfer) 2844 { 2845 usbd_pipe_handle pipe = xfer->pipe; 2846 ohci_softc_t *sc = pipe->device->bus->hci_private; 2847 2848 if (sc->sc_dying) 2849 return (USBD_IOERROR); 2850 2851 mutex_enter(&sc->sc_lock); 2852 KASSERT(sc->sc_intrxfer == NULL); 2853 sc->sc_intrxfer = xfer; 2854 mutex_exit(&sc->sc_lock); 2855 2856 return (USBD_IN_PROGRESS); 2857 } 2858 2859 /* Abort a root interrupt request. */ 2860 Static void 2861 ohci_root_intr_abort(usbd_xfer_handle xfer) 2862 { 2863 #ifdef DIAGNOSTIC 2864 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2865 #endif 2866 2867 KASSERT(mutex_owned(&sc->sc_lock)); 2868 2869 if (xfer->pipe->intrxfer == xfer) { 2870 DPRINTF(("ohci_root_intr_abort: remove\n")); 2871 xfer->pipe->intrxfer = NULL; 2872 } 2873 xfer->status = USBD_CANCELLED; 2874 usb_transfer_complete(xfer); 2875 } 2876 2877 /* Close the root pipe. */ 2878 Static void 2879 ohci_root_intr_close(usbd_pipe_handle pipe) 2880 { 2881 ohci_softc_t *sc = pipe->device->bus->hci_private; 2882 2883 KASSERT(mutex_owned(&sc->sc_lock)); 2884 2885 DPRINTF(("ohci_root_intr_close\n")); 2886 2887 sc->sc_intrxfer = NULL; 2888 } 2889 2890 /************************/ 2891 2892 Static usbd_status 2893 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2894 { 2895 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2896 usbd_status err; 2897 2898 /* Insert last in queue. */ 2899 mutex_enter(&sc->sc_lock); 2900 err = usb_insert_transfer(xfer); 2901 mutex_exit(&sc->sc_lock); 2902 if (err) 2903 return (err); 2904 2905 /* Pipe isn't running, start first */ 2906 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2907 } 2908 2909 Static usbd_status 2910 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2911 { 2912 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2913 usbd_status err; 2914 2915 if (sc->sc_dying) 2916 return (USBD_IOERROR); 2917 2918 #ifdef DIAGNOSTIC 2919 if (!(xfer->rqflags & URQ_REQUEST)) { 2920 /* XXX panic */ 2921 printf("ohci_device_ctrl_transfer: not a request\n"); 2922 return (USBD_INVAL); 2923 } 2924 #endif 2925 2926 mutex_enter(&sc->sc_lock); 2927 err = ohci_device_request(xfer); 2928 mutex_exit(&sc->sc_lock); 2929 if (err) 2930 return (err); 2931 2932 if (sc->sc_bus.use_polling) 2933 ohci_waitintr(sc, xfer); 2934 return (USBD_IN_PROGRESS); 2935 } 2936 2937 /* Abort a device control request. */ 2938 Static void 2939 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2940 { 2941 #ifdef DIAGNOSTIC 2942 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2943 #endif 2944 2945 KASSERT(mutex_owned(&sc->sc_lock)); 2946 2947 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2948 ohci_abort_xfer(xfer, USBD_CANCELLED); 2949 } 2950 2951 /* Close a device control pipe. */ 2952 Static void 2953 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2954 { 2955 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2956 ohci_softc_t *sc = pipe->device->bus->hci_private; 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2961 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2962 ohci_free_std(sc, opipe->tail.td); 2963 } 2964 2965 /************************/ 2966 2967 Static void 2968 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2969 { 2970 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2971 ohci_softc_t *sc = pipe->device->bus->hci_private; 2972 2973 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2974 } 2975 2976 Static void 2977 ohci_noop(usbd_pipe_handle pipe) 2978 { 2979 } 2980 2981 Static usbd_status 2982 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2983 { 2984 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2985 usbd_status err; 2986 2987 /* Insert last in queue. */ 2988 mutex_enter(&sc->sc_lock); 2989 err = usb_insert_transfer(xfer); 2990 mutex_exit(&sc->sc_lock); 2991 if (err) 2992 return (err); 2993 2994 /* Pipe isn't running, start first */ 2995 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2996 } 2997 2998 Static usbd_status 2999 ohci_device_bulk_start(usbd_xfer_handle xfer) 3000 { 3001 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3002 usbd_device_handle dev = opipe->pipe.device; 3003 ohci_softc_t *sc = dev->bus->hci_private; 3004 int addr = dev->address; 3005 ohci_soft_td_t *data, *tail, *tdp; 3006 ohci_soft_ed_t *sed; 3007 int len, isread, endpt; 3008 usbd_status err; 3009 3010 if (sc->sc_dying) 3011 return (USBD_IOERROR); 3012 3013 #ifdef DIAGNOSTIC 3014 if (xfer->rqflags & URQ_REQUEST) { 3015 /* XXX panic */ 3016 printf("ohci_device_bulk_start: a request\n"); 3017 return (USBD_INVAL); 3018 } 3019 #endif 3020 3021 mutex_enter(&sc->sc_lock); 3022 3023 len = xfer->length; 3024 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3025 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3026 sed = opipe->sed; 3027 3028 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3029 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3030 endpt)); 3031 3032 opipe->u.bulk.isread = isread; 3033 opipe->u.bulk.length = len; 3034 3035 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3037 /* Update device address */ 3038 sed->ed.ed_flags = HTOO32( 3039 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3040 OHCI_ED_SET_FA(addr)); 3041 3042 /* Allocate a chain of new TDs (including a new tail). */ 3043 data = opipe->tail.td; 3044 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3045 data, &tail); 3046 if (err) 3047 return err; 3048 3049 /* We want interrupt at the end of the transfer. */ 3050 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3051 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3052 tail->flags |= OHCI_CALL_DONE; 3053 tail = tail->nexttd; /* point at sentinel */ 3054 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3055 sizeof(tail->td.td_flags), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 if (err) { 3058 mutex_exit(&sc->sc_lock); 3059 return (err); 3060 } 3061 3062 tail->xfer = NULL; 3063 xfer->hcpriv = data; 3064 3065 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3066 "td_cbp=0x%08x td_be=0x%08x\n", 3067 (int)O32TOH(sed->ed.ed_flags), 3068 (int)O32TOH(data->td.td_flags), 3069 (int)O32TOH(data->td.td_cbp), 3070 (int)O32TOH(data->td.td_be))); 3071 3072 #ifdef OHCI_DEBUG 3073 if (ohcidebug > 5) { 3074 ohci_dump_ed(sc, sed); 3075 ohci_dump_tds(sc, data); 3076 } 3077 #endif 3078 3079 /* Insert ED in schedule */ 3080 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3081 tdp->xfer = xfer; 3082 } 3083 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3084 opipe->tail.td = tail; 3085 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3086 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3088 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3089 if (xfer->timeout && !sc->sc_bus.use_polling) { 3090 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3091 ohci_timeout, xfer); 3092 } 3093 mutex_exit(&sc->sc_lock); 3094 3095 #if 0 3096 /* This goes wrong if we are too slow. */ 3097 if (ohcidebug > 10) { 3098 delay(10000); 3099 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3100 OREAD4(sc, OHCI_COMMAND_STATUS))); 3101 ohci_dump_ed(sc, sed); 3102 ohci_dump_tds(sc, data); 3103 } 3104 #endif 3105 3106 return (USBD_IN_PROGRESS); 3107 } 3108 3109 Static void 3110 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3111 { 3112 #ifdef DIAGNOSTIC 3113 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3114 #endif 3115 3116 KASSERT(mutex_owned(&sc->sc_lock)); 3117 3118 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3119 ohci_abort_xfer(xfer, USBD_CANCELLED); 3120 } 3121 3122 /* 3123 * Close a device bulk pipe. 3124 */ 3125 Static void 3126 ohci_device_bulk_close(usbd_pipe_handle pipe) 3127 { 3128 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3129 ohci_softc_t *sc = pipe->device->bus->hci_private; 3130 3131 KASSERT(mutex_owned(&sc->sc_lock)); 3132 3133 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3134 ohci_close_pipe(pipe, sc->sc_bulk_head); 3135 ohci_free_std(sc, opipe->tail.td); 3136 } 3137 3138 /************************/ 3139 3140 Static usbd_status 3141 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3142 { 3143 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3144 usbd_status err; 3145 3146 /* Insert last in queue. */ 3147 mutex_enter(&sc->sc_lock); 3148 err = usb_insert_transfer(xfer); 3149 mutex_exit(&sc->sc_lock); 3150 if (err) 3151 return (err); 3152 3153 /* Pipe isn't running, start first */ 3154 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3155 } 3156 3157 Static usbd_status 3158 ohci_device_intr_start(usbd_xfer_handle xfer) 3159 { 3160 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3161 usbd_device_handle dev = opipe->pipe.device; 3162 ohci_softc_t *sc = dev->bus->hci_private; 3163 ohci_soft_ed_t *sed = opipe->sed; 3164 ohci_soft_td_t *data, *tail; 3165 int len, isread, endpt; 3166 3167 if (sc->sc_dying) 3168 return (USBD_IOERROR); 3169 3170 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3171 "flags=%d priv=%p\n", 3172 xfer, xfer->length, xfer->flags, xfer->priv)); 3173 3174 #ifdef DIAGNOSTIC 3175 if (xfer->rqflags & URQ_REQUEST) 3176 panic("ohci_device_intr_transfer: a request"); 3177 #endif 3178 3179 len = xfer->length; 3180 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3181 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3182 3183 data = opipe->tail.td; 3184 mutex_enter(&sc->sc_lock); 3185 tail = ohci_alloc_std(sc); 3186 mutex_exit(&sc->sc_lock); 3187 if (tail == NULL) 3188 return (USBD_NOMEM); 3189 tail->xfer = NULL; 3190 3191 data->td.td_flags = HTOO32( 3192 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3193 OHCI_TD_NOCC | 3194 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3195 if (xfer->flags & USBD_SHORT_XFER_OK) 3196 data->td.td_flags |= HTOO32(OHCI_TD_R); 3197 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3198 data->nexttd = tail; 3199 data->td.td_nexttd = HTOO32(tail->physaddr); 3200 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3201 data->len = len; 3202 data->xfer = xfer; 3203 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3204 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 xfer->hcpriv = data; 3207 3208 #ifdef OHCI_DEBUG 3209 if (ohcidebug > 5) { 3210 DPRINTF(("ohci_device_intr_transfer:\n")); 3211 ohci_dump_ed(sc, sed); 3212 ohci_dump_tds(sc, data); 3213 } 3214 #endif 3215 3216 /* Insert ED in schedule */ 3217 mutex_enter(&sc->sc_lock); 3218 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3219 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3220 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3221 opipe->tail.td = tail; 3222 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3223 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3224 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3225 3226 #if 0 3227 /* 3228 * This goes horribly wrong, printing thousands of descriptors, 3229 * because false references are followed due to the fact that the 3230 * TD is gone. 3231 */ 3232 if (ohcidebug > 5) { 3233 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3234 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3235 OREAD4(sc, OHCI_COMMAND_STATUS))); 3236 ohci_dump_ed(sc, sed); 3237 ohci_dump_tds(sc, data); 3238 } 3239 #endif 3240 mutex_exit(&sc->sc_lock); 3241 3242 return (USBD_IN_PROGRESS); 3243 } 3244 3245 /* Abort a device interrupt request. */ 3246 Static void 3247 ohci_device_intr_abort(usbd_xfer_handle xfer) 3248 { 3249 #ifdef DIAGNOSTIC 3250 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3251 #endif 3252 3253 KASSERT(mutex_owned(&sc->sc_lock)); 3254 3255 if (xfer->pipe->intrxfer == xfer) { 3256 DPRINTF(("ohci_device_intr_abort: remove\n")); 3257 xfer->pipe->intrxfer = NULL; 3258 } 3259 ohci_abort_xfer(xfer, USBD_CANCELLED); 3260 } 3261 3262 /* Close a device interrupt pipe. */ 3263 Static void 3264 ohci_device_intr_close(usbd_pipe_handle pipe) 3265 { 3266 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3267 ohci_softc_t *sc = pipe->device->bus->hci_private; 3268 int nslots = opipe->u.intr.nslots; 3269 int pos = opipe->u.intr.pos; 3270 int j; 3271 ohci_soft_ed_t *p, *sed = opipe->sed; 3272 3273 KASSERT(mutex_owned(&sc->sc_lock)); 3274 3275 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3276 pipe, nslots, pos)); 3277 usb_syncmem(&sed->dma, sed->offs, 3278 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3279 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3280 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3281 sizeof(sed->ed.ed_flags), 3282 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3283 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3284 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3285 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3286 3287 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3288 continue; 3289 #ifdef DIAGNOSTIC 3290 if (p == NULL) 3291 panic("ohci_device_intr_close: ED not found"); 3292 #endif 3293 p->next = sed->next; 3294 p->ed.ed_nexted = sed->ed.ed_nexted; 3295 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3296 sizeof(p->ed.ed_nexted), 3297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3298 3299 for (j = 0; j < nslots; j++) 3300 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3301 3302 ohci_free_std(sc, opipe->tail.td); 3303 ohci_free_sed(sc, opipe->sed); 3304 } 3305 3306 Static usbd_status 3307 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3308 { 3309 int i, j, best; 3310 u_int npoll, slow, shigh, nslots; 3311 u_int bestbw, bw; 3312 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3313 3314 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3315 if (ival == 0) { 3316 printf("ohci_setintr: 0 interval\n"); 3317 return (USBD_INVAL); 3318 } 3319 3320 npoll = OHCI_NO_INTRS; 3321 while (npoll > ival) 3322 npoll /= 2; 3323 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3324 3325 /* 3326 * We now know which level in the tree the ED must go into. 3327 * Figure out which slot has most bandwidth left over. 3328 * Slots to examine: 3329 * npoll 3330 * 1 0 3331 * 2 1 2 3332 * 4 3 4 5 6 3333 * 8 7 8 9 10 11 12 13 14 3334 * N (N-1) .. (N-1+N-1) 3335 */ 3336 slow = npoll-1; 3337 shigh = slow + npoll; 3338 nslots = OHCI_NO_INTRS / npoll; 3339 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3340 bw = 0; 3341 for (j = 0; j < nslots; j++) 3342 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3343 if (bw < bestbw) { 3344 best = i; 3345 bestbw = bw; 3346 } 3347 } 3348 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3349 best, slow, shigh, bestbw)); 3350 3351 mutex_enter(&sc->sc_lock); 3352 hsed = sc->sc_eds[best]; 3353 sed->next = hsed->next; 3354 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3355 sizeof(hsed->ed.ed_flags), 3356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3357 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3358 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3359 sizeof(sed->ed.ed_flags), 3360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3361 hsed->next = sed; 3362 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3363 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3364 sizeof(hsed->ed.ed_flags), 3365 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3366 mutex_exit(&sc->sc_lock); 3367 3368 for (j = 0; j < nslots; j++) 3369 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3370 opipe->u.intr.nslots = nslots; 3371 opipe->u.intr.pos = best; 3372 3373 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3374 return (USBD_NORMAL_COMPLETION); 3375 } 3376 3377 /***********************/ 3378 3379 usbd_status 3380 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3381 { 3382 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3383 usbd_status err; 3384 3385 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3386 3387 /* Put it on our queue, */ 3388 mutex_enter(&sc->sc_lock); 3389 err = usb_insert_transfer(xfer); 3390 mutex_exit(&sc->sc_lock); 3391 3392 /* bail out on error, */ 3393 if (err && err != USBD_IN_PROGRESS) 3394 return (err); 3395 3396 /* XXX should check inuse here */ 3397 3398 /* insert into schedule, */ 3399 ohci_device_isoc_enter(xfer); 3400 3401 /* and start if the pipe wasn't running */ 3402 if (!err) 3403 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3404 3405 return (err); 3406 } 3407 3408 void 3409 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3410 { 3411 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3412 usbd_device_handle dev = opipe->pipe.device; 3413 ohci_softc_t *sc = dev->bus->hci_private; 3414 ohci_soft_ed_t *sed = opipe->sed; 3415 struct iso *iso = &opipe->u.iso; 3416 ohci_soft_itd_t *sitd, *nsitd; 3417 ohci_physaddr_t buf, offs, noffs, bp0; 3418 int i, ncur, nframes; 3419 3420 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3421 "nframes=%d\n", 3422 iso->inuse, iso->next, xfer, xfer->nframes)); 3423 3424 if (sc->sc_dying) 3425 return; 3426 3427 if (iso->next == -1) { 3428 /* Not in use yet, schedule it a few frames ahead. */ 3429 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3430 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3431 iso->next)); 3432 } 3433 3434 sitd = opipe->tail.itd; 3435 buf = DMAADDR(&xfer->dmabuf, 0); 3436 bp0 = OHCI_PAGE(buf); 3437 offs = OHCI_PAGE_OFFSET(buf); 3438 nframes = xfer->nframes; 3439 xfer->hcpriv = sitd; 3440 for (i = ncur = 0; i < nframes; i++, ncur++) { 3441 noffs = offs + xfer->frlengths[i]; 3442 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3443 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3444 3445 /* Allocate next ITD */ 3446 mutex_enter(&sc->sc_lock); 3447 nsitd = ohci_alloc_sitd(sc); 3448 mutex_exit(&sc->sc_lock); 3449 if (nsitd == NULL) { 3450 /* XXX what now? */ 3451 printf("%s: isoc TD alloc failed\n", 3452 device_xname(sc->sc_dev)); 3453 return; 3454 } 3455 3456 /* Fill current ITD */ 3457 sitd->itd.itd_flags = HTOO32( 3458 OHCI_ITD_NOCC | 3459 OHCI_ITD_SET_SF(iso->next) | 3460 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3461 OHCI_ITD_SET_FC(ncur)); 3462 sitd->itd.itd_bp0 = HTOO32(bp0); 3463 sitd->nextitd = nsitd; 3464 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3465 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3466 sitd->xfer = xfer; 3467 sitd->flags = 0; 3468 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3470 3471 sitd = nsitd; 3472 iso->next = iso->next + ncur; 3473 bp0 = OHCI_PAGE(buf + offs); 3474 ncur = 0; 3475 } 3476 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3477 offs = noffs; 3478 } 3479 mutex_enter(&sc->sc_lock); 3480 nsitd = ohci_alloc_sitd(sc); 3481 mutex_exit(&sc->sc_lock); 3482 if (nsitd == NULL) { 3483 /* XXX what now? */ 3484 printf("%s: isoc TD alloc failed\n", 3485 device_xname(sc->sc_dev)); 3486 return; 3487 } 3488 /* Fixup last used ITD */ 3489 sitd->itd.itd_flags = HTOO32( 3490 OHCI_ITD_NOCC | 3491 OHCI_ITD_SET_SF(iso->next) | 3492 OHCI_ITD_SET_DI(0) | 3493 OHCI_ITD_SET_FC(ncur)); 3494 sitd->itd.itd_bp0 = HTOO32(bp0); 3495 sitd->nextitd = nsitd; 3496 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3497 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3498 sitd->xfer = xfer; 3499 sitd->flags = OHCI_CALL_DONE; 3500 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3502 3503 iso->next = iso->next + ncur; 3504 iso->inuse += nframes; 3505 3506 xfer->actlen = offs; /* XXX pretend we did it all */ 3507 3508 xfer->status = USBD_IN_PROGRESS; 3509 3510 #ifdef OHCI_DEBUG 3511 if (ohcidebug > 5) { 3512 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3513 O32TOH(sc->sc_hcca->hcca_frame_number))); 3514 ohci_dump_itds(sc, xfer->hcpriv); 3515 ohci_dump_ed(sc, sed); 3516 } 3517 #endif 3518 3519 mutex_enter(&sc->sc_lock); 3520 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3521 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3522 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3523 opipe->tail.itd = nsitd; 3524 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3525 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3526 sizeof(sed->ed.ed_flags), 3527 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3528 mutex_exit(&sc->sc_lock); 3529 3530 #ifdef OHCI_DEBUG 3531 if (ohcidebug > 5) { 3532 delay(150000); 3533 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3534 O32TOH(sc->sc_hcca->hcca_frame_number))); 3535 ohci_dump_itds(sc, xfer->hcpriv); 3536 ohci_dump_ed(sc, sed); 3537 } 3538 #endif 3539 } 3540 3541 usbd_status 3542 ohci_device_isoc_start(usbd_xfer_handle xfer) 3543 { 3544 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3545 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3546 3547 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3548 3549 mutex_enter(&sc->sc_lock); 3550 3551 if (sc->sc_dying) { 3552 mutex_exit(&sc->sc_lock); 3553 return (USBD_IOERROR); 3554 } 3555 3556 #ifdef DIAGNOSTIC 3557 if (xfer->status != USBD_IN_PROGRESS) 3558 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3559 #endif 3560 3561 /* XXX anything to do? */ 3562 3563 mutex_exit(&sc->sc_lock); 3564 3565 return (USBD_IN_PROGRESS); 3566 } 3567 3568 void 3569 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3570 { 3571 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3572 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3573 ohci_soft_ed_t *sed; 3574 ohci_soft_itd_t *sitd; 3575 3576 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3577 3578 KASSERT(mutex_owned(&sc->sc_lock)); 3579 3580 /* Transfer is already done. */ 3581 if (xfer->status != USBD_NOT_STARTED && 3582 xfer->status != USBD_IN_PROGRESS) { 3583 printf("ohci_device_isoc_abort: early return\n"); 3584 goto done; 3585 } 3586 3587 /* Give xfer the requested abort code. */ 3588 xfer->status = USBD_CANCELLED; 3589 3590 sed = opipe->sed; 3591 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3592 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3593 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3594 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3595 sizeof(sed->ed.ed_flags), 3596 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3597 3598 sitd = xfer->hcpriv; 3599 #ifdef DIAGNOSTIC 3600 if (sitd == NULL) { 3601 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3602 goto done; 3603 } 3604 #endif 3605 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3606 #ifdef DIAGNOSTIC 3607 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3608 sitd->isdone = 1; 3609 #endif 3610 } 3611 3612 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3613 3614 /* Run callback. */ 3615 usb_transfer_complete(xfer); 3616 3617 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3618 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3619 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3620 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3621 3622 done: 3623 KASSERT(mutex_owned(&sc->sc_lock)); 3624 } 3625 3626 void 3627 ohci_device_isoc_done(usbd_xfer_handle xfer) 3628 { 3629 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3630 } 3631 3632 usbd_status 3633 ohci_setup_isoc(usbd_pipe_handle pipe) 3634 { 3635 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3636 ohci_softc_t *sc = pipe->device->bus->hci_private; 3637 struct iso *iso = &opipe->u.iso; 3638 3639 iso->next = -1; 3640 iso->inuse = 0; 3641 3642 mutex_enter(&sc->sc_lock); 3643 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3644 mutex_exit(&sc->sc_lock); 3645 3646 return (USBD_NORMAL_COMPLETION); 3647 } 3648 3649 void 3650 ohci_device_isoc_close(usbd_pipe_handle pipe) 3651 { 3652 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3653 ohci_softc_t *sc = pipe->device->bus->hci_private; 3654 3655 KASSERT(mutex_owned(&sc->sc_lock)); 3656 3657 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3658 ohci_close_pipe(pipe, sc->sc_isoc_head); 3659 #ifdef DIAGNOSTIC 3660 opipe->tail.itd->isdone = 1; 3661 #endif 3662 ohci_free_sitd(sc, opipe->tail.itd); 3663 } 3664
Indexes created Wed Sep 24 22:09:59 GMT 2025