ohci.c revision 1.245
1 /* $NetBSD: ohci.c,v 1.245 2013/12/01 07:28:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.245 2013/12/01 07:28:47 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_status ohci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 131 Static void ohci_freem(struct usbd_bus *, usb_dma_t *); 132 133 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 134 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 135 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 136 137 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 138 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 139 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 140 Static void ohci_root_ctrl_close(usbd_pipe_handle); 141 Static void ohci_root_ctrl_done(usbd_xfer_handle); 142 143 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 144 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 145 Static void ohci_root_intr_abort(usbd_xfer_handle); 146 Static void ohci_root_intr_close(usbd_pipe_handle); 147 Static void ohci_root_intr_done(usbd_xfer_handle); 148 149 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 150 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 151 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 152 Static void ohci_device_ctrl_close(usbd_pipe_handle); 153 Static void ohci_device_ctrl_done(usbd_xfer_handle); 154 155 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 156 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 157 Static void ohci_device_bulk_abort(usbd_xfer_handle); 158 Static void ohci_device_bulk_close(usbd_pipe_handle); 159 Static void ohci_device_bulk_done(usbd_xfer_handle); 160 161 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 162 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 163 Static void ohci_device_intr_abort(usbd_xfer_handle); 164 Static void ohci_device_intr_close(usbd_pipe_handle); 165 Static void ohci_device_intr_done(usbd_xfer_handle); 166 167 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 168 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 169 Static void ohci_device_isoc_abort(usbd_xfer_handle); 170 Static void ohci_device_isoc_close(usbd_pipe_handle); 171 Static void ohci_device_isoc_done(usbd_xfer_handle); 172 173 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 174 struct ohci_pipe *pipe, int ival); 175 176 Static void ohci_timeout(void *); 177 Static void ohci_timeout_task(void *); 178 Static void ohci_rhsc_enable(void *); 179 180 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 181 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 182 183 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ohci_noop(usbd_pipe_handle pipe); 185 186 #ifdef OHCI_DEBUG 187 Static void ohci_dumpregs(ohci_softc_t *); 188 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 189 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 190 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 191 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 192 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 193 #endif 194 195 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 196 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 197 #define OWRITE1(sc, r, x) \ 198 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 199 #define OWRITE2(sc, r, x) \ 200 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 201 #define OWRITE4(sc, r, x) \ 202 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 203 204 static __inline uint32_t 205 OREAD4(ohci_softc_t *sc, bus_size_t r) 206 { 207 208 OBARR(sc); 209 return bus_space_read_4(sc->iot, sc->ioh, r); 210 } 211 212 /* Reverse the bits in a value 0 .. 31 */ 213 Static u_int8_t revbits[OHCI_NO_INTRS] = 214 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 215 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 216 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 217 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 218 219 struct ohci_pipe { 220 struct usbd_pipe pipe; 221 ohci_soft_ed_t *sed; 222 union { 223 ohci_soft_td_t *td; 224 ohci_soft_itd_t *itd; 225 } tail; 226 /* Info needed for different pipe kinds. */ 227 union { 228 /* Control pipe */ 229 struct { 230 usb_dma_t reqdma; 231 u_int length; 232 ohci_soft_td_t *setup, *data, *stat; 233 } ctl; 234 /* Interrupt pipe */ 235 struct { 236 int nslots; 237 int pos; 238 } intr; 239 /* Bulk pipe */ 240 struct { 241 u_int length; 242 int isread; 243 } bulk; 244 /* Iso pipe */ 245 struct iso { 246 int next, inuse; 247 } iso; 248 } u; 249 }; 250 251 #define OHCI_INTR_ENDPT 1 252 253 Static const struct usbd_bus_methods ohci_bus_methods = { 254 .open_pipe = ohci_open, 255 .soft_intr = ohci_softintr, 256 .do_poll = ohci_poll, 257 .allocm = ohci_allocm, 258 .freem = ohci_freem, 259 .allocx = ohci_allocx, 260 .freex = ohci_freex, 261 .get_lock = ohci_get_lock, 262 .new_device = NULL, 263 }; 264 265 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 266 .transfer = ohci_root_ctrl_transfer, 267 .start = ohci_root_ctrl_start, 268 .abort = ohci_root_ctrl_abort, 269 .close = ohci_root_ctrl_close, 270 .cleartoggle = ohci_noop, 271 .done = ohci_root_ctrl_done, 272 }; 273 274 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 275 .transfer = ohci_root_intr_transfer, 276 .start = ohci_root_intr_start, 277 .abort = ohci_root_intr_abort, 278 .close = ohci_root_intr_close, 279 .cleartoggle = ohci_noop, 280 .done = ohci_root_intr_done, 281 }; 282 283 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 284 .transfer = ohci_device_ctrl_transfer, 285 .start = ohci_device_ctrl_start, 286 .abort = ohci_device_ctrl_abort, 287 .close = ohci_device_ctrl_close, 288 .cleartoggle = ohci_noop, 289 .done = ohci_device_ctrl_done, 290 }; 291 292 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 293 .transfer = ohci_device_intr_transfer, 294 .start = ohci_device_intr_start, 295 .abort = ohci_device_intr_abort, 296 .close = ohci_device_intr_close, 297 .cleartoggle = ohci_device_clear_toggle, 298 .done = ohci_device_intr_done, 299 }; 300 301 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 302 .transfer = ohci_device_bulk_transfer, 303 .start = ohci_device_bulk_start, 304 .abort = ohci_device_bulk_abort, 305 .close = ohci_device_bulk_close, 306 .cleartoggle = ohci_device_clear_toggle, 307 .done = ohci_device_bulk_done, 308 }; 309 310 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 311 .transfer = ohci_device_isoc_transfer, 312 .start = ohci_device_isoc_start, 313 .abort = ohci_device_isoc_abort, 314 .close = ohci_device_isoc_close, 315 .cleartoggle = ohci_noop, 316 .done = ohci_device_isoc_done, 317 }; 318 319 int 320 ohci_activate(device_t self, enum devact act) 321 { 322 struct ohci_softc *sc = device_private(self); 323 324 switch (act) { 325 case DVACT_DEACTIVATE: 326 sc->sc_dying = 1; 327 return 0; 328 default: 329 return EOPNOTSUPP; 330 } 331 } 332 333 void 334 ohci_childdet(device_t self, device_t child) 335 { 336 struct ohci_softc *sc = device_private(self); 337 338 KASSERT(sc->sc_child == child); 339 sc->sc_child = NULL; 340 } 341 342 int 343 ohci_detach(struct ohci_softc *sc, int flags) 344 { 345 int rv = 0; 346 347 if (sc->sc_child != NULL) 348 rv = config_detach(sc->sc_child, flags); 349 350 if (rv != 0) 351 return (rv); 352 353 callout_stop(&sc->sc_tmo_rhsc); 354 355 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 356 callout_destroy(&sc->sc_tmo_rhsc); 357 358 softint_disestablish(sc->sc_rhsc_si); 359 360 cv_destroy(&sc->sc_softwake_cv); 361 362 mutex_destroy(&sc->sc_lock); 363 mutex_destroy(&sc->sc_intr_lock); 364 365 if (sc->sc_hcca != NULL) 366 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 367 pool_cache_destroy(sc->sc_xferpool); 368 369 return (rv); 370 } 371 372 ohci_soft_ed_t * 373 ohci_alloc_sed(ohci_softc_t *sc) 374 { 375 ohci_soft_ed_t *sed; 376 usbd_status err; 377 int i, offs; 378 usb_dma_t dma; 379 380 if (sc->sc_freeeds == NULL) { 381 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 382 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 383 OHCI_ED_ALIGN, &dma); 384 if (err) 385 return (0); 386 for (i = 0; i < OHCI_SED_CHUNK; i++) { 387 offs = i * OHCI_SED_SIZE; 388 sed = KERNADDR(&dma, offs); 389 sed->physaddr = DMAADDR(&dma, offs); 390 sed->dma = dma; 391 sed->offs = offs; 392 sed->next = sc->sc_freeeds; 393 sc->sc_freeeds = sed; 394 } 395 } 396 sed = sc->sc_freeeds; 397 sc->sc_freeeds = sed->next; 398 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 399 sed->next = 0; 400 return (sed); 401 } 402 403 void 404 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 405 { 406 sed->next = sc->sc_freeeds; 407 sc->sc_freeeds = sed; 408 } 409 410 ohci_soft_td_t * 411 ohci_alloc_std(ohci_softc_t *sc) 412 { 413 ohci_soft_td_t *std; 414 usbd_status err; 415 int i, offs; 416 usb_dma_t dma; 417 418 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 419 420 if (sc->sc_freetds == NULL) { 421 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 422 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 423 OHCI_TD_ALIGN, &dma); 424 if (err) 425 return (NULL); 426 for(i = 0; i < OHCI_STD_CHUNK; i++) { 427 offs = i * OHCI_STD_SIZE; 428 std = KERNADDR(&dma, offs); 429 std->physaddr = DMAADDR(&dma, offs); 430 std->dma = dma; 431 std->offs = offs; 432 std->nexttd = sc->sc_freetds; 433 sc->sc_freetds = std; 434 } 435 } 436 437 std = sc->sc_freetds; 438 sc->sc_freetds = std->nexttd; 439 memset(&std->td, 0, sizeof(ohci_td_t)); 440 std->nexttd = NULL; 441 std->xfer = NULL; 442 ohci_hash_add_td(sc, std); 443 444 return (std); 445 } 446 447 void 448 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 449 { 450 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 451 452 ohci_hash_rem_td(sc, std); 453 std->nexttd = sc->sc_freetds; 454 sc->sc_freetds = std; 455 } 456 457 usbd_status 458 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 459 int alen, int rd, usbd_xfer_handle xfer, 460 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 461 { 462 ohci_soft_td_t *next, *cur; 463 ohci_physaddr_t dataphys, dataphysend; 464 u_int32_t tdflags; 465 int len, curlen; 466 usb_dma_t *dma = &xfer->dmabuf; 467 u_int16_t flags = xfer->flags; 468 469 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 470 471 KASSERT(mutex_owned(&sc->sc_lock)); 472 473 len = alen; 474 cur = sp; 475 dataphys = DMAADDR(dma, 0); 476 dataphysend = OHCI_PAGE(dataphys + len - 1); 477 usb_syncmem(dma, 0, len, 478 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 479 tdflags = HTOO32( 480 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 481 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 482 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 483 484 for (;;) { 485 next = ohci_alloc_std(sc); 486 if (next == NULL) 487 goto nomem; 488 489 /* The OHCI hardware can handle at most one page crossing. */ 490 if (OHCI_PAGE(dataphys) == dataphysend || 491 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 492 /* we can handle it in this TD */ 493 curlen = len; 494 } else { 495 /* must use multiple TDs, fill as much as possible. */ 496 curlen = 2 * OHCI_PAGE_SIZE - 497 (dataphys & (OHCI_PAGE_SIZE-1)); 498 /* the length must be a multiple of the max size */ 499 curlen -= curlen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize); 500 #ifdef DIAGNOSTIC 501 if (curlen == 0) 502 panic("ohci_alloc_std: curlen == 0"); 503 #endif 504 } 505 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 506 "dataphysend=0x%08x len=%d curlen=%d\n", 507 dataphys, dataphysend, 508 len, curlen)); 509 len -= curlen; 510 511 cur->td.td_flags = tdflags; 512 cur->td.td_cbp = HTOO32(dataphys); 513 cur->nexttd = next; 514 cur->td.td_nexttd = HTOO32(next->physaddr); 515 cur->td.td_be = HTOO32(dataphys + curlen - 1); 516 cur->len = curlen; 517 cur->flags = OHCI_ADD_LEN; 518 cur->xfer = xfer; 519 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 520 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 521 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 522 dataphys, dataphys + curlen - 1)); 523 if (len == 0) 524 break; 525 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 526 dataphys += curlen; 527 cur = next; 528 } 529 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 530 alen % UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize) == 0) { 531 /* Force a 0 length transfer at the end. */ 532 533 cur = next; 534 next = ohci_alloc_std(sc); 535 if (next == NULL) 536 goto nomem; 537 538 cur->td.td_flags = tdflags; 539 cur->td.td_cbp = 0; /* indicate 0 length packet */ 540 cur->nexttd = next; 541 cur->td.td_nexttd = HTOO32(next->physaddr); 542 cur->td.td_be = ~0; 543 cur->len = 0; 544 cur->flags = 0; 545 cur->xfer = xfer; 546 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 548 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 549 } 550 *ep = cur; 551 552 return (USBD_NORMAL_COMPLETION); 553 554 nomem: 555 556 /* Don't free sp - let the caller do that */ 557 ohci_free_std_chain(sc, sp->nexttd, NULL); 558 559 return (USBD_NOMEM); 560 } 561 562 Static void 563 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 564 ohci_soft_td_t *stdend) 565 { 566 ohci_soft_td_t *p; 567 568 for (; std != stdend; std = p) { 569 p = std->nexttd; 570 ohci_free_std(sc, std); 571 } 572 } 573 574 ohci_soft_itd_t * 575 ohci_alloc_sitd(ohci_softc_t *sc) 576 { 577 ohci_soft_itd_t *sitd; 578 usbd_status err; 579 int i, offs; 580 usb_dma_t dma; 581 582 if (sc->sc_freeitds == NULL) { 583 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 584 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 585 OHCI_ITD_ALIGN, &dma); 586 if (err) 587 return (NULL); 588 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 589 offs = i * OHCI_SITD_SIZE; 590 sitd = KERNADDR(&dma, offs); 591 sitd->physaddr = DMAADDR(&dma, offs); 592 sitd->dma = dma; 593 sitd->offs = offs; 594 sitd->nextitd = sc->sc_freeitds; 595 sc->sc_freeitds = sitd; 596 } 597 } 598 599 sitd = sc->sc_freeitds; 600 sc->sc_freeitds = sitd->nextitd; 601 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 602 sitd->nextitd = NULL; 603 sitd->xfer = NULL; 604 ohci_hash_add_itd(sc, sitd); 605 606 #ifdef DIAGNOSTIC 607 sitd->isdone = 0; 608 #endif 609 610 return (sitd); 611 } 612 613 void 614 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 615 { 616 617 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 618 619 #ifdef DIAGNOSTIC 620 if (!sitd->isdone) { 621 panic("ohci_free_sitd: sitd=%p not done", sitd); 622 return; 623 } 624 /* Warn double free */ 625 sitd->isdone = 0; 626 #endif 627 628 ohci_hash_rem_itd(sc, sitd); 629 sitd->nextitd = sc->sc_freeitds; 630 sc->sc_freeitds = sitd; 631 } 632 633 usbd_status 634 ohci_init(ohci_softc_t *sc) 635 { 636 ohci_soft_ed_t *sed, *psed; 637 usbd_status err; 638 int i; 639 u_int32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 640 641 DPRINTF(("ohci_init: start\n")); 642 aprint_normal_dev(sc->sc_dev, ""); 643 644 sc->sc_hcca = NULL; 645 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 646 647 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 648 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 649 cv_init(&sc->sc_softwake_cv, "ohciab"); 650 651 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 652 ohci_rhsc_softint, sc); 653 654 for (i = 0; i < OHCI_HASH_SIZE; i++) 655 LIST_INIT(&sc->sc_hash_tds[i]); 656 for (i = 0; i < OHCI_HASH_SIZE; i++) 657 LIST_INIT(&sc->sc_hash_itds[i]); 658 659 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 660 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 661 662 rev = OREAD4(sc, OHCI_REVISION); 663 aprint_normal("OHCI version %d.%d%s\n", 664 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 665 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 666 667 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 668 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 669 sc->sc_bus.usbrev = USBREV_UNKNOWN; 670 return (USBD_INVAL); 671 } 672 sc->sc_bus.usbrev = USBREV_1_0; 673 674 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 675 USB_MEM_RESERVE); 676 677 /* XXX determine alignment by R/W */ 678 /* Allocate the HCCA area. */ 679 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 680 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 681 if (err) { 682 sc->sc_hcca = NULL; 683 return err; 684 } 685 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 686 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 687 688 sc->sc_eintrs = OHCI_NORMAL_INTRS; 689 690 /* Allocate dummy ED that starts the control list. */ 691 sc->sc_ctrl_head = ohci_alloc_sed(sc); 692 if (sc->sc_ctrl_head == NULL) { 693 err = USBD_NOMEM; 694 goto bad1; 695 } 696 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 697 698 /* Allocate dummy ED that starts the bulk list. */ 699 sc->sc_bulk_head = ohci_alloc_sed(sc); 700 if (sc->sc_bulk_head == NULL) { 701 err = USBD_NOMEM; 702 goto bad2; 703 } 704 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 705 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 706 sizeof(sc->sc_bulk_head->ed), 707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 708 709 /* Allocate dummy ED that starts the isochronous list. */ 710 sc->sc_isoc_head = ohci_alloc_sed(sc); 711 if (sc->sc_isoc_head == NULL) { 712 err = USBD_NOMEM; 713 goto bad3; 714 } 715 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 716 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 717 sizeof(sc->sc_isoc_head->ed), 718 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 719 720 /* Allocate all the dummy EDs that make up the interrupt tree. */ 721 for (i = 0; i < OHCI_NO_EDS; i++) { 722 sed = ohci_alloc_sed(sc); 723 if (sed == NULL) { 724 while (--i >= 0) 725 ohci_free_sed(sc, sc->sc_eds[i]); 726 err = USBD_NOMEM; 727 goto bad4; 728 } 729 /* All ED fields are set to 0. */ 730 sc->sc_eds[i] = sed; 731 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 732 if (i != 0) 733 psed = sc->sc_eds[(i-1) / 2]; 734 else 735 psed= sc->sc_isoc_head; 736 sed->next = psed; 737 sed->ed.ed_nexted = HTOO32(psed->physaddr); 738 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 740 } 741 /* 742 * Fill HCCA interrupt table. The bit reversal is to get 743 * the tree set up properly to spread the interrupts. 744 */ 745 for (i = 0; i < OHCI_NO_INTRS; i++) 746 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 747 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 748 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 750 751 #ifdef OHCI_DEBUG 752 if (ohcidebug > 15) { 753 for (i = 0; i < OHCI_NO_EDS; i++) { 754 printf("ed#%d ", i); 755 ohci_dump_ed(sc, sc->sc_eds[i]); 756 } 757 printf("iso "); 758 ohci_dump_ed(sc, sc->sc_isoc_head); 759 } 760 #endif 761 762 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 763 ctl = OREAD4(sc, OHCI_CONTROL); 764 rwc = ctl & OHCI_RWC; 765 fm = OREAD4(sc, OHCI_FM_INTERVAL); 766 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 767 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 768 769 /* Determine in what context we are running. */ 770 if (ctl & OHCI_IR) { 771 /* SMM active, request change */ 772 DPRINTF(("ohci_init: SMM active, request owner change\n")); 773 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 774 (OHCI_OC | OHCI_MIE)) 775 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 776 s = OREAD4(sc, OHCI_COMMAND_STATUS); 777 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 778 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 779 usb_delay_ms(&sc->sc_bus, 1); 780 ctl = OREAD4(sc, OHCI_CONTROL); 781 } 782 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 783 if ((ctl & OHCI_IR) == 0) { 784 aprint_error_dev(sc->sc_dev, 785 "SMM does not respond, resetting\n"); 786 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 787 goto reset; 788 } 789 #if 0 790 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 791 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 792 /* BIOS started controller. */ 793 DPRINTF(("ohci_init: BIOS active\n")); 794 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 795 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 796 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 797 } 798 #endif 799 } else { 800 DPRINTF(("ohci_init: cold started\n")); 801 reset: 802 /* Controller was cold started. */ 803 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 804 } 805 806 /* 807 * This reset should not be necessary according to the OHCI spec, but 808 * without it some controllers do not start. 809 */ 810 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 811 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 812 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 813 814 /* We now own the host controller and the bus has been reset. */ 815 816 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 817 /* Nominal time for a reset is 10 us. */ 818 for (i = 0; i < 10; i++) { 819 delay(10); 820 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 821 if (!hcr) 822 break; 823 } 824 if (hcr) { 825 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 826 err = USBD_IOERROR; 827 goto bad5; 828 } 829 #ifdef OHCI_DEBUG 830 if (ohcidebug > 15) 831 ohci_dumpregs(sc); 832 #endif 833 834 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 835 836 /* Set up HC registers. */ 837 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 838 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 839 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 840 /* disable all interrupts and then switch on all desired interrupts */ 841 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 842 /* switch on desired functional features */ 843 ctl = OREAD4(sc, OHCI_CONTROL); 844 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 845 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 846 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 847 /* And finally start it! */ 848 OWRITE4(sc, OHCI_CONTROL, ctl); 849 850 /* 851 * The controller is now OPERATIONAL. Set a some final 852 * registers that should be set earlier, but that the 853 * controller ignores when in the SUSPEND state. 854 */ 855 ival = OHCI_GET_IVAL(fm); 856 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 857 fm |= OHCI_FSMPS(ival) | ival; 858 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 859 per = OHCI_PERIODIC(ival); /* 90% periodic */ 860 OWRITE4(sc, OHCI_PERIODIC_START, per); 861 862 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 863 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 864 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 865 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 866 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 867 868 /* 869 * The AMD756 requires a delay before re-reading the register, 870 * otherwise it will occasionally report 0 ports. 871 */ 872 sc->sc_noport = 0; 873 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 874 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 875 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 876 } 877 878 #ifdef OHCI_DEBUG 879 if (ohcidebug > 5) 880 ohci_dumpregs(sc); 881 #endif 882 883 /* Set up the bus struct. */ 884 sc->sc_bus.methods = &ohci_bus_methods; 885 sc->sc_bus.pipe_size = sizeof(struct ohci_pipe); 886 887 sc->sc_control = sc->sc_intre = 0; 888 889 /* Finally, turn on interrupts. */ 890 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 891 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 892 893 return (USBD_NORMAL_COMPLETION); 894 895 bad5: 896 for (i = 0; i < OHCI_NO_EDS; i++) 897 ohci_free_sed(sc, sc->sc_eds[i]); 898 bad4: 899 ohci_free_sed(sc, sc->sc_isoc_head); 900 bad3: 901 ohci_free_sed(sc, sc->sc_bulk_head); 902 bad2: 903 ohci_free_sed(sc, sc->sc_ctrl_head); 904 bad1: 905 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 906 sc->sc_hcca = NULL; 907 return (err); 908 } 909 910 usbd_status 911 ohci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 912 { 913 struct ohci_softc *sc = bus->hci_private; 914 usbd_status status; 915 916 status = usb_allocmem(&sc->sc_bus, size, 0, dma); 917 if (status == USBD_NOMEM) 918 status = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 919 return status; 920 } 921 922 void 923 ohci_freem(struct usbd_bus *bus, usb_dma_t *dma) 924 { 925 struct ohci_softc *sc = bus->hci_private; 926 if (dma->block->flags & USB_DMA_RESERVE) { 927 usb_reserve_freem(&sc->sc_dma_reserve, dma); 928 return; 929 } 930 usb_freemem(&sc->sc_bus, dma); 931 } 932 933 usbd_xfer_handle 934 ohci_allocx(struct usbd_bus *bus) 935 { 936 struct ohci_softc *sc = bus->hci_private; 937 usbd_xfer_handle xfer; 938 939 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 940 if (xfer != NULL) { 941 memset(xfer, 0, sizeof(struct ohci_xfer)); 942 #ifdef DIAGNOSTIC 943 xfer->busy_free = XFER_BUSY; 944 #endif 945 } 946 return (xfer); 947 } 948 949 void 950 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 951 { 952 struct ohci_softc *sc = bus->hci_private; 953 954 #ifdef DIAGNOSTIC 955 if (xfer->busy_free != XFER_BUSY) { 956 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 957 xfer->busy_free); 958 } 959 xfer->busy_free = XFER_FREE; 960 #endif 961 pool_cache_put(sc->sc_xferpool, xfer); 962 } 963 964 Static void 965 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 966 { 967 struct ohci_softc *sc = bus->hci_private; 968 969 *lock = &sc->sc_lock; 970 } 971 972 /* 973 * Shut down the controller when the system is going down. 974 */ 975 bool 976 ohci_shutdown(device_t self, int flags) 977 { 978 ohci_softc_t *sc = device_private(self); 979 980 DPRINTF(("ohci_shutdown: stopping the HC\n")); 981 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 982 return true; 983 } 984 985 bool 986 ohci_resume(device_t dv, const pmf_qual_t *qual) 987 { 988 ohci_softc_t *sc = device_private(dv); 989 uint32_t ctl; 990 991 mutex_spin_enter(&sc->sc_intr_lock); 992 sc->sc_bus.use_polling++; 993 mutex_spin_exit(&sc->sc_intr_lock); 994 995 /* Some broken BIOSes do not recover these values */ 996 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 997 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 998 sc->sc_ctrl_head->physaddr); 999 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1000 sc->sc_bulk_head->physaddr); 1001 if (sc->sc_intre) 1002 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1003 (OHCI_ALL_INTRS | OHCI_MIE)); 1004 if (sc->sc_control) 1005 ctl = sc->sc_control; 1006 else 1007 ctl = OREAD4(sc, OHCI_CONTROL); 1008 ctl |= OHCI_HCFS_RESUME; 1009 OWRITE4(sc, OHCI_CONTROL, ctl); 1010 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1011 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1012 OWRITE4(sc, OHCI_CONTROL, ctl); 1013 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1014 sc->sc_control = sc->sc_intre = 0; 1015 1016 mutex_spin_enter(&sc->sc_intr_lock); 1017 sc->sc_bus.use_polling--; 1018 mutex_spin_exit(&sc->sc_intr_lock); 1019 1020 return true; 1021 } 1022 1023 bool 1024 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1025 { 1026 ohci_softc_t *sc = device_private(dv); 1027 uint32_t ctl; 1028 1029 mutex_spin_enter(&sc->sc_intr_lock); 1030 sc->sc_bus.use_polling++; 1031 mutex_spin_exit(&sc->sc_intr_lock); 1032 1033 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1034 if (sc->sc_control == 0) { 1035 /* 1036 * Preserve register values, in case that BIOS 1037 * does not recover them. 1038 */ 1039 sc->sc_control = ctl; 1040 sc->sc_intre = OREAD4(sc, 1041 OHCI_INTERRUPT_ENABLE); 1042 } 1043 ctl |= OHCI_HCFS_SUSPEND; 1044 OWRITE4(sc, OHCI_CONTROL, ctl); 1045 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1046 1047 mutex_spin_enter(&sc->sc_intr_lock); 1048 sc->sc_bus.use_polling--; 1049 mutex_spin_exit(&sc->sc_intr_lock); 1050 1051 return true; 1052 } 1053 1054 #ifdef OHCI_DEBUG 1055 void 1056 ohci_dumpregs(ohci_softc_t *sc) 1057 { 1058 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1059 OREAD4(sc, OHCI_REVISION), 1060 OREAD4(sc, OHCI_CONTROL), 1061 OREAD4(sc, OHCI_COMMAND_STATUS))); 1062 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1063 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1064 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1065 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1066 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1067 OREAD4(sc, OHCI_HCCA), 1068 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1069 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1070 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1071 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1072 OREAD4(sc, OHCI_BULK_HEAD_ED), 1073 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1074 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1075 OREAD4(sc, OHCI_DONE_HEAD), 1076 OREAD4(sc, OHCI_FM_INTERVAL), 1077 OREAD4(sc, OHCI_FM_REMAINING))); 1078 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1079 OREAD4(sc, OHCI_FM_NUMBER), 1080 OREAD4(sc, OHCI_PERIODIC_START), 1081 OREAD4(sc, OHCI_LS_THRESHOLD))); 1082 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1083 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1084 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1085 OREAD4(sc, OHCI_RH_STATUS))); 1086 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1087 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1088 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1089 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1090 O32TOH(sc->sc_hcca->hcca_frame_number), 1091 O32TOH(sc->sc_hcca->hcca_done_head))); 1092 } 1093 #endif 1094 1095 Static int ohci_intr1(ohci_softc_t *); 1096 1097 int 1098 ohci_intr(void *p) 1099 { 1100 ohci_softc_t *sc = p; 1101 int ret = 0; 1102 1103 if (sc == NULL) 1104 return (0); 1105 1106 mutex_spin_enter(&sc->sc_intr_lock); 1107 1108 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1109 goto done; 1110 1111 /* If we get an interrupt while polling, then just ignore it. */ 1112 if (sc->sc_bus.use_polling) { 1113 #ifdef DIAGNOSTIC 1114 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1115 #endif 1116 /* for level triggered intrs, should do something to ack */ 1117 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1118 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1119 1120 goto done; 1121 } 1122 1123 ret = ohci_intr1(sc); 1124 1125 done: 1126 mutex_spin_exit(&sc->sc_intr_lock); 1127 return ret; 1128 } 1129 1130 Static int 1131 ohci_intr1(ohci_softc_t *sc) 1132 { 1133 u_int32_t intrs, eintrs; 1134 1135 DPRINTFN(14,("ohci_intr1: enter\n")); 1136 1137 /* In case the interrupt occurs before initialization has completed. */ 1138 if (sc == NULL || sc->sc_hcca == NULL) { 1139 #ifdef DIAGNOSTIC 1140 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1141 #endif 1142 return (0); 1143 } 1144 1145 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1146 1147 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1148 if (!intrs) 1149 return (0); 1150 1151 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1152 eintrs = intrs & sc->sc_eintrs; 1153 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1154 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1155 (u_int)eintrs, sc->sc_eintrs)); 1156 1157 if (!eintrs) { 1158 return (0); 1159 } 1160 1161 sc->sc_bus.no_intrs++; 1162 if (eintrs & OHCI_SO) { 1163 sc->sc_overrun_cnt++; 1164 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1165 printf("%s: %u scheduling overruns\n", 1166 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1167 sc->sc_overrun_cnt = 0; 1168 } 1169 /* XXX do what */ 1170 eintrs &= ~OHCI_SO; 1171 } 1172 if (eintrs & OHCI_WDH) { 1173 /* 1174 * We block the interrupt below, and reenable it later from 1175 * ohci_softintr(). 1176 */ 1177 usb_schedsoftintr(&sc->sc_bus); 1178 } 1179 if (eintrs & OHCI_RD) { 1180 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1181 /* XXX process resume detect */ 1182 } 1183 if (eintrs & OHCI_UE) { 1184 printf("%s: unrecoverable error, controller halted\n", 1185 device_xname(sc->sc_dev)); 1186 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1187 /* XXX what else */ 1188 } 1189 if (eintrs & OHCI_RHSC) { 1190 /* 1191 * We block the interrupt below, and reenable it later from 1192 * a timeout. 1193 */ 1194 softint_schedule(sc->sc_rhsc_si); 1195 } 1196 1197 if (eintrs != 0) { 1198 /* Block unprocessed interrupts. */ 1199 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1200 sc->sc_eintrs &= ~eintrs; 1201 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1202 device_xname(sc->sc_dev), eintrs)); 1203 } 1204 1205 return (1); 1206 } 1207 1208 void 1209 ohci_rhsc_enable(void *v_sc) 1210 { 1211 ohci_softc_t *sc = v_sc; 1212 1213 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1214 mutex_spin_enter(&sc->sc_intr_lock); 1215 sc->sc_eintrs |= OHCI_RHSC; 1216 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1217 mutex_spin_exit(&sc->sc_intr_lock); 1218 } 1219 1220 #ifdef OHCI_DEBUG 1221 const char *ohci_cc_strs[] = { 1222 "NO_ERROR", 1223 "CRC", 1224 "BIT_STUFFING", 1225 "DATA_TOGGLE_MISMATCH", 1226 "STALL", 1227 "DEVICE_NOT_RESPONDING", 1228 "PID_CHECK_FAILURE", 1229 "UNEXPECTED_PID", 1230 "DATA_OVERRUN", 1231 "DATA_UNDERRUN", 1232 "BUFFER_OVERRUN", 1233 "BUFFER_UNDERRUN", 1234 "reserved", 1235 "reserved", 1236 "NOT_ACCESSED", 1237 "NOT_ACCESSED", 1238 }; 1239 #endif 1240 1241 void 1242 ohci_softintr(void *v) 1243 { 1244 struct usbd_bus *bus = v; 1245 ohci_softc_t *sc = bus->hci_private; 1246 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1247 ohci_soft_td_t *std, *sdone, *stdnext; 1248 usbd_xfer_handle xfer; 1249 struct ohci_pipe *opipe; 1250 int len, cc; 1251 int i, j, actlen, iframes, uedir; 1252 ohci_physaddr_t done; 1253 1254 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1255 1256 DPRINTFN(10,("ohci_softintr: enter\n")); 1257 1258 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1259 sizeof(sc->sc_hcca->hcca_done_head), 1260 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1261 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1262 sc->sc_hcca->hcca_done_head = 0; 1263 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1264 sizeof(sc->sc_hcca->hcca_done_head), 1265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1266 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1267 sc->sc_eintrs |= OHCI_WDH; 1268 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1269 1270 /* Reverse the done list. */ 1271 for (sdone = NULL, sidone = NULL; done != 0; ) { 1272 std = ohci_hash_find_td(sc, done); 1273 if (std != NULL) { 1274 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1275 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1276 std->dnext = sdone; 1277 done = O32TOH(std->td.td_nexttd); 1278 sdone = std; 1279 DPRINTFN(10,("add TD %p\n", std)); 1280 continue; 1281 } 1282 sitd = ohci_hash_find_itd(sc, done); 1283 if (sitd != NULL) { 1284 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1285 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1286 sitd->dnext = sidone; 1287 done = O32TOH(sitd->itd.itd_nextitd); 1288 sidone = sitd; 1289 DPRINTFN(5,("add ITD %p\n", sitd)); 1290 continue; 1291 } 1292 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1293 (u_long)done); 1294 break; 1295 } 1296 1297 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1298 1299 #ifdef OHCI_DEBUG 1300 if (ohcidebug > 10) { 1301 DPRINTF(("ohci_process_done: TD done:\n")); 1302 for (std = sdone; std; std = std->dnext) 1303 ohci_dump_td(sc, std); 1304 } 1305 #endif 1306 1307 for (std = sdone; std; std = stdnext) { 1308 xfer = std->xfer; 1309 stdnext = std->dnext; 1310 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1311 std, xfer, xfer ? xfer->hcpriv : 0)); 1312 if (xfer == NULL) { 1313 /* 1314 * xfer == NULL: There seems to be no xfer associated 1315 * with this TD. It is tailp that happened to end up on 1316 * the done queue. 1317 * Shouldn't happen, but some chips are broken(?). 1318 */ 1319 continue; 1320 } 1321 if (xfer->status == USBD_CANCELLED || 1322 xfer->status == USBD_TIMEOUT) { 1323 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1324 xfer)); 1325 /* Handled by abort routine. */ 1326 continue; 1327 } 1328 callout_stop(&xfer->timeout_handle); 1329 1330 len = std->len; 1331 if (std->td.td_cbp != 0) 1332 len -= O32TOH(std->td.td_be) - 1333 O32TOH(std->td.td_cbp) + 1; 1334 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1335 std->flags)); 1336 if (std->flags & OHCI_ADD_LEN) 1337 xfer->actlen += len; 1338 1339 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1340 if (cc == OHCI_CC_NO_ERROR) { 1341 if (std->flags & OHCI_CALL_DONE) { 1342 xfer->status = USBD_NORMAL_COMPLETION; 1343 usb_transfer_complete(xfer); 1344 } 1345 ohci_free_std(sc, std); 1346 } else { 1347 /* 1348 * Endpoint is halted. First unlink all the TDs 1349 * belonging to the failed transfer, and then restart 1350 * the endpoint. 1351 */ 1352 ohci_soft_td_t *p, *n; 1353 opipe = (struct ohci_pipe *)xfer->pipe; 1354 1355 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1356 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1357 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1358 1359 /* remove TDs */ 1360 for (p = std; p->xfer == xfer; p = n) { 1361 n = p->nexttd; 1362 ohci_free_std(sc, p); 1363 } 1364 1365 /* clear halt */ 1366 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1367 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1368 1369 if (cc == OHCI_CC_STALL) 1370 xfer->status = USBD_STALLED; 1371 else 1372 xfer->status = USBD_IOERROR; 1373 usb_transfer_complete(xfer); 1374 } 1375 } 1376 1377 #ifdef OHCI_DEBUG 1378 if (ohcidebug > 10) { 1379 DPRINTF(("ohci_softintr: ITD done:\n")); 1380 for (sitd = sidone; sitd; sitd = sitd->dnext) 1381 ohci_dump_itd(sc, sitd); 1382 } 1383 #endif 1384 1385 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1386 xfer = sitd->xfer; 1387 sitdnext = sitd->dnext; 1388 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1389 sitd, xfer, xfer ? xfer->hcpriv : 0)); 1390 if (xfer == NULL) 1391 continue; 1392 if (xfer->status == USBD_CANCELLED || 1393 xfer->status == USBD_TIMEOUT) { 1394 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1395 xfer)); 1396 /* Handled by abort routine. */ 1397 continue; 1398 } 1399 #ifdef DIAGNOSTIC 1400 if (sitd->isdone) 1401 printf("ohci_softintr: sitd=%p is done\n", sitd); 1402 sitd->isdone = 1; 1403 #endif 1404 if (sitd->flags & OHCI_CALL_DONE) { 1405 ohci_soft_itd_t *next; 1406 1407 opipe = (struct ohci_pipe *)xfer->pipe; 1408 opipe->u.iso.inuse -= xfer->nframes; 1409 uedir = UE_GET_DIR(xfer->pipe->endpoint->edesc-> 1410 bEndpointAddress); 1411 xfer->status = USBD_NORMAL_COMPLETION; 1412 actlen = 0; 1413 for (i = 0, sitd = xfer->hcpriv;; 1414 sitd = next) { 1415 next = sitd->nextitd; 1416 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1417 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1418 xfer->status = USBD_IOERROR; 1419 /* For input, update frlengths with actual */ 1420 /* XXX anything necessary for output? */ 1421 if (uedir == UE_DIR_IN && 1422 xfer->status == USBD_NORMAL_COMPLETION) { 1423 iframes = OHCI_ITD_GET_FC(O32TOH( 1424 sitd->itd.itd_flags)); 1425 for (j = 0; j < iframes; i++, j++) { 1426 len = O16TOH(sitd-> 1427 itd.itd_offset[j]); 1428 if ((OHCI_ITD_PSW_GET_CC(len) & 1429 OHCI_CC_NOT_ACCESSED_MASK) 1430 == OHCI_CC_NOT_ACCESSED) 1431 len = 0; 1432 else 1433 len = OHCI_ITD_PSW_LENGTH(len); 1434 xfer->frlengths[i] = len; 1435 actlen += len; 1436 } 1437 } 1438 if (sitd->flags & OHCI_CALL_DONE) 1439 break; 1440 ohci_free_sitd(sc, sitd); 1441 } 1442 ohci_free_sitd(sc, sitd); 1443 if (uedir == UE_DIR_IN && 1444 xfer->status == USBD_NORMAL_COMPLETION) 1445 xfer->actlen = actlen; 1446 xfer->hcpriv = NULL; 1447 1448 usb_transfer_complete(xfer); 1449 } 1450 } 1451 1452 if (sc->sc_softwake) { 1453 sc->sc_softwake = 0; 1454 cv_broadcast(&sc->sc_softwake_cv); 1455 } 1456 1457 DPRINTFN(10,("ohci_softintr: done:\n")); 1458 } 1459 1460 void 1461 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1462 { 1463 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1464 #ifdef DIAGNOSTIC 1465 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1466 #endif 1467 int len = UGETW(xfer->request.wLength); 1468 int isread = (xfer->request.bmRequestType & UT_READ); 1469 1470 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1471 1472 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1473 1474 #ifdef DIAGNOSTIC 1475 if (!(xfer->rqflags & URQ_REQUEST)) { 1476 panic("ohci_device_ctrl_done: not a request"); 1477 } 1478 #endif 1479 if (len) 1480 usb_syncmem(&xfer->dmabuf, 0, len, 1481 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1482 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1483 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1484 } 1485 1486 void 1487 ohci_device_intr_done(usbd_xfer_handle xfer) 1488 { 1489 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1490 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1491 ohci_soft_ed_t *sed = opipe->sed; 1492 ohci_soft_td_t *data, *tail; 1493 int isread = 1494 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1495 1496 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1497 xfer, xfer->actlen)); 1498 1499 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1500 1501 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1502 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1503 if (xfer->pipe->repeat) { 1504 data = opipe->tail.td; 1505 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1506 if (tail == NULL) { 1507 xfer->status = USBD_NOMEM; 1508 return; 1509 } 1510 tail->xfer = NULL; 1511 1512 data->td.td_flags = HTOO32( 1513 OHCI_TD_IN | OHCI_TD_NOCC | 1514 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1515 if (xfer->flags & USBD_SHORT_XFER_OK) 1516 data->td.td_flags |= HTOO32(OHCI_TD_R); 1517 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 1518 data->nexttd = tail; 1519 data->td.td_nexttd = HTOO32(tail->physaddr); 1520 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1521 xfer->length - 1); 1522 data->len = xfer->length; 1523 data->xfer = xfer; 1524 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1525 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1526 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1527 xfer->hcpriv = data; 1528 xfer->actlen = 0; 1529 1530 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1531 usb_syncmem(&sed->dma, 1532 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1533 sizeof(sed->ed.ed_tailp), 1534 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1535 opipe->tail.td = tail; 1536 } 1537 } 1538 1539 void 1540 ohci_device_bulk_done(usbd_xfer_handle xfer) 1541 { 1542 #ifdef DIAGNOSTIC 1543 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1544 #endif 1545 int isread = 1546 (UE_GET_DIR(xfer->pipe->endpoint->edesc->bEndpointAddress) == UE_DIR_IN); 1547 1548 KASSERT(mutex_owned(&sc->sc_lock)); 1549 1550 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1551 xfer, xfer->actlen)); 1552 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 1553 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1554 } 1555 1556 Static void 1557 ohci_rhsc_softint(void *arg) 1558 { 1559 ohci_softc_t *sc = arg; 1560 1561 mutex_enter(&sc->sc_lock); 1562 1563 ohci_rhsc(sc, sc->sc_intrxfer); 1564 1565 /* Do not allow RHSC interrupts > 1 per second */ 1566 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1567 1568 mutex_exit(&sc->sc_lock); 1569 } 1570 1571 void 1572 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1573 { 1574 u_char *p; 1575 int i, m; 1576 int hstatus __unused; 1577 1578 KASSERT(mutex_owned(&sc->sc_lock)); 1579 1580 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1581 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1582 sc, xfer, hstatus)); 1583 1584 if (xfer == NULL) { 1585 /* Just ignore the change. */ 1586 return; 1587 } 1588 1589 p = KERNADDR(&xfer->dmabuf, 0); 1590 m = min(sc->sc_noport, xfer->length * 8 - 1); 1591 memset(p, 0, xfer->length); 1592 for (i = 1; i <= m; i++) { 1593 /* Pick out CHANGE bits from the status reg. */ 1594 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1595 p[i/8] |= 1 << (i%8); 1596 } 1597 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1598 xfer->actlen = xfer->length; 1599 xfer->status = USBD_NORMAL_COMPLETION; 1600 1601 usb_transfer_complete(xfer); 1602 } 1603 1604 void 1605 ohci_root_intr_done(usbd_xfer_handle xfer) 1606 { 1607 } 1608 1609 void 1610 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1611 { 1612 } 1613 1614 /* 1615 * Wait here until controller claims to have an interrupt. 1616 * Then call ohci_intr and return. Use timeout to avoid waiting 1617 * too long. 1618 */ 1619 void 1620 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1621 { 1622 int timo; 1623 u_int32_t intrs; 1624 1625 mutex_enter(&sc->sc_lock); 1626 1627 xfer->status = USBD_IN_PROGRESS; 1628 for (timo = xfer->timeout; timo >= 0; timo--) { 1629 usb_delay_ms(&sc->sc_bus, 1); 1630 if (sc->sc_dying) 1631 break; 1632 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1633 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1634 #ifdef OHCI_DEBUG 1635 if (ohcidebug > 15) 1636 ohci_dumpregs(sc); 1637 #endif 1638 if (intrs) { 1639 mutex_spin_enter(&sc->sc_intr_lock); 1640 ohci_intr1(sc); 1641 mutex_spin_exit(&sc->sc_intr_lock); 1642 if (xfer->status != USBD_IN_PROGRESS) 1643 goto done; 1644 } 1645 } 1646 1647 /* Timeout */ 1648 DPRINTF(("ohci_waitintr: timeout\n")); 1649 xfer->status = USBD_TIMEOUT; 1650 usb_transfer_complete(xfer); 1651 1652 /* XXX should free TD */ 1653 1654 done: 1655 mutex_exit(&sc->sc_lock); 1656 } 1657 1658 void 1659 ohci_poll(struct usbd_bus *bus) 1660 { 1661 ohci_softc_t *sc = bus->hci_private; 1662 #ifdef OHCI_DEBUG 1663 static int last; 1664 int new; 1665 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1666 if (new != last) { 1667 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1668 last = new; 1669 } 1670 #endif 1671 sc->sc_eintrs |= OHCI_WDH; 1672 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1673 mutex_spin_enter(&sc->sc_intr_lock); 1674 ohci_intr1(sc); 1675 mutex_spin_exit(&sc->sc_intr_lock); 1676 } 1677 } 1678 1679 usbd_status 1680 ohci_device_request(usbd_xfer_handle xfer) 1681 { 1682 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 1683 usb_device_request_t *req = &xfer->request; 1684 usbd_device_handle dev = opipe->pipe.device; 1685 ohci_softc_t *sc = dev->bus->hci_private; 1686 int addr = dev->address; 1687 ohci_soft_td_t *setup, *stat, *next, *tail; 1688 ohci_soft_ed_t *sed; 1689 int isread; 1690 int len; 1691 usbd_status err; 1692 1693 KASSERT(mutex_owned(&sc->sc_lock)); 1694 1695 isread = req->bmRequestType & UT_READ; 1696 len = UGETW(req->wLength); 1697 1698 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1699 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1700 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1701 UGETW(req->wIndex), len, addr, 1702 opipe->pipe.endpoint->edesc->bEndpointAddress)); 1703 1704 setup = opipe->tail.td; 1705 stat = ohci_alloc_std(sc); 1706 if (stat == NULL) { 1707 err = USBD_NOMEM; 1708 goto bad1; 1709 } 1710 tail = ohci_alloc_std(sc); 1711 if (tail == NULL) { 1712 err = USBD_NOMEM; 1713 goto bad2; 1714 } 1715 tail->xfer = NULL; 1716 1717 sed = opipe->sed; 1718 opipe->u.ctl.length = len; 1719 1720 /* Update device address and length since they may have changed 1721 during the setup of the control pipe in usbd_new_device(). */ 1722 /* XXX This only needs to be done once, but it's too early in open. */ 1723 /* XXXX Should not touch ED here! */ 1724 1725 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1726 sizeof(sed->ed.ed_flags), 1727 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1728 sed->ed.ed_flags = HTOO32( 1729 (O32TOH(sed->ed.ed_flags) & ~(OHCI_ED_ADDRMASK | OHCI_ED_MAXPMASK)) | 1730 OHCI_ED_SET_FA(addr) | 1731 OHCI_ED_SET_MAXP(UGETW(opipe->pipe.endpoint->edesc->wMaxPacketSize))); 1732 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 1733 sizeof(sed->ed.ed_flags), 1734 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1735 1736 next = stat; 1737 1738 /* Set up data transaction */ 1739 if (len != 0) { 1740 ohci_soft_td_t *std = stat; 1741 1742 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1743 std, &stat); 1744 if (err) { 1745 /* stat is unchanged if error */ 1746 goto bad3; 1747 } 1748 stat = stat->nexttd; /* point at free TD */ 1749 1750 /* Start toggle at 1 and then use the carried toggle. */ 1751 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1752 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1753 usb_syncmem(&std->dma, 1754 std->offs + offsetof(ohci_td_t, td_flags), 1755 sizeof(std->td.td_flags), 1756 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1757 } 1758 1759 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1760 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1761 1762 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1763 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1764 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1765 setup->nexttd = next; 1766 setup->td.td_nexttd = HTOO32(next->physaddr); 1767 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1768 setup->len = 0; 1769 setup->xfer = xfer; 1770 setup->flags = 0; 1771 xfer->hcpriv = setup; 1772 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1773 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1774 1775 stat->td.td_flags = HTOO32( 1776 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1777 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1778 stat->td.td_cbp = 0; 1779 stat->nexttd = tail; 1780 stat->td.td_nexttd = HTOO32(tail->physaddr); 1781 stat->td.td_be = 0; 1782 stat->flags = OHCI_CALL_DONE; 1783 stat->len = 0; 1784 stat->xfer = xfer; 1785 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1787 1788 #ifdef OHCI_DEBUG 1789 if (ohcidebug > 5) { 1790 DPRINTF(("ohci_device_request:\n")); 1791 ohci_dump_ed(sc, sed); 1792 ohci_dump_tds(sc, setup); 1793 } 1794 #endif 1795 1796 /* Insert ED in schedule */ 1797 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1798 usb_syncmem(&sed->dma, 1799 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1800 sizeof(sed->ed.ed_tailp), 1801 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1802 opipe->tail.td = tail; 1803 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1804 if (xfer->timeout && !sc->sc_bus.use_polling) { 1805 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 1806 ohci_timeout, xfer); 1807 } 1808 1809 #ifdef OHCI_DEBUG 1810 if (ohcidebug > 20) { 1811 delay(10000); 1812 DPRINTF(("ohci_device_request: status=%x\n", 1813 OREAD4(sc, OHCI_COMMAND_STATUS))); 1814 ohci_dumpregs(sc); 1815 printf("ctrl head:\n"); 1816 ohci_dump_ed(sc, sc->sc_ctrl_head); 1817 printf("sed:\n"); 1818 ohci_dump_ed(sc, sed); 1819 ohci_dump_tds(sc, setup); 1820 } 1821 #endif 1822 1823 return (USBD_NORMAL_COMPLETION); 1824 1825 bad3: 1826 ohci_free_std(sc, tail); 1827 bad2: 1828 ohci_free_std(sc, stat); 1829 bad1: 1830 return (err); 1831 } 1832 1833 /* 1834 * Add an ED to the schedule. Called with USB lock held. 1835 */ 1836 Static void 1837 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1838 { 1839 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1840 1841 KASSERT(mutex_owned(&sc->sc_lock)); 1842 1843 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1844 sizeof(head->ed.ed_nexted), 1845 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1846 sed->next = head->next; 1847 sed->ed.ed_nexted = head->ed.ed_nexted; 1848 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1849 sizeof(sed->ed.ed_nexted), 1850 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1851 head->next = sed; 1852 head->ed.ed_nexted = HTOO32(sed->physaddr); 1853 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1854 sizeof(head->ed.ed_nexted), 1855 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1856 } 1857 1858 /* 1859 * Remove an ED from the schedule. Called with USB lock held. 1860 */ 1861 Static void 1862 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1863 { 1864 ohci_soft_ed_t *p; 1865 1866 KASSERT(mutex_owned(&sc->sc_lock)); 1867 1868 /* XXX */ 1869 for (p = head; p != NULL && p->next != sed; p = p->next) 1870 ; 1871 if (p == NULL) 1872 panic("ohci_rem_ed: ED not found"); 1873 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1874 sizeof(sed->ed.ed_nexted), 1875 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1876 p->next = sed->next; 1877 p->ed.ed_nexted = sed->ed.ed_nexted; 1878 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1879 sizeof(p->ed.ed_nexted), 1880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1881 } 1882 1883 /* 1884 * When a transfer is completed the TD is added to the done queue by 1885 * the host controller. This queue is the processed by software. 1886 * Unfortunately the queue contains the physical address of the TD 1887 * and we have no simple way to translate this back to a kernel address. 1888 * To make the translation possible (and fast) we use a hash table of 1889 * TDs currently in the schedule. The physical address is used as the 1890 * hash value. 1891 */ 1892 1893 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1894 /* Called with USB lock held. */ 1895 void 1896 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1897 { 1898 int h = HASH(std->physaddr); 1899 1900 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1901 1902 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1903 } 1904 1905 /* Called with USB lock held. */ 1906 void 1907 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1908 { 1909 1910 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 1911 1912 LIST_REMOVE(std, hnext); 1913 } 1914 1915 ohci_soft_td_t * 1916 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1917 { 1918 int h = HASH(a); 1919 ohci_soft_td_t *std; 1920 1921 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1922 std != NULL; 1923 std = LIST_NEXT(std, hnext)) 1924 if (std->physaddr == a) 1925 return (std); 1926 return (NULL); 1927 } 1928 1929 /* Called with USB lock held. */ 1930 void 1931 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1932 { 1933 int h = HASH(sitd->physaddr); 1934 1935 KASSERT(mutex_owned(&sc->sc_lock)); 1936 1937 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1938 sitd, (u_long)sitd->physaddr)); 1939 1940 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1941 } 1942 1943 /* Called with USB lock held. */ 1944 void 1945 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1946 { 1947 1948 KASSERT(mutex_owned(&sc->sc_lock)); 1949 1950 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1951 sitd, (u_long)sitd->physaddr)); 1952 1953 LIST_REMOVE(sitd, hnext); 1954 } 1955 1956 ohci_soft_itd_t * 1957 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1958 { 1959 int h = HASH(a); 1960 ohci_soft_itd_t *sitd; 1961 1962 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1963 sitd != NULL; 1964 sitd = LIST_NEXT(sitd, hnext)) 1965 if (sitd->physaddr == a) 1966 return (sitd); 1967 return (NULL); 1968 } 1969 1970 void 1971 ohci_timeout(void *addr) 1972 { 1973 struct ohci_xfer *oxfer = addr; 1974 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.pipe; 1975 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 1976 1977 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1978 1979 if (sc->sc_dying) { 1980 mutex_enter(&sc->sc_lock); 1981 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1982 mutex_exit(&sc->sc_lock); 1983 return; 1984 } 1985 1986 /* Execute the abort in a process context. */ 1987 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1988 USB_TASKQ_MPSAFE); 1989 usb_add_task(oxfer->xfer.pipe->device, &oxfer->abort_task, 1990 USB_TASKQ_HC); 1991 } 1992 1993 void 1994 ohci_timeout_task(void *addr) 1995 { 1996 usbd_xfer_handle xfer = addr; 1997 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1998 1999 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 2000 2001 mutex_enter(&sc->sc_lock); 2002 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2003 mutex_exit(&sc->sc_lock); 2004 } 2005 2006 #ifdef OHCI_DEBUG 2007 void 2008 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2009 { 2010 for (; std; std = std->nexttd) 2011 ohci_dump_td(sc, std); 2012 } 2013 2014 void 2015 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2016 { 2017 char sbuf[128]; 2018 2019 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2020 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2021 snprintb(sbuf, sizeof(sbuf), 2022 "\177\20" 2023 "b\22R\0" 2024 "f\23\02DP\0" 2025 "=\x0" "setup\0" 2026 "=\x1" "out\0" 2027 "=\x2" "in\0" 2028 "=\x3" "reserved\0" 2029 "f\25\03DI\0" 2030 "=\x07" "none\0" 2031 "f\30\02T\0" 2032 "=\x0" "carry\0" 2033 "=\x1" "carry\0" 2034 "=\x2" "0\0" 2035 "=\x3" "1\0" 2036 "f\32\02EC\0" 2037 "f\34\04CC\0", 2038 (u_int32_t)O32TOH(std->td.td_flags)); 2039 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2040 std, (u_long)std->physaddr, sbuf, 2041 (u_long)O32TOH(std->td.td_cbp), 2042 (u_long)O32TOH(std->td.td_nexttd), 2043 (u_long)O32TOH(std->td.td_be)); 2044 } 2045 2046 void 2047 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2048 { 2049 int i; 2050 2051 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2052 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2053 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2054 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2055 sitd, (u_long)sitd->physaddr, 2056 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2057 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2058 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2059 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2060 (u_long)O32TOH(sitd->itd.itd_bp0), 2061 (u_long)O32TOH(sitd->itd.itd_nextitd), 2062 (u_long)O32TOH(sitd->itd.itd_be)); 2063 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2064 printf("offs[%d]=0x%04x ", i, 2065 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2066 printf("\n"); 2067 } 2068 2069 void 2070 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2071 { 2072 for (; sitd; sitd = sitd->nextitd) 2073 ohci_dump_itd(sc, sitd); 2074 } 2075 2076 void 2077 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2078 { 2079 char sbuf[128], sbuf2[128]; 2080 2081 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2082 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2083 snprintb(sbuf, sizeof(sbuf), 2084 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2085 (u_int32_t)O32TOH(sed->ed.ed_flags)); 2086 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2087 (u_int32_t)O32TOH(sed->ed.ed_headp)); 2088 2089 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2090 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2091 sed, (u_long)sed->physaddr, 2092 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2093 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2094 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2095 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2096 (u_long)O32TOH(sed->ed.ed_headp), 2097 (u_long)O32TOH(sed->ed.ed_nexted)); 2098 } 2099 #endif 2100 2101 usbd_status 2102 ohci_open(usbd_pipe_handle pipe) 2103 { 2104 usbd_device_handle dev = pipe->device; 2105 ohci_softc_t *sc = dev->bus->hci_private; 2106 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 2107 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2108 u_int8_t addr = dev->address; 2109 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2110 ohci_soft_ed_t *sed; 2111 ohci_soft_td_t *std; 2112 ohci_soft_itd_t *sitd; 2113 ohci_physaddr_t tdphys; 2114 u_int32_t fmt; 2115 usbd_status err = USBD_NOMEM; 2116 int ival; 2117 2118 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2119 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2120 2121 if (sc->sc_dying) { 2122 return USBD_IOERROR; 2123 } 2124 2125 std = NULL; 2126 sed = NULL; 2127 2128 if (addr == sc->sc_addr) { 2129 switch (ed->bEndpointAddress) { 2130 case USB_CONTROL_ENDPOINT: 2131 pipe->methods = &ohci_root_ctrl_methods; 2132 break; 2133 case UE_DIR_IN | OHCI_INTR_ENDPT: 2134 pipe->methods = &ohci_root_intr_methods; 2135 break; 2136 default: 2137 err = USBD_INVAL; 2138 goto bad; 2139 } 2140 } else { 2141 sed = ohci_alloc_sed(sc); 2142 if (sed == NULL) 2143 goto bad; 2144 opipe->sed = sed; 2145 if (xfertype == UE_ISOCHRONOUS) { 2146 mutex_enter(&sc->sc_lock); 2147 sitd = ohci_alloc_sitd(sc); 2148 mutex_exit(&sc->sc_lock); 2149 if (sitd == NULL) 2150 goto bad; 2151 2152 opipe->tail.itd = sitd; 2153 tdphys = sitd->physaddr; 2154 fmt = OHCI_ED_FORMAT_ISO; 2155 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2156 fmt |= OHCI_ED_DIR_IN; 2157 else 2158 fmt |= OHCI_ED_DIR_OUT; 2159 } else { 2160 mutex_enter(&sc->sc_lock); 2161 std = ohci_alloc_std(sc); 2162 mutex_exit(&sc->sc_lock); 2163 if (std == NULL) 2164 goto bad; 2165 2166 opipe->tail.td = std; 2167 tdphys = std->physaddr; 2168 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2169 } 2170 sed->ed.ed_flags = HTOO32( 2171 OHCI_ED_SET_FA(addr) | 2172 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2173 (dev->speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2174 fmt | 2175 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2176 sed->ed.ed_headp = HTOO32(tdphys | 2177 (pipe->endpoint->datatoggle ? OHCI_TOGGLECARRY : 0)); 2178 sed->ed.ed_tailp = HTOO32(tdphys); 2179 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2181 2182 switch (xfertype) { 2183 case UE_CONTROL: 2184 pipe->methods = &ohci_device_ctrl_methods; 2185 err = usb_allocmem(&sc->sc_bus, 2186 sizeof(usb_device_request_t), 2187 0, &opipe->u.ctl.reqdma); 2188 if (err) 2189 goto bad; 2190 mutex_enter(&sc->sc_lock); 2191 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2192 mutex_exit(&sc->sc_lock); 2193 break; 2194 case UE_INTERRUPT: 2195 pipe->methods = &ohci_device_intr_methods; 2196 ival = pipe->interval; 2197 if (ival == USBD_DEFAULT_INTERVAL) 2198 ival = ed->bInterval; 2199 err = ohci_device_setintr(sc, opipe, ival); 2200 if (err) 2201 goto bad; 2202 break; 2203 case UE_ISOCHRONOUS: 2204 pipe->methods = &ohci_device_isoc_methods; 2205 return (ohci_setup_isoc(pipe)); 2206 case UE_BULK: 2207 pipe->methods = &ohci_device_bulk_methods; 2208 mutex_enter(&sc->sc_lock); 2209 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2210 mutex_exit(&sc->sc_lock); 2211 break; 2212 } 2213 } 2214 2215 return USBD_NORMAL_COMPLETION; 2216 2217 bad: 2218 if (std != NULL) { 2219 mutex_enter(&sc->sc_lock); 2220 ohci_free_std(sc, std); 2221 mutex_exit(&sc->sc_lock); 2222 } 2223 if (sed != NULL) 2224 ohci_free_sed(sc, sed); 2225 return err; 2226 2227 } 2228 2229 /* 2230 * Close a reqular pipe. 2231 * Assumes that there are no pending transactions. 2232 */ 2233 void 2234 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2235 { 2236 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2237 ohci_softc_t *sc = pipe->device->bus->hci_private; 2238 ohci_soft_ed_t *sed = opipe->sed; 2239 2240 KASSERT(mutex_owned(&sc->sc_lock)); 2241 2242 #ifdef DIAGNOSTIC 2243 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2244 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2245 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2246 ohci_soft_td_t *std; 2247 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2248 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2249 "tl=0x%x pipe=%p, std=%p\n", sed, 2250 (int)O32TOH(sed->ed.ed_headp), 2251 (int)O32TOH(sed->ed.ed_tailp), 2252 pipe, std); 2253 #ifdef OHCI_DEBUG 2254 usbd_dump_pipe(&opipe->pipe); 2255 ohci_dump_ed(sc, sed); 2256 if (std) 2257 ohci_dump_td(sc, std); 2258 #endif 2259 usb_delay_ms(&sc->sc_bus, 2); 2260 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2261 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2262 printf("ohci_close_pipe: pipe still not empty\n"); 2263 } 2264 #endif 2265 ohci_rem_ed(sc, sed, head); 2266 /* Make sure the host controller is not touching this ED */ 2267 usb_delay_ms(&sc->sc_bus, 1); 2268 pipe->endpoint->datatoggle = 2269 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2270 ohci_free_sed(sc, opipe->sed); 2271 } 2272 2273 /* 2274 * Abort a device request. 2275 * If this routine is called at splusb() it guarantees that the request 2276 * will be removed from the hardware scheduling and that the callback 2277 * for it will be called with USBD_CANCELLED status. 2278 * It's impossible to guarantee that the requested transfer will not 2279 * have happened since the hardware runs concurrently. 2280 * If the transaction has already happened we rely on the ordinary 2281 * interrupt processing to process it. 2282 * XXX This is most probably wrong. 2283 * XXXMRG this doesn't make sense anymore. 2284 */ 2285 void 2286 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2287 { 2288 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 2289 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 2290 ohci_soft_ed_t *sed = opipe->sed; 2291 ohci_soft_td_t *p, *n; 2292 ohci_physaddr_t headp; 2293 int hit; 2294 int wake; 2295 2296 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2297 2298 KASSERT(mutex_owned(&sc->sc_lock)); 2299 2300 if (sc->sc_dying) { 2301 /* If we're dying, just do the software part. */ 2302 xfer->status = status; /* make software ignore it */ 2303 callout_halt(&xfer->timeout_handle, &sc->sc_lock); 2304 usb_transfer_complete(xfer); 2305 return; 2306 } 2307 2308 if (cpu_intr_p() || cpu_softintr_p()) 2309 panic("ohci_abort_xfer: not in process context"); 2310 2311 /* 2312 * If an abort is already in progress then just wait for it to 2313 * complete and return. 2314 */ 2315 if (xfer->hcflags & UXFER_ABORTING) { 2316 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2317 #ifdef DIAGNOSTIC 2318 if (status == USBD_TIMEOUT) 2319 printf("%s: TIMEOUT while aborting\n", __func__); 2320 #endif 2321 /* Override the status which might be USBD_TIMEOUT. */ 2322 xfer->status = status; 2323 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2324 xfer->hcflags |= UXFER_ABORTWAIT; 2325 while (xfer->hcflags & UXFER_ABORTING) 2326 cv_wait(&xfer->hccv, &sc->sc_lock); 2327 goto done; 2328 } 2329 xfer->hcflags |= UXFER_ABORTING; 2330 2331 /* 2332 * Step 1: Make interrupt routine and hardware ignore xfer. 2333 */ 2334 xfer->status = status; /* make software ignore it */ 2335 callout_stop(&xfer->timeout_handle); 2336 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2337 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2338 sizeof(sed->ed.ed_flags), 2339 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2340 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2341 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2342 sizeof(sed->ed.ed_flags), 2343 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2344 2345 /* 2346 * Step 2: Wait until we know hardware has finished any possible 2347 * use of the xfer. Also make sure the soft interrupt routine 2348 * has run. 2349 */ 2350 /* Hardware finishes in 1ms */ 2351 usb_delay_ms_locked(opipe->pipe.device->bus, 20, &sc->sc_lock); 2352 sc->sc_softwake = 1; 2353 usb_schedsoftintr(&sc->sc_bus); 2354 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2355 2356 /* 2357 * Step 3: Remove any vestiges of the xfer from the hardware. 2358 * The complication here is that the hardware may have executed 2359 * beyond the xfer we're trying to abort. So as we're scanning 2360 * the TDs of this xfer we check if the hardware points to 2361 * any of them. 2362 */ 2363 p = xfer->hcpriv; 2364 #ifdef DIAGNOSTIC 2365 if (p == NULL) { 2366 xfer->hcflags &= ~UXFER_ABORTING; /* XXX */ 2367 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2368 goto done; 2369 } 2370 #endif 2371 #ifdef OHCI_DEBUG 2372 if (ohcidebug > 1) { 2373 DPRINTF(("ohci_abort_xfer: sed=\n")); 2374 ohci_dump_ed(sc, sed); 2375 ohci_dump_tds(sc, p); 2376 } 2377 #endif 2378 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2379 hit = 0; 2380 for (; p->xfer == xfer; p = n) { 2381 hit |= headp == p->physaddr; 2382 n = p->nexttd; 2383 ohci_free_std(sc, p); 2384 } 2385 /* Zap headp register if hardware pointed inside the xfer. */ 2386 if (hit) { 2387 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2388 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2389 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2390 usb_syncmem(&sed->dma, 2391 sed->offs + offsetof(ohci_ed_t, ed_headp), 2392 sizeof(sed->ed.ed_headp), 2393 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2394 } else { 2395 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2396 } 2397 2398 /* 2399 * Step 4: Turn on hardware again. 2400 */ 2401 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2402 sizeof(sed->ed.ed_flags), 2403 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2404 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2405 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2406 sizeof(sed->ed.ed_flags), 2407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2408 2409 /* 2410 * Step 5: Execute callback. 2411 */ 2412 wake = xfer->hcflags & UXFER_ABORTWAIT; 2413 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2414 usb_transfer_complete(xfer); 2415 if (wake) 2416 cv_broadcast(&xfer->hccv); 2417 2418 done: 2419 KASSERT(mutex_owned(&sc->sc_lock)); 2420 } 2421 2422 /* 2423 * Data structures and routines to emulate the root hub. 2424 */ 2425 Static usb_device_descriptor_t ohci_devd = { 2426 USB_DEVICE_DESCRIPTOR_SIZE, 2427 UDESC_DEVICE, /* type */ 2428 {0x00, 0x01}, /* USB version */ 2429 UDCLASS_HUB, /* class */ 2430 UDSUBCLASS_HUB, /* subclass */ 2431 UDPROTO_FSHUB, /* protocol */ 2432 64, /* max packet */ 2433 {0},{0},{0x00,0x01}, /* device id */ 2434 1,2,0, /* string indicies */ 2435 1 /* # of configurations */ 2436 }; 2437 2438 Static const usb_config_descriptor_t ohci_confd = { 2439 USB_CONFIG_DESCRIPTOR_SIZE, 2440 UDESC_CONFIG, 2441 {USB_CONFIG_DESCRIPTOR_SIZE + 2442 USB_INTERFACE_DESCRIPTOR_SIZE + 2443 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2444 1, 2445 1, 2446 0, 2447 UC_ATTR_MBO | UC_SELF_POWERED, 2448 0 /* max power */ 2449 }; 2450 2451 Static const usb_interface_descriptor_t ohci_ifcd = { 2452 USB_INTERFACE_DESCRIPTOR_SIZE, 2453 UDESC_INTERFACE, 2454 0, 2455 0, 2456 1, 2457 UICLASS_HUB, 2458 UISUBCLASS_HUB, 2459 UIPROTO_FSHUB, 2460 0 2461 }; 2462 2463 Static const usb_endpoint_descriptor_t ohci_endpd = { 2464 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2465 .bDescriptorType = UDESC_ENDPOINT, 2466 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2467 .bmAttributes = UE_INTERRUPT, 2468 .wMaxPacketSize = {8, 0}, /* max packet */ 2469 .bInterval = 255, 2470 }; 2471 2472 Static const usb_hub_descriptor_t ohci_hubd = { 2473 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2474 .bDescriptorType = UDESC_HUB, 2475 }; 2476 2477 /* 2478 * Simulate a hardware hub by handling all the necessary requests. 2479 */ 2480 Static usbd_status 2481 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2482 { 2483 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2484 usbd_status err; 2485 2486 /* Insert last in queue. */ 2487 mutex_enter(&sc->sc_lock); 2488 err = usb_insert_transfer(xfer); 2489 mutex_exit(&sc->sc_lock); 2490 if (err) 2491 return (err); 2492 2493 /* Pipe isn't running, start first */ 2494 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2495 } 2496 2497 Static usbd_status 2498 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2499 { 2500 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2501 usb_device_request_t *req; 2502 void *buf = NULL; 2503 int port, i; 2504 int len, value, index, l, totlen = 0; 2505 usb_port_status_t ps; 2506 usb_hub_descriptor_t hubd; 2507 usbd_status err; 2508 u_int32_t v; 2509 2510 if (sc->sc_dying) 2511 return (USBD_IOERROR); 2512 2513 #ifdef DIAGNOSTIC 2514 if (!(xfer->rqflags & URQ_REQUEST)) 2515 /* XXX panic */ 2516 return (USBD_INVAL); 2517 #endif 2518 req = &xfer->request; 2519 2520 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2521 req->bmRequestType, req->bRequest)); 2522 2523 len = UGETW(req->wLength); 2524 value = UGETW(req->wValue); 2525 index = UGETW(req->wIndex); 2526 2527 if (len != 0) 2528 buf = KERNADDR(&xfer->dmabuf, 0); 2529 2530 #define C(x,y) ((x) | ((y) << 8)) 2531 switch(C(req->bRequest, req->bmRequestType)) { 2532 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2533 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2534 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2535 /* 2536 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2537 * for the integrated root hub. 2538 */ 2539 break; 2540 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2541 if (len > 0) { 2542 *(u_int8_t *)buf = sc->sc_conf; 2543 totlen = 1; 2544 } 2545 break; 2546 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2547 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2548 if (len == 0) 2549 break; 2550 switch(value >> 8) { 2551 case UDESC_DEVICE: 2552 if ((value & 0xff) != 0) { 2553 err = USBD_IOERROR; 2554 goto ret; 2555 } 2556 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2557 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2558 memcpy(buf, &ohci_devd, l); 2559 break; 2560 case UDESC_CONFIG: 2561 if ((value & 0xff) != 0) { 2562 err = USBD_IOERROR; 2563 goto ret; 2564 } 2565 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2566 memcpy(buf, &ohci_confd, l); 2567 buf = (char *)buf + l; 2568 len -= l; 2569 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2570 totlen += l; 2571 memcpy(buf, &ohci_ifcd, l); 2572 buf = (char *)buf + l; 2573 len -= l; 2574 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2575 totlen += l; 2576 memcpy(buf, &ohci_endpd, l); 2577 break; 2578 case UDESC_STRING: 2579 #define sd ((usb_string_descriptor_t *)buf) 2580 switch (value & 0xff) { 2581 case 0: /* Language table */ 2582 totlen = usb_makelangtbl(sd, len); 2583 break; 2584 case 1: /* Vendor */ 2585 totlen = usb_makestrdesc(sd, len, 2586 sc->sc_vendor); 2587 break; 2588 case 2: /* Product */ 2589 totlen = usb_makestrdesc(sd, len, 2590 "OHCI root hub"); 2591 break; 2592 } 2593 #undef sd 2594 break; 2595 default: 2596 err = USBD_IOERROR; 2597 goto ret; 2598 } 2599 break; 2600 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2601 if (len > 0) { 2602 *(u_int8_t *)buf = 0; 2603 totlen = 1; 2604 } 2605 break; 2606 case C(UR_GET_STATUS, UT_READ_DEVICE): 2607 if (len > 1) { 2608 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2609 totlen = 2; 2610 } 2611 break; 2612 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2613 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2614 if (len > 1) { 2615 USETW(((usb_status_t *)buf)->wStatus, 0); 2616 totlen = 2; 2617 } 2618 break; 2619 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2620 if (value >= USB_MAX_DEVICES) { 2621 err = USBD_IOERROR; 2622 goto ret; 2623 } 2624 sc->sc_addr = value; 2625 break; 2626 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2627 if (value != 0 && value != 1) { 2628 err = USBD_IOERROR; 2629 goto ret; 2630 } 2631 sc->sc_conf = value; 2632 break; 2633 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2634 break; 2635 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2636 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2637 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2638 err = USBD_IOERROR; 2639 goto ret; 2640 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2641 break; 2642 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2643 break; 2644 /* Hub requests */ 2645 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2646 break; 2647 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2648 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2649 "port=%d feature=%d\n", 2650 index, value)); 2651 if (index < 1 || index > sc->sc_noport) { 2652 err = USBD_IOERROR; 2653 goto ret; 2654 } 2655 port = OHCI_RH_PORT_STATUS(index); 2656 switch(value) { 2657 case UHF_PORT_ENABLE: 2658 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2659 break; 2660 case UHF_PORT_SUSPEND: 2661 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2662 break; 2663 case UHF_PORT_POWER: 2664 /* Yes, writing to the LOW_SPEED bit clears power. */ 2665 OWRITE4(sc, port, UPS_LOW_SPEED); 2666 break; 2667 case UHF_C_PORT_CONNECTION: 2668 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2669 break; 2670 case UHF_C_PORT_ENABLE: 2671 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2672 break; 2673 case UHF_C_PORT_SUSPEND: 2674 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2675 break; 2676 case UHF_C_PORT_OVER_CURRENT: 2677 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2678 break; 2679 case UHF_C_PORT_RESET: 2680 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2681 break; 2682 default: 2683 err = USBD_IOERROR; 2684 goto ret; 2685 } 2686 switch(value) { 2687 case UHF_C_PORT_CONNECTION: 2688 case UHF_C_PORT_ENABLE: 2689 case UHF_C_PORT_SUSPEND: 2690 case UHF_C_PORT_OVER_CURRENT: 2691 case UHF_C_PORT_RESET: 2692 /* Enable RHSC interrupt if condition is cleared. */ 2693 if ((OREAD4(sc, port) >> 16) == 0) 2694 ohci_rhsc_enable(sc); 2695 break; 2696 default: 2697 break; 2698 } 2699 break; 2700 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2701 if (len == 0) 2702 break; 2703 if ((value & 0xff) != 0) { 2704 err = USBD_IOERROR; 2705 goto ret; 2706 } 2707 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2708 hubd = ohci_hubd; 2709 hubd.bNbrPorts = sc->sc_noport; 2710 USETW(hubd.wHubCharacteristics, 2711 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2712 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2713 /* XXX overcurrent */ 2714 ); 2715 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2716 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2717 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2718 hubd.DeviceRemovable[i++] = (u_int8_t)v; 2719 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2720 l = min(len, hubd.bDescLength); 2721 totlen = l; 2722 memcpy(buf, &hubd, l); 2723 break; 2724 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2725 if (len != 4) { 2726 err = USBD_IOERROR; 2727 goto ret; 2728 } 2729 memset(buf, 0, len); /* ? XXX */ 2730 totlen = len; 2731 break; 2732 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2733 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2734 index)); 2735 if (index < 1 || index > sc->sc_noport) { 2736 err = USBD_IOERROR; 2737 goto ret; 2738 } 2739 if (len != 4) { 2740 err = USBD_IOERROR; 2741 goto ret; 2742 } 2743 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2744 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2745 v)); 2746 USETW(ps.wPortStatus, v); 2747 USETW(ps.wPortChange, v >> 16); 2748 l = min(len, sizeof ps); 2749 memcpy(buf, &ps, l); 2750 totlen = l; 2751 break; 2752 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2753 err = USBD_IOERROR; 2754 goto ret; 2755 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2756 break; 2757 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2758 if (index < 1 || index > sc->sc_noport) { 2759 err = USBD_IOERROR; 2760 goto ret; 2761 } 2762 port = OHCI_RH_PORT_STATUS(index); 2763 switch(value) { 2764 case UHF_PORT_ENABLE: 2765 OWRITE4(sc, port, UPS_PORT_ENABLED); 2766 break; 2767 case UHF_PORT_SUSPEND: 2768 OWRITE4(sc, port, UPS_SUSPEND); 2769 break; 2770 case UHF_PORT_RESET: 2771 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2772 index)); 2773 OWRITE4(sc, port, UPS_RESET); 2774 for (i = 0; i < 5; i++) { 2775 usb_delay_ms(&sc->sc_bus, 2776 USB_PORT_ROOT_RESET_DELAY); 2777 if (sc->sc_dying) { 2778 err = USBD_IOERROR; 2779 goto ret; 2780 } 2781 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2782 break; 2783 } 2784 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2785 index, OREAD4(sc, port))); 2786 break; 2787 case UHF_PORT_POWER: 2788 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2789 "%d\n", index)); 2790 OWRITE4(sc, port, UPS_PORT_POWER); 2791 break; 2792 default: 2793 err = USBD_IOERROR; 2794 goto ret; 2795 } 2796 break; 2797 default: 2798 err = USBD_IOERROR; 2799 goto ret; 2800 } 2801 xfer->actlen = totlen; 2802 err = USBD_NORMAL_COMPLETION; 2803 ret: 2804 xfer->status = err; 2805 mutex_enter(&sc->sc_lock); 2806 usb_transfer_complete(xfer); 2807 mutex_exit(&sc->sc_lock); 2808 return (USBD_IN_PROGRESS); 2809 } 2810 2811 /* Abort a root control request. */ 2812 Static void 2813 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2814 { 2815 /* Nothing to do, all transfers are synchronous. */ 2816 } 2817 2818 /* Close the root pipe. */ 2819 Static void 2820 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2821 { 2822 DPRINTF(("ohci_root_ctrl_close\n")); 2823 /* Nothing to do. */ 2824 } 2825 2826 Static usbd_status 2827 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2828 { 2829 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2830 usbd_status err; 2831 2832 /* Insert last in queue. */ 2833 mutex_enter(&sc->sc_lock); 2834 err = usb_insert_transfer(xfer); 2835 mutex_exit(&sc->sc_lock); 2836 if (err) 2837 return (err); 2838 2839 /* Pipe isn't running, start first */ 2840 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2841 } 2842 2843 Static usbd_status 2844 ohci_root_intr_start(usbd_xfer_handle xfer) 2845 { 2846 usbd_pipe_handle pipe = xfer->pipe; 2847 ohci_softc_t *sc = pipe->device->bus->hci_private; 2848 2849 if (sc->sc_dying) 2850 return (USBD_IOERROR); 2851 2852 mutex_enter(&sc->sc_lock); 2853 KASSERT(sc->sc_intrxfer == NULL); 2854 sc->sc_intrxfer = xfer; 2855 mutex_exit(&sc->sc_lock); 2856 2857 return (USBD_IN_PROGRESS); 2858 } 2859 2860 /* Abort a root interrupt request. */ 2861 Static void 2862 ohci_root_intr_abort(usbd_xfer_handle xfer) 2863 { 2864 #ifdef DIAGNOSTIC 2865 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2866 #endif 2867 2868 KASSERT(mutex_owned(&sc->sc_lock)); 2869 2870 if (xfer->pipe->intrxfer == xfer) { 2871 DPRINTF(("ohci_root_intr_abort: remove\n")); 2872 xfer->pipe->intrxfer = NULL; 2873 } 2874 xfer->status = USBD_CANCELLED; 2875 usb_transfer_complete(xfer); 2876 } 2877 2878 /* Close the root pipe. */ 2879 Static void 2880 ohci_root_intr_close(usbd_pipe_handle pipe) 2881 { 2882 ohci_softc_t *sc = pipe->device->bus->hci_private; 2883 2884 KASSERT(mutex_owned(&sc->sc_lock)); 2885 2886 DPRINTF(("ohci_root_intr_close\n")); 2887 2888 sc->sc_intrxfer = NULL; 2889 } 2890 2891 /************************/ 2892 2893 Static usbd_status 2894 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2895 { 2896 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2897 usbd_status err; 2898 2899 /* Insert last in queue. */ 2900 mutex_enter(&sc->sc_lock); 2901 err = usb_insert_transfer(xfer); 2902 mutex_exit(&sc->sc_lock); 2903 if (err) 2904 return (err); 2905 2906 /* Pipe isn't running, start first */ 2907 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2908 } 2909 2910 Static usbd_status 2911 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2912 { 2913 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2914 usbd_status err; 2915 2916 if (sc->sc_dying) 2917 return (USBD_IOERROR); 2918 2919 #ifdef DIAGNOSTIC 2920 if (!(xfer->rqflags & URQ_REQUEST)) { 2921 /* XXX panic */ 2922 printf("ohci_device_ctrl_transfer: not a request\n"); 2923 return (USBD_INVAL); 2924 } 2925 #endif 2926 2927 mutex_enter(&sc->sc_lock); 2928 err = ohci_device_request(xfer); 2929 mutex_exit(&sc->sc_lock); 2930 if (err) 2931 return (err); 2932 2933 if (sc->sc_bus.use_polling) 2934 ohci_waitintr(sc, xfer); 2935 return (USBD_IN_PROGRESS); 2936 } 2937 2938 /* Abort a device control request. */ 2939 Static void 2940 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2941 { 2942 #ifdef DIAGNOSTIC 2943 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2944 #endif 2945 2946 KASSERT(mutex_owned(&sc->sc_lock)); 2947 2948 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2949 ohci_abort_xfer(xfer, USBD_CANCELLED); 2950 } 2951 2952 /* Close a device control pipe. */ 2953 Static void 2954 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2955 { 2956 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2957 ohci_softc_t *sc = pipe->device->bus->hci_private; 2958 2959 KASSERT(mutex_owned(&sc->sc_lock)); 2960 2961 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2962 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2963 ohci_free_std(sc, opipe->tail.td); 2964 } 2965 2966 /************************/ 2967 2968 Static void 2969 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2970 { 2971 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2972 ohci_softc_t *sc = pipe->device->bus->hci_private; 2973 2974 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2975 } 2976 2977 Static void 2978 ohci_noop(usbd_pipe_handle pipe) 2979 { 2980 } 2981 2982 Static usbd_status 2983 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2984 { 2985 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2986 usbd_status err; 2987 2988 /* Insert last in queue. */ 2989 mutex_enter(&sc->sc_lock); 2990 err = usb_insert_transfer(xfer); 2991 mutex_exit(&sc->sc_lock); 2992 if (err) 2993 return (err); 2994 2995 /* Pipe isn't running, start first */ 2996 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2997 } 2998 2999 Static usbd_status 3000 ohci_device_bulk_start(usbd_xfer_handle xfer) 3001 { 3002 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3003 usbd_device_handle dev = opipe->pipe.device; 3004 ohci_softc_t *sc = dev->bus->hci_private; 3005 int addr = dev->address; 3006 ohci_soft_td_t *data, *tail, *tdp; 3007 ohci_soft_ed_t *sed; 3008 int len, isread, endpt; 3009 usbd_status err; 3010 3011 if (sc->sc_dying) 3012 return (USBD_IOERROR); 3013 3014 #ifdef DIAGNOSTIC 3015 if (xfer->rqflags & URQ_REQUEST) { 3016 /* XXX panic */ 3017 printf("ohci_device_bulk_start: a request\n"); 3018 return (USBD_INVAL); 3019 } 3020 #endif 3021 3022 mutex_enter(&sc->sc_lock); 3023 3024 len = xfer->length; 3025 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3026 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3027 sed = opipe->sed; 3028 3029 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3030 "flags=%d endpt=%d\n", xfer, len, isread, xfer->flags, 3031 endpt)); 3032 3033 opipe->u.bulk.isread = isread; 3034 opipe->u.bulk.length = len; 3035 3036 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3037 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3038 /* Update device address */ 3039 sed->ed.ed_flags = HTOO32( 3040 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3041 OHCI_ED_SET_FA(addr)); 3042 3043 /* Allocate a chain of new TDs (including a new tail). */ 3044 data = opipe->tail.td; 3045 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3046 data, &tail); 3047 if (err) 3048 return err; 3049 3050 /* We want interrupt at the end of the transfer. */ 3051 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3052 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3053 tail->flags |= OHCI_CALL_DONE; 3054 tail = tail->nexttd; /* point at sentinel */ 3055 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3056 sizeof(tail->td.td_flags), 3057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3058 if (err) { 3059 mutex_exit(&sc->sc_lock); 3060 return (err); 3061 } 3062 3063 tail->xfer = NULL; 3064 xfer->hcpriv = data; 3065 3066 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3067 "td_cbp=0x%08x td_be=0x%08x\n", 3068 (int)O32TOH(sed->ed.ed_flags), 3069 (int)O32TOH(data->td.td_flags), 3070 (int)O32TOH(data->td.td_cbp), 3071 (int)O32TOH(data->td.td_be))); 3072 3073 #ifdef OHCI_DEBUG 3074 if (ohcidebug > 5) { 3075 ohci_dump_ed(sc, sed); 3076 ohci_dump_tds(sc, data); 3077 } 3078 #endif 3079 3080 /* Insert ED in schedule */ 3081 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3082 tdp->xfer = xfer; 3083 } 3084 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3085 opipe->tail.td = tail; 3086 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3087 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3088 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3089 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3090 if (xfer->timeout && !sc->sc_bus.use_polling) { 3091 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3092 ohci_timeout, xfer); 3093 } 3094 mutex_exit(&sc->sc_lock); 3095 3096 #if 0 3097 /* This goes wrong if we are too slow. */ 3098 if (ohcidebug > 10) { 3099 delay(10000); 3100 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3101 OREAD4(sc, OHCI_COMMAND_STATUS))); 3102 ohci_dump_ed(sc, sed); 3103 ohci_dump_tds(sc, data); 3104 } 3105 #endif 3106 3107 return (USBD_IN_PROGRESS); 3108 } 3109 3110 Static void 3111 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3112 { 3113 #ifdef DIAGNOSTIC 3114 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3115 #endif 3116 3117 KASSERT(mutex_owned(&sc->sc_lock)); 3118 3119 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3120 ohci_abort_xfer(xfer, USBD_CANCELLED); 3121 } 3122 3123 /* 3124 * Close a device bulk pipe. 3125 */ 3126 Static void 3127 ohci_device_bulk_close(usbd_pipe_handle pipe) 3128 { 3129 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3130 ohci_softc_t *sc = pipe->device->bus->hci_private; 3131 3132 KASSERT(mutex_owned(&sc->sc_lock)); 3133 3134 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3135 ohci_close_pipe(pipe, sc->sc_bulk_head); 3136 ohci_free_std(sc, opipe->tail.td); 3137 } 3138 3139 /************************/ 3140 3141 Static usbd_status 3142 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3143 { 3144 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3145 usbd_status err; 3146 3147 /* Insert last in queue. */ 3148 mutex_enter(&sc->sc_lock); 3149 err = usb_insert_transfer(xfer); 3150 mutex_exit(&sc->sc_lock); 3151 if (err) 3152 return (err); 3153 3154 /* Pipe isn't running, start first */ 3155 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3156 } 3157 3158 Static usbd_status 3159 ohci_device_intr_start(usbd_xfer_handle xfer) 3160 { 3161 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3162 usbd_device_handle dev = opipe->pipe.device; 3163 ohci_softc_t *sc = dev->bus->hci_private; 3164 ohci_soft_ed_t *sed = opipe->sed; 3165 ohci_soft_td_t *data, *tail; 3166 int len, isread, endpt; 3167 3168 if (sc->sc_dying) 3169 return (USBD_IOERROR); 3170 3171 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3172 "flags=%d priv=%p\n", 3173 xfer, xfer->length, xfer->flags, xfer->priv)); 3174 3175 #ifdef DIAGNOSTIC 3176 if (xfer->rqflags & URQ_REQUEST) 3177 panic("ohci_device_intr_transfer: a request"); 3178 #endif 3179 3180 len = xfer->length; 3181 endpt = xfer->pipe->endpoint->edesc->bEndpointAddress; 3182 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3183 3184 data = opipe->tail.td; 3185 mutex_enter(&sc->sc_lock); 3186 tail = ohci_alloc_std(sc); 3187 mutex_exit(&sc->sc_lock); 3188 if (tail == NULL) 3189 return (USBD_NOMEM); 3190 tail->xfer = NULL; 3191 3192 data->td.td_flags = HTOO32( 3193 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3194 OHCI_TD_NOCC | 3195 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3196 if (xfer->flags & USBD_SHORT_XFER_OK) 3197 data->td.td_flags |= HTOO32(OHCI_TD_R); 3198 data->td.td_cbp = HTOO32(DMAADDR(&xfer->dmabuf, 0)); 3199 data->nexttd = tail; 3200 data->td.td_nexttd = HTOO32(tail->physaddr); 3201 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3202 data->len = len; 3203 data->xfer = xfer; 3204 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3205 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3207 xfer->hcpriv = data; 3208 3209 #ifdef OHCI_DEBUG 3210 if (ohcidebug > 5) { 3211 DPRINTF(("ohci_device_intr_transfer:\n")); 3212 ohci_dump_ed(sc, sed); 3213 ohci_dump_tds(sc, data); 3214 } 3215 #endif 3216 3217 /* Insert ED in schedule */ 3218 mutex_enter(&sc->sc_lock); 3219 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3220 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3221 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3222 opipe->tail.td = tail; 3223 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3224 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3226 3227 #if 0 3228 /* 3229 * This goes horribly wrong, printing thousands of descriptors, 3230 * because false references are followed due to the fact that the 3231 * TD is gone. 3232 */ 3233 if (ohcidebug > 5) { 3234 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3235 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3236 OREAD4(sc, OHCI_COMMAND_STATUS))); 3237 ohci_dump_ed(sc, sed); 3238 ohci_dump_tds(sc, data); 3239 } 3240 #endif 3241 mutex_exit(&sc->sc_lock); 3242 3243 return (USBD_IN_PROGRESS); 3244 } 3245 3246 /* Abort a device interrupt request. */ 3247 Static void 3248 ohci_device_intr_abort(usbd_xfer_handle xfer) 3249 { 3250 #ifdef DIAGNOSTIC 3251 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3252 #endif 3253 3254 KASSERT(mutex_owned(&sc->sc_lock)); 3255 3256 if (xfer->pipe->intrxfer == xfer) { 3257 DPRINTF(("ohci_device_intr_abort: remove\n")); 3258 xfer->pipe->intrxfer = NULL; 3259 } 3260 ohci_abort_xfer(xfer, USBD_CANCELLED); 3261 } 3262 3263 /* Close a device interrupt pipe. */ 3264 Static void 3265 ohci_device_intr_close(usbd_pipe_handle pipe) 3266 { 3267 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3268 ohci_softc_t *sc = pipe->device->bus->hci_private; 3269 int nslots = opipe->u.intr.nslots; 3270 int pos = opipe->u.intr.pos; 3271 int j; 3272 ohci_soft_ed_t *p, *sed = opipe->sed; 3273 3274 KASSERT(mutex_owned(&sc->sc_lock)); 3275 3276 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3277 pipe, nslots, pos)); 3278 usb_syncmem(&sed->dma, sed->offs, 3279 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3280 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3281 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3282 sizeof(sed->ed.ed_flags), 3283 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3284 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3285 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3286 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3287 3288 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3289 continue; 3290 #ifdef DIAGNOSTIC 3291 if (p == NULL) 3292 panic("ohci_device_intr_close: ED not found"); 3293 #endif 3294 p->next = sed->next; 3295 p->ed.ed_nexted = sed->ed.ed_nexted; 3296 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3297 sizeof(p->ed.ed_nexted), 3298 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3299 3300 for (j = 0; j < nslots; j++) 3301 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3302 3303 ohci_free_std(sc, opipe->tail.td); 3304 ohci_free_sed(sc, opipe->sed); 3305 } 3306 3307 Static usbd_status 3308 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3309 { 3310 int i, j, best; 3311 u_int npoll, slow, shigh, nslots; 3312 u_int bestbw, bw; 3313 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3314 3315 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3316 if (ival == 0) { 3317 printf("ohci_setintr: 0 interval\n"); 3318 return (USBD_INVAL); 3319 } 3320 3321 npoll = OHCI_NO_INTRS; 3322 while (npoll > ival) 3323 npoll /= 2; 3324 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3325 3326 /* 3327 * We now know which level in the tree the ED must go into. 3328 * Figure out which slot has most bandwidth left over. 3329 * Slots to examine: 3330 * npoll 3331 * 1 0 3332 * 2 1 2 3333 * 4 3 4 5 6 3334 * 8 7 8 9 10 11 12 13 14 3335 * N (N-1) .. (N-1+N-1) 3336 */ 3337 slow = npoll-1; 3338 shigh = slow + npoll; 3339 nslots = OHCI_NO_INTRS / npoll; 3340 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3341 bw = 0; 3342 for (j = 0; j < nslots; j++) 3343 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3344 if (bw < bestbw) { 3345 best = i; 3346 bestbw = bw; 3347 } 3348 } 3349 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3350 best, slow, shigh, bestbw)); 3351 3352 mutex_enter(&sc->sc_lock); 3353 hsed = sc->sc_eds[best]; 3354 sed->next = hsed->next; 3355 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3356 sizeof(hsed->ed.ed_flags), 3357 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3358 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3359 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3360 sizeof(sed->ed.ed_flags), 3361 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3362 hsed->next = sed; 3363 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3364 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3365 sizeof(hsed->ed.ed_flags), 3366 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3367 mutex_exit(&sc->sc_lock); 3368 3369 for (j = 0; j < nslots; j++) 3370 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3371 opipe->u.intr.nslots = nslots; 3372 opipe->u.intr.pos = best; 3373 3374 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3375 return (USBD_NORMAL_COMPLETION); 3376 } 3377 3378 /***********************/ 3379 3380 usbd_status 3381 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3382 { 3383 ohci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3384 usbd_status err; 3385 3386 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3387 3388 /* Put it on our queue, */ 3389 mutex_enter(&sc->sc_lock); 3390 err = usb_insert_transfer(xfer); 3391 mutex_exit(&sc->sc_lock); 3392 3393 /* bail out on error, */ 3394 if (err && err != USBD_IN_PROGRESS) 3395 return (err); 3396 3397 /* XXX should check inuse here */ 3398 3399 /* insert into schedule, */ 3400 ohci_device_isoc_enter(xfer); 3401 3402 /* and start if the pipe wasn't running */ 3403 if (!err) 3404 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->pipe->queue)); 3405 3406 return (err); 3407 } 3408 3409 void 3410 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3411 { 3412 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3413 usbd_device_handle dev = opipe->pipe.device; 3414 ohci_softc_t *sc = dev->bus->hci_private; 3415 ohci_soft_ed_t *sed = opipe->sed; 3416 struct iso *iso = &opipe->u.iso; 3417 ohci_soft_itd_t *sitd, *nsitd; 3418 ohci_physaddr_t buf, offs, noffs, bp0; 3419 int i, ncur, nframes; 3420 3421 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3422 "nframes=%d\n", 3423 iso->inuse, iso->next, xfer, xfer->nframes)); 3424 3425 if (sc->sc_dying) 3426 return; 3427 3428 if (iso->next == -1) { 3429 /* Not in use yet, schedule it a few frames ahead. */ 3430 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3431 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3432 iso->next)); 3433 } 3434 3435 sitd = opipe->tail.itd; 3436 buf = DMAADDR(&xfer->dmabuf, 0); 3437 bp0 = OHCI_PAGE(buf); 3438 offs = OHCI_PAGE_OFFSET(buf); 3439 nframes = xfer->nframes; 3440 xfer->hcpriv = sitd; 3441 for (i = ncur = 0; i < nframes; i++, ncur++) { 3442 noffs = offs + xfer->frlengths[i]; 3443 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3444 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3445 3446 /* Allocate next ITD */ 3447 mutex_enter(&sc->sc_lock); 3448 nsitd = ohci_alloc_sitd(sc); 3449 mutex_exit(&sc->sc_lock); 3450 if (nsitd == NULL) { 3451 /* XXX what now? */ 3452 printf("%s: isoc TD alloc failed\n", 3453 device_xname(sc->sc_dev)); 3454 return; 3455 } 3456 3457 /* Fill current ITD */ 3458 sitd->itd.itd_flags = HTOO32( 3459 OHCI_ITD_NOCC | 3460 OHCI_ITD_SET_SF(iso->next) | 3461 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3462 OHCI_ITD_SET_FC(ncur)); 3463 sitd->itd.itd_bp0 = HTOO32(bp0); 3464 sitd->nextitd = nsitd; 3465 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3466 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3467 sitd->xfer = xfer; 3468 sitd->flags = 0; 3469 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3470 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3471 3472 sitd = nsitd; 3473 iso->next = iso->next + ncur; 3474 bp0 = OHCI_PAGE(buf + offs); 3475 ncur = 0; 3476 } 3477 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3478 offs = noffs; 3479 } 3480 mutex_enter(&sc->sc_lock); 3481 nsitd = ohci_alloc_sitd(sc); 3482 mutex_exit(&sc->sc_lock); 3483 if (nsitd == NULL) { 3484 /* XXX what now? */ 3485 printf("%s: isoc TD alloc failed\n", 3486 device_xname(sc->sc_dev)); 3487 return; 3488 } 3489 /* Fixup last used ITD */ 3490 sitd->itd.itd_flags = HTOO32( 3491 OHCI_ITD_NOCC | 3492 OHCI_ITD_SET_SF(iso->next) | 3493 OHCI_ITD_SET_DI(0) | 3494 OHCI_ITD_SET_FC(ncur)); 3495 sitd->itd.itd_bp0 = HTOO32(bp0); 3496 sitd->nextitd = nsitd; 3497 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3498 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3499 sitd->xfer = xfer; 3500 sitd->flags = OHCI_CALL_DONE; 3501 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3503 3504 iso->next = iso->next + ncur; 3505 iso->inuse += nframes; 3506 3507 xfer->actlen = offs; /* XXX pretend we did it all */ 3508 3509 xfer->status = USBD_IN_PROGRESS; 3510 3511 #ifdef OHCI_DEBUG 3512 if (ohcidebug > 5) { 3513 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3514 O32TOH(sc->sc_hcca->hcca_frame_number))); 3515 ohci_dump_itds(sc, xfer->hcpriv); 3516 ohci_dump_ed(sc, sed); 3517 } 3518 #endif 3519 3520 mutex_enter(&sc->sc_lock); 3521 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3522 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3523 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3524 opipe->tail.itd = nsitd; 3525 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3526 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3527 sizeof(sed->ed.ed_flags), 3528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3529 mutex_exit(&sc->sc_lock); 3530 3531 #ifdef OHCI_DEBUG 3532 if (ohcidebug > 5) { 3533 delay(150000); 3534 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3535 O32TOH(sc->sc_hcca->hcca_frame_number))); 3536 ohci_dump_itds(sc, xfer->hcpriv); 3537 ohci_dump_ed(sc, sed); 3538 } 3539 #endif 3540 } 3541 3542 usbd_status 3543 ohci_device_isoc_start(usbd_xfer_handle xfer) 3544 { 3545 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3546 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3547 3548 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3549 3550 mutex_enter(&sc->sc_lock); 3551 3552 if (sc->sc_dying) { 3553 mutex_exit(&sc->sc_lock); 3554 return (USBD_IOERROR); 3555 } 3556 3557 #ifdef DIAGNOSTIC 3558 if (xfer->status != USBD_IN_PROGRESS) 3559 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3560 #endif 3561 3562 /* XXX anything to do? */ 3563 3564 mutex_exit(&sc->sc_lock); 3565 3566 return (USBD_IN_PROGRESS); 3567 } 3568 3569 void 3570 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3571 { 3572 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->pipe; 3573 ohci_softc_t *sc = opipe->pipe.device->bus->hci_private; 3574 ohci_soft_ed_t *sed; 3575 ohci_soft_itd_t *sitd; 3576 3577 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3578 3579 KASSERT(mutex_owned(&sc->sc_lock)); 3580 3581 /* Transfer is already done. */ 3582 if (xfer->status != USBD_NOT_STARTED && 3583 xfer->status != USBD_IN_PROGRESS) { 3584 printf("ohci_device_isoc_abort: early return\n"); 3585 goto done; 3586 } 3587 3588 /* Give xfer the requested abort code. */ 3589 xfer->status = USBD_CANCELLED; 3590 3591 sed = opipe->sed; 3592 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3593 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3594 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3595 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3596 sizeof(sed->ed.ed_flags), 3597 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3598 3599 sitd = xfer->hcpriv; 3600 #ifdef DIAGNOSTIC 3601 if (sitd == NULL) { 3602 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3603 goto done; 3604 } 3605 #endif 3606 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3607 #ifdef DIAGNOSTIC 3608 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3609 sitd->isdone = 1; 3610 #endif 3611 } 3612 3613 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3614 3615 /* Run callback. */ 3616 usb_transfer_complete(xfer); 3617 3618 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3619 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3620 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3621 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3622 3623 done: 3624 KASSERT(mutex_owned(&sc->sc_lock)); 3625 } 3626 3627 void 3628 ohci_device_isoc_done(usbd_xfer_handle xfer) 3629 { 3630 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3631 } 3632 3633 usbd_status 3634 ohci_setup_isoc(usbd_pipe_handle pipe) 3635 { 3636 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3637 ohci_softc_t *sc = pipe->device->bus->hci_private; 3638 struct iso *iso = &opipe->u.iso; 3639 3640 iso->next = -1; 3641 iso->inuse = 0; 3642 3643 mutex_enter(&sc->sc_lock); 3644 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3645 mutex_exit(&sc->sc_lock); 3646 3647 return (USBD_NORMAL_COMPLETION); 3648 } 3649 3650 void 3651 ohci_device_isoc_close(usbd_pipe_handle pipe) 3652 { 3653 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3654 ohci_softc_t *sc = pipe->device->bus->hci_private; 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 3658 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3659 ohci_close_pipe(pipe, sc->sc_isoc_head); 3660 #ifdef DIAGNOSTIC 3661 opipe->tail.itd->isdone = 1; 3662 #endif 3663 ohci_free_sitd(sc, opipe->tail.itd); 3664 } 3665
Indexes created Wed Sep 24 15:09:51 GMT 2025