ohci.c revision 1.254.2.10
1 /* $NetBSD: ohci.c,v 1.254.2.10 2014/12/03 22:40:55 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.10 2014/12/03 22:40:55 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub_subr.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 131 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 132 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 133 134 Static usbd_status ohci_root_ctrl_transfer(usbd_xfer_handle); 135 Static usbd_status ohci_root_ctrl_start(usbd_xfer_handle); 136 Static void ohci_root_ctrl_abort(usbd_xfer_handle); 137 Static void ohci_root_ctrl_close(usbd_pipe_handle); 138 Static void ohci_root_ctrl_done(usbd_xfer_handle); 139 140 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 141 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 142 Static void ohci_root_intr_abort(usbd_xfer_handle); 143 Static void ohci_root_intr_close(usbd_pipe_handle); 144 Static void ohci_root_intr_done(usbd_xfer_handle); 145 146 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 147 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 148 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 149 Static void ohci_device_ctrl_close(usbd_pipe_handle); 150 Static void ohci_device_ctrl_done(usbd_xfer_handle); 151 152 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 153 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 154 Static void ohci_device_bulk_abort(usbd_xfer_handle); 155 Static void ohci_device_bulk_close(usbd_pipe_handle); 156 Static void ohci_device_bulk_done(usbd_xfer_handle); 157 158 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 159 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 160 Static void ohci_device_intr_abort(usbd_xfer_handle); 161 Static void ohci_device_intr_close(usbd_pipe_handle); 162 Static void ohci_device_intr_done(usbd_xfer_handle); 163 164 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 165 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 166 Static void ohci_device_isoc_abort(usbd_xfer_handle); 167 Static void ohci_device_isoc_close(usbd_pipe_handle); 168 Static void ohci_device_isoc_done(usbd_xfer_handle); 169 170 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 171 struct ohci_pipe *pipe, int ival); 172 173 Static void ohci_timeout(void *); 174 Static void ohci_timeout_task(void *); 175 Static void ohci_rhsc_enable(void *); 176 177 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 178 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 179 180 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 181 Static void ohci_noop(usbd_pipe_handle pipe); 182 183 #ifdef OHCI_DEBUG 184 Static void ohci_dumpregs(ohci_softc_t *); 185 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 186 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 187 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 188 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 189 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 190 #endif 191 192 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 193 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 194 #define OWRITE1(sc, r, x) \ 195 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 196 #define OWRITE2(sc, r, x) \ 197 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 198 #define OWRITE4(sc, r, x) \ 199 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 200 201 static __inline uint32_t 202 OREAD4(ohci_softc_t *sc, bus_size_t r) 203 { 204 205 OBARR(sc); 206 return bus_space_read_4(sc->iot, sc->ioh, r); 207 } 208 209 /* Reverse the bits in a value 0 .. 31 */ 210 Static uint8_t revbits[OHCI_NO_INTRS] = 211 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 212 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 213 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 214 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 215 216 struct ohci_pipe { 217 struct usbd_pipe pipe; 218 ohci_soft_ed_t *sed; 219 union { 220 ohci_soft_td_t *td; 221 ohci_soft_itd_t *itd; 222 } tail; 223 /* Info needed for different pipe kinds. */ 224 union { 225 /* Control pipe */ 226 struct { 227 usb_dma_t reqdma; 228 u_int length; 229 ohci_soft_td_t *setup, *data, *stat; 230 } ctl; 231 /* Interrupt pipe */ 232 struct { 233 int nslots; 234 int pos; 235 } intr; 236 /* Bulk pipe */ 237 struct { 238 u_int length; 239 int isread; 240 } bulk; 241 /* Iso pipe */ 242 struct iso { 243 int next, inuse; 244 } iso; 245 } u; 246 }; 247 248 #define OHCI_INTR_ENDPT 1 249 250 Static const struct usbd_bus_methods ohci_bus_methods = { 251 .ubm_open = ohci_open, 252 .ubm_softint = ohci_softintr, 253 .ubm_dopoll = ohci_poll, 254 .ubm_allocx = ohci_allocx, 255 .ubm_freex = ohci_freex, 256 .ubm_getlock = ohci_get_lock, 257 .ubm_newdev = NULL, 258 }; 259 260 Static const struct usbd_pipe_methods ohci_root_ctrl_methods = { 261 .upm_transfer = ohci_root_ctrl_transfer, 262 .upm_start = ohci_root_ctrl_start, 263 .upm_abort = ohci_root_ctrl_abort, 264 .upm_close = ohci_root_ctrl_close, 265 .upm_cleartoggle = ohci_noop, 266 .upm_done = ohci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 270 .upm_transfer = ohci_root_intr_transfer, 271 .upm_start = ohci_root_intr_start, 272 .upm_abort = ohci_root_intr_abort, 273 .upm_close = ohci_root_intr_close, 274 .upm_cleartoggle = ohci_noop, 275 .upm_done = ohci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 279 .upm_transfer = ohci_device_ctrl_transfer, 280 .upm_start = ohci_device_ctrl_start, 281 .upm_abort = ohci_device_ctrl_abort, 282 .upm_close = ohci_device_ctrl_close, 283 .upm_cleartoggle = ohci_noop, 284 .upm_done = ohci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 288 .upm_transfer = ohci_device_intr_transfer, 289 .upm_start = ohci_device_intr_start, 290 .upm_abort = ohci_device_intr_abort, 291 .upm_close = ohci_device_intr_close, 292 .upm_cleartoggle = ohci_device_clear_toggle, 293 .upm_done = ohci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 297 .upm_transfer = ohci_device_bulk_transfer, 298 .upm_start = ohci_device_bulk_start, 299 .upm_abort = ohci_device_bulk_abort, 300 .upm_close = ohci_device_bulk_close, 301 .upm_cleartoggle = ohci_device_clear_toggle, 302 .upm_done = ohci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 306 .upm_transfer = ohci_device_isoc_transfer, 307 .upm_start = ohci_device_isoc_start, 308 .upm_abort = ohci_device_isoc_abort, 309 .upm_close = ohci_device_isoc_close, 310 .upm_cleartoggle = ohci_noop, 311 .upm_done = ohci_device_isoc_done, 312 }; 313 314 int 315 ohci_activate(device_t self, enum devact act) 316 { 317 struct ohci_softc *sc = device_private(self); 318 319 switch (act) { 320 case DVACT_DEACTIVATE: 321 sc->sc_dying = 1; 322 return 0; 323 default: 324 return EOPNOTSUPP; 325 } 326 } 327 328 void 329 ohci_childdet(device_t self, device_t child) 330 { 331 struct ohci_softc *sc = device_private(self); 332 333 KASSERT(sc->sc_child == child); 334 sc->sc_child = NULL; 335 } 336 337 int 338 ohci_detach(struct ohci_softc *sc, int flags) 339 { 340 int rv = 0; 341 342 if (sc->sc_child != NULL) 343 rv = config_detach(sc->sc_child, flags); 344 345 if (rv != 0) 346 return (rv); 347 348 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 349 350 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 351 callout_destroy(&sc->sc_tmo_rhsc); 352 353 softint_disestablish(sc->sc_rhsc_si); 354 355 cv_destroy(&sc->sc_softwake_cv); 356 357 mutex_destroy(&sc->sc_lock); 358 mutex_destroy(&sc->sc_intr_lock); 359 360 if (sc->sc_hcca != NULL) 361 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 362 pool_cache_destroy(sc->sc_xferpool); 363 364 return (rv); 365 } 366 367 ohci_soft_ed_t * 368 ohci_alloc_sed(ohci_softc_t *sc) 369 { 370 ohci_soft_ed_t *sed; 371 usbd_status err; 372 int i, offs; 373 usb_dma_t dma; 374 375 if (sc->sc_freeeds == NULL) { 376 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 377 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 378 OHCI_ED_ALIGN, &dma); 379 if (err) 380 return (0); 381 for (i = 0; i < OHCI_SED_CHUNK; i++) { 382 offs = i * OHCI_SED_SIZE; 383 sed = KERNADDR(&dma, offs); 384 sed->physaddr = DMAADDR(&dma, offs); 385 sed->dma = dma; 386 sed->offs = offs; 387 sed->next = sc->sc_freeeds; 388 sc->sc_freeeds = sed; 389 } 390 } 391 sed = sc->sc_freeeds; 392 sc->sc_freeeds = sed->next; 393 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 394 sed->next = 0; 395 return (sed); 396 } 397 398 void 399 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 400 { 401 sed->next = sc->sc_freeeds; 402 sc->sc_freeeds = sed; 403 } 404 405 ohci_soft_td_t * 406 ohci_alloc_std(ohci_softc_t *sc) 407 { 408 ohci_soft_td_t *std; 409 usbd_status err; 410 int i, offs; 411 usb_dma_t dma; 412 413 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 414 415 if (sc->sc_freetds == NULL) { 416 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 417 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 418 OHCI_TD_ALIGN, &dma); 419 if (err) 420 return (NULL); 421 for(i = 0; i < OHCI_STD_CHUNK; i++) { 422 offs = i * OHCI_STD_SIZE; 423 std = KERNADDR(&dma, offs); 424 std->physaddr = DMAADDR(&dma, offs); 425 std->dma = dma; 426 std->offs = offs; 427 std->nexttd = sc->sc_freetds; 428 sc->sc_freetds = std; 429 } 430 } 431 432 std = sc->sc_freetds; 433 sc->sc_freetds = std->nexttd; 434 memset(&std->td, 0, sizeof(ohci_td_t)); 435 std->nexttd = NULL; 436 std->xfer = NULL; 437 ohci_hash_add_td(sc, std); 438 439 return (std); 440 } 441 442 void 443 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 444 { 445 446 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 447 448 ohci_hash_rem_td(sc, std); 449 std->nexttd = sc->sc_freetds; 450 sc->sc_freetds = std; 451 } 452 453 usbd_status 454 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 455 int alen, int rd, usbd_xfer_handle xfer, 456 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 457 { 458 ohci_soft_td_t *next, *cur; 459 ohci_physaddr_t dataphys, dataphysend; 460 uint32_t tdflags; 461 int len, curlen; 462 usb_dma_t *dma = &xfer->ux_dmabuf; 463 uint16_t flags = xfer->ux_flags; 464 465 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 466 467 KASSERT(mutex_owned(&sc->sc_lock)); 468 469 len = alen; 470 cur = sp; 471 dataphys = DMAADDR(dma, 0); 472 dataphysend = OHCI_PAGE(dataphys + len - 1); 473 usb_syncmem(dma, 0, len, 474 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 475 tdflags = HTOO32( 476 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 477 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 478 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 479 480 for (;;) { 481 next = ohci_alloc_std(sc); 482 if (next == NULL) 483 goto nomem; 484 485 /* The OHCI hardware can handle at most one page crossing. */ 486 if (OHCI_PAGE(dataphys) == dataphysend || 487 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 488 /* we can handle it in this TD */ 489 curlen = len; 490 } else { 491 /* must use multiple TDs, fill as much as possible. */ 492 curlen = 2 * OHCI_PAGE_SIZE - 493 (dataphys & (OHCI_PAGE_SIZE-1)); 494 /* the length must be a multiple of the max size */ 495 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 496 #ifdef DIAGNOSTIC 497 if (curlen == 0) 498 panic("ohci_alloc_std: curlen == 0"); 499 #endif 500 } 501 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 502 "dataphysend=0x%08x len=%d curlen=%d\n", 503 dataphys, dataphysend, 504 len, curlen)); 505 len -= curlen; 506 507 cur->td.td_flags = tdflags; 508 cur->td.td_cbp = HTOO32(dataphys); 509 cur->nexttd = next; 510 cur->td.td_nexttd = HTOO32(next->physaddr); 511 cur->td.td_be = HTOO32(dataphys + curlen - 1); 512 cur->len = curlen; 513 cur->flags = OHCI_ADD_LEN; 514 cur->xfer = xfer; 515 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 517 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 518 dataphys, dataphys + curlen - 1)); 519 if (len == 0) 520 break; 521 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 522 dataphys += curlen; 523 cur = next; 524 } 525 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 526 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 527 /* Force a 0 length transfer at the end. */ 528 529 cur = next; 530 next = ohci_alloc_std(sc); 531 if (next == NULL) 532 goto nomem; 533 534 cur->td.td_flags = tdflags; 535 cur->td.td_cbp = 0; /* indicate 0 length packet */ 536 cur->nexttd = next; 537 cur->td.td_nexttd = HTOO32(next->physaddr); 538 cur->td.td_be = ~0; 539 cur->len = 0; 540 cur->flags = 0; 541 cur->xfer = xfer; 542 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 544 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 545 } 546 *ep = cur; 547 548 return (USBD_NORMAL_COMPLETION); 549 550 nomem: 551 552 /* Don't free sp - let the caller do that */ 553 ohci_free_std_chain(sc, sp->nexttd, NULL); 554 555 return (USBD_NOMEM); 556 } 557 558 Static void 559 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 560 ohci_soft_td_t *stdend) 561 { 562 ohci_soft_td_t *p; 563 564 for (; std != stdend; std = p) { 565 p = std->nexttd; 566 ohci_free_std(sc, std); 567 } 568 } 569 570 ohci_soft_itd_t * 571 ohci_alloc_sitd(ohci_softc_t *sc) 572 { 573 ohci_soft_itd_t *sitd; 574 usbd_status err; 575 int i, offs; 576 usb_dma_t dma; 577 578 if (sc->sc_freeitds == NULL) { 579 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 580 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 581 OHCI_ITD_ALIGN, &dma); 582 if (err) 583 return (NULL); 584 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 585 offs = i * OHCI_SITD_SIZE; 586 sitd = KERNADDR(&dma, offs); 587 sitd->physaddr = DMAADDR(&dma, offs); 588 sitd->dma = dma; 589 sitd->offs = offs; 590 sitd->nextitd = sc->sc_freeitds; 591 sc->sc_freeitds = sitd; 592 } 593 } 594 595 sitd = sc->sc_freeitds; 596 sc->sc_freeitds = sitd->nextitd; 597 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 598 sitd->nextitd = NULL; 599 sitd->xfer = NULL; 600 ohci_hash_add_itd(sc, sitd); 601 602 #ifdef DIAGNOSTIC 603 sitd->isdone = 0; 604 #endif 605 606 return (sitd); 607 } 608 609 void 610 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 611 { 612 613 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 614 615 #ifdef DIAGNOSTIC 616 if (!sitd->isdone) { 617 panic("ohci_free_sitd: sitd=%p not done", sitd); 618 return; 619 } 620 /* Warn double free */ 621 sitd->isdone = 0; 622 #endif 623 624 ohci_hash_rem_itd(sc, sitd); 625 sitd->nextitd = sc->sc_freeitds; 626 sc->sc_freeitds = sitd; 627 } 628 629 usbd_status 630 ohci_init(ohci_softc_t *sc) 631 { 632 ohci_soft_ed_t *sed, *psed; 633 usbd_status err; 634 int i; 635 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 636 637 DPRINTF(("ohci_init: start\n")); 638 aprint_normal_dev(sc->sc_dev, ""); 639 640 sc->sc_hcca = NULL; 641 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 642 643 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 644 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 645 cv_init(&sc->sc_softwake_cv, "ohciab"); 646 647 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 648 ohci_rhsc_softint, sc); 649 650 for (i = 0; i < OHCI_HASH_SIZE; i++) 651 LIST_INIT(&sc->sc_hash_tds[i]); 652 for (i = 0; i < OHCI_HASH_SIZE; i++) 653 LIST_INIT(&sc->sc_hash_itds[i]); 654 655 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 656 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 657 658 rev = OREAD4(sc, OHCI_REVISION); 659 aprint_normal("OHCI version %d.%d%s\n", 660 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 661 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 662 663 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 664 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 665 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 666 return (USBD_INVAL); 667 } 668 sc->sc_bus.ub_revision = USBREV_1_0; 669 sc->sc_bus.ub_usedma = true; 670 671 /* XXX determine alignment by R/W */ 672 /* Allocate the HCCA area. */ 673 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 674 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 675 if (err) { 676 sc->sc_hcca = NULL; 677 return err; 678 } 679 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 680 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 681 682 sc->sc_eintrs = OHCI_NORMAL_INTRS; 683 684 /* Allocate dummy ED that starts the control list. */ 685 sc->sc_ctrl_head = ohci_alloc_sed(sc); 686 if (sc->sc_ctrl_head == NULL) { 687 err = USBD_NOMEM; 688 goto bad1; 689 } 690 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 691 692 /* Allocate dummy ED that starts the bulk list. */ 693 sc->sc_bulk_head = ohci_alloc_sed(sc); 694 if (sc->sc_bulk_head == NULL) { 695 err = USBD_NOMEM; 696 goto bad2; 697 } 698 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 699 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 700 sizeof(sc->sc_bulk_head->ed), 701 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 702 703 /* Allocate dummy ED that starts the isochronous list. */ 704 sc->sc_isoc_head = ohci_alloc_sed(sc); 705 if (sc->sc_isoc_head == NULL) { 706 err = USBD_NOMEM; 707 goto bad3; 708 } 709 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 710 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 711 sizeof(sc->sc_isoc_head->ed), 712 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 713 714 /* Allocate all the dummy EDs that make up the interrupt tree. */ 715 for (i = 0; i < OHCI_NO_EDS; i++) { 716 sed = ohci_alloc_sed(sc); 717 if (sed == NULL) { 718 while (--i >= 0) 719 ohci_free_sed(sc, sc->sc_eds[i]); 720 err = USBD_NOMEM; 721 goto bad4; 722 } 723 /* All ED fields are set to 0. */ 724 sc->sc_eds[i] = sed; 725 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 726 if (i != 0) 727 psed = sc->sc_eds[(i-1) / 2]; 728 else 729 psed= sc->sc_isoc_head; 730 sed->next = psed; 731 sed->ed.ed_nexted = HTOO32(psed->physaddr); 732 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 733 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 734 } 735 /* 736 * Fill HCCA interrupt table. The bit reversal is to get 737 * the tree set up properly to spread the interrupts. 738 */ 739 for (i = 0; i < OHCI_NO_INTRS; i++) 740 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 741 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 742 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 744 745 #ifdef OHCI_DEBUG 746 if (ohcidebug > 15) { 747 for (i = 0; i < OHCI_NO_EDS; i++) { 748 printf("ed#%d ", i); 749 ohci_dump_ed(sc, sc->sc_eds[i]); 750 } 751 printf("iso "); 752 ohci_dump_ed(sc, sc->sc_isoc_head); 753 } 754 #endif 755 756 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 757 ctl = OREAD4(sc, OHCI_CONTROL); 758 rwc = ctl & OHCI_RWC; 759 fm = OREAD4(sc, OHCI_FM_INTERVAL); 760 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 761 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 762 763 /* Determine in what context we are running. */ 764 if (ctl & OHCI_IR) { 765 /* SMM active, request change */ 766 DPRINTF(("ohci_init: SMM active, request owner change\n")); 767 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 768 (OHCI_OC | OHCI_MIE)) 769 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 770 s = OREAD4(sc, OHCI_COMMAND_STATUS); 771 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 772 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 773 usb_delay_ms(&sc->sc_bus, 1); 774 ctl = OREAD4(sc, OHCI_CONTROL); 775 } 776 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 777 if ((ctl & OHCI_IR) == 0) { 778 aprint_error_dev(sc->sc_dev, 779 "SMM does not respond, resetting\n"); 780 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 781 goto reset; 782 } 783 #if 0 784 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 785 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 786 /* BIOS started controller. */ 787 DPRINTF(("ohci_init: BIOS active\n")); 788 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 789 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 790 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 791 } 792 #endif 793 } else { 794 DPRINTF(("ohci_init: cold started\n")); 795 reset: 796 /* Controller was cold started. */ 797 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 798 } 799 800 /* 801 * This reset should not be necessary according to the OHCI spec, but 802 * without it some controllers do not start. 803 */ 804 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 805 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 806 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 807 808 /* We now own the host controller and the bus has been reset. */ 809 810 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 811 /* Nominal time for a reset is 10 us. */ 812 for (i = 0; i < 10; i++) { 813 delay(10); 814 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 815 if (!hcr) 816 break; 817 } 818 if (hcr) { 819 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 820 err = USBD_IOERROR; 821 goto bad5; 822 } 823 #ifdef OHCI_DEBUG 824 if (ohcidebug > 15) 825 ohci_dumpregs(sc); 826 #endif 827 828 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 829 830 /* Set up HC registers. */ 831 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 832 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 833 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 834 /* disable all interrupts and then switch on all desired interrupts */ 835 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 836 /* switch on desired functional features */ 837 ctl = OREAD4(sc, OHCI_CONTROL); 838 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 839 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 840 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 841 /* And finally start it! */ 842 OWRITE4(sc, OHCI_CONTROL, ctl); 843 844 /* 845 * The controller is now OPERATIONAL. Set a some final 846 * registers that should be set earlier, but that the 847 * controller ignores when in the SUSPEND state. 848 */ 849 ival = OHCI_GET_IVAL(fm); 850 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 851 fm |= OHCI_FSMPS(ival) | ival; 852 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 853 per = OHCI_PERIODIC(ival); /* 90% periodic */ 854 OWRITE4(sc, OHCI_PERIODIC_START, per); 855 856 if (sc->sc_flags & OHCIF_SUPERIO) { 857 /* no overcurrent protection */ 858 desca |= OHCI_NOCP; 859 /* 860 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 861 * that 862 * - ports are always power switched 863 * - don't wait for powered root hub port 864 */ 865 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 866 } 867 868 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 869 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 870 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 871 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 872 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 873 874 /* 875 * The AMD756 requires a delay before re-reading the register, 876 * otherwise it will occasionally report 0 ports. 877 */ 878 sc->sc_noport = 0; 879 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 880 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 881 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 882 } 883 884 #ifdef OHCI_DEBUG 885 if (ohcidebug > 5) 886 ohci_dumpregs(sc); 887 #endif 888 889 /* Set up the bus struct. */ 890 sc->sc_bus.ub_methods = &ohci_bus_methods; 891 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 892 893 sc->sc_control = sc->sc_intre = 0; 894 895 /* Finally, turn on interrupts. */ 896 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 897 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 898 899 return (USBD_NORMAL_COMPLETION); 900 901 bad5: 902 for (i = 0; i < OHCI_NO_EDS; i++) 903 ohci_free_sed(sc, sc->sc_eds[i]); 904 bad4: 905 ohci_free_sed(sc, sc->sc_isoc_head); 906 bad3: 907 ohci_free_sed(sc, sc->sc_bulk_head); 908 bad2: 909 ohci_free_sed(sc, sc->sc_ctrl_head); 910 bad1: 911 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 912 sc->sc_hcca = NULL; 913 return (err); 914 } 915 916 usbd_xfer_handle 917 ohci_allocx(struct usbd_bus *bus) 918 { 919 struct ohci_softc *sc = bus->ub_hcpriv; 920 usbd_xfer_handle xfer; 921 922 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 923 if (xfer != NULL) { 924 memset(xfer, 0, sizeof(struct ohci_xfer)); 925 #ifdef DIAGNOSTIC 926 xfer->ux_state = XFER_BUSY; 927 #endif 928 } 929 return (xfer); 930 } 931 932 void 933 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 934 { 935 struct ohci_softc *sc = bus->ub_hcpriv; 936 937 #ifdef DIAGNOSTIC 938 if (xfer->ux_state != XFER_BUSY) { 939 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 940 xfer->ux_state); 941 } 942 xfer->ux_state = XFER_FREE; 943 #endif 944 pool_cache_put(sc->sc_xferpool, xfer); 945 } 946 947 Static void 948 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 949 { 950 struct ohci_softc *sc = bus->ub_hcpriv; 951 952 *lock = &sc->sc_lock; 953 } 954 955 /* 956 * Shut down the controller when the system is going down. 957 */ 958 bool 959 ohci_shutdown(device_t self, int flags) 960 { 961 ohci_softc_t *sc = device_private(self); 962 963 DPRINTF(("ohci_shutdown: stopping the HC\n")); 964 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 965 return true; 966 } 967 968 bool 969 ohci_resume(device_t dv, const pmf_qual_t *qual) 970 { 971 ohci_softc_t *sc = device_private(dv); 972 uint32_t ctl; 973 974 mutex_spin_enter(&sc->sc_intr_lock); 975 sc->sc_bus.ub_usepolling++; 976 mutex_spin_exit(&sc->sc_intr_lock); 977 978 /* Some broken BIOSes do not recover these values */ 979 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 980 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 981 sc->sc_ctrl_head->physaddr); 982 OWRITE4(sc, OHCI_BULK_HEAD_ED, 983 sc->sc_bulk_head->physaddr); 984 if (sc->sc_intre) 985 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 986 (OHCI_ALL_INTRS | OHCI_MIE)); 987 if (sc->sc_control) 988 ctl = sc->sc_control; 989 else 990 ctl = OREAD4(sc, OHCI_CONTROL); 991 ctl |= OHCI_HCFS_RESUME; 992 OWRITE4(sc, OHCI_CONTROL, ctl); 993 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 994 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 995 OWRITE4(sc, OHCI_CONTROL, ctl); 996 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 997 sc->sc_control = sc->sc_intre = 0; 998 999 mutex_spin_enter(&sc->sc_intr_lock); 1000 sc->sc_bus.ub_usepolling--; 1001 mutex_spin_exit(&sc->sc_intr_lock); 1002 1003 return true; 1004 } 1005 1006 bool 1007 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1008 { 1009 ohci_softc_t *sc = device_private(dv); 1010 uint32_t ctl; 1011 1012 mutex_spin_enter(&sc->sc_intr_lock); 1013 sc->sc_bus.ub_usepolling++; 1014 mutex_spin_exit(&sc->sc_intr_lock); 1015 1016 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1017 if (sc->sc_control == 0) { 1018 /* 1019 * Preserve register values, in case that BIOS 1020 * does not recover them. 1021 */ 1022 sc->sc_control = ctl; 1023 sc->sc_intre = OREAD4(sc, 1024 OHCI_INTERRUPT_ENABLE); 1025 } 1026 ctl |= OHCI_HCFS_SUSPEND; 1027 OWRITE4(sc, OHCI_CONTROL, ctl); 1028 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1029 1030 mutex_spin_enter(&sc->sc_intr_lock); 1031 sc->sc_bus.ub_usepolling--; 1032 mutex_spin_exit(&sc->sc_intr_lock); 1033 1034 return true; 1035 } 1036 1037 #ifdef OHCI_DEBUG 1038 void 1039 ohci_dumpregs(ohci_softc_t *sc) 1040 { 1041 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1042 OREAD4(sc, OHCI_REVISION), 1043 OREAD4(sc, OHCI_CONTROL), 1044 OREAD4(sc, OHCI_COMMAND_STATUS))); 1045 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1046 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1047 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1048 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1049 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1050 OREAD4(sc, OHCI_HCCA), 1051 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1052 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1053 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1054 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1055 OREAD4(sc, OHCI_BULK_HEAD_ED), 1056 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1057 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1058 OREAD4(sc, OHCI_DONE_HEAD), 1059 OREAD4(sc, OHCI_FM_INTERVAL), 1060 OREAD4(sc, OHCI_FM_REMAINING))); 1061 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1062 OREAD4(sc, OHCI_FM_NUMBER), 1063 OREAD4(sc, OHCI_PERIODIC_START), 1064 OREAD4(sc, OHCI_LS_THRESHOLD))); 1065 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1066 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1067 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1068 OREAD4(sc, OHCI_RH_STATUS))); 1069 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1070 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1071 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1072 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1073 O32TOH(sc->sc_hcca->hcca_frame_number), 1074 O32TOH(sc->sc_hcca->hcca_done_head))); 1075 } 1076 #endif 1077 1078 Static int ohci_intr1(ohci_softc_t *); 1079 1080 int 1081 ohci_intr(void *p) 1082 { 1083 ohci_softc_t *sc = p; 1084 int ret = 0; 1085 1086 if (sc == NULL) 1087 return (0); 1088 1089 mutex_spin_enter(&sc->sc_intr_lock); 1090 1091 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1092 goto done; 1093 1094 /* If we get an interrupt while polling, then just ignore it. */ 1095 if (sc->sc_bus.ub_usepolling) { 1096 #ifdef DIAGNOSTIC 1097 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1098 #endif 1099 /* for level triggered intrs, should do something to ack */ 1100 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1101 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1102 1103 goto done; 1104 } 1105 1106 ret = ohci_intr1(sc); 1107 1108 done: 1109 mutex_spin_exit(&sc->sc_intr_lock); 1110 return ret; 1111 } 1112 1113 Static int 1114 ohci_intr1(ohci_softc_t *sc) 1115 { 1116 uint32_t intrs, eintrs; 1117 1118 DPRINTFN(14,("ohci_intr1: enter\n")); 1119 1120 /* In case the interrupt occurs before initialization has completed. */ 1121 if (sc == NULL || sc->sc_hcca == NULL) { 1122 #ifdef DIAGNOSTIC 1123 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1124 #endif 1125 return (0); 1126 } 1127 1128 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1129 1130 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1131 if (!intrs) 1132 return (0); 1133 1134 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1135 eintrs = intrs & sc->sc_eintrs; 1136 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1137 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1138 (u_int)eintrs, sc->sc_eintrs)); 1139 1140 if (!eintrs) { 1141 return (0); 1142 } 1143 1144 if (eintrs & OHCI_SO) { 1145 sc->sc_overrun_cnt++; 1146 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1147 printf("%s: %u scheduling overruns\n", 1148 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1149 sc->sc_overrun_cnt = 0; 1150 } 1151 /* XXX do what */ 1152 eintrs &= ~OHCI_SO; 1153 } 1154 if (eintrs & OHCI_WDH) { 1155 /* 1156 * We block the interrupt below, and reenable it later from 1157 * ohci_softintr(). 1158 */ 1159 usb_schedsoftintr(&sc->sc_bus); 1160 } 1161 if (eintrs & OHCI_RD) { 1162 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1163 /* XXX process resume detect */ 1164 } 1165 if (eintrs & OHCI_UE) { 1166 printf("%s: unrecoverable error, controller halted\n", 1167 device_xname(sc->sc_dev)); 1168 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1169 /* XXX what else */ 1170 } 1171 if (eintrs & OHCI_RHSC) { 1172 /* 1173 * We block the interrupt below, and reenable it later from 1174 * a timeout. 1175 */ 1176 softint_schedule(sc->sc_rhsc_si); 1177 } 1178 1179 if (eintrs != 0) { 1180 /* Block unprocessed interrupts. */ 1181 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1182 sc->sc_eintrs &= ~eintrs; 1183 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1184 device_xname(sc->sc_dev), eintrs)); 1185 } 1186 1187 return (1); 1188 } 1189 1190 void 1191 ohci_rhsc_enable(void *v_sc) 1192 { 1193 ohci_softc_t *sc = v_sc; 1194 1195 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1196 mutex_spin_enter(&sc->sc_intr_lock); 1197 sc->sc_eintrs |= OHCI_RHSC; 1198 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1199 mutex_spin_exit(&sc->sc_intr_lock); 1200 } 1201 1202 #ifdef OHCI_DEBUG 1203 const char *ohci_cc_strs[] = { 1204 "NO_ERROR", 1205 "CRC", 1206 "BIT_STUFFING", 1207 "DATA_TOGGLE_MISMATCH", 1208 "STALL", 1209 "DEVICE_NOT_RESPONDING", 1210 "PID_CHECK_FAILURE", 1211 "UNEXPECTED_PID", 1212 "DATA_OVERRUN", 1213 "DATA_UNDERRUN", 1214 "BUFFER_OVERRUN", 1215 "BUFFER_UNDERRUN", 1216 "reserved", 1217 "reserved", 1218 "NOT_ACCESSED", 1219 "NOT_ACCESSED", 1220 }; 1221 #endif 1222 1223 void 1224 ohci_softintr(void *v) 1225 { 1226 struct usbd_bus *bus = v; 1227 ohci_softc_t *sc = bus->ub_hcpriv; 1228 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1229 ohci_soft_td_t *std, *sdone, *stdnext; 1230 usbd_xfer_handle xfer; 1231 struct ohci_pipe *opipe; 1232 int len, cc; 1233 int i, j, actlen, iframes, uedir; 1234 ohci_physaddr_t done; 1235 1236 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1237 1238 DPRINTFN(10,("ohci_softintr: enter\n")); 1239 1240 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1241 sizeof(sc->sc_hcca->hcca_done_head), 1242 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1243 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1244 sc->sc_hcca->hcca_done_head = 0; 1245 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1246 sizeof(sc->sc_hcca->hcca_done_head), 1247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1248 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1249 sc->sc_eintrs |= OHCI_WDH; 1250 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1251 1252 /* Reverse the done list. */ 1253 for (sdone = NULL, sidone = NULL; done != 0; ) { 1254 std = ohci_hash_find_td(sc, done); 1255 if (std != NULL) { 1256 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1257 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1258 std->dnext = sdone; 1259 done = O32TOH(std->td.td_nexttd); 1260 sdone = std; 1261 DPRINTFN(10,("add TD %p\n", std)); 1262 continue; 1263 } 1264 sitd = ohci_hash_find_itd(sc, done); 1265 if (sitd != NULL) { 1266 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1267 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1268 sitd->dnext = sidone; 1269 done = O32TOH(sitd->itd.itd_nextitd); 1270 sidone = sitd; 1271 DPRINTFN(5,("add ITD %p\n", sitd)); 1272 continue; 1273 } 1274 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1275 (u_long)done); 1276 break; 1277 } 1278 1279 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1280 1281 #ifdef OHCI_DEBUG 1282 if (ohcidebug > 10) { 1283 DPRINTF(("ohci_process_done: TD done:\n")); 1284 for (std = sdone; std; std = std->dnext) 1285 ohci_dump_td(sc, std); 1286 } 1287 #endif 1288 1289 for (std = sdone; std; std = stdnext) { 1290 xfer = std->xfer; 1291 stdnext = std->dnext; 1292 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1293 std, xfer, xfer ? xfer->ux_hcpriv : 0)); 1294 if (xfer == NULL) { 1295 /* 1296 * xfer == NULL: There seems to be no xfer associated 1297 * with this TD. It is tailp that happened to end up on 1298 * the done queue. 1299 * Shouldn't happen, but some chips are broken(?). 1300 */ 1301 continue; 1302 } 1303 if (xfer->ux_status == USBD_CANCELLED || 1304 xfer->ux_status == USBD_TIMEOUT) { 1305 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1306 xfer)); 1307 /* Handled by abort routine. */ 1308 continue; 1309 } 1310 callout_stop(&xfer->ux_callout); 1311 1312 len = std->len; 1313 if (std->td.td_cbp != 0) 1314 len -= O32TOH(std->td.td_be) - 1315 O32TOH(std->td.td_cbp) + 1; 1316 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1317 std->flags)); 1318 if (std->flags & OHCI_ADD_LEN) 1319 xfer->ux_actlen += len; 1320 1321 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1322 if (cc == OHCI_CC_NO_ERROR) { 1323 if (std->flags & OHCI_CALL_DONE) { 1324 xfer->ux_status = USBD_NORMAL_COMPLETION; 1325 usb_transfer_complete(xfer); 1326 } 1327 ohci_free_std(sc, std); 1328 } else { 1329 /* 1330 * Endpoint is halted. First unlink all the TDs 1331 * belonging to the failed transfer, and then restart 1332 * the endpoint. 1333 */ 1334 ohci_soft_td_t *p, *n; 1335 opipe = (struct ohci_pipe *)xfer->ux_pipe; 1336 1337 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1338 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1339 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1340 1341 /* remove TDs */ 1342 for (p = std; p->xfer == xfer; p = n) { 1343 n = p->nexttd; 1344 ohci_free_std(sc, p); 1345 } 1346 1347 /* clear halt */ 1348 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1349 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1350 1351 if (cc == OHCI_CC_STALL) 1352 xfer->ux_status = USBD_STALLED; 1353 else 1354 xfer->ux_status = USBD_IOERROR; 1355 usb_transfer_complete(xfer); 1356 } 1357 } 1358 1359 #ifdef OHCI_DEBUG 1360 if (ohcidebug > 10) { 1361 DPRINTF(("ohci_softintr: ITD done:\n")); 1362 for (sitd = sidone; sitd; sitd = sitd->dnext) 1363 ohci_dump_itd(sc, sitd); 1364 } 1365 #endif 1366 1367 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1368 xfer = sitd->xfer; 1369 sitdnext = sitd->dnext; 1370 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1371 sitd, xfer, xfer ? xfer->ux_hcpriv : 0)); 1372 if (xfer == NULL) 1373 continue; 1374 if (xfer->ux_status == USBD_CANCELLED || 1375 xfer->ux_status == USBD_TIMEOUT) { 1376 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1377 xfer)); 1378 /* Handled by abort routine. */ 1379 continue; 1380 } 1381 #ifdef DIAGNOSTIC 1382 if (sitd->isdone) 1383 printf("ohci_softintr: sitd=%p is done\n", sitd); 1384 sitd->isdone = 1; 1385 #endif 1386 if (sitd->flags & OHCI_CALL_DONE) { 1387 ohci_soft_itd_t *next; 1388 1389 opipe = (struct ohci_pipe *)xfer->ux_pipe; 1390 opipe->u.iso.inuse -= xfer->ux_nframes; 1391 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1392 bEndpointAddress); 1393 xfer->ux_status = USBD_NORMAL_COMPLETION; 1394 actlen = 0; 1395 for (i = 0, sitd = xfer->ux_hcpriv;; 1396 sitd = next) { 1397 next = sitd->nextitd; 1398 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1399 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1400 xfer->ux_status = USBD_IOERROR; 1401 /* For input, update frlengths with actual */ 1402 /* XXX anything necessary for output? */ 1403 if (uedir == UE_DIR_IN && 1404 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1405 iframes = OHCI_ITD_GET_FC(O32TOH( 1406 sitd->itd.itd_flags)); 1407 for (j = 0; j < iframes; i++, j++) { 1408 len = O16TOH(sitd-> 1409 itd.itd_offset[j]); 1410 if ((OHCI_ITD_PSW_GET_CC(len) & 1411 OHCI_CC_NOT_ACCESSED_MASK) 1412 == OHCI_CC_NOT_ACCESSED) 1413 len = 0; 1414 else 1415 len = OHCI_ITD_PSW_LENGTH(len); 1416 xfer->ux_frlengths[i] = len; 1417 actlen += len; 1418 } 1419 } 1420 if (sitd->flags & OHCI_CALL_DONE) 1421 break; 1422 ohci_free_sitd(sc, sitd); 1423 } 1424 ohci_free_sitd(sc, sitd); 1425 if (uedir == UE_DIR_IN && 1426 xfer->ux_status == USBD_NORMAL_COMPLETION) 1427 xfer->ux_actlen = actlen; 1428 xfer->ux_hcpriv = NULL; 1429 1430 usb_transfer_complete(xfer); 1431 } 1432 } 1433 1434 if (sc->sc_softwake) { 1435 sc->sc_softwake = 0; 1436 cv_broadcast(&sc->sc_softwake_cv); 1437 } 1438 1439 DPRINTFN(10,("ohci_softintr: done:\n")); 1440 } 1441 1442 void 1443 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1444 { 1445 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1446 #ifdef DIAGNOSTIC 1447 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1448 #endif 1449 int len = UGETW(xfer->ux_request.wLength); 1450 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1451 1452 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1453 1454 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1455 1456 #ifdef DIAGNOSTIC 1457 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 1458 panic("ohci_device_ctrl_done: not a request"); 1459 } 1460 #endif 1461 if (len) 1462 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1463 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1464 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1465 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1466 } 1467 1468 void 1469 ohci_device_intr_done(usbd_xfer_handle xfer) 1470 { 1471 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1472 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 1473 ohci_soft_ed_t *sed = opipe->sed; 1474 ohci_soft_td_t *data, *tail; 1475 int isread = 1476 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1477 1478 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1479 xfer, xfer->ux_actlen)); 1480 1481 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1482 1483 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1484 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1485 if (xfer->ux_pipe->up_repeat) { 1486 data = opipe->tail.td; 1487 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1488 if (tail == NULL) { 1489 xfer->ux_status = USBD_NOMEM; 1490 return; 1491 } 1492 tail->xfer = NULL; 1493 1494 data->td.td_flags = HTOO32( 1495 OHCI_TD_IN | OHCI_TD_NOCC | 1496 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1497 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1498 data->td.td_flags |= HTOO32(OHCI_TD_R); 1499 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1500 data->nexttd = tail; 1501 data->td.td_nexttd = HTOO32(tail->physaddr); 1502 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1503 xfer->ux_length - 1); 1504 data->len = xfer->ux_length; 1505 data->xfer = xfer; 1506 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1507 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1508 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1509 xfer->ux_hcpriv = data; 1510 xfer->ux_actlen = 0; 1511 1512 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1513 usb_syncmem(&sed->dma, 1514 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1515 sizeof(sed->ed.ed_tailp), 1516 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1517 opipe->tail.td = tail; 1518 } 1519 } 1520 1521 void 1522 ohci_device_bulk_done(usbd_xfer_handle xfer) 1523 { 1524 #ifdef DIAGNOSTIC 1525 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1526 #endif 1527 int isread = 1528 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1529 1530 KASSERT(mutex_owned(&sc->sc_lock)); 1531 1532 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1533 xfer, xfer->ux_actlen)); 1534 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1535 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1536 } 1537 1538 Static void 1539 ohci_rhsc_softint(void *arg) 1540 { 1541 ohci_softc_t *sc = arg; 1542 1543 mutex_enter(&sc->sc_lock); 1544 1545 ohci_rhsc(sc, sc->sc_intrxfer); 1546 1547 /* Do not allow RHSC interrupts > 1 per second */ 1548 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1549 1550 mutex_exit(&sc->sc_lock); 1551 } 1552 1553 void 1554 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1555 { 1556 u_char *p; 1557 int i, m; 1558 int hstatus __unused; 1559 1560 KASSERT(mutex_owned(&sc->sc_lock)); 1561 1562 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1563 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1564 sc, xfer, hstatus)); 1565 1566 if (xfer == NULL) { 1567 /* Just ignore the change. */ 1568 return; 1569 } 1570 1571 p = xfer->ux_buf; 1572 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1573 memset(p, 0, xfer->ux_length); 1574 for (i = 1; i <= m; i++) { 1575 /* Pick out CHANGE bits from the status reg. */ 1576 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1577 p[i/8] |= 1 << (i%8); 1578 } 1579 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1580 xfer->ux_actlen = xfer->ux_length; 1581 xfer->ux_status = USBD_NORMAL_COMPLETION; 1582 1583 usb_transfer_complete(xfer); 1584 } 1585 1586 void 1587 ohci_root_intr_done(usbd_xfer_handle xfer) 1588 { 1589 } 1590 1591 void 1592 ohci_root_ctrl_done(usbd_xfer_handle xfer) 1593 { 1594 } 1595 1596 /* 1597 * Wait here until controller claims to have an interrupt. 1598 * Then call ohci_intr and return. Use timeout to avoid waiting 1599 * too long. 1600 */ 1601 void 1602 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1603 { 1604 int timo; 1605 uint32_t intrs; 1606 1607 mutex_enter(&sc->sc_lock); 1608 1609 xfer->ux_status = USBD_IN_PROGRESS; 1610 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1611 usb_delay_ms(&sc->sc_bus, 1); 1612 if (sc->sc_dying) 1613 break; 1614 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1615 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1616 #ifdef OHCI_DEBUG 1617 if (ohcidebug > 15) 1618 ohci_dumpregs(sc); 1619 #endif 1620 if (intrs) { 1621 mutex_spin_enter(&sc->sc_intr_lock); 1622 ohci_intr1(sc); 1623 mutex_spin_exit(&sc->sc_intr_lock); 1624 if (xfer->ux_status != USBD_IN_PROGRESS) 1625 goto done; 1626 } 1627 } 1628 1629 /* Timeout */ 1630 DPRINTF(("ohci_waitintr: timeout\n")); 1631 xfer->ux_status = USBD_TIMEOUT; 1632 usb_transfer_complete(xfer); 1633 1634 /* XXX should free TD */ 1635 1636 done: 1637 mutex_exit(&sc->sc_lock); 1638 } 1639 1640 void 1641 ohci_poll(struct usbd_bus *bus) 1642 { 1643 ohci_softc_t *sc = bus->ub_hcpriv; 1644 #ifdef OHCI_DEBUG 1645 static int last; 1646 int new; 1647 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1648 if (new != last) { 1649 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1650 last = new; 1651 } 1652 #endif 1653 sc->sc_eintrs |= OHCI_WDH; 1654 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1655 mutex_spin_enter(&sc->sc_intr_lock); 1656 ohci_intr1(sc); 1657 mutex_spin_exit(&sc->sc_intr_lock); 1658 } 1659 } 1660 1661 usbd_status 1662 ohci_device_request(usbd_xfer_handle xfer) 1663 { 1664 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1665 usb_device_request_t *req = &xfer->ux_request; 1666 usbd_device_handle dev = opipe->pipe.up_dev; 1667 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1668 ohci_soft_td_t *setup, *stat, *next, *tail; 1669 ohci_soft_ed_t *sed; 1670 int isread; 1671 int len; 1672 usbd_status err; 1673 1674 KASSERT(mutex_owned(&sc->sc_lock)); 1675 1676 isread = req->bmRequestType & UT_READ; 1677 len = UGETW(req->wLength); 1678 1679 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1680 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1681 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1682 UGETW(req->wIndex), len, dev->ud_addr, 1683 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)); 1684 1685 setup = opipe->tail.td; 1686 stat = ohci_alloc_std(sc); 1687 if (stat == NULL) { 1688 err = USBD_NOMEM; 1689 goto bad1; 1690 } 1691 tail = ohci_alloc_std(sc); 1692 if (tail == NULL) { 1693 err = USBD_NOMEM; 1694 goto bad2; 1695 } 1696 tail->xfer = NULL; 1697 1698 sed = opipe->sed; 1699 opipe->u.ctl.length = len; 1700 1701 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 1702 "address ED %d pipe %d\n", 1703 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 1704 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 1705 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 1706 "MPL ED %d pipe %d\n", 1707 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 1708 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 1709 1710 next = stat; 1711 1712 /* Set up data transaction */ 1713 if (len != 0) { 1714 ohci_soft_td_t *std = stat; 1715 1716 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1717 std, &stat); 1718 if (err) { 1719 /* stat is unchanged if error */ 1720 goto bad3; 1721 } 1722 stat = stat->nexttd; /* point at free TD */ 1723 1724 /* Start toggle at 1 and then use the carried toggle. */ 1725 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1726 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1727 usb_syncmem(&std->dma, 1728 std->offs + offsetof(ohci_td_t, td_flags), 1729 sizeof(std->td.td_flags), 1730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1731 } 1732 1733 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1734 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1735 1736 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1737 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1738 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1739 setup->nexttd = next; 1740 setup->td.td_nexttd = HTOO32(next->physaddr); 1741 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1742 setup->len = 0; 1743 setup->xfer = xfer; 1744 setup->flags = 0; 1745 xfer->ux_hcpriv = setup; 1746 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1747 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1748 1749 stat->td.td_flags = HTOO32( 1750 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1751 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1752 stat->td.td_cbp = 0; 1753 stat->nexttd = tail; 1754 stat->td.td_nexttd = HTOO32(tail->physaddr); 1755 stat->td.td_be = 0; 1756 stat->flags = OHCI_CALL_DONE; 1757 stat->len = 0; 1758 stat->xfer = xfer; 1759 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1761 1762 #ifdef OHCI_DEBUG 1763 if (ohcidebug > 5) { 1764 DPRINTF(("ohci_device_request:\n")); 1765 ohci_dump_ed(sc, sed); 1766 ohci_dump_tds(sc, setup); 1767 } 1768 #endif 1769 1770 /* Insert ED in schedule */ 1771 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1772 usb_syncmem(&sed->dma, 1773 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1774 sizeof(sed->ed.ed_tailp), 1775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1776 opipe->tail.td = tail; 1777 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1778 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 1779 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 1780 ohci_timeout, xfer); 1781 } 1782 1783 #ifdef OHCI_DEBUG 1784 if (ohcidebug > 20) { 1785 delay(10000); 1786 DPRINTF(("ohci_device_request: status=%x\n", 1787 OREAD4(sc, OHCI_COMMAND_STATUS))); 1788 ohci_dumpregs(sc); 1789 printf("ctrl head:\n"); 1790 ohci_dump_ed(sc, sc->sc_ctrl_head); 1791 printf("sed:\n"); 1792 ohci_dump_ed(sc, sed); 1793 ohci_dump_tds(sc, setup); 1794 } 1795 #endif 1796 1797 return (USBD_NORMAL_COMPLETION); 1798 1799 bad3: 1800 ohci_free_std(sc, tail); 1801 bad2: 1802 ohci_free_std(sc, stat); 1803 bad1: 1804 return (err); 1805 } 1806 1807 /* 1808 * Add an ED to the schedule. Called with USB lock held. 1809 */ 1810 Static void 1811 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1812 { 1813 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1814 1815 KASSERT(mutex_owned(&sc->sc_lock)); 1816 1817 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1818 sizeof(head->ed.ed_nexted), 1819 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1820 sed->next = head->next; 1821 sed->ed.ed_nexted = head->ed.ed_nexted; 1822 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1823 sizeof(sed->ed.ed_nexted), 1824 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1825 head->next = sed; 1826 head->ed.ed_nexted = HTOO32(sed->physaddr); 1827 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1828 sizeof(head->ed.ed_nexted), 1829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1830 } 1831 1832 /* 1833 * Remove an ED from the schedule. Called with USB lock held. 1834 */ 1835 Static void 1836 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1837 { 1838 ohci_soft_ed_t *p; 1839 1840 KASSERT(mutex_owned(&sc->sc_lock)); 1841 1842 /* XXX */ 1843 for (p = head; p != NULL && p->next != sed; p = p->next) 1844 ; 1845 if (p == NULL) 1846 panic("ohci_rem_ed: ED not found"); 1847 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1848 sizeof(sed->ed.ed_nexted), 1849 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1850 p->next = sed->next; 1851 p->ed.ed_nexted = sed->ed.ed_nexted; 1852 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1853 sizeof(p->ed.ed_nexted), 1854 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1855 } 1856 1857 /* 1858 * When a transfer is completed the TD is added to the done queue by 1859 * the host controller. This queue is the processed by software. 1860 * Unfortunately the queue contains the physical address of the TD 1861 * and we have no simple way to translate this back to a kernel address. 1862 * To make the translation possible (and fast) we use a hash table of 1863 * TDs currently in the schedule. The physical address is used as the 1864 * hash value. 1865 */ 1866 1867 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1868 /* Called with USB lock held. */ 1869 void 1870 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1871 { 1872 int h = HASH(std->physaddr); 1873 1874 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1875 1876 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1877 } 1878 1879 /* Called with USB lock held. */ 1880 void 1881 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1882 { 1883 1884 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1885 1886 LIST_REMOVE(std, hnext); 1887 } 1888 1889 ohci_soft_td_t * 1890 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1891 { 1892 int h = HASH(a); 1893 ohci_soft_td_t *std; 1894 1895 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1896 std != NULL; 1897 std = LIST_NEXT(std, hnext)) 1898 if (std->physaddr == a) 1899 return (std); 1900 return (NULL); 1901 } 1902 1903 /* Called with USB lock held. */ 1904 void 1905 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1906 { 1907 int h = HASH(sitd->physaddr); 1908 1909 KASSERT(mutex_owned(&sc->sc_lock)); 1910 1911 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1912 sitd, (u_long)sitd->physaddr)); 1913 1914 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1915 } 1916 1917 /* Called with USB lock held. */ 1918 void 1919 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1920 { 1921 1922 KASSERT(mutex_owned(&sc->sc_lock)); 1923 1924 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1925 sitd, (u_long)sitd->physaddr)); 1926 1927 LIST_REMOVE(sitd, hnext); 1928 } 1929 1930 ohci_soft_itd_t * 1931 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1932 { 1933 int h = HASH(a); 1934 ohci_soft_itd_t *sitd; 1935 1936 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1937 sitd != NULL; 1938 sitd = LIST_NEXT(sitd, hnext)) 1939 if (sitd->physaddr == a) 1940 return (sitd); 1941 return (NULL); 1942 } 1943 1944 void 1945 ohci_timeout(void *addr) 1946 { 1947 struct ohci_xfer *oxfer = addr; 1948 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.ux_pipe; 1949 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 1950 1951 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1952 1953 if (sc->sc_dying) { 1954 mutex_enter(&sc->sc_lock); 1955 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1956 mutex_exit(&sc->sc_lock); 1957 return; 1958 } 1959 1960 /* Execute the abort in a process context. */ 1961 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1962 USB_TASKQ_MPSAFE); 1963 usb_add_task(oxfer->xfer.ux_pipe->up_dev, &oxfer->abort_task, 1964 USB_TASKQ_HC); 1965 } 1966 1967 void 1968 ohci_timeout_task(void *addr) 1969 { 1970 usbd_xfer_handle xfer = addr; 1971 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1972 1973 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1974 1975 mutex_enter(&sc->sc_lock); 1976 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1977 mutex_exit(&sc->sc_lock); 1978 } 1979 1980 #ifdef OHCI_DEBUG 1981 void 1982 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1983 { 1984 for (; std; std = std->nexttd) 1985 ohci_dump_td(sc, std); 1986 } 1987 1988 void 1989 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1990 { 1991 char sbuf[128]; 1992 1993 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1994 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1995 snprintb(sbuf, sizeof(sbuf), 1996 "\177\20" 1997 "b\22R\0" 1998 "f\23\02DP\0" 1999 "=\x0" "setup\0" 2000 "=\x1" "out\0" 2001 "=\x2" "in\0" 2002 "=\x3" "reserved\0" 2003 "f\25\03DI\0" 2004 "=\x07" "none\0" 2005 "f\30\02T\0" 2006 "=\x0" "carry\0" 2007 "=\x1" "carry\0" 2008 "=\x2" "0\0" 2009 "=\x3" "1\0" 2010 "f\32\02EC\0" 2011 "f\34\04CC\0", 2012 (uint32_t)O32TOH(std->td.td_flags)); 2013 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 2014 std, (u_long)std->physaddr, sbuf, 2015 (u_long)O32TOH(std->td.td_cbp), 2016 (u_long)O32TOH(std->td.td_nexttd), 2017 (u_long)O32TOH(std->td.td_be)); 2018 } 2019 2020 void 2021 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2022 { 2023 int i; 2024 2025 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2026 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2027 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2028 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2029 sitd, (u_long)sitd->physaddr, 2030 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2031 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2032 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2033 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2034 (u_long)O32TOH(sitd->itd.itd_bp0), 2035 (u_long)O32TOH(sitd->itd.itd_nextitd), 2036 (u_long)O32TOH(sitd->itd.itd_be)); 2037 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2038 printf("offs[%d]=0x%04x ", i, 2039 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2040 printf("\n"); 2041 } 2042 2043 void 2044 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2045 { 2046 for (; sitd; sitd = sitd->nextitd) 2047 ohci_dump_itd(sc, sitd); 2048 } 2049 2050 void 2051 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2052 { 2053 char sbuf[128], sbuf2[128]; 2054 2055 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2057 snprintb(sbuf, sizeof(sbuf), 2058 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2059 (uint32_t)O32TOH(sed->ed.ed_flags)); 2060 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2061 (uint32_t)O32TOH(sed->ed.ed_headp)); 2062 2063 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2064 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2065 sed, (u_long)sed->physaddr, 2066 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2067 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2068 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2069 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2070 (u_long)O32TOH(sed->ed.ed_headp), 2071 (u_long)O32TOH(sed->ed.ed_nexted)); 2072 } 2073 #endif 2074 2075 usbd_status 2076 ohci_open(usbd_pipe_handle pipe) 2077 { 2078 usbd_device_handle dev = pipe->up_dev; 2079 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2080 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2081 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2082 uint8_t addr = dev->ud_addr; 2083 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2084 ohci_soft_ed_t *sed; 2085 ohci_soft_td_t *std; 2086 ohci_soft_itd_t *sitd; 2087 ohci_physaddr_t tdphys; 2088 uint32_t fmt; 2089 usbd_status err = USBD_NOMEM; 2090 int ival; 2091 2092 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2093 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 2094 2095 if (sc->sc_dying) { 2096 return USBD_IOERROR; 2097 } 2098 2099 std = NULL; 2100 sed = NULL; 2101 2102 if (addr == sc->sc_addr) { 2103 switch (ed->bEndpointAddress) { 2104 case USB_CONTROL_ENDPOINT: 2105 pipe->up_methods = &ohci_root_ctrl_methods; 2106 break; 2107 case UE_DIR_IN | OHCI_INTR_ENDPT: 2108 pipe->up_methods = &ohci_root_intr_methods; 2109 break; 2110 default: 2111 err = USBD_INVAL; 2112 goto bad; 2113 } 2114 } else { 2115 sed = ohci_alloc_sed(sc); 2116 if (sed == NULL) 2117 goto bad; 2118 opipe->sed = sed; 2119 if (xfertype == UE_ISOCHRONOUS) { 2120 mutex_enter(&sc->sc_lock); 2121 sitd = ohci_alloc_sitd(sc); 2122 mutex_exit(&sc->sc_lock); 2123 if (sitd == NULL) 2124 goto bad; 2125 2126 opipe->tail.itd = sitd; 2127 tdphys = sitd->physaddr; 2128 fmt = OHCI_ED_FORMAT_ISO; 2129 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2130 fmt |= OHCI_ED_DIR_IN; 2131 else 2132 fmt |= OHCI_ED_DIR_OUT; 2133 } else { 2134 mutex_enter(&sc->sc_lock); 2135 std = ohci_alloc_std(sc); 2136 mutex_exit(&sc->sc_lock); 2137 if (std == NULL) 2138 goto bad; 2139 2140 opipe->tail.td = std; 2141 tdphys = std->physaddr; 2142 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2143 } 2144 sed->ed.ed_flags = HTOO32( 2145 OHCI_ED_SET_FA(addr) | 2146 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2147 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2148 fmt | 2149 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2150 sed->ed.ed_headp = HTOO32(tdphys | 2151 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2152 sed->ed.ed_tailp = HTOO32(tdphys); 2153 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2154 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2155 2156 switch (xfertype) { 2157 case UE_CONTROL: 2158 pipe->up_methods = &ohci_device_ctrl_methods; 2159 err = usb_allocmem(&sc->sc_bus, 2160 sizeof(usb_device_request_t), 2161 0, &opipe->u.ctl.reqdma); 2162 if (err) 2163 goto bad; 2164 mutex_enter(&sc->sc_lock); 2165 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2166 mutex_exit(&sc->sc_lock); 2167 break; 2168 case UE_INTERRUPT: 2169 pipe->up_methods = &ohci_device_intr_methods; 2170 ival = pipe->up_interval; 2171 if (ival == USBD_DEFAULT_INTERVAL) 2172 ival = ed->bInterval; 2173 err = ohci_device_setintr(sc, opipe, ival); 2174 if (err) 2175 goto bad; 2176 break; 2177 case UE_ISOCHRONOUS: 2178 pipe->up_methods = &ohci_device_isoc_methods; 2179 return (ohci_setup_isoc(pipe)); 2180 case UE_BULK: 2181 pipe->up_methods = &ohci_device_bulk_methods; 2182 mutex_enter(&sc->sc_lock); 2183 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2184 mutex_exit(&sc->sc_lock); 2185 break; 2186 } 2187 } 2188 2189 return USBD_NORMAL_COMPLETION; 2190 2191 bad: 2192 if (std != NULL) { 2193 mutex_enter(&sc->sc_lock); 2194 ohci_free_std(sc, std); 2195 mutex_exit(&sc->sc_lock); 2196 } 2197 if (sed != NULL) 2198 ohci_free_sed(sc, sed); 2199 return err; 2200 2201 } 2202 2203 /* 2204 * Close a reqular pipe. 2205 * Assumes that there are no pending transactions. 2206 */ 2207 void 2208 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2209 { 2210 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2211 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2212 ohci_soft_ed_t *sed = opipe->sed; 2213 2214 KASSERT(mutex_owned(&sc->sc_lock)); 2215 2216 #ifdef DIAGNOSTIC 2217 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2218 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2219 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2220 ohci_soft_td_t *std; 2221 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2222 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2223 "tl=0x%x pipe=%p, std=%p\n", sed, 2224 (int)O32TOH(sed->ed.ed_headp), 2225 (int)O32TOH(sed->ed.ed_tailp), 2226 pipe, std); 2227 #ifdef OHCI_DEBUG 2228 usbd_dump_pipe(&opipe->pipe); 2229 ohci_dump_ed(sc, sed); 2230 if (std) 2231 ohci_dump_td(sc, std); 2232 #endif 2233 usb_delay_ms(&sc->sc_bus, 2); 2234 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2235 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2236 printf("ohci_close_pipe: pipe still not empty\n"); 2237 } 2238 #endif 2239 ohci_rem_ed(sc, sed, head); 2240 /* Make sure the host controller is not touching this ED */ 2241 usb_delay_ms(&sc->sc_bus, 1); 2242 pipe->up_endpoint->ue_toggle = 2243 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2244 ohci_free_sed(sc, opipe->sed); 2245 } 2246 2247 /* 2248 * Abort a device request. 2249 * If this routine is called at splusb() it guarantees that the request 2250 * will be removed from the hardware scheduling and that the callback 2251 * for it will be called with USBD_CANCELLED status. 2252 * It's impossible to guarantee that the requested transfer will not 2253 * have happened since the hardware runs concurrently. 2254 * If the transaction has already happened we rely on the ordinary 2255 * interrupt processing to process it. 2256 * XXX This is most probably wrong. 2257 * XXXMRG this doesn't make sense anymore. 2258 */ 2259 void 2260 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2261 { 2262 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 2263 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 2264 ohci_soft_ed_t *sed = opipe->sed; 2265 ohci_soft_td_t *p, *n; 2266 ohci_physaddr_t headp; 2267 int hit; 2268 int wake; 2269 2270 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2271 2272 KASSERT(mutex_owned(&sc->sc_lock)); 2273 ASSERT_SLEEPABLE(); 2274 2275 if (sc->sc_dying) { 2276 /* If we're dying, just do the software part. */ 2277 xfer->ux_status = status; /* make software ignore it */ 2278 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2279 usb_transfer_complete(xfer); 2280 return; 2281 } 2282 2283 /* 2284 * If an abort is already in progress then just wait for it to 2285 * complete and return. 2286 */ 2287 if (xfer->ux_hcflags & UXFER_ABORTING) { 2288 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2289 #ifdef DIAGNOSTIC 2290 if (status == USBD_TIMEOUT) 2291 printf("%s: TIMEOUT while aborting\n", __func__); 2292 #endif 2293 /* Override the status which might be USBD_TIMEOUT. */ 2294 xfer->ux_status = status; 2295 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2296 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2297 while (xfer->ux_hcflags & UXFER_ABORTING) 2298 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2299 goto done; 2300 } 2301 xfer->ux_hcflags |= UXFER_ABORTING; 2302 2303 /* 2304 * Step 1: Make interrupt routine and hardware ignore xfer. 2305 */ 2306 xfer->ux_status = status; /* make software ignore it */ 2307 callout_stop(&xfer->ux_callout); 2308 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2309 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2310 sizeof(sed->ed.ed_flags), 2311 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2312 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2313 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2314 sizeof(sed->ed.ed_flags), 2315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2316 2317 /* 2318 * Step 2: Wait until we know hardware has finished any possible 2319 * use of the xfer. Also make sure the soft interrupt routine 2320 * has run. 2321 */ 2322 /* Hardware finishes in 1ms */ 2323 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2324 sc->sc_softwake = 1; 2325 usb_schedsoftintr(&sc->sc_bus); 2326 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2327 2328 /* 2329 * Step 3: Remove any vestiges of the xfer from the hardware. 2330 * The complication here is that the hardware may have executed 2331 * beyond the xfer we're trying to abort. So as we're scanning 2332 * the TDs of this xfer we check if the hardware points to 2333 * any of them. 2334 */ 2335 p = xfer->ux_hcpriv; 2336 #ifdef DIAGNOSTIC 2337 if (p == NULL) { 2338 xfer->ux_hcflags &= ~UXFER_ABORTING; /* XXX */ 2339 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2340 goto done; 2341 } 2342 #endif 2343 #ifdef OHCI_DEBUG 2344 if (ohcidebug > 1) { 2345 DPRINTF(("ohci_abort_xfer: sed=\n")); 2346 ohci_dump_ed(sc, sed); 2347 ohci_dump_tds(sc, p); 2348 } 2349 #endif 2350 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2351 hit = 0; 2352 for (; p->xfer == xfer; p = n) { 2353 hit |= headp == p->physaddr; 2354 n = p->nexttd; 2355 ohci_free_std(sc, p); 2356 } 2357 /* Zap headp register if hardware pointed inside the xfer. */ 2358 if (hit) { 2359 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2360 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2361 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2362 usb_syncmem(&sed->dma, 2363 sed->offs + offsetof(ohci_ed_t, ed_headp), 2364 sizeof(sed->ed.ed_headp), 2365 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2366 } else { 2367 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2368 } 2369 2370 /* 2371 * Step 4: Turn on hardware again. 2372 */ 2373 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2374 sizeof(sed->ed.ed_flags), 2375 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2376 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2377 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2378 sizeof(sed->ed.ed_flags), 2379 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2380 2381 /* 2382 * Step 5: Execute callback. 2383 */ 2384 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2385 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2386 usb_transfer_complete(xfer); 2387 if (wake) 2388 cv_broadcast(&xfer->ux_hccv); 2389 2390 done: 2391 KASSERT(mutex_owned(&sc->sc_lock)); 2392 } 2393 2394 /* 2395 * Data structures and routines to emulate the root hub. 2396 */ 2397 Static usb_device_descriptor_t ohci_devd = { 2398 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2399 .bDescriptorType = UDESC_DEVICE, 2400 .bcdUSB = {0x00, 0x01}, 2401 .bDeviceClass = UDCLASS_HUB, 2402 .bDeviceSubClass = UDSUBCLASS_HUB, 2403 .bDeviceProtocol = UDPROTO_FSHUB, 2404 .bMaxPacketSize = 64, 2405 .idVendor = {0}, 2406 .idProduct = {0}, 2407 .bcdDevice = {0x00,0x01}, 2408 .iManufacturer = 1, 2409 .iProduct = 2, 2410 .iSerialNumber = 0, 2411 .bNumConfigurations = 1 2412 }; 2413 2414 Static const usb_config_descriptor_t ohci_confd = { 2415 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 2416 .bDescriptorType = UDESC_CONFIG, 2417 .wTotalLength = USETWD( 2418 USB_CONFIG_DESCRIPTOR_SIZE + 2419 USB_INTERFACE_DESCRIPTOR_SIZE + 2420 USB_ENDPOINT_DESCRIPTOR_SIZE), 2421 .bNumInterface = 1, 2422 .bConfigurationValue = 1, 2423 .iConfiguration = 0, 2424 .bmAttributes = UC_ATTR_MBO | UC_SELF_POWERED, 2425 .bMaxPower = 0 2426 }; 2427 2428 Static const usb_interface_descriptor_t ohci_ifcd = { 2429 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 2430 .bDescriptorType = UDESC_INTERFACE, 2431 .bInterfaceNumber = 0, 2432 .bAlternateSetting = 0, 2433 .bNumEndpoints = 1, 2434 .bInterfaceClass = UICLASS_HUB, 2435 .bInterfaceSubClass = UISUBCLASS_HUB, 2436 .bInterfaceProtocol = UIPROTO_FSHUB, 2437 .iInterface = 0 2438 }; 2439 2440 Static const usb_endpoint_descriptor_t ohci_endpd = { 2441 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2442 .bDescriptorType = UDESC_ENDPOINT, 2443 .bEndpointAddress = UE_DIR_IN | OHCI_INTR_ENDPT, 2444 .bmAttributes = UE_INTERRUPT, 2445 .wMaxPacketSize = USETWD(8), 2446 .bInterval = 255, 2447 }; 2448 2449 Static const usb_hub_descriptor_t ohci_hubd = { 2450 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2451 .bDescriptorType = UDESC_HUB, 2452 }; 2453 2454 /* 2455 * Simulate a hardware hub by handling all the necessary requests. 2456 */ 2457 Static usbd_status 2458 ohci_root_ctrl_transfer(usbd_xfer_handle xfer) 2459 { 2460 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2461 usbd_status err; 2462 2463 /* Insert last in queue. */ 2464 mutex_enter(&sc->sc_lock); 2465 err = usb_insert_transfer(xfer); 2466 mutex_exit(&sc->sc_lock); 2467 if (err) 2468 return (err); 2469 2470 /* Pipe isn't running, start first */ 2471 return (ohci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2472 } 2473 2474 Static usbd_status 2475 ohci_root_ctrl_start(usbd_xfer_handle xfer) 2476 { 2477 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2478 usb_device_request_t *req; 2479 void *buf = NULL; 2480 int port, i; 2481 int len, value, index, l, totlen = 0; 2482 usb_port_status_t ps; 2483 usb_hub_descriptor_t hubd; 2484 usbd_status err; 2485 uint32_t v; 2486 2487 if (sc->sc_dying) 2488 return (USBD_IOERROR); 2489 2490 #ifdef DIAGNOSTIC 2491 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2492 /* XXX panic */ 2493 return (USBD_INVAL); 2494 #endif 2495 req = &xfer->ux_request; 2496 2497 DPRINTFN(4,("ohci_root_ctrl_control type=0x%02x request=%02x\n", 2498 req->bmRequestType, req->bRequest)); 2499 2500 len = UGETW(req->wLength); 2501 value = UGETW(req->wValue); 2502 index = UGETW(req->wIndex); 2503 2504 if (len != 0) 2505 buf = xfer->ux_buf; 2506 2507 #define C(x,y) ((x) | ((y) << 8)) 2508 switch(C(req->bRequest, req->bmRequestType)) { 2509 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2510 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2511 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2512 /* 2513 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2514 * for the integrated root hub. 2515 */ 2516 break; 2517 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2518 if (len > 0) { 2519 *(uint8_t *)buf = sc->sc_conf; 2520 totlen = 1; 2521 } 2522 break; 2523 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2524 DPRINTFN(8,("ohci_root_ctrl_control wValue=0x%04x\n", value)); 2525 if (len == 0) 2526 break; 2527 switch(value >> 8) { 2528 case UDESC_DEVICE: 2529 if ((value & 0xff) != 0) { 2530 err = USBD_IOERROR; 2531 goto ret; 2532 } 2533 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2534 USETW(ohci_devd.idVendor, sc->sc_id_vendor); 2535 memcpy(buf, &ohci_devd, l); 2536 break; 2537 case UDESC_CONFIG: 2538 if ((value & 0xff) != 0) { 2539 err = USBD_IOERROR; 2540 goto ret; 2541 } 2542 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2543 memcpy(buf, &ohci_confd, l); 2544 buf = (char *)buf + l; 2545 len -= l; 2546 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2547 totlen += l; 2548 memcpy(buf, &ohci_ifcd, l); 2549 buf = (char *)buf + l; 2550 len -= l; 2551 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2552 totlen += l; 2553 memcpy(buf, &ohci_endpd, l); 2554 break; 2555 case UDESC_STRING: 2556 #define sd ((usb_string_descriptor_t *)buf) 2557 switch (value & 0xff) { 2558 case 0: /* Language table */ 2559 totlen = usb_makelangtbl(sd, len); 2560 break; 2561 case 1: /* Vendor */ 2562 totlen = usb_makestrdesc(sd, len, 2563 sc->sc_vendor); 2564 break; 2565 case 2: /* Product */ 2566 totlen = usb_makestrdesc(sd, len, 2567 "OHCI root hub"); 2568 break; 2569 } 2570 #undef sd 2571 break; 2572 default: 2573 err = USBD_IOERROR; 2574 goto ret; 2575 } 2576 break; 2577 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2578 if (len > 0) { 2579 *(uint8_t *)buf = 0; 2580 totlen = 1; 2581 } 2582 break; 2583 case C(UR_GET_STATUS, UT_READ_DEVICE): 2584 if (len > 1) { 2585 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2586 totlen = 2; 2587 } 2588 break; 2589 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2590 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2591 if (len > 1) { 2592 USETW(((usb_status_t *)buf)->wStatus, 0); 2593 totlen = 2; 2594 } 2595 break; 2596 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2597 if (value >= USB_MAX_DEVICES) { 2598 err = USBD_IOERROR; 2599 goto ret; 2600 } 2601 sc->sc_addr = value; 2602 break; 2603 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2604 if (value != 0 && value != 1) { 2605 err = USBD_IOERROR; 2606 goto ret; 2607 } 2608 sc->sc_conf = value; 2609 break; 2610 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2611 break; 2612 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2613 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2614 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2615 err = USBD_IOERROR; 2616 goto ret; 2617 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2618 break; 2619 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2620 break; 2621 /* Hub requests */ 2622 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2623 break; 2624 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2625 DPRINTFN(8, ("ohci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 2626 "port=%d feature=%d\n", 2627 index, value)); 2628 if (index < 1 || index > sc->sc_noport) { 2629 err = USBD_IOERROR; 2630 goto ret; 2631 } 2632 port = OHCI_RH_PORT_STATUS(index); 2633 switch(value) { 2634 case UHF_PORT_ENABLE: 2635 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2636 break; 2637 case UHF_PORT_SUSPEND: 2638 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2639 break; 2640 case UHF_PORT_POWER: 2641 /* Yes, writing to the LOW_SPEED bit clears power. */ 2642 OWRITE4(sc, port, UPS_LOW_SPEED); 2643 break; 2644 case UHF_C_PORT_CONNECTION: 2645 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2646 break; 2647 case UHF_C_PORT_ENABLE: 2648 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2649 break; 2650 case UHF_C_PORT_SUSPEND: 2651 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2652 break; 2653 case UHF_C_PORT_OVER_CURRENT: 2654 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2655 break; 2656 case UHF_C_PORT_RESET: 2657 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2658 break; 2659 default: 2660 err = USBD_IOERROR; 2661 goto ret; 2662 } 2663 switch(value) { 2664 case UHF_C_PORT_CONNECTION: 2665 case UHF_C_PORT_ENABLE: 2666 case UHF_C_PORT_SUSPEND: 2667 case UHF_C_PORT_OVER_CURRENT: 2668 case UHF_C_PORT_RESET: 2669 /* Enable RHSC interrupt if condition is cleared. */ 2670 if ((OREAD4(sc, port) >> 16) == 0) 2671 ohci_rhsc_enable(sc); 2672 break; 2673 default: 2674 break; 2675 } 2676 break; 2677 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2678 if (len == 0) 2679 break; 2680 if ((value & 0xff) != 0) { 2681 err = USBD_IOERROR; 2682 goto ret; 2683 } 2684 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2685 hubd = ohci_hubd; 2686 hubd.bNbrPorts = sc->sc_noport; 2687 USETW(hubd.wHubCharacteristics, 2688 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2689 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2690 /* XXX overcurrent */ 2691 ); 2692 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2693 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2694 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2695 hubd.DeviceRemovable[i++] = (uint8_t)v; 2696 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2697 l = min(len, hubd.bDescLength); 2698 totlen = l; 2699 memcpy(buf, &hubd, l); 2700 break; 2701 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2702 if (len != 4) { 2703 err = USBD_IOERROR; 2704 goto ret; 2705 } 2706 memset(buf, 0, len); /* ? XXX */ 2707 totlen = len; 2708 break; 2709 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2710 DPRINTFN(8,("ohci_root_ctrl_transfer: get port status i=%d\n", 2711 index)); 2712 if (index < 1 || index > sc->sc_noport) { 2713 err = USBD_IOERROR; 2714 goto ret; 2715 } 2716 if (len != 4) { 2717 err = USBD_IOERROR; 2718 goto ret; 2719 } 2720 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2721 DPRINTFN(8,("ohci_root_ctrl_transfer: port status=0x%04x\n", 2722 v)); 2723 USETW(ps.wPortStatus, v); 2724 USETW(ps.wPortChange, v >> 16); 2725 l = min(len, sizeof ps); 2726 memcpy(buf, &ps, l); 2727 totlen = l; 2728 break; 2729 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2730 err = USBD_IOERROR; 2731 goto ret; 2732 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2733 break; 2734 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2735 if (index < 1 || index > sc->sc_noport) { 2736 err = USBD_IOERROR; 2737 goto ret; 2738 } 2739 port = OHCI_RH_PORT_STATUS(index); 2740 switch(value) { 2741 case UHF_PORT_ENABLE: 2742 OWRITE4(sc, port, UPS_PORT_ENABLED); 2743 break; 2744 case UHF_PORT_SUSPEND: 2745 OWRITE4(sc, port, UPS_SUSPEND); 2746 break; 2747 case UHF_PORT_RESET: 2748 DPRINTFN(5,("ohci_root_ctrl_transfer: reset port %d\n", 2749 index)); 2750 OWRITE4(sc, port, UPS_RESET); 2751 for (i = 0; i < 5; i++) { 2752 usb_delay_ms(&sc->sc_bus, 2753 USB_PORT_ROOT_RESET_DELAY); 2754 if (sc->sc_dying) { 2755 err = USBD_IOERROR; 2756 goto ret; 2757 } 2758 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2759 break; 2760 } 2761 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2762 index, OREAD4(sc, port))); 2763 break; 2764 case UHF_PORT_POWER: 2765 DPRINTFN(2,("ohci_root_ctrl_transfer: set port power " 2766 "%d\n", index)); 2767 OWRITE4(sc, port, UPS_PORT_POWER); 2768 break; 2769 default: 2770 err = USBD_IOERROR; 2771 goto ret; 2772 } 2773 break; 2774 default: 2775 err = USBD_IOERROR; 2776 goto ret; 2777 } 2778 xfer->ux_actlen = totlen; 2779 err = USBD_NORMAL_COMPLETION; 2780 ret: 2781 xfer->ux_status = err; 2782 mutex_enter(&sc->sc_lock); 2783 usb_transfer_complete(xfer); 2784 mutex_exit(&sc->sc_lock); 2785 return (USBD_IN_PROGRESS); 2786 } 2787 2788 /* Abort a root control request. */ 2789 Static void 2790 ohci_root_ctrl_abort(usbd_xfer_handle xfer) 2791 { 2792 /* Nothing to do, all transfers are synchronous. */ 2793 } 2794 2795 /* Close the root pipe. */ 2796 Static void 2797 ohci_root_ctrl_close(usbd_pipe_handle pipe) 2798 { 2799 DPRINTF(("ohci_root_ctrl_close\n")); 2800 /* Nothing to do. */ 2801 } 2802 2803 Static usbd_status 2804 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2805 { 2806 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2807 usbd_status err; 2808 2809 /* Insert last in queue. */ 2810 mutex_enter(&sc->sc_lock); 2811 err = usb_insert_transfer(xfer); 2812 mutex_exit(&sc->sc_lock); 2813 if (err) 2814 return (err); 2815 2816 /* Pipe isn't running, start first */ 2817 return (ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2818 } 2819 2820 Static usbd_status 2821 ohci_root_intr_start(usbd_xfer_handle xfer) 2822 { 2823 usbd_pipe_handle pipe = xfer->ux_pipe; 2824 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2825 2826 if (sc->sc_dying) 2827 return (USBD_IOERROR); 2828 2829 mutex_enter(&sc->sc_lock); 2830 KASSERT(sc->sc_intrxfer == NULL); 2831 sc->sc_intrxfer = xfer; 2832 mutex_exit(&sc->sc_lock); 2833 2834 return (USBD_IN_PROGRESS); 2835 } 2836 2837 /* Abort a root interrupt request. */ 2838 Static void 2839 ohci_root_intr_abort(usbd_xfer_handle xfer) 2840 { 2841 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2842 2843 KASSERT(mutex_owned(&sc->sc_lock)); 2844 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2845 2846 sc->sc_intrxfer = NULL; 2847 2848 xfer->ux_status = USBD_CANCELLED; 2849 usb_transfer_complete(xfer); 2850 } 2851 2852 /* Close the root pipe. */ 2853 Static void 2854 ohci_root_intr_close(usbd_pipe_handle pipe) 2855 { 2856 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2857 2858 KASSERT(mutex_owned(&sc->sc_lock)); 2859 2860 DPRINTF(("ohci_root_intr_close\n")); 2861 2862 sc->sc_intrxfer = NULL; 2863 } 2864 2865 /************************/ 2866 2867 Static usbd_status 2868 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2869 { 2870 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2871 usbd_status err; 2872 2873 /* Insert last in queue. */ 2874 mutex_enter(&sc->sc_lock); 2875 err = usb_insert_transfer(xfer); 2876 mutex_exit(&sc->sc_lock); 2877 if (err) 2878 return (err); 2879 2880 /* Pipe isn't running, start first */ 2881 return (ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2882 } 2883 2884 Static usbd_status 2885 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2886 { 2887 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2888 usbd_status err; 2889 2890 if (sc->sc_dying) 2891 return (USBD_IOERROR); 2892 2893 #ifdef DIAGNOSTIC 2894 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 2895 /* XXX panic */ 2896 printf("ohci_device_ctrl_transfer: not a request\n"); 2897 return (USBD_INVAL); 2898 } 2899 #endif 2900 2901 mutex_enter(&sc->sc_lock); 2902 err = ohci_device_request(xfer); 2903 mutex_exit(&sc->sc_lock); 2904 if (err) 2905 return (err); 2906 2907 if (sc->sc_bus.ub_usepolling) 2908 ohci_waitintr(sc, xfer); 2909 return (USBD_IN_PROGRESS); 2910 } 2911 2912 /* Abort a device control request. */ 2913 Static void 2914 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2915 { 2916 #ifdef DIAGNOSTIC 2917 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2918 #endif 2919 2920 KASSERT(mutex_owned(&sc->sc_lock)); 2921 2922 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2923 ohci_abort_xfer(xfer, USBD_CANCELLED); 2924 } 2925 2926 /* Close a device control pipe. */ 2927 Static void 2928 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2929 { 2930 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2931 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2932 2933 KASSERT(mutex_owned(&sc->sc_lock)); 2934 2935 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2936 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2937 ohci_free_std(sc, opipe->tail.td); 2938 } 2939 2940 /************************/ 2941 2942 Static void 2943 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2944 { 2945 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2946 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2947 2948 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2949 } 2950 2951 Static void 2952 ohci_noop(usbd_pipe_handle pipe) 2953 { 2954 } 2955 2956 Static usbd_status 2957 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2958 { 2959 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2960 usbd_status err; 2961 2962 /* Insert last in queue. */ 2963 mutex_enter(&sc->sc_lock); 2964 err = usb_insert_transfer(xfer); 2965 mutex_exit(&sc->sc_lock); 2966 if (err) 2967 return (err); 2968 2969 /* Pipe isn't running, start first */ 2970 return (ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2971 } 2972 2973 Static usbd_status 2974 ohci_device_bulk_start(usbd_xfer_handle xfer) 2975 { 2976 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 2977 usbd_device_handle dev = opipe->pipe.up_dev; 2978 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2979 int addr = dev->ud_addr; 2980 ohci_soft_td_t *data, *tail, *tdp; 2981 ohci_soft_ed_t *sed; 2982 int len, isread, endpt; 2983 usbd_status err; 2984 2985 if (sc->sc_dying) 2986 return (USBD_IOERROR); 2987 2988 #ifdef DIAGNOSTIC 2989 if (xfer->ux_rqflags & URQ_REQUEST) { 2990 /* XXX panic */ 2991 printf("ohci_device_bulk_start: a request\n"); 2992 return (USBD_INVAL); 2993 } 2994 #endif 2995 2996 mutex_enter(&sc->sc_lock); 2997 2998 len = xfer->ux_length; 2999 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3000 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3001 sed = opipe->sed; 3002 3003 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 3004 "flags=%d endpt=%d\n", xfer, len, isread, xfer->ux_flags, 3005 endpt)); 3006 3007 opipe->u.bulk.isread = isread; 3008 opipe->u.bulk.length = len; 3009 3010 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3011 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3012 /* Update device address */ 3013 sed->ed.ed_flags = HTOO32( 3014 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 3015 OHCI_ED_SET_FA(addr)); 3016 3017 /* Allocate a chain of new TDs (including a new tail). */ 3018 data = opipe->tail.td; 3019 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 3020 data, &tail); 3021 if (err) 3022 return err; 3023 3024 /* We want interrupt at the end of the transfer. */ 3025 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 3026 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 3027 tail->flags |= OHCI_CALL_DONE; 3028 tail = tail->nexttd; /* point at sentinel */ 3029 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 3030 sizeof(tail->td.td_flags), 3031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3032 if (err) { 3033 mutex_exit(&sc->sc_lock); 3034 return (err); 3035 } 3036 3037 tail->xfer = NULL; 3038 xfer->ux_hcpriv = data; 3039 3040 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 3041 "td_cbp=0x%08x td_be=0x%08x\n", 3042 (int)O32TOH(sed->ed.ed_flags), 3043 (int)O32TOH(data->td.td_flags), 3044 (int)O32TOH(data->td.td_cbp), 3045 (int)O32TOH(data->td.td_be))); 3046 3047 #ifdef OHCI_DEBUG 3048 if (ohcidebug > 5) { 3049 ohci_dump_ed(sc, sed); 3050 ohci_dump_tds(sc, data); 3051 } 3052 #endif 3053 3054 /* Insert ED in schedule */ 3055 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 3056 tdp->xfer = xfer; 3057 } 3058 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3059 opipe->tail.td = tail; 3060 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3061 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3063 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 3064 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3065 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3066 ohci_timeout, xfer); 3067 } 3068 mutex_exit(&sc->sc_lock); 3069 3070 #if 0 3071 /* This goes wrong if we are too slow. */ 3072 if (ohcidebug > 10) { 3073 delay(10000); 3074 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3075 OREAD4(sc, OHCI_COMMAND_STATUS))); 3076 ohci_dump_ed(sc, sed); 3077 ohci_dump_tds(sc, data); 3078 } 3079 #endif 3080 3081 return (USBD_IN_PROGRESS); 3082 } 3083 3084 Static void 3085 ohci_device_bulk_abort(usbd_xfer_handle xfer) 3086 { 3087 #ifdef DIAGNOSTIC 3088 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3089 #endif 3090 3091 KASSERT(mutex_owned(&sc->sc_lock)); 3092 3093 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 3094 ohci_abort_xfer(xfer, USBD_CANCELLED); 3095 } 3096 3097 /* 3098 * Close a device bulk pipe. 3099 */ 3100 Static void 3101 ohci_device_bulk_close(usbd_pipe_handle pipe) 3102 { 3103 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3104 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3105 3106 KASSERT(mutex_owned(&sc->sc_lock)); 3107 3108 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 3109 ohci_close_pipe(pipe, sc->sc_bulk_head); 3110 ohci_free_std(sc, opipe->tail.td); 3111 } 3112 3113 /************************/ 3114 3115 Static usbd_status 3116 ohci_device_intr_transfer(usbd_xfer_handle xfer) 3117 { 3118 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3119 usbd_status err; 3120 3121 /* Insert last in queue. */ 3122 mutex_enter(&sc->sc_lock); 3123 err = usb_insert_transfer(xfer); 3124 mutex_exit(&sc->sc_lock); 3125 if (err) 3126 return (err); 3127 3128 /* Pipe isn't running, start first */ 3129 return (ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3130 } 3131 3132 Static usbd_status 3133 ohci_device_intr_start(usbd_xfer_handle xfer) 3134 { 3135 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3136 usbd_device_handle dev = opipe->pipe.up_dev; 3137 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3138 ohci_soft_ed_t *sed = opipe->sed; 3139 ohci_soft_td_t *data, *tail; 3140 int len, isread, endpt; 3141 3142 if (sc->sc_dying) 3143 return (USBD_IOERROR); 3144 3145 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 3146 "flags=%d priv=%p\n", 3147 xfer, xfer->ux_length, xfer->ux_flags, xfer->ux_priv)); 3148 3149 #ifdef DIAGNOSTIC 3150 if (xfer->ux_rqflags & URQ_REQUEST) 3151 panic("ohci_device_intr_transfer: a request"); 3152 #endif 3153 3154 len = xfer->ux_length; 3155 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 3156 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3157 3158 data = opipe->tail.td; 3159 mutex_enter(&sc->sc_lock); 3160 tail = ohci_alloc_std(sc); 3161 mutex_exit(&sc->sc_lock); 3162 if (tail == NULL) 3163 return (USBD_NOMEM); 3164 tail->xfer = NULL; 3165 3166 data->td.td_flags = HTOO32( 3167 isread ? OHCI_TD_IN : OHCI_TD_OUT | 3168 OHCI_TD_NOCC | 3169 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 3170 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 3171 data->td.td_flags |= HTOO32(OHCI_TD_R); 3172 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 3173 data->nexttd = tail; 3174 data->td.td_nexttd = HTOO32(tail->physaddr); 3175 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3176 data->len = len; 3177 data->xfer = xfer; 3178 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3179 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3181 xfer->ux_hcpriv = data; 3182 3183 #ifdef OHCI_DEBUG 3184 if (ohcidebug > 5) { 3185 DPRINTF(("ohci_device_intr_transfer:\n")); 3186 ohci_dump_ed(sc, sed); 3187 ohci_dump_tds(sc, data); 3188 } 3189 #endif 3190 3191 /* Insert ED in schedule */ 3192 mutex_enter(&sc->sc_lock); 3193 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3194 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3195 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3196 opipe->tail.td = tail; 3197 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3198 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3200 3201 #if 0 3202 /* 3203 * This goes horribly wrong, printing thousands of descriptors, 3204 * because false references are followed due to the fact that the 3205 * TD is gone. 3206 */ 3207 if (ohcidebug > 5) { 3208 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3209 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 3210 OREAD4(sc, OHCI_COMMAND_STATUS))); 3211 ohci_dump_ed(sc, sed); 3212 ohci_dump_tds(sc, data); 3213 } 3214 #endif 3215 mutex_exit(&sc->sc_lock); 3216 3217 return (USBD_IN_PROGRESS); 3218 } 3219 3220 /* Abort a device interrupt request. */ 3221 Static void 3222 ohci_device_intr_abort(usbd_xfer_handle xfer) 3223 { 3224 #ifdef DIAGNOSTIC 3225 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3226 #endif 3227 3228 KASSERT(mutex_owned(&sc->sc_lock)); 3229 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3230 3231 ohci_abort_xfer(xfer, USBD_CANCELLED); 3232 } 3233 3234 /* Close a device interrupt pipe. */ 3235 Static void 3236 ohci_device_intr_close(usbd_pipe_handle pipe) 3237 { 3238 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3239 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3240 int nslots = opipe->u.intr.nslots; 3241 int pos = opipe->u.intr.pos; 3242 int j; 3243 ohci_soft_ed_t *p, *sed = opipe->sed; 3244 3245 KASSERT(mutex_owned(&sc->sc_lock)); 3246 3247 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3248 pipe, nslots, pos)); 3249 usb_syncmem(&sed->dma, sed->offs, 3250 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3251 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3252 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3253 sizeof(sed->ed.ed_flags), 3254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3255 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3256 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3257 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3258 3259 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3260 continue; 3261 #ifdef DIAGNOSTIC 3262 if (p == NULL) 3263 panic("ohci_device_intr_close: ED not found"); 3264 #endif 3265 p->next = sed->next; 3266 p->ed.ed_nexted = sed->ed.ed_nexted; 3267 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3268 sizeof(p->ed.ed_nexted), 3269 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3270 3271 for (j = 0; j < nslots; j++) 3272 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3273 3274 ohci_free_std(sc, opipe->tail.td); 3275 ohci_free_sed(sc, opipe->sed); 3276 } 3277 3278 Static usbd_status 3279 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3280 { 3281 int i, j, best; 3282 u_int npoll, slow, shigh, nslots; 3283 u_int bestbw, bw; 3284 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3285 3286 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3287 if (ival == 0) { 3288 printf("ohci_setintr: 0 interval\n"); 3289 return (USBD_INVAL); 3290 } 3291 3292 npoll = OHCI_NO_INTRS; 3293 while (npoll > ival) 3294 npoll /= 2; 3295 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3296 3297 /* 3298 * We now know which level in the tree the ED must go into. 3299 * Figure out which slot has most bandwidth left over. 3300 * Slots to examine: 3301 * npoll 3302 * 1 0 3303 * 2 1 2 3304 * 4 3 4 5 6 3305 * 8 7 8 9 10 11 12 13 14 3306 * N (N-1) .. (N-1+N-1) 3307 */ 3308 slow = npoll-1; 3309 shigh = slow + npoll; 3310 nslots = OHCI_NO_INTRS / npoll; 3311 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3312 bw = 0; 3313 for (j = 0; j < nslots; j++) 3314 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3315 if (bw < bestbw) { 3316 best = i; 3317 bestbw = bw; 3318 } 3319 } 3320 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3321 best, slow, shigh, bestbw)); 3322 3323 mutex_enter(&sc->sc_lock); 3324 hsed = sc->sc_eds[best]; 3325 sed->next = hsed->next; 3326 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3327 sizeof(hsed->ed.ed_flags), 3328 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3329 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3330 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3331 sizeof(sed->ed.ed_flags), 3332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3333 hsed->next = sed; 3334 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3335 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3336 sizeof(hsed->ed.ed_flags), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 mutex_exit(&sc->sc_lock); 3339 3340 for (j = 0; j < nslots; j++) 3341 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3342 opipe->u.intr.nslots = nslots; 3343 opipe->u.intr.pos = best; 3344 3345 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3346 return (USBD_NORMAL_COMPLETION); 3347 } 3348 3349 /***********************/ 3350 3351 usbd_status 3352 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3353 { 3354 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3355 usbd_status err; 3356 3357 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3358 3359 /* Put it on our queue, */ 3360 mutex_enter(&sc->sc_lock); 3361 err = usb_insert_transfer(xfer); 3362 mutex_exit(&sc->sc_lock); 3363 3364 /* bail out on error, */ 3365 if (err && err != USBD_IN_PROGRESS) 3366 return (err); 3367 3368 /* XXX should check inuse here */ 3369 3370 /* insert into schedule, */ 3371 ohci_device_isoc_enter(xfer); 3372 3373 /* and start if the pipe wasn't running */ 3374 if (!err) 3375 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3376 3377 return (err); 3378 } 3379 3380 void 3381 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3382 { 3383 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3384 usbd_device_handle dev = opipe->pipe.up_dev; 3385 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3386 ohci_soft_ed_t *sed = opipe->sed; 3387 struct iso *iso = &opipe->u.iso; 3388 ohci_soft_itd_t *sitd, *nsitd; 3389 ohci_physaddr_t buf, offs, noffs, bp0; 3390 int i, ncur, nframes; 3391 3392 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3393 "nframes=%d\n", 3394 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 3395 3396 if (sc->sc_dying) 3397 return; 3398 3399 if (iso->next == -1) { 3400 /* Not in use yet, schedule it a few frames ahead. */ 3401 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3402 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3403 iso->next)); 3404 } 3405 3406 sitd = opipe->tail.itd; 3407 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3408 bp0 = OHCI_PAGE(buf); 3409 offs = OHCI_PAGE_OFFSET(buf); 3410 nframes = xfer->ux_nframes; 3411 xfer->ux_hcpriv = sitd; 3412 for (i = ncur = 0; i < nframes; i++, ncur++) { 3413 noffs = offs + xfer->ux_frlengths[i]; 3414 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3415 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3416 3417 /* Allocate next ITD */ 3418 mutex_enter(&sc->sc_lock); 3419 nsitd = ohci_alloc_sitd(sc); 3420 mutex_exit(&sc->sc_lock); 3421 if (nsitd == NULL) { 3422 /* XXX what now? */ 3423 printf("%s: isoc TD alloc failed\n", 3424 device_xname(sc->sc_dev)); 3425 return; 3426 } 3427 3428 /* Fill current ITD */ 3429 sitd->itd.itd_flags = HTOO32( 3430 OHCI_ITD_NOCC | 3431 OHCI_ITD_SET_SF(iso->next) | 3432 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3433 OHCI_ITD_SET_FC(ncur)); 3434 sitd->itd.itd_bp0 = HTOO32(bp0); 3435 sitd->nextitd = nsitd; 3436 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3437 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3438 sitd->xfer = xfer; 3439 sitd->flags = 0; 3440 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3442 3443 sitd = nsitd; 3444 iso->next = iso->next + ncur; 3445 bp0 = OHCI_PAGE(buf + offs); 3446 ncur = 0; 3447 } 3448 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3449 offs = noffs; 3450 } 3451 mutex_enter(&sc->sc_lock); 3452 nsitd = ohci_alloc_sitd(sc); 3453 mutex_exit(&sc->sc_lock); 3454 if (nsitd == NULL) { 3455 /* XXX what now? */ 3456 printf("%s: isoc TD alloc failed\n", 3457 device_xname(sc->sc_dev)); 3458 return; 3459 } 3460 /* Fixup last used ITD */ 3461 sitd->itd.itd_flags = HTOO32( 3462 OHCI_ITD_NOCC | 3463 OHCI_ITD_SET_SF(iso->next) | 3464 OHCI_ITD_SET_DI(0) | 3465 OHCI_ITD_SET_FC(ncur)); 3466 sitd->itd.itd_bp0 = HTOO32(bp0); 3467 sitd->nextitd = nsitd; 3468 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3469 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3470 sitd->xfer = xfer; 3471 sitd->flags = OHCI_CALL_DONE; 3472 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3473 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3474 3475 iso->next = iso->next + ncur; 3476 iso->inuse += nframes; 3477 3478 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3479 3480 xfer->ux_status = USBD_IN_PROGRESS; 3481 3482 #ifdef OHCI_DEBUG 3483 if (ohcidebug > 5) { 3484 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3485 O32TOH(sc->sc_hcca->hcca_frame_number))); 3486 ohci_dump_itds(sc, xfer->ux_hcpriv); 3487 ohci_dump_ed(sc, sed); 3488 } 3489 #endif 3490 3491 mutex_enter(&sc->sc_lock); 3492 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3493 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3494 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3495 opipe->tail.itd = nsitd; 3496 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3497 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3498 sizeof(sed->ed.ed_flags), 3499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3500 mutex_exit(&sc->sc_lock); 3501 3502 #ifdef OHCI_DEBUG 3503 if (ohcidebug > 5) { 3504 delay(150000); 3505 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3506 O32TOH(sc->sc_hcca->hcca_frame_number))); 3507 ohci_dump_itds(sc, xfer->ux_hcpriv); 3508 ohci_dump_ed(sc, sed); 3509 } 3510 #endif 3511 } 3512 3513 usbd_status 3514 ohci_device_isoc_start(usbd_xfer_handle xfer) 3515 { 3516 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3517 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 3518 3519 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3520 3521 mutex_enter(&sc->sc_lock); 3522 3523 if (sc->sc_dying) { 3524 mutex_exit(&sc->sc_lock); 3525 return (USBD_IOERROR); 3526 } 3527 3528 #ifdef DIAGNOSTIC 3529 if (xfer->ux_status != USBD_IN_PROGRESS) 3530 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3531 #endif 3532 3533 /* XXX anything to do? */ 3534 3535 mutex_exit(&sc->sc_lock); 3536 3537 return (USBD_IN_PROGRESS); 3538 } 3539 3540 void 3541 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3542 { 3543 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3544 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 3545 ohci_soft_ed_t *sed; 3546 ohci_soft_itd_t *sitd; 3547 3548 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3549 3550 KASSERT(mutex_owned(&sc->sc_lock)); 3551 3552 /* Transfer is already done. */ 3553 if (xfer->ux_status != USBD_NOT_STARTED && 3554 xfer->ux_status != USBD_IN_PROGRESS) { 3555 printf("ohci_device_isoc_abort: early return\n"); 3556 goto done; 3557 } 3558 3559 /* Give xfer the requested abort code. */ 3560 xfer->ux_status = USBD_CANCELLED; 3561 3562 sed = opipe->sed; 3563 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3564 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3565 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3566 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3567 sizeof(sed->ed.ed_flags), 3568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3569 3570 sitd = xfer->ux_hcpriv; 3571 #ifdef DIAGNOSTIC 3572 if (sitd == NULL) { 3573 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3574 goto done; 3575 } 3576 #endif 3577 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3578 #ifdef DIAGNOSTIC 3579 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3580 sitd->isdone = 1; 3581 #endif 3582 } 3583 3584 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3585 3586 /* Run callback. */ 3587 usb_transfer_complete(xfer); 3588 3589 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3590 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3591 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3592 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3593 3594 done: 3595 KASSERT(mutex_owned(&sc->sc_lock)); 3596 } 3597 3598 void 3599 ohci_device_isoc_done(usbd_xfer_handle xfer) 3600 { 3601 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3602 } 3603 3604 usbd_status 3605 ohci_setup_isoc(usbd_pipe_handle pipe) 3606 { 3607 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3608 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3609 struct iso *iso = &opipe->u.iso; 3610 3611 iso->next = -1; 3612 iso->inuse = 0; 3613 3614 mutex_enter(&sc->sc_lock); 3615 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3616 mutex_exit(&sc->sc_lock); 3617 3618 return (USBD_NORMAL_COMPLETION); 3619 } 3620 3621 void 3622 ohci_device_isoc_close(usbd_pipe_handle pipe) 3623 { 3624 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3625 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3626 3627 KASSERT(mutex_owned(&sc->sc_lock)); 3628 3629 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3630 ohci_close_pipe(pipe, sc->sc_isoc_head); 3631 #ifdef DIAGNOSTIC 3632 opipe->tail.itd->isdone = 1; 3633 #endif 3634 ohci_free_sitd(sc, opipe->tail.itd); 3635 } 3636
Indexes created Fri Oct 03 02:09:57 GMT 2025