ohci.c revision 1.254.2.14
1 /* $NetBSD: ohci.c,v 1.254.2.14 2014/12/05 13:23:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.14 2014/12/05 13:23:38 skrll Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kmem.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 #include <sys/select.h> 52 #include <sys/proc.h> 53 #include <sys/queue.h> 54 #include <sys/cpu.h> 55 56 #include <machine/endian.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include <dev/usb/usbdivar.h> 61 #include <dev/usb/usb_mem.h> 62 #include <dev/usb/usb_quirks.h> 63 64 #include <dev/usb/ohcireg.h> 65 #include <dev/usb/ohcivar.h> 66 #include <dev/usb/usbroothub.h> 67 68 69 70 #ifdef OHCI_DEBUG 71 #define DPRINTF(x) if (ohcidebug) printf x 72 #define DPRINTFN(n,x) if (ohcidebug>(n)) printf x 73 int ohcidebug = 0; 74 #else 75 #define DPRINTF(x) 76 #define DPRINTFN(n,x) 77 #endif 78 79 #if BYTE_ORDER == BIG_ENDIAN 80 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 81 #else 82 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 83 #endif 84 85 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 86 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 87 #define HTOO16(val) O16TOH(val) 88 #define HTOO32(val) O32TOH(val) 89 90 struct ohci_pipe; 91 92 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 93 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 94 95 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 96 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 97 98 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 99 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 100 101 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 102 ohci_soft_td_t *); 103 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 104 ohci_softc_t *, int, int, usbd_xfer_handle, 105 ohci_soft_td_t *, ohci_soft_td_t **); 106 107 Static usbd_status ohci_open(usbd_pipe_handle); 108 Static void ohci_poll(struct usbd_bus *); 109 Static void ohci_softintr(void *); 110 Static void ohci_waitintr(ohci_softc_t *, usbd_xfer_handle); 111 Static void ohci_rhsc(ohci_softc_t *, usbd_xfer_handle); 112 Static void ohci_rhsc_softint(void *arg); 113 114 Static usbd_status ohci_device_request(usbd_xfer_handle xfer); 115 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 116 ohci_soft_ed_t *); 117 118 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 119 ohci_soft_ed_t *); 120 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 121 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 122 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 123 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 124 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 125 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 126 127 Static usbd_status ohci_setup_isoc(usbd_pipe_handle pipe); 128 Static void ohci_device_isoc_enter(usbd_xfer_handle); 129 130 Static usbd_xfer_handle ohci_allocx(struct usbd_bus *); 131 Static void ohci_freex(struct usbd_bus *, usbd_xfer_handle); 132 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 133 Static int ohci_roothub_ctrl(struct usbd_bus *, 134 usb_device_request_t *, void *, int); 135 136 Static usbd_status ohci_root_intr_transfer(usbd_xfer_handle); 137 Static usbd_status ohci_root_intr_start(usbd_xfer_handle); 138 Static void ohci_root_intr_abort(usbd_xfer_handle); 139 Static void ohci_root_intr_close(usbd_pipe_handle); 140 Static void ohci_root_intr_done(usbd_xfer_handle); 141 142 Static usbd_status ohci_device_ctrl_transfer(usbd_xfer_handle); 143 Static usbd_status ohci_device_ctrl_start(usbd_xfer_handle); 144 Static void ohci_device_ctrl_abort(usbd_xfer_handle); 145 Static void ohci_device_ctrl_close(usbd_pipe_handle); 146 Static void ohci_device_ctrl_done(usbd_xfer_handle); 147 148 Static usbd_status ohci_device_bulk_transfer(usbd_xfer_handle); 149 Static usbd_status ohci_device_bulk_start(usbd_xfer_handle); 150 Static void ohci_device_bulk_abort(usbd_xfer_handle); 151 Static void ohci_device_bulk_close(usbd_pipe_handle); 152 Static void ohci_device_bulk_done(usbd_xfer_handle); 153 154 Static usbd_status ohci_device_intr_transfer(usbd_xfer_handle); 155 Static usbd_status ohci_device_intr_start(usbd_xfer_handle); 156 Static void ohci_device_intr_abort(usbd_xfer_handle); 157 Static void ohci_device_intr_close(usbd_pipe_handle); 158 Static void ohci_device_intr_done(usbd_xfer_handle); 159 160 Static usbd_status ohci_device_isoc_transfer(usbd_xfer_handle); 161 Static usbd_status ohci_device_isoc_start(usbd_xfer_handle); 162 Static void ohci_device_isoc_abort(usbd_xfer_handle); 163 Static void ohci_device_isoc_close(usbd_pipe_handle); 164 Static void ohci_device_isoc_done(usbd_xfer_handle); 165 166 Static usbd_status ohci_device_setintr(ohci_softc_t *sc, 167 struct ohci_pipe *pipe, int ival); 168 169 Static void ohci_timeout(void *); 170 Static void ohci_timeout_task(void *); 171 Static void ohci_rhsc_enable(void *); 172 173 Static void ohci_close_pipe(usbd_pipe_handle, ohci_soft_ed_t *); 174 Static void ohci_abort_xfer(usbd_xfer_handle, usbd_status); 175 176 Static void ohci_device_clear_toggle(usbd_pipe_handle pipe); 177 Static void ohci_noop(usbd_pipe_handle pipe); 178 179 #ifdef OHCI_DEBUG 180 Static void ohci_dumpregs(ohci_softc_t *); 181 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 182 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 183 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 184 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 185 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 186 #endif 187 188 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 189 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 190 #define OWRITE1(sc, r, x) \ 191 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 192 #define OWRITE2(sc, r, x) \ 193 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 194 #define OWRITE4(sc, r, x) \ 195 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 196 197 static __inline uint32_t 198 OREAD4(ohci_softc_t *sc, bus_size_t r) 199 { 200 201 OBARR(sc); 202 return bus_space_read_4(sc->iot, sc->ioh, r); 203 } 204 205 /* Reverse the bits in a value 0 .. 31 */ 206 Static uint8_t revbits[OHCI_NO_INTRS] = 207 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 208 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 209 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 210 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 211 212 struct ohci_pipe { 213 struct usbd_pipe pipe; 214 ohci_soft_ed_t *sed; 215 union { 216 ohci_soft_td_t *td; 217 ohci_soft_itd_t *itd; 218 } tail; 219 /* Info needed for different pipe kinds. */ 220 union { 221 /* Control pipe */ 222 struct { 223 usb_dma_t reqdma; 224 u_int length; 225 ohci_soft_td_t *setup, *data, *stat; 226 } ctl; 227 /* Interrupt pipe */ 228 struct { 229 int nslots; 230 int pos; 231 } intr; 232 /* Bulk pipe */ 233 struct { 234 u_int length; 235 int isread; 236 } bulk; 237 /* Iso pipe */ 238 struct iso { 239 int next, inuse; 240 } iso; 241 } u; 242 }; 243 244 Static const struct usbd_bus_methods ohci_bus_methods = { 245 .ubm_open = ohci_open, 246 .ubm_softint = ohci_softintr, 247 .ubm_dopoll = ohci_poll, 248 .ubm_allocx = ohci_allocx, 249 .ubm_freex = ohci_freex, 250 .ubm_getlock = ohci_get_lock, 251 .ubm_rhctrl = ohci_roothub_ctrl, 252 }; 253 254 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 255 .upm_transfer = ohci_root_intr_transfer, 256 .upm_start = ohci_root_intr_start, 257 .upm_abort = ohci_root_intr_abort, 258 .upm_close = ohci_root_intr_close, 259 .upm_cleartoggle = ohci_noop, 260 .upm_done = ohci_root_intr_done, 261 }; 262 263 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 264 .upm_transfer = ohci_device_ctrl_transfer, 265 .upm_start = ohci_device_ctrl_start, 266 .upm_abort = ohci_device_ctrl_abort, 267 .upm_close = ohci_device_ctrl_close, 268 .upm_cleartoggle = ohci_noop, 269 .upm_done = ohci_device_ctrl_done, 270 }; 271 272 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 273 .upm_transfer = ohci_device_intr_transfer, 274 .upm_start = ohci_device_intr_start, 275 .upm_abort = ohci_device_intr_abort, 276 .upm_close = ohci_device_intr_close, 277 .upm_cleartoggle = ohci_device_clear_toggle, 278 .upm_done = ohci_device_intr_done, 279 }; 280 281 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 282 .upm_transfer = ohci_device_bulk_transfer, 283 .upm_start = ohci_device_bulk_start, 284 .upm_abort = ohci_device_bulk_abort, 285 .upm_close = ohci_device_bulk_close, 286 .upm_cleartoggle = ohci_device_clear_toggle, 287 .upm_done = ohci_device_bulk_done, 288 }; 289 290 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 291 .upm_transfer = ohci_device_isoc_transfer, 292 .upm_start = ohci_device_isoc_start, 293 .upm_abort = ohci_device_isoc_abort, 294 .upm_close = ohci_device_isoc_close, 295 .upm_cleartoggle = ohci_noop, 296 .upm_done = ohci_device_isoc_done, 297 }; 298 299 int 300 ohci_activate(device_t self, enum devact act) 301 { 302 struct ohci_softc *sc = device_private(self); 303 304 switch (act) { 305 case DVACT_DEACTIVATE: 306 sc->sc_dying = 1; 307 return 0; 308 default: 309 return EOPNOTSUPP; 310 } 311 } 312 313 void 314 ohci_childdet(device_t self, device_t child) 315 { 316 struct ohci_softc *sc = device_private(self); 317 318 KASSERT(sc->sc_child == child); 319 sc->sc_child = NULL; 320 } 321 322 int 323 ohci_detach(struct ohci_softc *sc, int flags) 324 { 325 int rv = 0; 326 327 if (sc->sc_child != NULL) 328 rv = config_detach(sc->sc_child, flags); 329 330 if (rv != 0) 331 return rv; 332 333 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 334 335 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 336 callout_destroy(&sc->sc_tmo_rhsc); 337 338 softint_disestablish(sc->sc_rhsc_si); 339 340 cv_destroy(&sc->sc_softwake_cv); 341 342 mutex_destroy(&sc->sc_lock); 343 mutex_destroy(&sc->sc_intr_lock); 344 345 if (sc->sc_hcca != NULL) 346 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 347 pool_cache_destroy(sc->sc_xferpool); 348 349 return rv; 350 } 351 352 ohci_soft_ed_t * 353 ohci_alloc_sed(ohci_softc_t *sc) 354 { 355 ohci_soft_ed_t *sed; 356 usbd_status err; 357 int i, offs; 358 usb_dma_t dma; 359 360 if (sc->sc_freeeds == NULL) { 361 DPRINTFN(2, ("ohci_alloc_sed: allocating chunk\n")); 362 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 363 OHCI_ED_ALIGN, &dma); 364 if (err) 365 return 0; 366 for (i = 0; i < OHCI_SED_CHUNK; i++) { 367 offs = i * OHCI_SED_SIZE; 368 sed = KERNADDR(&dma, offs); 369 sed->physaddr = DMAADDR(&dma, offs); 370 sed->dma = dma; 371 sed->offs = offs; 372 sed->next = sc->sc_freeeds; 373 sc->sc_freeeds = sed; 374 } 375 } 376 sed = sc->sc_freeeds; 377 sc->sc_freeeds = sed->next; 378 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 379 sed->next = 0; 380 return sed; 381 } 382 383 void 384 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 385 { 386 sed->next = sc->sc_freeeds; 387 sc->sc_freeeds = sed; 388 } 389 390 ohci_soft_td_t * 391 ohci_alloc_std(ohci_softc_t *sc) 392 { 393 ohci_soft_td_t *std; 394 usbd_status err; 395 int i, offs; 396 usb_dma_t dma; 397 398 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 399 400 if (sc->sc_freetds == NULL) { 401 DPRINTFN(2, ("ohci_alloc_std: allocating chunk\n")); 402 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 403 OHCI_TD_ALIGN, &dma); 404 if (err) 405 return NULL; 406 for(i = 0; i < OHCI_STD_CHUNK; i++) { 407 offs = i * OHCI_STD_SIZE; 408 std = KERNADDR(&dma, offs); 409 std->physaddr = DMAADDR(&dma, offs); 410 std->dma = dma; 411 std->offs = offs; 412 std->nexttd = sc->sc_freetds; 413 sc->sc_freetds = std; 414 } 415 } 416 417 std = sc->sc_freetds; 418 sc->sc_freetds = std->nexttd; 419 memset(&std->td, 0, sizeof(ohci_td_t)); 420 std->nexttd = NULL; 421 std->xfer = NULL; 422 ohci_hash_add_td(sc, std); 423 424 return std; 425 } 426 427 void 428 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 429 { 430 431 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 432 433 ohci_hash_rem_td(sc, std); 434 std->nexttd = sc->sc_freetds; 435 sc->sc_freetds = std; 436 } 437 438 usbd_status 439 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 440 int alen, int rd, usbd_xfer_handle xfer, 441 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 442 { 443 ohci_soft_td_t *next, *cur; 444 ohci_physaddr_t dataphys, dataphysend; 445 uint32_t tdflags; 446 int len, curlen; 447 usb_dma_t *dma = &xfer->ux_dmabuf; 448 uint16_t flags = xfer->ux_flags; 449 450 DPRINTFN(alen < 4096,("ohci_alloc_std_chain: start len=%d\n", alen)); 451 452 KASSERT(mutex_owned(&sc->sc_lock)); 453 454 len = alen; 455 cur = sp; 456 dataphys = DMAADDR(dma, 0); 457 dataphysend = OHCI_PAGE(dataphys + len - 1); 458 usb_syncmem(dma, 0, len, 459 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 460 tdflags = HTOO32( 461 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 462 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 463 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 464 465 for (;;) { 466 next = ohci_alloc_std(sc); 467 if (next == NULL) 468 goto nomem; 469 470 /* The OHCI hardware can handle at most one page crossing. */ 471 if (OHCI_PAGE(dataphys) == dataphysend || 472 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 473 /* we can handle it in this TD */ 474 curlen = len; 475 } else { 476 /* must use multiple TDs, fill as much as possible. */ 477 curlen = 2 * OHCI_PAGE_SIZE - 478 (dataphys & (OHCI_PAGE_SIZE-1)); 479 /* the length must be a multiple of the max size */ 480 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 481 #ifdef DIAGNOSTIC 482 if (curlen == 0) 483 panic("ohci_alloc_std: curlen == 0"); 484 #endif 485 } 486 DPRINTFN(4,("ohci_alloc_std_chain: dataphys=0x%08x " 487 "dataphysend=0x%08x len=%d curlen=%d\n", 488 dataphys, dataphysend, 489 len, curlen)); 490 len -= curlen; 491 492 cur->td.td_flags = tdflags; 493 cur->td.td_cbp = HTOO32(dataphys); 494 cur->nexttd = next; 495 cur->td.td_nexttd = HTOO32(next->physaddr); 496 cur->td.td_be = HTOO32(dataphys + curlen - 1); 497 cur->len = curlen; 498 cur->flags = OHCI_ADD_LEN; 499 cur->xfer = xfer; 500 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 DPRINTFN(10,("ohci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 503 dataphys, dataphys + curlen - 1)); 504 if (len == 0) 505 break; 506 DPRINTFN(10,("ohci_alloc_std_chain: extend chain\n")); 507 dataphys += curlen; 508 cur = next; 509 } 510 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 511 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 512 /* Force a 0 length transfer at the end. */ 513 514 cur = next; 515 next = ohci_alloc_std(sc); 516 if (next == NULL) 517 goto nomem; 518 519 cur->td.td_flags = tdflags; 520 cur->td.td_cbp = 0; /* indicate 0 length packet */ 521 cur->nexttd = next; 522 cur->td.td_nexttd = HTOO32(next->physaddr); 523 cur->td.td_be = ~0; 524 cur->len = 0; 525 cur->flags = 0; 526 cur->xfer = xfer; 527 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 528 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 529 DPRINTFN(2,("ohci_alloc_std_chain: add 0 xfer\n")); 530 } 531 *ep = cur; 532 533 return USBD_NORMAL_COMPLETION; 534 535 nomem: 536 537 /* Don't free sp - let the caller do that */ 538 ohci_free_std_chain(sc, sp->nexttd, NULL); 539 540 return USBD_NOMEM; 541 } 542 543 Static void 544 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 545 ohci_soft_td_t *stdend) 546 { 547 ohci_soft_td_t *p; 548 549 for (; std != stdend; std = p) { 550 p = std->nexttd; 551 ohci_free_std(sc, std); 552 } 553 } 554 555 ohci_soft_itd_t * 556 ohci_alloc_sitd(ohci_softc_t *sc) 557 { 558 ohci_soft_itd_t *sitd; 559 usbd_status err; 560 int i, offs; 561 usb_dma_t dma; 562 563 if (sc->sc_freeitds == NULL) { 564 DPRINTFN(2, ("ohci_alloc_sitd: allocating chunk\n")); 565 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 566 OHCI_ITD_ALIGN, &dma); 567 if (err) 568 return NULL; 569 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 570 offs = i * OHCI_SITD_SIZE; 571 sitd = KERNADDR(&dma, offs); 572 sitd->physaddr = DMAADDR(&dma, offs); 573 sitd->dma = dma; 574 sitd->offs = offs; 575 sitd->nextitd = sc->sc_freeitds; 576 sc->sc_freeitds = sitd; 577 } 578 } 579 580 sitd = sc->sc_freeitds; 581 sc->sc_freeitds = sitd->nextitd; 582 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 583 sitd->nextitd = NULL; 584 sitd->xfer = NULL; 585 ohci_hash_add_itd(sc, sitd); 586 587 #ifdef DIAGNOSTIC 588 sitd->isdone = 0; 589 #endif 590 591 return sitd; 592 } 593 594 void 595 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 596 { 597 598 DPRINTFN(10,("ohci_free_sitd: sitd=%p\n", sitd)); 599 600 #ifdef DIAGNOSTIC 601 if (!sitd->isdone) { 602 panic("ohci_free_sitd: sitd=%p not done", sitd); 603 return; 604 } 605 /* Warn double free */ 606 sitd->isdone = 0; 607 #endif 608 609 ohci_hash_rem_itd(sc, sitd); 610 sitd->nextitd = sc->sc_freeitds; 611 sc->sc_freeitds = sitd; 612 } 613 614 int 615 ohci_init(ohci_softc_t *sc) 616 { 617 ohci_soft_ed_t *sed, *psed; 618 usbd_status err; 619 int i; 620 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 621 622 DPRINTF(("ohci_init: start\n")); 623 aprint_normal_dev(sc->sc_dev, ""); 624 625 sc->sc_hcca = NULL; 626 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 627 628 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 629 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 630 cv_init(&sc->sc_softwake_cv, "ohciab"); 631 632 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 633 ohci_rhsc_softint, sc); 634 635 for (i = 0; i < OHCI_HASH_SIZE; i++) 636 LIST_INIT(&sc->sc_hash_tds[i]); 637 for (i = 0; i < OHCI_HASH_SIZE; i++) 638 LIST_INIT(&sc->sc_hash_itds[i]); 639 640 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 641 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 642 643 rev = OREAD4(sc, OHCI_REVISION); 644 aprint_normal("OHCI version %d.%d%s\n", 645 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 646 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 647 648 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 649 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 650 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 651 return -1; 652 } 653 sc->sc_bus.ub_revision = USBREV_1_0; 654 sc->sc_bus.ub_usedma = true; 655 656 /* XXX determine alignment by R/W */ 657 /* Allocate the HCCA area. */ 658 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 659 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 660 if (err) { 661 sc->sc_hcca = NULL; 662 return err; 663 } 664 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 665 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 666 667 sc->sc_eintrs = OHCI_NORMAL_INTRS; 668 669 /* Allocate dummy ED that starts the control list. */ 670 sc->sc_ctrl_head = ohci_alloc_sed(sc); 671 if (sc->sc_ctrl_head == NULL) { 672 err = ENOMEM; 673 goto bad1; 674 } 675 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 676 677 /* Allocate dummy ED that starts the bulk list. */ 678 sc->sc_bulk_head = ohci_alloc_sed(sc); 679 if (sc->sc_bulk_head == NULL) { 680 err = ENOMEM; 681 goto bad2; 682 } 683 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 684 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 685 sizeof(sc->sc_bulk_head->ed), 686 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 687 688 /* Allocate dummy ED that starts the isochronous list. */ 689 sc->sc_isoc_head = ohci_alloc_sed(sc); 690 if (sc->sc_isoc_head == NULL) { 691 err = ENOMEM; 692 goto bad3; 693 } 694 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 695 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 696 sizeof(sc->sc_isoc_head->ed), 697 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 698 699 /* Allocate all the dummy EDs that make up the interrupt tree. */ 700 for (i = 0; i < OHCI_NO_EDS; i++) { 701 sed = ohci_alloc_sed(sc); 702 if (sed == NULL) { 703 while (--i >= 0) 704 ohci_free_sed(sc, sc->sc_eds[i]); 705 err = ENOMEM; 706 goto bad4; 707 } 708 /* All ED fields are set to 0. */ 709 sc->sc_eds[i] = sed; 710 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 711 if (i != 0) 712 psed = sc->sc_eds[(i-1) / 2]; 713 else 714 psed= sc->sc_isoc_head; 715 sed->next = psed; 716 sed->ed.ed_nexted = HTOO32(psed->physaddr); 717 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 718 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 719 } 720 /* 721 * Fill HCCA interrupt table. The bit reversal is to get 722 * the tree set up properly to spread the interrupts. 723 */ 724 for (i = 0; i < OHCI_NO_INTRS; i++) 725 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 726 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 727 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 729 730 #ifdef OHCI_DEBUG 731 if (ohcidebug > 15) { 732 for (i = 0; i < OHCI_NO_EDS; i++) { 733 printf("ed#%d ", i); 734 ohci_dump_ed(sc, sc->sc_eds[i]); 735 } 736 printf("iso "); 737 ohci_dump_ed(sc, sc->sc_isoc_head); 738 } 739 #endif 740 741 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 742 ctl = OREAD4(sc, OHCI_CONTROL); 743 rwc = ctl & OHCI_RWC; 744 fm = OREAD4(sc, OHCI_FM_INTERVAL); 745 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 746 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 747 748 /* Determine in what context we are running. */ 749 if (ctl & OHCI_IR) { 750 /* SMM active, request change */ 751 DPRINTF(("ohci_init: SMM active, request owner change\n")); 752 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 753 (OHCI_OC | OHCI_MIE)) 754 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 755 s = OREAD4(sc, OHCI_COMMAND_STATUS); 756 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 757 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 758 usb_delay_ms(&sc->sc_bus, 1); 759 ctl = OREAD4(sc, OHCI_CONTROL); 760 } 761 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 762 if ((ctl & OHCI_IR) == 0) { 763 aprint_error_dev(sc->sc_dev, 764 "SMM does not respond, resetting\n"); 765 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 766 goto reset; 767 } 768 #if 0 769 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 770 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 771 /* BIOS started controller. */ 772 DPRINTF(("ohci_init: BIOS active\n")); 773 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 774 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 775 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 776 } 777 #endif 778 } else { 779 DPRINTF(("ohci_init: cold started\n")); 780 reset: 781 /* Controller was cold started. */ 782 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 783 } 784 785 /* 786 * This reset should not be necessary according to the OHCI spec, but 787 * without it some controllers do not start. 788 */ 789 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 790 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 791 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 792 793 /* We now own the host controller and the bus has been reset. */ 794 795 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 796 /* Nominal time for a reset is 10 us. */ 797 for (i = 0; i < 10; i++) { 798 delay(10); 799 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 800 if (!hcr) 801 break; 802 } 803 if (hcr) { 804 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 805 err = EIO; 806 goto bad5; 807 } 808 #ifdef OHCI_DEBUG 809 if (ohcidebug > 15) 810 ohci_dumpregs(sc); 811 #endif 812 813 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 814 815 /* Set up HC registers. */ 816 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 817 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 818 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 819 /* disable all interrupts and then switch on all desired interrupts */ 820 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 821 /* switch on desired functional features */ 822 ctl = OREAD4(sc, OHCI_CONTROL); 823 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 824 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 825 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 826 /* And finally start it! */ 827 OWRITE4(sc, OHCI_CONTROL, ctl); 828 829 /* 830 * The controller is now OPERATIONAL. Set a some final 831 * registers that should be set earlier, but that the 832 * controller ignores when in the SUSPEND state. 833 */ 834 ival = OHCI_GET_IVAL(fm); 835 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 836 fm |= OHCI_FSMPS(ival) | ival; 837 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 838 per = OHCI_PERIODIC(ival); /* 90% periodic */ 839 OWRITE4(sc, OHCI_PERIODIC_START, per); 840 841 if (sc->sc_flags & OHCIF_SUPERIO) { 842 /* no overcurrent protection */ 843 desca |= OHCI_NOCP; 844 /* 845 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 846 * that 847 * - ports are always power switched 848 * - don't wait for powered root hub port 849 */ 850 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 851 } 852 853 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 854 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 855 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 856 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 857 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 858 859 /* 860 * The AMD756 requires a delay before re-reading the register, 861 * otherwise it will occasionally report 0 ports. 862 */ 863 sc->sc_noport = 0; 864 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 865 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 866 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 867 } 868 869 #ifdef OHCI_DEBUG 870 if (ohcidebug > 5) 871 ohci_dumpregs(sc); 872 #endif 873 874 /* Set up the bus struct. */ 875 sc->sc_bus.ub_methods = &ohci_bus_methods; 876 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 877 878 sc->sc_control = sc->sc_intre = 0; 879 880 /* Finally, turn on interrupts. */ 881 DPRINTFN(1,("ohci_init: enabling %#x\n", sc->sc_eintrs | OHCI_MIE)); 882 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 883 884 return 0; 885 886 bad5: 887 for (i = 0; i < OHCI_NO_EDS; i++) 888 ohci_free_sed(sc, sc->sc_eds[i]); 889 bad4: 890 ohci_free_sed(sc, sc->sc_isoc_head); 891 bad3: 892 ohci_free_sed(sc, sc->sc_bulk_head); 893 bad2: 894 ohci_free_sed(sc, sc->sc_ctrl_head); 895 bad1: 896 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 897 sc->sc_hcca = NULL; 898 return err; 899 } 900 901 usbd_xfer_handle 902 ohci_allocx(struct usbd_bus *bus) 903 { 904 struct ohci_softc *sc = bus->ub_hcpriv; 905 usbd_xfer_handle xfer; 906 907 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 908 if (xfer != NULL) { 909 memset(xfer, 0, sizeof(struct ohci_xfer)); 910 #ifdef DIAGNOSTIC 911 xfer->ux_state = XFER_BUSY; 912 #endif 913 } 914 return xfer; 915 } 916 917 void 918 ohci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 919 { 920 struct ohci_softc *sc = bus->ub_hcpriv; 921 922 #ifdef DIAGNOSTIC 923 if (xfer->ux_state != XFER_BUSY) { 924 printf("ohci_freex: xfer=%p not busy, 0x%08x\n", xfer, 925 xfer->ux_state); 926 } 927 xfer->ux_state = XFER_FREE; 928 #endif 929 pool_cache_put(sc->sc_xferpool, xfer); 930 } 931 932 Static void 933 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 934 { 935 struct ohci_softc *sc = bus->ub_hcpriv; 936 937 *lock = &sc->sc_lock; 938 } 939 940 /* 941 * Shut down the controller when the system is going down. 942 */ 943 bool 944 ohci_shutdown(device_t self, int flags) 945 { 946 ohci_softc_t *sc = device_private(self); 947 948 DPRINTF(("ohci_shutdown: stopping the HC\n")); 949 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 950 return true; 951 } 952 953 bool 954 ohci_resume(device_t dv, const pmf_qual_t *qual) 955 { 956 ohci_softc_t *sc = device_private(dv); 957 uint32_t ctl; 958 959 mutex_spin_enter(&sc->sc_intr_lock); 960 sc->sc_bus.ub_usepolling++; 961 mutex_spin_exit(&sc->sc_intr_lock); 962 963 /* Some broken BIOSes do not recover these values */ 964 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 965 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 966 sc->sc_ctrl_head->physaddr); 967 OWRITE4(sc, OHCI_BULK_HEAD_ED, 968 sc->sc_bulk_head->physaddr); 969 if (sc->sc_intre) 970 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 971 (OHCI_ALL_INTRS | OHCI_MIE)); 972 if (sc->sc_control) 973 ctl = sc->sc_control; 974 else 975 ctl = OREAD4(sc, OHCI_CONTROL); 976 ctl |= OHCI_HCFS_RESUME; 977 OWRITE4(sc, OHCI_CONTROL, ctl); 978 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 979 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 980 OWRITE4(sc, OHCI_CONTROL, ctl); 981 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 982 sc->sc_control = sc->sc_intre = 0; 983 984 mutex_spin_enter(&sc->sc_intr_lock); 985 sc->sc_bus.ub_usepolling--; 986 mutex_spin_exit(&sc->sc_intr_lock); 987 988 return true; 989 } 990 991 bool 992 ohci_suspend(device_t dv, const pmf_qual_t *qual) 993 { 994 ohci_softc_t *sc = device_private(dv); 995 uint32_t ctl; 996 997 mutex_spin_enter(&sc->sc_intr_lock); 998 sc->sc_bus.ub_usepolling++; 999 mutex_spin_exit(&sc->sc_intr_lock); 1000 1001 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1002 if (sc->sc_control == 0) { 1003 /* 1004 * Preserve register values, in case that BIOS 1005 * does not recover them. 1006 */ 1007 sc->sc_control = ctl; 1008 sc->sc_intre = OREAD4(sc, 1009 OHCI_INTERRUPT_ENABLE); 1010 } 1011 ctl |= OHCI_HCFS_SUSPEND; 1012 OWRITE4(sc, OHCI_CONTROL, ctl); 1013 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1014 1015 mutex_spin_enter(&sc->sc_intr_lock); 1016 sc->sc_bus.ub_usepolling--; 1017 mutex_spin_exit(&sc->sc_intr_lock); 1018 1019 return true; 1020 } 1021 1022 #ifdef OHCI_DEBUG 1023 void 1024 ohci_dumpregs(ohci_softc_t *sc) 1025 { 1026 DPRINTF(("ohci_dumpregs: rev=0x%08x control=0x%08x command=0x%08x\n", 1027 OREAD4(sc, OHCI_REVISION), 1028 OREAD4(sc, OHCI_CONTROL), 1029 OREAD4(sc, OHCI_COMMAND_STATUS))); 1030 DPRINTF((" intrstat=0x%08x intre=0x%08x intrd=0x%08x\n", 1031 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1032 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1033 OREAD4(sc, OHCI_INTERRUPT_DISABLE))); 1034 DPRINTF((" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x\n", 1035 OREAD4(sc, OHCI_HCCA), 1036 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1037 OREAD4(sc, OHCI_CONTROL_HEAD_ED))); 1038 DPRINTF((" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x\n", 1039 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1040 OREAD4(sc, OHCI_BULK_HEAD_ED), 1041 OREAD4(sc, OHCI_BULK_CURRENT_ED))); 1042 DPRINTF((" done=0x%08x fmival=0x%08x fmrem=0x%08x\n", 1043 OREAD4(sc, OHCI_DONE_HEAD), 1044 OREAD4(sc, OHCI_FM_INTERVAL), 1045 OREAD4(sc, OHCI_FM_REMAINING))); 1046 DPRINTF((" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x\n", 1047 OREAD4(sc, OHCI_FM_NUMBER), 1048 OREAD4(sc, OHCI_PERIODIC_START), 1049 OREAD4(sc, OHCI_LS_THRESHOLD))); 1050 DPRINTF((" desca=0x%08x descb=0x%08x stat=0x%08x\n", 1051 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1052 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1053 OREAD4(sc, OHCI_RH_STATUS))); 1054 DPRINTF((" port1=0x%08x port2=0x%08x\n", 1055 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1056 OREAD4(sc, OHCI_RH_PORT_STATUS(2)))); 1057 DPRINTF((" HCCA: frame_number=0x%04x done_head=0x%08x\n", 1058 O32TOH(sc->sc_hcca->hcca_frame_number), 1059 O32TOH(sc->sc_hcca->hcca_done_head))); 1060 } 1061 #endif 1062 1063 Static int ohci_intr1(ohci_softc_t *); 1064 1065 int 1066 ohci_intr(void *p) 1067 { 1068 ohci_softc_t *sc = p; 1069 int ret = 0; 1070 1071 if (sc == NULL) 1072 return 0; 1073 1074 mutex_spin_enter(&sc->sc_intr_lock); 1075 1076 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1077 goto done; 1078 1079 /* If we get an interrupt while polling, then just ignore it. */ 1080 if (sc->sc_bus.ub_usepolling) { 1081 #ifdef DIAGNOSTIC 1082 DPRINTFN(16, ("ohci_intr: ignored interrupt while polling\n")); 1083 #endif 1084 /* for level triggered intrs, should do something to ack */ 1085 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1086 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1087 1088 goto done; 1089 } 1090 1091 ret = ohci_intr1(sc); 1092 1093 done: 1094 mutex_spin_exit(&sc->sc_intr_lock); 1095 return ret; 1096 } 1097 1098 Static int 1099 ohci_intr1(ohci_softc_t *sc) 1100 { 1101 uint32_t intrs, eintrs; 1102 1103 DPRINTFN(14,("ohci_intr1: enter\n")); 1104 1105 /* In case the interrupt occurs before initialization has completed. */ 1106 if (sc == NULL || sc->sc_hcca == NULL) { 1107 #ifdef DIAGNOSTIC 1108 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1109 #endif 1110 return 0; 1111 } 1112 1113 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1114 1115 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1116 if (!intrs) 1117 return 0; 1118 1119 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1120 eintrs = intrs & sc->sc_eintrs; 1121 DPRINTFN(7, ("ohci_intr: sc=%p intrs=%#x(%#x) eintrs=%#x(%#x)\n", 1122 sc, (u_int)intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), 1123 (u_int)eintrs, sc->sc_eintrs)); 1124 1125 if (!eintrs) { 1126 return 0; 1127 } 1128 1129 if (eintrs & OHCI_SO) { 1130 sc->sc_overrun_cnt++; 1131 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1132 printf("%s: %u scheduling overruns\n", 1133 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1134 sc->sc_overrun_cnt = 0; 1135 } 1136 /* XXX do what */ 1137 eintrs &= ~OHCI_SO; 1138 } 1139 if (eintrs & OHCI_WDH) { 1140 /* 1141 * We block the interrupt below, and reenable it later from 1142 * ohci_softintr(). 1143 */ 1144 usb_schedsoftintr(&sc->sc_bus); 1145 } 1146 if (eintrs & OHCI_RD) { 1147 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1148 /* XXX process resume detect */ 1149 } 1150 if (eintrs & OHCI_UE) { 1151 printf("%s: unrecoverable error, controller halted\n", 1152 device_xname(sc->sc_dev)); 1153 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1154 /* XXX what else */ 1155 } 1156 if (eintrs & OHCI_RHSC) { 1157 /* 1158 * We block the interrupt below, and reenable it later from 1159 * a timeout. 1160 */ 1161 softint_schedule(sc->sc_rhsc_si); 1162 } 1163 1164 if (eintrs != 0) { 1165 /* Block unprocessed interrupts. */ 1166 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1167 sc->sc_eintrs &= ~eintrs; 1168 DPRINTFN(1, ("%s: blocking intrs 0x%x\n", 1169 device_xname(sc->sc_dev), eintrs)); 1170 } 1171 1172 return 1; 1173 } 1174 1175 void 1176 ohci_rhsc_enable(void *v_sc) 1177 { 1178 ohci_softc_t *sc = v_sc; 1179 1180 DPRINTFN(1, ("%s: %s\n", __func__, device_xname(sc->sc_dev))); 1181 mutex_spin_enter(&sc->sc_intr_lock); 1182 sc->sc_eintrs |= OHCI_RHSC; 1183 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1184 mutex_spin_exit(&sc->sc_intr_lock); 1185 } 1186 1187 #ifdef OHCI_DEBUG 1188 const char *ohci_cc_strs[] = { 1189 "NO_ERROR", 1190 "CRC", 1191 "BIT_STUFFING", 1192 "DATA_TOGGLE_MISMATCH", 1193 "STALL", 1194 "DEVICE_NOT_RESPONDING", 1195 "PID_CHECK_FAILURE", 1196 "UNEXPECTED_PID", 1197 "DATA_OVERRUN", 1198 "DATA_UNDERRUN", 1199 "BUFFER_OVERRUN", 1200 "BUFFER_UNDERRUN", 1201 "reserved", 1202 "reserved", 1203 "NOT_ACCESSED", 1204 "NOT_ACCESSED", 1205 }; 1206 #endif 1207 1208 void 1209 ohci_softintr(void *v) 1210 { 1211 struct usbd_bus *bus = v; 1212 ohci_softc_t *sc = bus->ub_hcpriv; 1213 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1214 ohci_soft_td_t *std, *sdone, *stdnext; 1215 usbd_xfer_handle xfer; 1216 struct ohci_pipe *opipe; 1217 int len, cc; 1218 int i, j, actlen, iframes, uedir; 1219 ohci_physaddr_t done; 1220 1221 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1222 1223 DPRINTFN(10,("ohci_softintr: enter\n")); 1224 1225 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1226 sizeof(sc->sc_hcca->hcca_done_head), 1227 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1228 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1229 sc->sc_hcca->hcca_done_head = 0; 1230 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1231 sizeof(sc->sc_hcca->hcca_done_head), 1232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1233 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1234 sc->sc_eintrs |= OHCI_WDH; 1235 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1236 1237 /* Reverse the done list. */ 1238 for (sdone = NULL, sidone = NULL; done != 0; ) { 1239 std = ohci_hash_find_td(sc, done); 1240 if (std != NULL) { 1241 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1242 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1243 std->dnext = sdone; 1244 done = O32TOH(std->td.td_nexttd); 1245 sdone = std; 1246 DPRINTFN(10,("add TD %p\n", std)); 1247 continue; 1248 } 1249 sitd = ohci_hash_find_itd(sc, done); 1250 if (sitd != NULL) { 1251 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1252 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1253 sitd->dnext = sidone; 1254 done = O32TOH(sitd->itd.itd_nextitd); 1255 sidone = sitd; 1256 DPRINTFN(5,("add ITD %p\n", sitd)); 1257 continue; 1258 } 1259 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1260 (u_long)done); 1261 break; 1262 } 1263 1264 DPRINTFN(10,("ohci_softintr: sdone=%p sidone=%p\n", sdone, sidone)); 1265 1266 #ifdef OHCI_DEBUG 1267 if (ohcidebug > 10) { 1268 DPRINTF(("ohci_process_done: TD done:\n")); 1269 for (std = sdone; std; std = std->dnext) 1270 ohci_dump_td(sc, std); 1271 } 1272 #endif 1273 1274 for (std = sdone; std; std = stdnext) { 1275 xfer = std->xfer; 1276 stdnext = std->dnext; 1277 DPRINTFN(10, ("ohci_process_done: std=%p xfer=%p hcpriv=%p\n", 1278 std, xfer, xfer ? xfer->ux_hcpriv : 0)); 1279 if (xfer == NULL) { 1280 /* 1281 * xfer == NULL: There seems to be no xfer associated 1282 * with this TD. It is tailp that happened to end up on 1283 * the done queue. 1284 * Shouldn't happen, but some chips are broken(?). 1285 */ 1286 continue; 1287 } 1288 if (xfer->ux_status == USBD_CANCELLED || 1289 xfer->ux_status == USBD_TIMEOUT) { 1290 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1291 xfer)); 1292 /* Handled by abort routine. */ 1293 continue; 1294 } 1295 callout_stop(&xfer->ux_callout); 1296 1297 len = std->len; 1298 if (std->td.td_cbp != 0) 1299 len -= O32TOH(std->td.td_be) - 1300 O32TOH(std->td.td_cbp) + 1; 1301 DPRINTFN(10, ("ohci_process_done: len=%d, flags=0x%x\n", len, 1302 std->flags)); 1303 if (std->flags & OHCI_ADD_LEN) 1304 xfer->ux_actlen += len; 1305 1306 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1307 if (cc == OHCI_CC_NO_ERROR) { 1308 if (std->flags & OHCI_CALL_DONE) { 1309 xfer->ux_status = USBD_NORMAL_COMPLETION; 1310 usb_transfer_complete(xfer); 1311 } 1312 ohci_free_std(sc, std); 1313 } else { 1314 /* 1315 * Endpoint is halted. First unlink all the TDs 1316 * belonging to the failed transfer, and then restart 1317 * the endpoint. 1318 */ 1319 ohci_soft_td_t *p, *n; 1320 opipe = (struct ohci_pipe *)xfer->ux_pipe; 1321 1322 DPRINTFN(15,("ohci_process_done: error cc=%d (%s)\n", 1323 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 1324 ohci_cc_strs[OHCI_TD_GET_CC(O32TOH(std->td.td_flags))])); 1325 1326 /* remove TDs */ 1327 for (p = std; p->xfer == xfer; p = n) { 1328 n = p->nexttd; 1329 ohci_free_std(sc, p); 1330 } 1331 1332 /* clear halt */ 1333 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1334 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1335 1336 if (cc == OHCI_CC_STALL) 1337 xfer->ux_status = USBD_STALLED; 1338 else 1339 xfer->ux_status = USBD_IOERROR; 1340 usb_transfer_complete(xfer); 1341 } 1342 } 1343 1344 #ifdef OHCI_DEBUG 1345 if (ohcidebug > 10) { 1346 DPRINTF(("ohci_softintr: ITD done:\n")); 1347 for (sitd = sidone; sitd; sitd = sitd->dnext) 1348 ohci_dump_itd(sc, sitd); 1349 } 1350 #endif 1351 1352 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1353 xfer = sitd->xfer; 1354 sitdnext = sitd->dnext; 1355 DPRINTFN(1, ("ohci_process_done: sitd=%p xfer=%p hcpriv=%p\n", 1356 sitd, xfer, xfer ? xfer->ux_hcpriv : 0)); 1357 if (xfer == NULL) 1358 continue; 1359 if (xfer->ux_status == USBD_CANCELLED || 1360 xfer->ux_status == USBD_TIMEOUT) { 1361 DPRINTF(("ohci_process_done: cancel/timeout %p\n", 1362 xfer)); 1363 /* Handled by abort routine. */ 1364 continue; 1365 } 1366 #ifdef DIAGNOSTIC 1367 if (sitd->isdone) 1368 printf("ohci_softintr: sitd=%p is done\n", sitd); 1369 sitd->isdone = 1; 1370 #endif 1371 if (sitd->flags & OHCI_CALL_DONE) { 1372 ohci_soft_itd_t *next; 1373 1374 opipe = (struct ohci_pipe *)xfer->ux_pipe; 1375 opipe->u.iso.inuse -= xfer->ux_nframes; 1376 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1377 bEndpointAddress); 1378 xfer->ux_status = USBD_NORMAL_COMPLETION; 1379 actlen = 0; 1380 for (i = 0, sitd = xfer->ux_hcpriv;; 1381 sitd = next) { 1382 next = sitd->nextitd; 1383 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1384 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1385 xfer->ux_status = USBD_IOERROR; 1386 /* For input, update frlengths with actual */ 1387 /* XXX anything necessary for output? */ 1388 if (uedir == UE_DIR_IN && 1389 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1390 iframes = OHCI_ITD_GET_FC(O32TOH( 1391 sitd->itd.itd_flags)); 1392 for (j = 0; j < iframes; i++, j++) { 1393 len = O16TOH(sitd-> 1394 itd.itd_offset[j]); 1395 if ((OHCI_ITD_PSW_GET_CC(len) & 1396 OHCI_CC_NOT_ACCESSED_MASK) 1397 == OHCI_CC_NOT_ACCESSED) 1398 len = 0; 1399 else 1400 len = OHCI_ITD_PSW_LENGTH(len); 1401 xfer->ux_frlengths[i] = len; 1402 actlen += len; 1403 } 1404 } 1405 if (sitd->flags & OHCI_CALL_DONE) 1406 break; 1407 ohci_free_sitd(sc, sitd); 1408 } 1409 ohci_free_sitd(sc, sitd); 1410 if (uedir == UE_DIR_IN && 1411 xfer->ux_status == USBD_NORMAL_COMPLETION) 1412 xfer->ux_actlen = actlen; 1413 xfer->ux_hcpriv = NULL; 1414 1415 usb_transfer_complete(xfer); 1416 } 1417 } 1418 1419 if (sc->sc_softwake) { 1420 sc->sc_softwake = 0; 1421 cv_broadcast(&sc->sc_softwake_cv); 1422 } 1423 1424 DPRINTFN(10,("ohci_softintr: done:\n")); 1425 } 1426 1427 void 1428 ohci_device_ctrl_done(usbd_xfer_handle xfer) 1429 { 1430 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1431 #ifdef DIAGNOSTIC 1432 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1433 #endif 1434 int len = UGETW(xfer->ux_request.wLength); 1435 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1436 1437 DPRINTFN(10,("ohci_device_ctrl_done: xfer=%p\n", xfer)); 1438 1439 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1440 1441 #ifdef DIAGNOSTIC 1442 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 1443 panic("ohci_device_ctrl_done: not a request"); 1444 } 1445 #endif 1446 if (len) 1447 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1448 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1449 usb_syncmem(&opipe->u.ctl.reqdma, 0, 1450 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1451 } 1452 1453 void 1454 ohci_device_intr_done(usbd_xfer_handle xfer) 1455 { 1456 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1457 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 1458 ohci_soft_ed_t *sed = opipe->sed; 1459 ohci_soft_td_t *data, *tail; 1460 int isread = 1461 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1462 1463 DPRINTFN(10,("ohci_device_intr_done: xfer=%p, actlen=%d\n", 1464 xfer, xfer->ux_actlen)); 1465 1466 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1467 1468 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1469 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1470 if (xfer->ux_pipe->up_repeat) { 1471 data = opipe->tail.td; 1472 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1473 if (tail == NULL) { 1474 xfer->ux_status = USBD_NOMEM; 1475 return; 1476 } 1477 tail->xfer = NULL; 1478 1479 data->td.td_flags = HTOO32( 1480 OHCI_TD_IN | OHCI_TD_NOCC | 1481 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1482 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1483 data->td.td_flags |= HTOO32(OHCI_TD_R); 1484 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1485 data->nexttd = tail; 1486 data->td.td_nexttd = HTOO32(tail->physaddr); 1487 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1488 xfer->ux_length - 1); 1489 data->len = xfer->ux_length; 1490 data->xfer = xfer; 1491 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1492 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1493 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1494 xfer->ux_hcpriv = data; 1495 xfer->ux_actlen = 0; 1496 1497 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1498 usb_syncmem(&sed->dma, 1499 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1500 sizeof(sed->ed.ed_tailp), 1501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1502 opipe->tail.td = tail; 1503 } 1504 } 1505 1506 void 1507 ohci_device_bulk_done(usbd_xfer_handle xfer) 1508 { 1509 #ifdef DIAGNOSTIC 1510 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1511 #endif 1512 int isread = 1513 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1514 1515 KASSERT(mutex_owned(&sc->sc_lock)); 1516 1517 DPRINTFN(10,("ohci_device_bulk_done: xfer=%p, actlen=%d\n", 1518 xfer, xfer->ux_actlen)); 1519 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1520 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1521 } 1522 1523 Static void 1524 ohci_rhsc_softint(void *arg) 1525 { 1526 ohci_softc_t *sc = arg; 1527 1528 mutex_enter(&sc->sc_lock); 1529 1530 ohci_rhsc(sc, sc->sc_intrxfer); 1531 1532 /* Do not allow RHSC interrupts > 1 per second */ 1533 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1534 1535 mutex_exit(&sc->sc_lock); 1536 } 1537 1538 void 1539 ohci_rhsc(ohci_softc_t *sc, usbd_xfer_handle xfer) 1540 { 1541 u_char *p; 1542 int i, m; 1543 int hstatus __unused; 1544 1545 KASSERT(mutex_owned(&sc->sc_lock)); 1546 1547 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1548 DPRINTF(("ohci_rhsc: sc=%p xfer=%p hstatus=0x%08x\n", 1549 sc, xfer, hstatus)); 1550 1551 if (xfer == NULL) { 1552 /* Just ignore the change. */ 1553 return; 1554 } 1555 1556 p = xfer->ux_buf; 1557 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1558 memset(p, 0, xfer->ux_length); 1559 for (i = 1; i <= m; i++) { 1560 /* Pick out CHANGE bits from the status reg. */ 1561 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1562 p[i/8] |= 1 << (i%8); 1563 } 1564 DPRINTF(("ohci_rhsc: change=0x%02x\n", *p)); 1565 xfer->ux_actlen = xfer->ux_length; 1566 xfer->ux_status = USBD_NORMAL_COMPLETION; 1567 1568 usb_transfer_complete(xfer); 1569 } 1570 1571 void 1572 ohci_root_intr_done(usbd_xfer_handle xfer) 1573 { 1574 } 1575 1576 /* 1577 * Wait here until controller claims to have an interrupt. 1578 * Then call ohci_intr and return. Use timeout to avoid waiting 1579 * too long. 1580 */ 1581 void 1582 ohci_waitintr(ohci_softc_t *sc, usbd_xfer_handle xfer) 1583 { 1584 int timo; 1585 uint32_t intrs; 1586 1587 mutex_enter(&sc->sc_lock); 1588 1589 xfer->ux_status = USBD_IN_PROGRESS; 1590 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1591 usb_delay_ms(&sc->sc_bus, 1); 1592 if (sc->sc_dying) 1593 break; 1594 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1595 DPRINTFN(15,("ohci_waitintr: 0x%04x\n", intrs)); 1596 #ifdef OHCI_DEBUG 1597 if (ohcidebug > 15) 1598 ohci_dumpregs(sc); 1599 #endif 1600 if (intrs) { 1601 mutex_spin_enter(&sc->sc_intr_lock); 1602 ohci_intr1(sc); 1603 mutex_spin_exit(&sc->sc_intr_lock); 1604 if (xfer->ux_status != USBD_IN_PROGRESS) 1605 goto done; 1606 } 1607 } 1608 1609 /* Timeout */ 1610 DPRINTF(("ohci_waitintr: timeout\n")); 1611 xfer->ux_status = USBD_TIMEOUT; 1612 usb_transfer_complete(xfer); 1613 1614 /* XXX should free TD */ 1615 1616 done: 1617 mutex_exit(&sc->sc_lock); 1618 } 1619 1620 void 1621 ohci_poll(struct usbd_bus *bus) 1622 { 1623 ohci_softc_t *sc = bus->ub_hcpriv; 1624 #ifdef OHCI_DEBUG 1625 static int last; 1626 int new; 1627 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1628 if (new != last) { 1629 DPRINTFN(10,("ohci_poll: intrs=0x%04x\n", new)); 1630 last = new; 1631 } 1632 #endif 1633 sc->sc_eintrs |= OHCI_WDH; 1634 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1635 mutex_spin_enter(&sc->sc_intr_lock); 1636 ohci_intr1(sc); 1637 mutex_spin_exit(&sc->sc_intr_lock); 1638 } 1639 } 1640 1641 usbd_status 1642 ohci_device_request(usbd_xfer_handle xfer) 1643 { 1644 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 1645 usb_device_request_t *req = &xfer->ux_request; 1646 usbd_device_handle dev = opipe->pipe.up_dev; 1647 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1648 ohci_soft_td_t *setup, *stat, *next, *tail; 1649 ohci_soft_ed_t *sed; 1650 int isread; 1651 int len; 1652 usbd_status err; 1653 1654 KASSERT(mutex_owned(&sc->sc_lock)); 1655 1656 isread = req->bmRequestType & UT_READ; 1657 len = UGETW(req->wLength); 1658 1659 DPRINTFN(3,("ohci_device_control type=0x%02x, request=0x%02x, " 1660 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 1661 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1662 UGETW(req->wIndex), len, dev->ud_addr, 1663 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)); 1664 1665 setup = opipe->tail.td; 1666 stat = ohci_alloc_std(sc); 1667 if (stat == NULL) { 1668 err = USBD_NOMEM; 1669 goto bad1; 1670 } 1671 tail = ohci_alloc_std(sc); 1672 if (tail == NULL) { 1673 err = USBD_NOMEM; 1674 goto bad2; 1675 } 1676 tail->xfer = NULL; 1677 1678 sed = opipe->sed; 1679 opipe->u.ctl.length = len; 1680 1681 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 1682 "address ED %d pipe %d\n", 1683 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 1684 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 1685 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 1686 "MPL ED %d pipe %d\n", 1687 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 1688 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 1689 1690 next = stat; 1691 1692 /* Set up data transaction */ 1693 if (len != 0) { 1694 ohci_soft_td_t *std = stat; 1695 1696 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1697 std, &stat); 1698 if (err) { 1699 /* stat is unchanged if error */ 1700 goto bad3; 1701 } 1702 stat = stat->nexttd; /* point at free TD */ 1703 1704 /* Start toggle at 1 and then use the carried toggle. */ 1705 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1706 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1707 usb_syncmem(&std->dma, 1708 std->offs + offsetof(ohci_td_t, td_flags), 1709 sizeof(std->td.td_flags), 1710 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1711 } 1712 1713 memcpy(KERNADDR(&opipe->u.ctl.reqdma, 0), req, sizeof *req); 1714 usb_syncmem(&opipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 1715 1716 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1717 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1718 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->u.ctl.reqdma, 0)); 1719 setup->nexttd = next; 1720 setup->td.td_nexttd = HTOO32(next->physaddr); 1721 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof *req - 1); 1722 setup->len = 0; 1723 setup->xfer = xfer; 1724 setup->flags = 0; 1725 xfer->ux_hcpriv = setup; 1726 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1727 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1728 1729 stat->td.td_flags = HTOO32( 1730 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1731 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1732 stat->td.td_cbp = 0; 1733 stat->nexttd = tail; 1734 stat->td.td_nexttd = HTOO32(tail->physaddr); 1735 stat->td.td_be = 0; 1736 stat->flags = OHCI_CALL_DONE; 1737 stat->len = 0; 1738 stat->xfer = xfer; 1739 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1740 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1741 1742 #ifdef OHCI_DEBUG 1743 if (ohcidebug > 5) { 1744 DPRINTF(("ohci_device_request:\n")); 1745 ohci_dump_ed(sc, sed); 1746 ohci_dump_tds(sc, setup); 1747 } 1748 #endif 1749 1750 /* Insert ED in schedule */ 1751 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1752 usb_syncmem(&sed->dma, 1753 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1754 sizeof(sed->ed.ed_tailp), 1755 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1756 opipe->tail.td = tail; 1757 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1758 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 1759 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 1760 ohci_timeout, xfer); 1761 } 1762 1763 #ifdef OHCI_DEBUG 1764 if (ohcidebug > 20) { 1765 delay(10000); 1766 DPRINTF(("ohci_device_request: status=%x\n", 1767 OREAD4(sc, OHCI_COMMAND_STATUS))); 1768 ohci_dumpregs(sc); 1769 printf("ctrl head:\n"); 1770 ohci_dump_ed(sc, sc->sc_ctrl_head); 1771 printf("sed:\n"); 1772 ohci_dump_ed(sc, sed); 1773 ohci_dump_tds(sc, setup); 1774 } 1775 #endif 1776 1777 return USBD_NORMAL_COMPLETION; 1778 1779 bad3: 1780 ohci_free_std(sc, tail); 1781 bad2: 1782 ohci_free_std(sc, stat); 1783 bad1: 1784 return err; 1785 } 1786 1787 /* 1788 * Add an ED to the schedule. Called with USB lock held. 1789 */ 1790 Static void 1791 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1792 { 1793 DPRINTFN(8,("ohci_add_ed: sed=%p head=%p\n", sed, head)); 1794 1795 KASSERT(mutex_owned(&sc->sc_lock)); 1796 1797 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1798 sizeof(head->ed.ed_nexted), 1799 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1800 sed->next = head->next; 1801 sed->ed.ed_nexted = head->ed.ed_nexted; 1802 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1803 sizeof(sed->ed.ed_nexted), 1804 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1805 head->next = sed; 1806 head->ed.ed_nexted = HTOO32(sed->physaddr); 1807 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1808 sizeof(head->ed.ed_nexted), 1809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1810 } 1811 1812 /* 1813 * Remove an ED from the schedule. Called with USB lock held. 1814 */ 1815 Static void 1816 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1817 { 1818 ohci_soft_ed_t *p; 1819 1820 KASSERT(mutex_owned(&sc->sc_lock)); 1821 1822 /* XXX */ 1823 for (p = head; p != NULL && p->next != sed; p = p->next) 1824 ; 1825 if (p == NULL) 1826 panic("ohci_rem_ed: ED not found"); 1827 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1828 sizeof(sed->ed.ed_nexted), 1829 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1830 p->next = sed->next; 1831 p->ed.ed_nexted = sed->ed.ed_nexted; 1832 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1833 sizeof(p->ed.ed_nexted), 1834 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1835 } 1836 1837 /* 1838 * When a transfer is completed the TD is added to the done queue by 1839 * the host controller. This queue is the processed by software. 1840 * Unfortunately the queue contains the physical address of the TD 1841 * and we have no simple way to translate this back to a kernel address. 1842 * To make the translation possible (and fast) we use a hash table of 1843 * TDs currently in the schedule. The physical address is used as the 1844 * hash value. 1845 */ 1846 1847 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1848 /* Called with USB lock held. */ 1849 void 1850 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1851 { 1852 int h = HASH(std->physaddr); 1853 1854 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1855 1856 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1857 } 1858 1859 /* Called with USB lock held. */ 1860 void 1861 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1862 { 1863 1864 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1865 1866 LIST_REMOVE(std, hnext); 1867 } 1868 1869 ohci_soft_td_t * 1870 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1871 { 1872 int h = HASH(a); 1873 ohci_soft_td_t *std; 1874 1875 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1876 std != NULL; 1877 std = LIST_NEXT(std, hnext)) 1878 if (std->physaddr == a) 1879 return std; 1880 return NULL; 1881 } 1882 1883 /* Called with USB lock held. */ 1884 void 1885 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1886 { 1887 int h = HASH(sitd->physaddr); 1888 1889 KASSERT(mutex_owned(&sc->sc_lock)); 1890 1891 DPRINTFN(10,("ohci_hash_add_itd: sitd=%p physaddr=0x%08lx\n", 1892 sitd, (u_long)sitd->physaddr)); 1893 1894 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1895 } 1896 1897 /* Called with USB lock held. */ 1898 void 1899 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1900 { 1901 1902 KASSERT(mutex_owned(&sc->sc_lock)); 1903 1904 DPRINTFN(10,("ohci_hash_rem_itd: sitd=%p physaddr=0x%08lx\n", 1905 sitd, (u_long)sitd->physaddr)); 1906 1907 LIST_REMOVE(sitd, hnext); 1908 } 1909 1910 ohci_soft_itd_t * 1911 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1912 { 1913 int h = HASH(a); 1914 ohci_soft_itd_t *sitd; 1915 1916 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1917 sitd != NULL; 1918 sitd = LIST_NEXT(sitd, hnext)) 1919 if (sitd->physaddr == a) 1920 return sitd; 1921 return NULL; 1922 } 1923 1924 void 1925 ohci_timeout(void *addr) 1926 { 1927 struct ohci_xfer *oxfer = addr; 1928 struct ohci_pipe *opipe = (struct ohci_pipe *)oxfer->xfer.ux_pipe; 1929 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 1930 1931 DPRINTF(("ohci_timeout: oxfer=%p\n", oxfer)); 1932 1933 if (sc->sc_dying) { 1934 mutex_enter(&sc->sc_lock); 1935 ohci_abort_xfer(&oxfer->xfer, USBD_TIMEOUT); 1936 mutex_exit(&sc->sc_lock); 1937 return; 1938 } 1939 1940 /* Execute the abort in a process context. */ 1941 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1942 USB_TASKQ_MPSAFE); 1943 usb_add_task(oxfer->xfer.ux_pipe->up_dev, &oxfer->abort_task, 1944 USB_TASKQ_HC); 1945 } 1946 1947 void 1948 ohci_timeout_task(void *addr) 1949 { 1950 usbd_xfer_handle xfer = addr; 1951 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1952 1953 DPRINTF(("ohci_timeout_task: xfer=%p\n", xfer)); 1954 1955 mutex_enter(&sc->sc_lock); 1956 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1957 mutex_exit(&sc->sc_lock); 1958 } 1959 1960 #ifdef OHCI_DEBUG 1961 void 1962 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1963 { 1964 for (; std; std = std->nexttd) 1965 ohci_dump_td(sc, std); 1966 } 1967 1968 void 1969 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1970 { 1971 char sbuf[128]; 1972 1973 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1975 snprintb(sbuf, sizeof(sbuf), 1976 "\177\20" 1977 "b\22R\0" 1978 "f\23\02DP\0" 1979 "=\x0" "setup\0" 1980 "=\x1" "out\0" 1981 "=\x2" "in\0" 1982 "=\x3" "reserved\0" 1983 "f\25\03DI\0" 1984 "=\x07" "none\0" 1985 "f\30\02T\0" 1986 "=\x0" "carry\0" 1987 "=\x1" "carry\0" 1988 "=\x2" "0\0" 1989 "=\x3" "1\0" 1990 "f\32\02EC\0" 1991 "f\34\04CC\0", 1992 (uint32_t)O32TOH(std->td.td_flags)); 1993 printf("TD(%p) at %08lx:\n\tflags=%s\n\tcbp=0x%08lx nexttd=0x%08lx be=0x%08lx\n", 1994 std, (u_long)std->physaddr, sbuf, 1995 (u_long)O32TOH(std->td.td_cbp), 1996 (u_long)O32TOH(std->td.td_nexttd), 1997 (u_long)O32TOH(std->td.td_be)); 1998 } 1999 2000 void 2001 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2002 { 2003 int i; 2004 2005 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2006 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2007 printf("ITD(%p) at %08lx: sf=%d di=%d fc=%d cc=%d\n" 2008 "bp0=0x%08lx next=0x%08lx be=0x%08lx\n", 2009 sitd, (u_long)sitd->physaddr, 2010 OHCI_ITD_GET_SF(O32TOH(sitd->itd.itd_flags)), 2011 OHCI_ITD_GET_DI(O32TOH(sitd->itd.itd_flags)), 2012 OHCI_ITD_GET_FC(O32TOH(sitd->itd.itd_flags)), 2013 OHCI_ITD_GET_CC(O32TOH(sitd->itd.itd_flags)), 2014 (u_long)O32TOH(sitd->itd.itd_bp0), 2015 (u_long)O32TOH(sitd->itd.itd_nextitd), 2016 (u_long)O32TOH(sitd->itd.itd_be)); 2017 for (i = 0; i < OHCI_ITD_NOFFSET; i++) 2018 printf("offs[%d]=0x%04x ", i, 2019 (u_int)O16TOH(sitd->itd.itd_offset[i])); 2020 printf("\n"); 2021 } 2022 2023 void 2024 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2025 { 2026 for (; sitd; sitd = sitd->nextitd) 2027 ohci_dump_itd(sc, sitd); 2028 } 2029 2030 void 2031 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2032 { 2033 char sbuf[128], sbuf2[128]; 2034 2035 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2037 snprintb(sbuf, sizeof(sbuf), 2038 "\20\14OUT\15IN\16LOWSPEED\17SKIP\20ISO", 2039 (uint32_t)O32TOH(sed->ed.ed_flags)); 2040 snprintb(sbuf2, sizeof(sbuf2), "\20\1HALT\2CARRY", 2041 (uint32_t)O32TOH(sed->ed.ed_headp)); 2042 2043 printf("ED(%p) at 0x%08lx: addr=%d endpt=%d maxp=%d flags=%s\ntailp=0x%08lx " 2044 "headflags=%s headp=0x%08lx nexted=0x%08lx\n", 2045 sed, (u_long)sed->physaddr, 2046 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), 2047 OHCI_ED_GET_EN(O32TOH(sed->ed.ed_flags)), 2048 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), sbuf, 2049 (u_long)O32TOH(sed->ed.ed_tailp), sbuf2, 2050 (u_long)O32TOH(sed->ed.ed_headp), 2051 (u_long)O32TOH(sed->ed.ed_nexted)); 2052 } 2053 #endif 2054 2055 usbd_status 2056 ohci_open(usbd_pipe_handle pipe) 2057 { 2058 usbd_device_handle dev = pipe->up_dev; 2059 struct usbd_bus *bus = dev->ud_bus; 2060 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2061 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2062 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2063 uint8_t addr = dev->ud_addr; 2064 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2065 ohci_soft_ed_t *sed; 2066 ohci_soft_td_t *std; 2067 ohci_soft_itd_t *sitd; 2068 ohci_physaddr_t tdphys; 2069 uint32_t fmt; 2070 usbd_status err = USBD_NOMEM; 2071 int ival; 2072 2073 DPRINTFN(1, ("ohci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 2074 pipe, addr, ed->bEndpointAddress, bus->ub_rhaddr)); 2075 2076 if (sc->sc_dying) { 2077 return USBD_IOERROR; 2078 } 2079 2080 std = NULL; 2081 sed = NULL; 2082 2083 if (addr == bus->ub_rhaddr) { 2084 switch (ed->bEndpointAddress) { 2085 case USB_CONTROL_ENDPOINT: 2086 pipe->up_methods = &roothub_ctrl_methods; 2087 break; 2088 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2089 pipe->up_methods = &ohci_root_intr_methods; 2090 break; 2091 default: 2092 err = USBD_INVAL; 2093 goto bad; 2094 } 2095 } else { 2096 sed = ohci_alloc_sed(sc); 2097 if (sed == NULL) 2098 goto bad; 2099 opipe->sed = sed; 2100 if (xfertype == UE_ISOCHRONOUS) { 2101 mutex_enter(&sc->sc_lock); 2102 sitd = ohci_alloc_sitd(sc); 2103 mutex_exit(&sc->sc_lock); 2104 if (sitd == NULL) 2105 goto bad; 2106 2107 opipe->tail.itd = sitd; 2108 tdphys = sitd->physaddr; 2109 fmt = OHCI_ED_FORMAT_ISO; 2110 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2111 fmt |= OHCI_ED_DIR_IN; 2112 else 2113 fmt |= OHCI_ED_DIR_OUT; 2114 } else { 2115 mutex_enter(&sc->sc_lock); 2116 std = ohci_alloc_std(sc); 2117 mutex_exit(&sc->sc_lock); 2118 if (std == NULL) 2119 goto bad; 2120 2121 opipe->tail.td = std; 2122 tdphys = std->physaddr; 2123 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2124 } 2125 sed->ed.ed_flags = HTOO32( 2126 OHCI_ED_SET_FA(addr) | 2127 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2128 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2129 fmt | 2130 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2131 sed->ed.ed_headp = HTOO32(tdphys | 2132 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2133 sed->ed.ed_tailp = HTOO32(tdphys); 2134 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2135 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2136 2137 switch (xfertype) { 2138 case UE_CONTROL: 2139 pipe->up_methods = &ohci_device_ctrl_methods; 2140 err = usb_allocmem(&sc->sc_bus, 2141 sizeof(usb_device_request_t), 2142 0, &opipe->u.ctl.reqdma); 2143 if (err) 2144 goto bad; 2145 mutex_enter(&sc->sc_lock); 2146 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2147 mutex_exit(&sc->sc_lock); 2148 break; 2149 case UE_INTERRUPT: 2150 pipe->up_methods = &ohci_device_intr_methods; 2151 ival = pipe->up_interval; 2152 if (ival == USBD_DEFAULT_INTERVAL) 2153 ival = ed->bInterval; 2154 err = ohci_device_setintr(sc, opipe, ival); 2155 if (err) 2156 goto bad; 2157 break; 2158 case UE_ISOCHRONOUS: 2159 pipe->up_methods = &ohci_device_isoc_methods; 2160 return ohci_setup_isoc(pipe); 2161 case UE_BULK: 2162 pipe->up_methods = &ohci_device_bulk_methods; 2163 mutex_enter(&sc->sc_lock); 2164 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2165 mutex_exit(&sc->sc_lock); 2166 break; 2167 } 2168 } 2169 2170 return USBD_NORMAL_COMPLETION; 2171 2172 bad: 2173 if (std != NULL) { 2174 mutex_enter(&sc->sc_lock); 2175 ohci_free_std(sc, std); 2176 mutex_exit(&sc->sc_lock); 2177 } 2178 if (sed != NULL) 2179 ohci_free_sed(sc, sed); 2180 return err; 2181 2182 } 2183 2184 /* 2185 * Close a reqular pipe. 2186 * Assumes that there are no pending transactions. 2187 */ 2188 void 2189 ohci_close_pipe(usbd_pipe_handle pipe, ohci_soft_ed_t *head) 2190 { 2191 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2192 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2193 ohci_soft_ed_t *sed = opipe->sed; 2194 2195 KASSERT(mutex_owned(&sc->sc_lock)); 2196 2197 #ifdef DIAGNOSTIC 2198 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2199 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2200 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2201 ohci_soft_td_t *std; 2202 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2203 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2204 "tl=0x%x pipe=%p, std=%p\n", sed, 2205 (int)O32TOH(sed->ed.ed_headp), 2206 (int)O32TOH(sed->ed.ed_tailp), 2207 pipe, std); 2208 #ifdef OHCI_DEBUG 2209 usbd_dump_pipe(&opipe->pipe); 2210 ohci_dump_ed(sc, sed); 2211 if (std) 2212 ohci_dump_td(sc, std); 2213 #endif 2214 usb_delay_ms(&sc->sc_bus, 2); 2215 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2216 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2217 printf("ohci_close_pipe: pipe still not empty\n"); 2218 } 2219 #endif 2220 ohci_rem_ed(sc, sed, head); 2221 /* Make sure the host controller is not touching this ED */ 2222 usb_delay_ms(&sc->sc_bus, 1); 2223 pipe->up_endpoint->ue_toggle = 2224 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2225 ohci_free_sed(sc, opipe->sed); 2226 } 2227 2228 /* 2229 * Abort a device request. 2230 * If this routine is called at splusb() it guarantees that the request 2231 * will be removed from the hardware scheduling and that the callback 2232 * for it will be called with USBD_CANCELLED status. 2233 * It's impossible to guarantee that the requested transfer will not 2234 * have happened since the hardware runs concurrently. 2235 * If the transaction has already happened we rely on the ordinary 2236 * interrupt processing to process it. 2237 * XXX This is most probably wrong. 2238 * XXXMRG this doesn't make sense anymore. 2239 */ 2240 void 2241 ohci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2242 { 2243 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 2244 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 2245 ohci_soft_ed_t *sed = opipe->sed; 2246 ohci_soft_td_t *p, *n; 2247 ohci_physaddr_t headp; 2248 int hit; 2249 int wake; 2250 2251 DPRINTF(("ohci_abort_xfer: xfer=%p pipe=%p sed=%p\n", xfer, opipe,sed)); 2252 2253 KASSERT(mutex_owned(&sc->sc_lock)); 2254 ASSERT_SLEEPABLE(); 2255 2256 if (sc->sc_dying) { 2257 /* If we're dying, just do the software part. */ 2258 xfer->ux_status = status; /* make software ignore it */ 2259 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2260 usb_transfer_complete(xfer); 2261 return; 2262 } 2263 2264 /* 2265 * If an abort is already in progress then just wait for it to 2266 * complete and return. 2267 */ 2268 if (xfer->ux_hcflags & UXFER_ABORTING) { 2269 DPRINTFN(2, ("ohci_abort_xfer: already aborting\n")); 2270 #ifdef DIAGNOSTIC 2271 if (status == USBD_TIMEOUT) 2272 printf("%s: TIMEOUT while aborting\n", __func__); 2273 #endif 2274 /* Override the status which might be USBD_TIMEOUT. */ 2275 xfer->ux_status = status; 2276 DPRINTFN(2, ("ohci_abort_xfer: waiting for abort to finish\n")); 2277 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2278 while (xfer->ux_hcflags & UXFER_ABORTING) 2279 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2280 goto done; 2281 } 2282 xfer->ux_hcflags |= UXFER_ABORTING; 2283 2284 /* 2285 * Step 1: Make interrupt routine and hardware ignore xfer. 2286 */ 2287 xfer->ux_status = status; /* make software ignore it */ 2288 callout_stop(&xfer->ux_callout); 2289 DPRINTFN(1,("ohci_abort_xfer: stop ed=%p\n", sed)); 2290 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2291 sizeof(sed->ed.ed_flags), 2292 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2293 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2294 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2295 sizeof(sed->ed.ed_flags), 2296 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2297 2298 /* 2299 * Step 2: Wait until we know hardware has finished any possible 2300 * use of the xfer. Also make sure the soft interrupt routine 2301 * has run. 2302 */ 2303 /* Hardware finishes in 1ms */ 2304 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2305 sc->sc_softwake = 1; 2306 usb_schedsoftintr(&sc->sc_bus); 2307 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2308 2309 /* 2310 * Step 3: Remove any vestiges of the xfer from the hardware. 2311 * The complication here is that the hardware may have executed 2312 * beyond the xfer we're trying to abort. So as we're scanning 2313 * the TDs of this xfer we check if the hardware points to 2314 * any of them. 2315 */ 2316 p = xfer->ux_hcpriv; 2317 #ifdef DIAGNOSTIC 2318 if (p == NULL) { 2319 xfer->ux_hcflags &= ~UXFER_ABORTING; /* XXX */ 2320 printf("ohci_abort_xfer: hcpriv is NULL\n"); 2321 goto done; 2322 } 2323 #endif 2324 #ifdef OHCI_DEBUG 2325 if (ohcidebug > 1) { 2326 DPRINTF(("ohci_abort_xfer: sed=\n")); 2327 ohci_dump_ed(sc, sed); 2328 ohci_dump_tds(sc, p); 2329 } 2330 #endif 2331 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2332 hit = 0; 2333 for (; p->xfer == xfer; p = n) { 2334 hit |= headp == p->physaddr; 2335 n = p->nexttd; 2336 ohci_free_std(sc, p); 2337 } 2338 /* Zap headp register if hardware pointed inside the xfer. */ 2339 if (hit) { 2340 DPRINTFN(1,("ohci_abort_xfer: set hd=0x%08x, tl=0x%08x\n", 2341 (int)p->physaddr, (int)O32TOH(sed->ed.ed_tailp))); 2342 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2343 usb_syncmem(&sed->dma, 2344 sed->offs + offsetof(ohci_ed_t, ed_headp), 2345 sizeof(sed->ed.ed_headp), 2346 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2347 } else { 2348 DPRINTFN(1,("ohci_abort_xfer: no hit\n")); 2349 } 2350 2351 /* 2352 * Step 4: Turn on hardware again. 2353 */ 2354 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2355 sizeof(sed->ed.ed_flags), 2356 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2357 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2358 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2359 sizeof(sed->ed.ed_flags), 2360 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2361 2362 /* 2363 * Step 5: Execute callback. 2364 */ 2365 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2366 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2367 usb_transfer_complete(xfer); 2368 if (wake) 2369 cv_broadcast(&xfer->ux_hccv); 2370 2371 done: 2372 KASSERT(mutex_owned(&sc->sc_lock)); 2373 } 2374 2375 /* 2376 * Data structures and routines to emulate the root hub. 2377 */ 2378 Static int 2379 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2380 void *buf, int buflen) 2381 { 2382 ohci_softc_t *sc = bus->ub_hcpriv; 2383 usb_port_status_t ps; 2384 uint16_t len, value, index; 2385 int l, totlen = 0; 2386 int port, i; 2387 uint32_t v; 2388 2389 if (sc->sc_dying) 2390 return -1; 2391 2392 DPRINTFN(4,("%s: type=0x%02x request=%02x\n", __func__, 2393 req->bmRequestType, req->bRequest)); 2394 2395 len = UGETW(req->wLength); 2396 value = UGETW(req->wValue); 2397 index = UGETW(req->wIndex); 2398 2399 #define C(x,y) ((x) | ((y) << 8)) 2400 switch (C(req->bRequest, req->bmRequestType)) { 2401 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2402 DPRINTFN(8,("%s: wValue=0x%04x\n", __func__, value)); 2403 if (len == 0) 2404 break; 2405 switch (value) { 2406 case C(0, UDESC_DEVICE): { 2407 usb_device_descriptor_t devd; 2408 2409 totlen = min(buflen, sizeof(devd)); 2410 memcpy(&devd, buf, totlen); 2411 USETW(devd.idVendor, sc->sc_id_vendor); 2412 memcpy(buf, &devd, totlen); 2413 break; 2414 } 2415 case C(1, UDESC_STRING): 2416 #define sd ((usb_string_descriptor_t *)buf) 2417 /* Vendor */ 2418 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2419 break; 2420 case C(2, UDESC_STRING): 2421 /* Product */ 2422 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2423 break; 2424 #undef sd 2425 default: 2426 /* default from usbroothub */ 2427 return buflen; 2428 } 2429 break; 2430 2431 /* Hub requests */ 2432 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2433 break; 2434 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2435 DPRINTFN(8, ("%s: UR_CLEAR_PORT_FEATURE " 2436 "port=%d feature=%d\n", __func__, 2437 index, value)); 2438 if (index < 1 || index > sc->sc_noport) { 2439 return -1; 2440 } 2441 port = OHCI_RH_PORT_STATUS(index); 2442 switch(value) { 2443 case UHF_PORT_ENABLE: 2444 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2445 break; 2446 case UHF_PORT_SUSPEND: 2447 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2448 break; 2449 case UHF_PORT_POWER: 2450 /* Yes, writing to the LOW_SPEED bit clears power. */ 2451 OWRITE4(sc, port, UPS_LOW_SPEED); 2452 break; 2453 case UHF_C_PORT_CONNECTION: 2454 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2455 break; 2456 case UHF_C_PORT_ENABLE: 2457 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2458 break; 2459 case UHF_C_PORT_SUSPEND: 2460 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2461 break; 2462 case UHF_C_PORT_OVER_CURRENT: 2463 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2464 break; 2465 case UHF_C_PORT_RESET: 2466 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2467 break; 2468 default: 2469 return -1; 2470 } 2471 switch(value) { 2472 case UHF_C_PORT_CONNECTION: 2473 case UHF_C_PORT_ENABLE: 2474 case UHF_C_PORT_SUSPEND: 2475 case UHF_C_PORT_OVER_CURRENT: 2476 case UHF_C_PORT_RESET: 2477 /* Enable RHSC interrupt if condition is cleared. */ 2478 if ((OREAD4(sc, port) >> 16) == 0) 2479 ohci_rhsc_enable(sc); 2480 break; 2481 default: 2482 break; 2483 } 2484 break; 2485 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2486 if (len == 0) 2487 break; 2488 if ((value & 0xff) != 0) { 2489 return -1; 2490 } 2491 usb_hub_descriptor_t hubd; 2492 2493 totlen = min(buflen, sizeof(hubd)); 2494 memcpy(&hubd, buf, totlen); 2495 2496 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2497 hubd.bNbrPorts = sc->sc_noport; 2498 USETW(hubd.wHubCharacteristics, 2499 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2500 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2501 /* XXX overcurrent */ 2502 ); 2503 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2504 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2505 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2506 hubd.DeviceRemovable[i++] = (uint8_t)v; 2507 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2508 totlen = min(totlen, hubd.bDescLength); 2509 memcpy(buf, &hubd, totlen); 2510 break; 2511 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2512 if (len != 4) { 2513 return -1; 2514 } 2515 memset(buf, 0, len); /* ? XXX */ 2516 totlen = len; 2517 break; 2518 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2519 DPRINTFN(8,("%s: get port status i=%d\n", __func__, 2520 index)); 2521 if (index < 1 || index > sc->sc_noport) { 2522 return -1; 2523 } 2524 if (len != 4) { 2525 return -1; 2526 } 2527 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2528 DPRINTFN(8,("%s: port status=0x%04x\n", __func__, 2529 v)); 2530 USETW(ps.wPortStatus, v); 2531 USETW(ps.wPortChange, v >> 16); 2532 totlen = min(len, sizeof(ps)); 2533 memcpy(buf, &ps, totlen); 2534 break; 2535 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2536 return -1; 2537 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2538 break; 2539 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2540 if (index < 1 || index > sc->sc_noport) { 2541 return -1; 2542 } 2543 port = OHCI_RH_PORT_STATUS(index); 2544 switch(value) { 2545 case UHF_PORT_ENABLE: 2546 OWRITE4(sc, port, UPS_PORT_ENABLED); 2547 break; 2548 case UHF_PORT_SUSPEND: 2549 OWRITE4(sc, port, UPS_SUSPEND); 2550 break; 2551 case UHF_PORT_RESET: 2552 DPRINTFN(5,("%s: reset port %d\n", __func__, 2553 index)); 2554 OWRITE4(sc, port, UPS_RESET); 2555 for (i = 0; i < 5; i++) { 2556 usb_delay_ms(&sc->sc_bus, 2557 USB_PORT_ROOT_RESET_DELAY); 2558 if (sc->sc_dying) { 2559 return -1; 2560 } 2561 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2562 break; 2563 } 2564 DPRINTFN(8,("ohci port %d reset, status = 0x%04x\n", 2565 index, OREAD4(sc, port))); 2566 break; 2567 case UHF_PORT_POWER: 2568 DPRINTFN(2,("%s: set port power " 2569 "%d\n", __func__, index)); 2570 OWRITE4(sc, port, UPS_PORT_POWER); 2571 break; 2572 default: 2573 return -1; 2574 } 2575 break; 2576 default: 2577 /* default from usbroothub */ 2578 return buflen; 2579 } 2580 2581 return totlen; 2582 } 2583 2584 Static usbd_status 2585 ohci_root_intr_transfer(usbd_xfer_handle xfer) 2586 { 2587 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2588 usbd_status err; 2589 2590 /* Insert last in queue. */ 2591 mutex_enter(&sc->sc_lock); 2592 err = usb_insert_transfer(xfer); 2593 mutex_exit(&sc->sc_lock); 2594 if (err) 2595 return err; 2596 2597 /* Pipe isn't running, start first */ 2598 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2599 } 2600 2601 Static usbd_status 2602 ohci_root_intr_start(usbd_xfer_handle xfer) 2603 { 2604 usbd_pipe_handle pipe = xfer->ux_pipe; 2605 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2606 2607 if (sc->sc_dying) 2608 return USBD_IOERROR; 2609 2610 mutex_enter(&sc->sc_lock); 2611 KASSERT(sc->sc_intrxfer == NULL); 2612 sc->sc_intrxfer = xfer; 2613 mutex_exit(&sc->sc_lock); 2614 2615 return USBD_IN_PROGRESS; 2616 } 2617 2618 /* Abort a root interrupt request. */ 2619 Static void 2620 ohci_root_intr_abort(usbd_xfer_handle xfer) 2621 { 2622 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2623 2624 KASSERT(mutex_owned(&sc->sc_lock)); 2625 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2626 2627 sc->sc_intrxfer = NULL; 2628 2629 xfer->ux_status = USBD_CANCELLED; 2630 usb_transfer_complete(xfer); 2631 } 2632 2633 /* Close the root pipe. */ 2634 Static void 2635 ohci_root_intr_close(usbd_pipe_handle pipe) 2636 { 2637 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2638 2639 KASSERT(mutex_owned(&sc->sc_lock)); 2640 2641 DPRINTF(("ohci_root_intr_close\n")); 2642 2643 sc->sc_intrxfer = NULL; 2644 } 2645 2646 /************************/ 2647 2648 Static usbd_status 2649 ohci_device_ctrl_transfer(usbd_xfer_handle xfer) 2650 { 2651 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2652 usbd_status err; 2653 2654 /* Insert last in queue. */ 2655 mutex_enter(&sc->sc_lock); 2656 err = usb_insert_transfer(xfer); 2657 mutex_exit(&sc->sc_lock); 2658 if (err) 2659 return err; 2660 2661 /* Pipe isn't running, start first */ 2662 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2663 } 2664 2665 Static usbd_status 2666 ohci_device_ctrl_start(usbd_xfer_handle xfer) 2667 { 2668 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2669 usbd_status err; 2670 2671 if (sc->sc_dying) 2672 return USBD_IOERROR; 2673 2674 #ifdef DIAGNOSTIC 2675 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 2676 /* XXX panic */ 2677 printf("ohci_device_ctrl_transfer: not a request\n"); 2678 return USBD_INVAL; 2679 } 2680 #endif 2681 2682 mutex_enter(&sc->sc_lock); 2683 err = ohci_device_request(xfer); 2684 mutex_exit(&sc->sc_lock); 2685 if (err) 2686 return err; 2687 2688 if (sc->sc_bus.ub_usepolling) 2689 ohci_waitintr(sc, xfer); 2690 return USBD_IN_PROGRESS; 2691 } 2692 2693 /* Abort a device control request. */ 2694 Static void 2695 ohci_device_ctrl_abort(usbd_xfer_handle xfer) 2696 { 2697 #ifdef DIAGNOSTIC 2698 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2699 #endif 2700 2701 KASSERT(mutex_owned(&sc->sc_lock)); 2702 2703 DPRINTF(("ohci_device_ctrl_abort: xfer=%p\n", xfer)); 2704 ohci_abort_xfer(xfer, USBD_CANCELLED); 2705 } 2706 2707 /* Close a device control pipe. */ 2708 Static void 2709 ohci_device_ctrl_close(usbd_pipe_handle pipe) 2710 { 2711 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2712 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2713 2714 KASSERT(mutex_owned(&sc->sc_lock)); 2715 2716 DPRINTF(("ohci_device_ctrl_close: pipe=%p\n", pipe)); 2717 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2718 ohci_free_std(sc, opipe->tail.td); 2719 } 2720 2721 /************************/ 2722 2723 Static void 2724 ohci_device_clear_toggle(usbd_pipe_handle pipe) 2725 { 2726 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2727 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2728 2729 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2730 } 2731 2732 Static void 2733 ohci_noop(usbd_pipe_handle pipe) 2734 { 2735 } 2736 2737 Static usbd_status 2738 ohci_device_bulk_transfer(usbd_xfer_handle xfer) 2739 { 2740 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2741 usbd_status err; 2742 2743 /* Insert last in queue. */ 2744 mutex_enter(&sc->sc_lock); 2745 err = usb_insert_transfer(xfer); 2746 mutex_exit(&sc->sc_lock); 2747 if (err) 2748 return err; 2749 2750 /* Pipe isn't running, start first */ 2751 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2752 } 2753 2754 Static usbd_status 2755 ohci_device_bulk_start(usbd_xfer_handle xfer) 2756 { 2757 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 2758 usbd_device_handle dev = opipe->pipe.up_dev; 2759 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2760 int addr = dev->ud_addr; 2761 ohci_soft_td_t *data, *tail, *tdp; 2762 ohci_soft_ed_t *sed; 2763 int len, isread, endpt; 2764 usbd_status err; 2765 2766 if (sc->sc_dying) 2767 return USBD_IOERROR; 2768 2769 #ifdef DIAGNOSTIC 2770 if (xfer->ux_rqflags & URQ_REQUEST) { 2771 /* XXX panic */ 2772 printf("ohci_device_bulk_start: a request\n"); 2773 return USBD_INVAL; 2774 } 2775 #endif 2776 2777 mutex_enter(&sc->sc_lock); 2778 2779 len = xfer->ux_length; 2780 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2781 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2782 sed = opipe->sed; 2783 2784 DPRINTFN(4,("ohci_device_bulk_start: xfer=%p len=%d isread=%d " 2785 "flags=%d endpt=%d\n", xfer, len, isread, xfer->ux_flags, 2786 endpt)); 2787 2788 opipe->u.bulk.isread = isread; 2789 opipe->u.bulk.length = len; 2790 2791 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2792 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2793 /* Update device address */ 2794 sed->ed.ed_flags = HTOO32( 2795 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2796 OHCI_ED_SET_FA(addr)); 2797 2798 /* Allocate a chain of new TDs (including a new tail). */ 2799 data = opipe->tail.td; 2800 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2801 data, &tail); 2802 if (err) 2803 return err; 2804 2805 /* We want interrupt at the end of the transfer. */ 2806 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2807 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2808 tail->flags |= OHCI_CALL_DONE; 2809 tail = tail->nexttd; /* point at sentinel */ 2810 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2811 sizeof(tail->td.td_flags), 2812 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2813 if (err) { 2814 mutex_exit(&sc->sc_lock); 2815 return err; 2816 } 2817 2818 tail->xfer = NULL; 2819 xfer->ux_hcpriv = data; 2820 2821 DPRINTFN(4,("ohci_device_bulk_start: ed_flags=0x%08x td_flags=0x%08x " 2822 "td_cbp=0x%08x td_be=0x%08x\n", 2823 (int)O32TOH(sed->ed.ed_flags), 2824 (int)O32TOH(data->td.td_flags), 2825 (int)O32TOH(data->td.td_cbp), 2826 (int)O32TOH(data->td.td_be))); 2827 2828 #ifdef OHCI_DEBUG 2829 if (ohcidebug > 5) { 2830 ohci_dump_ed(sc, sed); 2831 ohci_dump_tds(sc, data); 2832 } 2833 #endif 2834 2835 /* Insert ED in schedule */ 2836 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2837 tdp->xfer = xfer; 2838 } 2839 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2840 opipe->tail.td = tail; 2841 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2842 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2844 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2845 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2846 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2847 ohci_timeout, xfer); 2848 } 2849 mutex_exit(&sc->sc_lock); 2850 2851 #if 0 2852 /* This goes wrong if we are too slow. */ 2853 if (ohcidebug > 10) { 2854 delay(10000); 2855 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2856 OREAD4(sc, OHCI_COMMAND_STATUS))); 2857 ohci_dump_ed(sc, sed); 2858 ohci_dump_tds(sc, data); 2859 } 2860 #endif 2861 2862 return USBD_IN_PROGRESS; 2863 } 2864 2865 Static void 2866 ohci_device_bulk_abort(usbd_xfer_handle xfer) 2867 { 2868 #ifdef DIAGNOSTIC 2869 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2870 #endif 2871 2872 KASSERT(mutex_owned(&sc->sc_lock)); 2873 2874 DPRINTF(("ohci_device_bulk_abort: xfer=%p\n", xfer)); 2875 ohci_abort_xfer(xfer, USBD_CANCELLED); 2876 } 2877 2878 /* 2879 * Close a device bulk pipe. 2880 */ 2881 Static void 2882 ohci_device_bulk_close(usbd_pipe_handle pipe) 2883 { 2884 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 2885 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2886 2887 KASSERT(mutex_owned(&sc->sc_lock)); 2888 2889 DPRINTF(("ohci_device_bulk_close: pipe=%p\n", pipe)); 2890 ohci_close_pipe(pipe, sc->sc_bulk_head); 2891 ohci_free_std(sc, opipe->tail.td); 2892 } 2893 2894 /************************/ 2895 2896 Static usbd_status 2897 ohci_device_intr_transfer(usbd_xfer_handle xfer) 2898 { 2899 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2900 usbd_status err; 2901 2902 /* Insert last in queue. */ 2903 mutex_enter(&sc->sc_lock); 2904 err = usb_insert_transfer(xfer); 2905 mutex_exit(&sc->sc_lock); 2906 if (err) 2907 return err; 2908 2909 /* Pipe isn't running, start first */ 2910 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2911 } 2912 2913 Static usbd_status 2914 ohci_device_intr_start(usbd_xfer_handle xfer) 2915 { 2916 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 2917 usbd_device_handle dev = opipe->pipe.up_dev; 2918 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 2919 ohci_soft_ed_t *sed = opipe->sed; 2920 ohci_soft_td_t *data, *tail; 2921 int len, isread, endpt; 2922 2923 if (sc->sc_dying) 2924 return USBD_IOERROR; 2925 2926 DPRINTFN(3, ("ohci_device_intr_transfer: xfer=%p len=%d " 2927 "flags=%d priv=%p\n", 2928 xfer, xfer->ux_length, xfer->ux_flags, xfer->ux_priv)); 2929 2930 #ifdef DIAGNOSTIC 2931 if (xfer->ux_rqflags & URQ_REQUEST) 2932 panic("ohci_device_intr_transfer: a request"); 2933 #endif 2934 2935 len = xfer->ux_length; 2936 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2937 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2938 2939 data = opipe->tail.td; 2940 mutex_enter(&sc->sc_lock); 2941 tail = ohci_alloc_std(sc); 2942 mutex_exit(&sc->sc_lock); 2943 if (tail == NULL) 2944 return USBD_NOMEM; 2945 tail->xfer = NULL; 2946 2947 data->td.td_flags = HTOO32( 2948 isread ? OHCI_TD_IN : OHCI_TD_OUT | 2949 OHCI_TD_NOCC | 2950 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2951 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 2952 data->td.td_flags |= HTOO32(OHCI_TD_R); 2953 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 2954 data->nexttd = tail; 2955 data->td.td_nexttd = HTOO32(tail->physaddr); 2956 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 2957 data->len = len; 2958 data->xfer = xfer; 2959 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 2960 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 xfer->ux_hcpriv = data; 2963 2964 #ifdef OHCI_DEBUG 2965 if (ohcidebug > 5) { 2966 DPRINTF(("ohci_device_intr_transfer:\n")); 2967 ohci_dump_ed(sc, sed); 2968 ohci_dump_tds(sc, data); 2969 } 2970 #endif 2971 2972 /* Insert ED in schedule */ 2973 mutex_enter(&sc->sc_lock); 2974 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2976 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2977 opipe->tail.td = tail; 2978 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2979 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2981 2982 #if 0 2983 /* 2984 * This goes horribly wrong, printing thousands of descriptors, 2985 * because false references are followed due to the fact that the 2986 * TD is gone. 2987 */ 2988 if (ohcidebug > 5) { 2989 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 2990 DPRINTF(("ohci_device_intr_transfer: status=%x\n", 2991 OREAD4(sc, OHCI_COMMAND_STATUS))); 2992 ohci_dump_ed(sc, sed); 2993 ohci_dump_tds(sc, data); 2994 } 2995 #endif 2996 mutex_exit(&sc->sc_lock); 2997 2998 return USBD_IN_PROGRESS; 2999 } 3000 3001 /* Abort a device interrupt request. */ 3002 Static void 3003 ohci_device_intr_abort(usbd_xfer_handle xfer) 3004 { 3005 #ifdef DIAGNOSTIC 3006 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3007 #endif 3008 3009 KASSERT(mutex_owned(&sc->sc_lock)); 3010 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3011 3012 ohci_abort_xfer(xfer, USBD_CANCELLED); 3013 } 3014 3015 /* Close a device interrupt pipe. */ 3016 Static void 3017 ohci_device_intr_close(usbd_pipe_handle pipe) 3018 { 3019 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3020 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3021 int nslots = opipe->u.intr.nslots; 3022 int pos = opipe->u.intr.pos; 3023 int j; 3024 ohci_soft_ed_t *p, *sed = opipe->sed; 3025 3026 KASSERT(mutex_owned(&sc->sc_lock)); 3027 3028 DPRINTFN(1,("ohci_device_intr_close: pipe=%p nslots=%d pos=%d\n", 3029 pipe, nslots, pos)); 3030 usb_syncmem(&sed->dma, sed->offs, 3031 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3032 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3033 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3034 sizeof(sed->ed.ed_flags), 3035 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3036 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3037 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3038 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3039 3040 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3041 continue; 3042 #ifdef DIAGNOSTIC 3043 if (p == NULL) 3044 panic("ohci_device_intr_close: ED not found"); 3045 #endif 3046 p->next = sed->next; 3047 p->ed.ed_nexted = sed->ed.ed_nexted; 3048 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3049 sizeof(p->ed.ed_nexted), 3050 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3051 3052 for (j = 0; j < nslots; j++) 3053 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3054 3055 ohci_free_std(sc, opipe->tail.td); 3056 ohci_free_sed(sc, opipe->sed); 3057 } 3058 3059 Static usbd_status 3060 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3061 { 3062 int i, j, best; 3063 u_int npoll, slow, shigh, nslots; 3064 u_int bestbw, bw; 3065 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3066 3067 DPRINTFN(2, ("ohci_setintr: pipe=%p\n", opipe)); 3068 if (ival == 0) { 3069 printf("ohci_setintr: 0 interval\n"); 3070 return USBD_INVAL; 3071 } 3072 3073 npoll = OHCI_NO_INTRS; 3074 while (npoll > ival) 3075 npoll /= 2; 3076 DPRINTFN(2, ("ohci_setintr: ival=%d npoll=%d\n", ival, npoll)); 3077 3078 /* 3079 * We now know which level in the tree the ED must go into. 3080 * Figure out which slot has most bandwidth left over. 3081 * Slots to examine: 3082 * npoll 3083 * 1 0 3084 * 2 1 2 3085 * 4 3 4 5 6 3086 * 8 7 8 9 10 11 12 13 14 3087 * N (N-1) .. (N-1+N-1) 3088 */ 3089 slow = npoll-1; 3090 shigh = slow + npoll; 3091 nslots = OHCI_NO_INTRS / npoll; 3092 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3093 bw = 0; 3094 for (j = 0; j < nslots; j++) 3095 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3096 if (bw < bestbw) { 3097 best = i; 3098 bestbw = bw; 3099 } 3100 } 3101 DPRINTFN(2, ("ohci_setintr: best=%d(%d..%d) bestbw=%d\n", 3102 best, slow, shigh, bestbw)); 3103 3104 mutex_enter(&sc->sc_lock); 3105 hsed = sc->sc_eds[best]; 3106 sed->next = hsed->next; 3107 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3108 sizeof(hsed->ed.ed_flags), 3109 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3110 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3111 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3112 sizeof(sed->ed.ed_flags), 3113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3114 hsed->next = sed; 3115 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3116 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3117 sizeof(hsed->ed.ed_flags), 3118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3119 mutex_exit(&sc->sc_lock); 3120 3121 for (j = 0; j < nslots; j++) 3122 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3123 opipe->u.intr.nslots = nslots; 3124 opipe->u.intr.pos = best; 3125 3126 DPRINTFN(5, ("ohci_setintr: returns %p\n", opipe)); 3127 return USBD_NORMAL_COMPLETION; 3128 } 3129 3130 /***********************/ 3131 3132 usbd_status 3133 ohci_device_isoc_transfer(usbd_xfer_handle xfer) 3134 { 3135 ohci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3136 usbd_status err; 3137 3138 DPRINTFN(5,("ohci_device_isoc_transfer: xfer=%p\n", xfer)); 3139 3140 /* Put it on our queue, */ 3141 mutex_enter(&sc->sc_lock); 3142 err = usb_insert_transfer(xfer); 3143 mutex_exit(&sc->sc_lock); 3144 3145 /* bail out on error, */ 3146 if (err && err != USBD_IN_PROGRESS) 3147 return err; 3148 3149 /* XXX should check inuse here */ 3150 3151 /* insert into schedule, */ 3152 ohci_device_isoc_enter(xfer); 3153 3154 /* and start if the pipe wasn't running */ 3155 if (!err) 3156 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3157 3158 return err; 3159 } 3160 3161 void 3162 ohci_device_isoc_enter(usbd_xfer_handle xfer) 3163 { 3164 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3165 usbd_device_handle dev = opipe->pipe.up_dev; 3166 ohci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3167 ohci_soft_ed_t *sed = opipe->sed; 3168 struct iso *iso = &opipe->u.iso; 3169 ohci_soft_itd_t *sitd, *nsitd; 3170 ohci_physaddr_t buf, offs, noffs, bp0; 3171 int i, ncur, nframes; 3172 3173 DPRINTFN(1,("ohci_device_isoc_enter: used=%d next=%d xfer=%p " 3174 "nframes=%d\n", 3175 iso->inuse, iso->next, xfer, xfer->ux_nframes)); 3176 3177 if (sc->sc_dying) 3178 return; 3179 3180 if (iso->next == -1) { 3181 /* Not in use yet, schedule it a few frames ahead. */ 3182 iso->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3183 DPRINTFN(2,("ohci_device_isoc_enter: start next=%d\n", 3184 iso->next)); 3185 } 3186 3187 sitd = opipe->tail.itd; 3188 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3189 bp0 = OHCI_PAGE(buf); 3190 offs = OHCI_PAGE_OFFSET(buf); 3191 nframes = xfer->ux_nframes; 3192 xfer->ux_hcpriv = sitd; 3193 for (i = ncur = 0; i < nframes; i++, ncur++) { 3194 noffs = offs + xfer->ux_frlengths[i]; 3195 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3196 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3197 3198 /* Allocate next ITD */ 3199 mutex_enter(&sc->sc_lock); 3200 nsitd = ohci_alloc_sitd(sc); 3201 mutex_exit(&sc->sc_lock); 3202 if (nsitd == NULL) { 3203 /* XXX what now? */ 3204 printf("%s: isoc TD alloc failed\n", 3205 device_xname(sc->sc_dev)); 3206 return; 3207 } 3208 3209 /* Fill current ITD */ 3210 sitd->itd.itd_flags = HTOO32( 3211 OHCI_ITD_NOCC | 3212 OHCI_ITD_SET_SF(iso->next) | 3213 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3214 OHCI_ITD_SET_FC(ncur)); 3215 sitd->itd.itd_bp0 = HTOO32(bp0); 3216 sitd->nextitd = nsitd; 3217 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3218 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3219 sitd->xfer = xfer; 3220 sitd->flags = 0; 3221 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3223 3224 sitd = nsitd; 3225 iso->next = iso->next + ncur; 3226 bp0 = OHCI_PAGE(buf + offs); 3227 ncur = 0; 3228 } 3229 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3230 offs = noffs; 3231 } 3232 mutex_enter(&sc->sc_lock); 3233 nsitd = ohci_alloc_sitd(sc); 3234 mutex_exit(&sc->sc_lock); 3235 if (nsitd == NULL) { 3236 /* XXX what now? */ 3237 printf("%s: isoc TD alloc failed\n", 3238 device_xname(sc->sc_dev)); 3239 return; 3240 } 3241 /* Fixup last used ITD */ 3242 sitd->itd.itd_flags = HTOO32( 3243 OHCI_ITD_NOCC | 3244 OHCI_ITD_SET_SF(iso->next) | 3245 OHCI_ITD_SET_DI(0) | 3246 OHCI_ITD_SET_FC(ncur)); 3247 sitd->itd.itd_bp0 = HTOO32(bp0); 3248 sitd->nextitd = nsitd; 3249 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3250 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3251 sitd->xfer = xfer; 3252 sitd->flags = OHCI_CALL_DONE; 3253 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3255 3256 iso->next = iso->next + ncur; 3257 iso->inuse += nframes; 3258 3259 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3260 3261 xfer->ux_status = USBD_IN_PROGRESS; 3262 3263 #ifdef OHCI_DEBUG 3264 if (ohcidebug > 5) { 3265 DPRINTF(("ohci_device_isoc_enter: frame=%d\n", 3266 O32TOH(sc->sc_hcca->hcca_frame_number))); 3267 ohci_dump_itds(sc, xfer->ux_hcpriv); 3268 ohci_dump_ed(sc, sed); 3269 } 3270 #endif 3271 3272 mutex_enter(&sc->sc_lock); 3273 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3274 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3275 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3276 opipe->tail.itd = nsitd; 3277 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3278 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3279 sizeof(sed->ed.ed_flags), 3280 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3281 mutex_exit(&sc->sc_lock); 3282 3283 #ifdef OHCI_DEBUG 3284 if (ohcidebug > 5) { 3285 delay(150000); 3286 DPRINTF(("ohci_device_isoc_enter: after frame=%d\n", 3287 O32TOH(sc->sc_hcca->hcca_frame_number))); 3288 ohci_dump_itds(sc, xfer->ux_hcpriv); 3289 ohci_dump_ed(sc, sed); 3290 } 3291 #endif 3292 } 3293 3294 usbd_status 3295 ohci_device_isoc_start(usbd_xfer_handle xfer) 3296 { 3297 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3298 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 3299 3300 DPRINTFN(5,("ohci_device_isoc_start: xfer=%p\n", xfer)); 3301 3302 mutex_enter(&sc->sc_lock); 3303 3304 if (sc->sc_dying) { 3305 mutex_exit(&sc->sc_lock); 3306 return USBD_IOERROR; 3307 } 3308 3309 #ifdef DIAGNOSTIC 3310 if (xfer->ux_status != USBD_IN_PROGRESS) 3311 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3312 #endif 3313 3314 /* XXX anything to do? */ 3315 3316 mutex_exit(&sc->sc_lock); 3317 3318 return USBD_IN_PROGRESS; 3319 } 3320 3321 void 3322 ohci_device_isoc_abort(usbd_xfer_handle xfer) 3323 { 3324 struct ohci_pipe *opipe = (struct ohci_pipe *)xfer->ux_pipe; 3325 ohci_softc_t *sc = opipe->pipe.up_dev->ud_bus->ub_hcpriv; 3326 ohci_soft_ed_t *sed; 3327 ohci_soft_itd_t *sitd; 3328 3329 DPRINTFN(1,("ohci_device_isoc_abort: xfer=%p lock=%p\n", xfer, &sc->sc_lock)); 3330 3331 KASSERT(mutex_owned(&sc->sc_lock)); 3332 3333 /* Transfer is already done. */ 3334 if (xfer->ux_status != USBD_NOT_STARTED && 3335 xfer->ux_status != USBD_IN_PROGRESS) { 3336 printf("ohci_device_isoc_abort: early return\n"); 3337 goto done; 3338 } 3339 3340 /* Give xfer the requested abort code. */ 3341 xfer->ux_status = USBD_CANCELLED; 3342 3343 sed = opipe->sed; 3344 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3345 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3346 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3347 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3348 sizeof(sed->ed.ed_flags), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 3351 sitd = xfer->ux_hcpriv; 3352 #ifdef DIAGNOSTIC 3353 if (sitd == NULL) { 3354 printf("ohci_device_isoc_abort: hcpriv==0\n"); 3355 goto done; 3356 } 3357 #endif 3358 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3359 #ifdef DIAGNOSTIC 3360 DPRINTFN(1,("abort sets done sitd=%p\n", sitd)); 3361 sitd->isdone = 1; 3362 #endif 3363 } 3364 3365 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3366 3367 /* Run callback. */ 3368 usb_transfer_complete(xfer); 3369 3370 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3371 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3372 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3374 3375 done: 3376 KASSERT(mutex_owned(&sc->sc_lock)); 3377 } 3378 3379 void 3380 ohci_device_isoc_done(usbd_xfer_handle xfer) 3381 { 3382 DPRINTFN(1,("ohci_device_isoc_done: xfer=%p\n", xfer)); 3383 } 3384 3385 usbd_status 3386 ohci_setup_isoc(usbd_pipe_handle pipe) 3387 { 3388 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3389 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3390 struct iso *iso = &opipe->u.iso; 3391 3392 iso->next = -1; 3393 iso->inuse = 0; 3394 3395 mutex_enter(&sc->sc_lock); 3396 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3397 mutex_exit(&sc->sc_lock); 3398 3399 return USBD_NORMAL_COMPLETION; 3400 } 3401 3402 void 3403 ohci_device_isoc_close(usbd_pipe_handle pipe) 3404 { 3405 struct ohci_pipe *opipe = (struct ohci_pipe *)pipe; 3406 ohci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3407 3408 KASSERT(mutex_owned(&sc->sc_lock)); 3409 3410 DPRINTF(("ohci_device_isoc_close: pipe=%p\n", pipe)); 3411 ohci_close_pipe(pipe, sc->sc_isoc_head); 3412 #ifdef DIAGNOSTIC 3413 opipe->tail.itd->isdone = 1; 3414 #endif 3415 ohci_free_sitd(sc, opipe->tail.itd); 3416 } 3417
Indexes created Fri Oct 03 02:09:57 GMT 2025