ohci.c revision 1.254.2.26
1 /* $NetBSD: ohci.c,v 1.254.2.26 2015/11/14 07:18:35 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.26 2015/11/14 07:18:35 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 133 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 134 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 135 136 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 137 ohci_soft_td_t *); 138 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 139 ohci_softc_t *, int, int, struct usbd_xfer *, 140 ohci_soft_td_t *, ohci_soft_td_t **); 141 142 Static usbd_status ohci_open(struct usbd_pipe *); 143 Static void ohci_poll(struct usbd_bus *); 144 Static void ohci_softintr(void *); 145 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 146 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 147 Static void ohci_rhsc_softint(void *); 148 149 Static usbd_status ohci_device_request(struct usbd_xfer *xfer); 150 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 151 ohci_soft_ed_t *); 152 153 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 154 ohci_soft_ed_t *); 155 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 156 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 157 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 158 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 159 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 160 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 161 162 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 163 Static void ohci_device_isoc_enter(struct usbd_xfer *); 164 165 Static struct usbd_xfer * 166 ohci_allocx(struct usbd_bus *, unsigned int); 167 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 168 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 169 Static int ohci_roothub_ctrl(struct usbd_bus *, 170 usb_device_request_t *, void *, int); 171 172 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 173 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 174 Static void ohci_root_intr_abort(struct usbd_xfer *); 175 Static void ohci_root_intr_close(struct usbd_pipe *); 176 Static void ohci_root_intr_done(struct usbd_xfer *); 177 178 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 179 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 180 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 181 Static void ohci_device_ctrl_close(struct usbd_pipe *); 182 Static void ohci_device_ctrl_done(struct usbd_xfer *); 183 184 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 185 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 186 Static void ohci_device_bulk_abort(struct usbd_xfer *); 187 Static void ohci_device_bulk_close(struct usbd_pipe *); 188 Static void ohci_device_bulk_done(struct usbd_xfer *); 189 190 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 191 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 192 Static void ohci_device_intr_abort(struct usbd_xfer *); 193 Static void ohci_device_intr_close(struct usbd_pipe *); 194 Static void ohci_device_intr_done(struct usbd_xfer *); 195 196 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 197 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 198 Static void ohci_device_isoc_abort(struct usbd_xfer *); 199 Static void ohci_device_isoc_close(struct usbd_pipe *); 200 Static void ohci_device_isoc_done(struct usbd_xfer *); 201 202 Static usbd_status ohci_device_setintr(ohci_softc_t *, 203 struct ohci_pipe *, int); 204 205 Static void ohci_timeout(void *); 206 Static void ohci_timeout_task(void *); 207 Static void ohci_rhsc_enable(void *); 208 209 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 210 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 211 212 Static void ohci_device_clear_toggle(struct usbd_pipe *); 213 Static void ohci_noop(struct usbd_pipe *); 214 215 #ifdef OHCI_DEBUG 216 Static void ohci_dumpregs(ohci_softc_t *); 217 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 218 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 219 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 220 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 221 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 222 #endif 223 224 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 225 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 226 #define OWRITE1(sc, r, x) \ 227 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 228 #define OWRITE2(sc, r, x) \ 229 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 230 #define OWRITE4(sc, r, x) \ 231 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 232 233 static __inline uint32_t 234 OREAD4(ohci_softc_t *sc, bus_size_t r) 235 { 236 237 OBARR(sc); 238 return bus_space_read_4(sc->iot, sc->ioh, r); 239 } 240 241 /* Reverse the bits in a value 0 .. 31 */ 242 Static uint8_t revbits[OHCI_NO_INTRS] = 243 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 244 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 245 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 246 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 247 248 struct ohci_pipe { 249 struct usbd_pipe pipe; 250 ohci_soft_ed_t *sed; 251 union { 252 ohci_soft_td_t *td; 253 ohci_soft_itd_t *itd; 254 } tail; 255 /* Info needed for different pipe kinds. */ 256 union { 257 /* Control pipe */ 258 struct { 259 usb_dma_t reqdma; 260 u_int length; 261 ohci_soft_td_t *setup, *data, *stat; 262 } ctrl; 263 /* Interrupt pipe */ 264 struct { 265 int nslots; 266 int pos; 267 } intr; 268 /* Bulk pipe */ 269 struct { 270 u_int length; 271 int isread; 272 } bulk; 273 /* Isochronous pipe */ 274 struct isoc { 275 int next, inuse; 276 } isoc; 277 }; 278 }; 279 280 Static const struct usbd_bus_methods ohci_bus_methods = { 281 .ubm_open = ohci_open, 282 .ubm_softint = ohci_softintr, 283 .ubm_dopoll = ohci_poll, 284 .ubm_allocx = ohci_allocx, 285 .ubm_freex = ohci_freex, 286 .ubm_getlock = ohci_get_lock, 287 .ubm_rhctrl = ohci_roothub_ctrl, 288 }; 289 290 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 291 .upm_transfer = ohci_root_intr_transfer, 292 .upm_start = ohci_root_intr_start, 293 .upm_abort = ohci_root_intr_abort, 294 .upm_close = ohci_root_intr_close, 295 .upm_cleartoggle = ohci_noop, 296 .upm_done = ohci_root_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 300 .upm_transfer = ohci_device_ctrl_transfer, 301 .upm_start = ohci_device_ctrl_start, 302 .upm_abort = ohci_device_ctrl_abort, 303 .upm_close = ohci_device_ctrl_close, 304 .upm_cleartoggle = ohci_noop, 305 .upm_done = ohci_device_ctrl_done, 306 }; 307 308 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 309 .upm_transfer = ohci_device_intr_transfer, 310 .upm_start = ohci_device_intr_start, 311 .upm_abort = ohci_device_intr_abort, 312 .upm_close = ohci_device_intr_close, 313 .upm_cleartoggle = ohci_device_clear_toggle, 314 .upm_done = ohci_device_intr_done, 315 }; 316 317 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 318 .upm_transfer = ohci_device_bulk_transfer, 319 .upm_start = ohci_device_bulk_start, 320 .upm_abort = ohci_device_bulk_abort, 321 .upm_close = ohci_device_bulk_close, 322 .upm_cleartoggle = ohci_device_clear_toggle, 323 .upm_done = ohci_device_bulk_done, 324 }; 325 326 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 327 .upm_transfer = ohci_device_isoc_transfer, 328 .upm_start = ohci_device_isoc_start, 329 .upm_abort = ohci_device_isoc_abort, 330 .upm_close = ohci_device_isoc_close, 331 .upm_cleartoggle = ohci_noop, 332 .upm_done = ohci_device_isoc_done, 333 }; 334 335 int 336 ohci_activate(device_t self, enum devact act) 337 { 338 struct ohci_softc *sc = device_private(self); 339 340 switch (act) { 341 case DVACT_DEACTIVATE: 342 sc->sc_dying = 1; 343 return 0; 344 default: 345 return EOPNOTSUPP; 346 } 347 } 348 349 void 350 ohci_childdet(device_t self, device_t child) 351 { 352 struct ohci_softc *sc = device_private(self); 353 354 KASSERT(sc->sc_child == child); 355 sc->sc_child = NULL; 356 } 357 358 int 359 ohci_detach(struct ohci_softc *sc, int flags) 360 { 361 int rv = 0; 362 363 if (sc->sc_child != NULL) 364 rv = config_detach(sc->sc_child, flags); 365 366 if (rv != 0) 367 return rv; 368 369 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 370 371 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 372 callout_destroy(&sc->sc_tmo_rhsc); 373 374 softint_disestablish(sc->sc_rhsc_si); 375 376 cv_destroy(&sc->sc_softwake_cv); 377 378 mutex_destroy(&sc->sc_lock); 379 mutex_destroy(&sc->sc_intr_lock); 380 381 if (sc->sc_hcca != NULL) 382 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 383 pool_cache_destroy(sc->sc_xferpool); 384 385 return rv; 386 } 387 388 ohci_soft_ed_t * 389 ohci_alloc_sed(ohci_softc_t *sc) 390 { 391 ohci_soft_ed_t *sed; 392 usbd_status err; 393 int i, offs; 394 usb_dma_t dma; 395 396 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 397 398 if (sc->sc_freeeds == NULL) { 399 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 400 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 401 OHCI_ED_ALIGN, &dma); 402 if (err) 403 return 0; 404 for (i = 0; i < OHCI_SED_CHUNK; i++) { 405 offs = i * OHCI_SED_SIZE; 406 sed = KERNADDR(&dma, offs); 407 sed->physaddr = DMAADDR(&dma, offs); 408 sed->dma = dma; 409 sed->offs = offs; 410 sed->next = sc->sc_freeeds; 411 sc->sc_freeeds = sed; 412 } 413 } 414 sed = sc->sc_freeeds; 415 sc->sc_freeeds = sed->next; 416 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 417 sed->next = 0; 418 return sed; 419 } 420 421 void 422 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 423 { 424 sed->next = sc->sc_freeeds; 425 sc->sc_freeeds = sed; 426 } 427 428 ohci_soft_td_t * 429 ohci_alloc_std(ohci_softc_t *sc) 430 { 431 ohci_soft_td_t *std; 432 usbd_status err; 433 int i, offs; 434 usb_dma_t dma; 435 436 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 437 438 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 439 440 if (sc->sc_freetds == NULL) { 441 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 442 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 443 OHCI_TD_ALIGN, &dma); 444 if (err) 445 return NULL; 446 for(i = 0; i < OHCI_STD_CHUNK; i++) { 447 offs = i * OHCI_STD_SIZE; 448 std = KERNADDR(&dma, offs); 449 std->physaddr = DMAADDR(&dma, offs); 450 std->dma = dma; 451 std->offs = offs; 452 std->nexttd = sc->sc_freetds; 453 sc->sc_freetds = std; 454 } 455 } 456 457 std = sc->sc_freetds; 458 sc->sc_freetds = std->nexttd; 459 memset(&std->td, 0, sizeof(ohci_td_t)); 460 std->nexttd = NULL; 461 std->xfer = NULL; 462 ohci_hash_add_td(sc, std); 463 464 return std; 465 } 466 467 void 468 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 469 { 470 471 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 472 473 ohci_hash_rem_td(sc, std); 474 std->nexttd = sc->sc_freetds; 475 sc->sc_freetds = std; 476 } 477 478 usbd_status 479 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 480 int alen, int rd, struct usbd_xfer *xfer, 481 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 482 { 483 ohci_soft_td_t *next, *cur; 484 ohci_physaddr_t dataphys, dataphysend; 485 uint32_t tdflags; 486 int len, curlen; 487 usb_dma_t *dma = &xfer->ux_dmabuf; 488 uint16_t flags = xfer->ux_flags; 489 490 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 491 DPRINTF("start len=%d", alen, 0, 0, 0); 492 493 KASSERT(mutex_owned(&sc->sc_lock)); 494 495 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 496 opipe->pipe.up_dev->ud_addr, 497 UE_GET_ADDR(opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress), 498 alen, opipe->pipe.up_dev->ud_speed); 499 500 len = alen; 501 cur = sp; 502 dataphys = DMAADDR(dma, 0); 503 dataphysend = OHCI_PAGE(dataphys + len - 1); 504 usb_syncmem(dma, 0, len, 505 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 506 tdflags = HTOO32( 507 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 508 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 509 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 510 511 for (;;) { 512 next = ohci_alloc_std(sc); 513 if (next == NULL) 514 goto nomem; 515 516 /* The OHCI hardware can handle at most one page crossing. */ 517 if (OHCI_PAGE(dataphys) == dataphysend || 518 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 519 /* we can handle it in this TD */ 520 curlen = len; 521 } else { 522 /* must use multiple TDs, fill as much as possible. */ 523 curlen = 2 * OHCI_PAGE_SIZE - 524 (dataphys & (OHCI_PAGE_SIZE-1)); 525 /* the length must be a multiple of the max size */ 526 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 527 KASSERT(curlen != 0); 528 } 529 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 530 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 531 len -= curlen; 532 533 cur->td.td_flags = tdflags; 534 cur->td.td_cbp = HTOO32(dataphys); 535 cur->nexttd = next; 536 cur->td.td_nexttd = HTOO32(next->physaddr); 537 cur->td.td_be = HTOO32(dataphys + curlen - 1); 538 cur->len = curlen; 539 cur->flags = OHCI_ADD_LEN; 540 cur->xfer = xfer; 541 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 543 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 544 dataphys + curlen - 1, 0, 0); 545 if (len == 0) 546 break; 547 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 548 dataphys += curlen; 549 cur = next; 550 } 551 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 552 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 553 /* Force a 0 length transfer at the end. */ 554 555 cur = next; 556 next = ohci_alloc_std(sc); 557 if (next == NULL) 558 goto nomem; 559 560 cur->td.td_flags = tdflags; 561 cur->td.td_cbp = 0; /* indicate 0 length packet */ 562 cur->nexttd = next; 563 cur->td.td_nexttd = HTOO32(next->physaddr); 564 cur->td.td_be = ~0; 565 cur->len = 0; 566 cur->flags = 0; 567 cur->xfer = xfer; 568 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 569 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 570 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 571 } 572 *ep = cur; 573 574 return USBD_NORMAL_COMPLETION; 575 576 nomem: 577 578 /* Don't free sp - let the caller do that */ 579 ohci_free_std_chain(sc, sp->nexttd, NULL); 580 581 return USBD_NOMEM; 582 } 583 584 Static void 585 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 586 ohci_soft_td_t *stdend) 587 { 588 ohci_soft_td_t *p; 589 590 for (; std != stdend; std = p) { 591 p = std->nexttd; 592 ohci_free_std(sc, std); 593 } 594 } 595 596 ohci_soft_itd_t * 597 ohci_alloc_sitd(ohci_softc_t *sc) 598 { 599 ohci_soft_itd_t *sitd; 600 usbd_status err; 601 int i, offs; 602 usb_dma_t dma; 603 604 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 605 606 if (sc->sc_freeitds == NULL) { 607 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 608 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 609 OHCI_ITD_ALIGN, &dma); 610 if (err) 611 return NULL; 612 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 613 offs = i * OHCI_SITD_SIZE; 614 sitd = KERNADDR(&dma, offs); 615 sitd->physaddr = DMAADDR(&dma, offs); 616 sitd->dma = dma; 617 sitd->offs = offs; 618 sitd->nextitd = sc->sc_freeitds; 619 sc->sc_freeitds = sitd; 620 } 621 } 622 623 sitd = sc->sc_freeitds; 624 sc->sc_freeitds = sitd->nextitd; 625 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 626 sitd->nextitd = NULL; 627 sitd->xfer = NULL; 628 ohci_hash_add_itd(sc, sitd); 629 630 #ifdef DIAGNOSTIC 631 sitd->isdone = 0; 632 #endif 633 634 return sitd; 635 } 636 637 void 638 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 639 { 640 641 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 642 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 643 644 KASSERT(sitd->isdone); 645 #ifdef DIAGNOSTIC 646 /* Warn double free */ 647 sitd->isdone = 0; 648 #endif 649 650 ohci_hash_rem_itd(sc, sitd); 651 sitd->nextitd = sc->sc_freeitds; 652 sc->sc_freeitds = sitd; 653 } 654 655 int 656 ohci_init(ohci_softc_t *sc) 657 { 658 ohci_soft_ed_t *sed, *psed; 659 usbd_status err; 660 int i; 661 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 662 663 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 664 665 aprint_normal_dev(sc->sc_dev, ""); 666 667 sc->sc_hcca = NULL; 668 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 669 670 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 671 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 672 cv_init(&sc->sc_softwake_cv, "ohciab"); 673 674 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 675 ohci_rhsc_softint, sc); 676 677 for (i = 0; i < OHCI_HASH_SIZE; i++) 678 LIST_INIT(&sc->sc_hash_tds[i]); 679 for (i = 0; i < OHCI_HASH_SIZE; i++) 680 LIST_INIT(&sc->sc_hash_itds[i]); 681 682 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 683 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 684 685 rev = OREAD4(sc, OHCI_REVISION); 686 aprint_normal("OHCI version %d.%d%s\n", 687 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 688 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 689 690 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 691 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 692 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 693 return -1; 694 } 695 sc->sc_bus.ub_revision = USBREV_1_0; 696 sc->sc_bus.ub_usedma = true; 697 698 /* XXX determine alignment by R/W */ 699 /* Allocate the HCCA area. */ 700 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 701 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 702 if (err) { 703 sc->sc_hcca = NULL; 704 return err; 705 } 706 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 707 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 708 709 sc->sc_eintrs = OHCI_NORMAL_INTRS; 710 711 /* Allocate dummy ED that starts the control list. */ 712 sc->sc_ctrl_head = ohci_alloc_sed(sc); 713 if (sc->sc_ctrl_head == NULL) { 714 err = ENOMEM; 715 goto bad1; 716 } 717 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 718 719 /* Allocate dummy ED that starts the bulk list. */ 720 sc->sc_bulk_head = ohci_alloc_sed(sc); 721 if (sc->sc_bulk_head == NULL) { 722 err = ENOMEM; 723 goto bad2; 724 } 725 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 726 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 727 sizeof(sc->sc_bulk_head->ed), 728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 729 730 /* Allocate dummy ED that starts the isochronous list. */ 731 sc->sc_isoc_head = ohci_alloc_sed(sc); 732 if (sc->sc_isoc_head == NULL) { 733 err = ENOMEM; 734 goto bad3; 735 } 736 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 737 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 738 sizeof(sc->sc_isoc_head->ed), 739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 740 741 /* Allocate all the dummy EDs that make up the interrupt tree. */ 742 for (i = 0; i < OHCI_NO_EDS; i++) { 743 sed = ohci_alloc_sed(sc); 744 if (sed == NULL) { 745 while (--i >= 0) 746 ohci_free_sed(sc, sc->sc_eds[i]); 747 err = ENOMEM; 748 goto bad4; 749 } 750 /* All ED fields are set to 0. */ 751 sc->sc_eds[i] = sed; 752 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 753 if (i != 0) 754 psed = sc->sc_eds[(i-1) / 2]; 755 else 756 psed= sc->sc_isoc_head; 757 sed->next = psed; 758 sed->ed.ed_nexted = HTOO32(psed->physaddr); 759 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 761 } 762 /* 763 * Fill HCCA interrupt table. The bit reversal is to get 764 * the tree set up properly to spread the interrupts. 765 */ 766 for (i = 0; i < OHCI_NO_INTRS; i++) 767 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 768 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 769 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 770 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 771 772 #ifdef OHCI_DEBUG 773 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 774 if (ohcidebug > 15) { 775 for (i = 0; i < OHCI_NO_EDS; i++) { 776 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 777 ohci_dump_ed(sc, sc->sc_eds[i]); 778 } 779 DPRINTFN(15, "iso", 0, 0, 0 ,0); 780 ohci_dump_ed(sc, sc->sc_isoc_head); 781 } 782 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 783 #endif 784 785 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 786 ctl = OREAD4(sc, OHCI_CONTROL); 787 rwc = ctl & OHCI_RWC; 788 fm = OREAD4(sc, OHCI_FM_INTERVAL); 789 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 790 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 791 792 /* Determine in what context we are running. */ 793 if (ctl & OHCI_IR) { 794 /* SMM active, request change */ 795 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 796 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 797 (OHCI_OC | OHCI_MIE)) 798 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 799 s = OREAD4(sc, OHCI_COMMAND_STATUS); 800 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 801 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 802 usb_delay_ms(&sc->sc_bus, 1); 803 ctl = OREAD4(sc, OHCI_CONTROL); 804 } 805 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 806 if ((ctl & OHCI_IR) == 0) { 807 aprint_error_dev(sc->sc_dev, 808 "SMM does not respond, resetting\n"); 809 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 810 goto reset; 811 } 812 #if 0 813 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 814 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 815 /* BIOS started controller. */ 816 DPRINTF("BIOS active", 0, 0, 0, 0); 817 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 818 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 819 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 820 } 821 #endif 822 } else { 823 DPRINTF("cold started", 0 ,0 ,0 ,0); 824 reset: 825 /* Controller was cold started. */ 826 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 827 } 828 829 /* 830 * This reset should not be necessary according to the OHCI spec, but 831 * without it some controllers do not start. 832 */ 833 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 834 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 835 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 836 837 /* We now own the host controller and the bus has been reset. */ 838 839 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 840 /* Nominal time for a reset is 10 us. */ 841 for (i = 0; i < 10; i++) { 842 delay(10); 843 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 844 if (!hcr) 845 break; 846 } 847 if (hcr) { 848 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 849 err = EIO; 850 goto bad5; 851 } 852 #ifdef OHCI_DEBUG 853 if (ohcidebug > 15) 854 ohci_dumpregs(sc); 855 #endif 856 857 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 858 859 /* Set up HC registers. */ 860 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 861 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 862 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 863 /* disable all interrupts and then switch on all desired interrupts */ 864 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 865 /* switch on desired functional features */ 866 ctl = OREAD4(sc, OHCI_CONTROL); 867 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 868 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 869 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 870 /* And finally start it! */ 871 OWRITE4(sc, OHCI_CONTROL, ctl); 872 873 /* 874 * The controller is now OPERATIONAL. Set a some final 875 * registers that should be set earlier, but that the 876 * controller ignores when in the SUSPEND state. 877 */ 878 ival = OHCI_GET_IVAL(fm); 879 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 880 fm |= OHCI_FSMPS(ival) | ival; 881 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 882 per = OHCI_PERIODIC(ival); /* 90% periodic */ 883 OWRITE4(sc, OHCI_PERIODIC_START, per); 884 885 if (sc->sc_flags & OHCIF_SUPERIO) { 886 /* no overcurrent protection */ 887 desca |= OHCI_NOCP; 888 /* 889 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 890 * that 891 * - ports are always power switched 892 * - don't wait for powered root hub port 893 */ 894 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 895 } 896 897 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 898 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 899 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 900 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 901 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 902 903 /* 904 * The AMD756 requires a delay before re-reading the register, 905 * otherwise it will occasionally report 0 ports. 906 */ 907 sc->sc_noport = 0; 908 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 909 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 910 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 911 } 912 913 #ifdef OHCI_DEBUG 914 if (ohcidebug > 5) 915 ohci_dumpregs(sc); 916 #endif 917 918 /* Set up the bus struct. */ 919 sc->sc_bus.ub_methods = &ohci_bus_methods; 920 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 921 922 sc->sc_control = sc->sc_intre = 0; 923 924 /* Finally, turn on interrupts. */ 925 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 926 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 927 928 return 0; 929 930 bad5: 931 for (i = 0; i < OHCI_NO_EDS; i++) 932 ohci_free_sed(sc, sc->sc_eds[i]); 933 bad4: 934 ohci_free_sed(sc, sc->sc_isoc_head); 935 bad3: 936 ohci_free_sed(sc, sc->sc_bulk_head); 937 bad2: 938 ohci_free_sed(sc, sc->sc_ctrl_head); 939 bad1: 940 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 941 sc->sc_hcca = NULL; 942 return err; 943 } 944 945 struct usbd_xfer * 946 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 947 { 948 ohci_softc_t *sc = OHCI_BUS2SC(bus); 949 struct usbd_xfer *xfer; 950 951 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 952 if (xfer != NULL) { 953 memset(xfer, 0, sizeof(struct ohci_xfer)); 954 #ifdef DIAGNOSTIC 955 xfer->ux_state = XFER_BUSY; 956 #endif 957 } 958 return xfer; 959 } 960 961 void 962 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 963 { 964 ohci_softc_t *sc = OHCI_BUS2SC(bus); 965 966 KASSERTMSG(xfer->ux_state == XFER_BUSY, 967 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 968 #ifdef DIAGNOSTIC 969 xfer->ux_state = XFER_FREE; 970 #endif 971 pool_cache_put(sc->sc_xferpool, xfer); 972 } 973 974 Static void 975 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 976 { 977 ohci_softc_t *sc = OHCI_BUS2SC(bus); 978 979 *lock = &sc->sc_lock; 980 } 981 982 /* 983 * Shut down the controller when the system is going down. 984 */ 985 bool 986 ohci_shutdown(device_t self, int flags) 987 { 988 ohci_softc_t *sc = device_private(self); 989 990 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 991 992 DPRINTF("stopping the HC", 0, 0, 0, 0); 993 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 994 return true; 995 } 996 997 bool 998 ohci_resume(device_t dv, const pmf_qual_t *qual) 999 { 1000 ohci_softc_t *sc = device_private(dv); 1001 uint32_t ctl; 1002 1003 mutex_spin_enter(&sc->sc_intr_lock); 1004 sc->sc_bus.ub_usepolling++; 1005 mutex_spin_exit(&sc->sc_intr_lock); 1006 1007 /* Some broken BIOSes do not recover these values */ 1008 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1009 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1010 sc->sc_ctrl_head->physaddr); 1011 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1012 sc->sc_bulk_head->physaddr); 1013 if (sc->sc_intre) 1014 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1015 (OHCI_ALL_INTRS | OHCI_MIE)); 1016 if (sc->sc_control) 1017 ctl = sc->sc_control; 1018 else 1019 ctl = OREAD4(sc, OHCI_CONTROL); 1020 ctl |= OHCI_HCFS_RESUME; 1021 OWRITE4(sc, OHCI_CONTROL, ctl); 1022 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1023 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1024 OWRITE4(sc, OHCI_CONTROL, ctl); 1025 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1026 sc->sc_control = sc->sc_intre = 0; 1027 1028 mutex_spin_enter(&sc->sc_intr_lock); 1029 sc->sc_bus.ub_usepolling--; 1030 mutex_spin_exit(&sc->sc_intr_lock); 1031 1032 return true; 1033 } 1034 1035 bool 1036 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1037 { 1038 ohci_softc_t *sc = device_private(dv); 1039 uint32_t ctl; 1040 1041 mutex_spin_enter(&sc->sc_intr_lock); 1042 sc->sc_bus.ub_usepolling++; 1043 mutex_spin_exit(&sc->sc_intr_lock); 1044 1045 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1046 if (sc->sc_control == 0) { 1047 /* 1048 * Preserve register values, in case that BIOS 1049 * does not recover them. 1050 */ 1051 sc->sc_control = ctl; 1052 sc->sc_intre = OREAD4(sc, 1053 OHCI_INTERRUPT_ENABLE); 1054 } 1055 ctl |= OHCI_HCFS_SUSPEND; 1056 OWRITE4(sc, OHCI_CONTROL, ctl); 1057 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1058 1059 mutex_spin_enter(&sc->sc_intr_lock); 1060 sc->sc_bus.ub_usepolling--; 1061 mutex_spin_exit(&sc->sc_intr_lock); 1062 1063 return true; 1064 } 1065 1066 #ifdef OHCI_DEBUG 1067 void 1068 ohci_dumpregs(ohci_softc_t *sc) 1069 { 1070 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1071 1072 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1073 OREAD4(sc, OHCI_REVISION), 1074 OREAD4(sc, OHCI_CONTROL), 1075 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1076 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1077 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1078 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1079 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1080 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1081 OREAD4(sc, OHCI_HCCA), 1082 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1083 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1084 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1085 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1086 OREAD4(sc, OHCI_BULK_HEAD_ED), 1087 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1088 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1089 OREAD4(sc, OHCI_DONE_HEAD), 1090 OREAD4(sc, OHCI_FM_INTERVAL), 1091 OREAD4(sc, OHCI_FM_REMAINING), 0); 1092 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1093 OREAD4(sc, OHCI_FM_NUMBER), 1094 OREAD4(sc, OHCI_PERIODIC_START), 1095 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1096 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1097 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1098 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1099 OREAD4(sc, OHCI_RH_STATUS), 0); 1100 DPRINTF(" port1=0x%08x port2=0x%08x", 1101 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1102 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1103 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1104 O32TOH(sc->sc_hcca->hcca_frame_number), 1105 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1106 } 1107 #endif 1108 1109 Static int ohci_intr1(ohci_softc_t *); 1110 1111 int 1112 ohci_intr(void *p) 1113 { 1114 ohci_softc_t *sc = p; 1115 int ret = 0; 1116 1117 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1118 1119 if (sc == NULL) 1120 return 0; 1121 1122 mutex_spin_enter(&sc->sc_intr_lock); 1123 1124 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1125 goto done; 1126 1127 /* If we get an interrupt while polling, then just ignore it. */ 1128 if (sc->sc_bus.ub_usepolling) { 1129 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1130 /* for level triggered intrs, should do something to ack */ 1131 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1132 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1133 1134 goto done; 1135 } 1136 1137 ret = ohci_intr1(sc); 1138 1139 done: 1140 mutex_spin_exit(&sc->sc_intr_lock); 1141 return ret; 1142 } 1143 1144 Static int 1145 ohci_intr1(ohci_softc_t *sc) 1146 { 1147 uint32_t intrs, eintrs; 1148 1149 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1150 1151 /* In case the interrupt occurs before initialization has completed. */ 1152 if (sc == NULL || sc->sc_hcca == NULL) { 1153 #ifdef DIAGNOSTIC 1154 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1155 #endif 1156 return 0; 1157 } 1158 1159 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1160 1161 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1162 if (!intrs) 1163 return 0; 1164 1165 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1166 eintrs = intrs & sc->sc_eintrs; 1167 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1168 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1169 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1170 sc->sc_eintrs); 1171 1172 if (!eintrs) { 1173 return 0; 1174 } 1175 1176 if (eintrs & OHCI_SO) { 1177 sc->sc_overrun_cnt++; 1178 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1179 printf("%s: %u scheduling overruns\n", 1180 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1181 sc->sc_overrun_cnt = 0; 1182 } 1183 /* XXX do what */ 1184 eintrs &= ~OHCI_SO; 1185 } 1186 if (eintrs & OHCI_WDH) { 1187 /* 1188 * We block the interrupt below, and reenable it later from 1189 * ohci_softintr(). 1190 */ 1191 usb_schedsoftintr(&sc->sc_bus); 1192 } 1193 if (eintrs & OHCI_RD) { 1194 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1195 /* XXX process resume detect */ 1196 } 1197 if (eintrs & OHCI_UE) { 1198 printf("%s: unrecoverable error, controller halted\n", 1199 device_xname(sc->sc_dev)); 1200 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1201 /* XXX what else */ 1202 } 1203 if (eintrs & OHCI_RHSC) { 1204 /* 1205 * We block the interrupt below, and reenable it later from 1206 * a timeout. 1207 */ 1208 softint_schedule(sc->sc_rhsc_si); 1209 } 1210 1211 if (eintrs != 0) { 1212 /* Block unprocessed interrupts. */ 1213 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1214 sc->sc_eintrs &= ~eintrs; 1215 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1216 } 1217 1218 return 1; 1219 } 1220 1221 void 1222 ohci_rhsc_enable(void *v_sc) 1223 { 1224 ohci_softc_t *sc = v_sc; 1225 1226 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1227 DPRINTF("sc %p", sc, 0, 0, 0); 1228 mutex_spin_enter(&sc->sc_intr_lock); 1229 sc->sc_eintrs |= OHCI_RHSC; 1230 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1231 mutex_spin_exit(&sc->sc_intr_lock); 1232 } 1233 1234 #ifdef OHCI_DEBUG 1235 const char *ohci_cc_strs[] = { 1236 "NO_ERROR", 1237 "CRC", 1238 "BIT_STUFFING", 1239 "DATA_TOGGLE_MISMATCH", 1240 "STALL", 1241 "DEVICE_NOT_RESPONDING", 1242 "PID_CHECK_FAILURE", 1243 "UNEXPECTED_PID", 1244 "DATA_OVERRUN", 1245 "DATA_UNDERRUN", 1246 "BUFFER_OVERRUN", 1247 "BUFFER_UNDERRUN", 1248 "reserved", 1249 "reserved", 1250 "NOT_ACCESSED", 1251 "NOT_ACCESSED", 1252 }; 1253 #endif 1254 1255 void 1256 ohci_softintr(void *v) 1257 { 1258 struct usbd_bus *bus = v; 1259 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1260 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1261 ohci_soft_td_t *std, *sdone, *stdnext; 1262 struct usbd_xfer *xfer; 1263 struct ohci_pipe *opipe; 1264 int len, cc; 1265 int i, j, actlen, iframes, uedir; 1266 ohci_physaddr_t done; 1267 1268 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1269 1270 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1271 1272 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1273 sizeof(sc->sc_hcca->hcca_done_head), 1274 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1275 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1276 sc->sc_hcca->hcca_done_head = 0; 1277 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1278 sizeof(sc->sc_hcca->hcca_done_head), 1279 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1280 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1281 sc->sc_eintrs |= OHCI_WDH; 1282 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1283 1284 /* Reverse the done list. */ 1285 for (sdone = NULL, sidone = NULL; done != 0; ) { 1286 std = ohci_hash_find_td(sc, done); 1287 if (std != NULL) { 1288 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1289 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1290 std->dnext = sdone; 1291 done = O32TOH(std->td.td_nexttd); 1292 sdone = std; 1293 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1294 continue; 1295 } 1296 sitd = ohci_hash_find_itd(sc, done); 1297 if (sitd != NULL) { 1298 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1299 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1300 sitd->dnext = sidone; 1301 done = O32TOH(sitd->itd.itd_nextitd); 1302 sidone = sitd; 1303 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1304 continue; 1305 } 1306 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1307 (u_long)done); 1308 break; 1309 } 1310 1311 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1312 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1313 #ifdef OHCI_DEBUG 1314 if (ohcidebug > 10) { 1315 for (std = sdone; std; std = std->dnext) 1316 ohci_dump_td(sc, std); 1317 } 1318 #endif 1319 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1320 1321 for (std = sdone; std; std = stdnext) { 1322 xfer = std->xfer; 1323 stdnext = std->dnext; 1324 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1325 xfer ? xfer->ux_hcpriv : 0, 0); 1326 if (xfer == NULL) { 1327 /* 1328 * xfer == NULL: There seems to be no xfer associated 1329 * with this TD. It is tailp that happened to end up on 1330 * the done queue. 1331 * Shouldn't happen, but some chips are broken(?). 1332 */ 1333 continue; 1334 } 1335 if (xfer->ux_status == USBD_CANCELLED || 1336 xfer->ux_status == USBD_TIMEOUT) { 1337 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1338 /* Handled by abort routine. */ 1339 continue; 1340 } 1341 callout_stop(&xfer->ux_callout); 1342 1343 len = std->len; 1344 if (std->td.td_cbp != 0) 1345 len -= O32TOH(std->td.td_be) - 1346 O32TOH(std->td.td_cbp) + 1; 1347 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1348 if (std->flags & OHCI_ADD_LEN) 1349 xfer->ux_actlen += len; 1350 1351 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1352 if (cc == OHCI_CC_NO_ERROR) { 1353 if (std->flags & OHCI_CALL_DONE) { 1354 xfer->ux_status = USBD_NORMAL_COMPLETION; 1355 usb_transfer_complete(xfer); 1356 } 1357 ohci_free_std(sc, std); 1358 } else { 1359 /* 1360 * Endpoint is halted. First unlink all the TDs 1361 * belonging to the failed transfer, and then restart 1362 * the endpoint. 1363 */ 1364 ohci_soft_td_t *p, *n; 1365 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1366 1367 DPRINTFN(15, "error cc=%d", 1368 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1369 1370 /* remove TDs */ 1371 for (p = std; p->xfer == xfer; p = n) { 1372 n = p->nexttd; 1373 ohci_free_std(sc, p); 1374 } 1375 1376 /* clear halt */ 1377 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1378 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1379 1380 if (cc == OHCI_CC_STALL) 1381 xfer->ux_status = USBD_STALLED; 1382 else 1383 xfer->ux_status = USBD_IOERROR; 1384 usb_transfer_complete(xfer); 1385 } 1386 } 1387 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1388 #ifdef OHCI_DEBUG 1389 if (ohcidebug > 10) { 1390 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1391 for (sitd = sidone; sitd; sitd = sitd->dnext) 1392 ohci_dump_itd(sc, sitd); 1393 } 1394 #endif 1395 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1396 1397 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1398 xfer = sitd->xfer; 1399 sitdnext = sitd->dnext; 1400 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1401 xfer ? xfer->ux_hcpriv : 0, 0); 1402 if (xfer == NULL) 1403 continue; 1404 if (xfer->ux_status == USBD_CANCELLED || 1405 xfer->ux_status == USBD_TIMEOUT) { 1406 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1407 /* Handled by abort routine. */ 1408 continue; 1409 } 1410 KASSERT(!sitd->isdone); 1411 #ifdef DIAGNOSTIC 1412 sitd->isdone = 1; 1413 #endif 1414 if (sitd->flags & OHCI_CALL_DONE) { 1415 ohci_soft_itd_t *next; 1416 1417 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1418 opipe->isoc.inuse -= xfer->ux_nframes; 1419 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1420 bEndpointAddress); 1421 xfer->ux_status = USBD_NORMAL_COMPLETION; 1422 actlen = 0; 1423 for (i = 0, sitd = xfer->ux_hcpriv;; 1424 sitd = next) { 1425 next = sitd->nextitd; 1426 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1427 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1428 xfer->ux_status = USBD_IOERROR; 1429 /* For input, update frlengths with actual */ 1430 /* XXX anything necessary for output? */ 1431 if (uedir == UE_DIR_IN && 1432 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1433 iframes = OHCI_ITD_GET_FC(O32TOH( 1434 sitd->itd.itd_flags)); 1435 for (j = 0; j < iframes; i++, j++) { 1436 len = O16TOH(sitd-> 1437 itd.itd_offset[j]); 1438 if ((OHCI_ITD_PSW_GET_CC(len) & 1439 OHCI_CC_NOT_ACCESSED_MASK) 1440 == OHCI_CC_NOT_ACCESSED) 1441 len = 0; 1442 else 1443 len = OHCI_ITD_PSW_LENGTH(len); 1444 xfer->ux_frlengths[i] = len; 1445 actlen += len; 1446 } 1447 } 1448 if (sitd->flags & OHCI_CALL_DONE) 1449 break; 1450 ohci_free_sitd(sc, sitd); 1451 } 1452 ohci_free_sitd(sc, sitd); 1453 if (uedir == UE_DIR_IN && 1454 xfer->ux_status == USBD_NORMAL_COMPLETION) 1455 xfer->ux_actlen = actlen; 1456 xfer->ux_hcpriv = NULL; 1457 1458 usb_transfer_complete(xfer); 1459 } 1460 } 1461 1462 if (sc->sc_softwake) { 1463 sc->sc_softwake = 0; 1464 cv_broadcast(&sc->sc_softwake_cv); 1465 } 1466 1467 DPRINTFN(10, "done", 0, 0, 0, 0); 1468 } 1469 1470 void 1471 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1472 { 1473 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1474 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1475 int len = UGETW(xfer->ux_request.wLength); 1476 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1477 1478 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1479 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1480 1481 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1482 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1483 1484 if (len) 1485 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1486 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1487 usb_syncmem(&opipe->ctrl.reqdma, 0, 1488 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1489 } 1490 1491 void 1492 ohci_device_intr_done(struct usbd_xfer *xfer) 1493 { 1494 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1495 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1496 ohci_soft_ed_t *sed = opipe->sed; 1497 ohci_soft_td_t *data, *tail; 1498 int isread = 1499 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1500 1501 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1502 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1503 1504 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1505 1506 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1507 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1508 if (xfer->ux_pipe->up_repeat) { 1509 data = opipe->tail.td; 1510 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1511 if (tail == NULL) { 1512 xfer->ux_status = USBD_NOMEM; 1513 return; 1514 } 1515 tail->xfer = NULL; 1516 1517 data->td.td_flags = HTOO32( 1518 OHCI_TD_IN | OHCI_TD_NOCC | 1519 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1520 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1521 data->td.td_flags |= HTOO32(OHCI_TD_R); 1522 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1523 data->nexttd = tail; 1524 data->td.td_nexttd = HTOO32(tail->physaddr); 1525 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1526 xfer->ux_length - 1); 1527 data->len = xfer->ux_length; 1528 data->xfer = xfer; 1529 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1530 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1532 xfer->ux_hcpriv = data; 1533 xfer->ux_actlen = 0; 1534 1535 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1536 usb_syncmem(&sed->dma, 1537 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1538 sizeof(sed->ed.ed_tailp), 1539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1540 opipe->tail.td = tail; 1541 } 1542 } 1543 1544 void 1545 ohci_device_bulk_done(struct usbd_xfer *xfer) 1546 { 1547 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1548 1549 int isread = 1550 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1551 1552 KASSERT(mutex_owned(&sc->sc_lock)); 1553 1554 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1555 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1556 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1557 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1558 } 1559 1560 Static void 1561 ohci_rhsc_softint(void *arg) 1562 { 1563 ohci_softc_t *sc = arg; 1564 1565 mutex_enter(&sc->sc_lock); 1566 1567 ohci_rhsc(sc, sc->sc_intrxfer); 1568 1569 /* Do not allow RHSC interrupts > 1 per second */ 1570 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1571 1572 mutex_exit(&sc->sc_lock); 1573 } 1574 1575 void 1576 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1577 { 1578 u_char *p; 1579 int i, m; 1580 int hstatus __unused; 1581 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1582 1583 KASSERT(mutex_owned(&sc->sc_lock)); 1584 1585 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1586 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1587 1588 if (xfer == NULL) { 1589 /* Just ignore the change. */ 1590 return; 1591 } 1592 1593 p = xfer->ux_buf; 1594 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1595 memset(p, 0, xfer->ux_length); 1596 for (i = 1; i <= m; i++) { 1597 /* Pick out CHANGE bits from the status reg. */ 1598 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1599 p[i/8] |= 1 << (i%8); 1600 } 1601 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1602 xfer->ux_actlen = xfer->ux_length; 1603 xfer->ux_status = USBD_NORMAL_COMPLETION; 1604 1605 usb_transfer_complete(xfer); 1606 } 1607 1608 void 1609 ohci_root_intr_done(struct usbd_xfer *xfer) 1610 { 1611 } 1612 1613 /* 1614 * Wait here until controller claims to have an interrupt. 1615 * Then call ohci_intr and return. Use timeout to avoid waiting 1616 * too long. 1617 */ 1618 void 1619 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1620 { 1621 int timo; 1622 uint32_t intrs; 1623 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1624 1625 mutex_enter(&sc->sc_lock); 1626 1627 xfer->ux_status = USBD_IN_PROGRESS; 1628 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1629 usb_delay_ms(&sc->sc_bus, 1); 1630 if (sc->sc_dying) 1631 break; 1632 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1633 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1634 #ifdef OHCI_DEBUG 1635 if (ohcidebug > 15) 1636 ohci_dumpregs(sc); 1637 #endif 1638 if (intrs) { 1639 mutex_spin_enter(&sc->sc_intr_lock); 1640 ohci_intr1(sc); 1641 mutex_spin_exit(&sc->sc_intr_lock); 1642 if (xfer->ux_status != USBD_IN_PROGRESS) 1643 goto done; 1644 } 1645 } 1646 1647 /* Timeout */ 1648 DPRINTF("timeout", 0, 0, 0, 0); 1649 xfer->ux_status = USBD_TIMEOUT; 1650 usb_transfer_complete(xfer); 1651 1652 /* XXX should free TD */ 1653 1654 done: 1655 mutex_exit(&sc->sc_lock); 1656 } 1657 1658 void 1659 ohci_poll(struct usbd_bus *bus) 1660 { 1661 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1662 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1663 1664 #ifdef OHCI_DEBUG 1665 static int last; 1666 int new; 1667 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1668 if (new != last) { 1669 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1670 last = new; 1671 } 1672 #endif 1673 sc->sc_eintrs |= OHCI_WDH; 1674 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1675 mutex_spin_enter(&sc->sc_intr_lock); 1676 ohci_intr1(sc); 1677 mutex_spin_exit(&sc->sc_intr_lock); 1678 } 1679 } 1680 1681 usbd_status 1682 ohci_device_request(struct usbd_xfer *xfer) 1683 { 1684 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1685 usb_device_request_t *req = &xfer->ux_request; 1686 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 1687 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1688 ohci_soft_td_t *setup, *stat, *next, *tail; 1689 ohci_soft_ed_t *sed; 1690 int isread; 1691 int len; 1692 usbd_status err; 1693 1694 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1695 1696 KASSERT(mutex_owned(&sc->sc_lock)); 1697 1698 isread = req->bmRequestType & UT_READ; 1699 len = UGETW(req->wLength); 1700 1701 DPRINTF("type=0x%02x, request=0x%02x, " 1702 "wValue=0x%04x, wIndex=0x%04x", 1703 req->bmRequestType, req->bRequest, UGETW(req->wValue), 1704 UGETW(req->wIndex)); 1705 DPRINTF("len=%d, addr=%d, endpt=%d", 1706 len, dev->ud_addr, 1707 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 1708 1709 setup = opipe->tail.td; 1710 stat = ohci_alloc_std(sc); 1711 if (stat == NULL) { 1712 err = USBD_NOMEM; 1713 goto bad1; 1714 } 1715 tail = ohci_alloc_std(sc); 1716 if (tail == NULL) { 1717 err = USBD_NOMEM; 1718 goto bad2; 1719 } 1720 tail->xfer = NULL; 1721 1722 sed = opipe->sed; 1723 opipe->ctrl.length = len; 1724 1725 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 1726 "address ED %d pipe %d\n", 1727 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 1728 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 1729 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 1730 "MPL ED %d pipe %d\n", 1731 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 1732 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 1733 1734 next = stat; 1735 1736 /* Set up data transaction */ 1737 if (len != 0) { 1738 ohci_soft_td_t *std = stat; 1739 1740 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 1741 std, &stat); 1742 if (err) { 1743 /* stat is unchanged if error */ 1744 goto bad3; 1745 } 1746 stat = stat->nexttd; /* point at free TD */ 1747 1748 /* Start toggle at 1 and then use the carried toggle. */ 1749 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 1750 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 1751 usb_syncmem(&std->dma, 1752 std->offs + offsetof(ohci_td_t, td_flags), 1753 sizeof(std->td.td_flags), 1754 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1755 } 1756 1757 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 1758 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 1759 1760 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 1761 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 1762 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 1763 setup->nexttd = next; 1764 setup->td.td_nexttd = HTOO32(next->physaddr); 1765 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 1766 setup->len = 0; 1767 setup->xfer = xfer; 1768 setup->flags = 0; 1769 xfer->ux_hcpriv = setup; 1770 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 1771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1772 1773 stat->td.td_flags = HTOO32( 1774 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 1775 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 1776 stat->td.td_cbp = 0; 1777 stat->nexttd = tail; 1778 stat->td.td_nexttd = HTOO32(tail->physaddr); 1779 stat->td.td_be = 0; 1780 stat->flags = OHCI_CALL_DONE; 1781 stat->len = 0; 1782 stat->xfer = xfer; 1783 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 1784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1785 1786 #ifdef OHCI_DEBUG 1787 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1788 if (ohcidebug > 5) { 1789 ohci_dump_ed(sc, sed); 1790 ohci_dump_tds(sc, setup); 1791 } 1792 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1793 #endif 1794 1795 /* Insert ED in schedule */ 1796 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1797 usb_syncmem(&sed->dma, 1798 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1799 sizeof(sed->ed.ed_tailp), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 opipe->tail.td = tail; 1802 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1803 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 1804 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 1805 ohci_timeout, xfer); 1806 } 1807 1808 #ifdef OHCI_DEBUG 1809 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 1810 if (ohcidebug > 20) { 1811 delay(10000); 1812 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 1813 0, 0, 0); 1814 ohci_dumpregs(sc); 1815 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 1816 ohci_dump_ed(sc, sc->sc_ctrl_head); 1817 DPRINTF("sed:", 0, 0, 0, 0); 1818 ohci_dump_ed(sc, sed); 1819 ohci_dump_tds(sc, setup); 1820 } 1821 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 1822 #endif 1823 1824 return USBD_NORMAL_COMPLETION; 1825 1826 bad3: 1827 ohci_free_std(sc, tail); 1828 bad2: 1829 ohci_free_std(sc, stat); 1830 bad1: 1831 return err; 1832 } 1833 1834 /* 1835 * Add an ED to the schedule. Called with USB lock held. 1836 */ 1837 Static void 1838 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1839 { 1840 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1841 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1842 1843 KASSERT(mutex_owned(&sc->sc_lock)); 1844 1845 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1846 sizeof(head->ed.ed_nexted), 1847 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1848 sed->next = head->next; 1849 sed->ed.ed_nexted = head->ed.ed_nexted; 1850 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1851 sizeof(sed->ed.ed_nexted), 1852 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1853 head->next = sed; 1854 head->ed.ed_nexted = HTOO32(sed->physaddr); 1855 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1856 sizeof(head->ed.ed_nexted), 1857 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1858 } 1859 1860 /* 1861 * Remove an ED from the schedule. Called with USB lock held. 1862 */ 1863 Static void 1864 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1865 { 1866 ohci_soft_ed_t *p; 1867 1868 KASSERT(mutex_owned(&sc->sc_lock)); 1869 1870 /* XXX */ 1871 for (p = head; p != NULL && p->next != sed; p = p->next) 1872 ; 1873 KASSERT(p != NULL); 1874 1875 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1876 sizeof(sed->ed.ed_nexted), 1877 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1878 p->next = sed->next; 1879 p->ed.ed_nexted = sed->ed.ed_nexted; 1880 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1881 sizeof(p->ed.ed_nexted), 1882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1883 } 1884 1885 /* 1886 * When a transfer is completed the TD is added to the done queue by 1887 * the host controller. This queue is the processed by software. 1888 * Unfortunately the queue contains the physical address of the TD 1889 * and we have no simple way to translate this back to a kernel address. 1890 * To make the translation possible (and fast) we use a hash table of 1891 * TDs currently in the schedule. The physical address is used as the 1892 * hash value. 1893 */ 1894 1895 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1896 /* Called with USB lock held. */ 1897 void 1898 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1899 { 1900 int h = HASH(std->physaddr); 1901 1902 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1903 1904 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1905 } 1906 1907 /* Called with USB lock held. */ 1908 void 1909 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1910 { 1911 1912 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1913 1914 LIST_REMOVE(std, hnext); 1915 } 1916 1917 ohci_soft_td_t * 1918 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1919 { 1920 int h = HASH(a); 1921 ohci_soft_td_t *std; 1922 1923 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1924 std != NULL; 1925 std = LIST_NEXT(std, hnext)) 1926 if (std->physaddr == a) 1927 return std; 1928 return NULL; 1929 } 1930 1931 /* Called with USB lock held. */ 1932 void 1933 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1934 { 1935 int h = HASH(sitd->physaddr); 1936 1937 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1938 1939 KASSERT(mutex_owned(&sc->sc_lock)); 1940 1941 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1942 0, 0); 1943 1944 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1945 } 1946 1947 /* Called with USB lock held. */ 1948 void 1949 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1950 { 1951 1952 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1953 1954 KASSERT(mutex_owned(&sc->sc_lock)); 1955 1956 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1957 0, 0); 1958 1959 LIST_REMOVE(sitd, hnext); 1960 } 1961 1962 ohci_soft_itd_t * 1963 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1964 { 1965 int h = HASH(a); 1966 ohci_soft_itd_t *sitd; 1967 1968 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1969 sitd != NULL; 1970 sitd = LIST_NEXT(sitd, hnext)) 1971 if (sitd->physaddr == a) 1972 return sitd; 1973 return NULL; 1974 } 1975 1976 void 1977 ohci_timeout(void *addr) 1978 { 1979 struct usbd_xfer *xfer = addr; 1980 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1981 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1982 1983 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1984 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1985 1986 if (sc->sc_dying) { 1987 mutex_enter(&sc->sc_lock); 1988 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1989 mutex_exit(&sc->sc_lock); 1990 return; 1991 } 1992 1993 /* Execute the abort in a process context. */ 1994 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1995 USB_TASKQ_MPSAFE); 1996 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1997 USB_TASKQ_HC); 1998 } 1999 2000 void 2001 ohci_timeout_task(void *addr) 2002 { 2003 struct usbd_xfer *xfer = addr; 2004 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2005 2006 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2007 2008 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2009 2010 mutex_enter(&sc->sc_lock); 2011 ohci_abort_xfer(xfer, USBD_TIMEOUT); 2012 mutex_exit(&sc->sc_lock); 2013 } 2014 2015 #ifdef OHCI_DEBUG 2016 void 2017 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 2018 { 2019 for (; std; std = std->nexttd) 2020 ohci_dump_td(sc, std); 2021 } 2022 2023 void 2024 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 2025 { 2026 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2027 2028 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 2029 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2030 2031 uint32_t flags = O32TOH(std->td.td_flags); 2032 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 2033 DPRINTF(" round=%d DP=%x DI=%x T=%x", 2034 !!(flags & OHCI_TD_R), 2035 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 2036 OHCI_TD_GET_DI(flags), 2037 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 2038 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 2039 0, 0); 2040 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 2041 (u_long)O32TOH(std->td.td_cbp), 2042 (u_long)O32TOH(std->td.td_nexttd), 2043 (u_long)O32TOH(std->td.td_be), 0); 2044 } 2045 2046 void 2047 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2048 { 2049 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2050 2051 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 2052 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2053 2054 uint32_t flags = O32TOH(sitd->itd.itd_flags); 2055 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 2056 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 2057 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 2058 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 2059 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 2060 O32TOH(sitd->itd.itd_bp0), 2061 O32TOH(sitd->itd.itd_nextitd), 2062 O32TOH(sitd->itd.itd_be), 0); 2063 CTASSERT(OHCI_ITD_NOFFSET == 8); 2064 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 2065 "offs[2] = 0x%04x offs[3] = 0x%04x", 2066 O16TOH(sitd->itd.itd_offset[0]), 2067 O16TOH(sitd->itd.itd_offset[1]), 2068 O16TOH(sitd->itd.itd_offset[2]), 2069 O16TOH(sitd->itd.itd_offset[3])); 2070 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 2071 "offs[6] = 0x%04x offs[7] = 0x%04x", 2072 O16TOH(sitd->itd.itd_offset[4]), 2073 O16TOH(sitd->itd.itd_offset[5]), 2074 O16TOH(sitd->itd.itd_offset[6]), 2075 O16TOH(sitd->itd.itd_offset[7])); 2076 } 2077 2078 void 2079 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 2080 { 2081 for (; sitd; sitd = sitd->nextitd) 2082 ohci_dump_itd(sc, sitd); 2083 } 2084 2085 void 2086 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 2087 { 2088 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2089 2090 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2091 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2092 2093 uint32_t flags = O32TOH(sed->ed.ed_flags); 2094 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 2095 DPRINTF(" addr=%d endpt=%d maxp=%d", 2096 OHCI_ED_GET_FA(flags), 2097 OHCI_ED_GET_EN(flags), 2098 OHCI_ED_GET_MAXP(flags), 2099 0); 2100 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 2101 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 2102 !!(flags & OHCI_ED_SPEED), 2103 !!(flags & OHCI_ED_SKIP), 2104 !!(flags & OHCI_ED_FORMAT_ISO)); 2105 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 2106 0, 0, 0); 2107 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 2108 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 2109 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 2110 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 2111 } 2112 #endif 2113 2114 usbd_status 2115 ohci_open(struct usbd_pipe *pipe) 2116 { 2117 struct usbd_device *dev = pipe->up_dev; 2118 struct usbd_bus *bus = dev->ud_bus; 2119 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2120 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 2121 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2122 uint8_t addr = dev->ud_addr; 2123 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 2124 ohci_soft_ed_t *sed; 2125 ohci_soft_td_t *std; 2126 ohci_soft_itd_t *sitd; 2127 ohci_physaddr_t tdphys; 2128 uint32_t fmt; 2129 usbd_status err = USBD_NOMEM; 2130 int ival; 2131 2132 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2133 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 2134 ed->bEndpointAddress, bus->ub_rhaddr); 2135 2136 if (sc->sc_dying) { 2137 return USBD_IOERROR; 2138 } 2139 2140 std = NULL; 2141 sed = NULL; 2142 2143 if (addr == bus->ub_rhaddr) { 2144 switch (ed->bEndpointAddress) { 2145 case USB_CONTROL_ENDPOINT: 2146 pipe->up_methods = &roothub_ctrl_methods; 2147 break; 2148 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 2149 pipe->up_methods = &ohci_root_intr_methods; 2150 break; 2151 default: 2152 err = USBD_INVAL; 2153 goto bad; 2154 } 2155 } else { 2156 sed = ohci_alloc_sed(sc); 2157 if (sed == NULL) 2158 goto bad; 2159 opipe->sed = sed; 2160 if (xfertype == UE_ISOCHRONOUS) { 2161 mutex_enter(&sc->sc_lock); 2162 sitd = ohci_alloc_sitd(sc); 2163 mutex_exit(&sc->sc_lock); 2164 if (sitd == NULL) 2165 goto bad; 2166 2167 opipe->tail.itd = sitd; 2168 tdphys = sitd->physaddr; 2169 fmt = OHCI_ED_FORMAT_ISO; 2170 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2171 fmt |= OHCI_ED_DIR_IN; 2172 else 2173 fmt |= OHCI_ED_DIR_OUT; 2174 } else { 2175 mutex_enter(&sc->sc_lock); 2176 std = ohci_alloc_std(sc); 2177 mutex_exit(&sc->sc_lock); 2178 if (std == NULL) 2179 goto bad; 2180 2181 opipe->tail.td = std; 2182 tdphys = std->physaddr; 2183 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2184 } 2185 sed->ed.ed_flags = HTOO32( 2186 OHCI_ED_SET_FA(addr) | 2187 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2188 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2189 fmt | 2190 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2191 sed->ed.ed_headp = HTOO32(tdphys | 2192 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2193 sed->ed.ed_tailp = HTOO32(tdphys); 2194 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2196 2197 switch (xfertype) { 2198 case UE_CONTROL: 2199 pipe->up_methods = &ohci_device_ctrl_methods; 2200 err = usb_allocmem(&sc->sc_bus, 2201 sizeof(usb_device_request_t), 2202 0, &opipe->ctrl.reqdma); 2203 if (err) 2204 goto bad; 2205 mutex_enter(&sc->sc_lock); 2206 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2207 mutex_exit(&sc->sc_lock); 2208 break; 2209 case UE_INTERRUPT: 2210 pipe->up_methods = &ohci_device_intr_methods; 2211 ival = pipe->up_interval; 2212 if (ival == USBD_DEFAULT_INTERVAL) 2213 ival = ed->bInterval; 2214 err = ohci_device_setintr(sc, opipe, ival); 2215 if (err) 2216 goto bad; 2217 break; 2218 case UE_ISOCHRONOUS: 2219 pipe->up_methods = &ohci_device_isoc_methods; 2220 return ohci_setup_isoc(pipe); 2221 case UE_BULK: 2222 pipe->up_methods = &ohci_device_bulk_methods; 2223 mutex_enter(&sc->sc_lock); 2224 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2225 mutex_exit(&sc->sc_lock); 2226 break; 2227 } 2228 } 2229 2230 return USBD_NORMAL_COMPLETION; 2231 2232 bad: 2233 if (std != NULL) { 2234 mutex_enter(&sc->sc_lock); 2235 ohci_free_std(sc, std); 2236 mutex_exit(&sc->sc_lock); 2237 } 2238 if (sed != NULL) 2239 ohci_free_sed(sc, sed); 2240 return err; 2241 2242 } 2243 2244 /* 2245 * Close a reqular pipe. 2246 * Assumes that there are no pending transactions. 2247 */ 2248 void 2249 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2250 { 2251 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2252 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2253 ohci_soft_ed_t *sed = opipe->sed; 2254 2255 KASSERT(mutex_owned(&sc->sc_lock)); 2256 2257 #ifdef DIAGNOSTIC 2258 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2259 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2260 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2261 ohci_soft_td_t *std; 2262 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2263 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2264 "tl=0x%x pipe=%p, std=%p\n", sed, 2265 (int)O32TOH(sed->ed.ed_headp), 2266 (int)O32TOH(sed->ed.ed_tailp), 2267 pipe, std); 2268 #ifdef OHCI_DEBUG 2269 usbd_dump_pipe(&opipe->pipe); 2270 ohci_dump_ed(sc, sed); 2271 if (std) 2272 ohci_dump_td(sc, std); 2273 #endif 2274 usb_delay_ms(&sc->sc_bus, 2); 2275 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2276 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2277 printf("ohci_close_pipe: pipe still not empty\n"); 2278 } 2279 #endif 2280 ohci_rem_ed(sc, sed, head); 2281 /* Make sure the host controller is not touching this ED */ 2282 usb_delay_ms(&sc->sc_bus, 1); 2283 pipe->up_endpoint->ue_toggle = 2284 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2285 ohci_free_sed(sc, opipe->sed); 2286 } 2287 2288 /* 2289 * Abort a device request. 2290 * If this routine is called at splusb() it guarantees that the request 2291 * will be removed from the hardware scheduling and that the callback 2292 * for it will be called with USBD_CANCELLED status. 2293 * It's impossible to guarantee that the requested transfer will not 2294 * have happened since the hardware runs concurrently. 2295 * If the transaction has already happened we rely on the ordinary 2296 * interrupt processing to process it. 2297 * XXX This is most probably wrong. 2298 * XXXMRG this doesn't make sense anymore. 2299 */ 2300 void 2301 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2302 { 2303 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2304 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2305 ohci_soft_ed_t *sed = opipe->sed; 2306 ohci_soft_td_t *p, *n; 2307 ohci_physaddr_t headp; 2308 int hit; 2309 int wake; 2310 2311 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2312 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2313 2314 KASSERT(mutex_owned(&sc->sc_lock)); 2315 ASSERT_SLEEPABLE(); 2316 2317 if (sc->sc_dying) { 2318 /* If we're dying, just do the software part. */ 2319 xfer->ux_status = status; /* make software ignore it */ 2320 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2321 usb_transfer_complete(xfer); 2322 return; 2323 } 2324 2325 /* 2326 * If an abort is already in progress then just wait for it to 2327 * complete and return. 2328 */ 2329 if (xfer->ux_hcflags & UXFER_ABORTING) { 2330 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2331 #ifdef DIAGNOSTIC 2332 if (status == USBD_TIMEOUT) 2333 printf("%s: TIMEOUT while aborting\n", __func__); 2334 #endif 2335 /* Override the status which might be USBD_TIMEOUT. */ 2336 xfer->ux_status = status; 2337 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2338 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2339 while (xfer->ux_hcflags & UXFER_ABORTING) 2340 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2341 goto done; 2342 } 2343 xfer->ux_hcflags |= UXFER_ABORTING; 2344 2345 /* 2346 * Step 1: Make interrupt routine and hardware ignore xfer. 2347 */ 2348 xfer->ux_status = status; /* make software ignore it */ 2349 callout_stop(&xfer->ux_callout); 2350 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2351 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2352 sizeof(sed->ed.ed_flags), 2353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2354 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2355 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2356 sizeof(sed->ed.ed_flags), 2357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2358 2359 /* 2360 * Step 2: Wait until we know hardware has finished any possible 2361 * use of the xfer. Also make sure the soft interrupt routine 2362 * has run. 2363 */ 2364 /* Hardware finishes in 1ms */ 2365 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2366 sc->sc_softwake = 1; 2367 usb_schedsoftintr(&sc->sc_bus); 2368 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2369 2370 /* 2371 * Step 3: Remove any vestiges of the xfer from the hardware. 2372 * The complication here is that the hardware may have executed 2373 * beyond the xfer we're trying to abort. So as we're scanning 2374 * the TDs of this xfer we check if the hardware points to 2375 * any of them. 2376 */ 2377 p = xfer->ux_hcpriv; 2378 KASSERT(p); 2379 2380 #ifdef OHCI_DEBUG 2381 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2382 2383 if (ohcidebug > 1) { 2384 DPRINTF("sed:", 0, 0, 0, 0); 2385 ohci_dump_ed(sc, sed); 2386 ohci_dump_tds(sc, p); 2387 } 2388 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2389 #endif 2390 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2391 hit = 0; 2392 for (; p->xfer == xfer; p = n) { 2393 hit |= headp == p->physaddr; 2394 n = p->nexttd; 2395 ohci_free_std(sc, p); 2396 } 2397 /* Zap headp register if hardware pointed inside the xfer. */ 2398 if (hit) { 2399 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2400 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2401 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2402 usb_syncmem(&sed->dma, 2403 sed->offs + offsetof(ohci_ed_t, ed_headp), 2404 sizeof(sed->ed.ed_headp), 2405 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2406 } else { 2407 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2408 } 2409 2410 /* 2411 * Step 4: Turn on hardware again. 2412 */ 2413 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2414 sizeof(sed->ed.ed_flags), 2415 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2416 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2417 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2418 sizeof(sed->ed.ed_flags), 2419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2420 2421 /* 2422 * Step 5: Execute callback. 2423 */ 2424 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2425 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2426 usb_transfer_complete(xfer); 2427 if (wake) 2428 cv_broadcast(&xfer->ux_hccv); 2429 2430 done: 2431 KASSERT(mutex_owned(&sc->sc_lock)); 2432 } 2433 2434 /* 2435 * Data structures and routines to emulate the root hub. 2436 */ 2437 Static int 2438 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2439 void *buf, int buflen) 2440 { 2441 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2442 usb_port_status_t ps; 2443 uint16_t len, value, index; 2444 int l, totlen = 0; 2445 int port, i; 2446 uint32_t v; 2447 2448 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2449 2450 if (sc->sc_dying) 2451 return -1; 2452 2453 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2454 req->bRequest, 0, 0); 2455 2456 len = UGETW(req->wLength); 2457 value = UGETW(req->wValue); 2458 index = UGETW(req->wIndex); 2459 2460 #define C(x,y) ((x) | ((y) << 8)) 2461 switch (C(req->bRequest, req->bmRequestType)) { 2462 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2463 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2464 if (len == 0) 2465 break; 2466 switch (value) { 2467 case C(0, UDESC_DEVICE): { 2468 usb_device_descriptor_t devd; 2469 2470 totlen = min(buflen, sizeof(devd)); 2471 memcpy(&devd, buf, totlen); 2472 USETW(devd.idVendor, sc->sc_id_vendor); 2473 memcpy(buf, &devd, totlen); 2474 break; 2475 } 2476 case C(1, UDESC_STRING): 2477 #define sd ((usb_string_descriptor_t *)buf) 2478 /* Vendor */ 2479 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2480 break; 2481 case C(2, UDESC_STRING): 2482 /* Product */ 2483 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2484 break; 2485 #undef sd 2486 default: 2487 /* default from usbroothub */ 2488 return buflen; 2489 } 2490 break; 2491 2492 /* Hub requests */ 2493 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2494 break; 2495 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2496 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2497 index, value, 0, 0); 2498 if (index < 1 || index > sc->sc_noport) { 2499 return -1; 2500 } 2501 port = OHCI_RH_PORT_STATUS(index); 2502 switch(value) { 2503 case UHF_PORT_ENABLE: 2504 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2505 break; 2506 case UHF_PORT_SUSPEND: 2507 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2508 break; 2509 case UHF_PORT_POWER: 2510 /* Yes, writing to the LOW_SPEED bit clears power. */ 2511 OWRITE4(sc, port, UPS_LOW_SPEED); 2512 break; 2513 case UHF_C_PORT_CONNECTION: 2514 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2515 break; 2516 case UHF_C_PORT_ENABLE: 2517 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2518 break; 2519 case UHF_C_PORT_SUSPEND: 2520 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2521 break; 2522 case UHF_C_PORT_OVER_CURRENT: 2523 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2524 break; 2525 case UHF_C_PORT_RESET: 2526 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2527 break; 2528 default: 2529 return -1; 2530 } 2531 switch(value) { 2532 case UHF_C_PORT_CONNECTION: 2533 case UHF_C_PORT_ENABLE: 2534 case UHF_C_PORT_SUSPEND: 2535 case UHF_C_PORT_OVER_CURRENT: 2536 case UHF_C_PORT_RESET: 2537 /* Enable RHSC interrupt if condition is cleared. */ 2538 if ((OREAD4(sc, port) >> 16) == 0) 2539 ohci_rhsc_enable(sc); 2540 break; 2541 default: 2542 break; 2543 } 2544 break; 2545 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2546 if (len == 0) 2547 break; 2548 if ((value & 0xff) != 0) { 2549 return -1; 2550 } 2551 usb_hub_descriptor_t hubd; 2552 2553 totlen = min(buflen, sizeof(hubd)); 2554 memcpy(&hubd, buf, totlen); 2555 2556 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2557 hubd.bNbrPorts = sc->sc_noport; 2558 USETW(hubd.wHubCharacteristics, 2559 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2560 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2561 /* XXX overcurrent */ 2562 ); 2563 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2564 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2565 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2566 hubd.DeviceRemovable[i++] = (uint8_t)v; 2567 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2568 totlen = min(totlen, hubd.bDescLength); 2569 memcpy(buf, &hubd, totlen); 2570 break; 2571 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2572 if (len != 4) { 2573 return -1; 2574 } 2575 memset(buf, 0, len); /* ? XXX */ 2576 totlen = len; 2577 break; 2578 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2579 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2580 if (index < 1 || index > sc->sc_noport) { 2581 return -1; 2582 } 2583 if (len != 4) { 2584 return -1; 2585 } 2586 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2587 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2588 USETW(ps.wPortStatus, v); 2589 USETW(ps.wPortChange, v >> 16); 2590 totlen = min(len, sizeof(ps)); 2591 memcpy(buf, &ps, totlen); 2592 break; 2593 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2594 return -1; 2595 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2596 break; 2597 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2598 if (index < 1 || index > sc->sc_noport) { 2599 return -1; 2600 } 2601 port = OHCI_RH_PORT_STATUS(index); 2602 switch(value) { 2603 case UHF_PORT_ENABLE: 2604 OWRITE4(sc, port, UPS_PORT_ENABLED); 2605 break; 2606 case UHF_PORT_SUSPEND: 2607 OWRITE4(sc, port, UPS_SUSPEND); 2608 break; 2609 case UHF_PORT_RESET: 2610 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2611 OWRITE4(sc, port, UPS_RESET); 2612 for (i = 0; i < 5; i++) { 2613 usb_delay_ms(&sc->sc_bus, 2614 USB_PORT_ROOT_RESET_DELAY); 2615 if (sc->sc_dying) { 2616 return -1; 2617 } 2618 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2619 break; 2620 } 2621 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2622 OREAD4(sc, port), 0, 0); 2623 break; 2624 case UHF_PORT_POWER: 2625 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2626 OWRITE4(sc, port, UPS_PORT_POWER); 2627 break; 2628 default: 2629 return -1; 2630 } 2631 break; 2632 default: 2633 /* default from usbroothub */ 2634 return buflen; 2635 } 2636 2637 return totlen; 2638 } 2639 2640 Static usbd_status 2641 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2642 { 2643 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2644 usbd_status err; 2645 2646 /* Insert last in queue. */ 2647 mutex_enter(&sc->sc_lock); 2648 err = usb_insert_transfer(xfer); 2649 mutex_exit(&sc->sc_lock); 2650 if (err) 2651 return err; 2652 2653 /* Pipe isn't running, start first */ 2654 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2655 } 2656 2657 Static usbd_status 2658 ohci_root_intr_start(struct usbd_xfer *xfer) 2659 { 2660 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2661 2662 if (sc->sc_dying) 2663 return USBD_IOERROR; 2664 2665 mutex_enter(&sc->sc_lock); 2666 KASSERT(sc->sc_intrxfer == NULL); 2667 sc->sc_intrxfer = xfer; 2668 mutex_exit(&sc->sc_lock); 2669 2670 return USBD_IN_PROGRESS; 2671 } 2672 2673 /* Abort a root interrupt request. */ 2674 Static void 2675 ohci_root_intr_abort(struct usbd_xfer *xfer) 2676 { 2677 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2678 2679 KASSERT(mutex_owned(&sc->sc_lock)); 2680 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2681 2682 sc->sc_intrxfer = NULL; 2683 2684 xfer->ux_status = USBD_CANCELLED; 2685 usb_transfer_complete(xfer); 2686 } 2687 2688 /* Close the root pipe. */ 2689 Static void 2690 ohci_root_intr_close(struct usbd_pipe *pipe) 2691 { 2692 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2693 2694 KASSERT(mutex_owned(&sc->sc_lock)); 2695 2696 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2697 2698 sc->sc_intrxfer = NULL; 2699 } 2700 2701 /************************/ 2702 2703 Static usbd_status 2704 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2705 { 2706 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2707 usbd_status err; 2708 2709 /* Insert last in queue. */ 2710 mutex_enter(&sc->sc_lock); 2711 err = usb_insert_transfer(xfer); 2712 mutex_exit(&sc->sc_lock); 2713 if (err) 2714 return err; 2715 2716 /* Pipe isn't running, start first */ 2717 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2718 } 2719 2720 Static usbd_status 2721 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2722 { 2723 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2724 usbd_status err; 2725 2726 if (sc->sc_dying) 2727 return USBD_IOERROR; 2728 2729 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2730 2731 mutex_enter(&sc->sc_lock); 2732 err = ohci_device_request(xfer); 2733 mutex_exit(&sc->sc_lock); 2734 if (err) 2735 return err; 2736 2737 if (sc->sc_bus.ub_usepolling) 2738 ohci_waitintr(sc, xfer); 2739 return USBD_IN_PROGRESS; 2740 } 2741 2742 /* Abort a device control request. */ 2743 Static void 2744 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2745 { 2746 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2747 2748 KASSERT(mutex_owned(&sc->sc_lock)); 2749 2750 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2751 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2752 ohci_abort_xfer(xfer, USBD_CANCELLED); 2753 } 2754 2755 /* Close a device control pipe. */ 2756 Static void 2757 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2758 { 2759 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2760 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2761 2762 KASSERT(mutex_owned(&sc->sc_lock)); 2763 2764 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2765 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2766 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2767 ohci_free_std(sc, opipe->tail.td); 2768 } 2769 2770 /************************/ 2771 2772 Static void 2773 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2774 { 2775 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2776 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2777 2778 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2779 } 2780 2781 Static void 2782 ohci_noop(struct usbd_pipe *pipe) 2783 { 2784 } 2785 2786 Static usbd_status 2787 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2788 { 2789 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2790 usbd_status err; 2791 2792 /* Insert last in queue. */ 2793 mutex_enter(&sc->sc_lock); 2794 err = usb_insert_transfer(xfer); 2795 mutex_exit(&sc->sc_lock); 2796 if (err) 2797 return err; 2798 2799 /* Pipe isn't running, start first */ 2800 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2801 } 2802 2803 Static usbd_status 2804 ohci_device_bulk_start(struct usbd_xfer *xfer) 2805 { 2806 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2807 struct usbd_device *dev = opipe->pipe.up_dev; 2808 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2809 int addr = dev->ud_addr; 2810 ohci_soft_td_t *data, *tail, *tdp; 2811 ohci_soft_ed_t *sed; 2812 int len, isread, endpt; 2813 usbd_status err; 2814 2815 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2816 2817 if (sc->sc_dying) 2818 return USBD_IOERROR; 2819 2820 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2821 2822 mutex_enter(&sc->sc_lock); 2823 2824 len = xfer->ux_length; 2825 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2826 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2827 sed = opipe->sed; 2828 2829 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2830 xfer->ux_flags); 2831 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2832 2833 opipe->bulk.isread = isread; 2834 opipe->bulk.length = len; 2835 2836 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2837 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2838 /* Update device address */ 2839 sed->ed.ed_flags = HTOO32( 2840 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2841 OHCI_ED_SET_FA(addr)); 2842 2843 /* Allocate a chain of new TDs (including a new tail). */ 2844 data = opipe->tail.td; 2845 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2846 data, &tail); 2847 if (err) 2848 return err; 2849 2850 /* We want interrupt at the end of the transfer. */ 2851 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2852 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2853 tail->flags |= OHCI_CALL_DONE; 2854 tail = tail->nexttd; /* point at sentinel */ 2855 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2856 sizeof(tail->td.td_flags), 2857 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2858 if (err) { 2859 mutex_exit(&sc->sc_lock); 2860 return err; 2861 } 2862 2863 tail->xfer = NULL; 2864 xfer->ux_hcpriv = data; 2865 2866 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 2867 "td_cbp=0x%08x td_be=0x%08x", 2868 (int)O32TOH(sed->ed.ed_flags), 2869 (int)O32TOH(data->td.td_flags), 2870 (int)O32TOH(data->td.td_cbp), 2871 (int)O32TOH(data->td.td_be)); 2872 2873 #ifdef OHCI_DEBUG 2874 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2875 if (ohcidebug > 5) { 2876 ohci_dump_ed(sc, sed); 2877 ohci_dump_tds(sc, data); 2878 } 2879 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2880 #endif 2881 2882 /* Insert ED in schedule */ 2883 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2884 tdp->xfer = xfer; 2885 } 2886 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2887 opipe->tail.td = tail; 2888 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2889 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2891 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2892 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2893 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2894 ohci_timeout, xfer); 2895 } 2896 mutex_exit(&sc->sc_lock); 2897 2898 #if 0 2899 /* This goes wrong if we are too slow. */ 2900 if (ohcidebug > 10) { 2901 delay(10000); 2902 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2903 0, 0, 0); 2904 ohci_dump_ed(sc, sed); 2905 ohci_dump_tds(sc, data); 2906 } 2907 #endif 2908 2909 return USBD_IN_PROGRESS; 2910 } 2911 2912 Static void 2913 ohci_device_bulk_abort(struct usbd_xfer *xfer) 2914 { 2915 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2916 2917 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2918 2919 KASSERT(mutex_owned(&sc->sc_lock)); 2920 2921 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2922 ohci_abort_xfer(xfer, USBD_CANCELLED); 2923 } 2924 2925 /* 2926 * Close a device bulk pipe. 2927 */ 2928 Static void 2929 ohci_device_bulk_close(struct usbd_pipe *pipe) 2930 { 2931 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2932 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2933 2934 KASSERT(mutex_owned(&sc->sc_lock)); 2935 2936 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2937 2938 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2939 ohci_close_pipe(pipe, sc->sc_bulk_head); 2940 ohci_free_std(sc, opipe->tail.td); 2941 } 2942 2943 /************************/ 2944 2945 Static usbd_status 2946 ohci_device_intr_transfer(struct usbd_xfer *xfer) 2947 { 2948 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2949 usbd_status err; 2950 2951 /* Insert last in queue. */ 2952 mutex_enter(&sc->sc_lock); 2953 err = usb_insert_transfer(xfer); 2954 mutex_exit(&sc->sc_lock); 2955 if (err) 2956 return err; 2957 2958 /* Pipe isn't running, start first */ 2959 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2960 } 2961 2962 Static usbd_status 2963 ohci_device_intr_start(struct usbd_xfer *xfer) 2964 { 2965 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2966 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2967 ohci_soft_ed_t *sed = opipe->sed; 2968 ohci_soft_td_t *data, *tail; 2969 int len, isread, endpt; 2970 2971 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2972 2973 if (sc->sc_dying) 2974 return USBD_IOERROR; 2975 2976 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 2977 xfer->ux_flags, xfer->ux_priv); 2978 2979 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2980 2981 len = xfer->ux_length; 2982 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2983 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2984 2985 data = opipe->tail.td; 2986 mutex_enter(&sc->sc_lock); 2987 tail = ohci_alloc_std(sc); 2988 mutex_exit(&sc->sc_lock); 2989 if (tail == NULL) 2990 return USBD_NOMEM; 2991 tail->xfer = NULL; 2992 2993 data->td.td_flags = HTOO32( 2994 isread ? OHCI_TD_IN : OHCI_TD_OUT | 2995 OHCI_TD_NOCC | 2996 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2997 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 2998 data->td.td_flags |= HTOO32(OHCI_TD_R); 2999 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 3000 data->nexttd = tail; 3001 data->td.td_nexttd = HTOO32(tail->physaddr); 3002 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 3003 data->len = len; 3004 data->xfer = xfer; 3005 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 3006 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 3007 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3008 xfer->ux_hcpriv = data; 3009 3010 #ifdef OHCI_DEBUG 3011 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3012 if (ohcidebug > 5) { 3013 ohci_dump_ed(sc, sed); 3014 ohci_dump_tds(sc, data); 3015 } 3016 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3017 #endif 3018 3019 /* Insert ED in schedule */ 3020 mutex_enter(&sc->sc_lock); 3021 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3022 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3023 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3024 opipe->tail.td = tail; 3025 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3026 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3027 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3028 3029 #if 0 3030 /* 3031 * This goes horribly wrong, printing thousands of descriptors, 3032 * because false references are followed due to the fact that the 3033 * TD is gone. 3034 */ 3035 if (ohcidebug > 5) { 3036 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3037 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 3038 0, 0, 0); 3039 ohci_dump_ed(sc, sed); 3040 ohci_dump_tds(sc, data); 3041 } 3042 #endif 3043 mutex_exit(&sc->sc_lock); 3044 3045 return USBD_IN_PROGRESS; 3046 } 3047 3048 /* Abort a device interrupt request. */ 3049 Static void 3050 ohci_device_intr_abort(struct usbd_xfer *xfer) 3051 { 3052 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3053 3054 KASSERT(mutex_owned(&sc->sc_lock)); 3055 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3056 3057 ohci_abort_xfer(xfer, USBD_CANCELLED); 3058 } 3059 3060 /* Close a device interrupt pipe. */ 3061 Static void 3062 ohci_device_intr_close(struct usbd_pipe *pipe) 3063 { 3064 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3065 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3066 int nslots = opipe->intr.nslots; 3067 int pos = opipe->intr.pos; 3068 int j; 3069 ohci_soft_ed_t *p, *sed = opipe->sed; 3070 3071 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3072 3073 KASSERT(mutex_owned(&sc->sc_lock)); 3074 3075 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3076 usb_syncmem(&sed->dma, sed->offs, 3077 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3078 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3079 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3080 sizeof(sed->ed.ed_flags), 3081 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3082 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3083 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3084 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3085 3086 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3087 continue; 3088 KASSERT(p); 3089 p->next = sed->next; 3090 p->ed.ed_nexted = sed->ed.ed_nexted; 3091 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3092 sizeof(p->ed.ed_nexted), 3093 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3094 3095 for (j = 0; j < nslots; j++) 3096 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3097 3098 ohci_free_std(sc, opipe->tail.td); 3099 ohci_free_sed(sc, opipe->sed); 3100 } 3101 3102 Static usbd_status 3103 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3104 { 3105 int i, j, best; 3106 u_int npoll, slow, shigh, nslots; 3107 u_int bestbw, bw; 3108 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3109 3110 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3111 3112 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3113 if (ival == 0) { 3114 printf("ohci_setintr: 0 interval\n"); 3115 return USBD_INVAL; 3116 } 3117 3118 npoll = OHCI_NO_INTRS; 3119 while (npoll > ival) 3120 npoll /= 2; 3121 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3122 3123 /* 3124 * We now know which level in the tree the ED must go into. 3125 * Figure out which slot has most bandwidth left over. 3126 * Slots to examine: 3127 * npoll 3128 * 1 0 3129 * 2 1 2 3130 * 4 3 4 5 6 3131 * 8 7 8 9 10 11 12 13 14 3132 * N (N-1) .. (N-1+N-1) 3133 */ 3134 slow = npoll-1; 3135 shigh = slow + npoll; 3136 nslots = OHCI_NO_INTRS / npoll; 3137 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3138 bw = 0; 3139 for (j = 0; j < nslots; j++) 3140 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3141 if (bw < bestbw) { 3142 best = i; 3143 bestbw = bw; 3144 } 3145 } 3146 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3147 3148 mutex_enter(&sc->sc_lock); 3149 hsed = sc->sc_eds[best]; 3150 sed->next = hsed->next; 3151 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3152 sizeof(hsed->ed.ed_flags), 3153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3154 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3155 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3156 sizeof(sed->ed.ed_flags), 3157 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3158 hsed->next = sed; 3159 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3160 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3161 sizeof(hsed->ed.ed_flags), 3162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3163 mutex_exit(&sc->sc_lock); 3164 3165 for (j = 0; j < nslots; j++) 3166 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3167 opipe->intr.nslots = nslots; 3168 opipe->intr.pos = best; 3169 3170 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3171 return USBD_NORMAL_COMPLETION; 3172 } 3173 3174 /***********************/ 3175 3176 usbd_status 3177 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3178 { 3179 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3180 usbd_status err; 3181 3182 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3183 3184 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3185 3186 /* Put it on our queue, */ 3187 mutex_enter(&sc->sc_lock); 3188 err = usb_insert_transfer(xfer); 3189 mutex_exit(&sc->sc_lock); 3190 3191 /* bail out on error, */ 3192 if (err && err != USBD_IN_PROGRESS) 3193 return err; 3194 3195 /* XXX should check inuse here */ 3196 3197 /* insert into schedule, */ 3198 ohci_device_isoc_enter(xfer); 3199 3200 /* and start if the pipe wasn't running */ 3201 if (!err) 3202 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3203 3204 return err; 3205 } 3206 3207 void 3208 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3209 { 3210 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3211 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3212 ohci_soft_ed_t *sed = opipe->sed; 3213 struct isoc *isoc = &opipe->isoc; 3214 ohci_soft_itd_t *sitd, *nsitd; 3215 ohci_physaddr_t buf, offs, noffs, bp0; 3216 int i, ncur, nframes; 3217 3218 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3219 3220 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3221 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3222 3223 if (sc->sc_dying) 3224 return; 3225 3226 if (isoc->next == -1) { 3227 /* Not in use yet, schedule it a few frames ahead. */ 3228 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3229 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3230 } 3231 3232 sitd = opipe->tail.itd; 3233 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3234 bp0 = OHCI_PAGE(buf); 3235 offs = OHCI_PAGE_OFFSET(buf); 3236 nframes = xfer->ux_nframes; 3237 xfer->ux_hcpriv = sitd; 3238 for (i = ncur = 0; i < nframes; i++, ncur++) { 3239 noffs = offs + xfer->ux_frlengths[i]; 3240 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3241 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3242 3243 /* Allocate next ITD */ 3244 mutex_enter(&sc->sc_lock); 3245 nsitd = ohci_alloc_sitd(sc); 3246 mutex_exit(&sc->sc_lock); 3247 if (nsitd == NULL) { 3248 /* XXX what now? */ 3249 printf("%s: isoc TD alloc failed\n", 3250 device_xname(sc->sc_dev)); 3251 return; 3252 } 3253 3254 /* Fill current ITD */ 3255 sitd->itd.itd_flags = HTOO32( 3256 OHCI_ITD_NOCC | 3257 OHCI_ITD_SET_SF(isoc->next) | 3258 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3259 OHCI_ITD_SET_FC(ncur)); 3260 sitd->itd.itd_bp0 = HTOO32(bp0); 3261 sitd->nextitd = nsitd; 3262 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3263 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3264 sitd->xfer = xfer; 3265 sitd->flags = 0; 3266 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3267 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3268 3269 sitd = nsitd; 3270 isoc->next = isoc->next + ncur; 3271 bp0 = OHCI_PAGE(buf + offs); 3272 ncur = 0; 3273 } 3274 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3275 offs = noffs; 3276 } 3277 mutex_enter(&sc->sc_lock); 3278 nsitd = ohci_alloc_sitd(sc); 3279 mutex_exit(&sc->sc_lock); 3280 if (nsitd == NULL) { 3281 /* XXX what now? */ 3282 printf("%s: isoc TD alloc failed\n", 3283 device_xname(sc->sc_dev)); 3284 return; 3285 } 3286 /* Fixup last used ITD */ 3287 sitd->itd.itd_flags = HTOO32( 3288 OHCI_ITD_NOCC | 3289 OHCI_ITD_SET_SF(isoc->next) | 3290 OHCI_ITD_SET_DI(0) | 3291 OHCI_ITD_SET_FC(ncur)); 3292 sitd->itd.itd_bp0 = HTOO32(bp0); 3293 sitd->nextitd = nsitd; 3294 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3295 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3296 sitd->xfer = xfer; 3297 sitd->flags = OHCI_CALL_DONE; 3298 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3299 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3300 3301 isoc->next = isoc->next + ncur; 3302 isoc->inuse += nframes; 3303 3304 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3305 3306 xfer->ux_status = USBD_IN_PROGRESS; 3307 3308 #ifdef OHCI_DEBUG 3309 if (ohcidebug > 5) { 3310 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3311 0, 0, 0); 3312 ohci_dump_itds(sc, xfer->ux_hcpriv); 3313 ohci_dump_ed(sc, sed); 3314 } 3315 #endif 3316 3317 mutex_enter(&sc->sc_lock); 3318 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3319 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3320 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3321 opipe->tail.itd = nsitd; 3322 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3323 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3324 sizeof(sed->ed.ed_flags), 3325 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3326 mutex_exit(&sc->sc_lock); 3327 3328 #ifdef OHCI_DEBUG 3329 if (ohcidebug > 5) { 3330 delay(150000); 3331 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3332 0, 0, 0); 3333 ohci_dump_itds(sc, xfer->ux_hcpriv); 3334 ohci_dump_ed(sc, sed); 3335 } 3336 #endif 3337 } 3338 3339 usbd_status 3340 ohci_device_isoc_start(struct usbd_xfer *xfer) 3341 { 3342 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3343 3344 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3345 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3346 3347 mutex_enter(&sc->sc_lock); 3348 3349 if (sc->sc_dying) { 3350 mutex_exit(&sc->sc_lock); 3351 return USBD_IOERROR; 3352 } 3353 3354 3355 #ifdef DIAGNOSTIC 3356 if (xfer->ux_status != USBD_IN_PROGRESS) 3357 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3358 #endif 3359 3360 /* XXX anything to do? */ 3361 3362 mutex_exit(&sc->sc_lock); 3363 3364 return USBD_IN_PROGRESS; 3365 } 3366 3367 void 3368 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3369 { 3370 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3371 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3372 ohci_soft_ed_t *sed; 3373 ohci_soft_itd_t *sitd; 3374 3375 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3376 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3377 3378 KASSERT(mutex_owned(&sc->sc_lock)); 3379 3380 /* Transfer is already done. */ 3381 if (xfer->ux_status != USBD_NOT_STARTED && 3382 xfer->ux_status != USBD_IN_PROGRESS) { 3383 printf("ohci_device_isoc_abort: early return\n"); 3384 goto done; 3385 } 3386 3387 /* Give xfer the requested abort code. */ 3388 xfer->ux_status = USBD_CANCELLED; 3389 3390 sed = opipe->sed; 3391 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3392 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3393 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3394 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3395 sizeof(sed->ed.ed_flags), 3396 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3397 3398 sitd = xfer->ux_hcpriv; 3399 KASSERT(sitd); 3400 3401 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3402 #ifdef DIAGNOSTIC 3403 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3404 sitd->isdone = 1; 3405 #endif 3406 } 3407 3408 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3409 3410 /* Run callback. */ 3411 usb_transfer_complete(xfer); 3412 3413 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3414 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3415 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3417 3418 done: 3419 KASSERT(mutex_owned(&sc->sc_lock)); 3420 } 3421 3422 void 3423 ohci_device_isoc_done(struct usbd_xfer *xfer) 3424 { 3425 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3426 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3427 } 3428 3429 usbd_status 3430 ohci_setup_isoc(struct usbd_pipe *pipe) 3431 { 3432 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3433 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3434 struct isoc *isoc = &opipe->isoc; 3435 3436 isoc->next = -1; 3437 isoc->inuse = 0; 3438 3439 mutex_enter(&sc->sc_lock); 3440 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3441 mutex_exit(&sc->sc_lock); 3442 3443 return USBD_NORMAL_COMPLETION; 3444 } 3445 3446 void 3447 ohci_device_isoc_close(struct usbd_pipe *pipe) 3448 { 3449 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3450 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3451 3452 KASSERT(mutex_owned(&sc->sc_lock)); 3453 3454 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3455 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3456 ohci_close_pipe(pipe, sc->sc_isoc_head); 3457 #ifdef DIAGNOSTIC 3458 opipe->tail.itd->isdone = 1; 3459 #endif 3460 ohci_free_sitd(sc, opipe->tail.itd); 3461 } 3462
Indexes created Fri Oct 03 02:09:57 GMT 2025