ohci.c revision 1.254.2.27
1 /* $NetBSD: ohci.c,v 1.254.2.27 2015/11/14 10:05:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2004, 2005, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at 9 * Carlstedt Research & Technology, Jared D. McNeill (jmcneill (at) invisible.ca) 10 * and Matthew R. Green (mrg (at) eterna.com.au). 11 * This code is derived from software contributed to The NetBSD Foundation 12 * by Charles M. Hannum. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * USB Open Host Controller driver. 38 * 39 * OHCI spec: http://www.compaq.com/productinfo/development/openhci.html 40 * USB spec: http://www.usb.org/developers/docs/ 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: ohci.c,v 1.254.2.27 2015/11/14 10:05:47 skrll Exp $"); 45 46 #include "opt_usb.h" 47 48 #include <sys/param.h> 49 50 #include <sys/cpu.h> 51 #include <sys/device.h> 52 #include <sys/kernel.h> 53 #include <sys/kmem.h> 54 #include <sys/proc.h> 55 #include <sys/queue.h> 56 #include <sys/select.h> 57 #include <sys/sysctl.h> 58 #include <sys/systm.h> 59 60 #include <machine/endian.h> 61 62 #include <dev/usb/usb.h> 63 #include <dev/usb/usbdi.h> 64 #include <dev/usb/usbdivar.h> 65 #include <dev/usb/usb_mem.h> 66 #include <dev/usb/usb_quirks.h> 67 68 #include <dev/usb/ohcireg.h> 69 #include <dev/usb/ohcivar.h> 70 #include <dev/usb/usbroothub.h> 71 #include <dev/usb/usbhist.h> 72 73 #ifdef USB_DEBUG 74 #ifndef OHCI_DEBUG 75 #define ohcidebug 0 76 #else 77 static int ohcidebug = 0; 78 79 SYSCTL_SETUP(sysctl_hw_ohci_setup, "sysctl hw.ohci setup") 80 { 81 int err; 82 const struct sysctlnode *rnode; 83 const struct sysctlnode *cnode; 84 85 err = sysctl_createv(clog, 0, NULL, &rnode, 86 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ohci", 87 SYSCTL_DESCR("ohci global controls"), 88 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 89 90 if (err) 91 goto fail; 92 93 /* control debugging printfs */ 94 err = sysctl_createv(clog, 0, &rnode, &cnode, 95 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 96 "debug", SYSCTL_DESCR("Enable debugging output"), 97 NULL, 0, &ohcidebug, sizeof(ohcidebug), CTL_CREATE, CTL_EOL); 98 if (err) 99 goto fail; 100 101 return; 102 fail: 103 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 104 } 105 106 #endif /* OHCI_DEBUG */ 107 #endif /* USB_DEBUG */ 108 109 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ohcidebug,FMT,A,B,C,D) 110 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ohcidebug,N,FMT,A,B,C,D) 111 #define OHCIHIST_FUNC() USBHIST_FUNC() 112 #define OHCIHIST_CALLED(name) USBHIST_CALLED(ohcidebug) 113 114 #if BYTE_ORDER == BIG_ENDIAN 115 #define SWAP_ENDIAN OHCI_LITTLE_ENDIAN 116 #else 117 #define SWAP_ENDIAN OHCI_BIG_ENDIAN 118 #endif 119 120 #define O16TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap16(val) : val) 121 #define O32TOH(val) (sc->sc_endian == SWAP_ENDIAN ? bswap32(val) : val) 122 #define HTOO16(val) O16TOH(val) 123 #define HTOO32(val) O32TOH(val) 124 125 struct ohci_pipe; 126 127 Static ohci_soft_ed_t *ohci_alloc_sed(ohci_softc_t *); 128 Static void ohci_free_sed(ohci_softc_t *, ohci_soft_ed_t *); 129 130 Static ohci_soft_td_t *ohci_alloc_std(ohci_softc_t *); 131 Static void ohci_free_std(ohci_softc_t *, ohci_soft_td_t *); 132 133 Static ohci_soft_itd_t *ohci_alloc_sitd(ohci_softc_t *); 134 Static void ohci_free_sitd(ohci_softc_t *,ohci_soft_itd_t *); 135 136 Static void ohci_free_std_chain(ohci_softc_t *, ohci_soft_td_t *, 137 ohci_soft_td_t *); 138 Static usbd_status ohci_alloc_std_chain(struct ohci_pipe *, 139 ohci_softc_t *, int, int, struct usbd_xfer *, 140 ohci_soft_td_t *, ohci_soft_td_t **); 141 142 Static usbd_status ohci_open(struct usbd_pipe *); 143 Static void ohci_poll(struct usbd_bus *); 144 Static void ohci_softintr(void *); 145 Static void ohci_waitintr(ohci_softc_t *, struct usbd_xfer *); 146 Static void ohci_rhsc(ohci_softc_t *, struct usbd_xfer *); 147 Static void ohci_rhsc_softint(void *); 148 149 Static void ohci_add_ed(ohci_softc_t *, ohci_soft_ed_t *, 150 ohci_soft_ed_t *); 151 152 Static void ohci_rem_ed(ohci_softc_t *, ohci_soft_ed_t *, 153 ohci_soft_ed_t *); 154 Static void ohci_hash_add_td(ohci_softc_t *, ohci_soft_td_t *); 155 Static void ohci_hash_rem_td(ohci_softc_t *, ohci_soft_td_t *); 156 Static ohci_soft_td_t *ohci_hash_find_td(ohci_softc_t *, ohci_physaddr_t); 157 Static void ohci_hash_add_itd(ohci_softc_t *, ohci_soft_itd_t *); 158 Static void ohci_hash_rem_itd(ohci_softc_t *, ohci_soft_itd_t *); 159 Static ohci_soft_itd_t *ohci_hash_find_itd(ohci_softc_t *, ohci_physaddr_t); 160 161 Static usbd_status ohci_setup_isoc(struct usbd_pipe *); 162 Static void ohci_device_isoc_enter(struct usbd_xfer *); 163 164 Static struct usbd_xfer * 165 ohci_allocx(struct usbd_bus *, unsigned int); 166 Static void ohci_freex(struct usbd_bus *, struct usbd_xfer *); 167 Static void ohci_get_lock(struct usbd_bus *, kmutex_t **); 168 Static int ohci_roothub_ctrl(struct usbd_bus *, 169 usb_device_request_t *, void *, int); 170 171 Static usbd_status ohci_root_intr_transfer(struct usbd_xfer *); 172 Static usbd_status ohci_root_intr_start(struct usbd_xfer *); 173 Static void ohci_root_intr_abort(struct usbd_xfer *); 174 Static void ohci_root_intr_close(struct usbd_pipe *); 175 Static void ohci_root_intr_done(struct usbd_xfer *); 176 177 Static usbd_status ohci_device_ctrl_transfer(struct usbd_xfer *); 178 Static usbd_status ohci_device_ctrl_start(struct usbd_xfer *); 179 Static void ohci_device_ctrl_abort(struct usbd_xfer *); 180 Static void ohci_device_ctrl_close(struct usbd_pipe *); 181 Static void ohci_device_ctrl_done(struct usbd_xfer *); 182 183 Static usbd_status ohci_device_bulk_transfer(struct usbd_xfer *); 184 Static usbd_status ohci_device_bulk_start(struct usbd_xfer *); 185 Static void ohci_device_bulk_abort(struct usbd_xfer *); 186 Static void ohci_device_bulk_close(struct usbd_pipe *); 187 Static void ohci_device_bulk_done(struct usbd_xfer *); 188 189 Static usbd_status ohci_device_intr_transfer(struct usbd_xfer *); 190 Static usbd_status ohci_device_intr_start(struct usbd_xfer *); 191 Static void ohci_device_intr_abort(struct usbd_xfer *); 192 Static void ohci_device_intr_close(struct usbd_pipe *); 193 Static void ohci_device_intr_done(struct usbd_xfer *); 194 195 Static usbd_status ohci_device_isoc_transfer(struct usbd_xfer *); 196 Static usbd_status ohci_device_isoc_start(struct usbd_xfer *); 197 Static void ohci_device_isoc_abort(struct usbd_xfer *); 198 Static void ohci_device_isoc_close(struct usbd_pipe *); 199 Static void ohci_device_isoc_done(struct usbd_xfer *); 200 201 Static usbd_status ohci_device_setintr(ohci_softc_t *, 202 struct ohci_pipe *, int); 203 204 Static void ohci_timeout(void *); 205 Static void ohci_timeout_task(void *); 206 Static void ohci_rhsc_enable(void *); 207 208 Static void ohci_close_pipe(struct usbd_pipe *, ohci_soft_ed_t *); 209 Static void ohci_abort_xfer(struct usbd_xfer *, usbd_status); 210 211 Static void ohci_device_clear_toggle(struct usbd_pipe *); 212 Static void ohci_noop(struct usbd_pipe *); 213 214 #ifdef OHCI_DEBUG 215 Static void ohci_dumpregs(ohci_softc_t *); 216 Static void ohci_dump_tds(ohci_softc_t *, ohci_soft_td_t *); 217 Static void ohci_dump_td(ohci_softc_t *, ohci_soft_td_t *); 218 Static void ohci_dump_ed(ohci_softc_t *, ohci_soft_ed_t *); 219 Static void ohci_dump_itd(ohci_softc_t *, ohci_soft_itd_t *); 220 Static void ohci_dump_itds(ohci_softc_t *, ohci_soft_itd_t *); 221 #endif 222 223 #define OBARR(sc) bus_space_barrier((sc)->iot, (sc)->ioh, 0, (sc)->sc_size, \ 224 BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) 225 #define OWRITE1(sc, r, x) \ 226 do { OBARR(sc); bus_space_write_1((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 227 #define OWRITE2(sc, r, x) \ 228 do { OBARR(sc); bus_space_write_2((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 229 #define OWRITE4(sc, r, x) \ 230 do { OBARR(sc); bus_space_write_4((sc)->iot, (sc)->ioh, (r), (x)); } while (0) 231 232 static __inline uint32_t 233 OREAD4(ohci_softc_t *sc, bus_size_t r) 234 { 235 236 OBARR(sc); 237 return bus_space_read_4(sc->iot, sc->ioh, r); 238 } 239 240 /* Reverse the bits in a value 0 .. 31 */ 241 Static uint8_t revbits[OHCI_NO_INTRS] = 242 { 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, 243 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, 244 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, 245 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f }; 246 247 struct ohci_pipe { 248 struct usbd_pipe pipe; 249 ohci_soft_ed_t *sed; 250 union { 251 ohci_soft_td_t *td; 252 ohci_soft_itd_t *itd; 253 } tail; 254 /* Info needed for different pipe kinds. */ 255 union { 256 /* Control pipe */ 257 struct { 258 usb_dma_t reqdma; 259 u_int length; 260 ohci_soft_td_t *setup, *data, *stat; 261 } ctrl; 262 /* Interrupt pipe */ 263 struct { 264 int nslots; 265 int pos; 266 } intr; 267 /* Bulk pipe */ 268 struct { 269 u_int length; 270 int isread; 271 } bulk; 272 /* Isochronous pipe */ 273 struct isoc { 274 int next, inuse; 275 } isoc; 276 }; 277 }; 278 279 Static const struct usbd_bus_methods ohci_bus_methods = { 280 .ubm_open = ohci_open, 281 .ubm_softint = ohci_softintr, 282 .ubm_dopoll = ohci_poll, 283 .ubm_allocx = ohci_allocx, 284 .ubm_freex = ohci_freex, 285 .ubm_getlock = ohci_get_lock, 286 .ubm_rhctrl = ohci_roothub_ctrl, 287 }; 288 289 Static const struct usbd_pipe_methods ohci_root_intr_methods = { 290 .upm_transfer = ohci_root_intr_transfer, 291 .upm_start = ohci_root_intr_start, 292 .upm_abort = ohci_root_intr_abort, 293 .upm_close = ohci_root_intr_close, 294 .upm_cleartoggle = ohci_noop, 295 .upm_done = ohci_root_intr_done, 296 }; 297 298 Static const struct usbd_pipe_methods ohci_device_ctrl_methods = { 299 .upm_transfer = ohci_device_ctrl_transfer, 300 .upm_start = ohci_device_ctrl_start, 301 .upm_abort = ohci_device_ctrl_abort, 302 .upm_close = ohci_device_ctrl_close, 303 .upm_cleartoggle = ohci_noop, 304 .upm_done = ohci_device_ctrl_done, 305 }; 306 307 Static const struct usbd_pipe_methods ohci_device_intr_methods = { 308 .upm_transfer = ohci_device_intr_transfer, 309 .upm_start = ohci_device_intr_start, 310 .upm_abort = ohci_device_intr_abort, 311 .upm_close = ohci_device_intr_close, 312 .upm_cleartoggle = ohci_device_clear_toggle, 313 .upm_done = ohci_device_intr_done, 314 }; 315 316 Static const struct usbd_pipe_methods ohci_device_bulk_methods = { 317 .upm_transfer = ohci_device_bulk_transfer, 318 .upm_start = ohci_device_bulk_start, 319 .upm_abort = ohci_device_bulk_abort, 320 .upm_close = ohci_device_bulk_close, 321 .upm_cleartoggle = ohci_device_clear_toggle, 322 .upm_done = ohci_device_bulk_done, 323 }; 324 325 Static const struct usbd_pipe_methods ohci_device_isoc_methods = { 326 .upm_transfer = ohci_device_isoc_transfer, 327 .upm_start = ohci_device_isoc_start, 328 .upm_abort = ohci_device_isoc_abort, 329 .upm_close = ohci_device_isoc_close, 330 .upm_cleartoggle = ohci_noop, 331 .upm_done = ohci_device_isoc_done, 332 }; 333 334 int 335 ohci_activate(device_t self, enum devact act) 336 { 337 struct ohci_softc *sc = device_private(self); 338 339 switch (act) { 340 case DVACT_DEACTIVATE: 341 sc->sc_dying = 1; 342 return 0; 343 default: 344 return EOPNOTSUPP; 345 } 346 } 347 348 void 349 ohci_childdet(device_t self, device_t child) 350 { 351 struct ohci_softc *sc = device_private(self); 352 353 KASSERT(sc->sc_child == child); 354 sc->sc_child = NULL; 355 } 356 357 int 358 ohci_detach(struct ohci_softc *sc, int flags) 359 { 360 int rv = 0; 361 362 if (sc->sc_child != NULL) 363 rv = config_detach(sc->sc_child, flags); 364 365 if (rv != 0) 366 return rv; 367 368 callout_halt(&sc->sc_tmo_rhsc, &sc->sc_lock); 369 370 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 371 callout_destroy(&sc->sc_tmo_rhsc); 372 373 softint_disestablish(sc->sc_rhsc_si); 374 375 cv_destroy(&sc->sc_softwake_cv); 376 377 mutex_destroy(&sc->sc_lock); 378 mutex_destroy(&sc->sc_intr_lock); 379 380 if (sc->sc_hcca != NULL) 381 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 382 pool_cache_destroy(sc->sc_xferpool); 383 384 return rv; 385 } 386 387 ohci_soft_ed_t * 388 ohci_alloc_sed(ohci_softc_t *sc) 389 { 390 ohci_soft_ed_t *sed; 391 usbd_status err; 392 int i, offs; 393 usb_dma_t dma; 394 395 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 396 397 if (sc->sc_freeeds == NULL) { 398 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 399 err = usb_allocmem(&sc->sc_bus, OHCI_SED_SIZE * OHCI_SED_CHUNK, 400 OHCI_ED_ALIGN, &dma); 401 if (err) 402 return 0; 403 for (i = 0; i < OHCI_SED_CHUNK; i++) { 404 offs = i * OHCI_SED_SIZE; 405 sed = KERNADDR(&dma, offs); 406 sed->physaddr = DMAADDR(&dma, offs); 407 sed->dma = dma; 408 sed->offs = offs; 409 sed->next = sc->sc_freeeds; 410 sc->sc_freeeds = sed; 411 } 412 } 413 sed = sc->sc_freeeds; 414 sc->sc_freeeds = sed->next; 415 memset(&sed->ed, 0, sizeof(ohci_ed_t)); 416 sed->next = 0; 417 return sed; 418 } 419 420 void 421 ohci_free_sed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 422 { 423 sed->next = sc->sc_freeeds; 424 sc->sc_freeeds = sed; 425 } 426 427 ohci_soft_td_t * 428 ohci_alloc_std(ohci_softc_t *sc) 429 { 430 ohci_soft_td_t *std; 431 usbd_status err; 432 int i, offs; 433 usb_dma_t dma; 434 435 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 436 437 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 438 439 if (sc->sc_freetds == NULL) { 440 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 441 err = usb_allocmem(&sc->sc_bus, OHCI_STD_SIZE * OHCI_STD_CHUNK, 442 OHCI_TD_ALIGN, &dma); 443 if (err) 444 return NULL; 445 for(i = 0; i < OHCI_STD_CHUNK; i++) { 446 offs = i * OHCI_STD_SIZE; 447 std = KERNADDR(&dma, offs); 448 std->physaddr = DMAADDR(&dma, offs); 449 std->dma = dma; 450 std->offs = offs; 451 std->nexttd = sc->sc_freetds; 452 sc->sc_freetds = std; 453 } 454 } 455 456 std = sc->sc_freetds; 457 sc->sc_freetds = std->nexttd; 458 memset(&std->td, 0, sizeof(ohci_td_t)); 459 std->nexttd = NULL; 460 std->xfer = NULL; 461 ohci_hash_add_td(sc, std); 462 463 return std; 464 } 465 466 void 467 ohci_free_std(ohci_softc_t *sc, ohci_soft_td_t *std) 468 { 469 470 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 471 472 ohci_hash_rem_td(sc, std); 473 std->nexttd = sc->sc_freetds; 474 sc->sc_freetds = std; 475 } 476 477 usbd_status 478 ohci_alloc_std_chain(struct ohci_pipe *opipe, ohci_softc_t *sc, 479 int alen, int rd, struct usbd_xfer *xfer, 480 ohci_soft_td_t *sp, ohci_soft_td_t **ep) 481 { 482 ohci_soft_td_t *next, *cur; 483 ohci_physaddr_t dataphys, dataphysend; 484 uint32_t tdflags; 485 int len, curlen; 486 usb_dma_t *dma = &xfer->ux_dmabuf; 487 uint16_t flags = xfer->ux_flags; 488 489 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 490 DPRINTF("start len=%d", alen, 0, 0, 0); 491 492 KASSERT(mutex_owned(&sc->sc_lock)); 493 494 DPRINTFN(8, "addr=%d endpt=%d len=%d speed=%d", 495 opipe->pipe.up_dev->ud_addr, 496 UE_GET_ADDR(opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress), 497 alen, opipe->pipe.up_dev->ud_speed); 498 499 len = alen; 500 cur = sp; 501 dataphys = DMAADDR(dma, 0); 502 dataphysend = OHCI_PAGE(dataphys + len - 1); 503 usb_syncmem(dma, 0, len, 504 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 505 tdflags = HTOO32( 506 (rd ? OHCI_TD_IN : OHCI_TD_OUT) | 507 (flags & USBD_SHORT_XFER_OK ? OHCI_TD_R : 0) | 508 OHCI_TD_NOCC | OHCI_TD_TOGGLE_CARRY | OHCI_TD_NOINTR); 509 510 for (;;) { 511 next = ohci_alloc_std(sc); 512 if (next == NULL) 513 goto nomem; 514 515 /* The OHCI hardware can handle at most one page crossing. */ 516 if (OHCI_PAGE(dataphys) == dataphysend || 517 OHCI_PAGE(dataphys) + OHCI_PAGE_SIZE == dataphysend) { 518 /* we can handle it in this TD */ 519 curlen = len; 520 } else { 521 /* must use multiple TDs, fill as much as possible. */ 522 curlen = 2 * OHCI_PAGE_SIZE - 523 (dataphys & (OHCI_PAGE_SIZE-1)); 524 /* the length must be a multiple of the max size */ 525 curlen -= curlen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 526 KASSERT(curlen != 0); 527 } 528 DPRINTFN(4, "dataphys=0x%08x dataphysend=0x%08x " 529 "len=%d curlen=%d", dataphys, dataphysend, len, curlen); 530 len -= curlen; 531 532 cur->td.td_flags = tdflags; 533 cur->td.td_cbp = HTOO32(dataphys); 534 cur->nexttd = next; 535 cur->td.td_nexttd = HTOO32(next->physaddr); 536 cur->td.td_be = HTOO32(dataphys + curlen - 1); 537 cur->len = curlen; 538 cur->flags = OHCI_ADD_LEN; 539 cur->xfer = xfer; 540 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 541 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 542 DPRINTFN(10, "cbp=0x%08x be=0x%08x", dataphys, 543 dataphys + curlen - 1, 0, 0); 544 if (len == 0) 545 break; 546 DPRINTFN(10, "extend chain", 0, 0, 0, 0); 547 dataphys += curlen; 548 cur = next; 549 } 550 if (!rd && (flags & USBD_FORCE_SHORT_XFER) && 551 alen % UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize) == 0) { 552 /* Force a 0 length transfer at the end. */ 553 554 cur = next; 555 next = ohci_alloc_std(sc); 556 if (next == NULL) 557 goto nomem; 558 559 cur->td.td_flags = tdflags; 560 cur->td.td_cbp = 0; /* indicate 0 length packet */ 561 cur->nexttd = next; 562 cur->td.td_nexttd = HTOO32(next->physaddr); 563 cur->td.td_be = ~0; 564 cur->len = 0; 565 cur->flags = 0; 566 cur->xfer = xfer; 567 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->td), 568 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 569 DPRINTFN(2, "add 0 xfer", 0, 0, 0, 0); 570 } 571 *ep = cur; 572 573 return USBD_NORMAL_COMPLETION; 574 575 nomem: 576 577 /* Don't free sp - let the caller do that */ 578 ohci_free_std_chain(sc, sp->nexttd, NULL); 579 580 return USBD_NOMEM; 581 } 582 583 Static void 584 ohci_free_std_chain(ohci_softc_t *sc, ohci_soft_td_t *std, 585 ohci_soft_td_t *stdend) 586 { 587 ohci_soft_td_t *p; 588 589 for (; std != stdend; std = p) { 590 p = std->nexttd; 591 ohci_free_std(sc, std); 592 } 593 } 594 595 ohci_soft_itd_t * 596 ohci_alloc_sitd(ohci_softc_t *sc) 597 { 598 ohci_soft_itd_t *sitd; 599 usbd_status err; 600 int i, offs; 601 usb_dma_t dma; 602 603 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 604 605 if (sc->sc_freeitds == NULL) { 606 DPRINTFN(2, "allocating chunk", 0, 0, 0, 0); 607 err = usb_allocmem(&sc->sc_bus, OHCI_SITD_SIZE * OHCI_SITD_CHUNK, 608 OHCI_ITD_ALIGN, &dma); 609 if (err) 610 return NULL; 611 for(i = 0; i < OHCI_SITD_CHUNK; i++) { 612 offs = i * OHCI_SITD_SIZE; 613 sitd = KERNADDR(&dma, offs); 614 sitd->physaddr = DMAADDR(&dma, offs); 615 sitd->dma = dma; 616 sitd->offs = offs; 617 sitd->nextitd = sc->sc_freeitds; 618 sc->sc_freeitds = sitd; 619 } 620 } 621 622 sitd = sc->sc_freeitds; 623 sc->sc_freeitds = sitd->nextitd; 624 memset(&sitd->itd, 0, sizeof(ohci_itd_t)); 625 sitd->nextitd = NULL; 626 sitd->xfer = NULL; 627 ohci_hash_add_itd(sc, sitd); 628 629 #ifdef DIAGNOSTIC 630 sitd->isdone = 0; 631 #endif 632 633 return sitd; 634 } 635 636 void 637 ohci_free_sitd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 638 { 639 640 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 641 DPRINTFN(10, "sitd=%p", sitd, 0, 0, 0); 642 643 KASSERT(sitd->isdone); 644 #ifdef DIAGNOSTIC 645 /* Warn double free */ 646 sitd->isdone = 0; 647 #endif 648 649 ohci_hash_rem_itd(sc, sitd); 650 sitd->nextitd = sc->sc_freeitds; 651 sc->sc_freeitds = sitd; 652 } 653 654 int 655 ohci_init(ohci_softc_t *sc) 656 { 657 ohci_soft_ed_t *sed, *psed; 658 usbd_status err; 659 int i; 660 uint32_t s, ctl, rwc, ival, hcr, fm, per, rev, desca /*, descb */; 661 662 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 663 664 aprint_normal_dev(sc->sc_dev, ""); 665 666 sc->sc_hcca = NULL; 667 callout_init(&sc->sc_tmo_rhsc, CALLOUT_MPSAFE); 668 669 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 670 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 671 cv_init(&sc->sc_softwake_cv, "ohciab"); 672 673 sc->sc_rhsc_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 674 ohci_rhsc_softint, sc); 675 676 for (i = 0; i < OHCI_HASH_SIZE; i++) 677 LIST_INIT(&sc->sc_hash_tds[i]); 678 for (i = 0; i < OHCI_HASH_SIZE; i++) 679 LIST_INIT(&sc->sc_hash_itds[i]); 680 681 sc->sc_xferpool = pool_cache_init(sizeof(struct ohci_xfer), 0, 0, 0, 682 "ohcixfer", NULL, IPL_USB, NULL, NULL, NULL); 683 684 rev = OREAD4(sc, OHCI_REVISION); 685 aprint_normal("OHCI version %d.%d%s\n", 686 OHCI_REV_HI(rev), OHCI_REV_LO(rev), 687 OHCI_REV_LEGACY(rev) ? ", legacy support" : ""); 688 689 if (OHCI_REV_HI(rev) != 1 || OHCI_REV_LO(rev) != 0) { 690 aprint_error_dev(sc->sc_dev, "unsupported OHCI revision\n"); 691 sc->sc_bus.ub_revision = USBREV_UNKNOWN; 692 return -1; 693 } 694 sc->sc_bus.ub_revision = USBREV_1_0; 695 sc->sc_bus.ub_usedma = true; 696 697 /* XXX determine alignment by R/W */ 698 /* Allocate the HCCA area. */ 699 err = usb_allocmem(&sc->sc_bus, OHCI_HCCA_SIZE, 700 OHCI_HCCA_ALIGN, &sc->sc_hccadma); 701 if (err) { 702 sc->sc_hcca = NULL; 703 return err; 704 } 705 sc->sc_hcca = KERNADDR(&sc->sc_hccadma, 0); 706 memset(sc->sc_hcca, 0, OHCI_HCCA_SIZE); 707 708 sc->sc_eintrs = OHCI_NORMAL_INTRS; 709 710 /* Allocate dummy ED that starts the control list. */ 711 sc->sc_ctrl_head = ohci_alloc_sed(sc); 712 if (sc->sc_ctrl_head == NULL) { 713 err = ENOMEM; 714 goto bad1; 715 } 716 sc->sc_ctrl_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 717 718 /* Allocate dummy ED that starts the bulk list. */ 719 sc->sc_bulk_head = ohci_alloc_sed(sc); 720 if (sc->sc_bulk_head == NULL) { 721 err = ENOMEM; 722 goto bad2; 723 } 724 sc->sc_bulk_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 725 usb_syncmem(&sc->sc_bulk_head->dma, sc->sc_bulk_head->offs, 726 sizeof(sc->sc_bulk_head->ed), 727 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 728 729 /* Allocate dummy ED that starts the isochronous list. */ 730 sc->sc_isoc_head = ohci_alloc_sed(sc); 731 if (sc->sc_isoc_head == NULL) { 732 err = ENOMEM; 733 goto bad3; 734 } 735 sc->sc_isoc_head->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 736 usb_syncmem(&sc->sc_isoc_head->dma, sc->sc_isoc_head->offs, 737 sizeof(sc->sc_isoc_head->ed), 738 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 739 740 /* Allocate all the dummy EDs that make up the interrupt tree. */ 741 for (i = 0; i < OHCI_NO_EDS; i++) { 742 sed = ohci_alloc_sed(sc); 743 if (sed == NULL) { 744 while (--i >= 0) 745 ohci_free_sed(sc, sc->sc_eds[i]); 746 err = ENOMEM; 747 goto bad4; 748 } 749 /* All ED fields are set to 0. */ 750 sc->sc_eds[i] = sed; 751 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 752 if (i != 0) 753 psed = sc->sc_eds[(i-1) / 2]; 754 else 755 psed= sc->sc_isoc_head; 756 sed->next = psed; 757 sed->ed.ed_nexted = HTOO32(psed->physaddr); 758 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 760 } 761 /* 762 * Fill HCCA interrupt table. The bit reversal is to get 763 * the tree set up properly to spread the interrupts. 764 */ 765 for (i = 0; i < OHCI_NO_INTRS; i++) 766 sc->sc_hcca->hcca_interrupt_table[revbits[i]] = 767 HTOO32(sc->sc_eds[OHCI_NO_EDS-OHCI_NO_INTRS+i]->physaddr); 768 usb_syncmem(&sc->sc_hccadma, 0, OHCI_HCCA_SIZE, 769 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 770 771 #ifdef OHCI_DEBUG 772 DPRINTFN(15, "--- dump start ---", 0, 0, 0 ,0); 773 if (ohcidebug > 15) { 774 for (i = 0; i < OHCI_NO_EDS; i++) { 775 DPRINTFN(15, "ed#%d ", i, 0, 0, 0); 776 ohci_dump_ed(sc, sc->sc_eds[i]); 777 } 778 DPRINTFN(15, "iso", 0, 0, 0 ,0); 779 ohci_dump_ed(sc, sc->sc_isoc_head); 780 } 781 DPRINTFN(15, "--- dump end ---", 0, 0, 0 ,0); 782 #endif 783 784 /* Preserve values programmed by SMM/BIOS but lost over reset. */ 785 ctl = OREAD4(sc, OHCI_CONTROL); 786 rwc = ctl & OHCI_RWC; 787 fm = OREAD4(sc, OHCI_FM_INTERVAL); 788 desca = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 789 /* descb = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); */ 790 791 /* Determine in what context we are running. */ 792 if (ctl & OHCI_IR) { 793 /* SMM active, request change */ 794 DPRINTF("SMM active, request owner change", 0, 0, 0, 0); 795 if ((sc->sc_intre & (OHCI_OC | OHCI_MIE)) == 796 (OHCI_OC | OHCI_MIE)) 797 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_MIE); 798 s = OREAD4(sc, OHCI_COMMAND_STATUS); 799 OWRITE4(sc, OHCI_COMMAND_STATUS, s | OHCI_OCR); 800 for (i = 0; i < 100 && (ctl & OHCI_IR); i++) { 801 usb_delay_ms(&sc->sc_bus, 1); 802 ctl = OREAD4(sc, OHCI_CONTROL); 803 } 804 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_MIE); 805 if ((ctl & OHCI_IR) == 0) { 806 aprint_error_dev(sc->sc_dev, 807 "SMM does not respond, resetting\n"); 808 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 809 goto reset; 810 } 811 #if 0 812 /* Don't bother trying to reuse the BIOS init, we'll reset it anyway. */ 813 } else if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_RESET) { 814 /* BIOS started controller. */ 815 DPRINTF("BIOS active", 0, 0, 0, 0); 816 if ((ctl & OHCI_HCFS_MASK) != OHCI_HCFS_OPERATIONAL) { 817 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_OPERATIONAL | rwc); 818 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 819 } 820 #endif 821 } else { 822 DPRINTF("cold started", 0 ,0 ,0 ,0); 823 reset: 824 /* Controller was cold started. */ 825 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 826 } 827 828 /* 829 * This reset should not be necessary according to the OHCI spec, but 830 * without it some controllers do not start. 831 */ 832 DPRINTF("sc %p: resetting", sc, 0, 0, 0); 833 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET | rwc); 834 usb_delay_ms(&sc->sc_bus, USB_BUS_RESET_DELAY); 835 836 /* We now own the host controller and the bus has been reset. */ 837 838 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR); /* Reset HC */ 839 /* Nominal time for a reset is 10 us. */ 840 for (i = 0; i < 10; i++) { 841 delay(10); 842 hcr = OREAD4(sc, OHCI_COMMAND_STATUS) & OHCI_HCR; 843 if (!hcr) 844 break; 845 } 846 if (hcr) { 847 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 848 err = EIO; 849 goto bad5; 850 } 851 #ifdef OHCI_DEBUG 852 if (ohcidebug > 15) 853 ohci_dumpregs(sc); 854 #endif 855 856 /* The controller is now in SUSPEND state, we have 2ms to finish. */ 857 858 /* Set up HC registers. */ 859 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 860 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 861 OWRITE4(sc, OHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 862 /* disable all interrupts and then switch on all desired interrupts */ 863 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, OHCI_ALL_INTRS); 864 /* switch on desired functional features */ 865 ctl = OREAD4(sc, OHCI_CONTROL); 866 ctl &= ~(OHCI_CBSR_MASK | OHCI_LES | OHCI_HCFS_MASK | OHCI_IR); 867 ctl |= OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE | 868 OHCI_RATIO_1_4 | OHCI_HCFS_OPERATIONAL | rwc; 869 /* And finally start it! */ 870 OWRITE4(sc, OHCI_CONTROL, ctl); 871 872 /* 873 * The controller is now OPERATIONAL. Set a some final 874 * registers that should be set earlier, but that the 875 * controller ignores when in the SUSPEND state. 876 */ 877 ival = OHCI_GET_IVAL(fm); 878 fm = (OREAD4(sc, OHCI_FM_INTERVAL) & OHCI_FIT) ^ OHCI_FIT; 879 fm |= OHCI_FSMPS(ival) | ival; 880 OWRITE4(sc, OHCI_FM_INTERVAL, fm); 881 per = OHCI_PERIODIC(ival); /* 90% periodic */ 882 OWRITE4(sc, OHCI_PERIODIC_START, per); 883 884 if (sc->sc_flags & OHCIF_SUPERIO) { 885 /* no overcurrent protection */ 886 desca |= OHCI_NOCP; 887 /* 888 * Clear NoPowerSwitching and PowerOnToPowerGoodTime meaning 889 * that 890 * - ports are always power switched 891 * - don't wait for powered root hub port 892 */ 893 desca &= ~(__SHIFTIN(0xff, OHCI_POTPGT_MASK) | OHCI_NPS); 894 } 895 896 /* Fiddle the No OverCurrent Protection bit to avoid chip bug. */ 897 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca | OHCI_NOCP); 898 OWRITE4(sc, OHCI_RH_STATUS, OHCI_LPSC); /* Enable port power */ 899 usb_delay_ms(&sc->sc_bus, OHCI_ENABLE_POWER_DELAY); 900 OWRITE4(sc, OHCI_RH_DESCRIPTOR_A, desca); 901 902 /* 903 * The AMD756 requires a delay before re-reading the register, 904 * otherwise it will occasionally report 0 ports. 905 */ 906 sc->sc_noport = 0; 907 for (i = 0; i < 10 && sc->sc_noport == 0; i++) { 908 usb_delay_ms(&sc->sc_bus, OHCI_READ_DESC_DELAY); 909 sc->sc_noport = OHCI_GET_NDP(OREAD4(sc, OHCI_RH_DESCRIPTOR_A)); 910 } 911 912 #ifdef OHCI_DEBUG 913 if (ohcidebug > 5) 914 ohci_dumpregs(sc); 915 #endif 916 917 /* Set up the bus struct. */ 918 sc->sc_bus.ub_methods = &ohci_bus_methods; 919 sc->sc_bus.ub_pipesize = sizeof(struct ohci_pipe); 920 921 sc->sc_control = sc->sc_intre = 0; 922 923 /* Finally, turn on interrupts. */ 924 DPRINTF("enabling %#x", sc->sc_eintrs | OHCI_MIE, 0, 0, 0); 925 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_eintrs | OHCI_MIE); 926 927 return 0; 928 929 bad5: 930 for (i = 0; i < OHCI_NO_EDS; i++) 931 ohci_free_sed(sc, sc->sc_eds[i]); 932 bad4: 933 ohci_free_sed(sc, sc->sc_isoc_head); 934 bad3: 935 ohci_free_sed(sc, sc->sc_bulk_head); 936 bad2: 937 ohci_free_sed(sc, sc->sc_ctrl_head); 938 bad1: 939 usb_freemem(&sc->sc_bus, &sc->sc_hccadma); 940 sc->sc_hcca = NULL; 941 return err; 942 } 943 944 struct usbd_xfer * 945 ohci_allocx(struct usbd_bus *bus, unsigned int nframes) 946 { 947 ohci_softc_t *sc = OHCI_BUS2SC(bus); 948 struct usbd_xfer *xfer; 949 950 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 951 if (xfer != NULL) { 952 memset(xfer, 0, sizeof(struct ohci_xfer)); 953 #ifdef DIAGNOSTIC 954 xfer->ux_state = XFER_BUSY; 955 #endif 956 } 957 return xfer; 958 } 959 960 void 961 ohci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 962 { 963 ohci_softc_t *sc = OHCI_BUS2SC(bus); 964 965 KASSERTMSG(xfer->ux_state == XFER_BUSY, 966 "xfer=%p not busy, 0x%08x\n", xfer, xfer->ux_state); 967 #ifdef DIAGNOSTIC 968 xfer->ux_state = XFER_FREE; 969 #endif 970 pool_cache_put(sc->sc_xferpool, xfer); 971 } 972 973 Static void 974 ohci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 975 { 976 ohci_softc_t *sc = OHCI_BUS2SC(bus); 977 978 *lock = &sc->sc_lock; 979 } 980 981 /* 982 * Shut down the controller when the system is going down. 983 */ 984 bool 985 ohci_shutdown(device_t self, int flags) 986 { 987 ohci_softc_t *sc = device_private(self); 988 989 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 990 991 DPRINTF("stopping the HC", 0, 0, 0, 0); 992 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 993 return true; 994 } 995 996 bool 997 ohci_resume(device_t dv, const pmf_qual_t *qual) 998 { 999 ohci_softc_t *sc = device_private(dv); 1000 uint32_t ctl; 1001 1002 mutex_spin_enter(&sc->sc_intr_lock); 1003 sc->sc_bus.ub_usepolling++; 1004 mutex_spin_exit(&sc->sc_intr_lock); 1005 1006 /* Some broken BIOSes do not recover these values */ 1007 OWRITE4(sc, OHCI_HCCA, DMAADDR(&sc->sc_hccadma, 0)); 1008 OWRITE4(sc, OHCI_CONTROL_HEAD_ED, 1009 sc->sc_ctrl_head->physaddr); 1010 OWRITE4(sc, OHCI_BULK_HEAD_ED, 1011 sc->sc_bulk_head->physaddr); 1012 if (sc->sc_intre) 1013 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, sc->sc_intre & 1014 (OHCI_ALL_INTRS | OHCI_MIE)); 1015 if (sc->sc_control) 1016 ctl = sc->sc_control; 1017 else 1018 ctl = OREAD4(sc, OHCI_CONTROL); 1019 ctl |= OHCI_HCFS_RESUME; 1020 OWRITE4(sc, OHCI_CONTROL, ctl); 1021 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 1022 ctl = (ctl & ~OHCI_HCFS_MASK) | OHCI_HCFS_OPERATIONAL; 1023 OWRITE4(sc, OHCI_CONTROL, ctl); 1024 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 1025 sc->sc_control = sc->sc_intre = 0; 1026 1027 mutex_spin_enter(&sc->sc_intr_lock); 1028 sc->sc_bus.ub_usepolling--; 1029 mutex_spin_exit(&sc->sc_intr_lock); 1030 1031 return true; 1032 } 1033 1034 bool 1035 ohci_suspend(device_t dv, const pmf_qual_t *qual) 1036 { 1037 ohci_softc_t *sc = device_private(dv); 1038 uint32_t ctl; 1039 1040 mutex_spin_enter(&sc->sc_intr_lock); 1041 sc->sc_bus.ub_usepolling++; 1042 mutex_spin_exit(&sc->sc_intr_lock); 1043 1044 ctl = OREAD4(sc, OHCI_CONTROL) & ~OHCI_HCFS_MASK; 1045 if (sc->sc_control == 0) { 1046 /* 1047 * Preserve register values, in case that BIOS 1048 * does not recover them. 1049 */ 1050 sc->sc_control = ctl; 1051 sc->sc_intre = OREAD4(sc, 1052 OHCI_INTERRUPT_ENABLE); 1053 } 1054 ctl |= OHCI_HCFS_SUSPEND; 1055 OWRITE4(sc, OHCI_CONTROL, ctl); 1056 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1057 1058 mutex_spin_enter(&sc->sc_intr_lock); 1059 sc->sc_bus.ub_usepolling--; 1060 mutex_spin_exit(&sc->sc_intr_lock); 1061 1062 return true; 1063 } 1064 1065 #ifdef OHCI_DEBUG 1066 void 1067 ohci_dumpregs(ohci_softc_t *sc) 1068 { 1069 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1070 1071 DPRINTF("rev=0x%08x control=0x%08x command=0x%08x", 1072 OREAD4(sc, OHCI_REVISION), 1073 OREAD4(sc, OHCI_CONTROL), 1074 OREAD4(sc, OHCI_COMMAND_STATUS), 0); 1075 DPRINTF(" intrstat=0x%08x intre=0x%08x intrd=0x%08x", 1076 OREAD4(sc, OHCI_INTERRUPT_STATUS), 1077 OREAD4(sc, OHCI_INTERRUPT_ENABLE), 1078 OREAD4(sc, OHCI_INTERRUPT_DISABLE), 0); 1079 DPRINTF(" hcca=0x%08x percur=0x%08x ctrlhd=0x%08x", 1080 OREAD4(sc, OHCI_HCCA), 1081 OREAD4(sc, OHCI_PERIOD_CURRENT_ED), 1082 OREAD4(sc, OHCI_CONTROL_HEAD_ED), 0); 1083 DPRINTF(" ctrlcur=0x%08x bulkhd=0x%08x bulkcur=0x%08x", 1084 OREAD4(sc, OHCI_CONTROL_CURRENT_ED), 1085 OREAD4(sc, OHCI_BULK_HEAD_ED), 1086 OREAD4(sc, OHCI_BULK_CURRENT_ED) ,0); 1087 DPRINTF(" done=0x%08x fmival=0x%08x fmrem=0x%08x", 1088 OREAD4(sc, OHCI_DONE_HEAD), 1089 OREAD4(sc, OHCI_FM_INTERVAL), 1090 OREAD4(sc, OHCI_FM_REMAINING), 0); 1091 DPRINTF(" fmnum=0x%08x perst=0x%08x lsthrs=0x%08x", 1092 OREAD4(sc, OHCI_FM_NUMBER), 1093 OREAD4(sc, OHCI_PERIODIC_START), 1094 OREAD4(sc, OHCI_LS_THRESHOLD), 0); 1095 DPRINTF(" desca=0x%08x descb=0x%08x stat=0x%08x", 1096 OREAD4(sc, OHCI_RH_DESCRIPTOR_A), 1097 OREAD4(sc, OHCI_RH_DESCRIPTOR_B), 1098 OREAD4(sc, OHCI_RH_STATUS), 0); 1099 DPRINTF(" port1=0x%08x port2=0x%08x", 1100 OREAD4(sc, OHCI_RH_PORT_STATUS(1)), 1101 OREAD4(sc, OHCI_RH_PORT_STATUS(2)), 0, 0); 1102 DPRINTF(" HCCA: frame_number=0x%04x done_head=0x%08x", 1103 O32TOH(sc->sc_hcca->hcca_frame_number), 1104 O32TOH(sc->sc_hcca->hcca_done_head), 0, 0); 1105 } 1106 #endif 1107 1108 Static int ohci_intr1(ohci_softc_t *); 1109 1110 int 1111 ohci_intr(void *p) 1112 { 1113 ohci_softc_t *sc = p; 1114 int ret = 0; 1115 1116 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1117 1118 if (sc == NULL) 1119 return 0; 1120 1121 mutex_spin_enter(&sc->sc_intr_lock); 1122 1123 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 1124 goto done; 1125 1126 /* If we get an interrupt while polling, then just ignore it. */ 1127 if (sc->sc_bus.ub_usepolling) { 1128 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 1129 /* for level triggered intrs, should do something to ack */ 1130 OWRITE4(sc, OHCI_INTERRUPT_STATUS, 1131 OREAD4(sc, OHCI_INTERRUPT_STATUS)); 1132 1133 goto done; 1134 } 1135 1136 ret = ohci_intr1(sc); 1137 1138 done: 1139 mutex_spin_exit(&sc->sc_intr_lock); 1140 return ret; 1141 } 1142 1143 Static int 1144 ohci_intr1(ohci_softc_t *sc) 1145 { 1146 uint32_t intrs, eintrs; 1147 1148 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1149 1150 /* In case the interrupt occurs before initialization has completed. */ 1151 if (sc == NULL || sc->sc_hcca == NULL) { 1152 #ifdef DIAGNOSTIC 1153 printf("ohci_intr: sc->sc_hcca == NULL\n"); 1154 #endif 1155 return 0; 1156 } 1157 1158 KASSERT(mutex_owned(&sc->sc_intr_lock)); 1159 1160 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1161 if (!intrs) 1162 return 0; 1163 1164 OWRITE4(sc, OHCI_INTERRUPT_STATUS, intrs & ~(OHCI_MIE|OHCI_WDH)); /* Acknowledge */ 1165 eintrs = intrs & sc->sc_eintrs; 1166 DPRINTFN(7, "sc=%p", sc, 0, 0, 0); 1167 DPRINTFN(7, "intrs=%#x(%#x) eintrs=%#x(%#x)", 1168 intrs, OREAD4(sc, OHCI_INTERRUPT_STATUS), eintrs, 1169 sc->sc_eintrs); 1170 1171 if (!eintrs) { 1172 return 0; 1173 } 1174 1175 if (eintrs & OHCI_SO) { 1176 sc->sc_overrun_cnt++; 1177 if (usbd_ratecheck(&sc->sc_overrun_ntc)) { 1178 printf("%s: %u scheduling overruns\n", 1179 device_xname(sc->sc_dev), sc->sc_overrun_cnt); 1180 sc->sc_overrun_cnt = 0; 1181 } 1182 /* XXX do what */ 1183 eintrs &= ~OHCI_SO; 1184 } 1185 if (eintrs & OHCI_WDH) { 1186 /* 1187 * We block the interrupt below, and reenable it later from 1188 * ohci_softintr(). 1189 */ 1190 usb_schedsoftintr(&sc->sc_bus); 1191 } 1192 if (eintrs & OHCI_RD) { 1193 printf("%s: resume detect\n", device_xname(sc->sc_dev)); 1194 /* XXX process resume detect */ 1195 } 1196 if (eintrs & OHCI_UE) { 1197 printf("%s: unrecoverable error, controller halted\n", 1198 device_xname(sc->sc_dev)); 1199 OWRITE4(sc, OHCI_CONTROL, OHCI_HCFS_RESET); 1200 /* XXX what else */ 1201 } 1202 if (eintrs & OHCI_RHSC) { 1203 /* 1204 * We block the interrupt below, and reenable it later from 1205 * a timeout. 1206 */ 1207 softint_schedule(sc->sc_rhsc_si); 1208 } 1209 1210 if (eintrs != 0) { 1211 /* Block unprocessed interrupts. */ 1212 OWRITE4(sc, OHCI_INTERRUPT_DISABLE, eintrs); 1213 sc->sc_eintrs &= ~eintrs; 1214 DPRINTF("sc %p blocking intrs 0x%x", sc, eintrs, 0, 0); 1215 } 1216 1217 return 1; 1218 } 1219 1220 void 1221 ohci_rhsc_enable(void *v_sc) 1222 { 1223 ohci_softc_t *sc = v_sc; 1224 1225 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1226 DPRINTF("sc %p", sc, 0, 0, 0); 1227 mutex_spin_enter(&sc->sc_intr_lock); 1228 sc->sc_eintrs |= OHCI_RHSC; 1229 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_RHSC); 1230 mutex_spin_exit(&sc->sc_intr_lock); 1231 } 1232 1233 #ifdef OHCI_DEBUG 1234 const char *ohci_cc_strs[] = { 1235 "NO_ERROR", 1236 "CRC", 1237 "BIT_STUFFING", 1238 "DATA_TOGGLE_MISMATCH", 1239 "STALL", 1240 "DEVICE_NOT_RESPONDING", 1241 "PID_CHECK_FAILURE", 1242 "UNEXPECTED_PID", 1243 "DATA_OVERRUN", 1244 "DATA_UNDERRUN", 1245 "BUFFER_OVERRUN", 1246 "BUFFER_UNDERRUN", 1247 "reserved", 1248 "reserved", 1249 "NOT_ACCESSED", 1250 "NOT_ACCESSED", 1251 }; 1252 #endif 1253 1254 void 1255 ohci_softintr(void *v) 1256 { 1257 struct usbd_bus *bus = v; 1258 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1259 ohci_soft_itd_t *sitd, *sidone, *sitdnext; 1260 ohci_soft_td_t *std, *sdone, *stdnext; 1261 struct usbd_xfer *xfer; 1262 struct ohci_pipe *opipe; 1263 int len, cc; 1264 int i, j, actlen, iframes, uedir; 1265 ohci_physaddr_t done; 1266 1267 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1268 1269 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1270 1271 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1272 sizeof(sc->sc_hcca->hcca_done_head), 1273 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1274 done = O32TOH(sc->sc_hcca->hcca_done_head) & ~OHCI_DONE_INTRS; 1275 sc->sc_hcca->hcca_done_head = 0; 1276 usb_syncmem(&sc->sc_hccadma, offsetof(struct ohci_hcca, hcca_done_head), 1277 sizeof(sc->sc_hcca->hcca_done_head), 1278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1279 OWRITE4(sc, OHCI_INTERRUPT_STATUS, OHCI_WDH); 1280 sc->sc_eintrs |= OHCI_WDH; 1281 OWRITE4(sc, OHCI_INTERRUPT_ENABLE, OHCI_WDH); 1282 1283 /* Reverse the done list. */ 1284 for (sdone = NULL, sidone = NULL; done != 0; ) { 1285 std = ohci_hash_find_td(sc, done); 1286 if (std != NULL) { 1287 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1288 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1289 std->dnext = sdone; 1290 done = O32TOH(std->td.td_nexttd); 1291 sdone = std; 1292 DPRINTFN(10, "add TD %p", std, 0, 0, 0); 1293 continue; 1294 } 1295 sitd = ohci_hash_find_itd(sc, done); 1296 if (sitd != NULL) { 1297 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1298 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1299 sitd->dnext = sidone; 1300 done = O32TOH(sitd->itd.itd_nextitd); 1301 sidone = sitd; 1302 DPRINTFN(5, "add ITD %p", sitd, 0, 0, 0); 1303 continue; 1304 } 1305 device_printf(sc->sc_dev, "WARNING: addr 0x%08lx not found\n", 1306 (u_long)done); 1307 break; 1308 } 1309 1310 DPRINTFN(10, "sdone=%p sidone=%p", sdone, sidone, 0, 0); 1311 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1312 #ifdef OHCI_DEBUG 1313 if (ohcidebug > 10) { 1314 for (std = sdone; std; std = std->dnext) 1315 ohci_dump_td(sc, std); 1316 } 1317 #endif 1318 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1319 1320 for (std = sdone; std; std = stdnext) { 1321 xfer = std->xfer; 1322 stdnext = std->dnext; 1323 DPRINTFN(10, "std=%p xfer=%p hcpriv=%p", std, xfer, 1324 xfer ? xfer->ux_hcpriv : 0, 0); 1325 if (xfer == NULL) { 1326 /* 1327 * xfer == NULL: There seems to be no xfer associated 1328 * with this TD. It is tailp that happened to end up on 1329 * the done queue. 1330 * Shouldn't happen, but some chips are broken(?). 1331 */ 1332 continue; 1333 } 1334 if (xfer->ux_status == USBD_CANCELLED || 1335 xfer->ux_status == USBD_TIMEOUT) { 1336 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1337 /* Handled by abort routine. */ 1338 continue; 1339 } 1340 callout_stop(&xfer->ux_callout); 1341 1342 len = std->len; 1343 if (std->td.td_cbp != 0) 1344 len -= O32TOH(std->td.td_be) - 1345 O32TOH(std->td.td_cbp) + 1; 1346 DPRINTFN(10, "len=%d, flags=0x%x", len, std->flags, 0, 0); 1347 if (std->flags & OHCI_ADD_LEN) 1348 xfer->ux_actlen += len; 1349 1350 cc = OHCI_TD_GET_CC(O32TOH(std->td.td_flags)); 1351 if (cc == OHCI_CC_NO_ERROR) { 1352 if (std->flags & OHCI_CALL_DONE) { 1353 xfer->ux_status = USBD_NORMAL_COMPLETION; 1354 usb_transfer_complete(xfer); 1355 } 1356 ohci_free_std(sc, std); 1357 } else { 1358 /* 1359 * Endpoint is halted. First unlink all the TDs 1360 * belonging to the failed transfer, and then restart 1361 * the endpoint. 1362 */ 1363 ohci_soft_td_t *p, *n; 1364 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1365 1366 DPRINTFN(15, "error cc=%d", 1367 OHCI_TD_GET_CC(O32TOH(std->td.td_flags)), 0, 0, 0); 1368 1369 /* remove TDs */ 1370 for (p = std; p->xfer == xfer; p = n) { 1371 n = p->nexttd; 1372 ohci_free_std(sc, p); 1373 } 1374 1375 /* clear halt */ 1376 opipe->sed->ed.ed_headp = HTOO32(p->physaddr); 1377 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 1378 1379 if (cc == OHCI_CC_STALL) 1380 xfer->ux_status = USBD_STALLED; 1381 else 1382 xfer->ux_status = USBD_IOERROR; 1383 usb_transfer_complete(xfer); 1384 } 1385 } 1386 DPRINTFN(10, "--- dump start ---", 0, 0, 0, 0); 1387 #ifdef OHCI_DEBUG 1388 if (ohcidebug > 10) { 1389 DPRINTFN(10, "ITD done", 0, 0, 0, 0); 1390 for (sitd = sidone; sitd; sitd = sitd->dnext) 1391 ohci_dump_itd(sc, sitd); 1392 } 1393 #endif 1394 DPRINTFN(10, "--- dump end ---", 0, 0, 0, 0); 1395 1396 for (sitd = sidone; sitd != NULL; sitd = sitdnext) { 1397 xfer = sitd->xfer; 1398 sitdnext = sitd->dnext; 1399 DPRINTFN(1, "sitd=%p xfer=%p hcpriv=%p", sitd, xfer, 1400 xfer ? xfer->ux_hcpriv : 0, 0); 1401 if (xfer == NULL) 1402 continue; 1403 if (xfer->ux_status == USBD_CANCELLED || 1404 xfer->ux_status == USBD_TIMEOUT) { 1405 DPRINTF("cancel/timeout %p", xfer, 0, 0, 0); 1406 /* Handled by abort routine. */ 1407 continue; 1408 } 1409 KASSERT(!sitd->isdone); 1410 #ifdef DIAGNOSTIC 1411 sitd->isdone = 1; 1412 #endif 1413 if (sitd->flags & OHCI_CALL_DONE) { 1414 ohci_soft_itd_t *next; 1415 1416 opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1417 opipe->isoc.inuse -= xfer->ux_nframes; 1418 uedir = UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc-> 1419 bEndpointAddress); 1420 xfer->ux_status = USBD_NORMAL_COMPLETION; 1421 actlen = 0; 1422 for (i = 0, sitd = xfer->ux_hcpriv;; 1423 sitd = next) { 1424 next = sitd->nextitd; 1425 if (OHCI_ITD_GET_CC(O32TOH(sitd-> 1426 itd.itd_flags)) != OHCI_CC_NO_ERROR) 1427 xfer->ux_status = USBD_IOERROR; 1428 /* For input, update frlengths with actual */ 1429 /* XXX anything necessary for output? */ 1430 if (uedir == UE_DIR_IN && 1431 xfer->ux_status == USBD_NORMAL_COMPLETION) { 1432 iframes = OHCI_ITD_GET_FC(O32TOH( 1433 sitd->itd.itd_flags)); 1434 for (j = 0; j < iframes; i++, j++) { 1435 len = O16TOH(sitd-> 1436 itd.itd_offset[j]); 1437 if ((OHCI_ITD_PSW_GET_CC(len) & 1438 OHCI_CC_NOT_ACCESSED_MASK) 1439 == OHCI_CC_NOT_ACCESSED) 1440 len = 0; 1441 else 1442 len = OHCI_ITD_PSW_LENGTH(len); 1443 xfer->ux_frlengths[i] = len; 1444 actlen += len; 1445 } 1446 } 1447 if (sitd->flags & OHCI_CALL_DONE) 1448 break; 1449 ohci_free_sitd(sc, sitd); 1450 } 1451 ohci_free_sitd(sc, sitd); 1452 if (uedir == UE_DIR_IN && 1453 xfer->ux_status == USBD_NORMAL_COMPLETION) 1454 xfer->ux_actlen = actlen; 1455 xfer->ux_hcpriv = NULL; 1456 1457 usb_transfer_complete(xfer); 1458 } 1459 } 1460 1461 if (sc->sc_softwake) { 1462 sc->sc_softwake = 0; 1463 cv_broadcast(&sc->sc_softwake_cv); 1464 } 1465 1466 DPRINTFN(10, "done", 0, 0, 0, 0); 1467 } 1468 1469 void 1470 ohci_device_ctrl_done(struct usbd_xfer *xfer) 1471 { 1472 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1473 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1474 int len = UGETW(xfer->ux_request.wLength); 1475 int isread = (xfer->ux_request.bmRequestType & UT_READ); 1476 1477 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1478 DPRINTFN(10, "xfer=%p", xfer, 0, 0, 0); 1479 1480 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1481 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 1482 1483 if (len) 1484 usb_syncmem(&xfer->ux_dmabuf, 0, len, 1485 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1486 usb_syncmem(&opipe->ctrl.reqdma, 0, 1487 sizeof(usb_device_request_t), BUS_DMASYNC_POSTWRITE); 1488 } 1489 1490 void 1491 ohci_device_intr_done(struct usbd_xfer *xfer) 1492 { 1493 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 1494 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1495 ohci_soft_ed_t *sed = opipe->sed; 1496 ohci_soft_td_t *data, *tail; 1497 int isread = 1498 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1499 1500 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1501 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1502 1503 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1504 1505 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1506 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1507 if (xfer->ux_pipe->up_repeat) { 1508 data = opipe->tail.td; 1509 tail = ohci_alloc_std(sc); /* XXX should reuse TD */ 1510 if (tail == NULL) { 1511 xfer->ux_status = USBD_NOMEM; 1512 return; 1513 } 1514 tail->xfer = NULL; 1515 1516 data->td.td_flags = HTOO32( 1517 OHCI_TD_IN | OHCI_TD_NOCC | 1518 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 1519 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 1520 data->td.td_flags |= HTOO32(OHCI_TD_R); 1521 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 1522 data->nexttd = tail; 1523 data->td.td_nexttd = HTOO32(tail->physaddr); 1524 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + 1525 xfer->ux_length - 1); 1526 data->len = xfer->ux_length; 1527 data->xfer = xfer; 1528 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 1529 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 1530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1531 xfer->ux_hcpriv = data; 1532 xfer->ux_actlen = 0; 1533 1534 sed->ed.ed_tailp = HTOO32(tail->physaddr); 1535 usb_syncmem(&sed->dma, 1536 sed->offs + offsetof(ohci_ed_t, ed_tailp), 1537 sizeof(sed->ed.ed_tailp), 1538 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1539 opipe->tail.td = tail; 1540 } 1541 } 1542 1543 void 1544 ohci_device_bulk_done(struct usbd_xfer *xfer) 1545 { 1546 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 1547 1548 int isread = 1549 (UE_GET_DIR(xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress) == UE_DIR_IN); 1550 1551 KASSERT(mutex_owned(&sc->sc_lock)); 1552 1553 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1554 DPRINTFN(10, "xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 1555 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 1556 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1557 } 1558 1559 Static void 1560 ohci_rhsc_softint(void *arg) 1561 { 1562 ohci_softc_t *sc = arg; 1563 1564 mutex_enter(&sc->sc_lock); 1565 1566 ohci_rhsc(sc, sc->sc_intrxfer); 1567 1568 /* Do not allow RHSC interrupts > 1 per second */ 1569 callout_reset(&sc->sc_tmo_rhsc, hz, ohci_rhsc_enable, sc); 1570 1571 mutex_exit(&sc->sc_lock); 1572 } 1573 1574 void 1575 ohci_rhsc(ohci_softc_t *sc, struct usbd_xfer *xfer) 1576 { 1577 u_char *p; 1578 int i, m; 1579 int hstatus __unused; 1580 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1581 1582 KASSERT(mutex_owned(&sc->sc_lock)); 1583 1584 hstatus = OREAD4(sc, OHCI_RH_STATUS); 1585 DPRINTF("sc=%p xfer=%p hstatus=0x%08x", sc, xfer, hstatus, 0); 1586 1587 if (xfer == NULL) { 1588 /* Just ignore the change. */ 1589 return; 1590 } 1591 1592 p = xfer->ux_buf; 1593 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 1594 memset(p, 0, xfer->ux_length); 1595 for (i = 1; i <= m; i++) { 1596 /* Pick out CHANGE bits from the status reg. */ 1597 if (OREAD4(sc, OHCI_RH_PORT_STATUS(i)) >> 16) 1598 p[i/8] |= 1 << (i%8); 1599 } 1600 DPRINTF("change=0x%02x", *p, 0, 0, 0); 1601 xfer->ux_actlen = xfer->ux_length; 1602 xfer->ux_status = USBD_NORMAL_COMPLETION; 1603 1604 usb_transfer_complete(xfer); 1605 } 1606 1607 void 1608 ohci_root_intr_done(struct usbd_xfer *xfer) 1609 { 1610 } 1611 1612 /* 1613 * Wait here until controller claims to have an interrupt. 1614 * Then call ohci_intr and return. Use timeout to avoid waiting 1615 * too long. 1616 */ 1617 void 1618 ohci_waitintr(ohci_softc_t *sc, struct usbd_xfer *xfer) 1619 { 1620 int timo; 1621 uint32_t intrs; 1622 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1623 1624 mutex_enter(&sc->sc_lock); 1625 1626 xfer->ux_status = USBD_IN_PROGRESS; 1627 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1628 usb_delay_ms(&sc->sc_bus, 1); 1629 if (sc->sc_dying) 1630 break; 1631 intrs = OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs; 1632 DPRINTFN(15, "intrs 0x%04x", intrs, 0, 0, 0); 1633 #ifdef OHCI_DEBUG 1634 if (ohcidebug > 15) 1635 ohci_dumpregs(sc); 1636 #endif 1637 if (intrs) { 1638 mutex_spin_enter(&sc->sc_intr_lock); 1639 ohci_intr1(sc); 1640 mutex_spin_exit(&sc->sc_intr_lock); 1641 if (xfer->ux_status != USBD_IN_PROGRESS) 1642 goto done; 1643 } 1644 } 1645 1646 /* Timeout */ 1647 DPRINTF("timeout", 0, 0, 0, 0); 1648 xfer->ux_status = USBD_TIMEOUT; 1649 usb_transfer_complete(xfer); 1650 1651 /* XXX should free TD */ 1652 1653 done: 1654 mutex_exit(&sc->sc_lock); 1655 } 1656 1657 void 1658 ohci_poll(struct usbd_bus *bus) 1659 { 1660 ohci_softc_t *sc = OHCI_BUS2SC(bus); 1661 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1662 1663 #ifdef OHCI_DEBUG 1664 static int last; 1665 int new; 1666 new = OREAD4(sc, OHCI_INTERRUPT_STATUS); 1667 if (new != last) { 1668 DPRINTFN(10, "intrs=0x%04x", new, 0, 0, 0); 1669 last = new; 1670 } 1671 #endif 1672 sc->sc_eintrs |= OHCI_WDH; 1673 if (OREAD4(sc, OHCI_INTERRUPT_STATUS) & sc->sc_eintrs) { 1674 mutex_spin_enter(&sc->sc_intr_lock); 1675 ohci_intr1(sc); 1676 mutex_spin_exit(&sc->sc_intr_lock); 1677 } 1678 } 1679 1680 /* 1681 * Add an ED to the schedule. Called with USB lock held. 1682 */ 1683 Static void 1684 ohci_add_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1685 { 1686 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1687 DPRINTFN(8, "sed=%p head=%p", sed, head, 0, 0); 1688 1689 KASSERT(mutex_owned(&sc->sc_lock)); 1690 1691 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1692 sizeof(head->ed.ed_nexted), 1693 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1694 sed->next = head->next; 1695 sed->ed.ed_nexted = head->ed.ed_nexted; 1696 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1697 sizeof(sed->ed.ed_nexted), 1698 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1699 head->next = sed; 1700 head->ed.ed_nexted = HTOO32(sed->physaddr); 1701 usb_syncmem(&head->dma, head->offs + offsetof(ohci_ed_t, ed_nexted), 1702 sizeof(head->ed.ed_nexted), 1703 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1704 } 1705 1706 /* 1707 * Remove an ED from the schedule. Called with USB lock held. 1708 */ 1709 Static void 1710 ohci_rem_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed, ohci_soft_ed_t *head) 1711 { 1712 ohci_soft_ed_t *p; 1713 1714 KASSERT(mutex_owned(&sc->sc_lock)); 1715 1716 /* XXX */ 1717 for (p = head; p != NULL && p->next != sed; p = p->next) 1718 ; 1719 KASSERT(p != NULL); 1720 1721 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_nexted), 1722 sizeof(sed->ed.ed_nexted), 1723 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1724 p->next = sed->next; 1725 p->ed.ed_nexted = sed->ed.ed_nexted; 1726 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 1727 sizeof(p->ed.ed_nexted), 1728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1729 } 1730 1731 /* 1732 * When a transfer is completed the TD is added to the done queue by 1733 * the host controller. This queue is the processed by software. 1734 * Unfortunately the queue contains the physical address of the TD 1735 * and we have no simple way to translate this back to a kernel address. 1736 * To make the translation possible (and fast) we use a hash table of 1737 * TDs currently in the schedule. The physical address is used as the 1738 * hash value. 1739 */ 1740 1741 #define HASH(a) (((a) >> 4) % OHCI_HASH_SIZE) 1742 /* Called with USB lock held. */ 1743 void 1744 ohci_hash_add_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1745 { 1746 int h = HASH(std->physaddr); 1747 1748 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1749 1750 LIST_INSERT_HEAD(&sc->sc_hash_tds[h], std, hnext); 1751 } 1752 1753 /* Called with USB lock held. */ 1754 void 1755 ohci_hash_rem_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1756 { 1757 1758 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1759 1760 LIST_REMOVE(std, hnext); 1761 } 1762 1763 ohci_soft_td_t * 1764 ohci_hash_find_td(ohci_softc_t *sc, ohci_physaddr_t a) 1765 { 1766 int h = HASH(a); 1767 ohci_soft_td_t *std; 1768 1769 for (std = LIST_FIRST(&sc->sc_hash_tds[h]); 1770 std != NULL; 1771 std = LIST_NEXT(std, hnext)) 1772 if (std->physaddr == a) 1773 return std; 1774 return NULL; 1775 } 1776 1777 /* Called with USB lock held. */ 1778 void 1779 ohci_hash_add_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1780 { 1781 int h = HASH(sitd->physaddr); 1782 1783 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1784 1785 KASSERT(mutex_owned(&sc->sc_lock)); 1786 1787 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1788 0, 0); 1789 1790 LIST_INSERT_HEAD(&sc->sc_hash_itds[h], sitd, hnext); 1791 } 1792 1793 /* Called with USB lock held. */ 1794 void 1795 ohci_hash_rem_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1796 { 1797 1798 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1799 1800 KASSERT(mutex_owned(&sc->sc_lock)); 1801 1802 DPRINTFN(10, "sitd=%p physaddr=0x%08lx", sitd, (u_long)sitd->physaddr, 1803 0, 0); 1804 1805 LIST_REMOVE(sitd, hnext); 1806 } 1807 1808 ohci_soft_itd_t * 1809 ohci_hash_find_itd(ohci_softc_t *sc, ohci_physaddr_t a) 1810 { 1811 int h = HASH(a); 1812 ohci_soft_itd_t *sitd; 1813 1814 for (sitd = LIST_FIRST(&sc->sc_hash_itds[h]); 1815 sitd != NULL; 1816 sitd = LIST_NEXT(sitd, hnext)) 1817 if (sitd->physaddr == a) 1818 return sitd; 1819 return NULL; 1820 } 1821 1822 void 1823 ohci_timeout(void *addr) 1824 { 1825 struct usbd_xfer *xfer = addr; 1826 struct ohci_xfer *oxfer = OHCI_XFER2OXFER(xfer); 1827 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1828 1829 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1830 DPRINTF("oxfer=%p", oxfer, 0, 0, 0); 1831 1832 if (sc->sc_dying) { 1833 mutex_enter(&sc->sc_lock); 1834 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1835 mutex_exit(&sc->sc_lock); 1836 return; 1837 } 1838 1839 /* Execute the abort in a process context. */ 1840 usb_init_task(&oxfer->abort_task, ohci_timeout_task, addr, 1841 USB_TASKQ_MPSAFE); 1842 usb_add_task(xfer->ux_pipe->up_dev, &oxfer->abort_task, 1843 USB_TASKQ_HC); 1844 } 1845 1846 void 1847 ohci_timeout_task(void *addr) 1848 { 1849 struct usbd_xfer *xfer = addr; 1850 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 1851 1852 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1853 1854 DPRINTF("xfer=%p", xfer, 0, 0, 0); 1855 1856 mutex_enter(&sc->sc_lock); 1857 ohci_abort_xfer(xfer, USBD_TIMEOUT); 1858 mutex_exit(&sc->sc_lock); 1859 } 1860 1861 #ifdef OHCI_DEBUG 1862 void 1863 ohci_dump_tds(ohci_softc_t *sc, ohci_soft_td_t *std) 1864 { 1865 for (; std; std = std->nexttd) 1866 ohci_dump_td(sc, std); 1867 } 1868 1869 void 1870 ohci_dump_td(ohci_softc_t *sc, ohci_soft_td_t *std) 1871 { 1872 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1873 1874 usb_syncmem(&std->dma, std->offs, sizeof(std->td), 1875 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1876 1877 uint32_t flags = O32TOH(std->td.td_flags); 1878 DPRINTF("TD(%p) at %08lx:", std, (u_long)std->physaddr, 0, 0); 1879 DPRINTF(" round=%d DP=%x DI=%x T=%x", 1880 !!(flags & OHCI_TD_R), 1881 __SHIFTOUT(flags, OHCI_TD_DP_MASK), 1882 OHCI_TD_GET_DI(flags), 1883 __SHIFTOUT(flags, OHCI_TD_TOGGLE_MASK)); 1884 DPRINTF(" EC=%d CC=%d", OHCI_TD_GET_EC(flags), OHCI_TD_GET_CC(flags), 1885 0, 0); 1886 DPRINTF(" cbp=0x%08lx nexttd=0x%08lx be=0x%08lx", 1887 (u_long)O32TOH(std->td.td_cbp), 1888 (u_long)O32TOH(std->td.td_nexttd), 1889 (u_long)O32TOH(std->td.td_be), 0); 1890 } 1891 1892 void 1893 ohci_dump_itd(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1894 { 1895 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1896 1897 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 1898 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1899 1900 uint32_t flags = O32TOH(sitd->itd.itd_flags); 1901 DPRINTF("ITD(%p) at %08lx", sitd, (u_long)sitd->physaddr, 0, 0); 1902 DPRINTF(" sf=%d di=%d fc=%d cc=%d", 1903 OHCI_ITD_GET_SF(flags), OHCI_ITD_GET_DI(flags), 1904 OHCI_ITD_GET_FC(flags), OHCI_ITD_GET_CC(flags)); 1905 DPRINTF(" bp0=0x%08x next=0x%08x be=0x%08x", 1906 O32TOH(sitd->itd.itd_bp0), 1907 O32TOH(sitd->itd.itd_nextitd), 1908 O32TOH(sitd->itd.itd_be), 0); 1909 CTASSERT(OHCI_ITD_NOFFSET == 8); 1910 DPRINTF(" offs[0] = 0x%04x offs[1] = 0x%04x " 1911 "offs[2] = 0x%04x offs[3] = 0x%04x", 1912 O16TOH(sitd->itd.itd_offset[0]), 1913 O16TOH(sitd->itd.itd_offset[1]), 1914 O16TOH(sitd->itd.itd_offset[2]), 1915 O16TOH(sitd->itd.itd_offset[3])); 1916 DPRINTF(" offs[4] = 0x%04x offs[5] = 0x%04x " 1917 "offs[6] = 0x%04x offs[7] = 0x%04x", 1918 O16TOH(sitd->itd.itd_offset[4]), 1919 O16TOH(sitd->itd.itd_offset[5]), 1920 O16TOH(sitd->itd.itd_offset[6]), 1921 O16TOH(sitd->itd.itd_offset[7])); 1922 } 1923 1924 void 1925 ohci_dump_itds(ohci_softc_t *sc, ohci_soft_itd_t *sitd) 1926 { 1927 for (; sitd; sitd = sitd->nextitd) 1928 ohci_dump_itd(sc, sitd); 1929 } 1930 1931 void 1932 ohci_dump_ed(ohci_softc_t *sc, ohci_soft_ed_t *sed) 1933 { 1934 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1935 1936 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 1937 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1938 1939 uint32_t flags = O32TOH(sed->ed.ed_flags); 1940 DPRINTF("ED(%p) at 0x%08lx:", sed, sed->physaddr, 0, 0); 1941 DPRINTF(" addr=%d endpt=%d maxp=%d", 1942 OHCI_ED_GET_FA(flags), 1943 OHCI_ED_GET_EN(flags), 1944 OHCI_ED_GET_MAXP(flags), 1945 0); 1946 DPRINTF(" dir=%d speed=%d skip=%d iso=%d", 1947 __SHIFTOUT(flags, OHCI_ED_DIR_MASK), 1948 !!(flags & OHCI_ED_SPEED), 1949 !!(flags & OHCI_ED_SKIP), 1950 !!(flags & OHCI_ED_FORMAT_ISO)); 1951 DPRINTF(" tailp=0x%08lx", (u_long)O32TOH(sed->ed.ed_tailp), 1952 0, 0, 0); 1953 DPRINTF(" headp=0x%08lx nexted=0x%08lx halted=%d carry=%d", 1954 O32TOH(sed->ed.ed_headp), O32TOH(sed->ed.ed_nexted), 1955 !!(O32TOH(sed->ed.ed_headp) & OHCI_HALTED), 1956 !!(O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY)); 1957 } 1958 #endif 1959 1960 usbd_status 1961 ohci_open(struct usbd_pipe *pipe) 1962 { 1963 struct usbd_device *dev = pipe->up_dev; 1964 struct usbd_bus *bus = dev->ud_bus; 1965 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 1966 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1967 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 1968 uint8_t addr = dev->ud_addr; 1969 uint8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1970 ohci_soft_ed_t *sed; 1971 ohci_soft_td_t *std; 1972 ohci_soft_itd_t *sitd; 1973 ohci_physaddr_t tdphys; 1974 uint32_t fmt; 1975 usbd_status err = USBD_NOMEM; 1976 int ival; 1977 1978 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 1979 DPRINTFN(1, "pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1980 ed->bEndpointAddress, bus->ub_rhaddr); 1981 1982 if (sc->sc_dying) { 1983 return USBD_IOERROR; 1984 } 1985 1986 std = NULL; 1987 sed = NULL; 1988 1989 if (addr == bus->ub_rhaddr) { 1990 switch (ed->bEndpointAddress) { 1991 case USB_CONTROL_ENDPOINT: 1992 pipe->up_methods = &roothub_ctrl_methods; 1993 break; 1994 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1995 pipe->up_methods = &ohci_root_intr_methods; 1996 break; 1997 default: 1998 err = USBD_INVAL; 1999 goto bad; 2000 } 2001 } else { 2002 sed = ohci_alloc_sed(sc); 2003 if (sed == NULL) 2004 goto bad; 2005 opipe->sed = sed; 2006 if (xfertype == UE_ISOCHRONOUS) { 2007 mutex_enter(&sc->sc_lock); 2008 sitd = ohci_alloc_sitd(sc); 2009 mutex_exit(&sc->sc_lock); 2010 if (sitd == NULL) 2011 goto bad; 2012 2013 opipe->tail.itd = sitd; 2014 tdphys = sitd->physaddr; 2015 fmt = OHCI_ED_FORMAT_ISO; 2016 if (UE_GET_DIR(ed->bEndpointAddress) == UE_DIR_IN) 2017 fmt |= OHCI_ED_DIR_IN; 2018 else 2019 fmt |= OHCI_ED_DIR_OUT; 2020 } else { 2021 mutex_enter(&sc->sc_lock); 2022 std = ohci_alloc_std(sc); 2023 mutex_exit(&sc->sc_lock); 2024 if (std == NULL) 2025 goto bad; 2026 2027 opipe->tail.td = std; 2028 tdphys = std->physaddr; 2029 fmt = OHCI_ED_FORMAT_GEN | OHCI_ED_DIR_TD; 2030 } 2031 sed->ed.ed_flags = HTOO32( 2032 OHCI_ED_SET_FA(addr) | 2033 OHCI_ED_SET_EN(UE_GET_ADDR(ed->bEndpointAddress)) | 2034 (dev->ud_speed == USB_SPEED_LOW ? OHCI_ED_SPEED : 0) | 2035 fmt | 2036 OHCI_ED_SET_MAXP(UGETW(ed->wMaxPacketSize))); 2037 sed->ed.ed_headp = HTOO32(tdphys | 2038 (pipe->up_endpoint->ue_toggle ? OHCI_TOGGLECARRY : 0)); 2039 sed->ed.ed_tailp = HTOO32(tdphys); 2040 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2041 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2042 2043 switch (xfertype) { 2044 case UE_CONTROL: 2045 pipe->up_methods = &ohci_device_ctrl_methods; 2046 err = usb_allocmem(&sc->sc_bus, 2047 sizeof(usb_device_request_t), 2048 0, &opipe->ctrl.reqdma); 2049 if (err) 2050 goto bad; 2051 mutex_enter(&sc->sc_lock); 2052 ohci_add_ed(sc, sed, sc->sc_ctrl_head); 2053 mutex_exit(&sc->sc_lock); 2054 break; 2055 case UE_INTERRUPT: 2056 pipe->up_methods = &ohci_device_intr_methods; 2057 ival = pipe->up_interval; 2058 if (ival == USBD_DEFAULT_INTERVAL) 2059 ival = ed->bInterval; 2060 err = ohci_device_setintr(sc, opipe, ival); 2061 if (err) 2062 goto bad; 2063 break; 2064 case UE_ISOCHRONOUS: 2065 pipe->up_methods = &ohci_device_isoc_methods; 2066 return ohci_setup_isoc(pipe); 2067 case UE_BULK: 2068 pipe->up_methods = &ohci_device_bulk_methods; 2069 mutex_enter(&sc->sc_lock); 2070 ohci_add_ed(sc, sed, sc->sc_bulk_head); 2071 mutex_exit(&sc->sc_lock); 2072 break; 2073 } 2074 } 2075 2076 return USBD_NORMAL_COMPLETION; 2077 2078 bad: 2079 if (std != NULL) { 2080 mutex_enter(&sc->sc_lock); 2081 ohci_free_std(sc, std); 2082 mutex_exit(&sc->sc_lock); 2083 } 2084 if (sed != NULL) 2085 ohci_free_sed(sc, sed); 2086 return err; 2087 2088 } 2089 2090 /* 2091 * Close a reqular pipe. 2092 * Assumes that there are no pending transactions. 2093 */ 2094 void 2095 ohci_close_pipe(struct usbd_pipe *pipe, ohci_soft_ed_t *head) 2096 { 2097 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2098 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2099 ohci_soft_ed_t *sed = opipe->sed; 2100 2101 KASSERT(mutex_owned(&sc->sc_lock)); 2102 2103 #ifdef DIAGNOSTIC 2104 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 2105 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2106 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) { 2107 ohci_soft_td_t *std; 2108 std = ohci_hash_find_td(sc, O32TOH(sed->ed.ed_headp)); 2109 printf("ohci_close_pipe: pipe not empty sed=%p hd=0x%x " 2110 "tl=0x%x pipe=%p, std=%p\n", sed, 2111 (int)O32TOH(sed->ed.ed_headp), 2112 (int)O32TOH(sed->ed.ed_tailp), 2113 pipe, std); 2114 #ifdef OHCI_DEBUG 2115 usbd_dump_pipe(&opipe->pipe); 2116 ohci_dump_ed(sc, sed); 2117 if (std) 2118 ohci_dump_td(sc, std); 2119 #endif 2120 usb_delay_ms(&sc->sc_bus, 2); 2121 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 2122 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 2123 printf("ohci_close_pipe: pipe still not empty\n"); 2124 } 2125 #endif 2126 ohci_rem_ed(sc, sed, head); 2127 /* Make sure the host controller is not touching this ED */ 2128 usb_delay_ms(&sc->sc_bus, 1); 2129 pipe->up_endpoint->ue_toggle = 2130 (O32TOH(sed->ed.ed_headp) & OHCI_TOGGLECARRY) ? 1 : 0; 2131 ohci_free_sed(sc, opipe->sed); 2132 } 2133 2134 /* 2135 * Abort a device request. 2136 * If this routine is called at splusb() it guarantees that the request 2137 * will be removed from the hardware scheduling and that the callback 2138 * for it will be called with USBD_CANCELLED status. 2139 * It's impossible to guarantee that the requested transfer will not 2140 * have happened since the hardware runs concurrently. 2141 * If the transaction has already happened we rely on the ordinary 2142 * interrupt processing to process it. 2143 * XXX This is most probably wrong. 2144 * XXXMRG this doesn't make sense anymore. 2145 */ 2146 void 2147 ohci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 2148 { 2149 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2150 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2151 ohci_soft_ed_t *sed = opipe->sed; 2152 ohci_soft_td_t *p, *n; 2153 ohci_physaddr_t headp; 2154 int hit; 2155 int wake; 2156 2157 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2158 DPRINTF("xfer=%p pipe=%p sed=%p", xfer, opipe,sed, 0); 2159 2160 KASSERT(mutex_owned(&sc->sc_lock)); 2161 ASSERT_SLEEPABLE(); 2162 2163 if (sc->sc_dying) { 2164 /* If we're dying, just do the software part. */ 2165 xfer->ux_status = status; /* make software ignore it */ 2166 callout_halt(&xfer->ux_callout, &sc->sc_lock); 2167 usb_transfer_complete(xfer); 2168 return; 2169 } 2170 2171 /* 2172 * If an abort is already in progress then just wait for it to 2173 * complete and return. 2174 */ 2175 if (xfer->ux_hcflags & UXFER_ABORTING) { 2176 DPRINTFN(2, "already aborting", 0, 0, 0, 0); 2177 #ifdef DIAGNOSTIC 2178 if (status == USBD_TIMEOUT) 2179 printf("%s: TIMEOUT while aborting\n", __func__); 2180 #endif 2181 /* Override the status which might be USBD_TIMEOUT. */ 2182 xfer->ux_status = status; 2183 DPRINTFN(2, "waiting for abort to finish", 0, 0, 0, 0); 2184 xfer->ux_hcflags |= UXFER_ABORTWAIT; 2185 while (xfer->ux_hcflags & UXFER_ABORTING) 2186 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 2187 goto done; 2188 } 2189 xfer->ux_hcflags |= UXFER_ABORTING; 2190 2191 /* 2192 * Step 1: Make interrupt routine and hardware ignore xfer. 2193 */ 2194 xfer->ux_status = status; /* make software ignore it */ 2195 callout_stop(&xfer->ux_callout); 2196 DPRINTFN(1, "stop ed=%p", sed, 0, 0, 0); 2197 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2198 sizeof(sed->ed.ed_flags), 2199 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2200 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 2201 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2202 sizeof(sed->ed.ed_flags), 2203 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2204 2205 /* 2206 * Step 2: Wait until we know hardware has finished any possible 2207 * use of the xfer. Also make sure the soft interrupt routine 2208 * has run. 2209 */ 2210 /* Hardware finishes in 1ms */ 2211 usb_delay_ms_locked(opipe->pipe.up_dev->ud_bus, 20, &sc->sc_lock); 2212 sc->sc_softwake = 1; 2213 usb_schedsoftintr(&sc->sc_bus); 2214 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 2215 2216 /* 2217 * Step 3: Remove any vestiges of the xfer from the hardware. 2218 * The complication here is that the hardware may have executed 2219 * beyond the xfer we're trying to abort. So as we're scanning 2220 * the TDs of this xfer we check if the hardware points to 2221 * any of them. 2222 */ 2223 p = xfer->ux_hcpriv; 2224 KASSERT(p); 2225 2226 #ifdef OHCI_DEBUG 2227 DPRINTF("--- dump start ---", 0, 0, 0, 0); 2228 2229 if (ohcidebug > 1) { 2230 DPRINTF("sed:", 0, 0, 0, 0); 2231 ohci_dump_ed(sc, sed); 2232 ohci_dump_tds(sc, p); 2233 } 2234 DPRINTF("--- dump end ---", 0, 0, 0, 0); 2235 #endif 2236 headp = O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK; 2237 hit = 0; 2238 for (; p->xfer == xfer; p = n) { 2239 hit |= headp == p->physaddr; 2240 n = p->nexttd; 2241 ohci_free_std(sc, p); 2242 } 2243 /* Zap headp register if hardware pointed inside the xfer. */ 2244 if (hit) { 2245 DPRINTFN(1, "set hd=0x%08x, tl=0x%08x", (int)p->physaddr, 2246 (int)O32TOH(sed->ed.ed_tailp), 0, 0); 2247 sed->ed.ed_headp = HTOO32(p->physaddr); /* unlink TDs */ 2248 usb_syncmem(&sed->dma, 2249 sed->offs + offsetof(ohci_ed_t, ed_headp), 2250 sizeof(sed->ed.ed_headp), 2251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2252 } else { 2253 DPRINTFN(1, "no hit", 0, 0, 0, 0); 2254 } 2255 2256 /* 2257 * Step 4: Turn on hardware again. 2258 */ 2259 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2260 sizeof(sed->ed.ed_flags), 2261 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2262 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 2263 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 2264 sizeof(sed->ed.ed_flags), 2265 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2266 2267 /* 2268 * Step 5: Execute callback. 2269 */ 2270 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 2271 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2272 usb_transfer_complete(xfer); 2273 if (wake) 2274 cv_broadcast(&xfer->ux_hccv); 2275 2276 done: 2277 KASSERT(mutex_owned(&sc->sc_lock)); 2278 } 2279 2280 /* 2281 * Data structures and routines to emulate the root hub. 2282 */ 2283 Static int 2284 ohci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2285 void *buf, int buflen) 2286 { 2287 ohci_softc_t *sc = OHCI_BUS2SC(bus); 2288 usb_port_status_t ps; 2289 uint16_t len, value, index; 2290 int l, totlen = 0; 2291 int port, i; 2292 uint32_t v; 2293 2294 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2295 2296 if (sc->sc_dying) 2297 return -1; 2298 2299 DPRINTFN(4, "type=0x%02x request=%02x", req->bmRequestType, 2300 req->bRequest, 0, 0); 2301 2302 len = UGETW(req->wLength); 2303 value = UGETW(req->wValue); 2304 index = UGETW(req->wIndex); 2305 2306 #define C(x,y) ((x) | ((y) << 8)) 2307 switch (C(req->bRequest, req->bmRequestType)) { 2308 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2309 DPRINTFN(8, "wValue=0x%04x", value, 0, 0, 0); 2310 if (len == 0) 2311 break; 2312 switch (value) { 2313 case C(0, UDESC_DEVICE): { 2314 usb_device_descriptor_t devd; 2315 2316 totlen = min(buflen, sizeof(devd)); 2317 memcpy(&devd, buf, totlen); 2318 USETW(devd.idVendor, sc->sc_id_vendor); 2319 memcpy(buf, &devd, totlen); 2320 break; 2321 } 2322 case C(1, UDESC_STRING): 2323 #define sd ((usb_string_descriptor_t *)buf) 2324 /* Vendor */ 2325 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2326 break; 2327 case C(2, UDESC_STRING): 2328 /* Product */ 2329 totlen = usb_makestrdesc(sd, len, "OHCI root hub"); 2330 break; 2331 #undef sd 2332 default: 2333 /* default from usbroothub */ 2334 return buflen; 2335 } 2336 break; 2337 2338 /* Hub requests */ 2339 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2340 break; 2341 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2342 DPRINTFN(8, "UR_CLEAR_PORT_FEATURE port=%d feature=%d", 2343 index, value, 0, 0); 2344 if (index < 1 || index > sc->sc_noport) { 2345 return -1; 2346 } 2347 port = OHCI_RH_PORT_STATUS(index); 2348 switch(value) { 2349 case UHF_PORT_ENABLE: 2350 OWRITE4(sc, port, UPS_CURRENT_CONNECT_STATUS); 2351 break; 2352 case UHF_PORT_SUSPEND: 2353 OWRITE4(sc, port, UPS_OVERCURRENT_INDICATOR); 2354 break; 2355 case UHF_PORT_POWER: 2356 /* Yes, writing to the LOW_SPEED bit clears power. */ 2357 OWRITE4(sc, port, UPS_LOW_SPEED); 2358 break; 2359 case UHF_C_PORT_CONNECTION: 2360 OWRITE4(sc, port, UPS_C_CONNECT_STATUS << 16); 2361 break; 2362 case UHF_C_PORT_ENABLE: 2363 OWRITE4(sc, port, UPS_C_PORT_ENABLED << 16); 2364 break; 2365 case UHF_C_PORT_SUSPEND: 2366 OWRITE4(sc, port, UPS_C_SUSPEND << 16); 2367 break; 2368 case UHF_C_PORT_OVER_CURRENT: 2369 OWRITE4(sc, port, UPS_C_OVERCURRENT_INDICATOR << 16); 2370 break; 2371 case UHF_C_PORT_RESET: 2372 OWRITE4(sc, port, UPS_C_PORT_RESET << 16); 2373 break; 2374 default: 2375 return -1; 2376 } 2377 switch(value) { 2378 case UHF_C_PORT_CONNECTION: 2379 case UHF_C_PORT_ENABLE: 2380 case UHF_C_PORT_SUSPEND: 2381 case UHF_C_PORT_OVER_CURRENT: 2382 case UHF_C_PORT_RESET: 2383 /* Enable RHSC interrupt if condition is cleared. */ 2384 if ((OREAD4(sc, port) >> 16) == 0) 2385 ohci_rhsc_enable(sc); 2386 break; 2387 default: 2388 break; 2389 } 2390 break; 2391 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2392 if (len == 0) 2393 break; 2394 if ((value & 0xff) != 0) { 2395 return -1; 2396 } 2397 usb_hub_descriptor_t hubd; 2398 2399 totlen = min(buflen, sizeof(hubd)); 2400 memcpy(&hubd, buf, totlen); 2401 2402 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_A); 2403 hubd.bNbrPorts = sc->sc_noport; 2404 USETW(hubd.wHubCharacteristics, 2405 (v & OHCI_NPS ? UHD_PWR_NO_SWITCH : 2406 v & OHCI_PSM ? UHD_PWR_GANGED : UHD_PWR_INDIVIDUAL) 2407 /* XXX overcurrent */ 2408 ); 2409 hubd.bPwrOn2PwrGood = OHCI_GET_POTPGT(v); 2410 v = OREAD4(sc, OHCI_RH_DESCRIPTOR_B); 2411 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2412 hubd.DeviceRemovable[i++] = (uint8_t)v; 2413 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2414 totlen = min(totlen, hubd.bDescLength); 2415 memcpy(buf, &hubd, totlen); 2416 break; 2417 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2418 if (len != 4) { 2419 return -1; 2420 } 2421 memset(buf, 0, len); /* ? XXX */ 2422 totlen = len; 2423 break; 2424 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2425 DPRINTFN(8, "get port status i=%d", index, 0, 0, 0); 2426 if (index < 1 || index > sc->sc_noport) { 2427 return -1; 2428 } 2429 if (len != 4) { 2430 return -1; 2431 } 2432 v = OREAD4(sc, OHCI_RH_PORT_STATUS(index)); 2433 DPRINTFN(8, "port status=0x%04x", v, 0, 0, 0); 2434 USETW(ps.wPortStatus, v); 2435 USETW(ps.wPortChange, v >> 16); 2436 totlen = min(len, sizeof(ps)); 2437 memcpy(buf, &ps, totlen); 2438 break; 2439 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2440 return -1; 2441 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2442 break; 2443 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2444 if (index < 1 || index > sc->sc_noport) { 2445 return -1; 2446 } 2447 port = OHCI_RH_PORT_STATUS(index); 2448 switch(value) { 2449 case UHF_PORT_ENABLE: 2450 OWRITE4(sc, port, UPS_PORT_ENABLED); 2451 break; 2452 case UHF_PORT_SUSPEND: 2453 OWRITE4(sc, port, UPS_SUSPEND); 2454 break; 2455 case UHF_PORT_RESET: 2456 DPRINTFN(5, "reset port %d", index, 0, 0, 0); 2457 OWRITE4(sc, port, UPS_RESET); 2458 for (i = 0; i < 5; i++) { 2459 usb_delay_ms(&sc->sc_bus, 2460 USB_PORT_ROOT_RESET_DELAY); 2461 if (sc->sc_dying) { 2462 return -1; 2463 } 2464 if ((OREAD4(sc, port) & UPS_RESET) == 0) 2465 break; 2466 } 2467 DPRINTFN(8, "port %d reset, status = 0x%04x", index, 2468 OREAD4(sc, port), 0, 0); 2469 break; 2470 case UHF_PORT_POWER: 2471 DPRINTFN(2, "set port power %d", index, 0, 0, 0); 2472 OWRITE4(sc, port, UPS_PORT_POWER); 2473 break; 2474 default: 2475 return -1; 2476 } 2477 break; 2478 default: 2479 /* default from usbroothub */ 2480 return buflen; 2481 } 2482 2483 return totlen; 2484 } 2485 2486 Static usbd_status 2487 ohci_root_intr_transfer(struct usbd_xfer *xfer) 2488 { 2489 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2490 usbd_status err; 2491 2492 /* Insert last in queue. */ 2493 mutex_enter(&sc->sc_lock); 2494 err = usb_insert_transfer(xfer); 2495 mutex_exit(&sc->sc_lock); 2496 if (err) 2497 return err; 2498 2499 /* Pipe isn't running, start first */ 2500 return ohci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2501 } 2502 2503 Static usbd_status 2504 ohci_root_intr_start(struct usbd_xfer *xfer) 2505 { 2506 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2507 2508 if (sc->sc_dying) 2509 return USBD_IOERROR; 2510 2511 mutex_enter(&sc->sc_lock); 2512 KASSERT(sc->sc_intrxfer == NULL); 2513 sc->sc_intrxfer = xfer; 2514 mutex_exit(&sc->sc_lock); 2515 2516 return USBD_IN_PROGRESS; 2517 } 2518 2519 /* Abort a root interrupt request. */ 2520 Static void 2521 ohci_root_intr_abort(struct usbd_xfer *xfer) 2522 { 2523 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2524 2525 KASSERT(mutex_owned(&sc->sc_lock)); 2526 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2527 2528 sc->sc_intrxfer = NULL; 2529 2530 xfer->ux_status = USBD_CANCELLED; 2531 usb_transfer_complete(xfer); 2532 } 2533 2534 /* Close the root pipe. */ 2535 Static void 2536 ohci_root_intr_close(struct usbd_pipe *pipe) 2537 { 2538 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2539 2540 KASSERT(mutex_owned(&sc->sc_lock)); 2541 2542 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2543 2544 sc->sc_intrxfer = NULL; 2545 } 2546 2547 /************************/ 2548 2549 Static usbd_status 2550 ohci_device_ctrl_transfer(struct usbd_xfer *xfer) 2551 { 2552 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2553 usbd_status err; 2554 2555 /* Insert last in queue. */ 2556 mutex_enter(&sc->sc_lock); 2557 err = usb_insert_transfer(xfer); 2558 mutex_exit(&sc->sc_lock); 2559 if (err) 2560 return err; 2561 2562 /* Pipe isn't running, start first */ 2563 return ohci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2564 } 2565 2566 Static usbd_status 2567 ohci_device_ctrl_start(struct usbd_xfer *xfer) 2568 { 2569 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2570 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2571 usb_device_request_t *req = &xfer->ux_request; 2572 struct usbd_device *dev __diagused = opipe->pipe.up_dev; 2573 ohci_soft_td_t *setup, *stat, *next, *tail; 2574 ohci_soft_ed_t *sed; 2575 int isread; 2576 int len; 2577 usbd_status err; 2578 2579 2580 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2581 2582 if (sc->sc_dying) 2583 return USBD_IOERROR; 2584 2585 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 2586 2587 mutex_enter(&sc->sc_lock); 2588 2589 isread = req->bmRequestType & UT_READ; 2590 len = UGETW(req->wLength); 2591 2592 DPRINTF("type=0x%02x, request=0x%02x, " 2593 "wValue=0x%04x, wIndex=0x%04x", 2594 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2595 UGETW(req->wIndex)); 2596 DPRINTF("len=%d, addr=%d, endpt=%d", 2597 len, dev->ud_addr, 2598 opipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 2599 2600 setup = opipe->tail.td; 2601 stat = ohci_alloc_std(sc); 2602 if (stat == NULL) { 2603 err = USBD_NOMEM; 2604 goto bad1; 2605 } 2606 tail = ohci_alloc_std(sc); 2607 if (tail == NULL) { 2608 err = USBD_NOMEM; 2609 goto bad2; 2610 } 2611 tail->xfer = NULL; 2612 2613 sed = opipe->sed; 2614 opipe->ctrl.length = len; 2615 2616 KASSERTMSG(OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)) == dev->ud_addr, 2617 "address ED %d pipe %d\n", 2618 OHCI_ED_GET_FA(O32TOH(sed->ed.ed_flags)), dev->ud_addr); 2619 KASSERTMSG(OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)) == 2620 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 2621 "MPL ED %d pipe %d\n", 2622 OHCI_ED_GET_MAXP(O32TOH(sed->ed.ed_flags)), 2623 UGETW(opipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 2624 2625 next = stat; 2626 2627 /* Set up data transaction */ 2628 if (len != 0) { 2629 ohci_soft_td_t *std = stat; 2630 2631 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2632 std, &stat); 2633 if (err) { 2634 /* stat is unchanged if error */ 2635 goto bad3; 2636 } 2637 stat = stat->nexttd; /* point at free TD */ 2638 2639 /* Start toggle at 1 and then use the carried toggle. */ 2640 std->td.td_flags &= HTOO32(~OHCI_TD_TOGGLE_MASK); 2641 std->td.td_flags |= HTOO32(OHCI_TD_TOGGLE_1); 2642 usb_syncmem(&std->dma, 2643 std->offs + offsetof(ohci_td_t, td_flags), 2644 sizeof(std->td.td_flags), 2645 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2646 } 2647 2648 memcpy(KERNADDR(&opipe->ctrl.reqdma, 0), req, sizeof(*req)); 2649 usb_syncmem(&opipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 2650 2651 setup->td.td_flags = HTOO32(OHCI_TD_SETUP | OHCI_TD_NOCC | 2652 OHCI_TD_TOGGLE_0 | OHCI_TD_NOINTR); 2653 setup->td.td_cbp = HTOO32(DMAADDR(&opipe->ctrl.reqdma, 0)); 2654 setup->nexttd = next; 2655 setup->td.td_nexttd = HTOO32(next->physaddr); 2656 setup->td.td_be = HTOO32(O32TOH(setup->td.td_cbp) + sizeof(*req) - 1); 2657 setup->len = 0; 2658 setup->xfer = xfer; 2659 setup->flags = 0; 2660 xfer->ux_hcpriv = setup; 2661 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->td), 2662 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2663 2664 stat->td.td_flags = HTOO32( 2665 (isread ? OHCI_TD_OUT : OHCI_TD_IN) | 2666 OHCI_TD_NOCC | OHCI_TD_TOGGLE_1 | OHCI_TD_SET_DI(1)); 2667 stat->td.td_cbp = 0; 2668 stat->nexttd = tail; 2669 stat->td.td_nexttd = HTOO32(tail->physaddr); 2670 stat->td.td_be = 0; 2671 stat->flags = OHCI_CALL_DONE; 2672 stat->len = 0; 2673 stat->xfer = xfer; 2674 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->td), 2675 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2676 2677 #ifdef OHCI_DEBUG 2678 USBHIST_LOGN(ohcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2679 if (ohcidebug > 5) { 2680 ohci_dump_ed(sc, sed); 2681 ohci_dump_tds(sc, setup); 2682 } 2683 USBHIST_LOGN(ohcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2684 #endif 2685 2686 /* Insert ED in schedule */ 2687 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2688 usb_syncmem(&sed->dma, 2689 sed->offs + offsetof(ohci_ed_t, ed_tailp), 2690 sizeof(sed->ed.ed_tailp), 2691 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2692 opipe->tail.td = tail; 2693 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_CLF); 2694 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2695 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2696 ohci_timeout, xfer); 2697 } 2698 2699 #ifdef OHCI_DEBUG 2700 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2701 if (ohcidebug > 20) { 2702 delay(10000); 2703 DPRINTFN(20, "status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2704 0, 0, 0); 2705 ohci_dumpregs(sc); 2706 DPRINTFN(20, "ctrl head:", 0, 0, 0, 0); 2707 ohci_dump_ed(sc, sc->sc_ctrl_head); 2708 DPRINTF("sed:", 0, 0, 0, 0); 2709 ohci_dump_ed(sc, sed); 2710 ohci_dump_tds(sc, setup); 2711 } 2712 DPRINTFN(20, "--- dump start ---", 0, 0, 0, 0); 2713 #endif 2714 2715 mutex_exit(&sc->sc_lock); 2716 2717 if (sc->sc_bus.ub_usepolling) 2718 ohci_waitintr(sc, xfer); 2719 2720 return USBD_IN_PROGRESS; 2721 2722 bad3: 2723 ohci_free_std(sc, tail); 2724 bad2: 2725 ohci_free_std(sc, stat); 2726 bad1: 2727 mutex_exit(&sc->sc_lock); 2728 2729 return err; 2730 } 2731 2732 /* Abort a device control request. */ 2733 Static void 2734 ohci_device_ctrl_abort(struct usbd_xfer *xfer) 2735 { 2736 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2737 2738 KASSERT(mutex_owned(&sc->sc_lock)); 2739 2740 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2741 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2742 ohci_abort_xfer(xfer, USBD_CANCELLED); 2743 } 2744 2745 /* Close a device control pipe. */ 2746 Static void 2747 ohci_device_ctrl_close(struct usbd_pipe *pipe) 2748 { 2749 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2750 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2751 2752 KASSERT(mutex_owned(&sc->sc_lock)); 2753 2754 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2755 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2756 ohci_close_pipe(pipe, sc->sc_ctrl_head); 2757 ohci_free_std(sc, opipe->tail.td); 2758 } 2759 2760 /************************/ 2761 2762 Static void 2763 ohci_device_clear_toggle(struct usbd_pipe *pipe) 2764 { 2765 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2766 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2767 2768 opipe->sed->ed.ed_headp &= HTOO32(~OHCI_TOGGLECARRY); 2769 } 2770 2771 Static void 2772 ohci_noop(struct usbd_pipe *pipe) 2773 { 2774 } 2775 2776 Static usbd_status 2777 ohci_device_bulk_transfer(struct usbd_xfer *xfer) 2778 { 2779 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2780 usbd_status err; 2781 2782 /* Insert last in queue. */ 2783 mutex_enter(&sc->sc_lock); 2784 err = usb_insert_transfer(xfer); 2785 mutex_exit(&sc->sc_lock); 2786 if (err) 2787 return err; 2788 2789 /* Pipe isn't running, start first */ 2790 return ohci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2791 } 2792 2793 Static usbd_status 2794 ohci_device_bulk_start(struct usbd_xfer *xfer) 2795 { 2796 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2797 struct usbd_device *dev = opipe->pipe.up_dev; 2798 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2799 int addr = dev->ud_addr; 2800 ohci_soft_td_t *data, *tail, *tdp; 2801 ohci_soft_ed_t *sed; 2802 int len, isread, endpt; 2803 usbd_status err; 2804 2805 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2806 2807 if (sc->sc_dying) 2808 return USBD_IOERROR; 2809 2810 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2811 2812 mutex_enter(&sc->sc_lock); 2813 2814 len = xfer->ux_length; 2815 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2816 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2817 sed = opipe->sed; 2818 2819 DPRINTFN(4, "xfer=%p len=%d isread=%d flags=%d", xfer, len, isread, 2820 xfer->ux_flags); 2821 DPRINTFN(4, "endpt=%d", endpt, 0, 0, 0); 2822 2823 opipe->bulk.isread = isread; 2824 opipe->bulk.length = len; 2825 2826 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2827 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2828 /* Update device address */ 2829 sed->ed.ed_flags = HTOO32( 2830 (O32TOH(sed->ed.ed_flags) & ~OHCI_ED_ADDRMASK) | 2831 OHCI_ED_SET_FA(addr)); 2832 2833 /* Allocate a chain of new TDs (including a new tail). */ 2834 data = opipe->tail.td; 2835 err = ohci_alloc_std_chain(opipe, sc, len, isread, xfer, 2836 data, &tail); 2837 if (err) 2838 return err; 2839 2840 /* We want interrupt at the end of the transfer. */ 2841 tail->td.td_flags &= HTOO32(~OHCI_TD_INTR_MASK); 2842 tail->td.td_flags |= HTOO32(OHCI_TD_SET_DI(1)); 2843 tail->flags |= OHCI_CALL_DONE; 2844 tail = tail->nexttd; /* point at sentinel */ 2845 usb_syncmem(&tail->dma, tail->offs + offsetof(ohci_td_t, td_flags), 2846 sizeof(tail->td.td_flags), 2847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2848 if (err) { 2849 mutex_exit(&sc->sc_lock); 2850 return err; 2851 } 2852 2853 tail->xfer = NULL; 2854 xfer->ux_hcpriv = data; 2855 2856 DPRINTFN(4, "ed_flags=0x%08x td_flags=0x%08x " 2857 "td_cbp=0x%08x td_be=0x%08x", 2858 (int)O32TOH(sed->ed.ed_flags), 2859 (int)O32TOH(data->td.td_flags), 2860 (int)O32TOH(data->td.td_cbp), 2861 (int)O32TOH(data->td.td_be)); 2862 2863 #ifdef OHCI_DEBUG 2864 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2865 if (ohcidebug > 5) { 2866 ohci_dump_ed(sc, sed); 2867 ohci_dump_tds(sc, data); 2868 } 2869 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2870 #endif 2871 2872 /* Insert ED in schedule */ 2873 for (tdp = data; tdp != tail; tdp = tdp->nexttd) { 2874 tdp->xfer = xfer; 2875 } 2876 sed->ed.ed_tailp = HTOO32(tail->physaddr); 2877 opipe->tail.td = tail; 2878 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 2879 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 2880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2881 OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_BLF); 2882 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 2883 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 2884 ohci_timeout, xfer); 2885 } 2886 mutex_exit(&sc->sc_lock); 2887 2888 #if 0 2889 /* This goes wrong if we are too slow. */ 2890 if (ohcidebug > 10) { 2891 delay(10000); 2892 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 2893 0, 0, 0); 2894 ohci_dump_ed(sc, sed); 2895 ohci_dump_tds(sc, data); 2896 } 2897 #endif 2898 2899 return USBD_IN_PROGRESS; 2900 } 2901 2902 Static void 2903 ohci_device_bulk_abort(struct usbd_xfer *xfer) 2904 { 2905 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 2906 2907 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2908 2909 KASSERT(mutex_owned(&sc->sc_lock)); 2910 2911 DPRINTF("xfer=%p", xfer, 0, 0, 0); 2912 ohci_abort_xfer(xfer, USBD_CANCELLED); 2913 } 2914 2915 /* 2916 * Close a device bulk pipe. 2917 */ 2918 Static void 2919 ohci_device_bulk_close(struct usbd_pipe *pipe) 2920 { 2921 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 2922 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 2923 2924 KASSERT(mutex_owned(&sc->sc_lock)); 2925 2926 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2927 2928 DPRINTF("pipe=%p", pipe, 0, 0, 0); 2929 ohci_close_pipe(pipe, sc->sc_bulk_head); 2930 ohci_free_std(sc, opipe->tail.td); 2931 } 2932 2933 /************************/ 2934 2935 Static usbd_status 2936 ohci_device_intr_transfer(struct usbd_xfer *xfer) 2937 { 2938 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2939 usbd_status err; 2940 2941 /* Insert last in queue. */ 2942 mutex_enter(&sc->sc_lock); 2943 err = usb_insert_transfer(xfer); 2944 mutex_exit(&sc->sc_lock); 2945 if (err) 2946 return err; 2947 2948 /* Pipe isn't running, start first */ 2949 return ohci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2950 } 2951 2952 Static usbd_status 2953 ohci_device_intr_start(struct usbd_xfer *xfer) 2954 { 2955 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 2956 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 2957 ohci_soft_ed_t *sed = opipe->sed; 2958 ohci_soft_td_t *data, *tail; 2959 int len, isread, endpt; 2960 2961 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 2962 2963 if (sc->sc_dying) 2964 return USBD_IOERROR; 2965 2966 DPRINTFN(3, "xfer=%p len=%d flags=%d priv=%p", xfer, xfer->ux_length, 2967 xfer->ux_flags, xfer->ux_priv); 2968 2969 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 2970 2971 len = xfer->ux_length; 2972 endpt = xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress; 2973 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2974 2975 data = opipe->tail.td; 2976 mutex_enter(&sc->sc_lock); 2977 tail = ohci_alloc_std(sc); 2978 mutex_exit(&sc->sc_lock); 2979 if (tail == NULL) 2980 return USBD_NOMEM; 2981 tail->xfer = NULL; 2982 2983 data->td.td_flags = HTOO32( 2984 isread ? OHCI_TD_IN : OHCI_TD_OUT | 2985 OHCI_TD_NOCC | 2986 OHCI_TD_SET_DI(1) | OHCI_TD_TOGGLE_CARRY); 2987 if (xfer->ux_flags & USBD_SHORT_XFER_OK) 2988 data->td.td_flags |= HTOO32(OHCI_TD_R); 2989 data->td.td_cbp = HTOO32(DMAADDR(&xfer->ux_dmabuf, 0)); 2990 data->nexttd = tail; 2991 data->td.td_nexttd = HTOO32(tail->physaddr); 2992 data->td.td_be = HTOO32(O32TOH(data->td.td_cbp) + len - 1); 2993 data->len = len; 2994 data->xfer = xfer; 2995 data->flags = OHCI_CALL_DONE | OHCI_ADD_LEN; 2996 usb_syncmem(&data->dma, data->offs, sizeof(data->td), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 xfer->ux_hcpriv = data; 2999 3000 #ifdef OHCI_DEBUG 3001 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3002 if (ohcidebug > 5) { 3003 ohci_dump_ed(sc, sed); 3004 ohci_dump_tds(sc, data); 3005 } 3006 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3007 #endif 3008 3009 /* Insert ED in schedule */ 3010 mutex_enter(&sc->sc_lock); 3011 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3012 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3013 sed->ed.ed_tailp = HTOO32(tail->physaddr); 3014 opipe->tail.td = tail; 3015 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3016 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3017 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3018 3019 #if 0 3020 /* 3021 * This goes horribly wrong, printing thousands of descriptors, 3022 * because false references are followed due to the fact that the 3023 * TD is gone. 3024 */ 3025 if (ohcidebug > 5) { 3026 usb_delay_ms_locked(&sc->sc_bus, 5, &sc->sc_lock); 3027 DPRINTF("status=%x", OREAD4(sc, OHCI_COMMAND_STATUS), 3028 0, 0, 0); 3029 ohci_dump_ed(sc, sed); 3030 ohci_dump_tds(sc, data); 3031 } 3032 #endif 3033 mutex_exit(&sc->sc_lock); 3034 3035 return USBD_IN_PROGRESS; 3036 } 3037 3038 /* Abort a device interrupt request. */ 3039 Static void 3040 ohci_device_intr_abort(struct usbd_xfer *xfer) 3041 { 3042 ohci_softc_t *sc __diagused = OHCI_XFER2SC(xfer); 3043 3044 KASSERT(mutex_owned(&sc->sc_lock)); 3045 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3046 3047 ohci_abort_xfer(xfer, USBD_CANCELLED); 3048 } 3049 3050 /* Close a device interrupt pipe. */ 3051 Static void 3052 ohci_device_intr_close(struct usbd_pipe *pipe) 3053 { 3054 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3055 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3056 int nslots = opipe->intr.nslots; 3057 int pos = opipe->intr.pos; 3058 int j; 3059 ohci_soft_ed_t *p, *sed = opipe->sed; 3060 3061 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3062 3063 KASSERT(mutex_owned(&sc->sc_lock)); 3064 3065 DPRINTFN(1, "pipe=%p nslots=%d pos=%d", pipe, nslots, pos, 0); 3066 usb_syncmem(&sed->dma, sed->offs, 3067 sizeof(sed->ed), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3068 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); 3069 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3070 sizeof(sed->ed.ed_flags), 3071 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3072 if ((O32TOH(sed->ed.ed_tailp) & OHCI_HEADMASK) != 3073 (O32TOH(sed->ed.ed_headp) & OHCI_HEADMASK)) 3074 usb_delay_ms_locked(&sc->sc_bus, 2, &sc->sc_lock); 3075 3076 for (p = sc->sc_eds[pos]; p && p->next != sed; p = p->next) 3077 continue; 3078 KASSERT(p); 3079 p->next = sed->next; 3080 p->ed.ed_nexted = sed->ed.ed_nexted; 3081 usb_syncmem(&p->dma, p->offs + offsetof(ohci_ed_t, ed_nexted), 3082 sizeof(p->ed.ed_nexted), 3083 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3084 3085 for (j = 0; j < nslots; j++) 3086 --sc->sc_bws[(pos * nslots + j) % OHCI_NO_INTRS]; 3087 3088 ohci_free_std(sc, opipe->tail.td); 3089 ohci_free_sed(sc, opipe->sed); 3090 } 3091 3092 Static usbd_status 3093 ohci_device_setintr(ohci_softc_t *sc, struct ohci_pipe *opipe, int ival) 3094 { 3095 int i, j, best; 3096 u_int npoll, slow, shigh, nslots; 3097 u_int bestbw, bw; 3098 ohci_soft_ed_t *hsed, *sed = opipe->sed; 3099 3100 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3101 3102 DPRINTFN(2, "pipe=%p", opipe, 0, 0, 0); 3103 if (ival == 0) { 3104 printf("ohci_setintr: 0 interval\n"); 3105 return USBD_INVAL; 3106 } 3107 3108 npoll = OHCI_NO_INTRS; 3109 while (npoll > ival) 3110 npoll /= 2; 3111 DPRINTFN(2, "ival=%d npoll=%d", ival, npoll, 0, 0); 3112 3113 /* 3114 * We now know which level in the tree the ED must go into. 3115 * Figure out which slot has most bandwidth left over. 3116 * Slots to examine: 3117 * npoll 3118 * 1 0 3119 * 2 1 2 3120 * 4 3 4 5 6 3121 * 8 7 8 9 10 11 12 13 14 3122 * N (N-1) .. (N-1+N-1) 3123 */ 3124 slow = npoll-1; 3125 shigh = slow + npoll; 3126 nslots = OHCI_NO_INTRS / npoll; 3127 for (best = i = slow, bestbw = ~0; i < shigh; i++) { 3128 bw = 0; 3129 for (j = 0; j < nslots; j++) 3130 bw += sc->sc_bws[(i * nslots + j) % OHCI_NO_INTRS]; 3131 if (bw < bestbw) { 3132 best = i; 3133 bestbw = bw; 3134 } 3135 } 3136 DPRINTFN(2, "best=%d(%d..%d) bestbw=%d", best, slow, shigh, bestbw); 3137 3138 mutex_enter(&sc->sc_lock); 3139 hsed = sc->sc_eds[best]; 3140 sed->next = hsed->next; 3141 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3142 sizeof(hsed->ed.ed_flags), 3143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3144 sed->ed.ed_nexted = hsed->ed.ed_nexted; 3145 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3146 sizeof(sed->ed.ed_flags), 3147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3148 hsed->next = sed; 3149 hsed->ed.ed_nexted = HTOO32(sed->physaddr); 3150 usb_syncmem(&hsed->dma, hsed->offs + offsetof(ohci_ed_t, ed_flags), 3151 sizeof(hsed->ed.ed_flags), 3152 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3153 mutex_exit(&sc->sc_lock); 3154 3155 for (j = 0; j < nslots; j++) 3156 ++sc->sc_bws[(best * nslots + j) % OHCI_NO_INTRS]; 3157 opipe->intr.nslots = nslots; 3158 opipe->intr.pos = best; 3159 3160 DPRINTFN(5, "returns %p", opipe, 0, 0, 0); 3161 return USBD_NORMAL_COMPLETION; 3162 } 3163 3164 /***********************/ 3165 3166 usbd_status 3167 ohci_device_isoc_transfer(struct usbd_xfer *xfer) 3168 { 3169 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3170 usbd_status err; 3171 3172 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3173 3174 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3175 3176 /* Put it on our queue, */ 3177 mutex_enter(&sc->sc_lock); 3178 err = usb_insert_transfer(xfer); 3179 mutex_exit(&sc->sc_lock); 3180 3181 /* bail out on error, */ 3182 if (err && err != USBD_IN_PROGRESS) 3183 return err; 3184 3185 /* XXX should check inuse here */ 3186 3187 /* insert into schedule, */ 3188 ohci_device_isoc_enter(xfer); 3189 3190 /* and start if the pipe wasn't running */ 3191 if (!err) 3192 ohci_device_isoc_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3193 3194 return err; 3195 } 3196 3197 void 3198 ohci_device_isoc_enter(struct usbd_xfer *xfer) 3199 { 3200 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3201 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3202 ohci_soft_ed_t *sed = opipe->sed; 3203 struct isoc *isoc = &opipe->isoc; 3204 ohci_soft_itd_t *sitd, *nsitd; 3205 ohci_physaddr_t buf, offs, noffs, bp0; 3206 int i, ncur, nframes; 3207 3208 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3209 3210 DPRINTFN(1, "used=%d next=%d xfer=%p nframes=%d", 3211 isoc->inuse, isoc->next, xfer, xfer->ux_nframes); 3212 3213 if (sc->sc_dying) 3214 return; 3215 3216 if (isoc->next == -1) { 3217 /* Not in use yet, schedule it a few frames ahead. */ 3218 isoc->next = O32TOH(sc->sc_hcca->hcca_frame_number) + 5; 3219 DPRINTFN(2,"start next=%d", isoc->next, 0, 0, 0); 3220 } 3221 3222 sitd = opipe->tail.itd; 3223 buf = DMAADDR(&xfer->ux_dmabuf, 0); 3224 bp0 = OHCI_PAGE(buf); 3225 offs = OHCI_PAGE_OFFSET(buf); 3226 nframes = xfer->ux_nframes; 3227 xfer->ux_hcpriv = sitd; 3228 for (i = ncur = 0; i < nframes; i++, ncur++) { 3229 noffs = offs + xfer->ux_frlengths[i]; 3230 if (ncur == OHCI_ITD_NOFFSET || /* all offsets used */ 3231 OHCI_PAGE(buf + noffs) > bp0 + OHCI_PAGE_SIZE) { /* too many page crossings */ 3232 3233 /* Allocate next ITD */ 3234 mutex_enter(&sc->sc_lock); 3235 nsitd = ohci_alloc_sitd(sc); 3236 mutex_exit(&sc->sc_lock); 3237 if (nsitd == NULL) { 3238 /* XXX what now? */ 3239 printf("%s: isoc TD alloc failed\n", 3240 device_xname(sc->sc_dev)); 3241 return; 3242 } 3243 3244 /* Fill current ITD */ 3245 sitd->itd.itd_flags = HTOO32( 3246 OHCI_ITD_NOCC | 3247 OHCI_ITD_SET_SF(isoc->next) | 3248 OHCI_ITD_SET_DI(6) | /* delay intr a little */ 3249 OHCI_ITD_SET_FC(ncur)); 3250 sitd->itd.itd_bp0 = HTOO32(bp0); 3251 sitd->nextitd = nsitd; 3252 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3253 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3254 sitd->xfer = xfer; 3255 sitd->flags = 0; 3256 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3257 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3258 3259 sitd = nsitd; 3260 isoc->next = isoc->next + ncur; 3261 bp0 = OHCI_PAGE(buf + offs); 3262 ncur = 0; 3263 } 3264 sitd->itd.itd_offset[ncur] = HTOO16(OHCI_ITD_MK_OFFS(offs)); 3265 offs = noffs; 3266 } 3267 mutex_enter(&sc->sc_lock); 3268 nsitd = ohci_alloc_sitd(sc); 3269 mutex_exit(&sc->sc_lock); 3270 if (nsitd == NULL) { 3271 /* XXX what now? */ 3272 printf("%s: isoc TD alloc failed\n", 3273 device_xname(sc->sc_dev)); 3274 return; 3275 } 3276 /* Fixup last used ITD */ 3277 sitd->itd.itd_flags = HTOO32( 3278 OHCI_ITD_NOCC | 3279 OHCI_ITD_SET_SF(isoc->next) | 3280 OHCI_ITD_SET_DI(0) | 3281 OHCI_ITD_SET_FC(ncur)); 3282 sitd->itd.itd_bp0 = HTOO32(bp0); 3283 sitd->nextitd = nsitd; 3284 sitd->itd.itd_nextitd = HTOO32(nsitd->physaddr); 3285 sitd->itd.itd_be = HTOO32(bp0 + offs - 1); 3286 sitd->xfer = xfer; 3287 sitd->flags = OHCI_CALL_DONE; 3288 usb_syncmem(&sitd->dma, sitd->offs, sizeof(sitd->itd), 3289 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3290 3291 isoc->next = isoc->next + ncur; 3292 isoc->inuse += nframes; 3293 3294 xfer->ux_actlen = offs; /* XXX pretend we did it all */ 3295 3296 xfer->ux_status = USBD_IN_PROGRESS; 3297 3298 #ifdef OHCI_DEBUG 3299 if (ohcidebug > 5) { 3300 DPRINTF("frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3301 0, 0, 0); 3302 ohci_dump_itds(sc, xfer->ux_hcpriv); 3303 ohci_dump_ed(sc, sed); 3304 } 3305 #endif 3306 3307 mutex_enter(&sc->sc_lock); 3308 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3309 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3310 sed->ed.ed_tailp = HTOO32(nsitd->physaddr); 3311 opipe->tail.itd = nsitd; 3312 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); 3313 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3314 sizeof(sed->ed.ed_flags), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 mutex_exit(&sc->sc_lock); 3317 3318 #ifdef OHCI_DEBUG 3319 if (ohcidebug > 5) { 3320 delay(150000); 3321 DPRINTF("after frame=%d", O32TOH(sc->sc_hcca->hcca_frame_number), 3322 0, 0, 0); 3323 ohci_dump_itds(sc, xfer->ux_hcpriv); 3324 ohci_dump_ed(sc, sed); 3325 } 3326 #endif 3327 } 3328 3329 usbd_status 3330 ohci_device_isoc_start(struct usbd_xfer *xfer) 3331 { 3332 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3333 3334 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3335 DPRINTFN(5, "xfer=%p", xfer, 0, 0, 0); 3336 3337 mutex_enter(&sc->sc_lock); 3338 3339 if (sc->sc_dying) { 3340 mutex_exit(&sc->sc_lock); 3341 return USBD_IOERROR; 3342 } 3343 3344 3345 #ifdef DIAGNOSTIC 3346 if (xfer->ux_status != USBD_IN_PROGRESS) 3347 printf("ohci_device_isoc_start: not in progress %p\n", xfer); 3348 #endif 3349 3350 /* XXX anything to do? */ 3351 3352 mutex_exit(&sc->sc_lock); 3353 3354 return USBD_IN_PROGRESS; 3355 } 3356 3357 void 3358 ohci_device_isoc_abort(struct usbd_xfer *xfer) 3359 { 3360 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(xfer->ux_pipe); 3361 ohci_softc_t *sc = OHCI_XFER2SC(xfer); 3362 ohci_soft_ed_t *sed; 3363 ohci_soft_itd_t *sitd; 3364 3365 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3366 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3367 3368 KASSERT(mutex_owned(&sc->sc_lock)); 3369 3370 /* Transfer is already done. */ 3371 if (xfer->ux_status != USBD_NOT_STARTED && 3372 xfer->ux_status != USBD_IN_PROGRESS) { 3373 printf("ohci_device_isoc_abort: early return\n"); 3374 goto done; 3375 } 3376 3377 /* Give xfer the requested abort code. */ 3378 xfer->ux_status = USBD_CANCELLED; 3379 3380 sed = opipe->sed; 3381 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3382 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3383 sed->ed.ed_flags |= HTOO32(OHCI_ED_SKIP); /* force hardware skip */ 3384 usb_syncmem(&sed->dma, sed->offs + offsetof(ohci_ed_t, ed_flags), 3385 sizeof(sed->ed.ed_flags), 3386 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3387 3388 sitd = xfer->ux_hcpriv; 3389 KASSERT(sitd); 3390 3391 for (; sitd->xfer == xfer; sitd = sitd->nextitd) { 3392 #ifdef DIAGNOSTIC 3393 DPRINTFN(1, "abort sets done sitd=%p", sitd, 0, 0, 0); 3394 sitd->isdone = 1; 3395 #endif 3396 } 3397 3398 usb_delay_ms_locked(&sc->sc_bus, OHCI_ITD_NOFFSET, &sc->sc_lock); 3399 3400 /* Run callback. */ 3401 usb_transfer_complete(xfer); 3402 3403 sed->ed.ed_headp = HTOO32(sitd->physaddr); /* unlink TDs */ 3404 sed->ed.ed_flags &= HTOO32(~OHCI_ED_SKIP); /* remove hardware skip */ 3405 usb_syncmem(&sed->dma, sed->offs, sizeof(sed->ed), 3406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3407 3408 done: 3409 KASSERT(mutex_owned(&sc->sc_lock)); 3410 } 3411 3412 void 3413 ohci_device_isoc_done(struct usbd_xfer *xfer) 3414 { 3415 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3416 DPRINTFN(1, "xfer=%p", xfer, 0, 0, 0); 3417 } 3418 3419 usbd_status 3420 ohci_setup_isoc(struct usbd_pipe *pipe) 3421 { 3422 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3423 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3424 struct isoc *isoc = &opipe->isoc; 3425 3426 isoc->next = -1; 3427 isoc->inuse = 0; 3428 3429 mutex_enter(&sc->sc_lock); 3430 ohci_add_ed(sc, opipe->sed, sc->sc_isoc_head); 3431 mutex_exit(&sc->sc_lock); 3432 3433 return USBD_NORMAL_COMPLETION; 3434 } 3435 3436 void 3437 ohci_device_isoc_close(struct usbd_pipe *pipe) 3438 { 3439 struct ohci_pipe *opipe = OHCI_PIPE2OPIPE(pipe); 3440 ohci_softc_t *sc = OHCI_PIPE2SC(pipe); 3441 3442 KASSERT(mutex_owned(&sc->sc_lock)); 3443 3444 OHCIHIST_FUNC(); OHCIHIST_CALLED(); 3445 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3446 ohci_close_pipe(pipe, sc->sc_isoc_head); 3447 #ifdef DIAGNOSTIC 3448 opipe->tail.itd->isdone = 1; 3449 #endif 3450 ohci_free_sitd(sc, opipe->tail.itd); 3451 } 3452
Indexes created Fri Oct 03 02:09:57 GMT 2025